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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
92.98 99.25 93.67 100.00 98.40 99.51 67.06


Total test records in report: 423
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T33 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.1585200851 Mar 05 12:38:52 PM PST 24 Mar 05 12:38:55 PM PST 24 1195518941 ps
T31 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.1204013584 Mar 05 12:39:11 PM PST 24 Mar 05 12:39:15 PM PST 24 4794228653 ps
T284 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.4159588984 Mar 05 12:39:15 PM PST 24 Mar 05 12:39:17 PM PST 24 518176081 ps
T285 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.2216947280 Mar 05 12:39:17 PM PST 24 Mar 05 12:39:19 PM PST 24 520568909 ps
T32 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.1321940070 Mar 05 12:39:08 PM PST 24 Mar 05 12:39:14 PM PST 24 2336254887 ps
T99 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.136189569 Mar 05 12:39:21 PM PST 24 Mar 05 12:39:23 PM PST 24 483221060 ps
T68 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.2949703685 Mar 05 12:39:17 PM PST 24 Mar 05 12:39:21 PM PST 24 1378111526 ps
T286 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.3476419908 Mar 05 12:39:13 PM PST 24 Mar 05 12:39:14 PM PST 24 286481620 ps
T287 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.3946162407 Mar 05 12:38:47 PM PST 24 Mar 05 12:38:48 PM PST 24 862916119 ps
T34 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.1888493219 Mar 05 12:38:49 PM PST 24 Mar 05 12:38:55 PM PST 24 4025132215 ps
T288 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.1300725811 Mar 05 12:39:22 PM PST 24 Mar 05 12:39:23 PM PST 24 302365191 ps
T289 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.1026647154 Mar 05 12:38:48 PM PST 24 Mar 05 12:38:49 PM PST 24 458175444 ps
T95 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.2099918240 Mar 05 12:39:06 PM PST 24 Mar 05 12:39:16 PM PST 24 8547092438 ps
T290 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.397209005 Mar 05 12:39:28 PM PST 24 Mar 05 12:39:28 PM PST 24 420094243 ps
T291 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.2212199797 Mar 05 12:38:45 PM PST 24 Mar 05 12:38:46 PM PST 24 397230743 ps
T292 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.4000549012 Mar 05 12:39:00 PM PST 24 Mar 05 12:39:02 PM PST 24 315890768 ps
T69 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.4071026392 Mar 05 12:38:51 PM PST 24 Mar 05 12:38:55 PM PST 24 2158274813 ps
T293 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.1655490991 Mar 05 12:38:58 PM PST 24 Mar 05 12:39:11 PM PST 24 13918928956 ps
T96 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.2355472163 Mar 05 12:39:09 PM PST 24 Mar 05 12:39:17 PM PST 24 4435305013 ps
T294 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.2344328768 Mar 05 12:39:00 PM PST 24 Mar 05 12:39:03 PM PST 24 545896290 ps
T295 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.3209743934 Mar 05 12:39:13 PM PST 24 Mar 05 12:39:14 PM PST 24 462373038 ps
T92 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.849396718 Mar 05 12:39:12 PM PST 24 Mar 05 12:39:14 PM PST 24 3910390395 ps
T70 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.3781932581 Mar 05 12:39:10 PM PST 24 Mar 05 12:39:11 PM PST 24 407414671 ps
T71 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.4182823217 Mar 05 12:39:15 PM PST 24 Mar 05 12:39:23 PM PST 24 2881508398 ps
T296 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.3092130537 Mar 05 12:38:49 PM PST 24 Mar 05 12:38:50 PM PST 24 499596896 ps
T297 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.2952447360 Mar 05 12:39:11 PM PST 24 Mar 05 12:39:11 PM PST 24 555433654 ps
T298 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.2445903798 Mar 05 12:39:08 PM PST 24 Mar 05 12:39:09 PM PST 24 491848936 ps
T299 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.3604102904 Mar 05 12:39:07 PM PST 24 Mar 05 12:39:08 PM PST 24 469335098 ps
T97 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.1740474146 Mar 05 12:39:00 PM PST 24 Mar 05 12:39:05 PM PST 24 8171820994 ps
T72 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.730010320 Mar 05 12:38:59 PM PST 24 Mar 05 12:39:00 PM PST 24 443660323 ps
T300 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.3504486719 Mar 05 12:38:52 PM PST 24 Mar 05 12:38:59 PM PST 24 1175215054 ps
T301 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.158731329 Mar 05 12:38:59 PM PST 24 Mar 05 12:39:01 PM PST 24 446976463 ps
T98 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.632426424 Mar 05 12:39:14 PM PST 24 Mar 05 12:39:18 PM PST 24 4653926968 ps
T73 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.3368122326 Mar 05 12:38:58 PM PST 24 Mar 05 12:39:00 PM PST 24 1463471737 ps
T302 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.722855719 Mar 05 12:39:06 PM PST 24 Mar 05 12:39:08 PM PST 24 578027632 ps
T74 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.2088130722 Mar 05 12:38:59 PM PST 24 Mar 05 12:39:01 PM PST 24 2629519431 ps
T303 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.2894467687 Mar 05 12:39:13 PM PST 24 Mar 05 12:39:14 PM PST 24 462173962 ps
T304 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.3400985195 Mar 05 12:39:23 PM PST 24 Mar 05 12:39:24 PM PST 24 351180134 ps
T305 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.2840741738 Mar 05 12:38:52 PM PST 24 Mar 05 12:38:54 PM PST 24 306930496 ps
T306 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.1112968330 Mar 05 12:39:06 PM PST 24 Mar 05 12:39:08 PM PST 24 384705754 ps
T307 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.2681676315 Mar 05 12:39:23 PM PST 24 Mar 05 12:39:25 PM PST 24 409690347 ps
T308 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.1283083531 Mar 05 12:39:15 PM PST 24 Mar 05 12:39:17 PM PST 24 605584101 ps
T309 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.2163877305 Mar 05 12:39:07 PM PST 24 Mar 05 12:39:11 PM PST 24 4145923276 ps
T310 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.4284169696 Mar 05 12:39:26 PM PST 24 Mar 05 12:39:27 PM PST 24 338491096 ps
T75 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.3182427247 Mar 05 12:39:01 PM PST 24 Mar 05 12:39:05 PM PST 24 2855367306 ps
T311 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.1490145822 Mar 05 12:39:09 PM PST 24 Mar 05 12:39:10 PM PST 24 453331266 ps
T312 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.450576955 Mar 05 12:39:31 PM PST 24 Mar 05 12:39:31 PM PST 24 335775410 ps
T313 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.3574815601 Mar 05 12:39:20 PM PST 24 Mar 05 12:39:23 PM PST 24 467633117 ps
T314 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.2270367950 Mar 05 12:38:59 PM PST 24 Mar 05 12:38:59 PM PST 24 566416714 ps
T315 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.164330474 Mar 05 12:39:20 PM PST 24 Mar 05 12:39:21 PM PST 24 307495297 ps
T93 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.2141011848 Mar 05 12:38:51 PM PST 24 Mar 05 12:38:57 PM PST 24 3635959469 ps
T94 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.3372796047 Mar 05 12:38:57 PM PST 24 Mar 05 12:39:02 PM PST 24 9155510460 ps
T316 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.708236751 Mar 05 12:39:14 PM PST 24 Mar 05 12:39:14 PM PST 24 490784368 ps
T47 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.291821770 Mar 05 12:39:11 PM PST 24 Mar 05 12:39:12 PM PST 24 481535259 ps
T317 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.2707542131 Mar 05 12:38:56 PM PST 24 Mar 05 12:38:57 PM PST 24 516945776 ps
T76 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.3289616314 Mar 05 12:38:56 PM PST 24 Mar 05 12:38:56 PM PST 24 683699178 ps
T318 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.186356416 Mar 05 12:39:40 PM PST 24 Mar 05 12:39:41 PM PST 24 425461408 ps
T319 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.3765315608 Mar 05 12:39:10 PM PST 24 Mar 05 12:39:11 PM PST 24 384911087 ps
T320 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.2092547794 Mar 05 12:39:12 PM PST 24 Mar 05 12:39:13 PM PST 24 376072744 ps
T321 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.3192296581 Mar 05 12:38:54 PM PST 24 Mar 05 12:38:55 PM PST 24 285420197 ps
T322 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.1368745083 Mar 05 12:38:43 PM PST 24 Mar 05 12:38:47 PM PST 24 4511707992 ps
T323 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.616251733 Mar 05 12:39:05 PM PST 24 Mar 05 12:39:09 PM PST 24 330219349 ps
T324 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.2908731543 Mar 05 12:39:06 PM PST 24 Mar 05 12:39:08 PM PST 24 1869409895 ps
T325 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.760305322 Mar 05 12:39:11 PM PST 24 Mar 05 12:39:12 PM PST 24 536409032 ps
T326 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.1344720286 Mar 05 12:39:03 PM PST 24 Mar 05 12:39:04 PM PST 24 381191316 ps
T327 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.235003713 Mar 05 12:39:15 PM PST 24 Mar 05 12:39:16 PM PST 24 1568129180 ps
T48 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.2223928344 Mar 05 12:39:13 PM PST 24 Mar 05 12:39:14 PM PST 24 468834875 ps
T328 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.2150352956 Mar 05 12:39:14 PM PST 24 Mar 05 12:39:16 PM PST 24 1198745609 ps
T329 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.619821757 Mar 05 12:39:27 PM PST 24 Mar 05 12:39:28 PM PST 24 429948271 ps
T330 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.1760415926 Mar 05 12:39:14 PM PST 24 Mar 05 12:39:15 PM PST 24 521776391 ps
T331 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.4081288575 Mar 05 12:39:12 PM PST 24 Mar 05 12:39:13 PM PST 24 442996418 ps
T332 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.58303932 Mar 05 12:39:36 PM PST 24 Mar 05 12:39:38 PM PST 24 494758855 ps
T333 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.3239448531 Mar 05 12:38:59 PM PST 24 Mar 05 12:39:01 PM PST 24 888847812 ps
T334 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.4120159554 Mar 05 12:39:11 PM PST 24 Mar 05 12:39:12 PM PST 24 323130671 ps
T335 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.849347008 Mar 05 12:38:59 PM PST 24 Mar 05 12:39:10 PM PST 24 7367600881 ps
T336 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.2416697473 Mar 05 12:39:00 PM PST 24 Mar 05 12:39:01 PM PST 24 402340022 ps
T337 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.812969 Mar 05 12:39:37 PM PST 24 Mar 05 12:39:44 PM PST 24 4242440581 ps
T338 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.2867371894 Mar 05 12:38:49 PM PST 24 Mar 05 12:38:50 PM PST 24 622981433 ps
T339 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.3820894111 Mar 05 12:38:59 PM PST 24 Mar 05 12:39:08 PM PST 24 537288097 ps
T340 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.3131839979 Mar 05 12:39:04 PM PST 24 Mar 05 12:39:08 PM PST 24 505182636 ps
T341 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.1254215814 Mar 05 12:39:15 PM PST 24 Mar 05 12:39:17 PM PST 24 528604317 ps
T342 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.2420771363 Mar 05 12:39:08 PM PST 24 Mar 05 12:39:10 PM PST 24 1148715086 ps
T343 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.4147194865 Mar 05 12:39:34 PM PST 24 Mar 05 12:39:35 PM PST 24 414474991 ps
T344 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.2735847422 Mar 05 12:38:54 PM PST 24 Mar 05 12:38:55 PM PST 24 398762696 ps
T345 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.2311643102 Mar 05 12:38:54 PM PST 24 Mar 05 12:38:58 PM PST 24 7059571579 ps
T346 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.3388935523 Mar 05 12:39:09 PM PST 24 Mar 05 12:39:10 PM PST 24 362063356 ps
T49 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.416834958 Mar 05 12:38:46 PM PST 24 Mar 05 12:38:47 PM PST 24 620817054 ps
T347 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.2263895106 Mar 05 12:39:03 PM PST 24 Mar 05 12:39:06 PM PST 24 4706167956 ps
T348 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.2368400987 Mar 05 12:38:52 PM PST 24 Mar 05 12:38:53 PM PST 24 458623230 ps
T349 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.3179774668 Mar 05 12:38:50 PM PST 24 Mar 05 12:38:51 PM PST 24 404167916 ps
T350 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.3746446241 Mar 05 12:38:51 PM PST 24 Mar 05 12:38:52 PM PST 24 475824412 ps
T351 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.3703635698 Mar 05 12:39:10 PM PST 24 Mar 05 12:39:13 PM PST 24 510928487 ps
T50 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.1594694913 Mar 05 12:38:42 PM PST 24 Mar 05 12:38:44 PM PST 24 306514573 ps
T352 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.3893382864 Mar 05 12:38:59 PM PST 24 Mar 05 12:39:01 PM PST 24 380543325 ps
T353 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.2709224057 Mar 05 12:39:18 PM PST 24 Mar 05 12:39:19 PM PST 24 510667167 ps
T354 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.497058122 Mar 05 12:39:05 PM PST 24 Mar 05 12:39:14 PM PST 24 556614322 ps
T355 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.2965138374 Mar 05 12:39:04 PM PST 24 Mar 05 12:39:11 PM PST 24 5025003980 ps
T356 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.3442281735 Mar 05 12:38:52 PM PST 24 Mar 05 12:38:53 PM PST 24 585825783 ps
T357 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.2291759575 Mar 05 12:39:15 PM PST 24 Mar 05 12:39:16 PM PST 24 342753663 ps
T51 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.1741311766 Mar 05 12:38:42 PM PST 24 Mar 05 12:38:43 PM PST 24 602257804 ps
T358 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.3892149940 Mar 05 12:39:02 PM PST 24 Mar 05 12:39:04 PM PST 24 398948364 ps
T359 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.1932325107 Mar 05 12:38:46 PM PST 24 Mar 05 12:38:48 PM PST 24 444292349 ps
T360 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.346001715 Mar 05 12:39:06 PM PST 24 Mar 05 12:39:07 PM PST 24 431433943 ps
T361 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.1758202864 Mar 05 12:39:04 PM PST 24 Mar 05 12:39:08 PM PST 24 515090609 ps
T362 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.1106477166 Mar 05 12:38:50 PM PST 24 Mar 05 12:38:52 PM PST 24 409819963 ps
T363 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.3821912776 Mar 05 12:39:04 PM PST 24 Mar 05 12:39:07 PM PST 24 360106024 ps
T364 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.3972239823 Mar 05 12:39:16 PM PST 24 Mar 05 12:39:17 PM PST 24 515641975 ps
T365 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.852117204 Mar 05 12:39:37 PM PST 24 Mar 05 12:39:38 PM PST 24 1494489083 ps
T366 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.610684005 Mar 05 12:39:05 PM PST 24 Mar 05 12:39:09 PM PST 24 478445518 ps
T367 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.4153211406 Mar 05 12:38:57 PM PST 24 Mar 05 12:38:57 PM PST 24 510173060 ps
T368 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.1009236489 Mar 05 12:38:51 PM PST 24 Mar 05 12:38:52 PM PST 24 603045734 ps
T369 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.182398802 Mar 05 12:39:24 PM PST 24 Mar 05 12:39:25 PM PST 24 518808405 ps
T52 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.150379173 Mar 05 12:38:36 PM PST 24 Mar 05 12:38:39 PM PST 24 6347772109 ps
T370 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.1923972997 Mar 05 12:39:01 PM PST 24 Mar 05 12:39:02 PM PST 24 514416759 ps
T371 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.2426180537 Mar 05 12:39:18 PM PST 24 Mar 05 12:39:20 PM PST 24 2405599612 ps
T372 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.4165746120 Mar 05 12:39:40 PM PST 24 Mar 05 12:39:46 PM PST 24 409803254 ps
T373 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.950894996 Mar 05 12:38:40 PM PST 24 Mar 05 12:38:43 PM PST 24 537193982 ps
T374 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.1116852864 Mar 05 12:39:10 PM PST 24 Mar 05 12:39:16 PM PST 24 431605063 ps
T375 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.1690646734 Mar 05 12:39:26 PM PST 24 Mar 05 12:39:27 PM PST 24 335515024 ps
T376 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.3699927975 Mar 05 12:38:49 PM PST 24 Mar 05 12:38:51 PM PST 24 275779255 ps
T377 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.825838995 Mar 05 12:39:09 PM PST 24 Mar 05 12:39:11 PM PST 24 456194797 ps
T378 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.3594007326 Mar 05 12:38:48 PM PST 24 Mar 05 12:38:50 PM PST 24 4721500470 ps
T379 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.980299401 Mar 05 12:39:05 PM PST 24 Mar 05 12:39:08 PM PST 24 319643469 ps
T380 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.3240624659 Mar 05 12:39:02 PM PST 24 Mar 05 12:39:04 PM PST 24 759969469 ps
T381 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.3608178521 Mar 05 12:39:06 PM PST 24 Mar 05 12:39:08 PM PST 24 510452677 ps
T382 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.2492045863 Mar 05 12:38:59 PM PST 24 Mar 05 12:39:00 PM PST 24 441369936 ps
T383 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.2004738800 Mar 05 12:39:05 PM PST 24 Mar 05 12:39:07 PM PST 24 557287858 ps
T384 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.2119301498 Mar 05 12:39:12 PM PST 24 Mar 05 12:39:14 PM PST 24 607005697 ps
T385 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.2530873909 Mar 05 12:38:46 PM PST 24 Mar 05 12:38:49 PM PST 24 604533793 ps
T386 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.3971376387 Mar 05 12:38:47 PM PST 24 Mar 05 12:38:50 PM PST 24 490201142 ps
T387 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.247600151 Mar 05 12:39:13 PM PST 24 Mar 05 12:39:15 PM PST 24 1416138879 ps
T388 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.2798368745 Mar 05 12:38:51 PM PST 24 Mar 05 12:38:52 PM PST 24 337950035 ps
T389 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.1772270014 Mar 05 12:39:29 PM PST 24 Mar 05 12:39:30 PM PST 24 538826893 ps
T390 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.1866346186 Mar 05 12:39:18 PM PST 24 Mar 05 12:39:20 PM PST 24 1183291136 ps
T391 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.221493134 Mar 05 12:38:56 PM PST 24 Mar 05 12:39:01 PM PST 24 4366675177 ps
T392 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.1851123178 Mar 05 12:39:02 PM PST 24 Mar 05 12:39:03 PM PST 24 320627236 ps
T393 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.3877973599 Mar 05 12:39:22 PM PST 24 Mar 05 12:39:23 PM PST 24 304421713 ps
T394 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.3959713874 Mar 05 12:38:57 PM PST 24 Mar 05 12:38:58 PM PST 24 514118202 ps
T395 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.2465552867 Mar 05 12:39:04 PM PST 24 Mar 05 12:39:07 PM PST 24 368198686 ps
T396 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.2516433878 Mar 05 12:39:08 PM PST 24 Mar 05 12:39:10 PM PST 24 472213885 ps
T397 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.3475180842 Mar 05 12:38:53 PM PST 24 Mar 05 12:38:53 PM PST 24 322129252 ps
T398 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.4107646792 Mar 05 12:38:53 PM PST 24 Mar 05 12:38:54 PM PST 24 451726371 ps
T53 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.1782595153 Mar 05 12:38:47 PM PST 24 Mar 05 12:38:48 PM PST 24 418836182 ps
T399 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.3298176420 Mar 05 12:39:09 PM PST 24 Mar 05 12:39:09 PM PST 24 430289924 ps
T400 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.2036616301 Mar 05 12:38:45 PM PST 24 Mar 05 12:38:46 PM PST 24 394789517 ps
T401 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.3627137600 Mar 05 12:39:02 PM PST 24 Mar 05 12:39:05 PM PST 24 4534904687 ps
T402 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.1961416706 Mar 05 12:39:10 PM PST 24 Mar 05 12:39:11 PM PST 24 438523093 ps
T403 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.3420935919 Mar 05 12:38:54 PM PST 24 Mar 05 12:38:58 PM PST 24 1793662136 ps
T404 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.1977997753 Mar 05 12:39:12 PM PST 24 Mar 05 12:39:12 PM PST 24 458496268 ps
T54 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.1763301758 Mar 05 12:38:59 PM PST 24 Mar 05 12:38:59 PM PST 24 430481036 ps
T405 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.2376096258 Mar 05 12:39:17 PM PST 24 Mar 05 12:39:19 PM PST 24 386567464 ps
T406 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.4103946610 Mar 05 12:39:15 PM PST 24 Mar 05 12:39:16 PM PST 24 405155104 ps
T407 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.2190618876 Mar 05 12:39:22 PM PST 24 Mar 05 12:39:23 PM PST 24 428724258 ps
T408 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.2351829542 Mar 05 12:39:02 PM PST 24 Mar 05 12:39:02 PM PST 24 457949428 ps
T409 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.3883080132 Mar 05 12:39:06 PM PST 24 Mar 05 12:39:07 PM PST 24 461353060 ps
T55 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.766051609 Mar 05 12:39:20 PM PST 24 Mar 05 12:39:31 PM PST 24 511156149 ps
T410 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.3813810991 Mar 05 12:39:18 PM PST 24 Mar 05 12:39:19 PM PST 24 460112431 ps
T58 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.831474021 Mar 05 12:39:10 PM PST 24 Mar 05 12:39:12 PM PST 24 503728913 ps
T411 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.1000350898 Mar 05 12:39:13 PM PST 24 Mar 05 12:39:17 PM PST 24 4718980924 ps
T412 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.3011242390 Mar 05 12:39:01 PM PST 24 Mar 05 12:39:02 PM PST 24 524380680 ps
T413 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.1072767004 Mar 05 12:38:59 PM PST 24 Mar 05 12:39:00 PM PST 24 354937891 ps
T414 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.4173434886 Mar 05 12:39:16 PM PST 24 Mar 05 12:39:18 PM PST 24 471339788 ps
T415 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.2862835817 Mar 05 12:39:12 PM PST 24 Mar 05 12:39:25 PM PST 24 8064668329 ps
T416 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.2967102261 Mar 05 12:38:50 PM PST 24 Mar 05 12:38:51 PM PST 24 490932762 ps
T417 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.3609905823 Mar 05 12:39:15 PM PST 24 Mar 05 12:39:16 PM PST 24 388832606 ps
T418 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.2570152780 Mar 05 12:39:10 PM PST 24 Mar 05 12:39:11 PM PST 24 1613834466 ps
T56 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.3098102979 Mar 05 12:39:01 PM PST 24 Mar 05 12:39:06 PM PST 24 1564978657 ps
T419 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.3121366106 Mar 05 12:39:01 PM PST 24 Mar 05 12:39:12 PM PST 24 2473602827 ps
T57 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.857027425 Mar 05 12:38:44 PM PST 24 Mar 05 12:38:46 PM PST 24 1195295281 ps
T420 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.593005615 Mar 05 12:38:57 PM PST 24 Mar 05 12:38:59 PM PST 24 1423329596 ps
T421 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.3332379835 Mar 05 12:39:10 PM PST 24 Mar 05 12:39:11 PM PST 24 597487404 ps
T422 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.409083228 Mar 05 12:39:02 PM PST 24 Mar 05 12:39:09 PM PST 24 2225861460 ps
T423 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.2056068932 Mar 05 12:39:09 PM PST 24 Mar 05 12:39:15 PM PST 24 2196803387 ps

Test location /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.2487831248
Short name T7
Test name
Test status
Simulation time 91419401585 ps
CPU time 474.52 seconds
Started Mar 05 12:40:30 PM PST 24
Finished Mar 05 12:48:26 PM PST 24
Peak memory 198768 kb
Host smart-4010ebfd-1646-4022-8edb-ef6a23d21426
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487831248 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.2487831248
Directory /workspace/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.1888493219
Short name T34
Test name
Test status
Simulation time 4025132215 ps
CPU time 6.04 seconds
Started Mar 05 12:38:49 PM PST 24
Finished Mar 05 12:38:55 PM PST 24
Peak memory 196268 kb
Host smart-5f064a57-ab54-4e36-8fa9-c8d4d835ba0b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888493219 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl
_intg_err.1888493219
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.2558741299
Short name T35
Test name
Test status
Simulation time 153644665977 ps
CPU time 718.74 seconds
Started Mar 05 12:40:29 PM PST 24
Finished Mar 05 12:52:34 PM PST 24
Peak memory 201636 kb
Host smart-a7718bf0-c9cb-4950-972e-52725269495c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558741299 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.2558741299
Directory /workspace/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.3282172742
Short name T15
Test name
Test status
Simulation time 3982110916 ps
CPU time 3.73 seconds
Started Mar 05 12:40:04 PM PST 24
Finished Mar 05 12:40:08 PM PST 24
Peak memory 215324 kb
Host smart-a35c74ca-6aca-407f-b16e-8b7498d2688f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282172742 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.3282172742
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.440109482
Short name T4
Test name
Test status
Simulation time 65893890999 ps
CPU time 23.59 seconds
Started Mar 05 12:40:07 PM PST 24
Finished Mar 05 12:40:31 PM PST 24
Peak memory 194400 kb
Host smart-def8d004-12f7-493a-858e-1d03f1eb38f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440109482 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_al
l.440109482
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.2682198766
Short name T37
Test name
Test status
Simulation time 295021912724 ps
CPU time 640.98 seconds
Started Mar 05 12:40:30 PM PST 24
Finished Mar 05 12:51:12 PM PST 24
Peak memory 206968 kb
Host smart-4acbd75f-9e4a-42ad-8da9-038fab0c777f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682198766 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.2682198766
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.1741311766
Short name T51
Test name
Test status
Simulation time 602257804 ps
CPU time 1 seconds
Started Mar 05 12:38:42 PM PST 24
Finished Mar 05 12:38:43 PM PST 24
Peak memory 193220 kb
Host smart-5faf058b-1c1d-468d-8796-3fc104e6ebbc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741311766 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_a
liasing.1741311766
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.4071026392
Short name T69
Test name
Test status
Simulation time 2158274813 ps
CPU time 3.85 seconds
Started Mar 05 12:38:51 PM PST 24
Finished Mar 05 12:38:55 PM PST 24
Peak memory 193720 kb
Host smart-f86706ae-e852-420f-a3bc-0b73b03095a0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071026392 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon
_timer_same_csr_outstanding.4071026392
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.1000350898
Short name T411
Test name
Test status
Simulation time 4718980924 ps
CPU time 3.99 seconds
Started Mar 05 12:39:13 PM PST 24
Finished Mar 05 12:39:17 PM PST 24
Peak memory 196596 kb
Host smart-cf386d8e-83ad-480d-abe8-d133bdfb683f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000350898 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_t
l_intg_err.1000350898
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.3372796047
Short name T94
Test name
Test status
Simulation time 9155510460 ps
CPU time 4.26 seconds
Started Mar 05 12:38:57 PM PST 24
Finished Mar 05 12:39:02 PM PST 24
Peak memory 196996 kb
Host smart-aeda9633-a2cb-4c1b-8855-8ee386294c60
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372796047 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_t
l_intg_err.3372796047
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.4068932595
Short name T25
Test name
Test status
Simulation time 65079506329 ps
CPU time 108.66 seconds
Started Mar 05 12:40:05 PM PST 24
Finished Mar 05 12:41:55 PM PST 24
Peak memory 184040 kb
Host smart-bc10cb45-6972-46e3-9ff5-17ca91b28d6a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068932595 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_a
ll.4068932595
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.2311643102
Short name T345
Test name
Test status
Simulation time 7059571579 ps
CPU time 4.7 seconds
Started Mar 05 12:38:54 PM PST 24
Finished Mar 05 12:38:58 PM PST 24
Peak memory 183260 kb
Host smart-3b3bb6ca-6de5-4ae9-8897-f6339da29349
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311643102 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_b
it_bash.2311643102
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.857027425
Short name T57
Test name
Test status
Simulation time 1195295281 ps
CPU time 1.53 seconds
Started Mar 05 12:38:44 PM PST 24
Finished Mar 05 12:38:46 PM PST 24
Peak memory 182924 kb
Host smart-c2810a7b-5080-4a4a-97c3-b0bc5fd03025
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857027425 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_hw
_reset.857027425
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.3604102904
Short name T299
Test name
Test status
Simulation time 469335098 ps
CPU time 0.92 seconds
Started Mar 05 12:39:07 PM PST 24
Finished Mar 05 12:39:08 PM PST 24
Peak memory 194928 kb
Host smart-fe1758a2-a901-43dc-9f72-b33be21145a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604102904 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.3604102904
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.1782595153
Short name T53
Test name
Test status
Simulation time 418836182 ps
CPU time 0.71 seconds
Started Mar 05 12:38:47 PM PST 24
Finished Mar 05 12:38:48 PM PST 24
Peak memory 182880 kb
Host smart-3d5ec985-37eb-497a-91f6-62e8aee5b1e8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782595153 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.1782595153
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.1026647154
Short name T289
Test name
Test status
Simulation time 458175444 ps
CPU time 1.01 seconds
Started Mar 05 12:38:48 PM PST 24
Finished Mar 05 12:38:49 PM PST 24
Peak memory 182796 kb
Host smart-9ad30208-5f0e-4c8b-a64c-110d9e141fbd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026647154 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.1026647154
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.2212199797
Short name T291
Test name
Test status
Simulation time 397230743 ps
CPU time 0.77 seconds
Started Mar 05 12:38:45 PM PST 24
Finished Mar 05 12:38:46 PM PST 24
Peak memory 181964 kb
Host smart-236f9109-e651-445c-9059-ea7e0e5aea73
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212199797 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_t
imer_mem_partial_access.2212199797
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.3442281735
Short name T356
Test name
Test status
Simulation time 585825783 ps
CPU time 0.57 seconds
Started Mar 05 12:38:52 PM PST 24
Finished Mar 05 12:38:53 PM PST 24
Peak memory 182016 kb
Host smart-3e4135e9-c2be-4bda-9f29-612fe09bccb5
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442281735 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_w
alk.3442281735
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.3420935919
Short name T403
Test name
Test status
Simulation time 1793662136 ps
CPU time 4.04 seconds
Started Mar 05 12:38:54 PM PST 24
Finished Mar 05 12:38:58 PM PST 24
Peak memory 193732 kb
Host smart-6a5c7951-4397-4793-ac73-8d53c111d6d0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420935919 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon
_timer_same_csr_outstanding.3420935919
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.3971376387
Short name T386
Test name
Test status
Simulation time 490201142 ps
CPU time 1.88 seconds
Started Mar 05 12:38:47 PM PST 24
Finished Mar 05 12:38:50 PM PST 24
Peak memory 197784 kb
Host smart-961805b4-a0f6-466d-a5d1-451b1bd00e31
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971376387 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.3971376387
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.2965138374
Short name T355
Test name
Test status
Simulation time 5025003980 ps
CPU time 5.13 seconds
Started Mar 05 12:39:04 PM PST 24
Finished Mar 05 12:39:11 PM PST 24
Peak memory 196840 kb
Host smart-62efb5e1-e940-4d2f-9d11-75e4b3e7618d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965138374 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl
_intg_err.2965138374
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.1009236489
Short name T368
Test name
Test status
Simulation time 603045734 ps
CPU time 0.71 seconds
Started Mar 05 12:38:51 PM PST 24
Finished Mar 05 12:38:52 PM PST 24
Peak memory 182924 kb
Host smart-777f74d0-a68d-47e2-90d4-2fa917b3a9cf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009236489 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_a
liasing.1009236489
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.3098102979
Short name T56
Test name
Test status
Simulation time 1564978657 ps
CPU time 4.14 seconds
Started Mar 05 12:39:01 PM PST 24
Finished Mar 05 12:39:06 PM PST 24
Peak memory 191396 kb
Host smart-028065bf-062e-44d1-ae15-db6251f34856
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098102979 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_b
it_bash.3098102979
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.1585200851
Short name T33
Test name
Test status
Simulation time 1195518941 ps
CPU time 2.31 seconds
Started Mar 05 12:38:52 PM PST 24
Finished Mar 05 12:38:55 PM PST 24
Peak memory 182884 kb
Host smart-93266d00-cd6b-43f6-b7ee-872b2043f590
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585200851 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_h
w_reset.1585200851
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.2270367950
Short name T314
Test name
Test status
Simulation time 566416714 ps
CPU time 0.81 seconds
Started Mar 05 12:38:59 PM PST 24
Finished Mar 05 12:38:59 PM PST 24
Peak memory 194196 kb
Host smart-aec5ce3b-09aa-4202-b317-aa6d44eaccea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270367950 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.2270367950
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.1594694913
Short name T50
Test name
Test status
Simulation time 306514573 ps
CPU time 0.69 seconds
Started Mar 05 12:38:42 PM PST 24
Finished Mar 05 12:38:44 PM PST 24
Peak memory 192396 kb
Host smart-fe5510dd-83d1-4b4a-a451-ebaf0d7589eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594694913 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.1594694913
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.4107646792
Short name T398
Test name
Test status
Simulation time 451726371 ps
CPU time 1.16 seconds
Started Mar 05 12:38:53 PM PST 24
Finished Mar 05 12:38:54 PM PST 24
Peak memory 182800 kb
Host smart-5abf2295-2301-4b7b-b13b-97ae76d4e74e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107646792 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.4107646792
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.1106477166
Short name T362
Test name
Test status
Simulation time 409819963 ps
CPU time 1.26 seconds
Started Mar 05 12:38:50 PM PST 24
Finished Mar 05 12:38:52 PM PST 24
Peak memory 182796 kb
Host smart-7a18766e-cee5-44f5-9667-e023a55914d5
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106477166 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_t
imer_mem_partial_access.1106477166
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.3092130537
Short name T296
Test name
Test status
Simulation time 499596896 ps
CPU time 1.17 seconds
Started Mar 05 12:38:49 PM PST 24
Finished Mar 05 12:38:50 PM PST 24
Peak memory 182032 kb
Host smart-20d98a3e-e93e-46f0-900e-72805757999c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092130537 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_w
alk.3092130537
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.2530873909
Short name T385
Test name
Test status
Simulation time 604533793 ps
CPU time 2.79 seconds
Started Mar 05 12:38:46 PM PST 24
Finished Mar 05 12:38:49 PM PST 24
Peak memory 197788 kb
Host smart-704795fd-efcb-4586-b559-d99e62115723
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530873909 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.2530873909
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.3594007326
Short name T378
Test name
Test status
Simulation time 4721500470 ps
CPU time 1.47 seconds
Started Mar 05 12:38:48 PM PST 24
Finished Mar 05 12:38:50 PM PST 24
Peak memory 196576 kb
Host smart-2a434975-fa77-4600-8848-3513748e7ffc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594007326 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl
_intg_err.3594007326
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.2351829542
Short name T408
Test name
Test status
Simulation time 457949428 ps
CPU time 0.82 seconds
Started Mar 05 12:39:02 PM PST 24
Finished Mar 05 12:39:02 PM PST 24
Peak memory 196056 kb
Host smart-52f2ebef-0dd0-4ff0-95b5-849bbdcc0e0d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351829542 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.2351829542
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.2465552867
Short name T395
Test name
Test status
Simulation time 368198686 ps
CPU time 0.71 seconds
Started Mar 05 12:39:04 PM PST 24
Finished Mar 05 12:39:07 PM PST 24
Peak memory 182996 kb
Host smart-051dd780-e23f-403c-bfb4-5354412cbbc9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465552867 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.2465552867
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.4081288575
Short name T331
Test name
Test status
Simulation time 442996418 ps
CPU time 0.87 seconds
Started Mar 05 12:39:12 PM PST 24
Finished Mar 05 12:39:13 PM PST 24
Peak memory 182800 kb
Host smart-5268ded9-f759-49bb-9068-bdb7bab2c20b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081288575 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.4081288575
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.593005615
Short name T420
Test name
Test status
Simulation time 1423329596 ps
CPU time 1.17 seconds
Started Mar 05 12:38:57 PM PST 24
Finished Mar 05 12:38:59 PM PST 24
Peak memory 192508 kb
Host smart-8d4ce772-328f-4150-bc84-19553436eb41
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593005615 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon
_timer_same_csr_outstanding.593005615
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.980299401
Short name T379
Test name
Test status
Simulation time 319643469 ps
CPU time 1.42 seconds
Started Mar 05 12:39:05 PM PST 24
Finished Mar 05 12:39:08 PM PST 24
Peak memory 197572 kb
Host smart-6a4d6aa4-115a-45df-b03b-fb14ba6bfed4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980299401 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.980299401
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.2263895106
Short name T347
Test name
Test status
Simulation time 4706167956 ps
CPU time 2.55 seconds
Started Mar 05 12:39:03 PM PST 24
Finished Mar 05 12:39:06 PM PST 24
Peak memory 196992 kb
Host smart-c26623a9-39c4-4134-9fd4-a88710e3f4b2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263895106 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_t
l_intg_err.2263895106
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.825838995
Short name T377
Test name
Test status
Simulation time 456194797 ps
CPU time 1.25 seconds
Started Mar 05 12:39:09 PM PST 24
Finished Mar 05 12:39:11 PM PST 24
Peak memory 194344 kb
Host smart-3648d68d-508a-446b-9108-48986c2b41ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825838995 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.825838995
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.760305322
Short name T325
Test name
Test status
Simulation time 536409032 ps
CPU time 0.97 seconds
Started Mar 05 12:39:11 PM PST 24
Finished Mar 05 12:39:12 PM PST 24
Peak memory 182924 kb
Host smart-ef2a0714-f28c-422f-b830-01fed96bff3b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760305322 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.760305322
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.4153211406
Short name T367
Test name
Test status
Simulation time 510173060 ps
CPU time 0.72 seconds
Started Mar 05 12:38:57 PM PST 24
Finished Mar 05 12:38:57 PM PST 24
Peak memory 182796 kb
Host smart-48dbffff-f8c9-4c80-be56-e527b18b5d53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153211406 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.4153211406
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.3368122326
Short name T73
Test name
Test status
Simulation time 1463471737 ps
CPU time 1.7 seconds
Started Mar 05 12:38:58 PM PST 24
Finished Mar 05 12:39:00 PM PST 24
Peak memory 182956 kb
Host smart-309711c5-e670-4f97-b2a9-906812b73658
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368122326 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.ao
n_timer_same_csr_outstanding.3368122326
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.3820894111
Short name T339
Test name
Test status
Simulation time 537288097 ps
CPU time 1.29 seconds
Started Mar 05 12:38:59 PM PST 24
Finished Mar 05 12:39:08 PM PST 24
Peak memory 197576 kb
Host smart-5ab9bf89-fb56-40c5-bb72-863a7e2228b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820894111 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.3820894111
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.2492045863
Short name T382
Test name
Test status
Simulation time 441369936 ps
CPU time 0.95 seconds
Started Mar 05 12:38:59 PM PST 24
Finished Mar 05 12:39:00 PM PST 24
Peak memory 194920 kb
Host smart-5a637f65-058f-47f2-8325-f936ae151eb6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492045863 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.2492045863
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.1977997753
Short name T404
Test name
Test status
Simulation time 458496268 ps
CPU time 0.76 seconds
Started Mar 05 12:39:12 PM PST 24
Finished Mar 05 12:39:12 PM PST 24
Peak memory 192184 kb
Host smart-80a28218-2393-4a87-9fe4-086fdc81b8fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977997753 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.1977997753
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.3883080132
Short name T409
Test name
Test status
Simulation time 461353060 ps
CPU time 0.67 seconds
Started Mar 05 12:39:06 PM PST 24
Finished Mar 05 12:39:07 PM PST 24
Peak memory 182756 kb
Host smart-a595e170-a0e2-4af6-8c54-47e116e1fa7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883080132 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.3883080132
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.247600151
Short name T387
Test name
Test status
Simulation time 1416138879 ps
CPU time 2.42 seconds
Started Mar 05 12:39:13 PM PST 24
Finished Mar 05 12:39:15 PM PST 24
Peak memory 182984 kb
Host smart-130990df-99ee-47b1-8dc9-a11d8dae5041
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247600151 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon
_timer_same_csr_outstanding.247600151
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.3703635698
Short name T351
Test name
Test status
Simulation time 510928487 ps
CPU time 2.47 seconds
Started Mar 05 12:39:10 PM PST 24
Finished Mar 05 12:39:13 PM PST 24
Peak memory 197820 kb
Host smart-8a9250e0-8b8c-4866-90dd-1356f51bb23d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703635698 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.3703635698
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.3959713874
Short name T394
Test name
Test status
Simulation time 514118202 ps
CPU time 1.42 seconds
Started Mar 05 12:38:57 PM PST 24
Finished Mar 05 12:38:58 PM PST 24
Peak memory 195416 kb
Host smart-dd9e55db-2540-4e2a-92b3-93a1babf13e6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959713874 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.3959713874
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.3746446241
Short name T350
Test name
Test status
Simulation time 475824412 ps
CPU time 0.66 seconds
Started Mar 05 12:38:51 PM PST 24
Finished Mar 05 12:38:52 PM PST 24
Peak memory 182928 kb
Host smart-0d0d0afd-59f4-493e-9428-1654f5710cc5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746446241 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.3746446241
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.3821912776
Short name T363
Test name
Test status
Simulation time 360106024 ps
CPU time 0.8 seconds
Started Mar 05 12:39:04 PM PST 24
Finished Mar 05 12:39:07 PM PST 24
Peak memory 182700 kb
Host smart-d6c4c095-7b71-4788-aa7a-6d09c5feefbc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821912776 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.3821912776
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.2056068932
Short name T423
Test name
Test status
Simulation time 2196803387 ps
CPU time 5.43 seconds
Started Mar 05 12:39:09 PM PST 24
Finished Mar 05 12:39:15 PM PST 24
Peak memory 183052 kb
Host smart-5bad68da-a0ee-40da-ac67-932289ebfb2d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056068932 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.ao
n_timer_same_csr_outstanding.2056068932
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.2119301498
Short name T384
Test name
Test status
Simulation time 607005697 ps
CPU time 2 seconds
Started Mar 05 12:39:12 PM PST 24
Finished Mar 05 12:39:14 PM PST 24
Peak memory 197672 kb
Host smart-63955614-947d-4db2-b43f-222c6e7b3f07
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119301498 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.2119301498
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.632426424
Short name T98
Test name
Test status
Simulation time 4653926968 ps
CPU time 4.06 seconds
Started Mar 05 12:39:14 PM PST 24
Finished Mar 05 12:39:18 PM PST 24
Peak memory 196732 kb
Host smart-070d35b1-ec54-4194-9b19-a49d3677a529
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632426424 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl
_intg_err.632426424
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.3574815601
Short name T313
Test name
Test status
Simulation time 467633117 ps
CPU time 1.05 seconds
Started Mar 05 12:39:20 PM PST 24
Finished Mar 05 12:39:23 PM PST 24
Peak memory 197576 kb
Host smart-a61b7a04-cbb6-4fe3-b8a3-a604840ccf34
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574815601 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.3574815601
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.3608178521
Short name T381
Test name
Test status
Simulation time 510452677 ps
CPU time 0.99 seconds
Started Mar 05 12:39:06 PM PST 24
Finished Mar 05 12:39:08 PM PST 24
Peak memory 183068 kb
Host smart-35f8d55b-dc10-4207-8c76-e20432380eaa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608178521 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.3608178521
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.3476419908
Short name T286
Test name
Test status
Simulation time 286481620 ps
CPU time 0.92 seconds
Started Mar 05 12:39:13 PM PST 24
Finished Mar 05 12:39:14 PM PST 24
Peak memory 182760 kb
Host smart-f0656fec-f246-4748-8e26-af55462d2764
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476419908 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.3476419908
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.2150352956
Short name T328
Test name
Test status
Simulation time 1198745609 ps
CPU time 1.21 seconds
Started Mar 05 12:39:14 PM PST 24
Finished Mar 05 12:39:16 PM PST 24
Peak memory 192512 kb
Host smart-686f4696-4fdc-499b-81c4-9009188d8fc0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150352956 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao
n_timer_same_csr_outstanding.2150352956
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.3892149940
Short name T358
Test name
Test status
Simulation time 398948364 ps
CPU time 1.63 seconds
Started Mar 05 12:39:02 PM PST 24
Finished Mar 05 12:39:04 PM PST 24
Peak memory 197784 kb
Host smart-346da1aa-d0a9-4533-9ea8-3fd6e08d4554
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892149940 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.3892149940
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.2163877305
Short name T309
Test name
Test status
Simulation time 4145923276 ps
CPU time 3.76 seconds
Started Mar 05 12:39:07 PM PST 24
Finished Mar 05 12:39:11 PM PST 24
Peak memory 196660 kb
Host smart-315a5a3c-48ca-4828-9e3f-117e6d7ba1c3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163877305 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_t
l_intg_err.2163877305
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.1758202864
Short name T361
Test name
Test status
Simulation time 515090609 ps
CPU time 1.31 seconds
Started Mar 05 12:39:04 PM PST 24
Finished Mar 05 12:39:08 PM PST 24
Peak memory 194504 kb
Host smart-2708d35b-4b9b-487b-bfb2-04883f2f6ed3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758202864 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.1758202864
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.766051609
Short name T55
Test name
Test status
Simulation time 511156149 ps
CPU time 0.74 seconds
Started Mar 05 12:39:20 PM PST 24
Finished Mar 05 12:39:31 PM PST 24
Peak memory 183116 kb
Host smart-628170f4-ae11-456a-b0b9-17d39a39731e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766051609 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.766051609
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.1760415926
Short name T330
Test name
Test status
Simulation time 521776391 ps
CPU time 1.1 seconds
Started Mar 05 12:39:14 PM PST 24
Finished Mar 05 12:39:15 PM PST 24
Peak memory 183008 kb
Host smart-4a16553b-75fd-4623-bfcb-e4498ae67232
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760415926 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.1760415926
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.3121366106
Short name T419
Test name
Test status
Simulation time 2473602827 ps
CPU time 5.69 seconds
Started Mar 05 12:39:01 PM PST 24
Finished Mar 05 12:39:12 PM PST 24
Peak memory 183052 kb
Host smart-d5e25bcd-cb2b-47b5-aa2d-9c914bf1503c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121366106 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.ao
n_timer_same_csr_outstanding.3121366106
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.3972239823
Short name T364
Test name
Test status
Simulation time 515641975 ps
CPU time 1.3 seconds
Started Mar 05 12:39:16 PM PST 24
Finished Mar 05 12:39:17 PM PST 24
Peak memory 197208 kb
Host smart-c555bf42-1878-4162-a6c9-6a8b20ce8f6c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972239823 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.3972239823
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.812969
Short name T337
Test name
Test status
Simulation time 4242440581 ps
CPU time 7.48 seconds
Started Mar 05 12:39:37 PM PST 24
Finished Mar 05 12:39:44 PM PST 24
Peak memory 196688 kb
Host smart-aa3bce75-e45a-4d2a-966c-ba5e717df234
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812969 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_in
tg_err.812969
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.136189569
Short name T99
Test name
Test status
Simulation time 483221060 ps
CPU time 1.08 seconds
Started Mar 05 12:39:21 PM PST 24
Finished Mar 05 12:39:23 PM PST 24
Peak memory 194516 kb
Host smart-8e3a8105-7dfc-4ea4-9157-752d9a181034
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136189569 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.136189569
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.3388935523
Short name T346
Test name
Test status
Simulation time 362063356 ps
CPU time 0.68 seconds
Started Mar 05 12:39:09 PM PST 24
Finished Mar 05 12:39:10 PM PST 24
Peak memory 183112 kb
Host smart-bb229190-81f3-4bfd-ad07-82ba52d4fbc6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388935523 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.3388935523
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.182398802
Short name T369
Test name
Test status
Simulation time 518808405 ps
CPU time 1.38 seconds
Started Mar 05 12:39:24 PM PST 24
Finished Mar 05 12:39:25 PM PST 24
Peak memory 182800 kb
Host smart-c19468e3-1ef1-4b5c-878b-ec4726d71022
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182398802 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.182398802
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.2570152780
Short name T418
Test name
Test status
Simulation time 1613834466 ps
CPU time 1.18 seconds
Started Mar 05 12:39:10 PM PST 24
Finished Mar 05 12:39:11 PM PST 24
Peak memory 182924 kb
Host smart-222a63a9-5d5f-4d5c-b446-28e264c51dee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570152780 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.ao
n_timer_same_csr_outstanding.2570152780
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.2344328768
Short name T294
Test name
Test status
Simulation time 545896290 ps
CPU time 2.97 seconds
Started Mar 05 12:39:00 PM PST 24
Finished Mar 05 12:39:03 PM PST 24
Peak memory 197788 kb
Host smart-08372788-2cfe-43ac-960c-f9f974eaf581
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344328768 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.2344328768
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.221493134
Short name T391
Test name
Test status
Simulation time 4366675177 ps
CPU time 5.3 seconds
Started Mar 05 12:38:56 PM PST 24
Finished Mar 05 12:39:01 PM PST 24
Peak memory 196760 kb
Host smart-4f2f561f-73d7-4024-b630-12027d1961b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221493134 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl
_intg_err.221493134
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.2004738800
Short name T383
Test name
Test status
Simulation time 557287858 ps
CPU time 1.07 seconds
Started Mar 05 12:39:05 PM PST 24
Finished Mar 05 12:39:07 PM PST 24
Peak memory 194528 kb
Host smart-9b8f8a37-587a-4c44-9238-33c5d46d78bd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004738800 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.2004738800
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.2223928344
Short name T48
Test name
Test status
Simulation time 468834875 ps
CPU time 0.75 seconds
Started Mar 05 12:39:13 PM PST 24
Finished Mar 05 12:39:14 PM PST 24
Peak memory 183112 kb
Host smart-6065e620-521e-4d85-a004-9e3cca33d158
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223928344 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.2223928344
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.2709224057
Short name T353
Test name
Test status
Simulation time 510667167 ps
CPU time 0.6 seconds
Started Mar 05 12:39:18 PM PST 24
Finished Mar 05 12:39:19 PM PST 24
Peak memory 182852 kb
Host smart-5fa5dcb4-950e-466b-b2f7-51e96b4c6d55
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709224057 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.2709224057
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.1866346186
Short name T390
Test name
Test status
Simulation time 1183291136 ps
CPU time 2.15 seconds
Started Mar 05 12:39:18 PM PST 24
Finished Mar 05 12:39:20 PM PST 24
Peak memory 192592 kb
Host smart-4376f4d9-4656-4aef-b719-53831615cfbd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866346186 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.ao
n_timer_same_csr_outstanding.1866346186
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.1254215814
Short name T341
Test name
Test status
Simulation time 528604317 ps
CPU time 2.25 seconds
Started Mar 05 12:39:15 PM PST 24
Finished Mar 05 12:39:17 PM PST 24
Peak memory 197784 kb
Host smart-6e07f86a-02c3-4602-8352-963c927c4038
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254215814 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.1254215814
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.2862835817
Short name T415
Test name
Test status
Simulation time 8064668329 ps
CPU time 12.63 seconds
Started Mar 05 12:39:12 PM PST 24
Finished Mar 05 12:39:25 PM PST 24
Peak memory 197144 kb
Host smart-153a23e7-1459-4573-8d46-344695b8a93e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862835817 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_t
l_intg_err.2862835817
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.1283083531
Short name T308
Test name
Test status
Simulation time 605584101 ps
CPU time 1.49 seconds
Started Mar 05 12:39:15 PM PST 24
Finished Mar 05 12:39:17 PM PST 24
Peak memory 194896 kb
Host smart-48a3a8ef-a65c-48ed-b654-ef9a9adab898
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283083531 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.1283083531
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.291821770
Short name T47
Test name
Test status
Simulation time 481535259 ps
CPU time 0.89 seconds
Started Mar 05 12:39:11 PM PST 24
Finished Mar 05 12:39:12 PM PST 24
Peak memory 182964 kb
Host smart-7d1a11d4-14c5-4f1c-883a-c1c018abf75e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291821770 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.291821770
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.397209005
Short name T290
Test name
Test status
Simulation time 420094243 ps
CPU time 0.63 seconds
Started Mar 05 12:39:28 PM PST 24
Finished Mar 05 12:39:28 PM PST 24
Peak memory 182752 kb
Host smart-fa44a12e-75d3-4861-b8e8-c0b4aa6d90b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397209005 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.397209005
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.2426180537
Short name T371
Test name
Test status
Simulation time 2405599612 ps
CPU time 1.17 seconds
Started Mar 05 12:39:18 PM PST 24
Finished Mar 05 12:39:20 PM PST 24
Peak memory 193692 kb
Host smart-d3c7b237-beaa-4049-b94d-38ff3014a119
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426180537 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.ao
n_timer_same_csr_outstanding.2426180537
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.3240624659
Short name T380
Test name
Test status
Simulation time 759969469 ps
CPU time 2.16 seconds
Started Mar 05 12:39:02 PM PST 24
Finished Mar 05 12:39:04 PM PST 24
Peak memory 197668 kb
Host smart-15eb3491-fcd3-4cad-be77-3942c320bae2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240624659 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.3240624659
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.2355472163
Short name T96
Test name
Test status
Simulation time 4435305013 ps
CPU time 7.76 seconds
Started Mar 05 12:39:09 PM PST 24
Finished Mar 05 12:39:17 PM PST 24
Peak memory 196604 kb
Host smart-d22294a5-69e4-49c8-908b-98592d2a05e3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355472163 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_t
l_intg_err.2355472163
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.3332379835
Short name T421
Test name
Test status
Simulation time 597487404 ps
CPU time 1.1 seconds
Started Mar 05 12:39:10 PM PST 24
Finished Mar 05 12:39:11 PM PST 24
Peak memory 197648 kb
Host smart-e9768207-a671-4d8d-a1b0-e99ec21631e6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332379835 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.3332379835
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.619821757
Short name T329
Test name
Test status
Simulation time 429948271 ps
CPU time 1.24 seconds
Started Mar 05 12:39:27 PM PST 24
Finished Mar 05 12:39:28 PM PST 24
Peak memory 183032 kb
Host smart-95b356d7-7fd0-4ee8-9fca-45776f50f8e8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619821757 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.619821757
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.2092547794
Short name T320
Test name
Test status
Simulation time 376072744 ps
CPU time 0.7 seconds
Started Mar 05 12:39:12 PM PST 24
Finished Mar 05 12:39:13 PM PST 24
Peak memory 182792 kb
Host smart-b52a177b-35c1-4a17-b1b5-8913d3b7e875
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092547794 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.2092547794
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.1321940070
Short name T32
Test name
Test status
Simulation time 2336254887 ps
CPU time 6.21 seconds
Started Mar 05 12:39:08 PM PST 24
Finished Mar 05 12:39:14 PM PST 24
Peak memory 193592 kb
Host smart-1c6b1339-2a64-46c2-a731-501e77fd280d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321940070 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao
n_timer_same_csr_outstanding.1321940070
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.610684005
Short name T366
Test name
Test status
Simulation time 478445518 ps
CPU time 2.38 seconds
Started Mar 05 12:39:05 PM PST 24
Finished Mar 05 12:39:09 PM PST 24
Peak memory 197752 kb
Host smart-edd3e070-b690-4c0a-99bb-42bf0c6cfb48
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610684005 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.610684005
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.849396718
Short name T92
Test name
Test status
Simulation time 3910390395 ps
CPU time 2.32 seconds
Started Mar 05 12:39:12 PM PST 24
Finished Mar 05 12:39:14 PM PST 24
Peak memory 195540 kb
Host smart-66c8ceae-07d2-4c00-83c4-b8af3e836cfe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849396718 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl
_intg_err.849396718
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.722855719
Short name T302
Test name
Test status
Simulation time 578027632 ps
CPU time 0.89 seconds
Started Mar 05 12:39:06 PM PST 24
Finished Mar 05 12:39:08 PM PST 24
Peak memory 182932 kb
Host smart-c9f75c94-113f-4902-8900-f640674d047e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722855719 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_al
iasing.722855719
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.1655490991
Short name T293
Test name
Test status
Simulation time 13918928956 ps
CPU time 13.19 seconds
Started Mar 05 12:38:58 PM PST 24
Finished Mar 05 12:39:11 PM PST 24
Peak memory 191456 kb
Host smart-396b6cd4-46d8-45e1-bf48-bc36e433f6b2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655490991 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_b
it_bash.1655490991
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.3239448531
Short name T333
Test name
Test status
Simulation time 888847812 ps
CPU time 2.05 seconds
Started Mar 05 12:38:59 PM PST 24
Finished Mar 05 12:39:01 PM PST 24
Peak memory 182996 kb
Host smart-8e6e2fe2-00ea-4c4e-a39b-fee4388174e4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239448531 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_h
w_reset.3239448531
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.1932325107
Short name T359
Test name
Test status
Simulation time 444292349 ps
CPU time 0.99 seconds
Started Mar 05 12:38:46 PM PST 24
Finished Mar 05 12:38:48 PM PST 24
Peak memory 197240 kb
Host smart-c5ecca5b-a046-45d2-9f3d-b45f5cdbdfe1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932325107 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.1932325107
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.3289616314
Short name T76
Test name
Test status
Simulation time 683699178 ps
CPU time 0.63 seconds
Started Mar 05 12:38:56 PM PST 24
Finished Mar 05 12:38:56 PM PST 24
Peak memory 183104 kb
Host smart-1a2a9dee-80bd-416f-9249-a56866521ed6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289616314 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.3289616314
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.2735847422
Short name T344
Test name
Test status
Simulation time 398762696 ps
CPU time 0.82 seconds
Started Mar 05 12:38:54 PM PST 24
Finished Mar 05 12:38:55 PM PST 24
Peak memory 182776 kb
Host smart-1960f35a-9fcb-4cb4-9884-0f2415b1f26e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735847422 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.2735847422
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.2368400987
Short name T348
Test name
Test status
Simulation time 458623230 ps
CPU time 0.7 seconds
Started Mar 05 12:38:52 PM PST 24
Finished Mar 05 12:38:53 PM PST 24
Peak memory 182036 kb
Host smart-dd84e2c3-2ea8-4439-8ed3-e9374109d87c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368400987 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_t
imer_mem_partial_access.2368400987
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.3699927975
Short name T376
Test name
Test status
Simulation time 275779255 ps
CPU time 0.91 seconds
Started Mar 05 12:38:49 PM PST 24
Finished Mar 05 12:38:51 PM PST 24
Peak memory 182800 kb
Host smart-03661d7b-d545-4326-8b8a-98cdf3da8557
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699927975 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_w
alk.3699927975
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.4182823217
Short name T71
Test name
Test status
Simulation time 2881508398 ps
CPU time 3.03 seconds
Started Mar 05 12:39:15 PM PST 24
Finished Mar 05 12:39:23 PM PST 24
Peak memory 193808 kb
Host smart-eabe14c0-685f-4c8d-9787-930d544257c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182823217 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon
_timer_same_csr_outstanding.4182823217
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.950894996
Short name T373
Test name
Test status
Simulation time 537193982 ps
CPU time 1.89 seconds
Started Mar 05 12:38:40 PM PST 24
Finished Mar 05 12:38:43 PM PST 24
Peak memory 197812 kb
Host smart-a497d7f6-5d87-4610-ba80-c9e48239adbf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950894996 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.950894996
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.4103946610
Short name T406
Test name
Test status
Simulation time 405155104 ps
CPU time 1.11 seconds
Started Mar 05 12:39:15 PM PST 24
Finished Mar 05 12:39:16 PM PST 24
Peak memory 182956 kb
Host smart-9d5dbda9-8e17-40b7-9efd-052fe9ebc1a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103946610 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.4103946610
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.1772270014
Short name T389
Test name
Test status
Simulation time 538826893 ps
CPU time 0.7 seconds
Started Mar 05 12:39:29 PM PST 24
Finished Mar 05 12:39:30 PM PST 24
Peak memory 182800 kb
Host smart-d94c3d21-831f-4069-a47d-f2421a3cd8a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772270014 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.1772270014
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.4159588984
Short name T284
Test name
Test status
Simulation time 518176081 ps
CPU time 1.05 seconds
Started Mar 05 12:39:15 PM PST 24
Finished Mar 05 12:39:17 PM PST 24
Peak memory 182252 kb
Host smart-d3d54169-1d23-4dd5-a915-6b482234388c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159588984 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.4159588984
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.1851123178
Short name T392
Test name
Test status
Simulation time 320627236 ps
CPU time 0.65 seconds
Started Mar 05 12:39:02 PM PST 24
Finished Mar 05 12:39:03 PM PST 24
Peak memory 182852 kb
Host smart-93bfffeb-4e9b-4017-a1dd-31ee03e90120
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851123178 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.1851123178
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.2216947280
Short name T285
Test name
Test status
Simulation time 520568909 ps
CPU time 1.04 seconds
Started Mar 05 12:39:17 PM PST 24
Finished Mar 05 12:39:19 PM PST 24
Peak memory 182760 kb
Host smart-51134ec4-182e-41fc-926b-05cb2e37b0a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216947280 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.2216947280
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.4147194865
Short name T343
Test name
Test status
Simulation time 414474991 ps
CPU time 0.69 seconds
Started Mar 05 12:39:34 PM PST 24
Finished Mar 05 12:39:35 PM PST 24
Peak memory 182708 kb
Host smart-46b619f3-d22b-4935-8c94-d43dca7127b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147194865 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.4147194865
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.1112968330
Short name T306
Test name
Test status
Simulation time 384705754 ps
CPU time 0.66 seconds
Started Mar 05 12:39:06 PM PST 24
Finished Mar 05 12:39:08 PM PST 24
Peak memory 182708 kb
Host smart-ce19bdfb-297f-4997-9cbf-59b0a5c30069
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112968330 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.1112968330
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.3609905823
Short name T417
Test name
Test status
Simulation time 388832606 ps
CPU time 0.79 seconds
Started Mar 05 12:39:15 PM PST 24
Finished Mar 05 12:39:16 PM PST 24
Peak memory 182796 kb
Host smart-6b8b3354-f222-4432-a641-6e44d370d8ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609905823 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.3609905823
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.3131839979
Short name T340
Test name
Test status
Simulation time 505182636 ps
CPU time 1.29 seconds
Started Mar 05 12:39:04 PM PST 24
Finished Mar 05 12:39:08 PM PST 24
Peak memory 182700 kb
Host smart-fa6e7376-177b-413f-8729-2ba9ab9a20a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131839979 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.3131839979
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.3765315608
Short name T319
Test name
Test status
Simulation time 384911087 ps
CPU time 1.06 seconds
Started Mar 05 12:39:10 PM PST 24
Finished Mar 05 12:39:11 PM PST 24
Peak memory 182708 kb
Host smart-609d1adb-d737-4103-b33c-78a116c455bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765315608 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.3765315608
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.416834958
Short name T49
Test name
Test status
Simulation time 620817054 ps
CPU time 1.01 seconds
Started Mar 05 12:38:46 PM PST 24
Finished Mar 05 12:38:47 PM PST 24
Peak memory 182924 kb
Host smart-b8682b71-b544-4102-8f8f-04aeb23fc95c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416834958 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_al
iasing.416834958
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.150379173
Short name T52
Test name
Test status
Simulation time 6347772109 ps
CPU time 2.44 seconds
Started Mar 05 12:38:36 PM PST 24
Finished Mar 05 12:38:39 PM PST 24
Peak memory 191432 kb
Host smart-9832dd11-7ff0-4337-ba5b-ac58319675c9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150379173 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_bi
t_bash.150379173
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.3946162407
Short name T287
Test name
Test status
Simulation time 862916119 ps
CPU time 0.72 seconds
Started Mar 05 12:38:47 PM PST 24
Finished Mar 05 12:38:48 PM PST 24
Peak memory 182924 kb
Host smart-e4f58abe-e8cc-4db0-bc7f-31f8c04b1116
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946162407 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_h
w_reset.3946162407
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.2867371894
Short name T338
Test name
Test status
Simulation time 622981433 ps
CPU time 0.82 seconds
Started Mar 05 12:38:49 PM PST 24
Finished Mar 05 12:38:50 PM PST 24
Peak memory 197516 kb
Host smart-6e8ebeb9-9633-4297-a322-f98ff8207bd6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867371894 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.2867371894
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.831474021
Short name T58
Test name
Test status
Simulation time 503728913 ps
CPU time 1.29 seconds
Started Mar 05 12:39:10 PM PST 24
Finished Mar 05 12:39:12 PM PST 24
Peak memory 183164 kb
Host smart-9e765a1a-e858-40c6-b588-c8117363248b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831474021 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.831474021
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.2798368745
Short name T388
Test name
Test status
Simulation time 337950035 ps
CPU time 0.67 seconds
Started Mar 05 12:38:51 PM PST 24
Finished Mar 05 12:38:52 PM PST 24
Peak memory 182800 kb
Host smart-19e26767-0687-4095-a616-802262d260d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798368745 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.2798368745
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.3192296581
Short name T321
Test name
Test status
Simulation time 285420197 ps
CPU time 0.93 seconds
Started Mar 05 12:38:54 PM PST 24
Finished Mar 05 12:38:55 PM PST 24
Peak memory 182796 kb
Host smart-fbc862ad-698d-4ea3-8248-0470c25a1284
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192296581 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_t
imer_mem_partial_access.3192296581
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.2967102261
Short name T416
Test name
Test status
Simulation time 490932762 ps
CPU time 0.72 seconds
Started Mar 05 12:38:50 PM PST 24
Finished Mar 05 12:38:51 PM PST 24
Peak memory 182020 kb
Host smart-819d3e46-3862-4257-9c86-5d723da97035
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967102261 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_w
alk.2967102261
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.409083228
Short name T422
Test name
Test status
Simulation time 2225861460 ps
CPU time 6.25 seconds
Started Mar 05 12:39:02 PM PST 24
Finished Mar 05 12:39:09 PM PST 24
Peak memory 183048 kb
Host smart-cbd0da2d-db6c-423f-bc8c-16a8c04a30cb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409083228 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_
timer_same_csr_outstanding.409083228
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.2707542131
Short name T317
Test name
Test status
Simulation time 516945776 ps
CPU time 1.52 seconds
Started Mar 05 12:38:56 PM PST 24
Finished Mar 05 12:38:57 PM PST 24
Peak memory 197680 kb
Host smart-6cb65c20-f3be-4bfa-b8c4-3b958daff19e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707542131 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.2707542131
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.2141011848
Short name T93
Test name
Test status
Simulation time 3635959469 ps
CPU time 6.08 seconds
Started Mar 05 12:38:51 PM PST 24
Finished Mar 05 12:38:57 PM PST 24
Peak memory 196640 kb
Host smart-4da11dc2-1f62-4d6b-94d9-331147e0c209
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141011848 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl
_intg_err.2141011848
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.186356416
Short name T318
Test name
Test status
Simulation time 425461408 ps
CPU time 0.71 seconds
Started Mar 05 12:39:40 PM PST 24
Finished Mar 05 12:39:41 PM PST 24
Peak memory 182796 kb
Host smart-de5d84f0-13ac-4903-988e-dd71cd64ce70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186356416 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.186356416
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.2681676315
Short name T307
Test name
Test status
Simulation time 409690347 ps
CPU time 1.23 seconds
Started Mar 05 12:39:23 PM PST 24
Finished Mar 05 12:39:25 PM PST 24
Peak memory 182800 kb
Host smart-43e6844f-532a-4828-976c-1f63f03e896c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681676315 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.2681676315
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.1490145822
Short name T311
Test name
Test status
Simulation time 453331266 ps
CPU time 0.88 seconds
Started Mar 05 12:39:09 PM PST 24
Finished Mar 05 12:39:10 PM PST 24
Peak memory 182724 kb
Host smart-f8afd4da-b807-40b6-947c-2bb7c601098e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490145822 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.1490145822
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.164330474
Short name T315
Test name
Test status
Simulation time 307495297 ps
CPU time 0.65 seconds
Started Mar 05 12:39:20 PM PST 24
Finished Mar 05 12:39:21 PM PST 24
Peak memory 182800 kb
Host smart-358b895d-af94-4f94-9129-fef2f2237767
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164330474 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.164330474
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.3209743934
Short name T295
Test name
Test status
Simulation time 462373038 ps
CPU time 1.23 seconds
Started Mar 05 12:39:13 PM PST 24
Finished Mar 05 12:39:14 PM PST 24
Peak memory 182728 kb
Host smart-d2c99fe6-b7b2-4f29-9d06-19d3d284cc14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209743934 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.3209743934
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.58303932
Short name T332
Test name
Test status
Simulation time 494758855 ps
CPU time 1.23 seconds
Started Mar 05 12:39:36 PM PST 24
Finished Mar 05 12:39:38 PM PST 24
Peak memory 182800 kb
Host smart-c9c540bd-a73b-454b-9de8-624efe14fbc3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58303932 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.58303932
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.4120159554
Short name T334
Test name
Test status
Simulation time 323130671 ps
CPU time 0.66 seconds
Started Mar 05 12:39:11 PM PST 24
Finished Mar 05 12:39:12 PM PST 24
Peak memory 182800 kb
Host smart-5418556e-ce97-4001-8298-c379f7ecac72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120159554 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.4120159554
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.346001715
Short name T360
Test name
Test status
Simulation time 431433943 ps
CPU time 1.05 seconds
Started Mar 05 12:39:06 PM PST 24
Finished Mar 05 12:39:07 PM PST 24
Peak memory 182796 kb
Host smart-1e713127-7ab2-427e-b66f-db2ec30011bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346001715 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.346001715
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.3877973599
Short name T393
Test name
Test status
Simulation time 304421713 ps
CPU time 0.94 seconds
Started Mar 05 12:39:22 PM PST 24
Finished Mar 05 12:39:23 PM PST 24
Peak memory 182800 kb
Host smart-dee0f54a-7c3b-4fdf-90d7-7c88f1052f40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877973599 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.3877973599
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.2453265436
Short name T283
Test name
Test status
Simulation time 455312823 ps
CPU time 0.93 seconds
Started Mar 05 12:39:10 PM PST 24
Finished Mar 05 12:39:11 PM PST 24
Peak memory 182676 kb
Host smart-74995ebc-1a05-4c0d-9228-cbee214ed053
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453265436 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.2453265436
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.1923972997
Short name T370
Test name
Test status
Simulation time 514416759 ps
CPU time 1.39 seconds
Started Mar 05 12:39:01 PM PST 24
Finished Mar 05 12:39:02 PM PST 24
Peak memory 192276 kb
Host smart-269def85-7d17-4143-8cd0-21ac32ac1f8d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923972997 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_a
liasing.1923972997
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.849347008
Short name T335
Test name
Test status
Simulation time 7367600881 ps
CPU time 11.27 seconds
Started Mar 05 12:38:59 PM PST 24
Finished Mar 05 12:39:10 PM PST 24
Peak memory 191496 kb
Host smart-f04b397e-a394-485a-9f6c-3eeb69c9f015
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849347008 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_bi
t_bash.849347008
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.3504486719
Short name T300
Test name
Test status
Simulation time 1175215054 ps
CPU time 2.16 seconds
Started Mar 05 12:38:52 PM PST 24
Finished Mar 05 12:38:59 PM PST 24
Peak memory 182972 kb
Host smart-3ad2462e-fcbb-480c-8178-0e3487e9f847
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504486719 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_h
w_reset.3504486719
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.2416697473
Short name T336
Test name
Test status
Simulation time 402340022 ps
CPU time 1.09 seconds
Started Mar 05 12:39:00 PM PST 24
Finished Mar 05 12:39:01 PM PST 24
Peak memory 194928 kb
Host smart-4d80349d-52f0-465a-9b58-31268d310d43
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416697473 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.2416697473
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.730010320
Short name T72
Test name
Test status
Simulation time 443660323 ps
CPU time 1.31 seconds
Started Mar 05 12:38:59 PM PST 24
Finished Mar 05 12:39:00 PM PST 24
Peak memory 182924 kb
Host smart-b5f52d75-4b84-4368-a601-2529a49a2a44
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730010320 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.730010320
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.2376096258
Short name T405
Test name
Test status
Simulation time 386567464 ps
CPU time 1.08 seconds
Started Mar 05 12:39:17 PM PST 24
Finished Mar 05 12:39:19 PM PST 24
Peak memory 182792 kb
Host smart-ebc124ee-131e-4067-8c4c-5fa905197a24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376096258 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.2376096258
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.3475180842
Short name T397
Test name
Test status
Simulation time 322129252 ps
CPU time 0.62 seconds
Started Mar 05 12:38:53 PM PST 24
Finished Mar 05 12:38:53 PM PST 24
Peak memory 182120 kb
Host smart-938d819a-f3e8-45e9-8b94-91d03d88f035
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475180842 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_t
imer_mem_partial_access.3475180842
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.2036616301
Short name T400
Test name
Test status
Simulation time 394789517 ps
CPU time 0.64 seconds
Started Mar 05 12:38:45 PM PST 24
Finished Mar 05 12:38:46 PM PST 24
Peak memory 182032 kb
Host smart-6b9b5589-2aa5-4bea-945d-7f2271df593f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036616301 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_w
alk.2036616301
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.2949703685
Short name T68
Test name
Test status
Simulation time 1378111526 ps
CPU time 4.23 seconds
Started Mar 05 12:39:17 PM PST 24
Finished Mar 05 12:39:21 PM PST 24
Peak memory 192424 kb
Host smart-183954c4-8b8e-49de-a171-181bd758b905
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949703685 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon
_timer_same_csr_outstanding.2949703685
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.2420771363
Short name T342
Test name
Test status
Simulation time 1148715086 ps
CPU time 2.09 seconds
Started Mar 05 12:39:08 PM PST 24
Finished Mar 05 12:39:10 PM PST 24
Peak memory 197788 kb
Host smart-9b6e4997-ef1c-4e20-b639-cbef4073306d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420771363 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.2420771363
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.1368745083
Short name T322
Test name
Test status
Simulation time 4511707992 ps
CPU time 2.69 seconds
Started Mar 05 12:38:43 PM PST 24
Finished Mar 05 12:38:47 PM PST 24
Peak memory 196288 kb
Host smart-faa40165-5f7b-41fc-8802-1759391c3939
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368745083 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl
_intg_err.1368745083
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.4165746120
Short name T372
Test name
Test status
Simulation time 409803254 ps
CPU time 0.62 seconds
Started Mar 05 12:39:40 PM PST 24
Finished Mar 05 12:39:46 PM PST 24
Peak memory 182796 kb
Host smart-854f7959-369c-4549-9b38-24f561988bcb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165746120 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.4165746120
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.2445903798
Short name T298
Test name
Test status
Simulation time 491848936 ps
CPU time 1.18 seconds
Started Mar 05 12:39:08 PM PST 24
Finished Mar 05 12:39:09 PM PST 24
Peak memory 182800 kb
Host smart-9adb4c7c-497f-479f-982b-0348ee104633
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445903798 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.2445903798
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.1116852864
Short name T374
Test name
Test status
Simulation time 431605063 ps
CPU time 0.88 seconds
Started Mar 05 12:39:10 PM PST 24
Finished Mar 05 12:39:16 PM PST 24
Peak memory 182796 kb
Host smart-2dffe916-780d-49e2-9703-43c8c3dc4917
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116852864 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.1116852864
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.3813810991
Short name T410
Test name
Test status
Simulation time 460112431 ps
CPU time 0.74 seconds
Started Mar 05 12:39:18 PM PST 24
Finished Mar 05 12:39:19 PM PST 24
Peak memory 182796 kb
Host smart-a142b2fc-f45d-4eca-96c6-16f8c6904f5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813810991 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.3813810991
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.4284169696
Short name T310
Test name
Test status
Simulation time 338491096 ps
CPU time 0.78 seconds
Started Mar 05 12:39:26 PM PST 24
Finished Mar 05 12:39:27 PM PST 24
Peak memory 182800 kb
Host smart-f3421930-59d5-4f90-9f97-75f219227106
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284169696 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.4284169696
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.1961416706
Short name T402
Test name
Test status
Simulation time 438523093 ps
CPU time 1.18 seconds
Started Mar 05 12:39:10 PM PST 24
Finished Mar 05 12:39:11 PM PST 24
Peak memory 182824 kb
Host smart-d1e0dc74-828f-471c-8957-58896941039c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961416706 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.1961416706
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.3400985195
Short name T304
Test name
Test status
Simulation time 351180134 ps
CPU time 1.09 seconds
Started Mar 05 12:39:23 PM PST 24
Finished Mar 05 12:39:24 PM PST 24
Peak memory 182800 kb
Host smart-d99e8b29-cd22-4ef5-aeed-8b0dc3034e69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400985195 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.3400985195
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.450576955
Short name T312
Test name
Test status
Simulation time 335775410 ps
CPU time 0.59 seconds
Started Mar 05 12:39:31 PM PST 24
Finished Mar 05 12:39:31 PM PST 24
Peak memory 182800 kb
Host smart-7a54ef47-4276-4b24-be30-7e0f798b768d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450576955 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.450576955
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.2894467687
Short name T303
Test name
Test status
Simulation time 462173962 ps
CPU time 0.69 seconds
Started Mar 05 12:39:13 PM PST 24
Finished Mar 05 12:39:14 PM PST 24
Peak memory 182804 kb
Host smart-50f05b15-1b33-4127-aecd-102b40b0f86b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894467687 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.2894467687
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.3298176420
Short name T399
Test name
Test status
Simulation time 430289924 ps
CPU time 0.88 seconds
Started Mar 05 12:39:09 PM PST 24
Finished Mar 05 12:39:09 PM PST 24
Peak memory 182852 kb
Host smart-48bffd04-b7b5-433c-b73f-97c0d547a4a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298176420 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.3298176420
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.708236751
Short name T316
Test name
Test status
Simulation time 490784368 ps
CPU time 0.78 seconds
Started Mar 05 12:39:14 PM PST 24
Finished Mar 05 12:39:14 PM PST 24
Peak memory 195348 kb
Host smart-3185ba17-e50f-41a7-be07-ecf618ce01da
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708236751 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.708236751
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.1763301758
Short name T54
Test name
Test status
Simulation time 430481036 ps
CPU time 0.73 seconds
Started Mar 05 12:38:59 PM PST 24
Finished Mar 05 12:38:59 PM PST 24
Peak memory 183160 kb
Host smart-3d72f3a2-76da-46bd-a98d-c2102f3742ba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763301758 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.1763301758
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.3011242390
Short name T412
Test name
Test status
Simulation time 524380680 ps
CPU time 0.64 seconds
Started Mar 05 12:39:01 PM PST 24
Finished Mar 05 12:39:02 PM PST 24
Peak memory 182800 kb
Host smart-a98a3673-6c58-4cf2-bb58-e40df574dadd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011242390 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.3011242390
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.235003713
Short name T327
Test name
Test status
Simulation time 1568129180 ps
CPU time 1 seconds
Started Mar 05 12:39:15 PM PST 24
Finished Mar 05 12:39:16 PM PST 24
Peak memory 192720 kb
Host smart-1eaeb2d3-ade8-4f2a-a275-9b3cfc4d94cb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235003713 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_
timer_same_csr_outstanding.235003713
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.1072767004
Short name T413
Test name
Test status
Simulation time 354937891 ps
CPU time 1.23 seconds
Started Mar 05 12:38:59 PM PST 24
Finished Mar 05 12:39:00 PM PST 24
Peak memory 195992 kb
Host smart-96077f2f-829d-41de-b0a8-857db05bfdce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072767004 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.1072767004
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.2099918240
Short name T95
Test name
Test status
Simulation time 8547092438 ps
CPU time 4.59 seconds
Started Mar 05 12:39:06 PM PST 24
Finished Mar 05 12:39:16 PM PST 24
Peak memory 197140 kb
Host smart-cf2df3ee-c7b6-4ca9-8291-d6b48247075f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099918240 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl
_intg_err.2099918240
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.497058122
Short name T354
Test name
Test status
Simulation time 556614322 ps
CPU time 0.93 seconds
Started Mar 05 12:39:05 PM PST 24
Finished Mar 05 12:39:14 PM PST 24
Peak memory 195488 kb
Host smart-75696715-d0b9-47b9-ae14-f0fd45c26a54
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497058122 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.497058122
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.3781932581
Short name T70
Test name
Test status
Simulation time 407414671 ps
CPU time 0.75 seconds
Started Mar 05 12:39:10 PM PST 24
Finished Mar 05 12:39:11 PM PST 24
Peak memory 182984 kb
Host smart-078b23b1-1e09-4bbf-b700-9d188a279b85
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781932581 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.3781932581
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.2291759575
Short name T357
Test name
Test status
Simulation time 342753663 ps
CPU time 0.83 seconds
Started Mar 05 12:39:15 PM PST 24
Finished Mar 05 12:39:16 PM PST 24
Peak memory 182932 kb
Host smart-7858b40e-52c4-4605-ae0c-3a5d765e8ce6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291759575 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.2291759575
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.2088130722
Short name T74
Test name
Test status
Simulation time 2629519431 ps
CPU time 1.59 seconds
Started Mar 05 12:38:59 PM PST 24
Finished Mar 05 12:39:01 PM PST 24
Peak memory 193576 kb
Host smart-6ff212aa-8d85-4058-a9b6-125337981243
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088130722 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon
_timer_same_csr_outstanding.2088130722
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.2840741738
Short name T305
Test name
Test status
Simulation time 306930496 ps
CPU time 1.91 seconds
Started Mar 05 12:38:52 PM PST 24
Finished Mar 05 12:38:54 PM PST 24
Peak memory 197768 kb
Host smart-e50fa12a-32f8-4127-a3a0-5099ea4e2f89
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840741738 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.2840741738
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.1204013584
Short name T31
Test name
Test status
Simulation time 4794228653 ps
CPU time 3.35 seconds
Started Mar 05 12:39:11 PM PST 24
Finished Mar 05 12:39:15 PM PST 24
Peak memory 196332 kb
Host smart-f5cdb11f-09b9-49d7-b526-de4c5615154c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204013584 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl
_intg_err.1204013584
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.3179774668
Short name T349
Test name
Test status
Simulation time 404167916 ps
CPU time 0.9 seconds
Started Mar 05 12:38:50 PM PST 24
Finished Mar 05 12:38:51 PM PST 24
Peak memory 197068 kb
Host smart-7441367b-344a-42e6-a798-c24654a11d30
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179774668 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.3179774668
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.616251733
Short name T323
Test name
Test status
Simulation time 330219349 ps
CPU time 1.16 seconds
Started Mar 05 12:39:05 PM PST 24
Finished Mar 05 12:39:09 PM PST 24
Peak memory 182768 kb
Host smart-599d028d-1a2e-4496-abbe-5962984da771
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616251733 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.616251733
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.1690646734
Short name T375
Test name
Test status
Simulation time 335515024 ps
CPU time 1.02 seconds
Started Mar 05 12:39:26 PM PST 24
Finished Mar 05 12:39:27 PM PST 24
Peak memory 182736 kb
Host smart-6dc5feaa-621d-4137-9715-28fd60879fe3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690646734 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.1690646734
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.2908731543
Short name T324
Test name
Test status
Simulation time 1869409895 ps
CPU time 1.64 seconds
Started Mar 05 12:39:06 PM PST 24
Finished Mar 05 12:39:08 PM PST 24
Peak memory 182956 kb
Host smart-5b1871e8-0556-4664-b33b-2c77ac2a7b6a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908731543 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon
_timer_same_csr_outstanding.2908731543
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.158731329
Short name T301
Test name
Test status
Simulation time 446976463 ps
CPU time 1.95 seconds
Started Mar 05 12:38:59 PM PST 24
Finished Mar 05 12:39:01 PM PST 24
Peak memory 197736 kb
Host smart-f0d27989-241f-4b0c-ae77-ad72ba766000
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158731329 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.158731329
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.3384494143
Short name T30
Test name
Test status
Simulation time 4629044529 ps
CPU time 4.47 seconds
Started Mar 05 12:39:17 PM PST 24
Finished Mar 05 12:39:21 PM PST 24
Peak memory 196744 kb
Host smart-17a6ccec-7e13-4b07-a843-3c6cea2d56ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384494143 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl
_intg_err.3384494143
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.1344720286
Short name T326
Test name
Test status
Simulation time 381191316 ps
CPU time 0.97 seconds
Started Mar 05 12:39:03 PM PST 24
Finished Mar 05 12:39:04 PM PST 24
Peak memory 195120 kb
Host smart-5d15b1a8-048c-4099-9186-ad49a9fb8f58
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344720286 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.1344720286
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.4173434886
Short name T414
Test name
Test status
Simulation time 471339788 ps
CPU time 1.35 seconds
Started Mar 05 12:39:16 PM PST 24
Finished Mar 05 12:39:18 PM PST 24
Peak memory 182948 kb
Host smart-cdf50957-b8b2-493d-9d00-3e07ce22c3c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173434886 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.4173434886
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.4000549012
Short name T292
Test name
Test status
Simulation time 315890768 ps
CPU time 1.01 seconds
Started Mar 05 12:39:00 PM PST 24
Finished Mar 05 12:39:02 PM PST 24
Peak memory 182796 kb
Host smart-7aacfc93-9409-4af0-a6cc-6e96ba9d68aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000549012 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.4000549012
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.3182427247
Short name T75
Test name
Test status
Simulation time 2855367306 ps
CPU time 3.55 seconds
Started Mar 05 12:39:01 PM PST 24
Finished Mar 05 12:39:05 PM PST 24
Peak memory 183048 kb
Host smart-e46e65f1-19ba-4577-b260-95c194e56230
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182427247 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon
_timer_same_csr_outstanding.3182427247
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.2516433878
Short name T396
Test name
Test status
Simulation time 472213885 ps
CPU time 1.42 seconds
Started Mar 05 12:39:08 PM PST 24
Finished Mar 05 12:39:10 PM PST 24
Peak memory 197484 kb
Host smart-c49e8d09-d09a-41b0-ad98-b84fd20491b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516433878 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.2516433878
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.1740474146
Short name T97
Test name
Test status
Simulation time 8171820994 ps
CPU time 4.72 seconds
Started Mar 05 12:39:00 PM PST 24
Finished Mar 05 12:39:05 PM PST 24
Peak memory 197116 kb
Host smart-463ee755-4ed9-4a25-bda3-4c93ba5c2041
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740474146 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl
_intg_err.1740474146
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.2190618876
Short name T407
Test name
Test status
Simulation time 428724258 ps
CPU time 1.27 seconds
Started Mar 05 12:39:22 PM PST 24
Finished Mar 05 12:39:23 PM PST 24
Peak memory 194228 kb
Host smart-c51f4c48-f986-4aaf-a54b-2b18fc403aaa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190618876 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.2190618876
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.2952447360
Short name T297
Test name
Test status
Simulation time 555433654 ps
CPU time 0.6 seconds
Started Mar 05 12:39:11 PM PST 24
Finished Mar 05 12:39:11 PM PST 24
Peak memory 182880 kb
Host smart-76e22fc8-1f21-4994-a622-1d2aa8ed430f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952447360 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.2952447360
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.1300725811
Short name T288
Test name
Test status
Simulation time 302365191 ps
CPU time 0.78 seconds
Started Mar 05 12:39:22 PM PST 24
Finished Mar 05 12:39:23 PM PST 24
Peak memory 182852 kb
Host smart-c2d58ea4-284a-4dbb-b912-6d7bc2b303ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300725811 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.1300725811
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.852117204
Short name T365
Test name
Test status
Simulation time 1494489083 ps
CPU time 0.98 seconds
Started Mar 05 12:39:37 PM PST 24
Finished Mar 05 12:39:38 PM PST 24
Peak memory 192596 kb
Host smart-aa763dd4-9c64-4d82-8e97-2e2af2ba75f0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852117204 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_
timer_same_csr_outstanding.852117204
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.3893382864
Short name T352
Test name
Test status
Simulation time 380543325 ps
CPU time 2.42 seconds
Started Mar 05 12:38:59 PM PST 24
Finished Mar 05 12:39:01 PM PST 24
Peak memory 197824 kb
Host smart-3b5d4321-e291-49a3-bdfd-e02c0975d996
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893382864 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.3893382864
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.3627137600
Short name T401
Test name
Test status
Simulation time 4534904687 ps
CPU time 2.64 seconds
Started Mar 05 12:39:02 PM PST 24
Finished Mar 05 12:39:05 PM PST 24
Peak memory 196636 kb
Host smart-1afb3732-87da-45aa-a822-027a56bef7d8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627137600 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl
_intg_err.3627137600
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_jump.1955562530
Short name T134
Test name
Test status
Simulation time 483838394 ps
CPU time 0.71 seconds
Started Mar 05 12:40:09 PM PST 24
Finished Mar 05 12:40:10 PM PST 24
Peak memory 183840 kb
Host smart-50980a91-c571-46f3-acd6-e4c0e21ec2d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955562530 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.1955562530
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.519999080
Short name T209
Test name
Test status
Simulation time 37346768225 ps
CPU time 27 seconds
Started Mar 05 12:40:07 PM PST 24
Finished Mar 05 12:40:35 PM PST 24
Peak memory 183964 kb
Host smart-dec47917-b4f8-4a90-a823-0191ec4daca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519999080 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.519999080
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.223565289
Short name T171
Test name
Test status
Simulation time 415148952 ps
CPU time 1.13 seconds
Started Mar 05 12:40:17 PM PST 24
Finished Mar 05 12:40:19 PM PST 24
Peak memory 183840 kb
Host smart-180271d4-8c86-413f-95c6-2a1caf3e4516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223565289 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.223565289
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.3602985011
Short name T216
Test name
Test status
Simulation time 290491220451 ps
CPU time 467.79 seconds
Started Mar 05 12:40:15 PM PST 24
Finished Mar 05 12:48:03 PM PST 24
Peak memory 198760 kb
Host smart-60a8c99c-d46c-4b40-be8d-a9672cf3b296
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602985011 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.3602985011
Directory /workspace/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.aon_timer_jump.2803099236
Short name T273
Test name
Test status
Simulation time 459296022 ps
CPU time 0.63 seconds
Started Mar 05 12:40:03 PM PST 24
Finished Mar 05 12:40:04 PM PST 24
Peak memory 183780 kb
Host smart-f5cab64d-8759-4ec9-a91d-3d4f5a7c8c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803099236 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.2803099236
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.555113754
Short name T173
Test name
Test status
Simulation time 46627298056 ps
CPU time 14.82 seconds
Started Mar 05 12:40:20 PM PST 24
Finished Mar 05 12:40:35 PM PST 24
Peak memory 183960 kb
Host smart-2c784c14-b00b-45ea-b48a-193f0bdb5fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555113754 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.555113754
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.1357677668
Short name T16
Test name
Test status
Simulation time 9041677665 ps
CPU time 2.46 seconds
Started Mar 05 12:39:58 PM PST 24
Finished Mar 05 12:40:01 PM PST 24
Peak memory 215724 kb
Host smart-942c3468-16b1-4cb2-9d8c-5fadbed00a64
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357677668 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.1357677668
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.1061233696
Short name T107
Test name
Test status
Simulation time 439042801 ps
CPU time 0.79 seconds
Started Mar 05 12:40:08 PM PST 24
Finished Mar 05 12:40:09 PM PST 24
Peak memory 183836 kb
Host smart-03166c80-8b20-460e-8678-0765384167b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061233696 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.1061233696
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.2417370930
Short name T147
Test name
Test status
Simulation time 333812063800 ps
CPU time 218.44 seconds
Started Mar 05 12:40:03 PM PST 24
Finished Mar 05 12:43:41 PM PST 24
Peak memory 183960 kb
Host smart-007f0066-3539-4f5c-890a-9ffe2eb7acb8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417370930 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_a
ll.2417370930
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.1084413709
Short name T38
Test name
Test status
Simulation time 486136785145 ps
CPU time 963.58 seconds
Started Mar 05 12:40:06 PM PST 24
Finished Mar 05 12:56:10 PM PST 24
Peak memory 204280 kb
Host smart-bce04dc0-6b13-4f89-a55d-0bc2a3fa8bd2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084413709 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.1084413709
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.aon_timer_jump.4080561717
Short name T242
Test name
Test status
Simulation time 598948752 ps
CPU time 0.71 seconds
Started Mar 05 12:40:32 PM PST 24
Finished Mar 05 12:40:33 PM PST 24
Peak memory 183852 kb
Host smart-685e91f5-69b4-4e6a-b255-12401ac08223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080561717 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.4080561717
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.2685813862
Short name T45
Test name
Test status
Simulation time 9760826751 ps
CPU time 14.74 seconds
Started Mar 05 12:40:14 PM PST 24
Finished Mar 05 12:40:29 PM PST 24
Peak memory 192196 kb
Host smart-cf1799cd-140a-4dfa-8816-7c76b55784fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685813862 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.2685813862
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.1650037664
Short name T227
Test name
Test status
Simulation time 578810465 ps
CPU time 1.02 seconds
Started Mar 05 12:40:17 PM PST 24
Finished Mar 05 12:40:19 PM PST 24
Peak memory 183952 kb
Host smart-28449f61-0c85-450b-8daf-f7f197775d90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650037664 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.1650037664
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.1599711794
Short name T239
Test name
Test status
Simulation time 153243805853 ps
CPU time 13.32 seconds
Started Mar 05 12:40:29 PM PST 24
Finished Mar 05 12:40:44 PM PST 24
Peak memory 183972 kb
Host smart-647c53ba-c323-48f5-ba24-e806a0e5f627
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599711794 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_
all.1599711794
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.2900621486
Short name T129
Test name
Test status
Simulation time 57745967653 ps
CPU time 321.81 seconds
Started Mar 05 12:40:29 PM PST 24
Finished Mar 05 12:45:52 PM PST 24
Peak memory 198908 kb
Host smart-c7142bb9-2a16-4183-88e6-46b71df4a4f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900621486 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.2900621486
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.aon_timer_jump.4074837656
Short name T23
Test name
Test status
Simulation time 594891348 ps
CPU time 0.73 seconds
Started Mar 05 12:40:34 PM PST 24
Finished Mar 05 12:40:35 PM PST 24
Peak memory 183852 kb
Host smart-871517bc-5d2e-423d-8918-873252ebaf1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074837656 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.4074837656
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.543210264
Short name T199
Test name
Test status
Simulation time 1961638550 ps
CPU time 0.87 seconds
Started Mar 05 12:40:22 PM PST 24
Finished Mar 05 12:40:23 PM PST 24
Peak memory 183852 kb
Host smart-8c76f2e6-279f-470d-8872-8a3a52253eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543210264 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.543210264
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.2122737640
Short name T254
Test name
Test status
Simulation time 490762057 ps
CPU time 0.93 seconds
Started Mar 05 12:40:29 PM PST 24
Finished Mar 05 12:40:31 PM PST 24
Peak memory 183856 kb
Host smart-075aabef-bcd8-4e26-8ed3-a64f03151b6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122737640 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.2122737640
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.287068695
Short name T141
Test name
Test status
Simulation time 209508279244 ps
CPU time 278.14 seconds
Started Mar 05 12:40:17 PM PST 24
Finished Mar 05 12:44:56 PM PST 24
Peak memory 195596 kb
Host smart-4b6084b3-3411-4653-9338-5b1dea9b1f76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287068695 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_a
ll.287068695
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.761081263
Short name T83
Test name
Test status
Simulation time 13856825672 ps
CPU time 95.5 seconds
Started Mar 05 12:40:20 PM PST 24
Finished Mar 05 12:41:55 PM PST 24
Peak memory 198800 kb
Host smart-97402670-91df-4089-93ca-fd6e60a360a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761081263 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand_reset.761081263
Directory /workspace/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.aon_timer_jump.3239911327
Short name T208
Test name
Test status
Simulation time 594220167 ps
CPU time 1.52 seconds
Started Mar 05 12:40:30 PM PST 24
Finished Mar 05 12:40:33 PM PST 24
Peak memory 183852 kb
Host smart-bc282bbb-91a8-46ac-bfd1-98cab2c7545f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239911327 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.3239911327
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.231343490
Short name T138
Test name
Test status
Simulation time 34748854856 ps
CPU time 51.06 seconds
Started Mar 05 12:40:29 PM PST 24
Finished Mar 05 12:41:21 PM PST 24
Peak memory 183952 kb
Host smart-292dcb87-adff-46ff-8b56-243209c67471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231343490 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.231343490
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.1520882111
Short name T189
Test name
Test status
Simulation time 594307377 ps
CPU time 1.06 seconds
Started Mar 05 12:40:14 PM PST 24
Finished Mar 05 12:40:15 PM PST 24
Peak memory 183844 kb
Host smart-2ff7d01a-aeb0-4c4e-9541-bdaebb83e543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520882111 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.1520882111
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.1803502640
Short name T183
Test name
Test status
Simulation time 128141131629 ps
CPU time 42.42 seconds
Started Mar 05 12:40:38 PM PST 24
Finished Mar 05 12:41:21 PM PST 24
Peak memory 195496 kb
Host smart-54be9d0b-88a6-46fe-84f9-6b41e428f9c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803502640 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_
all.1803502640
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.884457152
Short name T24
Test name
Test status
Simulation time 951722179439 ps
CPU time 425.25 seconds
Started Mar 05 12:40:26 PM PST 24
Finished Mar 05 12:47:33 PM PST 24
Peak memory 198792 kb
Host smart-14714d3d-d846-463b-a576-96df2f13a8c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884457152 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.884457152
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_jump.449227789
Short name T252
Test name
Test status
Simulation time 334544241 ps
CPU time 1.08 seconds
Started Mar 05 12:40:26 PM PST 24
Finished Mar 05 12:40:28 PM PST 24
Peak memory 183856 kb
Host smart-4a13b30c-23d6-4cab-a1c8-347d60ac39fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449227789 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.449227789
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.285899079
Short name T91
Test name
Test status
Simulation time 32546844296 ps
CPU time 49.04 seconds
Started Mar 05 12:40:20 PM PST 24
Finished Mar 05 12:41:09 PM PST 24
Peak memory 183952 kb
Host smart-041c977b-02d1-4e25-a562-1767ae968012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285899079 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.285899079
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.3617720030
Short name T229
Test name
Test status
Simulation time 455008711 ps
CPU time 0.73 seconds
Started Mar 05 12:40:43 PM PST 24
Finished Mar 05 12:40:44 PM PST 24
Peak memory 183844 kb
Host smart-a5a78b31-5b60-4d3d-821e-1f3e9701e844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617720030 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.3617720030
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.496654296
Short name T201
Test name
Test status
Simulation time 101281101496 ps
CPU time 165.46 seconds
Started Mar 05 12:40:13 PM PST 24
Finished Mar 05 12:42:59 PM PST 24
Peak memory 183964 kb
Host smart-8cd1eb19-a39c-48e1-9856-6eda569df8c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496654296 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_a
ll.496654296
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.3462589213
Short name T124
Test name
Test status
Simulation time 19527315926 ps
CPU time 83.92 seconds
Started Mar 05 12:40:30 PM PST 24
Finished Mar 05 12:41:55 PM PST 24
Peak memory 198804 kb
Host smart-bfd0dff4-d1f6-441f-aab5-675648689b95
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462589213 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.3462589213
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.aon_timer_jump.3215151082
Short name T5
Test name
Test status
Simulation time 441404277 ps
CPU time 0.81 seconds
Started Mar 05 12:40:32 PM PST 24
Finished Mar 05 12:40:33 PM PST 24
Peak memory 183852 kb
Host smart-131b96ef-9e00-4701-87bd-410884bd8296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215151082 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.3215151082
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.2035915071
Short name T6
Test name
Test status
Simulation time 55603685874 ps
CPU time 82.53 seconds
Started Mar 05 12:40:23 PM PST 24
Finished Mar 05 12:41:46 PM PST 24
Peak memory 183976 kb
Host smart-1cd33c83-1350-489e-8557-a0061c1ec9cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035915071 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.2035915071
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.645152438
Short name T100
Test name
Test status
Simulation time 463046369 ps
CPU time 0.75 seconds
Started Mar 05 12:40:29 PM PST 24
Finished Mar 05 12:40:31 PM PST 24
Peak memory 183932 kb
Host smart-b450aa36-7784-49af-9925-fc07ffe96cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645152438 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.645152438
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.3443788260
Short name T161
Test name
Test status
Simulation time 131834473074 ps
CPU time 195.21 seconds
Started Mar 05 12:40:57 PM PST 24
Finished Mar 05 12:44:12 PM PST 24
Peak memory 183948 kb
Host smart-a1b59756-b393-4a21-8bad-17e5bd70c9b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443788260 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_
all.3443788260
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.3413084120
Short name T80
Test name
Test status
Simulation time 64022852992 ps
CPU time 533.03 seconds
Started Mar 05 12:40:26 PM PST 24
Finished Mar 05 12:49:20 PM PST 24
Peak memory 198828 kb
Host smart-3ec66840-c1fe-4297-bdcb-4b5ec2a9d5c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413084120 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.3413084120
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.aon_timer_jump.928839515
Short name T191
Test name
Test status
Simulation time 622216619 ps
CPU time 1.19 seconds
Started Mar 05 12:40:43 PM PST 24
Finished Mar 05 12:40:44 PM PST 24
Peak memory 183816 kb
Host smart-8bb8f7a6-2d77-4f60-b13f-f6d6ed7bda43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928839515 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.928839515
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.1195864182
Short name T122
Test name
Test status
Simulation time 7998952007 ps
CPU time 12.69 seconds
Started Mar 05 12:40:29 PM PST 24
Finished Mar 05 12:40:42 PM PST 24
Peak memory 183892 kb
Host smart-73b2d5ee-dd01-4f97-a8cd-f86cd6f0526a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195864182 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.1195864182
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.1618033800
Short name T22
Test name
Test status
Simulation time 543351602 ps
CPU time 0.73 seconds
Started Mar 05 12:40:35 PM PST 24
Finished Mar 05 12:40:36 PM PST 24
Peak memory 183844 kb
Host smart-27507ed2-f744-4ff3-beca-e21fac1d993c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618033800 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.1618033800
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.713230522
Short name T40
Test name
Test status
Simulation time 10531609819 ps
CPU time 16.89 seconds
Started Mar 05 12:40:22 PM PST 24
Finished Mar 05 12:40:39 PM PST 24
Peak memory 194400 kb
Host smart-05934384-5bab-4558-bffd-467b93cd5c2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713230522 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_a
ll.713230522
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_jump.2893291175
Short name T62
Test name
Test status
Simulation time 519676605 ps
CPU time 0.8 seconds
Started Mar 05 12:40:36 PM PST 24
Finished Mar 05 12:40:37 PM PST 24
Peak memory 183936 kb
Host smart-f9a67d33-6c78-49f4-ae2d-9e85ac301ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893291175 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.2893291175
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.3539120968
Short name T9
Test name
Test status
Simulation time 19256846550 ps
CPU time 7.78 seconds
Started Mar 05 12:40:38 PM PST 24
Finished Mar 05 12:40:46 PM PST 24
Peak memory 183944 kb
Host smart-7f655eb4-d5a8-4ebc-a819-5ad6ebbf5f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539120968 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.3539120968
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.3783239160
Short name T234
Test name
Test status
Simulation time 616809836 ps
CPU time 1.59 seconds
Started Mar 05 12:40:32 PM PST 24
Finished Mar 05 12:40:34 PM PST 24
Peak memory 183844 kb
Host smart-118a268f-eed0-4cee-8dc7-56d1afaabe8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783239160 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.3783239160
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.1849567407
Short name T18
Test name
Test status
Simulation time 63307512227 ps
CPU time 21.06 seconds
Started Mar 05 12:40:35 PM PST 24
Finished Mar 05 12:40:56 PM PST 24
Peak memory 183976 kb
Host smart-feda1dc6-d5f1-4447-aafb-7045ca7d7a5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849567407 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_
all.1849567407
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.2403857095
Short name T86
Test name
Test status
Simulation time 78668030315 ps
CPU time 571.86 seconds
Started Mar 05 12:40:30 PM PST 24
Finished Mar 05 12:50:08 PM PST 24
Peak memory 198968 kb
Host smart-5038aca3-1818-44a9-a757-81239c9c7ff7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403857095 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.2403857095
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.aon_timer_jump.1586446636
Short name T233
Test name
Test status
Simulation time 470162714 ps
CPU time 0.75 seconds
Started Mar 05 12:40:31 PM PST 24
Finished Mar 05 12:40:32 PM PST 24
Peak memory 183852 kb
Host smart-9d4d283b-810c-4869-bb87-aa54141e0ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586446636 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.1586446636
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.472999489
Short name T250
Test name
Test status
Simulation time 15737193058 ps
CPU time 25.34 seconds
Started Mar 05 12:40:53 PM PST 24
Finished Mar 05 12:41:19 PM PST 24
Peak memory 192176 kb
Host smart-6cbea63b-369d-4197-8019-8584badb3400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472999489 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.472999489
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.216451814
Short name T240
Test name
Test status
Simulation time 465812412 ps
CPU time 0.65 seconds
Started Mar 05 12:40:26 PM PST 24
Finished Mar 05 12:40:26 PM PST 24
Peak memory 183936 kb
Host smart-784c5494-f8e3-44e6-960c-2d357c04d6b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216451814 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.216451814
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.1021557255
Short name T219
Test name
Test status
Simulation time 153194161830 ps
CPU time 251.49 seconds
Started Mar 05 12:40:33 PM PST 24
Finished Mar 05 12:44:46 PM PST 24
Peak memory 183976 kb
Host smart-92bb02dd-ff4a-4422-a88f-c0df3749303f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021557255 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_
all.1021557255
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.4284163347
Short name T270
Test name
Test status
Simulation time 25781630067 ps
CPU time 99.3 seconds
Started Mar 05 12:40:26 PM PST 24
Finished Mar 05 12:42:06 PM PST 24
Peak memory 198832 kb
Host smart-425f89ee-0954-4e07-a194-7409d4989f7e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284163347 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.4284163347
Directory /workspace/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.aon_timer_jump.4211744523
Short name T282
Test name
Test status
Simulation time 388092987 ps
CPU time 0.71 seconds
Started Mar 05 12:40:27 PM PST 24
Finished Mar 05 12:40:29 PM PST 24
Peak memory 183932 kb
Host smart-52d0ed28-1376-4f94-aa50-60a3f3fcb6ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211744523 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.4211744523
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.2363795962
Short name T231
Test name
Test status
Simulation time 35647794532 ps
CPU time 22.44 seconds
Started Mar 05 12:40:29 PM PST 24
Finished Mar 05 12:40:53 PM PST 24
Peak memory 184052 kb
Host smart-b98d1cd8-95fb-4209-a812-c7480497eb71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363795962 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.2363795962
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.4226728245
Short name T154
Test name
Test status
Simulation time 481065982 ps
CPU time 1.25 seconds
Started Mar 05 12:40:43 PM PST 24
Finished Mar 05 12:40:44 PM PST 24
Peak memory 183848 kb
Host smart-4da70054-84a4-4506-be68-d97493808c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226728245 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.4226728245
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.1161796582
Short name T42
Test name
Test status
Simulation time 297228183206 ps
CPU time 114.74 seconds
Started Mar 05 12:40:28 PM PST 24
Finished Mar 05 12:42:24 PM PST 24
Peak memory 183892 kb
Host smart-83a6f046-dbe8-43cb-8dc4-5bf887ed99b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161796582 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_
all.1161796582
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.3271056463
Short name T143
Test name
Test status
Simulation time 666365764026 ps
CPU time 701.16 seconds
Started Mar 05 12:40:23 PM PST 24
Finished Mar 05 12:52:05 PM PST 24
Peak memory 201816 kb
Host smart-604afc1f-8c1f-48ae-a88a-badb2c06865c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271056463 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.3271056463
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.aon_timer_jump.1308514402
Short name T151
Test name
Test status
Simulation time 547172440 ps
CPU time 0.65 seconds
Started Mar 05 12:40:45 PM PST 24
Finished Mar 05 12:40:52 PM PST 24
Peak memory 183848 kb
Host smart-aca3aa1a-08a5-4d1c-a215-298d1feb3fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308514402 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.1308514402
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.1059420628
Short name T152
Test name
Test status
Simulation time 12193656152 ps
CPU time 16.17 seconds
Started Mar 05 12:40:54 PM PST 24
Finished Mar 05 12:41:10 PM PST 24
Peak memory 183960 kb
Host smart-5a32bb55-c692-4129-be3f-5f4ead0e266b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059420628 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.1059420628
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.1709466925
Short name T44
Test name
Test status
Simulation time 637199747 ps
CPU time 0.71 seconds
Started Mar 05 12:40:30 PM PST 24
Finished Mar 05 12:40:32 PM PST 24
Peak memory 183780 kb
Host smart-a61ac929-d849-49db-9ade-369ed4da00f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709466925 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.1709466925
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.3354086193
Short name T132
Test name
Test status
Simulation time 282996103795 ps
CPU time 197.72 seconds
Started Mar 05 12:40:42 PM PST 24
Finished Mar 05 12:44:04 PM PST 24
Peak memory 195264 kb
Host smart-017cbaf1-5875-4c4c-b7a5-6c610e22ed17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354086193 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_
all.3354086193
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.2060783731
Short name T276
Test name
Test status
Simulation time 224673855681 ps
CPU time 421.12 seconds
Started Mar 05 12:40:42 PM PST 24
Finished Mar 05 12:47:47 PM PST 24
Peak memory 198792 kb
Host smart-e98e1527-b00a-49b8-aa56-574c7481af0b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060783731 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.2060783731
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_jump.1768623504
Short name T109
Test name
Test status
Simulation time 529244963 ps
CPU time 1.28 seconds
Started Mar 05 12:40:14 PM PST 24
Finished Mar 05 12:40:15 PM PST 24
Peak memory 183832 kb
Host smart-d73c0621-be6e-498e-a737-b63d311da54b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768623504 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.1768623504
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.2402728604
Short name T128
Test name
Test status
Simulation time 31729503078 ps
CPU time 24.3 seconds
Started Mar 05 12:40:06 PM PST 24
Finished Mar 05 12:40:31 PM PST 24
Peak memory 183952 kb
Host smart-58158e85-2516-4203-bcc4-50adbc79fb5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402728604 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.2402728604
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.1060245975
Short name T14
Test name
Test status
Simulation time 8043096631 ps
CPU time 3.69 seconds
Started Mar 05 12:40:08 PM PST 24
Finished Mar 05 12:40:12 PM PST 24
Peak memory 215976 kb
Host smart-b90410f3-0cda-4b08-8d35-6f334f1f1e20
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060245975 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.1060245975
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.3013820188
Short name T172
Test name
Test status
Simulation time 518620586 ps
CPU time 0.59 seconds
Started Mar 05 12:40:15 PM PST 24
Finished Mar 05 12:40:16 PM PST 24
Peak memory 183832 kb
Host smart-b3115866-f3f5-4bb5-a4b9-12cf5bd677b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013820188 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.3013820188
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.1929563610
Short name T278
Test name
Test status
Simulation time 39666398277 ps
CPU time 180.57 seconds
Started Mar 05 12:40:09 PM PST 24
Finished Mar 05 12:43:10 PM PST 24
Peak memory 198724 kb
Host smart-763ae5b6-5164-4f70-aa5d-f58236bd40a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929563610 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.1929563610
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.aon_timer_jump.1659244859
Short name T220
Test name
Test status
Simulation time 567372693 ps
CPU time 0.75 seconds
Started Mar 05 12:40:32 PM PST 24
Finished Mar 05 12:40:33 PM PST 24
Peak memory 183852 kb
Host smart-4ba16f10-9a0f-477d-b925-957cb5859e0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659244859 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.1659244859
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.3144602930
Short name T155
Test name
Test status
Simulation time 30856977813 ps
CPU time 8.88 seconds
Started Mar 05 12:40:51 PM PST 24
Finished Mar 05 12:41:00 PM PST 24
Peak memory 192136 kb
Host smart-f27082ce-a701-409f-be34-7cd101a01e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144602930 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.3144602930
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.500281799
Short name T104
Test name
Test status
Simulation time 623246082 ps
CPU time 0.68 seconds
Started Mar 05 12:40:40 PM PST 24
Finished Mar 05 12:40:41 PM PST 24
Peak memory 183852 kb
Host smart-18d835c4-5936-43ab-8b8f-55edbd969cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500281799 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.500281799
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.73565213
Short name T192
Test name
Test status
Simulation time 109493134338 ps
CPU time 153.46 seconds
Started Mar 05 12:40:32 PM PST 24
Finished Mar 05 12:43:06 PM PST 24
Peak memory 183972 kb
Host smart-454fa38a-2023-45c4-aeb7-72af5ad69063
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73565213 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_al
l.73565213
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.3676957323
Short name T181
Test name
Test status
Simulation time 109747631691 ps
CPU time 459.36 seconds
Started Mar 05 12:40:28 PM PST 24
Finished Mar 05 12:48:09 PM PST 24
Peak memory 198772 kb
Host smart-e148190b-67cc-4db9-9591-72ab3a8f1756
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676957323 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.3676957323
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_jump.1094032348
Short name T120
Test name
Test status
Simulation time 517117674 ps
CPU time 1.3 seconds
Started Mar 05 12:40:39 PM PST 24
Finished Mar 05 12:40:41 PM PST 24
Peak memory 183852 kb
Host smart-029b2ee6-2ea5-4669-9c3f-0b40487cf803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094032348 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.1094032348
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.450908507
Short name T20
Test name
Test status
Simulation time 16559066621 ps
CPU time 11.5 seconds
Started Mar 05 12:40:39 PM PST 24
Finished Mar 05 12:40:51 PM PST 24
Peak memory 183932 kb
Host smart-fcd3a225-911b-481b-a164-e7afca597f2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450908507 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.450908507
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.4088695330
Short name T114
Test name
Test status
Simulation time 522817868 ps
CPU time 1.3 seconds
Started Mar 05 12:40:35 PM PST 24
Finished Mar 05 12:40:37 PM PST 24
Peak memory 183848 kb
Host smart-76189e37-4a60-4d18-acf6-b41b3e1200e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088695330 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.4088695330
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.13773904
Short name T272
Test name
Test status
Simulation time 114534492370 ps
CPU time 48.14 seconds
Started Mar 05 12:40:37 PM PST 24
Finished Mar 05 12:41:26 PM PST 24
Peak memory 194764 kb
Host smart-07baeee0-400f-4b7b-9394-9c74aab0db95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13773904 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_al
l.13773904
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_jump.1348773973
Short name T66
Test name
Test status
Simulation time 458704109 ps
CPU time 1.2 seconds
Started Mar 05 12:40:40 PM PST 24
Finished Mar 05 12:40:47 PM PST 24
Peak memory 183852 kb
Host smart-47e61cfc-60ea-4594-ba97-038888a01160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348773973 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.1348773973
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.1243597211
Short name T261
Test name
Test status
Simulation time 17381409102 ps
CPU time 30.04 seconds
Started Mar 05 12:40:40 PM PST 24
Finished Mar 05 12:41:11 PM PST 24
Peak memory 183956 kb
Host smart-817b4004-fdec-4b11-bdb4-b6ca9aca4060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243597211 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.1243597211
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.1590198571
Short name T142
Test name
Test status
Simulation time 474403195 ps
CPU time 0.61 seconds
Started Mar 05 12:40:35 PM PST 24
Finished Mar 05 12:40:36 PM PST 24
Peak memory 183848 kb
Host smart-b345dd94-a7fe-4d1d-a5db-9445ea8d90b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590198571 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.1590198571
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.2079266485
Short name T148
Test name
Test status
Simulation time 173715640773 ps
CPU time 144.7 seconds
Started Mar 05 12:40:40 PM PST 24
Finished Mar 05 12:43:05 PM PST 24
Peak memory 183916 kb
Host smart-09ec4845-58d0-40ad-b737-a45bd42cc02d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079266485 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_
all.2079266485
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.957037082
Short name T11
Test name
Test status
Simulation time 97826502681 ps
CPU time 417.83 seconds
Started Mar 05 12:40:52 PM PST 24
Finished Mar 05 12:47:50 PM PST 24
Peak memory 198868 kb
Host smart-e15b401f-9eed-47ac-91dc-817198a4a8f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957037082 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.957037082
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.aon_timer_jump.2820062473
Short name T257
Test name
Test status
Simulation time 506709192 ps
CPU time 1.35 seconds
Started Mar 05 12:40:45 PM PST 24
Finished Mar 05 12:40:47 PM PST 24
Peak memory 183848 kb
Host smart-6b568423-4a10-4103-96cb-6aa41d9bdf59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820062473 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.2820062473
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.1233537393
Short name T139
Test name
Test status
Simulation time 7599289541 ps
CPU time 12.28 seconds
Started Mar 05 12:40:52 PM PST 24
Finished Mar 05 12:41:05 PM PST 24
Peak memory 183964 kb
Host smart-44ed4a1c-fb7d-4aaf-badd-e25ce99f27a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233537393 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.1233537393
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.2548804722
Short name T162
Test name
Test status
Simulation time 397430853 ps
CPU time 0.7 seconds
Started Mar 05 12:40:38 PM PST 24
Finished Mar 05 12:40:39 PM PST 24
Peak memory 183848 kb
Host smart-96e0e02f-10a3-4f2b-ad50-98f6b4fd07f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548804722 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.2548804722
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.867535888
Short name T144
Test name
Test status
Simulation time 269585105711 ps
CPU time 93.72 seconds
Started Mar 05 12:40:30 PM PST 24
Finished Mar 05 12:42:05 PM PST 24
Peak memory 194368 kb
Host smart-f806f28b-420e-4b5f-b536-e9982a3ae97c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867535888 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_a
ll.867535888
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_jump.2272219846
Short name T176
Test name
Test status
Simulation time 547413962 ps
CPU time 0.77 seconds
Started Mar 05 12:40:55 PM PST 24
Finished Mar 05 12:40:56 PM PST 24
Peak memory 183924 kb
Host smart-001f24d0-cd3c-4b8e-92c4-a2d72a9d6c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272219846 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.2272219846
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.4123166035
Short name T194
Test name
Test status
Simulation time 39777902383 ps
CPU time 12.5 seconds
Started Mar 05 12:40:47 PM PST 24
Finished Mar 05 12:41:00 PM PST 24
Peak memory 192120 kb
Host smart-37f3cffc-810d-4a8f-90b0-fa79063f1a1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123166035 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.4123166035
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.580388626
Short name T241
Test name
Test status
Simulation time 469372569 ps
CPU time 0.7 seconds
Started Mar 05 12:40:40 PM PST 24
Finished Mar 05 12:40:41 PM PST 24
Peak memory 183948 kb
Host smart-eb8f424d-12d9-4675-9b17-63c33d25db6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580388626 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.580388626
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.1700528496
Short name T169
Test name
Test status
Simulation time 167779901351 ps
CPU time 229.43 seconds
Started Mar 05 12:40:29 PM PST 24
Finished Mar 05 12:44:20 PM PST 24
Peak memory 183920 kb
Host smart-de618c1a-02e1-444c-84bd-e0df99edae31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700528496 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_
all.1700528496
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.1945884766
Short name T246
Test name
Test status
Simulation time 577100216573 ps
CPU time 258.01 seconds
Started Mar 05 12:40:29 PM PST 24
Finished Mar 05 12:44:49 PM PST 24
Peak memory 206944 kb
Host smart-83e6c231-8713-45c2-be75-8b24b1d719f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945884766 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand_reset.1945884766
Directory /workspace/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.aon_timer_jump.4136317099
Short name T177
Test name
Test status
Simulation time 409991890 ps
CPU time 1.18 seconds
Started Mar 05 12:40:52 PM PST 24
Finished Mar 05 12:40:54 PM PST 24
Peak memory 183928 kb
Host smart-9a0e15cb-973b-492e-9d7b-4ff8b77d34fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136317099 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.4136317099
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.174502783
Short name T116
Test name
Test status
Simulation time 49030985713 ps
CPU time 71.92 seconds
Started Mar 05 12:40:39 PM PST 24
Finished Mar 05 12:41:52 PM PST 24
Peak memory 192152 kb
Host smart-8430e5d9-7fe6-4f51-9423-6f2cf8eda516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174502783 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.174502783
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.148785869
Short name T202
Test name
Test status
Simulation time 545437808 ps
CPU time 1.34 seconds
Started Mar 05 12:40:44 PM PST 24
Finished Mar 05 12:40:46 PM PST 24
Peak memory 183928 kb
Host smart-3de9e236-f193-4f9f-bf43-adad78403318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148785869 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.148785869
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.1397538487
Short name T197
Test name
Test status
Simulation time 382393096339 ps
CPU time 318.19 seconds
Started Mar 05 12:40:43 PM PST 24
Finished Mar 05 12:46:01 PM PST 24
Peak memory 194308 kb
Host smart-c88892cf-8245-4b9b-82f8-08c18a1d4308
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397538487 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_
all.1397538487
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.3305805488
Short name T39
Test name
Test status
Simulation time 139565994586 ps
CPU time 580.07 seconds
Started Mar 05 12:40:42 PM PST 24
Finished Mar 05 12:50:22 PM PST 24
Peak memory 199368 kb
Host smart-5b37106f-3409-4d70-81a9-92931de53b5a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305805488 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.3305805488
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.aon_timer_jump.155603625
Short name T41
Test name
Test status
Simulation time 587918231 ps
CPU time 0.97 seconds
Started Mar 05 12:40:44 PM PST 24
Finished Mar 05 12:40:45 PM PST 24
Peak memory 183920 kb
Host smart-1981ee64-d045-43d9-962f-bb2632aa7de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155603625 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.155603625
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.4122011171
Short name T264
Test name
Test status
Simulation time 40450727216 ps
CPU time 12.19 seconds
Started Mar 05 12:40:52 PM PST 24
Finished Mar 05 12:41:05 PM PST 24
Peak memory 183856 kb
Host smart-058d1b06-7691-496c-9c14-ffd42d3d0fe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122011171 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.4122011171
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.3887210051
Short name T27
Test name
Test status
Simulation time 569103667 ps
CPU time 0.73 seconds
Started Mar 05 12:40:34 PM PST 24
Finished Mar 05 12:40:36 PM PST 24
Peak memory 183744 kb
Host smart-e4b4e948-946f-4dae-b296-709647db7191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887210051 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.3887210051
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.1187755494
Short name T119
Test name
Test status
Simulation time 55124598798 ps
CPU time 41.76 seconds
Started Mar 05 12:40:17 PM PST 24
Finished Mar 05 12:41:00 PM PST 24
Peak memory 192056 kb
Host smart-8ac7c0e7-0f29-48fa-9377-315b085d2900
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187755494 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_
all.1187755494
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.2353516200
Short name T78
Test name
Test status
Simulation time 203202396077 ps
CPU time 509.6 seconds
Started Mar 05 12:40:46 PM PST 24
Finished Mar 05 12:49:16 PM PST 24
Peak memory 199252 kb
Host smart-fde7cfd3-af7f-48c9-b05a-2d86493c58b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353516200 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.2353516200
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_jump.1696228034
Short name T203
Test name
Test status
Simulation time 493655682 ps
CPU time 0.95 seconds
Started Mar 05 12:40:36 PM PST 24
Finished Mar 05 12:40:38 PM PST 24
Peak memory 183808 kb
Host smart-ac829d72-70f7-4393-a812-3263a986acdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696228034 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.1696228034
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.2205766786
Short name T258
Test name
Test status
Simulation time 9493073528 ps
CPU time 4.51 seconds
Started Mar 05 12:40:45 PM PST 24
Finished Mar 05 12:40:50 PM PST 24
Peak memory 183956 kb
Host smart-55afd551-61c9-4ceb-8166-f22d8ad01866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205766786 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.2205766786
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.498151758
Short name T236
Test name
Test status
Simulation time 588248411 ps
CPU time 0.75 seconds
Started Mar 05 12:40:57 PM PST 24
Finished Mar 05 12:40:58 PM PST 24
Peak memory 183748 kb
Host smart-e921f14c-d198-4e44-b003-01c1d440a184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498151758 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.498151758
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.1927754176
Short name T60
Test name
Test status
Simulation time 113475578983 ps
CPU time 21.73 seconds
Started Mar 05 12:40:28 PM PST 24
Finished Mar 05 12:40:51 PM PST 24
Peak memory 195180 kb
Host smart-7cfc4d33-2113-4c68-b695-c699a1f6bf61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927754176 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_
all.1927754176
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.3755872397
Short name T81
Test name
Test status
Simulation time 154973423543 ps
CPU time 566.73 seconds
Started Mar 05 12:40:30 PM PST 24
Finished Mar 05 12:49:58 PM PST 24
Peak memory 198936 kb
Host smart-937edb84-ccde-4c43-8819-f076731da55a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755872397 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.3755872397
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_jump.2971734069
Short name T106
Test name
Test status
Simulation time 550396642 ps
CPU time 0.72 seconds
Started Mar 05 12:40:45 PM PST 24
Finished Mar 05 12:40:45 PM PST 24
Peak memory 183824 kb
Host smart-a654ad86-728a-47e4-ab44-20db56169472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971734069 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.2971734069
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.1221075667
Short name T184
Test name
Test status
Simulation time 28532076776 ps
CPU time 8.01 seconds
Started Mar 05 12:40:37 PM PST 24
Finished Mar 05 12:40:45 PM PST 24
Peak memory 184040 kb
Host smart-5d80b7d7-cb72-4dd9-b7a8-8c360819df19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221075667 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.1221075667
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.3912562240
Short name T102
Test name
Test status
Simulation time 513689522 ps
CPU time 0.97 seconds
Started Mar 05 12:40:33 PM PST 24
Finished Mar 05 12:40:34 PM PST 24
Peak memory 183848 kb
Host smart-12b898a2-2d27-4cc8-b88f-e4b8e758e472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912562240 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.3912562240
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.556321348
Short name T271
Test name
Test status
Simulation time 335832773257 ps
CPU time 268.91 seconds
Started Mar 05 12:40:33 PM PST 24
Finished Mar 05 12:45:02 PM PST 24
Peak memory 183996 kb
Host smart-d7271fdd-9a0d-405a-9038-9e1508be9314
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556321348 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_a
ll.556321348
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.989696206
Short name T277
Test name
Test status
Simulation time 246470989320 ps
CPU time 411.28 seconds
Started Mar 05 12:40:23 PM PST 24
Finished Mar 05 12:47:15 PM PST 24
Peak memory 198792 kb
Host smart-e6625bed-981e-4d14-a7b7-b620110c8abd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989696206 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.989696206
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.aon_timer_jump.2106321697
Short name T170
Test name
Test status
Simulation time 526902516 ps
CPU time 1.36 seconds
Started Mar 05 12:40:25 PM PST 24
Finished Mar 05 12:40:26 PM PST 24
Peak memory 183860 kb
Host smart-2440784b-76f0-4bff-adf8-029f0c359c9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106321697 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.2106321697
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.332244597
Short name T146
Test name
Test status
Simulation time 14439572140 ps
CPU time 24.78 seconds
Started Mar 05 12:40:29 PM PST 24
Finished Mar 05 12:40:56 PM PST 24
Peak memory 184040 kb
Host smart-f0e561dd-553f-49e6-83a2-2503e0013627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332244597 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.332244597
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.1911612854
Short name T103
Test name
Test status
Simulation time 551487344 ps
CPU time 0.67 seconds
Started Mar 05 12:40:32 PM PST 24
Finished Mar 05 12:40:33 PM PST 24
Peak memory 183844 kb
Host smart-829a415f-ae39-4e12-8bc5-03804cbca6be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911612854 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.1911612854
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.1391984637
Short name T174
Test name
Test status
Simulation time 140496341871 ps
CPU time 107.53 seconds
Started Mar 05 12:40:22 PM PST 24
Finished Mar 05 12:42:10 PM PST 24
Peak memory 194684 kb
Host smart-94baad72-be1f-4323-9e97-171ef2de7048
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391984637 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_
all.1391984637
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_jump.54255447
Short name T228
Test name
Test status
Simulation time 529289893 ps
CPU time 0.61 seconds
Started Mar 05 12:40:11 PM PST 24
Finished Mar 05 12:40:11 PM PST 24
Peak memory 183836 kb
Host smart-b46a9848-5d50-489a-b9a6-38f74ac58d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54255447 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.54255447
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.2054752634
Short name T179
Test name
Test status
Simulation time 28809935387 ps
CPU time 11.52 seconds
Started Mar 05 12:40:27 PM PST 24
Finished Mar 05 12:40:40 PM PST 24
Peak memory 183948 kb
Host smart-e6115df6-935c-4698-83ce-07f0851b53f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054752634 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.2054752634
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.1066917737
Short name T13
Test name
Test status
Simulation time 8111202062 ps
CPU time 4.18 seconds
Started Mar 05 12:40:22 PM PST 24
Finished Mar 05 12:40:26 PM PST 24
Peak memory 215652 kb
Host smart-fa7a4629-3fe8-4f02-9111-910479d9f266
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066917737 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.1066917737
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.2673285154
Short name T204
Test name
Test status
Simulation time 554662061 ps
CPU time 1.05 seconds
Started Mar 05 12:40:14 PM PST 24
Finished Mar 05 12:40:15 PM PST 24
Peak memory 183920 kb
Host smart-f0239e23-b3e1-4e01-b741-85a835010188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673285154 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.2673285154
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.4006286269
Short name T230
Test name
Test status
Simulation time 44164901655 ps
CPU time 35.97 seconds
Started Mar 05 12:40:08 PM PST 24
Finished Mar 05 12:40:44 PM PST 24
Peak memory 183884 kb
Host smart-96df292d-8cd4-483c-98ba-bc16764677e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006286269 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_a
ll.4006286269
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.4233817090
Short name T221
Test name
Test status
Simulation time 89559284015 ps
CPU time 245.06 seconds
Started Mar 05 12:40:05 PM PST 24
Finished Mar 05 12:44:10 PM PST 24
Peak memory 198840 kb
Host smart-59179894-ea4c-4712-93be-570ec3c4d646
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233817090 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.4233817090
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_jump.3464872974
Short name T188
Test name
Test status
Simulation time 533931575 ps
CPU time 1.21 seconds
Started Mar 05 12:40:32 PM PST 24
Finished Mar 05 12:40:33 PM PST 24
Peak memory 183932 kb
Host smart-75797761-fa6c-43d8-a952-29740dde5c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464872974 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.3464872974
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.4172262292
Short name T211
Test name
Test status
Simulation time 39666201493 ps
CPU time 14.21 seconds
Started Mar 05 12:40:40 PM PST 24
Finished Mar 05 12:40:55 PM PST 24
Peak memory 183960 kb
Host smart-84febf3a-a711-4f68-819c-6182791e5775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172262292 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.4172262292
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.3668127087
Short name T193
Test name
Test status
Simulation time 570658439 ps
CPU time 1.4 seconds
Started Mar 05 12:40:40 PM PST 24
Finished Mar 05 12:40:42 PM PST 24
Peak memory 183788 kb
Host smart-08dc8a7c-d5c5-48a7-a27b-7a04d983a18e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668127087 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.3668127087
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.2599116282
Short name T43
Test name
Test status
Simulation time 36517323031 ps
CPU time 14.62 seconds
Started Mar 05 12:40:29 PM PST 24
Finished Mar 05 12:40:45 PM PST 24
Peak memory 195600 kb
Host smart-306653ee-74c0-4334-919a-64bb2bbf4dbf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599116282 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_
all.2599116282
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.1713226173
Short name T84
Test name
Test status
Simulation time 53462024122 ps
CPU time 418.76 seconds
Started Mar 05 12:40:39 PM PST 24
Finished Mar 05 12:47:39 PM PST 24
Peak memory 198776 kb
Host smart-7441493f-e53b-4f06-be0b-dc36c3d6dfec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713226173 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.1713226173
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.aon_timer_jump.945780630
Short name T281
Test name
Test status
Simulation time 602926562 ps
CPU time 1.02 seconds
Started Mar 05 12:40:50 PM PST 24
Finished Mar 05 12:40:52 PM PST 24
Peak memory 183836 kb
Host smart-7ced3efb-eee5-4e77-a042-8e58e749c779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945780630 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.945780630
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.616786006
Short name T26
Test name
Test status
Simulation time 35719500177 ps
CPU time 11.03 seconds
Started Mar 05 12:40:29 PM PST 24
Finished Mar 05 12:40:42 PM PST 24
Peak memory 183896 kb
Host smart-e217d6c8-f729-46c4-a92d-7fd8b8287163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616786006 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.616786006
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.3489187782
Short name T156
Test name
Test status
Simulation time 339384158 ps
CPU time 0.77 seconds
Started Mar 05 12:40:37 PM PST 24
Finished Mar 05 12:40:38 PM PST 24
Peak memory 183856 kb
Host smart-96a90845-dd27-4e99-8892-63540833ad1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489187782 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.3489187782
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.4170941765
Short name T185
Test name
Test status
Simulation time 339943334690 ps
CPU time 478.61 seconds
Started Mar 05 12:40:29 PM PST 24
Finished Mar 05 12:48:28 PM PST 24
Peak memory 184040 kb
Host smart-563ce7dc-8ad5-4be9-bf46-016b8007fdc7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170941765 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_
all.4170941765
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.1497968848
Short name T79
Test name
Test status
Simulation time 83864473589 ps
CPU time 164.67 seconds
Started Mar 05 12:40:40 PM PST 24
Finished Mar 05 12:43:25 PM PST 24
Peak memory 198756 kb
Host smart-ecf33713-3481-445c-9a5c-66a11df640ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497968848 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.1497968848
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.aon_timer_jump.2931603218
Short name T164
Test name
Test status
Simulation time 378079519 ps
CPU time 1.19 seconds
Started Mar 05 12:40:35 PM PST 24
Finished Mar 05 12:40:36 PM PST 24
Peak memory 183792 kb
Host smart-91a1cdbc-4f4b-4189-a71e-2d19adb76ca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931603218 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.2931603218
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.853783848
Short name T244
Test name
Test status
Simulation time 32409073253 ps
CPU time 43.4 seconds
Started Mar 05 12:40:29 PM PST 24
Finished Mar 05 12:41:14 PM PST 24
Peak memory 183952 kb
Host smart-0fbd1821-84ff-4bfb-b4bb-8cbbc3e637e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853783848 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.853783848
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.602818488
Short name T115
Test name
Test status
Simulation time 509008713 ps
CPU time 1.24 seconds
Started Mar 05 12:40:27 PM PST 24
Finished Mar 05 12:40:30 PM PST 24
Peak memory 183860 kb
Host smart-ebabc1e2-0a37-48a8-924f-c70561363eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602818488 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.602818488
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.2874906671
Short name T200
Test name
Test status
Simulation time 101270025088 ps
CPU time 27.46 seconds
Started Mar 05 12:40:30 PM PST 24
Finished Mar 05 12:40:59 PM PST 24
Peak memory 183960 kb
Host smart-e7c53b21-2ace-4317-9f7b-056d2f584765
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874906671 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_
all.2874906671
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.4059928182
Short name T214
Test name
Test status
Simulation time 278129173602 ps
CPU time 506.61 seconds
Started Mar 05 12:40:34 PM PST 24
Finished Mar 05 12:49:01 PM PST 24
Peak memory 198840 kb
Host smart-4ed1a73e-1be0-4321-b412-c08cf5ec3953
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059928182 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_reset.4059928182
Directory /workspace/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.aon_timer_jump.1598279380
Short name T131
Test name
Test status
Simulation time 494989725 ps
CPU time 0.75 seconds
Started Mar 05 12:40:32 PM PST 24
Finished Mar 05 12:40:33 PM PST 24
Peak memory 183872 kb
Host smart-dedd0829-432c-44f1-b20f-39ba97957722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598279380 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.1598279380
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.3799688066
Short name T163
Test name
Test status
Simulation time 477700671 ps
CPU time 0.91 seconds
Started Mar 05 12:40:28 PM PST 24
Finished Mar 05 12:40:30 PM PST 24
Peak memory 183852 kb
Host smart-ddf2a1ed-1393-4cdb-890c-f1107d71c843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799688066 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.3799688066
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.2740117342
Short name T111
Test name
Test status
Simulation time 511410152 ps
CPU time 1.03 seconds
Started Mar 05 12:40:32 PM PST 24
Finished Mar 05 12:40:33 PM PST 24
Peak memory 183852 kb
Host smart-d319efe0-1b0b-4f50-a346-779193cd6cc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740117342 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.2740117342
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.2297476353
Short name T29
Test name
Test status
Simulation time 53961526673 ps
CPU time 19.92 seconds
Started Mar 05 12:40:32 PM PST 24
Finished Mar 05 12:40:52 PM PST 24
Peak memory 183960 kb
Host smart-b9f5c9cc-e98b-4339-9bf7-acd5d95527e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297476353 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_
all.2297476353
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.1935708800
Short name T237
Test name
Test status
Simulation time 11907844379 ps
CPU time 93.71 seconds
Started Mar 05 12:40:22 PM PST 24
Finished Mar 05 12:41:56 PM PST 24
Peak memory 198788 kb
Host smart-ef54d6da-d251-414d-9ced-855116b43248
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935708800 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.1935708800
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.aon_timer_jump.94760610
Short name T140
Test name
Test status
Simulation time 336576999 ps
CPU time 1.08 seconds
Started Mar 05 12:40:28 PM PST 24
Finished Mar 05 12:40:31 PM PST 24
Peak memory 183840 kb
Host smart-d0d47866-2c21-49dd-8d7d-3f236ac828c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94760610 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.94760610
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.2560926393
Short name T205
Test name
Test status
Simulation time 37129003642 ps
CPU time 14.04 seconds
Started Mar 05 12:40:26 PM PST 24
Finished Mar 05 12:40:41 PM PST 24
Peak memory 183968 kb
Host smart-95107d39-94da-4a42-ab8c-54b0ab6180c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560926393 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.2560926393
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.488154287
Short name T269
Test name
Test status
Simulation time 511083286 ps
CPU time 0.89 seconds
Started Mar 05 12:40:27 PM PST 24
Finished Mar 05 12:40:30 PM PST 24
Peak memory 183852 kb
Host smart-b07fbc69-ce00-460e-a34a-22f0f00a750b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488154287 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.488154287
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.1198385255
Short name T256
Test name
Test status
Simulation time 218188548393 ps
CPU time 345.46 seconds
Started Mar 05 12:40:22 PM PST 24
Finished Mar 05 12:46:07 PM PST 24
Peak memory 193588 kb
Host smart-49ddae01-12f3-4714-909d-0f6f32752317
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198385255 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_
all.1198385255
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.1386301974
Short name T82
Test name
Test status
Simulation time 28884849873 ps
CPU time 196.4 seconds
Started Mar 05 12:40:42 PM PST 24
Finished Mar 05 12:43:59 PM PST 24
Peak memory 198804 kb
Host smart-61a3676e-45b0-438e-9522-023713732df0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386301974 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.1386301974
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.aon_timer_jump.3780548549
Short name T238
Test name
Test status
Simulation time 473109104 ps
CPU time 0.73 seconds
Started Mar 05 12:40:17 PM PST 24
Finished Mar 05 12:40:18 PM PST 24
Peak memory 183824 kb
Host smart-a207537b-a04f-4047-992e-37e193cd8a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780548549 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.3780548549
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.1996871872
Short name T178
Test name
Test status
Simulation time 32585596121 ps
CPU time 22.18 seconds
Started Mar 05 12:40:46 PM PST 24
Finished Mar 05 12:41:09 PM PST 24
Peak memory 183956 kb
Host smart-70eeca26-c882-4695-8713-6f9859423023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996871872 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.1996871872
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.814545518
Short name T224
Test name
Test status
Simulation time 418605578 ps
CPU time 0.67 seconds
Started Mar 05 12:40:48 PM PST 24
Finished Mar 05 12:40:49 PM PST 24
Peak memory 183832 kb
Host smart-b18c8209-60aa-4d02-83e4-e609b0dee9c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814545518 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.814545518
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.2587007315
Short name T248
Test name
Test status
Simulation time 375607044407 ps
CPU time 44.23 seconds
Started Mar 05 12:40:30 PM PST 24
Finished Mar 05 12:41:15 PM PST 24
Peak memory 183932 kb
Host smart-3cd5a770-78b4-47b4-a7d1-6dcfad622a06
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587007315 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_
all.2587007315
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_jump.3132320007
Short name T235
Test name
Test status
Simulation time 379774645 ps
CPU time 1.18 seconds
Started Mar 05 12:40:32 PM PST 24
Finished Mar 05 12:40:34 PM PST 24
Peak memory 183792 kb
Host smart-36c5ee32-cfd3-48bf-943f-5c7801315e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132320007 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.3132320007
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.3033425026
Short name T218
Test name
Test status
Simulation time 33216469302 ps
CPU time 16.79 seconds
Started Mar 05 12:40:42 PM PST 24
Finished Mar 05 12:41:03 PM PST 24
Peak memory 192180 kb
Host smart-02a50abf-6787-4109-a05a-4d5808b3364f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033425026 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.3033425026
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.1974388158
Short name T260
Test name
Test status
Simulation time 372020011 ps
CPU time 0.82 seconds
Started Mar 05 12:40:48 PM PST 24
Finished Mar 05 12:40:49 PM PST 24
Peak memory 183848 kb
Host smart-10f987a9-defa-4b79-be68-f0e6488eb2ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974388158 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.1974388158
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.1877304116
Short name T175
Test name
Test status
Simulation time 135607489035 ps
CPU time 57.26 seconds
Started Mar 05 12:40:39 PM PST 24
Finished Mar 05 12:41:37 PM PST 24
Peak memory 192140 kb
Host smart-40f1fe85-13a4-494a-b017-17d11c8f7d26
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877304116 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_
all.1877304116
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.2058103849
Short name T36
Test name
Test status
Simulation time 92661800784 ps
CPU time 739.35 seconds
Started Mar 05 12:40:33 PM PST 24
Finished Mar 05 12:52:53 PM PST 24
Peak memory 201360 kb
Host smart-e40980f3-d4c2-4924-8320-184adc9b930f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058103849 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.2058103849
Directory /workspace/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.aon_timer_jump.4285614537
Short name T167
Test name
Test status
Simulation time 440874536 ps
CPU time 1.18 seconds
Started Mar 05 12:40:27 PM PST 24
Finished Mar 05 12:40:29 PM PST 24
Peak memory 183872 kb
Host smart-1b8cdaa5-423a-4559-bbc5-e8ef2aa9f548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285614537 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.4285614537
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.2094714421
Short name T157
Test name
Test status
Simulation time 25187142762 ps
CPU time 9.05 seconds
Started Mar 05 12:40:35 PM PST 24
Finished Mar 05 12:40:44 PM PST 24
Peak memory 192092 kb
Host smart-711a1646-52f7-4039-8684-16eeaaa70699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094714421 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.2094714421
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.4178694762
Short name T145
Test name
Test status
Simulation time 423661384 ps
CPU time 0.6 seconds
Started Mar 05 12:40:20 PM PST 24
Finished Mar 05 12:40:21 PM PST 24
Peak memory 183828 kb
Host smart-ce2b640c-4ebd-4caf-b97e-6490c764da2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178694762 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.4178694762
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.1633199873
Short name T118
Test name
Test status
Simulation time 236934126774 ps
CPU time 168.69 seconds
Started Mar 05 12:40:42 PM PST 24
Finished Mar 05 12:43:32 PM PST 24
Peak memory 194096 kb
Host smart-40f24f6b-54b1-4f99-a8d7-5fc944ea7a22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633199873 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_
all.1633199873
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.3272650780
Short name T117
Test name
Test status
Simulation time 124816089884 ps
CPU time 260.98 seconds
Started Mar 05 12:41:03 PM PST 24
Finished Mar 05 12:45:24 PM PST 24
Peak memory 198820 kb
Host smart-0959fec2-2d14-4659-a8c1-26aa19cd02bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272650780 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.3272650780
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.aon_timer_jump.1430712578
Short name T65
Test name
Test status
Simulation time 383786109 ps
CPU time 0.72 seconds
Started Mar 05 12:40:26 PM PST 24
Finished Mar 05 12:40:28 PM PST 24
Peak memory 183932 kb
Host smart-c4f89420-317e-4723-9bfb-71644642e6a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430712578 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.1430712578
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.2782667669
Short name T207
Test name
Test status
Simulation time 32826859476 ps
CPU time 5.67 seconds
Started Mar 05 12:40:45 PM PST 24
Finished Mar 05 12:40:50 PM PST 24
Peak memory 183960 kb
Host smart-9de959b8-8152-4bdf-a664-2223a1ee5367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782667669 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.2782667669
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.335105646
Short name T130
Test name
Test status
Simulation time 473815922 ps
CPU time 0.71 seconds
Started Mar 05 12:40:25 PM PST 24
Finished Mar 05 12:40:26 PM PST 24
Peak memory 183852 kb
Host smart-e0ba3244-40ea-44c1-a971-8ca65b8821e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335105646 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.335105646
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.3109946218
Short name T159
Test name
Test status
Simulation time 138843321822 ps
CPU time 60.23 seconds
Started Mar 05 12:40:32 PM PST 24
Finished Mar 05 12:41:33 PM PST 24
Peak memory 195264 kb
Host smart-73c08b9c-09dd-448f-8f9c-1e223ac35f24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109946218 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_
all.3109946218
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_jump.1117289010
Short name T190
Test name
Test status
Simulation time 516630532 ps
CPU time 1.37 seconds
Started Mar 05 12:40:22 PM PST 24
Finished Mar 05 12:40:23 PM PST 24
Peak memory 183848 kb
Host smart-c33be5a4-8086-4a68-952f-67638e47c730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117289010 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.1117289010
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.4181555936
Short name T89
Test name
Test status
Simulation time 18246019132 ps
CPU time 15.09 seconds
Started Mar 05 12:40:32 PM PST 24
Finished Mar 05 12:40:47 PM PST 24
Peak memory 183896 kb
Host smart-e7cd0da2-e7a8-4999-b660-d5db13800cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181555936 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.4181555936
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.2746102269
Short name T222
Test name
Test status
Simulation time 440131279 ps
CPU time 0.9 seconds
Started Mar 05 12:40:29 PM PST 24
Finished Mar 05 12:40:31 PM PST 24
Peak memory 183848 kb
Host smart-749c1b35-a17b-41b6-a471-ca9d1f8f479c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746102269 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.2746102269
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.827837694
Short name T125
Test name
Test status
Simulation time 115140775020 ps
CPU time 174.01 seconds
Started Mar 05 12:40:30 PM PST 24
Finished Mar 05 12:43:25 PM PST 24
Peak memory 184044 kb
Host smart-caaaa575-35e2-4a4c-b5f9-b9d15ff4de67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827837694 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_a
ll.827837694
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.1204099077
Short name T223
Test name
Test status
Simulation time 112243253656 ps
CPU time 478.34 seconds
Started Mar 05 12:40:31 PM PST 24
Finished Mar 05 12:48:30 PM PST 24
Peak memory 198840 kb
Host smart-8eb4d4d9-4c36-4582-8d75-95dd5c2e9383
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204099077 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.1204099077
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_jump.3568692216
Short name T198
Test name
Test status
Simulation time 504600436 ps
CPU time 0.7 seconds
Started Mar 05 12:40:11 PM PST 24
Finished Mar 05 12:40:12 PM PST 24
Peak memory 183848 kb
Host smart-14698cca-b4d4-4ba8-9369-b42728a6fbff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568692216 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.3568692216
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.3991736573
Short name T210
Test name
Test status
Simulation time 29353230727 ps
CPU time 49.89 seconds
Started Mar 05 12:40:11 PM PST 24
Finished Mar 05 12:41:01 PM PST 24
Peak memory 183884 kb
Host smart-512d1eb2-7773-469d-ac79-54c627fdd7da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991736573 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.3991736573
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.2102120380
Short name T17
Test name
Test status
Simulation time 8031084359 ps
CPU time 3.89 seconds
Started Mar 05 12:40:34 PM PST 24
Finished Mar 05 12:40:39 PM PST 24
Peak memory 216060 kb
Host smart-0cf6fbac-311b-4a97-9106-be235ad875d3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102120380 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.2102120380
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.3957261942
Short name T217
Test name
Test status
Simulation time 409991179 ps
CPU time 0.69 seconds
Started Mar 05 12:40:05 PM PST 24
Finished Mar 05 12:40:06 PM PST 24
Peak memory 183860 kb
Host smart-079cc99c-dcf0-42e2-8949-1a1dce5b9c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957261942 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.3957261942
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.965683395
Short name T245
Test name
Test status
Simulation time 21450372482 ps
CPU time 9.06 seconds
Started Mar 05 12:40:31 PM PST 24
Finished Mar 05 12:40:41 PM PST 24
Peak memory 195240 kb
Host smart-f4a4a85d-27a7-477d-8f0c-be3df9fbb33a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965683395 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_al
l.965683395
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.2346480062
Short name T46
Test name
Test status
Simulation time 128757445180 ps
CPU time 212.97 seconds
Started Mar 05 12:40:05 PM PST 24
Finished Mar 05 12:43:39 PM PST 24
Peak memory 198908 kb
Host smart-ec322e34-d21f-4b0b-a6e6-e029e655fde1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346480062 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.2346480062
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.aon_timer_jump.1556083395
Short name T247
Test name
Test status
Simulation time 535445197 ps
CPU time 1.03 seconds
Started Mar 05 12:40:20 PM PST 24
Finished Mar 05 12:40:27 PM PST 24
Peak memory 183848 kb
Host smart-76aca68f-a009-451c-857e-fe944893fd82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556083395 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.1556083395
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.31661062
Short name T212
Test name
Test status
Simulation time 5622088743 ps
CPU time 2.34 seconds
Started Mar 05 12:40:23 PM PST 24
Finished Mar 05 12:40:26 PM PST 24
Peak memory 183968 kb
Host smart-f22de765-78c1-4a60-b79e-ac9fd3697b13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31661062 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.31661062
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.3227579918
Short name T268
Test name
Test status
Simulation time 524417564 ps
CPU time 0.67 seconds
Started Mar 05 12:40:38 PM PST 24
Finished Mar 05 12:40:39 PM PST 24
Peak memory 183848 kb
Host smart-fbf2366a-6e14-4b9a-84ba-226180ebe59a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227579918 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.3227579918
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.2663489528
Short name T280
Test name
Test status
Simulation time 84361745855 ps
CPU time 24.29 seconds
Started Mar 05 12:40:29 PM PST 24
Finished Mar 05 12:40:55 PM PST 24
Peak memory 194644 kb
Host smart-c18b6d8f-16ea-4f1e-9d47-c1d764c9bb25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663489528 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_
all.2663489528
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.2332650542
Short name T19
Test name
Test status
Simulation time 63229975364 ps
CPU time 470.43 seconds
Started Mar 05 12:40:37 PM PST 24
Finished Mar 05 12:48:28 PM PST 24
Peak memory 198776 kb
Host smart-d18e0016-8267-4078-9cda-ca2c63612831
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332650542 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.2332650542
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.aon_timer_jump.1753961662
Short name T150
Test name
Test status
Simulation time 447020865 ps
CPU time 0.87 seconds
Started Mar 05 12:40:25 PM PST 24
Finished Mar 05 12:40:26 PM PST 24
Peak memory 183848 kb
Host smart-5e01278f-597d-44d6-9261-3d2eb6f625f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753961662 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.1753961662
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.2091135396
Short name T165
Test name
Test status
Simulation time 9085409031 ps
CPU time 13.96 seconds
Started Mar 05 12:40:35 PM PST 24
Finished Mar 05 12:40:50 PM PST 24
Peak memory 192156 kb
Host smart-9302650e-99b1-49e7-8484-dd0c0819cb9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091135396 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.2091135396
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.3121413096
Short name T215
Test name
Test status
Simulation time 345884402 ps
CPU time 0.84 seconds
Started Mar 05 12:40:28 PM PST 24
Finished Mar 05 12:40:30 PM PST 24
Peak memory 183844 kb
Host smart-bcbe3186-177e-441b-8c69-2b1685001596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121413096 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.3121413096
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.2913336843
Short name T243
Test name
Test status
Simulation time 52489131365 ps
CPU time 72.49 seconds
Started Mar 05 12:40:28 PM PST 24
Finished Mar 05 12:41:41 PM PST 24
Peak memory 194452 kb
Host smart-823ffd89-9ced-4695-8b75-0e04a5937e7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913336843 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_
all.2913336843
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.312211667
Short name T253
Test name
Test status
Simulation time 56849030695 ps
CPU time 589.72 seconds
Started Mar 05 12:40:42 PM PST 24
Finished Mar 05 12:50:33 PM PST 24
Peak memory 198724 kb
Host smart-e4a3bc39-0842-4ad4-85cc-4b78f66b21d0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312211667 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.312211667
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.aon_timer_jump.2659538586
Short name T225
Test name
Test status
Simulation time 556712524 ps
CPU time 1.32 seconds
Started Mar 05 12:40:37 PM PST 24
Finished Mar 05 12:40:38 PM PST 24
Peak memory 183780 kb
Host smart-8f00ae6d-c3d0-4fba-b010-2febbac7e035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659538586 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.2659538586
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.1932658174
Short name T196
Test name
Test status
Simulation time 11816857849 ps
CPU time 18.57 seconds
Started Mar 05 12:40:36 PM PST 24
Finished Mar 05 12:41:05 PM PST 24
Peak memory 183856 kb
Host smart-ba5cfe68-74cd-4dbd-8290-0bcaa79cf2d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932658174 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.1932658174
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.2857033092
Short name T186
Test name
Test status
Simulation time 463224721 ps
CPU time 0.73 seconds
Started Mar 05 12:40:28 PM PST 24
Finished Mar 05 12:40:30 PM PST 24
Peak memory 183928 kb
Host smart-3b8fde06-fee7-43a8-b2f3-f60348b97e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857033092 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.2857033092
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.2117889144
Short name T232
Test name
Test status
Simulation time 75643615997 ps
CPU time 28.32 seconds
Started Mar 05 12:40:42 PM PST 24
Finished Mar 05 12:41:11 PM PST 24
Peak memory 195664 kb
Host smart-bc619f4a-d999-4a6e-a59d-e25b55de0def
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117889144 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_
all.2117889144
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.3460021494
Short name T133
Test name
Test status
Simulation time 20724834967 ps
CPU time 209.78 seconds
Started Mar 05 12:40:43 PM PST 24
Finished Mar 05 12:44:13 PM PST 24
Peak memory 198856 kb
Host smart-d67a1567-e38d-41fc-87a0-db51937f0d2f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460021494 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.3460021494
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.aon_timer_jump.3561465099
Short name T262
Test name
Test status
Simulation time 500303355 ps
CPU time 0.74 seconds
Started Mar 05 12:40:29 PM PST 24
Finished Mar 05 12:40:31 PM PST 24
Peak memory 183820 kb
Host smart-bcab22c6-7112-484b-9fbd-bdbe3f58297d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561465099 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.3561465099
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.953716950
Short name T274
Test name
Test status
Simulation time 26086522337 ps
CPU time 43.61 seconds
Started Mar 05 12:40:28 PM PST 24
Finished Mar 05 12:41:13 PM PST 24
Peak memory 183912 kb
Host smart-96a5ff25-77e4-4ad9-8a57-f9dea8c8e41b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953716950 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.953716950
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.3162150743
Short name T158
Test name
Test status
Simulation time 546293510 ps
CPU time 1.29 seconds
Started Mar 05 12:40:26 PM PST 24
Finished Mar 05 12:40:28 PM PST 24
Peak memory 183800 kb
Host smart-2b50ca07-4e8e-4c9b-b35e-e1337e58e05d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162150743 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.3162150743
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_jump.2906848741
Short name T195
Test name
Test status
Simulation time 586057098 ps
CPU time 1.32 seconds
Started Mar 05 12:40:36 PM PST 24
Finished Mar 05 12:40:38 PM PST 24
Peak memory 183840 kb
Host smart-1f4108e1-d17b-47f0-bb2b-d4191b00d872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906848741 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.2906848741
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.992618712
Short name T3
Test name
Test status
Simulation time 47151728037 ps
CPU time 16.24 seconds
Started Mar 05 12:40:43 PM PST 24
Finished Mar 05 12:40:59 PM PST 24
Peak memory 192164 kb
Host smart-1213503a-8020-4b81-8ecd-2fef15246026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992618712 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.992618712
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.2312222225
Short name T166
Test name
Test status
Simulation time 574941878 ps
CPU time 0.96 seconds
Started Mar 05 12:40:31 PM PST 24
Finished Mar 05 12:40:33 PM PST 24
Peak memory 183800 kb
Host smart-53aae2de-8873-44fc-942f-a131d40887a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312222225 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.2312222225
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.2165050163
Short name T88
Test name
Test status
Simulation time 150474278775 ps
CPU time 124.8 seconds
Started Mar 05 12:40:36 PM PST 24
Finished Mar 05 12:42:41 PM PST 24
Peak memory 183932 kb
Host smart-6d275604-d126-4bf5-b18c-d021abe3085c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165050163 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_
all.2165050163
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_jump.3737478038
Short name T21
Test name
Test status
Simulation time 389664490 ps
CPU time 0.6 seconds
Started Mar 05 12:40:49 PM PST 24
Finished Mar 05 12:40:50 PM PST 24
Peak memory 183928 kb
Host smart-50773191-c9d7-416c-aa2b-5cf6ced3c6ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737478038 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.3737478038
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.1827695903
Short name T121
Test name
Test status
Simulation time 23241741978 ps
CPU time 36.76 seconds
Started Mar 05 12:40:27 PM PST 24
Finished Mar 05 12:41:04 PM PST 24
Peak memory 192144 kb
Host smart-7b8be60c-ccf6-49c1-82dd-cb80fc459900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827695903 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.1827695903
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.3379008928
Short name T105
Test name
Test status
Simulation time 502767120 ps
CPU time 1.22 seconds
Started Mar 05 12:40:27 PM PST 24
Finished Mar 05 12:40:30 PM PST 24
Peak memory 183832 kb
Host smart-fad75a3e-a676-4c53-bfc0-1bcdf26ebddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379008928 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.3379008928
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.1533889242
Short name T59
Test name
Test status
Simulation time 168622587838 ps
CPU time 61.44 seconds
Started Mar 05 12:40:52 PM PST 24
Finished Mar 05 12:41:54 PM PST 24
Peak memory 194528 kb
Host smart-5f9368d0-efa8-43fd-a9f4-f139d6509509
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533889242 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_
all.1533889242
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.730876647
Short name T87
Test name
Test status
Simulation time 116963596667 ps
CPU time 823.92 seconds
Started Mar 05 12:40:50 PM PST 24
Finished Mar 05 12:54:34 PM PST 24
Peak memory 202256 kb
Host smart-70c8b88e-ad40-47a2-924b-b80bffe6d3b6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730876647 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.730876647
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.aon_timer_jump.316188310
Short name T279
Test name
Test status
Simulation time 573964932 ps
CPU time 1.43 seconds
Started Mar 05 12:40:38 PM PST 24
Finished Mar 05 12:40:40 PM PST 24
Peak memory 183812 kb
Host smart-2a4c73e6-440c-4858-985f-cd10350c015b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316188310 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.316188310
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.2600815474
Short name T180
Test name
Test status
Simulation time 26108975781 ps
CPU time 20.21 seconds
Started Mar 05 12:40:32 PM PST 24
Finished Mar 05 12:40:53 PM PST 24
Peak memory 183968 kb
Host smart-f9ffd8d0-6926-4620-ae98-44f9ca3cc4d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600815474 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.2600815474
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.3569451153
Short name T63
Test name
Test status
Simulation time 349649271 ps
CPU time 1 seconds
Started Mar 05 12:40:38 PM PST 24
Finished Mar 05 12:40:40 PM PST 24
Peak memory 183824 kb
Host smart-42e16b5b-f267-4963-882c-42ca59bb9576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569451153 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.3569451153
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.3570837984
Short name T187
Test name
Test status
Simulation time 48941659616 ps
CPU time 6.81 seconds
Started Mar 05 12:40:38 PM PST 24
Finished Mar 05 12:40:45 PM PST 24
Peak memory 195312 kb
Host smart-a7bb2112-81e4-4f1b-92ef-8cf02beceda9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570837984 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_
all.3570837984
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.2847215382
Short name T85
Test name
Test status
Simulation time 169517107793 ps
CPU time 560.83 seconds
Started Mar 05 12:40:40 PM PST 24
Finished Mar 05 12:50:01 PM PST 24
Peak memory 198880 kb
Host smart-ff0ce87e-d2b3-4293-8f27-45a73c9fce61
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847215382 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.2847215382
Directory /workspace/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.aon_timer_jump.4122534458
Short name T61
Test name
Test status
Simulation time 415590090 ps
CPU time 0.66 seconds
Started Mar 05 12:40:44 PM PST 24
Finished Mar 05 12:40:44 PM PST 24
Peak memory 183852 kb
Host smart-890bd8c9-755c-4ed7-8795-82094bc21753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122534458 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.4122534458
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.3867232467
Short name T153
Test name
Test status
Simulation time 3622576124 ps
CPU time 6 seconds
Started Mar 05 12:40:43 PM PST 24
Finished Mar 05 12:40:49 PM PST 24
Peak memory 184076 kb
Host smart-ed31922e-7751-4a3a-b032-5b3edc4f885f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867232467 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.3867232467
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.247662138
Short name T101
Test name
Test status
Simulation time 561347494 ps
CPU time 1.3 seconds
Started Mar 05 12:40:58 PM PST 24
Finished Mar 05 12:40:59 PM PST 24
Peak memory 183964 kb
Host smart-cbf56390-df7c-49bf-8056-e824d82e0ce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247662138 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.247662138
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.3944066245
Short name T251
Test name
Test status
Simulation time 203325872487 ps
CPU time 22.21 seconds
Started Mar 05 12:40:50 PM PST 24
Finished Mar 05 12:41:12 PM PST 24
Peak memory 195936 kb
Host smart-ce641f12-eea0-48c8-ab36-bc91c065e750
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944066245 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_
all.3944066245
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.4238745625
Short name T275
Test name
Test status
Simulation time 26928353075 ps
CPU time 221.92 seconds
Started Mar 05 12:40:46 PM PST 24
Finished Mar 05 12:44:28 PM PST 24
Peak memory 198872 kb
Host smart-11fb27df-11c0-40b5-ad86-2f31cc6a9a14
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238745625 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.4238745625
Directory /workspace/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_jump.4162379652
Short name T64
Test name
Test status
Simulation time 569248169 ps
CPU time 1.43 seconds
Started Mar 05 12:40:46 PM PST 24
Finished Mar 05 12:40:48 PM PST 24
Peak memory 183840 kb
Host smart-ecb5dd4a-ccea-46f0-9204-699fa12bcc0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162379652 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.4162379652
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.434794498
Short name T136
Test name
Test status
Simulation time 29339296791 ps
CPU time 39.77 seconds
Started Mar 05 12:40:34 PM PST 24
Finished Mar 05 12:41:14 PM PST 24
Peak memory 192280 kb
Host smart-95dbab6b-9141-4077-9086-f1e654f61c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434794498 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.434794498
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.768584104
Short name T127
Test name
Test status
Simulation time 566615959 ps
CPU time 0.75 seconds
Started Mar 05 12:40:45 PM PST 24
Finished Mar 05 12:40:46 PM PST 24
Peak memory 183964 kb
Host smart-2c9ab2c2-6db3-47fc-afaa-f887760af65e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768584104 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.768584104
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.3321687356
Short name T10
Test name
Test status
Simulation time 74987576061 ps
CPU time 30.52 seconds
Started Mar 05 12:40:43 PM PST 24
Finished Mar 05 12:41:14 PM PST 24
Peak memory 192160 kb
Host smart-18950184-f30d-49f8-883c-db1a997757f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321687356 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_
all.3321687356
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.1349385519
Short name T112
Test name
Test status
Simulation time 67354587573 ps
CPU time 278.27 seconds
Started Mar 05 12:40:28 PM PST 24
Finished Mar 05 12:45:07 PM PST 24
Peak memory 198784 kb
Host smart-71190e26-1bf0-4f4b-91df-91401776c4e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349385519 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.1349385519
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.aon_timer_jump.1805203095
Short name T137
Test name
Test status
Simulation time 415081557 ps
CPU time 0.7 seconds
Started Mar 05 12:40:46 PM PST 24
Finished Mar 05 12:40:47 PM PST 24
Peak memory 183860 kb
Host smart-e78a2fd4-0aa5-4626-914e-7733f62d1ed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805203095 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.1805203095
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.1164271710
Short name T160
Test name
Test status
Simulation time 34662248321 ps
CPU time 54.25 seconds
Started Mar 05 12:40:26 PM PST 24
Finished Mar 05 12:41:21 PM PST 24
Peak memory 183944 kb
Host smart-387aa34a-0b2d-41c9-816b-de797b7caef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164271710 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.1164271710
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.1487466363
Short name T226
Test name
Test status
Simulation time 485411913 ps
CPU time 1.32 seconds
Started Mar 05 12:40:33 PM PST 24
Finished Mar 05 12:40:35 PM PST 24
Peak memory 183848 kb
Host smart-80a86518-4be9-4b92-8b07-ba9be8dcc7bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487466363 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.1487466363
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.1046311931
Short name T90
Test name
Test status
Simulation time 134609347302 ps
CPU time 213.21 seconds
Started Mar 05 12:40:39 PM PST 24
Finished Mar 05 12:44:13 PM PST 24
Peak memory 183956 kb
Host smart-d39d0fb5-f2bd-4306-a476-5faf8f896667
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046311931 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_
all.1046311931
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.1245313725
Short name T77
Test name
Test status
Simulation time 53720100643 ps
CPU time 113.98 seconds
Started Mar 05 12:40:46 PM PST 24
Finished Mar 05 12:42:40 PM PST 24
Peak memory 198772 kb
Host smart-469abea7-9612-4a4c-88af-0e94d5ce9998
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245313725 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.1245313725
Directory /workspace/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.aon_timer_jump.2919902431
Short name T213
Test name
Test status
Simulation time 474129422 ps
CPU time 1.26 seconds
Started Mar 05 12:40:54 PM PST 24
Finished Mar 05 12:40:56 PM PST 24
Peak memory 183812 kb
Host smart-b522e81e-e7e9-4503-b369-c243cad0e3e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919902431 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.2919902431
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.4077752566
Short name T110
Test name
Test status
Simulation time 25625983392 ps
CPU time 9.76 seconds
Started Mar 05 12:40:17 PM PST 24
Finished Mar 05 12:40:27 PM PST 24
Peak memory 183952 kb
Host smart-f7429eaa-c0fd-4056-9184-62cd667bfd59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077752566 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.4077752566
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.2485935588
Short name T267
Test name
Test status
Simulation time 544844123 ps
CPU time 0.63 seconds
Started Mar 05 12:40:20 PM PST 24
Finished Mar 05 12:40:21 PM PST 24
Peak memory 183836 kb
Host smart-0951f337-1d02-48e6-9c18-737c849f6507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485935588 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.2485935588
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.1928567388
Short name T108
Test name
Test status
Simulation time 359104987846 ps
CPU time 287.68 seconds
Started Mar 05 12:40:06 PM PST 24
Finished Mar 05 12:44:55 PM PST 24
Peak memory 195820 kb
Host smart-ab495f37-6daa-4e2b-8b03-0a405172d2bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928567388 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_a
ll.1928567388
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.3519394548
Short name T263
Test name
Test status
Simulation time 21721313743 ps
CPU time 234.35 seconds
Started Mar 05 12:40:24 PM PST 24
Finished Mar 05 12:44:18 PM PST 24
Peak memory 198844 kb
Host smart-7bc469e5-7765-4219-9a21-64b6d9a0543f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519394548 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.3519394548
Directory /workspace/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.aon_timer_jump.1819362641
Short name T259
Test name
Test status
Simulation time 564814060 ps
CPU time 0.86 seconds
Started Mar 05 12:40:19 PM PST 24
Finished Mar 05 12:40:21 PM PST 24
Peak memory 183808 kb
Host smart-f4e811bf-0ddc-49e5-9dcf-59abe012c118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819362641 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.1819362641
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.1338079729
Short name T168
Test name
Test status
Simulation time 30992104987 ps
CPU time 40.64 seconds
Started Mar 05 12:40:30 PM PST 24
Finished Mar 05 12:41:11 PM PST 24
Peak memory 184152 kb
Host smart-be3d9089-f75a-4851-9089-2efd0bce6500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338079729 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.1338079729
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.718134545
Short name T265
Test name
Test status
Simulation time 583448121 ps
CPU time 1.3 seconds
Started Mar 05 12:40:32 PM PST 24
Finished Mar 05 12:40:34 PM PST 24
Peak memory 183844 kb
Host smart-c9a72ca9-846b-49c8-bffc-6586fc517efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718134545 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.718134545
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.1436498207
Short name T67
Test name
Test status
Simulation time 66122916988 ps
CPU time 11.14 seconds
Started Mar 05 12:40:28 PM PST 24
Finished Mar 05 12:40:40 PM PST 24
Peak memory 183960 kb
Host smart-dfca0c2f-e067-409a-b82d-74cf3e8ea132
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436498207 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_a
ll.1436498207
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_jump.2680440713
Short name T2
Test name
Test status
Simulation time 434440253 ps
CPU time 1.12 seconds
Started Mar 05 12:40:35 PM PST 24
Finished Mar 05 12:40:36 PM PST 24
Peak memory 183840 kb
Host smart-e25eff82-e815-4512-b387-e835a1a92822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680440713 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.2680440713
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.1451497067
Short name T126
Test name
Test status
Simulation time 35727434844 ps
CPU time 13.29 seconds
Started Mar 05 12:40:24 PM PST 24
Finished Mar 05 12:40:37 PM PST 24
Peak memory 192152 kb
Host smart-ab6c40a7-6e70-4bfe-b7e9-9f7f9b710fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451497067 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.1451497067
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.1568239045
Short name T135
Test name
Test status
Simulation time 537065374 ps
CPU time 1.3 seconds
Started Mar 05 12:40:41 PM PST 24
Finished Mar 05 12:40:43 PM PST 24
Peak memory 183840 kb
Host smart-c0af34f5-e8d8-4c36-97a4-cb62fb4564f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568239045 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.1568239045
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.3737232672
Short name T1
Test name
Test status
Simulation time 279751386100 ps
CPU time 103.2 seconds
Started Mar 05 12:40:15 PM PST 24
Finished Mar 05 12:41:59 PM PST 24
Peak memory 194676 kb
Host smart-e824b085-5dec-4869-9802-66f116fea37a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737232672 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_a
ll.3737232672
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.3261270998
Short name T28
Test name
Test status
Simulation time 224840031649 ps
CPU time 632.31 seconds
Started Mar 05 12:40:34 PM PST 24
Finished Mar 05 12:51:07 PM PST 24
Peak memory 199532 kb
Host smart-29deaf98-b455-4671-97ff-86a64dae2525
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261270998 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.3261270998
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.aon_timer_jump.2718681639
Short name T206
Test name
Test status
Simulation time 610158217 ps
CPU time 1.02 seconds
Started Mar 05 12:40:38 PM PST 24
Finished Mar 05 12:40:39 PM PST 24
Peak memory 183840 kb
Host smart-914f4624-3585-412f-8662-5a560a933b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718681639 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.2718681639
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.1609167682
Short name T113
Test name
Test status
Simulation time 61759862246 ps
CPU time 18.8 seconds
Started Mar 05 12:40:22 PM PST 24
Finished Mar 05 12:40:41 PM PST 24
Peak memory 183948 kb
Host smart-e21866b4-b2a5-48fe-8464-ed24b4330c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609167682 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.1609167682
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.1454091187
Short name T249
Test name
Test status
Simulation time 567651602 ps
CPU time 1.47 seconds
Started Mar 05 12:40:31 PM PST 24
Finished Mar 05 12:40:33 PM PST 24
Peak memory 183808 kb
Host smart-497e858f-03dd-46e2-bd95-ab29a6eac155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454091187 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.1454091187
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.3246651403
Short name T255
Test name
Test status
Simulation time 111044625999 ps
CPU time 37.27 seconds
Started Mar 05 12:40:24 PM PST 24
Finished Mar 05 12:41:01 PM PST 24
Peak memory 194388 kb
Host smart-e67ab4b9-9547-4435-970d-3a92bc1e8929
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246651403 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_a
ll.3246651403
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.712304142
Short name T12
Test name
Test status
Simulation time 18675927549 ps
CPU time 185.64 seconds
Started Mar 05 12:40:19 PM PST 24
Finished Mar 05 12:43:26 PM PST 24
Peak memory 198772 kb
Host smart-2130510c-6d8c-44f5-8b01-9610a14d04ff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712304142 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.712304142
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.aon_timer_jump.1924707930
Short name T149
Test name
Test status
Simulation time 565648590 ps
CPU time 1.52 seconds
Started Mar 05 12:40:27 PM PST 24
Finished Mar 05 12:40:30 PM PST 24
Peak memory 183952 kb
Host smart-24e752ac-d505-4b53-a876-bd04c260e13e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924707930 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.1924707930
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.1480776857
Short name T8
Test name
Test status
Simulation time 30164355372 ps
CPU time 11.66 seconds
Started Mar 05 12:40:42 PM PST 24
Finished Mar 05 12:40:53 PM PST 24
Peak memory 184072 kb
Host smart-cd46c8f5-d545-462a-8f83-11de63186e4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480776857 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.1480776857
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.371929282
Short name T182
Test name
Test status
Simulation time 563099152 ps
CPU time 1.44 seconds
Started Mar 05 12:40:16 PM PST 24
Finished Mar 05 12:40:19 PM PST 24
Peak memory 183880 kb
Host smart-9b1bf6b2-255f-4a5b-93a1-80d43050e561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371929282 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.371929282
Directory /workspace/9.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.3238403506
Short name T266
Test name
Test status
Simulation time 183915707750 ps
CPU time 142.92 seconds
Started Mar 05 12:40:14 PM PST 24
Finished Mar 05 12:42:37 PM PST 24
Peak memory 192160 kb
Host smart-94119610-bb4f-451e-8e3f-f6072f5cad07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238403506 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_a
ll.3238403506
Directory /workspace/9.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.967607042
Short name T123
Test name
Test status
Simulation time 53542403208 ps
CPU time 436.43 seconds
Started Mar 05 12:40:19 PM PST 24
Finished Mar 05 12:47:36 PM PST 24
Peak memory 198792 kb
Host smart-e8e00992-b03f-4d56-aa99-0c3daf664ef4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967607042 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.967607042
Directory /workspace/9.aon_timer_stress_all_with_rand_reset/latest
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