Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
24.86 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv


Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 173 130 43 24.86


Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
bark_thold_cp 34 32 2 5.88 100 1 1 0
bite_thold_cp 34 32 2 5.88 100 1 1 0
pause_in_sleep_cp 2 1 1 50.00 100 1 1 2
prescale_cp 34 1 33 97.06 100 1 1 0
wdog_regwen_cp 2 0 2 100.00 100 1 1 2
wkup_cause_cp 1 0 1 100.00 100 1 1 0
wkup_thold_cp 66 64 2 3.03 100 1 1 0


Summary for Variable bark_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 32 2 5.88


User Defined Bins for bark_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
bark_max 0 1 1
bark[1] 0 1 1
bark[2] 0 1 1
bark[3] 0 1 1
bark[4] 0 1 1
bark[5] 0 1 1
bark[6] 0 1 1
bark[7] 0 1 1
bark[8] 0 1 1
bark[9] 0 1 1
bark[10] 0 1 1
bark[11] 0 1 1
bark[12] 0 1 1
bark[13] 0 1 1
bark[14] 0 1 1
bark[15] 0 1 1
bark[16] 0 1 1
bark[17] 0 1 1
bark[18] 0 1 1
bark[19] 0 1 1
bark[20] 0 1 1
bark[21] 0 1 1
bark[22] 0 1 1
bark[23] 0 1 1
bark[24] 0 1 1
bark[25] 0 1 1
bark[26] 0 1 1
bark[27] 0 1 1
bark[28] 0 1 1
bark[29] 0 1 1
bark[30] 0 1 1
bark[31] 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
bark[0] 50763 1 T1 273 T2 12 T3 11
bark_0 4568 1 T1 7 T2 7 T3 7


Summary for Variable bite_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 32 2 5.88


User Defined Bins for bite_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
bite_max 0 1 1
bite[1] 0 1 1
bite[2] 0 1 1
bite[3] 0 1 1
bite[4] 0 1 1
bite[5] 0 1 1
bite[6] 0 1 1
bite[7] 0 1 1
bite[8] 0 1 1
bite[9] 0 1 1
bite[10] 0 1 1
bite[11] 0 1 1
bite[12] 0 1 1
bite[13] 0 1 1
bite[14] 0 1 1
bite[15] 0 1 1
bite[16] 0 1 1
bite[17] 0 1 1
bite[18] 0 1 1
bite[19] 0 1 1
bite[20] 0 1 1
bite[21] 0 1 1
bite[22] 0 1 1
bite[23] 0 1 1
bite[24] 0 1 1
bite[25] 0 1 1
bite[26] 0 1 1
bite[27] 0 1 1
bite[28] 0 1 1
bite[29] 0 1 1
bite[30] 0 1 1
bite[31] 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
bite[0] 50240 1 T1 272 T2 11 T3 10
bite_0 5091 1 T1 8 T2 8 T3 8


Summary for Variable pause_in_sleep_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for pause_in_sleep_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 55331 1 T1 280 T2 19 T3 18


Summary for Variable prescale_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for prescale_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
prescale_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
prescale[0] 1137 1 T11 23 T27 19 T12 69
prescale[1] 776 1 T37 49 T41 28 T48 33
prescale[2] 1229 1 T6 64 T12 158 T45 24
prescale[3] 695 1 T12 9 T99 9 T95 134
prescale[4] 772 1 T27 121 T22 130 T40 20
prescale[5] 1014 1 T2 9 T12 30 T22 132
prescale[6] 1010 1 T12 83 T45 19 T46 37
prescale[7] 1181 1 T8 71 T36 47 T22 92
prescale[8] 1287 1 T1 53 T5 49 T6 33
prescale[9] 942 1 T8 30 T12 2 T45 28
prescale[10] 1066 1 T11 47 T12 37 T37 67
prescale[11] 702 1 T5 19 T8 145 T12 19
prescale[12] 904 1 T22 40 T100 28 T40 2
prescale[13] 962 1 T27 9 T22 37 T25 47
prescale[14] 583 1 T11 23 T45 37 T37 69
prescale[15] 943 1 T12 183 T22 96 T39 43
prescale[16] 753 1 T5 19 T6 19 T8 62
prescale[17] 1160 1 T1 80 T5 37 T6 147
prescale[18] 661 1 T5 38 T32 40 T46 37
prescale[19] 611 1 T1 19 T8 97 T37 19
prescale[20] 685 1 T6 69 T8 2 T41 30
prescale[21] 1189 1 T12 24 T36 2 T101 38
prescale[22] 842 1 T6 9 T46 42 T36 140
prescale[23] 676 1 T1 37 T8 2 T12 118
prescale[24] 948 1 T5 19 T42 9 T12 19
prescale[25] 628 1 T1 28 T6 79 T8 2
prescale[26] 681 1 T6 58 T8 2 T37 37
prescale[27] 1096 1 T46 41 T37 61 T47 30
prescale[28] 1061 1 T6 2 T12 76 T32 9
prescale[29] 508 1 T37 2 T102 38 T89 50
prescale[30] 1244 1 T6 19 T8 28 T36 99
prescale[31] 929 1 T4 9 T5 27 T43 9
prescale_0 26456 1 T1 63 T2 10 T3 18


Summary for Variable wdog_regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for wdog_regwen_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 42016 1 T1 196 T2 9 T3 9
auto[1] 13315 1 T1 84 T2 10 T3 9


Summary for Variable wkup_cause_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for wkup_cause_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
wkup_cause_cleared 55331 1 T1 280 T2 19 T3 18


Summary for Variable wkup_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 66 64 2 3.03


User Defined Bins for wkup_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
wkup_max 0 1 1
wkup[1] 0 1 1
wkup[2] 0 1 1
wkup[3] 0 1 1
wkup[4] 0 1 1
wkup[5] 0 1 1
wkup[6] 0 1 1
wkup[7] 0 1 1
wkup[8] 0 1 1
wkup[9] 0 1 1
wkup[10] 0 1 1
wkup[11] 0 1 1
wkup[12] 0 1 1
wkup[13] 0 1 1
wkup[14] 0 1 1
wkup[15] 0 1 1
wkup[16] 0 1 1
wkup[17] 0 1 1
wkup[18] 0 1 1
wkup[19] 0 1 1
wkup[20] 0 1 1
wkup[21] 0 1 1
wkup[22] 0 1 1
wkup[23] 0 1 1
wkup[24] 0 1 1
wkup[25] 0 1 1
wkup[26] 0 1 1
wkup[27] 0 1 1
wkup[28] 0 1 1
wkup[29] 0 1 1
wkup[30] 0 1 1
wkup[31] 0 1 1
wkup[32] 0 1 1
wkup[33] 0 1 1
wkup[34] 0 1 1
wkup[35] 0 1 1
wkup[36] 0 1 1
wkup[37] 0 1 1
wkup[38] 0 1 1
wkup[39] 0 1 1
wkup[40] 0 1 1
wkup[41] 0 1 1
wkup[42] 0 1 1
wkup[43] 0 1 1
wkup[44] 0 1 1
wkup[45] 0 1 1
wkup[46] 0 1 1
wkup[47] 0 1 1
wkup[48] 0 1 1
wkup[49] 0 1 1
wkup[50] 0 1 1
wkup[51] 0 1 1
wkup[52] 0 1 1
wkup[53] 0 1 1
wkup[54] 0 1 1
wkup[55] 0 1 1
wkup[56] 0 1 1
wkup[57] 0 1 1
wkup[58] 0 1 1
wkup[59] 0 1 1
wkup[60] 0 1 1
wkup[61] 0 1 1
wkup[62] 0 1 1
wkup[63] 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
wkup[0] 51762 1 T1 275 T2 14 T3 13
wkup_0 3569 1 T1 5 T2 5 T3 5

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%