Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
92.98 99.25 93.67 100.00 98.40 99.51 67.06


Total test records in report: 423
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T31 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.2466353734 Mar 07 12:27:10 PM PST 24 Mar 07 12:27:11 PM PST 24 341166682 ps
T283 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.202665382 Mar 07 12:27:27 PM PST 24 Mar 07 12:27:29 PM PST 24 749786287 ps
T33 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.3910416201 Mar 07 12:29:08 PM PST 24 Mar 07 12:29:09 PM PST 24 2311257256 ps
T93 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.1138463106 Mar 07 12:27:42 PM PST 24 Mar 07 12:27:43 PM PST 24 485294191 ps
T284 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.135038713 Mar 07 12:28:03 PM PST 24 Mar 07 12:28:04 PM PST 24 398150306 ps
T285 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.2161540222 Mar 07 12:27:11 PM PST 24 Mar 07 12:27:12 PM PST 24 447647284 ps
T286 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.2794308481 Mar 07 12:28:47 PM PST 24 Mar 07 12:28:48 PM PST 24 502432334 ps
T287 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.1864147321 Mar 07 12:27:49 PM PST 24 Mar 07 12:27:51 PM PST 24 522694827 ps
T288 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.607046268 Mar 07 12:27:18 PM PST 24 Mar 07 12:27:19 PM PST 24 405356782 ps
T289 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.3374405537 Mar 07 12:27:31 PM PST 24 Mar 07 12:27:33 PM PST 24 528341122 ps
T94 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.4096321617 Mar 07 12:27:04 PM PST 24 Mar 07 12:27:10 PM PST 24 7014149675 ps
T290 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.42673132 Mar 07 12:27:50 PM PST 24 Mar 07 12:27:51 PM PST 24 463881730 ps
T291 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.1601983220 Mar 07 12:28:08 PM PST 24 Mar 07 12:28:09 PM PST 24 336391144 ps
T292 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.555116196 Mar 07 12:28:13 PM PST 24 Mar 07 12:28:14 PM PST 24 484288271 ps
T293 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.3075262640 Mar 07 12:28:03 PM PST 24 Mar 07 12:28:04 PM PST 24 399013544 ps
T59 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.366250992 Mar 07 12:27:05 PM PST 24 Mar 07 12:27:06 PM PST 24 440947196 ps
T294 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.3127689221 Mar 07 12:28:12 PM PST 24 Mar 07 12:28:13 PM PST 24 289812539 ps
T295 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.4259806454 Mar 07 12:27:21 PM PST 24 Mar 07 12:27:22 PM PST 24 333888428 ps
T296 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.4113232845 Mar 07 12:28:06 PM PST 24 Mar 07 12:28:08 PM PST 24 408416819 ps
T297 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.2177712838 Mar 07 12:27:48 PM PST 24 Mar 07 12:27:49 PM PST 24 485495193 ps
T107 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.2738748523 Mar 07 12:27:29 PM PST 24 Mar 07 12:27:30 PM PST 24 369368395 ps
T298 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.2696626633 Mar 07 12:27:11 PM PST 24 Mar 07 12:27:13 PM PST 24 558742319 ps
T81 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.2103403855 Mar 07 12:27:37 PM PST 24 Mar 07 12:27:40 PM PST 24 1420317907 ps
T299 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.1023498139 Mar 07 12:27:56 PM PST 24 Mar 07 12:27:57 PM PST 24 376155444 ps
T300 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.3720894087 Mar 07 12:27:39 PM PST 24 Mar 07 12:27:40 PM PST 24 397769184 ps
T301 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.57693563 Mar 07 12:27:49 PM PST 24 Mar 07 12:27:50 PM PST 24 481036287 ps
T34 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.1876606204 Mar 07 12:27:47 PM PST 24 Mar 07 12:27:51 PM PST 24 4222065413 ps
T82 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.2705429403 Mar 07 12:27:38 PM PST 24 Mar 07 12:27:40 PM PST 24 1239207336 ps
T302 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.151447850 Mar 07 12:27:30 PM PST 24 Mar 07 12:27:31 PM PST 24 556372918 ps
T303 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.194405959 Mar 07 12:27:50 PM PST 24 Mar 07 12:27:51 PM PST 24 488364624 ps
T304 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.3510302195 Mar 07 12:27:11 PM PST 24 Mar 07 12:27:12 PM PST 24 311098288 ps
T305 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.2761295372 Mar 07 12:27:09 PM PST 24 Mar 07 12:27:10 PM PST 24 410267197 ps
T83 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.2528115211 Mar 07 12:27:11 PM PST 24 Mar 07 12:27:15 PM PST 24 2141449953 ps
T35 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.2260756713 Mar 07 12:27:51 PM PST 24 Mar 07 12:27:54 PM PST 24 4733926163 ps
T306 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.4167429679 Mar 07 12:27:30 PM PST 24 Mar 07 12:27:31 PM PST 24 321604351 ps
T84 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.894817801 Mar 07 12:27:18 PM PST 24 Mar 07 12:27:20 PM PST 24 1302779443 ps
T307 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.2622834819 Mar 07 12:27:05 PM PST 24 Mar 07 12:27:07 PM PST 24 553604464 ps
T85 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.1893869504 Mar 07 12:28:00 PM PST 24 Mar 07 12:28:01 PM PST 24 471695788 ps
T86 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.3241827189 Mar 07 12:27:51 PM PST 24 Mar 07 12:27:52 PM PST 24 397682265 ps
T87 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.1279784003 Mar 07 12:30:19 PM PST 24 Mar 07 12:30:20 PM PST 24 1065919878 ps
T308 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.1093255569 Mar 07 12:27:10 PM PST 24 Mar 07 12:27:13 PM PST 24 7566073509 ps
T104 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.2192121830 Mar 07 12:27:49 PM PST 24 Mar 07 12:27:52 PM PST 24 4550090285 ps
T88 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.3268738910 Mar 07 12:27:00 PM PST 24 Mar 07 12:27:02 PM PST 24 1064763381 ps
T309 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.2495895380 Mar 07 12:27:42 PM PST 24 Mar 07 12:27:44 PM PST 24 793530531 ps
T310 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.1386265245 Mar 07 12:29:36 PM PST 24 Mar 07 12:29:37 PM PST 24 415059390 ps
T311 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.1411173772 Mar 07 12:28:08 PM PST 24 Mar 07 12:28:11 PM PST 24 442071514 ps
T60 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.770371495 Mar 07 12:27:30 PM PST 24 Mar 07 12:27:31 PM PST 24 369775367 ps
T312 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.1850944206 Mar 07 12:27:52 PM PST 24 Mar 07 12:27:54 PM PST 24 530750477 ps
T313 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.278681838 Mar 07 12:27:57 PM PST 24 Mar 07 12:27:59 PM PST 24 515710014 ps
T314 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.2837865918 Mar 07 12:27:35 PM PST 24 Mar 07 12:27:36 PM PST 24 1241486388 ps
T315 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.3020503107 Mar 07 12:27:38 PM PST 24 Mar 07 12:27:39 PM PST 24 323721740 ps
T316 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.310303981 Mar 07 12:27:16 PM PST 24 Mar 07 12:27:19 PM PST 24 472371770 ps
T317 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.4088868381 Mar 07 12:27:07 PM PST 24 Mar 07 12:27:07 PM PST 24 364869279 ps
T318 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.1007970073 Mar 07 12:27:08 PM PST 24 Mar 07 12:27:10 PM PST 24 585279467 ps
T319 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.3798986334 Mar 07 12:27:31 PM PST 24 Mar 07 12:27:33 PM PST 24 336354991 ps
T320 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.433741047 Mar 07 12:27:30 PM PST 24 Mar 07 12:27:31 PM PST 24 499200379 ps
T321 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.2381385513 Mar 07 12:27:12 PM PST 24 Mar 07 12:27:13 PM PST 24 587268984 ps
T322 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.1933026770 Mar 07 12:28:02 PM PST 24 Mar 07 12:28:04 PM PST 24 358919165 ps
T323 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.2702485599 Mar 07 12:28:03 PM PST 24 Mar 07 12:28:06 PM PST 24 414577806 ps
T61 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.3097621132 Mar 07 12:27:41 PM PST 24 Mar 07 12:27:43 PM PST 24 446536912 ps
T324 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.1942512636 Mar 07 12:30:02 PM PST 24 Mar 07 12:30:05 PM PST 24 371872318 ps
T325 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.1421725692 Mar 07 12:28:00 PM PST 24 Mar 07 12:28:01 PM PST 24 439670133 ps
T326 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.1518658121 Mar 07 12:27:28 PM PST 24 Mar 07 12:27:31 PM PST 24 537946890 ps
T327 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.197592191 Mar 07 12:29:36 PM PST 24 Mar 07 12:29:38 PM PST 24 284360664 ps
T62 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.3752425437 Mar 07 12:27:12 PM PST 24 Mar 07 12:27:13 PM PST 24 1035387897 ps
T63 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.2258386304 Mar 07 12:27:09 PM PST 24 Mar 07 12:27:10 PM PST 24 348981454 ps
T328 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.1246204645 Mar 07 12:27:10 PM PST 24 Mar 07 12:27:11 PM PST 24 324709853 ps
T329 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.3084081514 Mar 07 12:28:12 PM PST 24 Mar 07 12:28:13 PM PST 24 504798177 ps
T103 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.928977143 Mar 07 12:27:28 PM PST 24 Mar 07 12:27:31 PM PST 24 4457663467 ps
T330 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.4010198204 Mar 07 12:28:02 PM PST 24 Mar 07 12:28:03 PM PST 24 324043471 ps
T331 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.4236065986 Mar 07 12:28:55 PM PST 24 Mar 07 12:28:56 PM PST 24 610679586 ps
T105 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.2096118104 Mar 07 12:27:30 PM PST 24 Mar 07 12:27:33 PM PST 24 4095018493 ps
T332 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.4089376437 Mar 07 12:28:11 PM PST 24 Mar 07 12:28:12 PM PST 24 411488623 ps
T333 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.2300073977 Mar 07 12:27:37 PM PST 24 Mar 07 12:27:39 PM PST 24 1116971469 ps
T334 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.1489388167 Mar 07 12:27:08 PM PST 24 Mar 07 12:27:12 PM PST 24 1832235662 ps
T335 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.410876595 Mar 07 12:28:56 PM PST 24 Mar 07 12:28:58 PM PST 24 531055894 ps
T336 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.2393185472 Mar 07 12:27:06 PM PST 24 Mar 07 12:27:07 PM PST 24 264770096 ps
T337 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.357515136 Mar 07 12:28:22 PM PST 24 Mar 07 12:28:24 PM PST 24 510942071 ps
T338 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.1616252846 Mar 07 12:27:05 PM PST 24 Mar 07 12:27:07 PM PST 24 371133263 ps
T339 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.3551197268 Mar 07 12:28:07 PM PST 24 Mar 07 12:28:09 PM PST 24 324845376 ps
T64 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.3423391765 Mar 07 12:27:28 PM PST 24 Mar 07 12:27:29 PM PST 24 473826881 ps
T340 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.2521095776 Mar 07 12:28:02 PM PST 24 Mar 07 12:28:04 PM PST 24 448318909 ps
T341 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.2770851583 Mar 07 12:27:54 PM PST 24 Mar 07 12:27:56 PM PST 24 321342518 ps
T342 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.3293425714 Mar 07 12:27:49 PM PST 24 Mar 07 12:27:50 PM PST 24 309047123 ps
T343 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.2756380178 Mar 07 12:27:21 PM PST 24 Mar 07 12:27:22 PM PST 24 529552977 ps
T344 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.871826474 Mar 07 12:27:12 PM PST 24 Mar 07 12:27:13 PM PST 24 1430255941 ps
T345 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.1513409117 Mar 07 12:27:54 PM PST 24 Mar 07 12:27:55 PM PST 24 447561231 ps
T346 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.2970901566 Mar 07 12:27:42 PM PST 24 Mar 07 12:27:44 PM PST 24 446463149 ps
T347 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.4253496566 Mar 07 12:27:42 PM PST 24 Mar 07 12:27:43 PM PST 24 427691799 ps
T348 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.1772948012 Mar 07 12:27:31 PM PST 24 Mar 07 12:27:32 PM PST 24 484677321 ps
T349 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.3753425046 Mar 07 12:29:53 PM PST 24 Mar 07 12:29:54 PM PST 24 481816377 ps
T350 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.2572281101 Mar 07 12:29:53 PM PST 24 Mar 07 12:29:54 PM PST 24 404969257 ps
T351 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.1327058362 Mar 07 12:27:54 PM PST 24 Mar 07 12:27:55 PM PST 24 441346237 ps
T352 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.1607884084 Mar 07 12:28:08 PM PST 24 Mar 07 12:28:09 PM PST 24 384383349 ps
T353 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.2489321629 Mar 07 12:27:49 PM PST 24 Mar 07 12:27:51 PM PST 24 1655751075 ps
T354 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.2307337583 Mar 07 12:30:19 PM PST 24 Mar 07 12:30:20 PM PST 24 1501361702 ps
T355 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.1329916142 Mar 07 12:27:04 PM PST 24 Mar 07 12:27:06 PM PST 24 326841284 ps
T356 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.2611583067 Mar 07 12:27:42 PM PST 24 Mar 07 12:27:43 PM PST 24 388485328 ps
T357 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.2181264349 Mar 07 12:27:33 PM PST 24 Mar 07 12:27:41 PM PST 24 4340506904 ps
T358 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.1441529015 Mar 07 12:27:21 PM PST 24 Mar 07 12:27:24 PM PST 24 569273756 ps
T65 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.42832186 Mar 07 12:27:45 PM PST 24 Mar 07 12:27:46 PM PST 24 339353596 ps
T359 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.3043563932 Mar 07 12:27:09 PM PST 24 Mar 07 12:27:11 PM PST 24 465281289 ps
T360 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.3956598945 Mar 07 12:29:36 PM PST 24 Mar 07 12:29:38 PM PST 24 517411635 ps
T361 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.912348415 Mar 07 12:29:51 PM PST 24 Mar 07 12:29:52 PM PST 24 392993108 ps
T362 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.3619087070 Mar 07 12:27:47 PM PST 24 Mar 07 12:27:49 PM PST 24 431666445 ps
T363 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.2464715489 Mar 07 12:27:29 PM PST 24 Mar 07 12:27:30 PM PST 24 405348828 ps
T364 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.2543954345 Mar 07 12:27:21 PM PST 24 Mar 07 12:27:23 PM PST 24 510835157 ps
T365 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.3824755303 Mar 07 12:27:31 PM PST 24 Mar 07 12:27:33 PM PST 24 1894432761 ps
T66 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.2129540284 Mar 07 12:28:00 PM PST 24 Mar 07 12:28:01 PM PST 24 471167078 ps
T366 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.2772670920 Mar 07 12:27:18 PM PST 24 Mar 07 12:27:58 PM PST 24 13845747734 ps
T367 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.2825466129 Mar 07 12:27:42 PM PST 24 Mar 07 12:27:43 PM PST 24 487247037 ps
T368 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.1664292304 Mar 07 12:27:42 PM PST 24 Mar 07 12:27:43 PM PST 24 405544272 ps
T369 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.1956129731 Mar 07 12:27:08 PM PST 24 Mar 07 12:27:10 PM PST 24 1285885996 ps
T67 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.2157852944 Mar 07 12:27:27 PM PST 24 Mar 07 12:27:28 PM PST 24 410598940 ps
T370 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.1749216582 Mar 07 12:27:48 PM PST 24 Mar 07 12:27:50 PM PST 24 513907791 ps
T371 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.20359948 Mar 07 12:30:18 PM PST 24 Mar 07 12:30:34 PM PST 24 8264632311 ps
T372 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.2043252623 Mar 07 12:27:06 PM PST 24 Mar 07 12:27:07 PM PST 24 900573345 ps
T373 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.2443585846 Mar 07 12:27:09 PM PST 24 Mar 07 12:27:24 PM PST 24 8663161863 ps
T374 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.2495292721 Mar 07 12:27:51 PM PST 24 Mar 07 12:27:53 PM PST 24 1805004535 ps
T375 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.1371785181 Mar 07 12:27:46 PM PST 24 Mar 07 12:27:51 PM PST 24 1403250988 ps
T376 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.3488931056 Mar 07 12:27:12 PM PST 24 Mar 07 12:27:12 PM PST 24 444233502 ps
T377 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.1445160770 Mar 07 12:28:11 PM PST 24 Mar 07 12:28:12 PM PST 24 374847007 ps
T378 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.3632610000 Mar 07 12:27:37 PM PST 24 Mar 07 12:27:38 PM PST 24 539991658 ps
T379 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.383880853 Mar 07 12:27:21 PM PST 24 Mar 07 12:27:22 PM PST 24 518847948 ps
T380 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.4188709318 Mar 07 12:27:19 PM PST 24 Mar 07 12:27:20 PM PST 24 504817880 ps
T381 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.3251670385 Mar 07 12:27:42 PM PST 24 Mar 07 12:27:44 PM PST 24 321354900 ps
T382 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.1305394877 Mar 07 12:28:15 PM PST 24 Mar 07 12:28:17 PM PST 24 1969228892 ps
T383 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.2161377271 Mar 07 12:27:11 PM PST 24 Mar 07 12:27:18 PM PST 24 4477756974 ps
T384 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.3454492194 Mar 07 12:27:39 PM PST 24 Mar 07 12:27:40 PM PST 24 597538553 ps
T385 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.668509375 Mar 07 12:27:15 PM PST 24 Mar 07 12:27:16 PM PST 24 424848370 ps
T386 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.1812098174 Mar 07 12:27:33 PM PST 24 Mar 07 12:27:40 PM PST 24 4457897448 ps
T387 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.3150318054 Mar 07 12:27:21 PM PST 24 Mar 07 12:27:26 PM PST 24 8352993633 ps
T388 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.2569746690 Mar 07 12:27:44 PM PST 24 Mar 07 12:27:46 PM PST 24 400597066 ps
T389 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.2857821242 Mar 07 12:27:12 PM PST 24 Mar 07 12:27:12 PM PST 24 509611815 ps
T68 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.2642697324 Mar 07 12:27:01 PM PST 24 Mar 07 12:27:12 PM PST 24 12984366109 ps
T390 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.3402038749 Mar 07 12:27:41 PM PST 24 Mar 07 12:27:43 PM PST 24 1183034066 ps
T391 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.805289575 Mar 07 12:27:17 PM PST 24 Mar 07 12:27:19 PM PST 24 326377778 ps
T392 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.1735419982 Mar 07 12:27:31 PM PST 24 Mar 07 12:27:46 PM PST 24 8331122586 ps
T393 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.3770788010 Mar 07 12:28:29 PM PST 24 Mar 07 12:28:40 PM PST 24 2349283865 ps
T394 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.1089216483 Mar 07 12:27:48 PM PST 24 Mar 07 12:27:50 PM PST 24 1408487308 ps
T69 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.606703346 Mar 07 12:27:04 PM PST 24 Mar 07 12:27:06 PM PST 24 514683508 ps
T395 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.3812304953 Mar 07 12:27:31 PM PST 24 Mar 07 12:27:34 PM PST 24 460171314 ps
T396 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.2871803190 Mar 07 12:27:06 PM PST 24 Mar 07 12:27:07 PM PST 24 401714008 ps
T397 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.3616960356 Mar 07 12:27:42 PM PST 24 Mar 07 12:27:50 PM PST 24 4009406683 ps
T398 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.2512566210 Mar 07 12:27:53 PM PST 24 Mar 07 12:27:54 PM PST 24 405106459 ps
T80 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.3244723393 Mar 07 12:27:42 PM PST 24 Mar 07 12:27:43 PM PST 24 384550729 ps
T399 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.3303715590 Mar 07 12:27:37 PM PST 24 Mar 07 12:27:43 PM PST 24 2672978996 ps
T400 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.663972619 Mar 07 12:30:20 PM PST 24 Mar 07 12:30:22 PM PST 24 353833102 ps
T401 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.295945895 Mar 07 12:27:23 PM PST 24 Mar 07 12:27:24 PM PST 24 513054965 ps
T402 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.558472282 Mar 07 12:27:30 PM PST 24 Mar 07 12:27:31 PM PST 24 278152683 ps
T403 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.2219461010 Mar 07 12:27:46 PM PST 24 Mar 07 12:27:48 PM PST 24 526318409 ps
T404 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.2066921738 Mar 07 12:27:04 PM PST 24 Mar 07 12:27:06 PM PST 24 4881526503 ps
T405 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.3491274690 Mar 07 12:27:09 PM PST 24 Mar 07 12:27:10 PM PST 24 328780593 ps
T406 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.368473514 Mar 07 12:27:39 PM PST 24 Mar 07 12:27:40 PM PST 24 372228113 ps
T407 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.584657730 Mar 07 12:27:21 PM PST 24 Mar 07 12:27:22 PM PST 24 358107814 ps
T408 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.3877863004 Mar 07 12:27:48 PM PST 24 Mar 07 12:27:49 PM PST 24 326834160 ps
T409 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.1033291711 Mar 07 12:29:51 PM PST 24 Mar 07 12:29:52 PM PST 24 432157716 ps
T410 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.2712120224 Mar 07 12:27:42 PM PST 24 Mar 07 12:27:43 PM PST 24 584125702 ps
T106 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.3882799636 Mar 07 12:27:31 PM PST 24 Mar 07 12:27:47 PM PST 24 8521692754 ps
T411 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.2038756035 Mar 07 12:27:09 PM PST 24 Mar 07 12:27:10 PM PST 24 541332924 ps
T412 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.1845562807 Mar 07 12:27:09 PM PST 24 Mar 07 12:27:18 PM PST 24 8635100953 ps
T413 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.3458653701 Mar 07 12:28:02 PM PST 24 Mar 07 12:28:04 PM PST 24 1538202764 ps
T414 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.4077067528 Mar 07 12:27:11 PM PST 24 Mar 07 12:27:12 PM PST 24 340546243 ps
T415 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.233710129 Mar 07 12:27:19 PM PST 24 Mar 07 12:27:26 PM PST 24 8018594607 ps
T416 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.1750141081 Mar 07 12:27:19 PM PST 24 Mar 07 12:27:23 PM PST 24 8302546967 ps
T417 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.896887575 Mar 07 12:28:17 PM PST 24 Mar 07 12:28:20 PM PST 24 413936335 ps
T418 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.1282195194 Mar 07 12:28:02 PM PST 24 Mar 07 12:28:04 PM PST 24 491390022 ps
T419 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.1944393074 Mar 07 12:27:11 PM PST 24 Mar 07 12:27:12 PM PST 24 450309436 ps
T420 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.160393905 Mar 07 12:28:00 PM PST 24 Mar 07 12:28:04 PM PST 24 8062557044 ps
T421 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.2324568780 Mar 07 12:28:13 PM PST 24 Mar 07 12:28:14 PM PST 24 350458330 ps
T422 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.3852542967 Mar 07 12:27:13 PM PST 24 Mar 07 12:27:15 PM PST 24 1054754969 ps
T423 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.543208036 Mar 07 12:28:08 PM PST 24 Mar 07 12:28:09 PM PST 24 357278217 ps
T70 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.2624441836 Mar 07 12:27:00 PM PST 24 Mar 07 12:27:02 PM PST 24 625768393 ps

Test location /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.1458205497
Short name T6
Test name
Test status
Simulation time 83095113716 ps
CPU time 322.42 seconds
Started Mar 07 12:29:34 PM PST 24
Finished Mar 07 12:34:57 PM PST 24
Peak memory 198768 kb
Host smart-4a1741bb-a978-4222-a565-868c8730a40d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458205497 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.1458205497
Directory /workspace/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.3938178184
Short name T30
Test name
Test status
Simulation time 8611612627 ps
CPU time 4.48 seconds
Started Mar 07 12:27:06 PM PST 24
Finished Mar 07 12:27:10 PM PST 24
Peak memory 197080 kb
Host smart-36a7f04c-6500-43c6-af70-a7bc41555f82
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938178184 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl
_intg_err.3938178184
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.3474814734
Short name T12
Test name
Test status
Simulation time 67692132814 ps
CPU time 175.74 seconds
Started Mar 07 12:30:53 PM PST 24
Finished Mar 07 12:33:49 PM PST 24
Peak memory 197896 kb
Host smart-266a58a7-9d0b-4b74-8998-4d14e795a979
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474814734 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.3474814734
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.111921735
Short name T27
Test name
Test status
Simulation time 29467928575 ps
CPU time 12.01 seconds
Started Mar 07 12:29:23 PM PST 24
Finished Mar 07 12:29:35 PM PST 24
Peak memory 183772 kb
Host smart-6bec4fea-26ac-49bd-821a-9d989ada6be7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111921735 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_a
ll.111921735
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.770371495
Short name T60
Test name
Test status
Simulation time 369775367 ps
CPU time 1.26 seconds
Started Mar 07 12:27:30 PM PST 24
Finished Mar 07 12:27:31 PM PST 24
Peak memory 192440 kb
Host smart-48a2d0ef-fb6e-4828-a4ff-f0506a9d694c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770371495 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.770371495
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.1847311644
Short name T15
Test name
Test status
Simulation time 7494601244 ps
CPU time 3.41 seconds
Started Mar 07 12:29:04 PM PST 24
Finished Mar 07 12:29:08 PM PST 24
Peak memory 215628 kb
Host smart-91be9f2d-aa61-4e4c-897b-7807eadba2e7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847311644 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.1847311644
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.2803217039
Short name T37
Test name
Test status
Simulation time 25890909936 ps
CPU time 207.69 seconds
Started Mar 07 12:29:04 PM PST 24
Finished Mar 07 12:32:31 PM PST 24
Peak memory 198952 kb
Host smart-47c220e9-6b19-47a1-b661-37e6253054d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803217039 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.2803217039
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.3743573269
Short name T89
Test name
Test status
Simulation time 137127245002 ps
CPU time 261.04 seconds
Started Mar 07 12:29:05 PM PST 24
Finished Mar 07 12:33:27 PM PST 24
Peak memory 198892 kb
Host smart-ebb42487-68bf-4906-9833-67c1d336869b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743573269 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.3743573269
Directory /workspace/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.3782508683
Short name T49
Test name
Test status
Simulation time 45547725257 ps
CPU time 363.23 seconds
Started Mar 07 12:29:10 PM PST 24
Finished Mar 07 12:35:14 PM PST 24
Peak memory 198868 kb
Host smart-1f4de846-1c4d-49c7-b77a-57848f89612a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782508683 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.3782508683
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.2622834819
Short name T307
Test name
Test status
Simulation time 553604464 ps
CPU time 1.41 seconds
Started Mar 07 12:27:05 PM PST 24
Finished Mar 07 12:27:07 PM PST 24
Peak memory 183076 kb
Host smart-a965367d-1fcb-4b18-a79f-60e869c5b4e4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622834819 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_a
liasing.2622834819
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.2642697324
Short name T68
Test name
Test status
Simulation time 12984366109 ps
CPU time 10.5 seconds
Started Mar 07 12:27:01 PM PST 24
Finished Mar 07 12:27:12 PM PST 24
Peak memory 191632 kb
Host smart-bba36225-65bd-40d7-a8a0-5a537cd267a8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642697324 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_b
it_bash.2642697324
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.2495895380
Short name T309
Test name
Test status
Simulation time 793530531 ps
CPU time 1.7 seconds
Started Mar 07 12:27:42 PM PST 24
Finished Mar 07 12:27:44 PM PST 24
Peak memory 182704 kb
Host smart-2647d192-4b62-4bd4-95f5-444b44fddb04
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495895380 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_h
w_reset.2495895380
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.1007970073
Short name T318
Test name
Test status
Simulation time 585279467 ps
CPU time 1.52 seconds
Started Mar 07 12:27:08 PM PST 24
Finished Mar 07 12:27:10 PM PST 24
Peak memory 195964 kb
Host smart-a61bbf64-6c7b-4638-a4ba-5425c2c62a52
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007970073 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.1007970073
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.606703346
Short name T69
Test name
Test status
Simulation time 514683508 ps
CPU time 1.03 seconds
Started Mar 07 12:27:04 PM PST 24
Finished Mar 07 12:27:06 PM PST 24
Peak memory 183208 kb
Host smart-872522f2-ad7a-4ea2-84f3-abc6a7dc5bdd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606703346 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.606703346
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.1772948012
Short name T348
Test name
Test status
Simulation time 484677321 ps
CPU time 1.23 seconds
Started Mar 07 12:27:31 PM PST 24
Finished Mar 07 12:27:32 PM PST 24
Peak memory 183016 kb
Host smart-d0eb1a07-d63d-47d1-ad5d-988d08eeab63
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772948012 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.1772948012
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.3020503107
Short name T315
Test name
Test status
Simulation time 323721740 ps
CPU time 1.01 seconds
Started Mar 07 12:27:38 PM PST 24
Finished Mar 07 12:27:39 PM PST 24
Peak memory 182792 kb
Host smart-bd200e3b-8334-411a-b8c4-c094bdf4772f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020503107 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_t
imer_mem_partial_access.3020503107
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.607046268
Short name T288
Test name
Test status
Simulation time 405356782 ps
CPU time 0.86 seconds
Started Mar 07 12:27:18 PM PST 24
Finished Mar 07 12:27:19 PM PST 24
Peak memory 182064 kb
Host smart-b5a2df67-4228-4beb-877b-ea4f6a67968a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607046268 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_wa
lk.607046268
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.3268738910
Short name T88
Test name
Test status
Simulation time 1064763381 ps
CPU time 1.41 seconds
Started Mar 07 12:27:00 PM PST 24
Finished Mar 07 12:27:02 PM PST 24
Peak memory 192660 kb
Host smart-c2ea1f43-bba5-47be-ba9d-303df4243b1a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268738910 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon
_timer_same_csr_outstanding.3268738910
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.3374405537
Short name T289
Test name
Test status
Simulation time 528341122 ps
CPU time 2 seconds
Started Mar 07 12:27:31 PM PST 24
Finished Mar 07 12:27:33 PM PST 24
Peak memory 197948 kb
Host smart-c850a45d-a093-430a-bc69-e59864186842
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374405537 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.3374405537
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.233710129
Short name T415
Test name
Test status
Simulation time 8018594607 ps
CPU time 7.07 seconds
Started Mar 07 12:27:19 PM PST 24
Finished Mar 07 12:27:26 PM PST 24
Peak memory 197124 kb
Host smart-c6d7e39b-b80e-47da-aa55-6d0f9b957de0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233710129 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_
intg_err.233710129
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.2258386304
Short name T63
Test name
Test status
Simulation time 348981454 ps
CPU time 0.95 seconds
Started Mar 07 12:27:09 PM PST 24
Finished Mar 07 12:27:10 PM PST 24
Peak memory 193368 kb
Host smart-2ffc3c42-2aa4-46ac-8680-bbefd71d74e9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258386304 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_a
liasing.2258386304
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.4096321617
Short name T94
Test name
Test status
Simulation time 7014149675 ps
CPU time 5.24 seconds
Started Mar 07 12:27:04 PM PST 24
Finished Mar 07 12:27:10 PM PST 24
Peak memory 191476 kb
Host smart-695ee48c-524a-4b36-b052-c1a879aa2d1d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096321617 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_b
it_bash.4096321617
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.2043252623
Short name T372
Test name
Test status
Simulation time 900573345 ps
CPU time 1.12 seconds
Started Mar 07 12:27:06 PM PST 24
Finished Mar 07 12:27:07 PM PST 24
Peak memory 182916 kb
Host smart-99220211-d125-4f3c-94f0-f4dae1b46c80
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043252623 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_h
w_reset.2043252623
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.4253496566
Short name T347
Test name
Test status
Simulation time 427691799 ps
CPU time 1.24 seconds
Started Mar 07 12:27:42 PM PST 24
Finished Mar 07 12:27:43 PM PST 24
Peak memory 194460 kb
Host smart-9a69fa22-50ce-444e-9937-1c6f8f6bb968
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253496566 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.4253496566
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.2038756035
Short name T411
Test name
Test status
Simulation time 541332924 ps
CPU time 1.06 seconds
Started Mar 07 12:27:09 PM PST 24
Finished Mar 07 12:27:10 PM PST 24
Peak memory 183208 kb
Host smart-6a780884-1283-4e4e-9ece-4eb78a82ab62
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038756035 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.2038756035
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.2393185472
Short name T336
Test name
Test status
Simulation time 264770096 ps
CPU time 0.9 seconds
Started Mar 07 12:27:06 PM PST 24
Finished Mar 07 12:27:07 PM PST 24
Peak memory 182784 kb
Host smart-744490be-52ed-4a6e-965e-ccabdfb4b018
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393185472 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.2393185472
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.4088868381
Short name T317
Test name
Test status
Simulation time 364869279 ps
CPU time 0.63 seconds
Started Mar 07 12:27:07 PM PST 24
Finished Mar 07 12:27:07 PM PST 24
Peak memory 182792 kb
Host smart-c7f6ed10-1e65-4247-9a8a-24c5549e6d7b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088868381 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_t
imer_mem_partial_access.4088868381
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.3488931056
Short name T376
Test name
Test status
Simulation time 444233502 ps
CPU time 0.58 seconds
Started Mar 07 12:27:12 PM PST 24
Finished Mar 07 12:27:12 PM PST 24
Peak memory 182832 kb
Host smart-97244530-f22d-42f4-baa6-a45c1bc9bc9b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488931056 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_w
alk.3488931056
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.3303715590
Short name T399
Test name
Test status
Simulation time 2672978996 ps
CPU time 5.85 seconds
Started Mar 07 12:27:37 PM PST 24
Finished Mar 07 12:27:43 PM PST 24
Peak memory 191252 kb
Host smart-03d2d8db-3674-4b3a-a29a-7205609aed4b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303715590 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon
_timer_same_csr_outstanding.3303715590
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.1329916142
Short name T355
Test name
Test status
Simulation time 326841284 ps
CPU time 1.67 seconds
Started Mar 07 12:27:04 PM PST 24
Finished Mar 07 12:27:06 PM PST 24
Peak memory 197880 kb
Host smart-82ba269c-3aab-461f-ad4d-1edf9ef8fb22
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329916142 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.1329916142
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.2066921738
Short name T404
Test name
Test status
Simulation time 4881526503 ps
CPU time 1.44 seconds
Started Mar 07 12:27:04 PM PST 24
Finished Mar 07 12:27:06 PM PST 24
Peak memory 195856 kb
Host smart-a2183ede-7cb6-459f-a94d-cff4e1550091
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066921738 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl
_intg_err.2066921738
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.151447850
Short name T302
Test name
Test status
Simulation time 556372918 ps
CPU time 1.01 seconds
Started Mar 07 12:27:30 PM PST 24
Finished Mar 07 12:27:31 PM PST 24
Peak memory 194184 kb
Host smart-dd663950-96eb-4945-b3c0-3e8f70043072
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151447850 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.151447850
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.2157852944
Short name T67
Test name
Test status
Simulation time 410598940 ps
CPU time 1.03 seconds
Started Mar 07 12:27:27 PM PST 24
Finished Mar 07 12:27:28 PM PST 24
Peak memory 183128 kb
Host smart-2750b3fe-7132-49de-8efd-3914cb85b235
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157852944 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.2157852944
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.558472282
Short name T402
Test name
Test status
Simulation time 278152683 ps
CPU time 0.96 seconds
Started Mar 07 12:27:30 PM PST 24
Finished Mar 07 12:27:31 PM PST 24
Peak memory 182804 kb
Host smart-5ff465dd-20a6-48b4-a5ac-074471939764
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558472282 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.558472282
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.3824755303
Short name T365
Test name
Test status
Simulation time 1894432761 ps
CPU time 2.12 seconds
Started Mar 07 12:27:31 PM PST 24
Finished Mar 07 12:27:33 PM PST 24
Peak memory 183044 kb
Host smart-26f9fa20-a580-4cdb-872b-63411e28bccb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824755303 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.ao
n_timer_same_csr_outstanding.3824755303
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.1942512636
Short name T324
Test name
Test status
Simulation time 371872318 ps
CPU time 1.88 seconds
Started Mar 07 12:30:02 PM PST 24
Finished Mar 07 12:30:05 PM PST 24
Peak memory 196988 kb
Host smart-08deb85b-e3f7-45ea-8fc3-67f389614b77
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942512636 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.1942512636
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.2096118104
Short name T105
Test name
Test status
Simulation time 4095018493 ps
CPU time 2.36 seconds
Started Mar 07 12:27:30 PM PST 24
Finished Mar 07 12:27:33 PM PST 24
Peak memory 196260 kb
Host smart-56e49f82-e903-49ec-a78a-4a9c3311b4bc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096118104 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_t
l_intg_err.2096118104
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.4167429679
Short name T306
Test name
Test status
Simulation time 321604351 ps
CPU time 1.14 seconds
Started Mar 07 12:27:30 PM PST 24
Finished Mar 07 12:27:31 PM PST 24
Peak memory 194180 kb
Host smart-b01f1d76-7ebb-46a8-8bdf-602abea30560
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167429679 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.4167429679
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.3423391765
Short name T64
Test name
Test status
Simulation time 473826881 ps
CPU time 0.88 seconds
Started Mar 07 12:27:28 PM PST 24
Finished Mar 07 12:27:29 PM PST 24
Peak memory 183088 kb
Host smart-f38b9b25-07f8-48d6-aae9-a4d3df96c583
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423391765 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.3423391765
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.663972619
Short name T400
Test name
Test status
Simulation time 353833102 ps
CPU time 1.12 seconds
Started Mar 07 12:30:20 PM PST 24
Finished Mar 07 12:30:22 PM PST 24
Peak memory 182852 kb
Host smart-f6b36703-2970-4c48-ab43-e40b3050ce04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663972619 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.663972619
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.1279784003
Short name T87
Test name
Test status
Simulation time 1065919878 ps
CPU time 1.72 seconds
Started Mar 07 12:30:19 PM PST 24
Finished Mar 07 12:30:20 PM PST 24
Peak memory 182996 kb
Host smart-eef187ad-52d6-4ef2-af94-1e351f1913ff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279784003 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.ao
n_timer_same_csr_outstanding.1279784003
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.1518658121
Short name T326
Test name
Test status
Simulation time 537946890 ps
CPU time 2.7 seconds
Started Mar 07 12:27:28 PM PST 24
Finished Mar 07 12:27:31 PM PST 24
Peak memory 197772 kb
Host smart-c08cceaf-f99b-4cc0-aaef-716a75585ff3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518658121 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.1518658121
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.2181264349
Short name T357
Test name
Test status
Simulation time 4340506904 ps
CPU time 7.9 seconds
Started Mar 07 12:27:33 PM PST 24
Finished Mar 07 12:27:41 PM PST 24
Peak memory 196584 kb
Host smart-680833b8-2c25-4495-a1cb-e298b966d6a3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181264349 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_t
l_intg_err.2181264349
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.433741047
Short name T320
Test name
Test status
Simulation time 499200379 ps
CPU time 1 seconds
Started Mar 07 12:27:30 PM PST 24
Finished Mar 07 12:27:31 PM PST 24
Peak memory 197476 kb
Host smart-f4075c08-ab45-4ead-b525-ffee059b986d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433741047 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.433741047
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.3720894087
Short name T300
Test name
Test status
Simulation time 397769184 ps
CPU time 0.99 seconds
Started Mar 07 12:27:39 PM PST 24
Finished Mar 07 12:27:40 PM PST 24
Peak memory 183064 kb
Host smart-05b0101d-9812-474f-bb6f-d0770118d21e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720894087 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.3720894087
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.2307337583
Short name T354
Test name
Test status
Simulation time 1501361702 ps
CPU time 0.91 seconds
Started Mar 07 12:30:19 PM PST 24
Finished Mar 07 12:30:20 PM PST 24
Peak memory 192480 kb
Host smart-4fe6c610-d5ba-4957-b304-935b554f9198
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307337583 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.ao
n_timer_same_csr_outstanding.2307337583
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.310303981
Short name T316
Test name
Test status
Simulation time 472371770 ps
CPU time 2.84 seconds
Started Mar 07 12:27:16 PM PST 24
Finished Mar 07 12:27:19 PM PST 24
Peak memory 197800 kb
Host smart-c3abd1ee-c21e-49cd-b6b8-94ade0831c6c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310303981 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.310303981
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.20359948
Short name T371
Test name
Test status
Simulation time 8264632311 ps
CPU time 15.28 seconds
Started Mar 07 12:30:18 PM PST 24
Finished Mar 07 12:30:34 PM PST 24
Peak memory 197032 kb
Host smart-dba55850-d8eb-4143-a165-aece5e341490
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20359948 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_
intg_err.20359948
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.2712120224
Short name T410
Test name
Test status
Simulation time 584125702 ps
CPU time 1.41 seconds
Started Mar 07 12:27:42 PM PST 24
Finished Mar 07 12:27:43 PM PST 24
Peak memory 194892 kb
Host smart-d4aa68c5-0107-4fb3-96dc-92888e338d24
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712120224 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.2712120224
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.3244723393
Short name T80
Test name
Test status
Simulation time 384550729 ps
CPU time 0.74 seconds
Started Mar 07 12:27:42 PM PST 24
Finished Mar 07 12:27:43 PM PST 24
Peak memory 182772 kb
Host smart-d2da7194-bdee-421c-8b5f-0d6aab91e3d3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244723393 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.3244723393
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.3127689221
Short name T294
Test name
Test status
Simulation time 289812539 ps
CPU time 0.84 seconds
Started Mar 07 12:28:12 PM PST 24
Finished Mar 07 12:28:13 PM PST 24
Peak memory 182552 kb
Host smart-a8cb4315-1683-4499-9787-9919bca70871
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127689221 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.3127689221
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.2705429403
Short name T82
Test name
Test status
Simulation time 1239207336 ps
CPU time 1.19 seconds
Started Mar 07 12:27:38 PM PST 24
Finished Mar 07 12:27:40 PM PST 24
Peak memory 182996 kb
Host smart-1566fc1a-a061-4113-9d04-042c54f7e11e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705429403 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.ao
n_timer_same_csr_outstanding.2705429403
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.2569746690
Short name T388
Test name
Test status
Simulation time 400597066 ps
CPU time 2.14 seconds
Started Mar 07 12:27:44 PM PST 24
Finished Mar 07 12:27:46 PM PST 24
Peak memory 197892 kb
Host smart-5988f203-964e-49f6-890e-f99705d93e57
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569746690 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.2569746690
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.3616960356
Short name T397
Test name
Test status
Simulation time 4009406683 ps
CPU time 8.12 seconds
Started Mar 07 12:27:42 PM PST 24
Finished Mar 07 12:27:50 PM PST 24
Peak memory 196120 kb
Host smart-a1401d6c-bc4f-4a19-b58f-c8c4d1f85a8d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616960356 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_t
l_intg_err.3616960356
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.2464715489
Short name T363
Test name
Test status
Simulation time 405348828 ps
CPU time 1.25 seconds
Started Mar 07 12:27:29 PM PST 24
Finished Mar 07 12:27:30 PM PST 24
Peak memory 194416 kb
Host smart-fd0248c5-0c29-4d7d-bac1-8dca81376050
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464715489 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.2464715489
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.3632610000
Short name T378
Test name
Test status
Simulation time 539991658 ps
CPU time 1.26 seconds
Started Mar 07 12:27:37 PM PST 24
Finished Mar 07 12:27:38 PM PST 24
Peak memory 192344 kb
Host smart-3d389cab-20e1-4c8d-b424-bfe12138e2ab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632610000 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.3632610000
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.2970901566
Short name T346
Test name
Test status
Simulation time 446463149 ps
CPU time 1.29 seconds
Started Mar 07 12:27:42 PM PST 24
Finished Mar 07 12:27:44 PM PST 24
Peak memory 182328 kb
Host smart-f036059f-669b-49f2-b846-33ffb20b8332
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970901566 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.2970901566
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.2103403855
Short name T81
Test name
Test status
Simulation time 1420317907 ps
CPU time 3.06 seconds
Started Mar 07 12:27:37 PM PST 24
Finished Mar 07 12:27:40 PM PST 24
Peak memory 183092 kb
Host smart-7f56316a-6de7-4c23-8b8d-515f4e1c2542
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103403855 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao
n_timer_same_csr_outstanding.2103403855
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.368473514
Short name T406
Test name
Test status
Simulation time 372228113 ps
CPU time 1.3 seconds
Started Mar 07 12:27:39 PM PST 24
Finished Mar 07 12:27:40 PM PST 24
Peak memory 197528 kb
Host smart-9d71af0a-cabf-4ada-a53a-d39e4522f293
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368473514 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.368473514
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.1812098174
Short name T386
Test name
Test status
Simulation time 4457897448 ps
CPU time 6.61 seconds
Started Mar 07 12:27:33 PM PST 24
Finished Mar 07 12:27:40 PM PST 24
Peak memory 195868 kb
Host smart-aa7ce111-423e-4552-8284-aa0ab9de094a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812098174 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_t
l_intg_err.1812098174
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.2738748523
Short name T107
Test name
Test status
Simulation time 369368395 ps
CPU time 0.92 seconds
Started Mar 07 12:27:29 PM PST 24
Finished Mar 07 12:27:30 PM PST 24
Peak memory 195748 kb
Host smart-28118140-2735-4067-b555-0640d3c93ffb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738748523 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.2738748523
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.1138463106
Short name T93
Test name
Test status
Simulation time 485294191 ps
CPU time 0.89 seconds
Started Mar 07 12:27:42 PM PST 24
Finished Mar 07 12:27:43 PM PST 24
Peak memory 181164 kb
Host smart-caf89e42-19f0-42de-a13b-ed3ff9248dfb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138463106 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.1138463106
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.2521095776
Short name T340
Test name
Test status
Simulation time 448318909 ps
CPU time 1.26 seconds
Started Mar 07 12:28:02 PM PST 24
Finished Mar 07 12:28:04 PM PST 24
Peak memory 182968 kb
Host smart-b421f0c5-7770-4b79-9df1-b0d958366e11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521095776 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.2521095776
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.2837865918
Short name T314
Test name
Test status
Simulation time 1241486388 ps
CPU time 1.1 seconds
Started Mar 07 12:27:35 PM PST 24
Finished Mar 07 12:27:36 PM PST 24
Peak memory 182756 kb
Host smart-4ccab5f9-ac74-44b9-83fd-ea10a448bb40
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837865918 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.ao
n_timer_same_csr_outstanding.2837865918
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.1664292304
Short name T368
Test name
Test status
Simulation time 405544272 ps
CPU time 0.92 seconds
Started Mar 07 12:27:42 PM PST 24
Finished Mar 07 12:27:43 PM PST 24
Peak memory 195876 kb
Host smart-95cfca6a-b382-486c-96cf-252a0c79cbc6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664292304 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.1664292304
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.1735419982
Short name T392
Test name
Test status
Simulation time 8331122586 ps
CPU time 14.88 seconds
Started Mar 07 12:27:31 PM PST 24
Finished Mar 07 12:27:46 PM PST 24
Peak memory 197240 kb
Host smart-f1b7d209-7261-4bf2-bbfb-94f09dd8a3c8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735419982 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_t
l_intg_err.1735419982
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.2219461010
Short name T403
Test name
Test status
Simulation time 526318409 ps
CPU time 1.49 seconds
Started Mar 07 12:27:46 PM PST 24
Finished Mar 07 12:27:48 PM PST 24
Peak memory 194388 kb
Host smart-da862aeb-1af4-41f4-8cf3-35f2ee02c7dc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219461010 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.2219461010
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.1893869504
Short name T85
Test name
Test status
Simulation time 471695788 ps
CPU time 1.22 seconds
Started Mar 07 12:28:00 PM PST 24
Finished Mar 07 12:28:01 PM PST 24
Peak memory 182944 kb
Host smart-61cf9fad-a115-4eb2-a69e-00d58595e2a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893869504 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.1893869504
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.3251670385
Short name T381
Test name
Test status
Simulation time 321354900 ps
CPU time 1.08 seconds
Started Mar 07 12:27:42 PM PST 24
Finished Mar 07 12:27:44 PM PST 24
Peak memory 181636 kb
Host smart-24c27c4c-8b46-4aac-b24f-67247304276d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251670385 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.3251670385
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.3458653701
Short name T413
Test name
Test status
Simulation time 1538202764 ps
CPU time 1.07 seconds
Started Mar 07 12:28:02 PM PST 24
Finished Mar 07 12:28:04 PM PST 24
Peak memory 192756 kb
Host smart-40c7c3a8-54bd-4262-9c66-b03ac3647f2d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458653701 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.ao
n_timer_same_csr_outstanding.3458653701
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.2300073977
Short name T333
Test name
Test status
Simulation time 1116971469 ps
CPU time 2.08 seconds
Started Mar 07 12:27:37 PM PST 24
Finished Mar 07 12:27:39 PM PST 24
Peak memory 197948 kb
Host smart-fe23682a-b6ed-4ae4-8101-f15a9f019a21
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300073977 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.2300073977
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.928977143
Short name T103
Test name
Test status
Simulation time 4457663467 ps
CPU time 2.62 seconds
Started Mar 07 12:27:28 PM PST 24
Finished Mar 07 12:27:31 PM PST 24
Peak memory 196680 kb
Host smart-8c6dee83-4e22-4d1f-8ad6-f7157e638fb0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928977143 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl
_intg_err.928977143
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.57693563
Short name T301
Test name
Test status
Simulation time 481036287 ps
CPU time 0.77 seconds
Started Mar 07 12:27:49 PM PST 24
Finished Mar 07 12:27:50 PM PST 24
Peak memory 195204 kb
Host smart-51a3dd4a-cf37-45ef-8c60-7fd31cb0b9f8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57693563 -assert nopostproc +UVM_TESTNAME=a
on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.57693563
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.2129540284
Short name T66
Test name
Test status
Simulation time 471167078 ps
CPU time 0.91 seconds
Started Mar 07 12:28:00 PM PST 24
Finished Mar 07 12:28:01 PM PST 24
Peak memory 183072 kb
Host smart-7a474c8d-6b6e-4f4e-8378-c8c71f3eb67b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129540284 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.2129540284
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.2770851583
Short name T341
Test name
Test status
Simulation time 321342518 ps
CPU time 1 seconds
Started Mar 07 12:27:54 PM PST 24
Finished Mar 07 12:27:56 PM PST 24
Peak memory 182876 kb
Host smart-a5a398e3-f33e-47b6-bb77-642cdc9f5f1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770851583 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.2770851583
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.2495292721
Short name T374
Test name
Test status
Simulation time 1805004535 ps
CPU time 1.81 seconds
Started Mar 07 12:27:51 PM PST 24
Finished Mar 07 12:27:53 PM PST 24
Peak memory 191440 kb
Host smart-5b592906-3267-493e-988c-690553d881dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495292721 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.ao
n_timer_same_csr_outstanding.2495292721
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.1850944206
Short name T312
Test name
Test status
Simulation time 530750477 ps
CPU time 2.1 seconds
Started Mar 07 12:27:52 PM PST 24
Finished Mar 07 12:27:54 PM PST 24
Peak memory 197912 kb
Host smart-eb53eaee-3048-4f60-8bfb-fd99e0776fca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850944206 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.1850944206
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.160393905
Short name T420
Test name
Test status
Simulation time 8062557044 ps
CPU time 4.15 seconds
Started Mar 07 12:28:00 PM PST 24
Finished Mar 07 12:28:04 PM PST 24
Peak memory 197124 kb
Host smart-2aed3b76-7c40-411a-b33e-c4e2426967ad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160393905 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl
_intg_err.160393905
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.1327058362
Short name T351
Test name
Test status
Simulation time 441346237 ps
CPU time 1.2 seconds
Started Mar 07 12:27:54 PM PST 24
Finished Mar 07 12:27:55 PM PST 24
Peak memory 194908 kb
Host smart-b74e71bc-91a5-4f53-bb97-1dc3e5c2b38e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327058362 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.1327058362
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.3241827189
Short name T86
Test name
Test status
Simulation time 397682265 ps
CPU time 0.69 seconds
Started Mar 07 12:27:51 PM PST 24
Finished Mar 07 12:27:52 PM PST 24
Peak memory 183172 kb
Host smart-3f140124-c77a-4887-bf6d-6218daa1dff4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241827189 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.3241827189
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.3551197268
Short name T339
Test name
Test status
Simulation time 324845376 ps
CPU time 0.67 seconds
Started Mar 07 12:28:07 PM PST 24
Finished Mar 07 12:28:09 PM PST 24
Peak memory 182824 kb
Host smart-70152abc-3c9b-4e3e-b4d5-154badf195e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551197268 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.3551197268
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.1089216483
Short name T394
Test name
Test status
Simulation time 1408487308 ps
CPU time 1.68 seconds
Started Mar 07 12:27:48 PM PST 24
Finished Mar 07 12:27:50 PM PST 24
Peak memory 192440 kb
Host smart-bf92f3cd-c60e-4974-a758-fa9dcf1c3e62
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089216483 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.ao
n_timer_same_csr_outstanding.1089216483
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.410876595
Short name T335
Test name
Test status
Simulation time 531055894 ps
CPU time 1.41 seconds
Started Mar 07 12:28:56 PM PST 24
Finished Mar 07 12:28:58 PM PST 24
Peak memory 195936 kb
Host smart-dcd5b00c-3f9f-40e8-af5c-11380dddd29d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410876595 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.410876595
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.2192121830
Short name T104
Test name
Test status
Simulation time 4550090285 ps
CPU time 2.86 seconds
Started Mar 07 12:27:49 PM PST 24
Finished Mar 07 12:27:52 PM PST 24
Peak memory 196612 kb
Host smart-0b14ce63-0a05-4106-ab67-7c4976e0e180
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192121830 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_t
l_intg_err.2192121830
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.1282195194
Short name T418
Test name
Test status
Simulation time 491390022 ps
CPU time 1.59 seconds
Started Mar 07 12:28:02 PM PST 24
Finished Mar 07 12:28:04 PM PST 24
Peak memory 195100 kb
Host smart-798d2920-130f-417d-9e83-a518b2626dd1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282195194 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.1282195194
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.1749216582
Short name T370
Test name
Test status
Simulation time 513907791 ps
CPU time 0.73 seconds
Started Mar 07 12:27:48 PM PST 24
Finished Mar 07 12:27:50 PM PST 24
Peak memory 182972 kb
Host smart-039a8e9f-90e3-40ab-955c-6c44e96d7a14
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749216582 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.1749216582
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.2177712838
Short name T297
Test name
Test status
Simulation time 485495193 ps
CPU time 1.21 seconds
Started Mar 07 12:27:48 PM PST 24
Finished Mar 07 12:27:49 PM PST 24
Peak memory 182864 kb
Host smart-2e6a9e73-7cd8-432b-9b17-710bb0492b15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177712838 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.2177712838
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.1371785181
Short name T375
Test name
Test status
Simulation time 1403250988 ps
CPU time 3.87 seconds
Started Mar 07 12:27:46 PM PST 24
Finished Mar 07 12:27:51 PM PST 24
Peak memory 183160 kb
Host smart-b8dc75b2-5abb-4792-89db-923b6654358a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371785181 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao
n_timer_same_csr_outstanding.1371785181
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.2702485599
Short name T323
Test name
Test status
Simulation time 414577806 ps
CPU time 2.55 seconds
Started Mar 07 12:28:03 PM PST 24
Finished Mar 07 12:28:06 PM PST 24
Peak memory 197772 kb
Host smart-53ff6441-3b14-4372-883e-6ce05ea44330
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702485599 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.2702485599
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.2260756713
Short name T35
Test name
Test status
Simulation time 4733926163 ps
CPU time 2.32 seconds
Started Mar 07 12:27:51 PM PST 24
Finished Mar 07 12:27:54 PM PST 24
Peak memory 195728 kb
Host smart-ac495537-f349-44fa-a9bc-ac87fcf77f52
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260756713 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_t
l_intg_err.2260756713
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.2825466129
Short name T367
Test name
Test status
Simulation time 487247037 ps
CPU time 0.85 seconds
Started Mar 07 12:27:42 PM PST 24
Finished Mar 07 12:27:43 PM PST 24
Peak memory 182268 kb
Host smart-1fed9441-af39-4ec7-bf95-88cf3f3a130b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825466129 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_a
liasing.2825466129
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.1093255569
Short name T308
Test name
Test status
Simulation time 7566073509 ps
CPU time 2.85 seconds
Started Mar 07 12:27:10 PM PST 24
Finished Mar 07 12:27:13 PM PST 24
Peak memory 191536 kb
Host smart-f7b6e99a-f4e2-4a9c-ae1d-a893e85a0c75
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093255569 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_b
it_bash.1093255569
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.3852542967
Short name T422
Test name
Test status
Simulation time 1054754969 ps
CPU time 1.89 seconds
Started Mar 07 12:27:13 PM PST 24
Finished Mar 07 12:27:15 PM PST 24
Peak memory 182972 kb
Host smart-a8c56886-82e1-40d9-962c-6888375910fb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852542967 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_h
w_reset.3852542967
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.2466353734
Short name T31
Test name
Test status
Simulation time 341166682 ps
CPU time 1.2 seconds
Started Mar 07 12:27:10 PM PST 24
Finished Mar 07 12:27:11 PM PST 24
Peak memory 194872 kb
Host smart-177cae5e-a935-4b7c-826b-222d3c0c9e5d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466353734 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.2466353734
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.805289575
Short name T391
Test name
Test status
Simulation time 326377778 ps
CPU time 1.05 seconds
Started Mar 07 12:27:17 PM PST 24
Finished Mar 07 12:27:19 PM PST 24
Peak memory 192448 kb
Host smart-673bf809-1c8e-4767-80a6-3378584e47e9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805289575 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.805289575
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.3510302195
Short name T304
Test name
Test status
Simulation time 311098288 ps
CPU time 0.96 seconds
Started Mar 07 12:27:11 PM PST 24
Finished Mar 07 12:27:12 PM PST 24
Peak memory 182860 kb
Host smart-ef08c8ad-7486-41e5-a198-9382509d42e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510302195 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.3510302195
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.1246204645
Short name T328
Test name
Test status
Simulation time 324709853 ps
CPU time 0.57 seconds
Started Mar 07 12:27:10 PM PST 24
Finished Mar 07 12:27:11 PM PST 24
Peak memory 182152 kb
Host smart-d31b2de9-870c-4ee8-ab47-e80efb67d2e4
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246204645 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_t
imer_mem_partial_access.1246204645
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.2794308481
Short name T286
Test name
Test status
Simulation time 502432334 ps
CPU time 1.32 seconds
Started Mar 07 12:28:47 PM PST 24
Finished Mar 07 12:28:48 PM PST 24
Peak memory 181972 kb
Host smart-eacaca40-c5f5-400f-9e9c-787b1073869b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794308481 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_w
alk.2794308481
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.871826474
Short name T344
Test name
Test status
Simulation time 1430255941 ps
CPU time 1.49 seconds
Started Mar 07 12:27:12 PM PST 24
Finished Mar 07 12:27:13 PM PST 24
Peak memory 182944 kb
Host smart-81670d61-29b0-4c57-bc06-00c56236d7ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871826474 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_
timer_same_csr_outstanding.871826474
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.2871803190
Short name T396
Test name
Test status
Simulation time 401714008 ps
CPU time 1.2 seconds
Started Mar 07 12:27:06 PM PST 24
Finished Mar 07 12:27:07 PM PST 24
Peak memory 197564 kb
Host smart-24fe17de-4d54-43c2-85cb-c0644b0663e7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871803190 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.2871803190
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.2611583067
Short name T356
Test name
Test status
Simulation time 388485328 ps
CPU time 0.68 seconds
Started Mar 07 12:27:42 PM PST 24
Finished Mar 07 12:27:43 PM PST 24
Peak memory 182968 kb
Host smart-7285d4f9-f1f7-4260-a2db-888a7ccaab46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611583067 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.2611583067
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.42673132
Short name T290
Test name
Test status
Simulation time 463881730 ps
CPU time 0.74 seconds
Started Mar 07 12:27:50 PM PST 24
Finished Mar 07 12:27:51 PM PST 24
Peak memory 182860 kb
Host smart-ac694927-547f-4b8f-9a98-2f88a70b1b26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42673132 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.42673132
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.3619087070
Short name T362
Test name
Test status
Simulation time 431666445 ps
CPU time 1.06 seconds
Started Mar 07 12:27:47 PM PST 24
Finished Mar 07 12:27:49 PM PST 24
Peak memory 182916 kb
Host smart-06a671a0-71e2-4c41-aa1b-2e968b622a20
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619087070 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.3619087070
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.555116196
Short name T292
Test name
Test status
Simulation time 484288271 ps
CPU time 1.26 seconds
Started Mar 07 12:28:13 PM PST 24
Finished Mar 07 12:28:14 PM PST 24
Peak memory 182988 kb
Host smart-9bd9c80a-5b79-4fe0-9e6c-ce0f630d48af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555116196 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.555116196
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.278681838
Short name T313
Test name
Test status
Simulation time 515710014 ps
CPU time 1.27 seconds
Started Mar 07 12:27:57 PM PST 24
Finished Mar 07 12:27:59 PM PST 24
Peak memory 182940 kb
Host smart-73de74ea-420d-43a7-be18-5ae32e366973
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278681838 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.278681838
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.2572281101
Short name T350
Test name
Test status
Simulation time 404969257 ps
CPU time 1.03 seconds
Started Mar 07 12:29:53 PM PST 24
Finished Mar 07 12:29:54 PM PST 24
Peak memory 182788 kb
Host smart-028bb2e1-d39f-435c-a68c-b3e9c2ce5a28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572281101 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.2572281101
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.3956598945
Short name T360
Test name
Test status
Simulation time 517411635 ps
CPU time 1.31 seconds
Started Mar 07 12:29:36 PM PST 24
Finished Mar 07 12:29:38 PM PST 24
Peak memory 181176 kb
Host smart-d2865ebf-713b-443d-8a07-fbdbef95e42a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956598945 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.3956598945
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.2512566210
Short name T398
Test name
Test status
Simulation time 405106459 ps
CPU time 0.69 seconds
Started Mar 07 12:27:53 PM PST 24
Finished Mar 07 12:27:54 PM PST 24
Peak memory 182944 kb
Host smart-97df0ec1-8e0b-4dba-b78d-1d8fe28aff1e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512566210 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.2512566210
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.3293425714
Short name T342
Test name
Test status
Simulation time 309047123 ps
CPU time 0.77 seconds
Started Mar 07 12:27:49 PM PST 24
Finished Mar 07 12:27:50 PM PST 24
Peak memory 182016 kb
Host smart-39161ace-576a-4f0b-83c7-929bafa05aea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293425714 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.3293425714
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.1386265245
Short name T310
Test name
Test status
Simulation time 415059390 ps
CPU time 0.7 seconds
Started Mar 07 12:29:36 PM PST 24
Finished Mar 07 12:29:37 PM PST 24
Peak memory 180868 kb
Host smart-8631f1e5-cf0f-40a0-93b8-59300c51478a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386265245 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.1386265245
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.42832186
Short name T65
Test name
Test status
Simulation time 339353596 ps
CPU time 1.11 seconds
Started Mar 07 12:27:45 PM PST 24
Finished Mar 07 12:27:46 PM PST 24
Peak memory 183012 kb
Host smart-1509dbfa-9108-4176-877f-29c63986dcb1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42832186 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_ali
asing.42832186
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.3752425437
Short name T62
Test name
Test status
Simulation time 1035387897 ps
CPU time 1.42 seconds
Started Mar 07 12:27:12 PM PST 24
Finished Mar 07 12:27:13 PM PST 24
Peak memory 183208 kb
Host smart-08888001-4344-414a-a82a-08dd884fc554
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752425437 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_b
it_bash.3752425437
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.3402038749
Short name T390
Test name
Test status
Simulation time 1183034066 ps
CPU time 1.06 seconds
Started Mar 07 12:27:41 PM PST 24
Finished Mar 07 12:27:43 PM PST 24
Peak memory 183104 kb
Host smart-69bfbf9e-1134-4e8f-a772-02adad046993
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402038749 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_h
w_reset.3402038749
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.3043563932
Short name T359
Test name
Test status
Simulation time 465281289 ps
CPU time 1.36 seconds
Started Mar 07 12:27:09 PM PST 24
Finished Mar 07 12:27:11 PM PST 24
Peak memory 194836 kb
Host smart-40f12a1e-8178-4f2a-aacd-cef679b0b2c3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043563932 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.3043563932
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.3097621132
Short name T61
Test name
Test status
Simulation time 446536912 ps
CPU time 0.76 seconds
Started Mar 07 12:27:41 PM PST 24
Finished Mar 07 12:27:43 PM PST 24
Peak memory 183104 kb
Host smart-c628b47c-f023-4cb9-a912-078252765c0e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097621132 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.3097621132
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.3877863004
Short name T408
Test name
Test status
Simulation time 326834160 ps
CPU time 0.67 seconds
Started Mar 07 12:27:48 PM PST 24
Finished Mar 07 12:27:49 PM PST 24
Peak memory 182860 kb
Host smart-573785e4-f459-45af-bc2d-ec123adad218
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877863004 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.3877863004
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.543208036
Short name T423
Test name
Test status
Simulation time 357278217 ps
CPU time 0.76 seconds
Started Mar 07 12:28:08 PM PST 24
Finished Mar 07 12:28:09 PM PST 24
Peak memory 182056 kb
Host smart-af344933-3836-4165-9a68-2939f17a9ffe
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543208036 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_ti
mer_mem_partial_access.543208036
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.2761295372
Short name T305
Test name
Test status
Simulation time 410267197 ps
CPU time 1.12 seconds
Started Mar 07 12:27:09 PM PST 24
Finished Mar 07 12:27:10 PM PST 24
Peak memory 182104 kb
Host smart-c76263bf-eebb-42b2-883f-87f28b6a9c2a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761295372 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_w
alk.2761295372
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.3910416201
Short name T33
Test name
Test status
Simulation time 2311257256 ps
CPU time 1.14 seconds
Started Mar 07 12:29:08 PM PST 24
Finished Mar 07 12:29:09 PM PST 24
Peak memory 193852 kb
Host smart-bb2d9b49-c874-4648-b030-a93d49db26c8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910416201 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon
_timer_same_csr_outstanding.3910416201
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.3812304953
Short name T395
Test name
Test status
Simulation time 460171314 ps
CPU time 2.36 seconds
Started Mar 07 12:27:31 PM PST 24
Finished Mar 07 12:27:34 PM PST 24
Peak memory 197932 kb
Host smart-987435af-a215-45cb-b560-40da06c712be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812304953 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.3812304953
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.2161377271
Short name T383
Test name
Test status
Simulation time 4477756974 ps
CPU time 7.18 seconds
Started Mar 07 12:27:11 PM PST 24
Finished Mar 07 12:27:18 PM PST 24
Peak memory 196652 kb
Host smart-cc04ea8c-a48f-4242-b155-2b1fd45c57a0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161377271 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl
_intg_err.2161377271
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.912348415
Short name T361
Test name
Test status
Simulation time 392993108 ps
CPU time 0.63 seconds
Started Mar 07 12:29:51 PM PST 24
Finished Mar 07 12:29:52 PM PST 24
Peak memory 182788 kb
Host smart-9a67617a-a51f-407f-8b5b-2f79cb07c40f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912348415 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.912348415
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.896887575
Short name T417
Test name
Test status
Simulation time 413936335 ps
CPU time 0.82 seconds
Started Mar 07 12:28:17 PM PST 24
Finished Mar 07 12:28:20 PM PST 24
Peak memory 182012 kb
Host smart-91c4fce7-0156-400f-85ec-3eb9b2b32d8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896887575 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.896887575
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.2324568780
Short name T421
Test name
Test status
Simulation time 350458330 ps
CPU time 1.1 seconds
Started Mar 07 12:28:13 PM PST 24
Finished Mar 07 12:28:14 PM PST 24
Peak memory 182936 kb
Host smart-7f0d9f4f-d35d-4243-9073-68a6c265378d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324568780 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.2324568780
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.1023498139
Short name T299
Test name
Test status
Simulation time 376155444 ps
CPU time 0.85 seconds
Started Mar 07 12:27:56 PM PST 24
Finished Mar 07 12:27:57 PM PST 24
Peak memory 182940 kb
Host smart-13b2ea1f-70c7-4ce3-a8c9-2c38e4c81932
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023498139 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.1023498139
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.4089376437
Short name T332
Test name
Test status
Simulation time 411488623 ps
CPU time 0.93 seconds
Started Mar 07 12:28:11 PM PST 24
Finished Mar 07 12:28:12 PM PST 24
Peak memory 182864 kb
Host smart-4ea4603f-ea02-41b3-8860-f82572122ca9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089376437 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.4089376437
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.197592191
Short name T327
Test name
Test status
Simulation time 284360664 ps
CPU time 0.88 seconds
Started Mar 07 12:29:36 PM PST 24
Finished Mar 07 12:29:38 PM PST 24
Peak memory 180852 kb
Host smart-d0bed14c-132f-4f1a-a187-c56b750e59dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197592191 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.197592191
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.4010198204
Short name T330
Test name
Test status
Simulation time 324043471 ps
CPU time 1.05 seconds
Started Mar 07 12:28:02 PM PST 24
Finished Mar 07 12:28:03 PM PST 24
Peak memory 182832 kb
Host smart-9b00e3ef-c5b3-490c-beff-dbc129fecf27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010198204 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.4010198204
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.1933026770
Short name T322
Test name
Test status
Simulation time 358919165 ps
CPU time 0.94 seconds
Started Mar 07 12:28:02 PM PST 24
Finished Mar 07 12:28:04 PM PST 24
Peak memory 182936 kb
Host smart-1d4e9a93-eaab-44d6-ac45-c85acf90067e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933026770 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.1933026770
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.3075262640
Short name T293
Test name
Test status
Simulation time 399013544 ps
CPU time 0.83 seconds
Started Mar 07 12:28:03 PM PST 24
Finished Mar 07 12:28:04 PM PST 24
Peak memory 182944 kb
Host smart-d3516953-5604-45ce-8d92-8ed992d25202
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075262640 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.3075262640
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.1513409117
Short name T345
Test name
Test status
Simulation time 447561231 ps
CPU time 0.84 seconds
Started Mar 07 12:27:54 PM PST 24
Finished Mar 07 12:27:55 PM PST 24
Peak memory 182944 kb
Host smart-7b4dbfb5-31e9-4cf2-be3e-2998ee337134
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513409117 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.1513409117
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.2624441836
Short name T70
Test name
Test status
Simulation time 625768393 ps
CPU time 1.25 seconds
Started Mar 07 12:27:00 PM PST 24
Finished Mar 07 12:27:02 PM PST 24
Peak memory 193564 kb
Host smart-2d5a92c7-d7e8-42f4-9065-90c6f6526f2a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624441836 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_a
liasing.2624441836
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.2772670920
Short name T366
Test name
Test status
Simulation time 13845747734 ps
CPU time 39.7 seconds
Started Mar 07 12:27:18 PM PST 24
Finished Mar 07 12:27:58 PM PST 24
Peak memory 191488 kb
Host smart-6df1968b-9e30-474f-8c1f-0c30a16be2bc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772670920 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_b
it_bash.2772670920
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.1956129731
Short name T369
Test name
Test status
Simulation time 1285885996 ps
CPU time 1.54 seconds
Started Mar 07 12:27:08 PM PST 24
Finished Mar 07 12:27:10 PM PST 24
Peak memory 192484 kb
Host smart-efa83b6a-0f7a-4c0c-90b6-1ffafe3bb347
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956129731 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_h
w_reset.1956129731
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.1616252846
Short name T338
Test name
Test status
Simulation time 371133263 ps
CPU time 1.33 seconds
Started Mar 07 12:27:05 PM PST 24
Finished Mar 07 12:27:07 PM PST 24
Peak memory 195072 kb
Host smart-519a8b21-3ee9-498d-a20b-b5177e65733b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616252846 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.1616252846
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.366250992
Short name T59
Test name
Test status
Simulation time 440947196 ps
CPU time 0.75 seconds
Started Mar 07 12:27:05 PM PST 24
Finished Mar 07 12:27:06 PM PST 24
Peak memory 183072 kb
Host smart-a3ea86ba-f849-4d87-9afd-6ee44f77a868
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366250992 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.366250992
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.4188709318
Short name T380
Test name
Test status
Simulation time 504817880 ps
CPU time 1.31 seconds
Started Mar 07 12:27:19 PM PST 24
Finished Mar 07 12:27:20 PM PST 24
Peak memory 182832 kb
Host smart-9955be32-59d6-45e0-89fe-a430d32db1a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188709318 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.4188709318
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.668509375
Short name T385
Test name
Test status
Simulation time 424848370 ps
CPU time 1.12 seconds
Started Mar 07 12:27:15 PM PST 24
Finished Mar 07 12:27:16 PM PST 24
Peak memory 182056 kb
Host smart-570e8f0e-da3c-4979-af0f-2861f5707900
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668509375 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_ti
mer_mem_partial_access.668509375
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.383880853
Short name T379
Test name
Test status
Simulation time 518847948 ps
CPU time 0.82 seconds
Started Mar 07 12:27:21 PM PST 24
Finished Mar 07 12:27:22 PM PST 24
Peak memory 182968 kb
Host smart-0ecec16c-1aaf-4314-9415-4b5e9350d951
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383880853 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_wa
lk.383880853
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.1489388167
Short name T334
Test name
Test status
Simulation time 1832235662 ps
CPU time 3.63 seconds
Started Mar 07 12:27:08 PM PST 24
Finished Mar 07 12:27:12 PM PST 24
Peak memory 183120 kb
Host smart-346008f5-66b0-4629-942c-5c8312e707cc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489388167 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon
_timer_same_csr_outstanding.1489388167
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.1411173772
Short name T311
Test name
Test status
Simulation time 442071514 ps
CPU time 2.1 seconds
Started Mar 07 12:28:08 PM PST 24
Finished Mar 07 12:28:11 PM PST 24
Peak memory 197840 kb
Host smart-32fa12c3-8107-4ed2-a03a-1ccfb9f69f52
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411173772 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.1411173772
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.1845562807
Short name T412
Test name
Test status
Simulation time 8635100953 ps
CPU time 8.28 seconds
Started Mar 07 12:27:09 PM PST 24
Finished Mar 07 12:27:18 PM PST 24
Peak memory 197084 kb
Host smart-00c01fa7-41d3-4c21-bded-039f14c88c4c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845562807 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl
_intg_err.1845562807
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.3084081514
Short name T329
Test name
Test status
Simulation time 504798177 ps
CPU time 1.22 seconds
Started Mar 07 12:28:12 PM PST 24
Finished Mar 07 12:28:13 PM PST 24
Peak memory 182936 kb
Host smart-e90e393a-ce1d-4c73-a5bb-93c86b81bbbf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084081514 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.3084081514
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.1607884084
Short name T352
Test name
Test status
Simulation time 384383349 ps
CPU time 0.81 seconds
Started Mar 07 12:28:08 PM PST 24
Finished Mar 07 12:28:09 PM PST 24
Peak memory 182940 kb
Host smart-82e8dd8f-fc5a-420b-b496-b4cf11c16eea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607884084 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.1607884084
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.4113232845
Short name T296
Test name
Test status
Simulation time 408416819 ps
CPU time 1.15 seconds
Started Mar 07 12:28:06 PM PST 24
Finished Mar 07 12:28:08 PM PST 24
Peak memory 182824 kb
Host smart-25021a16-73dc-4506-8686-05bcd1dd5b0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113232845 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.4113232845
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.135038713
Short name T284
Test name
Test status
Simulation time 398150306 ps
CPU time 0.86 seconds
Started Mar 07 12:28:03 PM PST 24
Finished Mar 07 12:28:04 PM PST 24
Peak memory 182940 kb
Host smart-8870b612-53cc-489a-b145-cad461c60920
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135038713 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.135038713
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.1445160770
Short name T377
Test name
Test status
Simulation time 374847007 ps
CPU time 0.62 seconds
Started Mar 07 12:28:11 PM PST 24
Finished Mar 07 12:28:12 PM PST 24
Peak memory 182864 kb
Host smart-ce83a1be-acff-48cd-9ece-e9765a86aa99
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445160770 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.1445160770
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.1033291711
Short name T409
Test name
Test status
Simulation time 432157716 ps
CPU time 0.82 seconds
Started Mar 07 12:29:51 PM PST 24
Finished Mar 07 12:29:52 PM PST 24
Peak memory 182840 kb
Host smart-6d5cf17d-c50f-4739-94d2-8867b88fd8f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033291711 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.1033291711
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.194405959
Short name T303
Test name
Test status
Simulation time 488364624 ps
CPU time 0.69 seconds
Started Mar 07 12:27:50 PM PST 24
Finished Mar 07 12:27:51 PM PST 24
Peak memory 182860 kb
Host smart-8256628a-357a-43fb-b500-6cdf31c88c5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194405959 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.194405959
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.1601983220
Short name T291
Test name
Test status
Simulation time 336391144 ps
CPU time 1.11 seconds
Started Mar 07 12:28:08 PM PST 24
Finished Mar 07 12:28:09 PM PST 24
Peak memory 182812 kb
Host smart-3d19b3c4-a305-49c6-9ebf-5a7de3c9b249
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601983220 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.1601983220
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.1421725692
Short name T325
Test name
Test status
Simulation time 439670133 ps
CPU time 0.65 seconds
Started Mar 07 12:28:00 PM PST 24
Finished Mar 07 12:28:01 PM PST 24
Peak memory 182812 kb
Host smart-c9129bd4-3a2e-4874-8ff8-e43acd279655
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421725692 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.1421725692
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.3753425046
Short name T349
Test name
Test status
Simulation time 481816377 ps
CPU time 1.23 seconds
Started Mar 07 12:29:53 PM PST 24
Finished Mar 07 12:29:54 PM PST 24
Peak memory 182784 kb
Host smart-ab493bc4-5a19-4ff5-ad3b-cf04b8c915f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753425046 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.3753425046
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.3454492194
Short name T384
Test name
Test status
Simulation time 597538553 ps
CPU time 0.9 seconds
Started Mar 07 12:27:39 PM PST 24
Finished Mar 07 12:27:40 PM PST 24
Peak memory 194556 kb
Host smart-7bd88990-db47-4f08-b731-914de881a8c2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454492194 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.3454492194
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.4077067528
Short name T414
Test name
Test status
Simulation time 340546243 ps
CPU time 0.72 seconds
Started Mar 07 12:27:11 PM PST 24
Finished Mar 07 12:27:12 PM PST 24
Peak memory 182936 kb
Host smart-cf04653a-3bf8-4f2e-ba30-4c30999d7cd1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077067528 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.4077067528
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.2161540222
Short name T285
Test name
Test status
Simulation time 447647284 ps
CPU time 0.9 seconds
Started Mar 07 12:27:11 PM PST 24
Finished Mar 07 12:27:12 PM PST 24
Peak memory 182808 kb
Host smart-7fea4670-1475-46cb-9006-9ac580ad16f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161540222 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.2161540222
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.3770788010
Short name T393
Test name
Test status
Simulation time 2349283865 ps
CPU time 6.72 seconds
Started Mar 07 12:28:29 PM PST 24
Finished Mar 07 12:28:40 PM PST 24
Peak memory 193860 kb
Host smart-bfdb5e3d-8f6a-4cb6-b95a-eaa780c39670
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770788010 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon
_timer_same_csr_outstanding.3770788010
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.3798986334
Short name T319
Test name
Test status
Simulation time 336354991 ps
CPU time 2.33 seconds
Started Mar 07 12:27:31 PM PST 24
Finished Mar 07 12:27:33 PM PST 24
Peak memory 197832 kb
Host smart-71a6ddd0-1dd7-419a-afce-29e710de4f9a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798986334 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.3798986334
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.3882799636
Short name T106
Test name
Test status
Simulation time 8521692754 ps
CPU time 15.53 seconds
Started Mar 07 12:27:31 PM PST 24
Finished Mar 07 12:27:47 PM PST 24
Peak memory 197128 kb
Host smart-3f9bf6fa-8108-4282-9b47-9a3a31cac863
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882799636 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl
_intg_err.3882799636
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.1864147321
Short name T287
Test name
Test status
Simulation time 522694827 ps
CPU time 1.35 seconds
Started Mar 07 12:27:49 PM PST 24
Finished Mar 07 12:27:51 PM PST 24
Peak memory 194356 kb
Host smart-5a6be5fd-150f-48b2-b479-52c6693919b4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864147321 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.1864147321
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.584657730
Short name T407
Test name
Test status
Simulation time 358107814 ps
CPU time 1.03 seconds
Started Mar 07 12:27:21 PM PST 24
Finished Mar 07 12:27:22 PM PST 24
Peak memory 182284 kb
Host smart-69069c34-91cd-4173-82a2-5b7347baa1e5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584657730 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.584657730
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.4236065986
Short name T331
Test name
Test status
Simulation time 610679586 ps
CPU time 0.59 seconds
Started Mar 07 12:28:55 PM PST 24
Finished Mar 07 12:28:56 PM PST 24
Peak memory 182800 kb
Host smart-ea93cd1b-8cc0-4c78-8935-db9ac8e3ff7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236065986 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.4236065986
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.894817801
Short name T84
Test name
Test status
Simulation time 1302779443 ps
CPU time 1.53 seconds
Started Mar 07 12:27:18 PM PST 24
Finished Mar 07 12:27:20 PM PST 24
Peak memory 192704 kb
Host smart-2fe3eefa-fe1b-440d-9c33-a4348e3d0b6e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894817801 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_
timer_same_csr_outstanding.894817801
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.3491274690
Short name T405
Test name
Test status
Simulation time 328780593 ps
CPU time 1 seconds
Started Mar 07 12:27:09 PM PST 24
Finished Mar 07 12:27:10 PM PST 24
Peak memory 197088 kb
Host smart-253a1978-454e-4e36-b7b7-eb51fca39e66
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491274690 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.3491274690
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.2443585846
Short name T373
Test name
Test status
Simulation time 8663161863 ps
CPU time 14.9 seconds
Started Mar 07 12:27:09 PM PST 24
Finished Mar 07 12:27:24 PM PST 24
Peak memory 197132 kb
Host smart-9312f4f6-fd85-44ed-b67c-cc53e4e2045c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443585846 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl
_intg_err.2443585846
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.357515136
Short name T337
Test name
Test status
Simulation time 510942071 ps
CPU time 1.44 seconds
Started Mar 07 12:28:22 PM PST 24
Finished Mar 07 12:28:24 PM PST 24
Peak memory 194444 kb
Host smart-931506c9-88ad-4cef-8bb9-18a73e6bfac2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357515136 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.357515136
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.4259806454
Short name T295
Test name
Test status
Simulation time 333888428 ps
CPU time 0.79 seconds
Started Mar 07 12:27:21 PM PST 24
Finished Mar 07 12:27:22 PM PST 24
Peak memory 183040 kb
Host smart-16f350fb-42ea-418a-9f3f-bacd3a17a73b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259806454 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.4259806454
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.295945895
Short name T401
Test name
Test status
Simulation time 513054965 ps
CPU time 1.24 seconds
Started Mar 07 12:27:23 PM PST 24
Finished Mar 07 12:27:24 PM PST 24
Peak memory 182808 kb
Host smart-9efbfbc6-2a32-4eb7-812d-a4b446cb4bd3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295945895 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.295945895
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.2528115211
Short name T83
Test name
Test status
Simulation time 2141449953 ps
CPU time 3.77 seconds
Started Mar 07 12:27:11 PM PST 24
Finished Mar 07 12:27:15 PM PST 24
Peak memory 182380 kb
Host smart-580afcef-d413-4b7c-b87c-6553c459e6c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528115211 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon
_timer_same_csr_outstanding.2528115211
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.2696626633
Short name T298
Test name
Test status
Simulation time 558742319 ps
CPU time 1.7 seconds
Started Mar 07 12:27:11 PM PST 24
Finished Mar 07 12:27:13 PM PST 24
Peak memory 182176 kb
Host smart-035ada6c-debd-489c-bd5e-0ea1bd59d999
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696626633 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.2696626633
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.1876606204
Short name T34
Test name
Test status
Simulation time 4222065413 ps
CPU time 3.88 seconds
Started Mar 07 12:27:47 PM PST 24
Finished Mar 07 12:27:51 PM PST 24
Peak memory 195320 kb
Host smart-f9bc3e84-d860-46ae-801f-e9b0ae767bb5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876606204 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl
_intg_err.1876606204
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.2381385513
Short name T321
Test name
Test status
Simulation time 587268984 ps
CPU time 1.39 seconds
Started Mar 07 12:27:12 PM PST 24
Finished Mar 07 12:27:13 PM PST 24
Peak memory 194852 kb
Host smart-5eaebd88-e042-4372-b793-2856b57566e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381385513 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.2381385513
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.2543954345
Short name T364
Test name
Test status
Simulation time 510835157 ps
CPU time 1.38 seconds
Started Mar 07 12:27:21 PM PST 24
Finished Mar 07 12:27:23 PM PST 24
Peak memory 183152 kb
Host smart-654dcb04-1e38-471e-a8ca-2774ce2e768d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543954345 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.2543954345
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.2857821242
Short name T389
Test name
Test status
Simulation time 509611815 ps
CPU time 0.56 seconds
Started Mar 07 12:27:12 PM PST 24
Finished Mar 07 12:27:12 PM PST 24
Peak memory 182488 kb
Host smart-5e063bba-7e6a-4242-bedc-ccbe923eb579
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857821242 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.2857821242
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.1305394877
Short name T382
Test name
Test status
Simulation time 1969228892 ps
CPU time 2.42 seconds
Started Mar 07 12:28:15 PM PST 24
Finished Mar 07 12:28:17 PM PST 24
Peak memory 192660 kb
Host smart-1f0ac29e-0174-49b4-a4f6-354238c925d0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305394877 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon
_timer_same_csr_outstanding.1305394877
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.1441529015
Short name T358
Test name
Test status
Simulation time 569273756 ps
CPU time 2.87 seconds
Started Mar 07 12:27:21 PM PST 24
Finished Mar 07 12:27:24 PM PST 24
Peak memory 197136 kb
Host smart-e79901fe-d037-4482-8608-3b5a8bedce58
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441529015 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.1441529015
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.3150318054
Short name T387
Test name
Test status
Simulation time 8352993633 ps
CPU time 4.59 seconds
Started Mar 07 12:27:21 PM PST 24
Finished Mar 07 12:27:26 PM PST 24
Peak memory 197116 kb
Host smart-b742f9cc-6bc2-44b2-82e3-52a3a9a0becd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150318054 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl
_intg_err.3150318054
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.1658650016
Short name T29
Test name
Test status
Simulation time 453190062 ps
CPU time 0.99 seconds
Started Mar 07 12:27:16 PM PST 24
Finished Mar 07 12:27:18 PM PST 24
Peak memory 194648 kb
Host smart-781200c8-2d00-450b-83b5-c91f8666c47f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658650016 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.1658650016
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.2756380178
Short name T343
Test name
Test status
Simulation time 529552977 ps
CPU time 0.77 seconds
Started Mar 07 12:27:21 PM PST 24
Finished Mar 07 12:27:22 PM PST 24
Peak memory 183088 kb
Host smart-744c669a-a895-4918-9222-08d90aca24f5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756380178 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.2756380178
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.1944393074
Short name T419
Test name
Test status
Simulation time 450309436 ps
CPU time 0.74 seconds
Started Mar 07 12:27:11 PM PST 24
Finished Mar 07 12:27:12 PM PST 24
Peak memory 181680 kb
Host smart-5b80080d-2290-4ec4-99bb-fdf03d0f1447
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944393074 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.1944393074
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.2489321629
Short name T353
Test name
Test status
Simulation time 1655751075 ps
CPU time 2.19 seconds
Started Mar 07 12:27:49 PM PST 24
Finished Mar 07 12:27:51 PM PST 24
Peak memory 192648 kb
Host smart-335388e3-60bd-4fd7-8395-2d9078128ef2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489321629 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon
_timer_same_csr_outstanding.2489321629
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.202665382
Short name T283
Test name
Test status
Simulation time 749786287 ps
CPU time 1.54 seconds
Started Mar 07 12:27:27 PM PST 24
Finished Mar 07 12:27:29 PM PST 24
Peak memory 197808 kb
Host smart-8ecd4ce8-a22a-44c1-aeae-47c86574f14f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202665382 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.202665382
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.1750141081
Short name T416
Test name
Test status
Simulation time 8302546967 ps
CPU time 4.19 seconds
Started Mar 07 12:27:19 PM PST 24
Finished Mar 07 12:27:23 PM PST 24
Peak memory 197060 kb
Host smart-c2e0b38e-36c8-48d7-b023-459e186c5844
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750141081 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl
_intg_err.1750141081
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_jump.2729352679
Short name T128
Test name
Test status
Simulation time 440382041 ps
CPU time 0.72 seconds
Started Mar 07 12:29:05 PM PST 24
Finished Mar 07 12:29:06 PM PST 24
Peak memory 183784 kb
Host smart-d10dc6c5-2413-423b-8246-92fce614d57b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729352679 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.2729352679
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.1525938757
Short name T242
Test name
Test status
Simulation time 37981177882 ps
CPU time 47.48 seconds
Started Mar 07 12:29:04 PM PST 24
Finished Mar 07 12:29:52 PM PST 24
Peak memory 183928 kb
Host smart-2912614b-3ffb-449b-a60c-a8e063676d89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525938757 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.1525938757
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.3535671914
Short name T278
Test name
Test status
Simulation time 410570299 ps
CPU time 0.65 seconds
Started Mar 07 12:29:04 PM PST 24
Finished Mar 07 12:29:05 PM PST 24
Peak memory 183820 kb
Host smart-5c0b71ee-cf35-4f4a-b43f-71c65535ee9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535671914 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.3535671914
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.1617025737
Short name T154
Test name
Test status
Simulation time 133332618229 ps
CPU time 108.08 seconds
Started Mar 07 12:29:04 PM PST 24
Finished Mar 07 12:30:53 PM PST 24
Peak memory 183940 kb
Host smart-05a00cca-eb44-4b61-bb48-429dc7769ca5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617025737 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_a
ll.1617025737
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.1896891438
Short name T263
Test name
Test status
Simulation time 26743177005 ps
CPU time 197.08 seconds
Started Mar 07 12:29:05 PM PST 24
Finished Mar 07 12:32:22 PM PST 24
Peak memory 198828 kb
Host smart-23a38cda-31ea-4d99-9158-3babaf803546
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896891438 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.1896891438
Directory /workspace/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.aon_timer_jump.1011332417
Short name T179
Test name
Test status
Simulation time 510854097 ps
CPU time 0.67 seconds
Started Mar 07 12:29:05 PM PST 24
Finished Mar 07 12:29:06 PM PST 24
Peak memory 183788 kb
Host smart-5dc24cd5-ea33-4654-9dc6-35858929fcfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011332417 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.1011332417
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.1841578520
Short name T204
Test name
Test status
Simulation time 22924238294 ps
CPU time 10.05 seconds
Started Mar 07 12:29:03 PM PST 24
Finished Mar 07 12:29:13 PM PST 24
Peak memory 183928 kb
Host smart-e334b4d6-ddd5-4165-8767-414653fa1dbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841578520 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.1841578520
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.264734759
Short name T13
Test name
Test status
Simulation time 7542398718 ps
CPU time 13.28 seconds
Started Mar 07 12:29:01 PM PST 24
Finished Mar 07 12:29:15 PM PST 24
Peak memory 213960 kb
Host smart-719047a0-ccf0-4aab-a3ed-b17bcca798b1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264734759 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.264734759
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.1965968599
Short name T3
Test name
Test status
Simulation time 465053182 ps
CPU time 0.57 seconds
Started Mar 07 12:29:07 PM PST 24
Finished Mar 07 12:29:08 PM PST 24
Peak memory 183784 kb
Host smart-eeca913f-489a-404d-b89d-e22e8c3db00f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965968599 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.1965968599
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.451740082
Short name T185
Test name
Test status
Simulation time 60325306838 ps
CPU time 13.65 seconds
Started Mar 07 12:29:02 PM PST 24
Finished Mar 07 12:29:15 PM PST 24
Peak memory 195796 kb
Host smart-fc538c3e-747c-488d-9db0-cfa8e2ea174a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451740082 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_al
l.451740082
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/10.aon_timer_jump.1026535223
Short name T228
Test name
Test status
Simulation time 443037909 ps
CPU time 1.2 seconds
Started Mar 07 12:29:13 PM PST 24
Finished Mar 07 12:29:15 PM PST 24
Peak memory 183816 kb
Host smart-2f37021f-6a81-43ff-b20d-490f0222f89b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026535223 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.1026535223
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.791641936
Short name T157
Test name
Test status
Simulation time 20902751670 ps
CPU time 34.04 seconds
Started Mar 07 12:29:10 PM PST 24
Finished Mar 07 12:29:44 PM PST 24
Peak memory 183904 kb
Host smart-c1b660e0-6c99-4e98-85e4-1f6e20173cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791641936 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.791641936
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.1987217571
Short name T216
Test name
Test status
Simulation time 471045957 ps
CPU time 1.25 seconds
Started Mar 07 12:29:19 PM PST 24
Finished Mar 07 12:29:20 PM PST 24
Peak memory 183788 kb
Host smart-ed8bcd69-a5c9-433a-b7f7-c088fbe3d22c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987217571 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.1987217571
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.3164168769
Short name T100
Test name
Test status
Simulation time 173653607178 ps
CPU time 267.9 seconds
Started Mar 07 12:29:09 PM PST 24
Finished Mar 07 12:33:37 PM PST 24
Peak memory 183948 kb
Host smart-30cc8b11-adf2-480b-b4f4-67141d461d97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164168769 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_
all.3164168769
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_jump.242470137
Short name T152
Test name
Test status
Simulation time 603854689 ps
CPU time 1.54 seconds
Started Mar 07 12:29:04 PM PST 24
Finished Mar 07 12:29:06 PM PST 24
Peak memory 183784 kb
Host smart-049fb844-7719-4948-91e0-7958bac0a419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242470137 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.242470137
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.1122620316
Short name T205
Test name
Test status
Simulation time 16797227335 ps
CPU time 21.22 seconds
Started Mar 07 12:29:08 PM PST 24
Finished Mar 07 12:29:29 PM PST 24
Peak memory 184088 kb
Host smart-8d975cb5-cc53-416d-b69f-020b373edec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122620316 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.1122620316
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.2862184016
Short name T256
Test name
Test status
Simulation time 411494953 ps
CPU time 0.68 seconds
Started Mar 07 12:29:18 PM PST 24
Finished Mar 07 12:29:19 PM PST 24
Peak memory 183972 kb
Host smart-6ab95f33-b2c3-4d06-9b18-f1f69050c5bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862184016 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.2862184016
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.2777939209
Short name T222
Test name
Test status
Simulation time 109168646195 ps
CPU time 41.21 seconds
Started Mar 07 12:29:10 PM PST 24
Finished Mar 07 12:29:51 PM PST 24
Peak memory 183980 kb
Host smart-d172bc0f-820d-4a3b-a3e0-24b389227e45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777939209 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_
all.2777939209
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.754711642
Short name T246
Test name
Test status
Simulation time 15557988996 ps
CPU time 118.61 seconds
Started Mar 07 12:29:11 PM PST 24
Finished Mar 07 12:31:09 PM PST 24
Peak memory 198768 kb
Host smart-f1aa2334-6c18-4139-8876-ab4e06723759
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754711642 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand_reset.754711642
Directory /workspace/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.aon_timer_jump.1000123711
Short name T110
Test name
Test status
Simulation time 526197565 ps
CPU time 0.64 seconds
Started Mar 07 12:29:09 PM PST 24
Finished Mar 07 12:29:10 PM PST 24
Peak memory 183944 kb
Host smart-b362eedf-9148-410f-a0d8-97845efbbfa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000123711 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.1000123711
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.2857310362
Short name T244
Test name
Test status
Simulation time 39762306834 ps
CPU time 57.4 seconds
Started Mar 07 12:29:04 PM PST 24
Finished Mar 07 12:30:01 PM PST 24
Peak memory 183936 kb
Host smart-cc23567d-1960-4496-882c-08a0b5447ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857310362 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.2857310362
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.3293479560
Short name T199
Test name
Test status
Simulation time 555434811 ps
CPU time 0.76 seconds
Started Mar 07 12:29:09 PM PST 24
Finished Mar 07 12:29:10 PM PST 24
Peak memory 183764 kb
Host smart-29bcca6f-57bc-4a04-9add-80630843bd0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293479560 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.3293479560
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.857944428
Short name T229
Test name
Test status
Simulation time 166324527612 ps
CPU time 59.74 seconds
Started Mar 07 12:29:02 PM PST 24
Finished Mar 07 12:30:02 PM PST 24
Peak memory 194348 kb
Host smart-2c6e1e77-306a-4fab-9ec9-c4308743a546
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857944428 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_a
ll.857944428
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.693272416
Short name T98
Test name
Test status
Simulation time 184788746168 ps
CPU time 365.11 seconds
Started Mar 07 12:29:04 PM PST 24
Finished Mar 07 12:35:10 PM PST 24
Peak memory 198780 kb
Host smart-3d92f78f-a829-4f8a-8f51-03cac34755d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693272416 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.693272416
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_jump.1702671805
Short name T209
Test name
Test status
Simulation time 380930098 ps
CPU time 0.67 seconds
Started Mar 07 12:29:04 PM PST 24
Finished Mar 07 12:29:05 PM PST 24
Peak memory 183784 kb
Host smart-851e57ab-565a-407b-bb09-717ffad772a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702671805 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.1702671805
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.616729706
Short name T241
Test name
Test status
Simulation time 9737080599 ps
CPU time 13.3 seconds
Started Mar 07 12:29:09 PM PST 24
Finished Mar 07 12:29:22 PM PST 24
Peak memory 191452 kb
Host smart-7cea61a1-8c1b-4a3e-925a-9076674eba8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616729706 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.616729706
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.1002467489
Short name T115
Test name
Test status
Simulation time 470353834 ps
CPU time 1.26 seconds
Started Mar 07 12:29:02 PM PST 24
Finished Mar 07 12:29:04 PM PST 24
Peak memory 183924 kb
Host smart-18b0b2bf-f40a-4a73-8314-3b2e83692593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002467489 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.1002467489
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.3989418089
Short name T171
Test name
Test status
Simulation time 144474771407 ps
CPU time 121.86 seconds
Started Mar 07 12:29:07 PM PST 24
Finished Mar 07 12:31:09 PM PST 24
Peak memory 183892 kb
Host smart-3f65dfc3-32d2-4449-9c3b-4e024516252b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989418089 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_
all.3989418089
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.1591687247
Short name T186
Test name
Test status
Simulation time 227719060324 ps
CPU time 595.74 seconds
Started Mar 07 12:29:01 PM PST 24
Finished Mar 07 12:38:57 PM PST 24
Peak memory 198772 kb
Host smart-c00f2118-f040-4197-89f6-1bb74dfab6a6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591687247 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.1591687247
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.aon_timer_jump.1332431459
Short name T192
Test name
Test status
Simulation time 488360048 ps
CPU time 1.27 seconds
Started Mar 07 12:29:06 PM PST 24
Finished Mar 07 12:29:07 PM PST 24
Peak memory 183944 kb
Host smart-735297a0-7327-45a5-98c9-5436d3d4c911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332431459 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.1332431459
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.3934328879
Short name T197
Test name
Test status
Simulation time 6365671846 ps
CPU time 9.56 seconds
Started Mar 07 12:29:09 PM PST 24
Finished Mar 07 12:29:19 PM PST 24
Peak memory 183880 kb
Host smart-3a1fcbb2-00d6-429a-8280-6eba80e5b4f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934328879 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.3934328879
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.854735938
Short name T170
Test name
Test status
Simulation time 350947594 ps
CPU time 1.04 seconds
Started Mar 07 12:29:09 PM PST 24
Finished Mar 07 12:29:10 PM PST 24
Peak memory 183832 kb
Host smart-70683667-a06b-4dd8-98ca-d6be7bf4f6db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854735938 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.854735938
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.2616724198
Short name T166
Test name
Test status
Simulation time 276328664498 ps
CPU time 398.42 seconds
Started Mar 07 12:29:29 PM PST 24
Finished Mar 07 12:36:07 PM PST 24
Peak memory 194348 kb
Host smart-6672b6c1-2360-4649-81f5-881fad8882e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616724198 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_
all.2616724198
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.3667348634
Short name T96
Test name
Test status
Simulation time 304630937770 ps
CPU time 235.51 seconds
Started Mar 07 12:29:06 PM PST 24
Finished Mar 07 12:33:02 PM PST 24
Peak memory 214328 kb
Host smart-ec65cfa5-0e9d-4da5-9370-e926bb274ceb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667348634 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.3667348634
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.aon_timer_jump.2620098236
Short name T266
Test name
Test status
Simulation time 586152349 ps
CPU time 0.64 seconds
Started Mar 07 12:29:10 PM PST 24
Finished Mar 07 12:29:11 PM PST 24
Peak memory 183716 kb
Host smart-1b4a45c5-162c-4469-822b-033a6fb9a850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620098236 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.2620098236
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.562545440
Short name T227
Test name
Test status
Simulation time 19609244573 ps
CPU time 17.03 seconds
Started Mar 07 12:29:14 PM PST 24
Finished Mar 07 12:29:31 PM PST 24
Peak memory 183980 kb
Host smart-67ac15a1-2fa3-49aa-a149-5271930b4961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562545440 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.562545440
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.857716375
Short name T117
Test name
Test status
Simulation time 430644044 ps
CPU time 0.59 seconds
Started Mar 07 12:29:09 PM PST 24
Finished Mar 07 12:29:10 PM PST 24
Peak memory 183080 kb
Host smart-26d1fbd7-4d29-4edb-9070-7659bb62d784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857716375 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.857716375
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.1618151541
Short name T47
Test name
Test status
Simulation time 58395140533 ps
CPU time 26.49 seconds
Started Mar 07 12:29:20 PM PST 24
Finished Mar 07 12:29:47 PM PST 24
Peak memory 195756 kb
Host smart-9a02b531-e9bf-4304-94ed-1b965369e391
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618151541 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_
all.1618151541
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.2328986861
Short name T212
Test name
Test status
Simulation time 12618789697 ps
CPU time 129.85 seconds
Started Mar 07 12:29:10 PM PST 24
Finished Mar 07 12:31:20 PM PST 24
Peak memory 198640 kb
Host smart-1f18abe0-268e-4668-8741-314ac11ff7f5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328986861 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.2328986861
Directory /workspace/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.aon_timer_jump.804866901
Short name T260
Test name
Test status
Simulation time 398132788 ps
CPU time 0.9 seconds
Started Mar 07 12:29:10 PM PST 24
Finished Mar 07 12:29:11 PM PST 24
Peak memory 183816 kb
Host smart-f68ecad6-f98b-47b5-aed2-f22703ad9918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804866901 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.804866901
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.4050289715
Short name T232
Test name
Test status
Simulation time 19855560248 ps
CPU time 30.33 seconds
Started Mar 07 12:29:09 PM PST 24
Finished Mar 07 12:29:40 PM PST 24
Peak memory 183768 kb
Host smart-62769ea1-25e9-4198-a418-40b717702edd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050289715 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.4050289715
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.591173159
Short name T109
Test name
Test status
Simulation time 497255207 ps
CPU time 0.91 seconds
Started Mar 07 12:29:22 PM PST 24
Finished Mar 07 12:29:23 PM PST 24
Peak memory 183948 kb
Host smart-668d87e3-4853-46f0-9d88-dd99d5b9f1af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591173159 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.591173159
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.532539595
Short name T135
Test name
Test status
Simulation time 88182524579 ps
CPU time 145.6 seconds
Started Mar 07 12:29:17 PM PST 24
Finished Mar 07 12:31:43 PM PST 24
Peak memory 194252 kb
Host smart-c703ce61-d488-439b-9921-29f448f65d52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532539595 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_a
ll.532539595
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.3854459022
Short name T217
Test name
Test status
Simulation time 32384814570 ps
CPU time 274.99 seconds
Started Mar 07 12:29:15 PM PST 24
Finished Mar 07 12:33:50 PM PST 24
Peak memory 198968 kb
Host smart-88159ed1-548f-410f-8fe7-7dc79da15b53
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854459022 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.3854459022
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.aon_timer_jump.506840906
Short name T148
Test name
Test status
Simulation time 533158433 ps
CPU time 1.41 seconds
Started Mar 07 12:29:17 PM PST 24
Finished Mar 07 12:29:19 PM PST 24
Peak memory 183948 kb
Host smart-2b2c889a-44ee-45d6-96f3-36698c3a2fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506840906 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.506840906
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.1173039685
Short name T4
Test name
Test status
Simulation time 59946755176 ps
CPU time 62.05 seconds
Started Mar 07 12:29:10 PM PST 24
Finished Mar 07 12:30:12 PM PST 24
Peak memory 183900 kb
Host smart-f538b639-5063-420b-ad5b-edc6fc1660af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173039685 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.1173039685
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.763672708
Short name T158
Test name
Test status
Simulation time 494531173 ps
CPU time 1.19 seconds
Started Mar 07 12:29:10 PM PST 24
Finished Mar 07 12:29:11 PM PST 24
Peak memory 183788 kb
Host smart-c1ca5c82-7338-4a83-b816-4e9231271952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763672708 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.763672708
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.1336637996
Short name T201
Test name
Test status
Simulation time 35711284035 ps
CPU time 30.37 seconds
Started Mar 07 12:29:23 PM PST 24
Finished Mar 07 12:29:53 PM PST 24
Peak memory 183896 kb
Host smart-38dfd70b-35ef-4f93-aea9-80079b4a2e2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336637996 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_
all.1336637996
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_jump.3607337520
Short name T156
Test name
Test status
Simulation time 456594507 ps
CPU time 1.23 seconds
Started Mar 07 12:29:10 PM PST 24
Finished Mar 07 12:29:11 PM PST 24
Peak memory 183824 kb
Host smart-97d8f99f-c643-42f3-aab2-44cd281653cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607337520 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.3607337520
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.2288892562
Short name T153
Test name
Test status
Simulation time 13721226968 ps
CPU time 3.67 seconds
Started Mar 07 12:29:03 PM PST 24
Finished Mar 07 12:29:07 PM PST 24
Peak memory 183976 kb
Host smart-2cb399e8-9e8e-47d3-8103-0e6788e70ac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288892562 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.2288892562
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.923748443
Short name T138
Test name
Test status
Simulation time 380543097 ps
CPU time 0.79 seconds
Started Mar 07 12:29:08 PM PST 24
Finished Mar 07 12:29:09 PM PST 24
Peak memory 183732 kb
Host smart-daa9b7d4-9749-466c-b995-868b214f7325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923748443 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.923748443
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.716854409
Short name T172
Test name
Test status
Simulation time 44833450334 ps
CPU time 66.55 seconds
Started Mar 07 12:29:10 PM PST 24
Finished Mar 07 12:30:17 PM PST 24
Peak memory 183952 kb
Host smart-56ce038c-f51b-4894-929e-972e0b363a45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716854409 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_a
ll.716854409
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.4272049466
Short name T220
Test name
Test status
Simulation time 22878755121 ps
CPU time 233.52 seconds
Started Mar 07 12:29:13 PM PST 24
Finished Mar 07 12:33:07 PM PST 24
Peak memory 198820 kb
Host smart-3ec816a3-19e2-40a2-bf97-8e7438d49233
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272049466 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.4272049466
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.aon_timer_jump.1428647176
Short name T28
Test name
Test status
Simulation time 585275167 ps
CPU time 1.48 seconds
Started Mar 07 12:29:20 PM PST 24
Finished Mar 07 12:29:22 PM PST 24
Peak memory 183948 kb
Host smart-d9d67ee0-199f-40e8-b329-2ce82c48c8da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428647176 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.1428647176
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.2353729620
Short name T198
Test name
Test status
Simulation time 51238347007 ps
CPU time 61.52 seconds
Started Mar 07 12:29:06 PM PST 24
Finished Mar 07 12:30:07 PM PST 24
Peak memory 184092 kb
Host smart-037444e4-ccef-4010-9a70-89ba3dd970c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353729620 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.2353729620
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.1280208412
Short name T215
Test name
Test status
Simulation time 385453993 ps
CPU time 1.14 seconds
Started Mar 07 12:29:06 PM PST 24
Finished Mar 07 12:29:08 PM PST 24
Peak memory 183944 kb
Host smart-7781220f-f194-42db-ac5c-d9e744fb8eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280208412 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.1280208412
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.1434436492
Short name T177
Test name
Test status
Simulation time 105770097113 ps
CPU time 18.55 seconds
Started Mar 07 12:29:09 PM PST 24
Finished Mar 07 12:29:28 PM PST 24
Peak memory 183936 kb
Host smart-598ba1fb-5da4-4654-806f-330fe41b203e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434436492 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_
all.1434436492
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.3666143579
Short name T165
Test name
Test status
Simulation time 40293877265 ps
CPU time 193.89 seconds
Started Mar 07 12:29:07 PM PST 24
Finished Mar 07 12:32:21 PM PST 24
Peak memory 198408 kb
Host smart-dc37e347-c32d-4c6a-bc15-2da08307e239
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666143579 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.3666143579
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_jump.588229913
Short name T243
Test name
Test status
Simulation time 542419177 ps
CPU time 0.78 seconds
Started Mar 07 12:29:04 PM PST 24
Finished Mar 07 12:29:05 PM PST 24
Peak memory 183784 kb
Host smart-aa2bf576-5dd7-449d-90c2-d59ace45d23f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588229913 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.588229913
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.355111368
Short name T54
Test name
Test status
Simulation time 11474537133 ps
CPU time 13.23 seconds
Started Mar 07 12:28:55 PM PST 24
Finished Mar 07 12:29:09 PM PST 24
Peak memory 183892 kb
Host smart-e158b6a2-090b-4103-a26a-44ca644b9ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355111368 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.355111368
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.3449728552
Short name T14
Test name
Test status
Simulation time 8385085630 ps
CPU time 2.86 seconds
Started Mar 07 12:29:08 PM PST 24
Finished Mar 07 12:29:11 PM PST 24
Peak memory 215588 kb
Host smart-d0a2e7f6-bb5a-42c0-ad1f-5402a97c11b8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449728552 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.3449728552
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.1600067447
Short name T203
Test name
Test status
Simulation time 421782813 ps
CPU time 0.66 seconds
Started Mar 07 12:29:04 PM PST 24
Finished Mar 07 12:29:05 PM PST 24
Peak memory 183784 kb
Host smart-af25a5a0-970d-4cc5-a119-864fd16b7901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600067447 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.1600067447
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.269235752
Short name T183
Test name
Test status
Simulation time 154612233773 ps
CPU time 227.89 seconds
Started Mar 07 12:28:54 PM PST 24
Finished Mar 07 12:32:42 PM PST 24
Peak memory 184024 kb
Host smart-0f23bd89-59bb-4673-a0f0-5760f2812bbb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269235752 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_al
l.269235752
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.1231626356
Short name T48
Test name
Test status
Simulation time 344669341472 ps
CPU time 192.16 seconds
Started Mar 07 12:28:57 PM PST 24
Finished Mar 07 12:32:09 PM PST 24
Peak memory 198716 kb
Host smart-d7cc70f7-9da7-491c-8793-6a73c75b6312
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231626356 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.1231626356
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.aon_timer_jump.4241171668
Short name T259
Test name
Test status
Simulation time 443604403 ps
CPU time 1.12 seconds
Started Mar 07 12:29:14 PM PST 24
Finished Mar 07 12:29:15 PM PST 24
Peak memory 183860 kb
Host smart-ea50d0e2-5092-418b-8e20-4188b6e15c2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241171668 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.4241171668
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.176243491
Short name T44
Test name
Test status
Simulation time 48440230657 ps
CPU time 17.33 seconds
Started Mar 07 12:29:20 PM PST 24
Finished Mar 07 12:29:37 PM PST 24
Peak memory 184060 kb
Host smart-ccb979e5-35fb-4733-beed-ddde0d9dc0a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176243491 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.176243491
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.2501497645
Short name T254
Test name
Test status
Simulation time 498030641 ps
CPU time 0.91 seconds
Started Mar 07 12:29:13 PM PST 24
Finished Mar 07 12:29:13 PM PST 24
Peak memory 183944 kb
Host smart-c70fcc14-fd18-4956-b824-fb2943d71629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501497645 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.2501497645
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.723856795
Short name T236
Test name
Test status
Simulation time 129372840926 ps
CPU time 99.64 seconds
Started Mar 07 12:29:10 PM PST 24
Finished Mar 07 12:30:50 PM PST 24
Peak memory 183952 kb
Host smart-b7989dba-a8a1-4d49-a8d6-ab1b0af5ac53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723856795 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_a
ll.723856795
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/21.aon_timer_jump.4185134469
Short name T277
Test name
Test status
Simulation time 482064635 ps
CPU time 0.92 seconds
Started Mar 07 12:29:13 PM PST 24
Finished Mar 07 12:29:14 PM PST 24
Peak memory 183804 kb
Host smart-5e63afa5-5894-4ce7-b9c9-1fbb6ac20fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185134469 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.4185134469
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.3805231170
Short name T235
Test name
Test status
Simulation time 12739853762 ps
CPU time 19.15 seconds
Started Mar 07 12:29:10 PM PST 24
Finished Mar 07 12:29:29 PM PST 24
Peak memory 183972 kb
Host smart-067de7f0-c4e4-4fee-b650-39827c40fcfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805231170 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.3805231170
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.1267997930
Short name T140
Test name
Test status
Simulation time 457265252 ps
CPU time 0.91 seconds
Started Mar 07 12:29:07 PM PST 24
Finished Mar 07 12:29:08 PM PST 24
Peak memory 183812 kb
Host smart-92b5410e-0b45-4967-a64b-b58b390152af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267997930 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.1267997930
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.1613034234
Short name T163
Test name
Test status
Simulation time 224232792448 ps
CPU time 350.51 seconds
Started Mar 07 12:29:09 PM PST 24
Finished Mar 07 12:35:00 PM PST 24
Peak memory 195272 kb
Host smart-dc3dee69-1517-4373-9138-318db36a5500
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613034234 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_
all.1613034234
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.2236902870
Short name T58
Test name
Test status
Simulation time 155198021084 ps
CPU time 1390.22 seconds
Started Mar 07 12:29:10 PM PST 24
Finished Mar 07 12:52:20 PM PST 24
Peak memory 208808 kb
Host smart-276c6fad-11df-466e-b395-66045b2e7b71
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236902870 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.2236902870
Directory /workspace/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.aon_timer_jump.2928674323
Short name T79
Test name
Test status
Simulation time 407377311 ps
CPU time 0.9 seconds
Started Mar 07 12:29:12 PM PST 24
Finished Mar 07 12:29:13 PM PST 24
Peak memory 183744 kb
Host smart-3c13cbce-c9f5-4fc5-8c76-9840c0baf3b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928674323 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.2928674323
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.91645903
Short name T281
Test name
Test status
Simulation time 41510483587 ps
CPU time 44.34 seconds
Started Mar 07 12:29:13 PM PST 24
Finished Mar 07 12:29:57 PM PST 24
Peak memory 184176 kb
Host smart-cb6c2287-01e6-4484-bfca-68c8539a51e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91645903 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.91645903
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.111691140
Short name T248
Test name
Test status
Simulation time 522302835 ps
CPU time 0.72 seconds
Started Mar 07 12:29:07 PM PST 24
Finished Mar 07 12:29:08 PM PST 24
Peak memory 183784 kb
Host smart-77298d58-97fa-4691-9b62-9884b5d0944e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111691140 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.111691140
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.3633773794
Short name T116
Test name
Test status
Simulation time 121999554580 ps
CPU time 187.99 seconds
Started Mar 07 12:29:26 PM PST 24
Finished Mar 07 12:32:35 PM PST 24
Peak memory 183952 kb
Host smart-8d1390e4-556a-40d9-92a0-a1c111a25dcf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633773794 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_
all.3633773794
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.4008461350
Short name T269
Test name
Test status
Simulation time 22186864726 ps
CPU time 253.52 seconds
Started Mar 07 12:29:06 PM PST 24
Finished Mar 07 12:33:24 PM PST 24
Peak memory 198776 kb
Host smart-37738a22-6e23-41a3-9007-538e1975575e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008461350 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.4008461350
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.aon_timer_jump.202463054
Short name T261
Test name
Test status
Simulation time 571658834 ps
CPU time 0.98 seconds
Started Mar 07 12:29:18 PM PST 24
Finished Mar 07 12:29:19 PM PST 24
Peak memory 183924 kb
Host smart-516c83fd-d431-4852-8475-3099e4991d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202463054 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.202463054
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.479644681
Short name T268
Test name
Test status
Simulation time 54137119720 ps
CPU time 12.92 seconds
Started Mar 07 12:29:08 PM PST 24
Finished Mar 07 12:29:21 PM PST 24
Peak memory 192260 kb
Host smart-41a44112-1f5c-4c0a-839d-939c09ae4cf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479644681 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.479644681
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.1614237961
Short name T146
Test name
Test status
Simulation time 482188686 ps
CPU time 0.78 seconds
Started Mar 07 12:29:11 PM PST 24
Finished Mar 07 12:29:12 PM PST 24
Peak memory 183876 kb
Host smart-93e25e62-0a76-40ee-bb2c-cbbbfc924740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614237961 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.1614237961
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.2151077021
Short name T208
Test name
Test status
Simulation time 298104673236 ps
CPU time 120.73 seconds
Started Mar 07 12:29:29 PM PST 24
Finished Mar 07 12:31:30 PM PST 24
Peak memory 183944 kb
Host smart-b7ea5bad-81f2-4e82-87d1-bf170a909fd4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151077021 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_
all.2151077021
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.3311701878
Short name T280
Test name
Test status
Simulation time 58512417125 ps
CPU time 631.42 seconds
Started Mar 07 12:29:11 PM PST 24
Finished Mar 07 12:39:43 PM PST 24
Peak memory 207120 kb
Host smart-bf71a582-3b90-4213-9397-1c1f45f53ecd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311701878 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.3311701878
Directory /workspace/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.aon_timer_jump.794603840
Short name T51
Test name
Test status
Simulation time 664746606 ps
CPU time 0.65 seconds
Started Mar 07 12:29:14 PM PST 24
Finished Mar 07 12:29:14 PM PST 24
Peak memory 183856 kb
Host smart-13a7423c-3fb5-4840-9fc1-8ea3fdf7c711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794603840 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.794603840
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.3345344438
Short name T279
Test name
Test status
Simulation time 4314360138 ps
CPU time 4.58 seconds
Started Mar 07 12:29:24 PM PST 24
Finished Mar 07 12:29:29 PM PST 24
Peak memory 184060 kb
Host smart-f2b8d676-d869-4229-b0cb-32886b505596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345344438 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.3345344438
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.351617272
Short name T120
Test name
Test status
Simulation time 601894523 ps
CPU time 1.49 seconds
Started Mar 07 12:29:11 PM PST 24
Finished Mar 07 12:29:13 PM PST 24
Peak memory 183812 kb
Host smart-7b7291f5-75d4-4a35-9aff-277c99c53b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351617272 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.351617272
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.3424347682
Short name T129
Test name
Test status
Simulation time 211113869658 ps
CPU time 166.13 seconds
Started Mar 07 12:29:09 PM PST 24
Finished Mar 07 12:31:55 PM PST 24
Peak memory 183992 kb
Host smart-9cdfe3ce-dc73-4bd3-82d0-651075a8c49d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424347682 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_
all.3424347682
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.4022178436
Short name T95
Test name
Test status
Simulation time 103611210788 ps
CPU time 387.43 seconds
Started Mar 07 12:29:28 PM PST 24
Finished Mar 07 12:35:56 PM PST 24
Peak memory 198756 kb
Host smart-b28d145f-0aa0-4f7e-84d8-93dd4c347111
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022178436 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand_reset.4022178436
Directory /workspace/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.aon_timer_jump.2883133113
Short name T206
Test name
Test status
Simulation time 343425897 ps
CPU time 1.02 seconds
Started Mar 07 12:29:06 PM PST 24
Finished Mar 07 12:29:08 PM PST 24
Peak memory 183820 kb
Host smart-827958a8-67d8-4a1a-8b9b-b7c8d626a170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883133113 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.2883133113
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.4130226255
Short name T55
Test name
Test status
Simulation time 23303874976 ps
CPU time 38.46 seconds
Started Mar 07 12:29:08 PM PST 24
Finished Mar 07 12:29:47 PM PST 24
Peak memory 184064 kb
Host smart-f37426f5-5ece-4bd3-b1f3-ad5c142ff8d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130226255 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.4130226255
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.426354909
Short name T272
Test name
Test status
Simulation time 399722376 ps
CPU time 1.19 seconds
Started Mar 07 12:29:10 PM PST 24
Finished Mar 07 12:29:11 PM PST 24
Peak memory 183604 kb
Host smart-a92c5dd2-66fc-4f08-a478-d22adc27cfc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426354909 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.426354909
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.2730638434
Short name T102
Test name
Test status
Simulation time 388329247014 ps
CPU time 149.01 seconds
Started Mar 07 12:29:15 PM PST 24
Finished Mar 07 12:31:45 PM PST 24
Peak memory 194084 kb
Host smart-e033f5c5-34ad-47e3-a674-2639123d34cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730638434 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_
all.2730638434
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.4198435345
Short name T22
Test name
Test status
Simulation time 145693423527 ps
CPU time 309.35 seconds
Started Mar 07 12:29:06 PM PST 24
Finished Mar 07 12:34:17 PM PST 24
Peak memory 198852 kb
Host smart-56822162-df3c-4251-8f9c-bb1e4035d1b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198435345 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.4198435345
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.aon_timer_jump.4142572698
Short name T160
Test name
Test status
Simulation time 360785933 ps
CPU time 1.09 seconds
Started Mar 07 12:29:08 PM PST 24
Finished Mar 07 12:29:10 PM PST 24
Peak memory 183816 kb
Host smart-ec49be9c-9687-4176-8c9e-998e45243440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142572698 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.4142572698
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.1620058716
Short name T207
Test name
Test status
Simulation time 61680293506 ps
CPU time 49.5 seconds
Started Mar 07 12:29:08 PM PST 24
Finished Mar 07 12:29:57 PM PST 24
Peak memory 184084 kb
Host smart-ed150d4b-b821-4070-a99a-83af9e09a35b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620058716 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.1620058716
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.4118981013
Short name T255
Test name
Test status
Simulation time 395550960 ps
CPU time 1.18 seconds
Started Mar 07 12:29:13 PM PST 24
Finished Mar 07 12:29:15 PM PST 24
Peak memory 183860 kb
Host smart-020df66a-356e-434d-9adf-9557cfa6569f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118981013 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.4118981013
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.2956015505
Short name T250
Test name
Test status
Simulation time 97950117952 ps
CPU time 60.63 seconds
Started Mar 07 12:29:04 PM PST 24
Finished Mar 07 12:30:05 PM PST 24
Peak memory 194016 kb
Host smart-3db9984b-9bfa-4b51-a9b8-8365d90eecdd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956015505 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_
all.2956015505
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.497286320
Short name T91
Test name
Test status
Simulation time 119909638780 ps
CPU time 418.73 seconds
Started Mar 07 12:29:30 PM PST 24
Finished Mar 07 12:36:29 PM PST 24
Peak memory 198864 kb
Host smart-03ddfb44-dc59-43ba-8e98-10707e9e549f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497286320 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.497286320
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_jump.3192150023
Short name T150
Test name
Test status
Simulation time 353333460 ps
CPU time 1.02 seconds
Started Mar 07 12:29:17 PM PST 24
Finished Mar 07 12:29:18 PM PST 24
Peak memory 183820 kb
Host smart-eff4b3f8-ce6a-4400-b270-f1f76ed0160d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192150023 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.3192150023
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.1541536401
Short name T108
Test name
Test status
Simulation time 32813601110 ps
CPU time 26.1 seconds
Started Mar 07 12:29:09 PM PST 24
Finished Mar 07 12:29:35 PM PST 24
Peak memory 184064 kb
Host smart-aaab28d4-f2f2-4b27-87ad-b2acf6b6f265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541536401 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.1541536401
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.4150997541
Short name T50
Test name
Test status
Simulation time 383191949 ps
CPU time 0.72 seconds
Started Mar 07 12:29:10 PM PST 24
Finished Mar 07 12:29:11 PM PST 24
Peak memory 183828 kb
Host smart-38cbdf18-7793-4050-a23d-604942ac96c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150997541 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.4150997541
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.1013429790
Short name T173
Test name
Test status
Simulation time 89423441856 ps
CPU time 33.98 seconds
Started Mar 07 12:29:23 PM PST 24
Finished Mar 07 12:29:58 PM PST 24
Peak memory 183896 kb
Host smart-b3c476c9-8a87-4e04-b868-13503d13343c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013429790 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_
all.1013429790
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.3909373917
Short name T39
Test name
Test status
Simulation time 117199737862 ps
CPU time 453.77 seconds
Started Mar 07 12:29:06 PM PST 24
Finished Mar 07 12:36:41 PM PST 24
Peak memory 198900 kb
Host smart-0f68d3d7-de54-41b7-a202-622f1f1f3729
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909373917 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.3909373917
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_jump.1054237909
Short name T123
Test name
Test status
Simulation time 480972478 ps
CPU time 0.69 seconds
Started Mar 07 12:29:19 PM PST 24
Finished Mar 07 12:29:20 PM PST 24
Peak memory 183800 kb
Host smart-0e874e04-c530-44fb-bef6-ed623070b5a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054237909 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.1054237909
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.3441452120
Short name T211
Test name
Test status
Simulation time 5840240806 ps
CPU time 9.21 seconds
Started Mar 07 12:29:06 PM PST 24
Finished Mar 07 12:29:16 PM PST 24
Peak memory 183916 kb
Host smart-ee7f8569-5522-4e18-980c-0999a7b65f54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441452120 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.3441452120
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.1223789468
Short name T251
Test name
Test status
Simulation time 506006588 ps
CPU time 1.3 seconds
Started Mar 07 12:29:11 PM PST 24
Finished Mar 07 12:29:12 PM PST 24
Peak memory 183764 kb
Host smart-119cb606-d27d-4296-bb9c-609dfeafc2b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223789468 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.1223789468
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.3182069927
Short name T25
Test name
Test status
Simulation time 139947758520 ps
CPU time 50.31 seconds
Started Mar 07 12:29:14 PM PST 24
Finished Mar 07 12:30:04 PM PST 24
Peak memory 194520 kb
Host smart-21dd361a-9cc2-4f4e-9c31-03713c58d715
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182069927 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_
all.3182069927
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.362065856
Short name T73
Test name
Test status
Simulation time 28178273662 ps
CPU time 229.87 seconds
Started Mar 07 12:29:21 PM PST 24
Finished Mar 07 12:33:11 PM PST 24
Peak memory 198772 kb
Host smart-64157dfe-55db-4a9c-9a10-986b6e9c08f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362065856 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.362065856
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.aon_timer_jump.3358625025
Short name T180
Test name
Test status
Simulation time 420591351 ps
CPU time 0.78 seconds
Started Mar 07 12:29:25 PM PST 24
Finished Mar 07 12:29:26 PM PST 24
Peak memory 183924 kb
Host smart-3441c7a8-8a4c-4af9-be4d-a65188710b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358625025 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.3358625025
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.1587193583
Short name T159
Test name
Test status
Simulation time 19860042528 ps
CPU time 8.56 seconds
Started Mar 07 12:29:21 PM PST 24
Finished Mar 07 12:29:30 PM PST 24
Peak memory 192096 kb
Host smart-7a09958a-53dd-4129-86f2-31576513eb96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587193583 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.1587193583
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.3094373305
Short name T127
Test name
Test status
Simulation time 529587685 ps
CPU time 1.31 seconds
Started Mar 07 12:29:10 PM PST 24
Finished Mar 07 12:29:11 PM PST 24
Peak memory 183684 kb
Host smart-8bed58ab-5cd7-4b3a-8662-206880f32fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094373305 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.3094373305
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.577559326
Short name T114
Test name
Test status
Simulation time 495630824726 ps
CPU time 254.34 seconds
Started Mar 07 12:29:08 PM PST 24
Finished Mar 07 12:33:23 PM PST 24
Peak memory 183924 kb
Host smart-da8adce7-3f17-4be2-9a75-2507350775cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577559326 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_a
ll.577559326
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.2155593286
Short name T38
Test name
Test status
Simulation time 11723094240 ps
CPU time 88.5 seconds
Started Mar 07 12:29:12 PM PST 24
Finished Mar 07 12:30:41 PM PST 24
Peak memory 198992 kb
Host smart-3309c487-48e5-4356-b2b5-64eed014e2e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155593286 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.2155593286
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.aon_timer_jump.2699200837
Short name T76
Test name
Test status
Simulation time 349285213 ps
CPU time 1.05 seconds
Started Mar 07 12:28:56 PM PST 24
Finished Mar 07 12:28:57 PM PST 24
Peak memory 183764 kb
Host smart-c1d365cc-ca11-4c9f-a596-02270a4beb97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699200837 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.2699200837
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.2162702013
Short name T18
Test name
Test status
Simulation time 16357049000 ps
CPU time 11.88 seconds
Started Mar 07 12:29:00 PM PST 24
Finished Mar 07 12:29:12 PM PST 24
Peak memory 183956 kb
Host smart-87a5e0a1-5b7f-4b41-b388-244a84e00c70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162702013 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.2162702013
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.4125770323
Short name T16
Test name
Test status
Simulation time 8209411426 ps
CPU time 12.96 seconds
Started Mar 07 12:29:13 PM PST 24
Finished Mar 07 12:29:26 PM PST 24
Peak memory 215676 kb
Host smart-8aea3668-5463-43a6-84e2-4529fab4d8df
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125770323 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.4125770323
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.1993193193
Short name T253
Test name
Test status
Simulation time 520684306 ps
CPU time 0.67 seconds
Started Mar 07 12:29:00 PM PST 24
Finished Mar 07 12:29:01 PM PST 24
Peak memory 183872 kb
Host smart-8d38524c-3712-4749-ae6a-8c23269eaa80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993193193 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.1993193193
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.2438543801
Short name T137
Test name
Test status
Simulation time 288175074125 ps
CPU time 67.07 seconds
Started Mar 07 12:29:10 PM PST 24
Finished Mar 07 12:30:17 PM PST 24
Peak memory 183904 kb
Host smart-b8b2e972-affe-4b1a-86b8-b0627848565a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438543801 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_a
ll.2438543801
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.3588820339
Short name T90
Test name
Test status
Simulation time 173377694377 ps
CPU time 284.46 seconds
Started Mar 07 12:28:59 PM PST 24
Finished Mar 07 12:33:44 PM PST 24
Peak memory 198928 kb
Host smart-0cc28b17-a624-45ea-b653-a2623e78efe9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588820339 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.3588820339
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_jump.2184753503
Short name T225
Test name
Test status
Simulation time 504446563 ps
CPU time 0.65 seconds
Started Mar 07 12:29:23 PM PST 24
Finished Mar 07 12:29:24 PM PST 24
Peak memory 183784 kb
Host smart-4d0be757-65b8-4522-887a-833de2e32ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184753503 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.2184753503
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.768739295
Short name T23
Test name
Test status
Simulation time 8687625995 ps
CPU time 12.53 seconds
Started Mar 07 12:29:10 PM PST 24
Finished Mar 07 12:29:23 PM PST 24
Peak memory 183948 kb
Host smart-86f1e981-c386-45b7-859b-e429d0668c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768739295 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.768739295
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.3385768153
Short name T252
Test name
Test status
Simulation time 533058675 ps
CPU time 0.75 seconds
Started Mar 07 12:29:24 PM PST 24
Finished Mar 07 12:29:24 PM PST 24
Peak memory 183972 kb
Host smart-12884fb0-c8a2-44e2-92cd-42cb2ba4343b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385768153 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.3385768153
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.2824572292
Short name T45
Test name
Test status
Simulation time 243377425417 ps
CPU time 45.74 seconds
Started Mar 07 12:29:35 PM PST 24
Finished Mar 07 12:30:21 PM PST 24
Peak memory 195288 kb
Host smart-ed0276de-0b13-4dbb-9363-cfb46abc8a2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824572292 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_
all.2824572292
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.4139031054
Short name T273
Test name
Test status
Simulation time 19334632659 ps
CPU time 146.4 seconds
Started Mar 07 12:29:11 PM PST 24
Finished Mar 07 12:31:38 PM PST 24
Peak memory 198468 kb
Host smart-f410219b-3df9-4d99-bfd9-c4ee23b7418a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139031054 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.4139031054
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.aon_timer_jump.1318437088
Short name T230
Test name
Test status
Simulation time 508421538 ps
CPU time 0.93 seconds
Started Mar 07 12:29:09 PM PST 24
Finished Mar 07 12:29:10 PM PST 24
Peak memory 183848 kb
Host smart-256000a8-eb37-49ab-a7c7-d5d8ef3c6f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318437088 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.1318437088
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.2966107217
Short name T218
Test name
Test status
Simulation time 33161796256 ps
CPU time 52.74 seconds
Started Mar 07 12:29:21 PM PST 24
Finished Mar 07 12:30:14 PM PST 24
Peak memory 184088 kb
Host smart-fe402823-a8bd-4c4f-b676-793997a62f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966107217 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.2966107217
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.3638284182
Short name T130
Test name
Test status
Simulation time 389216505 ps
CPU time 1.2 seconds
Started Mar 07 12:29:15 PM PST 24
Finished Mar 07 12:29:16 PM PST 24
Peak memory 183764 kb
Host smart-b380b22f-7087-4526-ae00-31e1fc84399e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638284182 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.3638284182
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.3368286634
Short name T200
Test name
Test status
Simulation time 387342656155 ps
CPU time 130.29 seconds
Started Mar 07 12:29:30 PM PST 24
Finished Mar 07 12:31:40 PM PST 24
Peak memory 195460 kb
Host smart-67c2df66-a24b-4eb3-b4ce-d6d7a989e92d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368286634 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_
all.3368286634
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.3058339871
Short name T195
Test name
Test status
Simulation time 58381335643 ps
CPU time 485.12 seconds
Started Mar 07 12:29:25 PM PST 24
Finished Mar 07 12:37:30 PM PST 24
Peak memory 198868 kb
Host smart-dda67e59-f6bc-4928-975a-b975d2625e63
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058339871 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.3058339871
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.aon_timer_jump.1659622297
Short name T184
Test name
Test status
Simulation time 438220582 ps
CPU time 0.92 seconds
Started Mar 07 12:29:09 PM PST 24
Finished Mar 07 12:29:10 PM PST 24
Peak memory 183632 kb
Host smart-b9fa7520-aad4-44a4-b6c4-4354f67ad39a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659622297 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.1659622297
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.1592735748
Short name T43
Test name
Test status
Simulation time 40101075785 ps
CPU time 59.9 seconds
Started Mar 07 12:29:13 PM PST 24
Finished Mar 07 12:30:13 PM PST 24
Peak memory 184184 kb
Host smart-36d7ec56-1f5d-4800-baa2-71ff46a2d38d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592735748 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.1592735748
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.705642367
Short name T270
Test name
Test status
Simulation time 521267458 ps
CPU time 1.37 seconds
Started Mar 07 12:29:12 PM PST 24
Finished Mar 07 12:29:13 PM PST 24
Peak memory 183516 kb
Host smart-9df3e8ce-8cb3-4361-a733-9b190c3a52a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705642367 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.705642367
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.316889413
Short name T265
Test name
Test status
Simulation time 54100750831 ps
CPU time 381.04 seconds
Started Mar 07 12:29:11 PM PST 24
Finished Mar 07 12:35:32 PM PST 24
Peak memory 198776 kb
Host smart-3a351a62-efeb-42a0-b5c5-37aa9261fc45
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316889413 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_reset.316889413
Directory /workspace/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.aon_timer_jump.1737955319
Short name T162
Test name
Test status
Simulation time 411781239 ps
CPU time 1.09 seconds
Started Mar 07 12:29:19 PM PST 24
Finished Mar 07 12:29:20 PM PST 24
Peak memory 183800 kb
Host smart-68ec91f0-72d1-406b-b2cf-134977c300c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737955319 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.1737955319
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.1908329374
Short name T78
Test name
Test status
Simulation time 27224773457 ps
CPU time 7.1 seconds
Started Mar 07 12:29:30 PM PST 24
Finished Mar 07 12:29:37 PM PST 24
Peak memory 183972 kb
Host smart-66968da2-f10d-4e05-8b61-106d48dbcf2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908329374 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.1908329374
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.3949874966
Short name T121
Test name
Test status
Simulation time 439945532 ps
CPU time 0.89 seconds
Started Mar 07 12:29:30 PM PST 24
Finished Mar 07 12:29:31 PM PST 24
Peak memory 183848 kb
Host smart-21b85680-e484-4dc0-ae8f-ae304e314a6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949874966 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.3949874966
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.2168490493
Short name T190
Test name
Test status
Simulation time 85846666450 ps
CPU time 74.8 seconds
Started Mar 07 12:29:35 PM PST 24
Finished Mar 07 12:30:50 PM PST 24
Peak memory 183972 kb
Host smart-2999a204-e6d2-4632-849f-1f7983f81c42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168490493 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_
all.2168490493
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.3319646619
Short name T275
Test name
Test status
Simulation time 82581532007 ps
CPU time 168.91 seconds
Started Mar 07 12:29:31 PM PST 24
Finished Mar 07 12:32:21 PM PST 24
Peak memory 198724 kb
Host smart-e0f9b64e-c434-4e8c-a94b-0248fa42dacd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319646619 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.3319646619
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.aon_timer_jump.1998881344
Short name T221
Test name
Test status
Simulation time 400617455 ps
CPU time 0.91 seconds
Started Mar 07 12:29:07 PM PST 24
Finished Mar 07 12:29:08 PM PST 24
Peak memory 183960 kb
Host smart-6af6966e-8093-4d3a-9971-bb7b27e9aabf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998881344 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.1998881344
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.3690822512
Short name T234
Test name
Test status
Simulation time 52639957301 ps
CPU time 77.88 seconds
Started Mar 07 12:29:26 PM PST 24
Finished Mar 07 12:30:44 PM PST 24
Peak memory 192172 kb
Host smart-8263ccaa-fa8b-4ef2-a950-9f9e47d0b106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690822512 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.3690822512
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.3224303774
Short name T126
Test name
Test status
Simulation time 555758590 ps
CPU time 1.42 seconds
Started Mar 07 12:29:17 PM PST 24
Finished Mar 07 12:29:19 PM PST 24
Peak memory 183848 kb
Host smart-e8f96fc8-b271-4a2a-aba7-cae006764039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224303774 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.3224303774
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.317752538
Short name T194
Test name
Test status
Simulation time 155589567869 ps
CPU time 52.96 seconds
Started Mar 07 12:29:30 PM PST 24
Finished Mar 07 12:30:23 PM PST 24
Peak memory 183976 kb
Host smart-54d23db0-6c8f-4971-bedc-19174e0e2b72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317752538 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_a
ll.317752538
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/35.aon_timer_jump.1818555975
Short name T122
Test name
Test status
Simulation time 400946352 ps
CPU time 0.81 seconds
Started Mar 07 12:29:10 PM PST 24
Finished Mar 07 12:29:11 PM PST 24
Peak memory 183816 kb
Host smart-fb3d727f-6a79-490f-8d1e-342adf4b4356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818555975 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.1818555975
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.479288628
Short name T74
Test name
Test status
Simulation time 21363040547 ps
CPU time 7.89 seconds
Started Mar 07 12:29:15 PM PST 24
Finished Mar 07 12:29:23 PM PST 24
Peak memory 183840 kb
Host smart-67f25c2d-cc31-4b3e-a69d-be6eece59caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479288628 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.479288628
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.4039588516
Short name T214
Test name
Test status
Simulation time 546061291 ps
CPU time 1.4 seconds
Started Mar 07 12:29:31 PM PST 24
Finished Mar 07 12:29:33 PM PST 24
Peak memory 183852 kb
Host smart-c89f4556-c209-4bc2-9e46-5b5eea9cb287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039588516 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.4039588516
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.1991340015
Short name T99
Test name
Test status
Simulation time 267665006088 ps
CPU time 328.97 seconds
Started Mar 07 12:29:15 PM PST 24
Finished Mar 07 12:34:44 PM PST 24
Peak memory 198684 kb
Host smart-05cf60bf-42ff-4073-bf3f-68de099e564e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991340015 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.1991340015
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.aon_timer_jump.1923860777
Short name T231
Test name
Test status
Simulation time 475556340 ps
CPU time 0.73 seconds
Started Mar 07 12:29:28 PM PST 24
Finished Mar 07 12:29:29 PM PST 24
Peak memory 183544 kb
Host smart-eaf05157-0e09-42e0-a883-5ccaedc47615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923860777 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.1923860777
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.3598527376
Short name T262
Test name
Test status
Simulation time 61512050206 ps
CPU time 24.39 seconds
Started Mar 07 12:29:17 PM PST 24
Finished Mar 07 12:29:42 PM PST 24
Peak memory 183844 kb
Host smart-cb4c9823-2309-4bbd-b6df-00df84b7118a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598527376 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.3598527376
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.3420698988
Short name T174
Test name
Test status
Simulation time 519957058 ps
CPU time 1.31 seconds
Started Mar 07 12:29:18 PM PST 24
Finished Mar 07 12:29:20 PM PST 24
Peak memory 183764 kb
Host smart-902bad84-a1e9-4df8-bece-d795e9f5cced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420698988 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.3420698988
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.2961190894
Short name T112
Test name
Test status
Simulation time 119266276862 ps
CPU time 86.44 seconds
Started Mar 07 12:29:21 PM PST 24
Finished Mar 07 12:30:47 PM PST 24
Peak memory 184068 kb
Host smart-f72333c5-8b95-4c9b-8dcd-ec27d8e7a26b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961190894 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_
all.2961190894
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.1145135440
Short name T258
Test name
Test status
Simulation time 126320745855 ps
CPU time 368.08 seconds
Started Mar 07 12:29:27 PM PST 24
Finished Mar 07 12:35:35 PM PST 24
Peak memory 198816 kb
Host smart-e7d16c5b-688d-468f-8676-fe4e08865d6c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145135440 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.1145135440
Directory /workspace/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.aon_timer_jump.1192153555
Short name T151
Test name
Test status
Simulation time 503752826 ps
CPU time 0.77 seconds
Started Mar 07 12:29:19 PM PST 24
Finished Mar 07 12:29:20 PM PST 24
Peak memory 183732 kb
Host smart-24a09048-990f-40d5-afc7-f3fe3baa6276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192153555 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.1192153555
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.3742106724
Short name T164
Test name
Test status
Simulation time 42072336817 ps
CPU time 64.25 seconds
Started Mar 07 12:29:21 PM PST 24
Finished Mar 07 12:30:25 PM PST 24
Peak memory 183852 kb
Host smart-c4b00961-e578-464d-8ac8-69dcba019af3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742106724 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.3742106724
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.1016186936
Short name T131
Test name
Test status
Simulation time 525170117 ps
CPU time 0.73 seconds
Started Mar 07 12:29:21 PM PST 24
Finished Mar 07 12:29:22 PM PST 24
Peak memory 183748 kb
Host smart-43ebee0b-bad0-4d4c-88a8-6e8f17347163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016186936 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.1016186936
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.290830422
Short name T32
Test name
Test status
Simulation time 88348239861 ps
CPU time 35.74 seconds
Started Mar 07 12:29:25 PM PST 24
Finished Mar 07 12:30:01 PM PST 24
Peak memory 183904 kb
Host smart-9315ec83-4e8d-4ca9-8542-b413602e79b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290830422 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_a
ll.290830422
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.1323249416
Short name T41
Test name
Test status
Simulation time 197255602480 ps
CPU time 424.4 seconds
Started Mar 07 12:29:26 PM PST 24
Finished Mar 07 12:36:31 PM PST 24
Peak memory 198836 kb
Host smart-0a743880-2e43-4d5a-a89c-f574a919e43e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323249416 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.1323249416
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.aon_timer_jump.1768434652
Short name T26
Test name
Test status
Simulation time 487283014 ps
CPU time 1.2 seconds
Started Mar 07 12:29:24 PM PST 24
Finished Mar 07 12:29:25 PM PST 24
Peak memory 183812 kb
Host smart-b46c513b-c98f-4b8d-bb7f-0985aecdca56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768434652 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.1768434652
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.2848528340
Short name T247
Test name
Test status
Simulation time 23401486157 ps
CPU time 34.63 seconds
Started Mar 07 12:29:21 PM PST 24
Finished Mar 07 12:29:56 PM PST 24
Peak memory 192120 kb
Host smart-8fb51dce-749d-4572-bbd4-8525d99a1219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848528340 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.2848528340
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.1495818318
Short name T276
Test name
Test status
Simulation time 368508364 ps
CPU time 1.13 seconds
Started Mar 07 12:29:17 PM PST 24
Finished Mar 07 12:29:19 PM PST 24
Peak memory 183728 kb
Host smart-3c97b2f0-2171-4ee2-99be-beb87fa9af2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495818318 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.1495818318
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.1512603182
Short name T136
Test name
Test status
Simulation time 236553382806 ps
CPU time 125.58 seconds
Started Mar 07 12:29:17 PM PST 24
Finished Mar 07 12:31:23 PM PST 24
Peak memory 184080 kb
Host smart-f78b8728-9a5a-4dfa-a077-26b8a35b3396
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512603182 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_
all.1512603182
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_jump.3825509265
Short name T191
Test name
Test status
Simulation time 372703318 ps
CPU time 0.78 seconds
Started Mar 07 12:29:23 PM PST 24
Finished Mar 07 12:29:24 PM PST 24
Peak memory 183812 kb
Host smart-453553a3-26b1-4e8b-aece-9b011f00f8d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825509265 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.3825509265
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.1496097684
Short name T245
Test name
Test status
Simulation time 3203136643 ps
CPU time 2.97 seconds
Started Mar 07 12:29:41 PM PST 24
Finished Mar 07 12:29:44 PM PST 24
Peak memory 183936 kb
Host smart-cb77a09b-a549-4344-ac24-828796688f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496097684 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.1496097684
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.3598126958
Short name T144
Test name
Test status
Simulation time 509058442 ps
CPU time 0.73 seconds
Started Mar 07 12:29:33 PM PST 24
Finished Mar 07 12:29:35 PM PST 24
Peak memory 182968 kb
Host smart-33b0d38d-084a-4eb0-8d75-7ea515a8e39b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598126958 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.3598126958
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.2409043496
Short name T257
Test name
Test status
Simulation time 190809700006 ps
CPU time 16.69 seconds
Started Mar 07 12:29:37 PM PST 24
Finished Mar 07 12:29:54 PM PST 24
Peak memory 194484 kb
Host smart-cd732062-5c45-4310-8509-63d7aa0dd1c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409043496 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_
all.2409043496
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.2985384589
Short name T92
Test name
Test status
Simulation time 102701077590 ps
CPU time 741.25 seconds
Started Mar 07 12:29:32 PM PST 24
Finished Mar 07 12:41:53 PM PST 24
Peak memory 201668 kb
Host smart-9329aaf2-10ce-4e09-abb3-ea4b940de64c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985384589 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.2985384589
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_jump.2733358246
Short name T124
Test name
Test status
Simulation time 365276891 ps
CPU time 1.11 seconds
Started Mar 07 12:29:09 PM PST 24
Finished Mar 07 12:29:10 PM PST 24
Peak memory 183768 kb
Host smart-99aae923-3bc6-4df4-b9fa-bfcedd11e303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733358246 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.2733358246
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.1368780158
Short name T188
Test name
Test status
Simulation time 26851937150 ps
CPU time 10.97 seconds
Started Mar 07 12:29:08 PM PST 24
Finished Mar 07 12:29:19 PM PST 24
Peak memory 184080 kb
Host smart-b2c35684-4383-471b-8e3b-36d7518d9125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368780158 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.1368780158
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.2460203733
Short name T17
Test name
Test status
Simulation time 8255831636 ps
CPU time 4.73 seconds
Started Mar 07 12:28:56 PM PST 24
Finished Mar 07 12:29:01 PM PST 24
Peak memory 215656 kb
Host smart-a818285a-00e6-4844-a1ca-888ac0478ea1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460203733 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.2460203733
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.968658428
Short name T167
Test name
Test status
Simulation time 525897924 ps
CPU time 0.9 seconds
Started Mar 07 12:29:11 PM PST 24
Finished Mar 07 12:29:12 PM PST 24
Peak memory 184016 kb
Host smart-36d79824-0f87-4a15-b586-2341f8aa225f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968658428 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.968658428
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.3867550070
Short name T274
Test name
Test status
Simulation time 118565168608 ps
CPU time 191.47 seconds
Started Mar 07 12:29:06 PM PST 24
Finished Mar 07 12:32:17 PM PST 24
Peak memory 194504 kb
Host smart-c2103047-122e-4481-aae5-6d43e8ff9e45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867550070 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_a
ll.3867550070
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_jump.651852811
Short name T169
Test name
Test status
Simulation time 370662042 ps
CPU time 1.09 seconds
Started Mar 07 12:29:37 PM PST 24
Finished Mar 07 12:29:39 PM PST 24
Peak memory 183824 kb
Host smart-435a3299-49e1-47be-8956-c5ad04384dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651852811 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.651852811
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.1147440981
Short name T75
Test name
Test status
Simulation time 9910116612 ps
CPU time 16.38 seconds
Started Mar 07 12:29:43 PM PST 24
Finished Mar 07 12:30:00 PM PST 24
Peak memory 183900 kb
Host smart-1f4c2276-3fe3-4b31-ac62-ccb5de2f4a45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147440981 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.1147440981
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.1848054812
Short name T21
Test name
Test status
Simulation time 490916686 ps
CPU time 1.17 seconds
Started Mar 07 12:29:21 PM PST 24
Finished Mar 07 12:29:22 PM PST 24
Peak memory 183740 kb
Host smart-3e51188c-5670-4c8d-9c95-505c12907159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848054812 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.1848054812
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.2111711926
Short name T5
Test name
Test status
Simulation time 406402802807 ps
CPU time 130.3 seconds
Started Mar 07 12:29:28 PM PST 24
Finished Mar 07 12:31:39 PM PST 24
Peak memory 183940 kb
Host smart-416e73f2-7d5e-4346-a1a8-dcd1e886d061
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111711926 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_
all.2111711926
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.1609511656
Short name T239
Test name
Test status
Simulation time 127533946888 ps
CPU time 1381.81 seconds
Started Mar 07 12:29:20 PM PST 24
Finished Mar 07 12:52:22 PM PST 24
Peak memory 211044 kb
Host smart-2659c3d9-5146-44c2-bb95-0933538ce851
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609511656 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.1609511656
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.aon_timer_jump.532628522
Short name T187
Test name
Test status
Simulation time 500020574 ps
CPU time 0.75 seconds
Started Mar 07 12:29:35 PM PST 24
Finished Mar 07 12:29:36 PM PST 24
Peak memory 183368 kb
Host smart-5f5c9c3b-b6bf-4b5d-b63a-220cc36dbe86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532628522 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.532628522
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.3122955290
Short name T145
Test name
Test status
Simulation time 18274217569 ps
CPU time 2.19 seconds
Started Mar 07 12:29:23 PM PST 24
Finished Mar 07 12:29:25 PM PST 24
Peak memory 183932 kb
Host smart-5628c5b3-2c5b-4839-a413-d1dcbe36f8a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122955290 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.3122955290
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.390669887
Short name T147
Test name
Test status
Simulation time 390555161 ps
CPU time 0.79 seconds
Started Mar 07 12:29:30 PM PST 24
Finished Mar 07 12:29:30 PM PST 24
Peak memory 183840 kb
Host smart-3d991691-46e4-46c6-a7a1-6fcf94ce6051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390669887 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.390669887
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.2375626093
Short name T24
Test name
Test status
Simulation time 141035355615 ps
CPU time 62.7 seconds
Started Mar 07 12:29:18 PM PST 24
Finished Mar 07 12:30:20 PM PST 24
Peak memory 184080 kb
Host smart-a70eb71c-d562-4e8e-a16a-aab207f9461f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375626093 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_
all.2375626093
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.3998054309
Short name T36
Test name
Test status
Simulation time 26063686689 ps
CPU time 192.73 seconds
Started Mar 07 12:29:20 PM PST 24
Finished Mar 07 12:32:33 PM PST 24
Peak memory 198808 kb
Host smart-f1a9df27-857f-4b7f-b513-d845cc611173
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998054309 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.3998054309
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.aon_timer_jump.2928893537
Short name T10
Test name
Test status
Simulation time 580183047 ps
CPU time 0.7 seconds
Started Mar 07 12:29:35 PM PST 24
Finished Mar 07 12:29:36 PM PST 24
Peak memory 183788 kb
Host smart-32f62fc4-478e-433f-8993-295a1e8b76a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928893537 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.2928893537
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.1089173709
Short name T271
Test name
Test status
Simulation time 1142645109 ps
CPU time 0.97 seconds
Started Mar 07 12:29:17 PM PST 24
Finished Mar 07 12:29:18 PM PST 24
Peak memory 183964 kb
Host smart-cc61a5b2-d395-44f5-b622-e8eb7755e18d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089173709 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.1089173709
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.673572840
Short name T189
Test name
Test status
Simulation time 402504336 ps
CPU time 0.69 seconds
Started Mar 07 12:29:26 PM PST 24
Finished Mar 07 12:29:27 PM PST 24
Peak memory 183944 kb
Host smart-e6cfe378-4964-485a-b4e3-e824a0ce7615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673572840 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.673572840
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.2633529971
Short name T97
Test name
Test status
Simulation time 178742817499 ps
CPU time 317.7 seconds
Started Mar 07 12:29:23 PM PST 24
Finished Mar 07 12:34:41 PM PST 24
Peak memory 198736 kb
Host smart-81691f39-ce06-41ff-91bc-6c94c5d258fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633529971 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.2633529971
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.aon_timer_jump.2685803034
Short name T118
Test name
Test status
Simulation time 550306880 ps
CPU time 0.75 seconds
Started Mar 07 12:29:25 PM PST 24
Finished Mar 07 12:29:25 PM PST 24
Peak memory 183868 kb
Host smart-6f046860-2b97-4a52-bc5d-f0bab0cc0a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685803034 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.2685803034
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.2992878839
Short name T111
Test name
Test status
Simulation time 45213099309 ps
CPU time 18.43 seconds
Started Mar 07 12:29:35 PM PST 24
Finished Mar 07 12:29:54 PM PST 24
Peak memory 183936 kb
Host smart-a047a4cc-83d2-410e-89b7-1508990aa357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992878839 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.2992878839
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.4044361458
Short name T9
Test name
Test status
Simulation time 538155940 ps
CPU time 0.78 seconds
Started Mar 07 12:29:34 PM PST 24
Finished Mar 07 12:29:36 PM PST 24
Peak memory 183964 kb
Host smart-36e40f68-ca0f-4a23-9f50-58f810557b95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044361458 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.4044361458
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.498030633
Short name T149
Test name
Test status
Simulation time 303004525494 ps
CPU time 104.7 seconds
Started Mar 07 12:29:39 PM PST 24
Finished Mar 07 12:31:24 PM PST 24
Peak memory 183900 kb
Host smart-1a27cf59-bda4-4444-885a-b02d186fdc78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498030633 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_a
ll.498030633
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_jump.748776594
Short name T282
Test name
Test status
Simulation time 360990842 ps
CPU time 0.68 seconds
Started Mar 07 12:29:24 PM PST 24
Finished Mar 07 12:29:30 PM PST 24
Peak memory 183748 kb
Host smart-49d06f0c-49d6-4c98-8f26-e1a4d60ff323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748776594 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.748776594
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.670974074
Short name T2
Test name
Test status
Simulation time 11817793343 ps
CPU time 20.09 seconds
Started Mar 07 12:29:25 PM PST 24
Finished Mar 07 12:29:45 PM PST 24
Peak memory 183940 kb
Host smart-82f4d1b3-cbf9-456c-8aa5-acf89ac62693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670974074 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.670974074
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.1496854441
Short name T56
Test name
Test status
Simulation time 459671811 ps
CPU time 1.17 seconds
Started Mar 07 12:29:24 PM PST 24
Finished Mar 07 12:29:25 PM PST 24
Peak memory 183800 kb
Host smart-cdc34910-8f0b-4f07-b646-e791dc8cdca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496854441 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.1496854441
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.3246452988
Short name T155
Test name
Test status
Simulation time 160239139470 ps
CPU time 177.32 seconds
Started Mar 07 12:29:24 PM PST 24
Finished Mar 07 12:32:22 PM PST 24
Peak memory 183940 kb
Host smart-c7bffdf7-83ea-49c5-8877-f9167c3555b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246452988 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_
all.3246452988
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.3218768732
Short name T40
Test name
Test status
Simulation time 259425484465 ps
CPU time 497.14 seconds
Started Mar 07 12:29:24 PM PST 24
Finished Mar 07 12:37:42 PM PST 24
Peak memory 198760 kb
Host smart-6fbbbdc9-2012-4fd5-8665-e80b6787a8c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218768732 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.3218768732
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.aon_timer_jump.3395298171
Short name T113
Test name
Test status
Simulation time 417074338 ps
CPU time 0.87 seconds
Started Mar 07 12:29:27 PM PST 24
Finished Mar 07 12:29:28 PM PST 24
Peak memory 183716 kb
Host smart-2ce5bc1d-4f5f-4775-8be9-12c518b0199a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395298171 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.3395298171
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.4081388777
Short name T133
Test name
Test status
Simulation time 5479077753 ps
CPU time 1.83 seconds
Started Mar 07 12:31:02 PM PST 24
Finished Mar 07 12:31:05 PM PST 24
Peak memory 183772 kb
Host smart-c904eb0e-eed2-434a-9d91-e68a04f16b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081388777 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.4081388777
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.3391917391
Short name T77
Test name
Test status
Simulation time 434515015 ps
CPU time 0.88 seconds
Started Mar 07 12:29:35 PM PST 24
Finished Mar 07 12:29:36 PM PST 24
Peak memory 183788 kb
Host smart-41dd4eca-365a-4d12-b9e1-0ad250c06c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391917391 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.3391917391
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.1684540152
Short name T1
Test name
Test status
Simulation time 636577104807 ps
CPU time 94.69 seconds
Started Mar 07 12:29:31 PM PST 24
Finished Mar 07 12:31:06 PM PST 24
Peak memory 194184 kb
Host smart-a3c56c9c-b8fa-4bc2-8c6c-1e2f1fb40a45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684540152 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_
all.1684540152
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.275444142
Short name T223
Test name
Test status
Simulation time 40098439398 ps
CPU time 423.58 seconds
Started Mar 07 12:29:37 PM PST 24
Finished Mar 07 12:36:41 PM PST 24
Peak memory 198764 kb
Host smart-d22298bc-2d6f-4b1c-a7f1-eea16c0acf03
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275444142 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.275444142
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.aon_timer_jump.3379998466
Short name T219
Test name
Test status
Simulation time 518494846 ps
CPU time 0.91 seconds
Started Mar 07 12:29:24 PM PST 24
Finished Mar 07 12:29:25 PM PST 24
Peak memory 183764 kb
Host smart-d049e363-183c-44a2-acee-8c27baff4f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379998466 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.3379998466
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.1184136784
Short name T125
Test name
Test status
Simulation time 7429605026 ps
CPU time 1.17 seconds
Started Mar 07 12:31:02 PM PST 24
Finished Mar 07 12:31:04 PM PST 24
Peak memory 183772 kb
Host smart-c72aed00-dfe3-4bce-b558-ce76612e55d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184136784 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.1184136784
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.1421621099
Short name T264
Test name
Test status
Simulation time 338577584 ps
CPU time 1.01 seconds
Started Mar 07 12:29:38 PM PST 24
Finished Mar 07 12:29:40 PM PST 24
Peak memory 183788 kb
Host smart-3848fe51-f8ce-4837-9d8a-ec6d3be41781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421621099 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.1421621099
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.463834131
Short name T11
Test name
Test status
Simulation time 35709137898 ps
CPU time 58.18 seconds
Started Mar 07 12:29:25 PM PST 24
Finished Mar 07 12:30:24 PM PST 24
Peak memory 183940 kb
Host smart-fb9b3b39-2c7b-4113-8596-95045e4e44df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463834131 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_a
ll.463834131
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_jump.2635347419
Short name T19
Test name
Test status
Simulation time 587558936 ps
CPU time 0.78 seconds
Started Mar 07 12:29:24 PM PST 24
Finished Mar 07 12:29:24 PM PST 24
Peak memory 183916 kb
Host smart-7890a502-f8d5-40b6-9448-454b111de219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635347419 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.2635347419
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.786670897
Short name T213
Test name
Test status
Simulation time 38205380419 ps
CPU time 60.14 seconds
Started Mar 07 12:29:26 PM PST 24
Finished Mar 07 12:30:26 PM PST 24
Peak memory 184056 kb
Host smart-0ebd8b5c-0d95-4f30-b57e-97a4badee5d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786670897 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.786670897
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.4272033313
Short name T249
Test name
Test status
Simulation time 365382443 ps
CPU time 1.01 seconds
Started Mar 07 12:31:02 PM PST 24
Finished Mar 07 12:31:04 PM PST 24
Peak memory 183580 kb
Host smart-13ec0a14-52c4-4ca5-978a-db259825d452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272033313 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.4272033313
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.3160596620
Short name T178
Test name
Test status
Simulation time 39499028904 ps
CPU time 3.91 seconds
Started Mar 07 12:29:36 PM PST 24
Finished Mar 07 12:29:40 PM PST 24
Peak memory 183944 kb
Host smart-8b143877-12cf-4d16-875f-775a96581173
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160596620 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_
all.3160596620
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.3569278313
Short name T168
Test name
Test status
Simulation time 19533995312 ps
CPU time 202.02 seconds
Started Mar 07 12:29:45 PM PST 24
Finished Mar 07 12:33:08 PM PST 24
Peak memory 198820 kb
Host smart-9a276e59-7884-4bf8-a1ef-d29a249f702f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569278313 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.3569278313
Directory /workspace/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_jump.32093699
Short name T175
Test name
Test status
Simulation time 595626062 ps
CPU time 0.8 seconds
Started Mar 07 12:29:26 PM PST 24
Finished Mar 07 12:29:27 PM PST 24
Peak memory 183944 kb
Host smart-799b444f-af00-47b0-b97a-65dd21e3d498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32093699 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.32093699
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.238554767
Short name T196
Test name
Test status
Simulation time 23706495873 ps
CPU time 10.36 seconds
Started Mar 07 12:29:26 PM PST 24
Finished Mar 07 12:29:36 PM PST 24
Peak memory 192048 kb
Host smart-f4f9e1f1-52f4-4ad9-9bb5-dacb5a42ad86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238554767 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.238554767
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.1403778664
Short name T119
Test name
Test status
Simulation time 588157476 ps
CPU time 0.75 seconds
Started Mar 07 12:31:02 PM PST 24
Finished Mar 07 12:31:03 PM PST 24
Peak memory 183540 kb
Host smart-06e6c4b3-5b74-4f26-8a37-2fc21e5da913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403778664 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.1403778664
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.1757322668
Short name T143
Test name
Test status
Simulation time 56244072959 ps
CPU time 27.99 seconds
Started Mar 07 12:29:25 PM PST 24
Finished Mar 07 12:29:53 PM PST 24
Peak memory 194456 kb
Host smart-4a52b127-12cc-4cd8-8c2a-a252bb72d755
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757322668 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_
all.1757322668
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.2480752649
Short name T161
Test name
Test status
Simulation time 41685348978 ps
CPU time 448.53 seconds
Started Mar 07 12:29:28 PM PST 24
Finished Mar 07 12:36:57 PM PST 24
Peak memory 198720 kb
Host smart-39091174-d717-4cdf-9594-456e8779200c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480752649 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.2480752649
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.aon_timer_jump.2576045777
Short name T134
Test name
Test status
Simulation time 566803031 ps
CPU time 1.41 seconds
Started Mar 07 12:29:27 PM PST 24
Finished Mar 07 12:29:28 PM PST 24
Peak memory 183724 kb
Host smart-ed3f889c-17a8-452a-b00d-f7b1419fae56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576045777 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.2576045777
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.2454625554
Short name T57
Test name
Test status
Simulation time 29997961918 ps
CPU time 22.02 seconds
Started Mar 07 12:29:28 PM PST 24
Finished Mar 07 12:29:50 PM PST 24
Peak memory 184184 kb
Host smart-47ec4795-eec0-4d8b-a015-697a9d984e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454625554 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.2454625554
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.1177002755
Short name T132
Test name
Test status
Simulation time 389789094 ps
CPU time 0.84 seconds
Started Mar 07 12:29:25 PM PST 24
Finished Mar 07 12:29:26 PM PST 24
Peak memory 183748 kb
Host smart-08c42cef-4aa5-4afb-b1a9-e9136392cd22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177002755 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.1177002755
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.3883500329
Short name T226
Test name
Test status
Simulation time 59185678900 ps
CPU time 94.86 seconds
Started Mar 07 12:29:42 PM PST 24
Finished Mar 07 12:31:17 PM PST 24
Peak memory 194424 kb
Host smart-0cb0641e-e3ed-4028-a30c-72cf8577d64a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883500329 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_
all.3883500329
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.1462858508
Short name T71
Test name
Test status
Simulation time 388535377954 ps
CPU time 905.87 seconds
Started Mar 07 12:29:31 PM PST 24
Finished Mar 07 12:44:37 PM PST 24
Peak memory 204064 kb
Host smart-bf85cf65-e180-42ba-b3bb-04b50b7d652e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462858508 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.1462858508
Directory /workspace/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.aon_timer_jump.403458280
Short name T267
Test name
Test status
Simulation time 520832543 ps
CPU time 0.78 seconds
Started Mar 07 12:29:00 PM PST 24
Finished Mar 07 12:29:00 PM PST 24
Peak memory 183784 kb
Host smart-8153eb1d-bf2c-4f2f-853a-bd548f279191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403458280 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.403458280
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.2268945417
Short name T238
Test name
Test status
Simulation time 19322340566 ps
CPU time 3.65 seconds
Started Mar 07 12:29:09 PM PST 24
Finished Mar 07 12:29:12 PM PST 24
Peak memory 183888 kb
Host smart-daa56d61-dd4d-4f55-89b1-ddb89c6a9de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268945417 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.2268945417
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.3939677910
Short name T193
Test name
Test status
Simulation time 534391413 ps
CPU time 0.81 seconds
Started Mar 07 12:29:06 PM PST 24
Finished Mar 07 12:29:08 PM PST 24
Peak memory 183812 kb
Host smart-121b6403-5410-4e04-9feb-71c3bf91fcf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939677910 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.3939677910
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.3354866993
Short name T224
Test name
Test status
Simulation time 3280968500 ps
CPU time 1.92 seconds
Started Mar 07 12:29:05 PM PST 24
Finished Mar 07 12:29:07 PM PST 24
Peak memory 184088 kb
Host smart-cd1ab4d9-331e-4e86-ab7b-d7c5e23c73a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354866993 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_a
ll.3354866993
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.1826937159
Short name T52
Test name
Test status
Simulation time 22750055519 ps
CPU time 166.03 seconds
Started Mar 07 12:29:10 PM PST 24
Finished Mar 07 12:31:56 PM PST 24
Peak memory 198828 kb
Host smart-fbae1f09-a737-4719-823e-46b9d88c72c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826937159 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.1826937159
Directory /workspace/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.aon_timer_jump.3103093893
Short name T210
Test name
Test status
Simulation time 429588469 ps
CPU time 1.19 seconds
Started Mar 07 12:29:01 PM PST 24
Finished Mar 07 12:29:03 PM PST 24
Peak memory 183968 kb
Host smart-4af63a97-e374-4820-aeeb-c0e0a133f6fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103093893 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.3103093893
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.855765645
Short name T139
Test name
Test status
Simulation time 24729928102 ps
CPU time 37.8 seconds
Started Mar 07 12:29:11 PM PST 24
Finished Mar 07 12:29:49 PM PST 24
Peak memory 183956 kb
Host smart-1e65a32a-d709-4b47-9fe2-6845a061ac43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855765645 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.855765645
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.393076768
Short name T141
Test name
Test status
Simulation time 477539202 ps
CPU time 1.24 seconds
Started Mar 07 12:29:03 PM PST 24
Finished Mar 07 12:29:04 PM PST 24
Peak memory 183832 kb
Host smart-0c1f676e-64e0-42e6-b1f1-6228aca63a75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393076768 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.393076768
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.4161120478
Short name T237
Test name
Test status
Simulation time 194616010154 ps
CPU time 307.17 seconds
Started Mar 07 12:29:06 PM PST 24
Finished Mar 07 12:34:14 PM PST 24
Peak memory 183896 kb
Host smart-d5968ef1-24c7-4069-a6c3-b2d40d448019
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161120478 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_a
ll.4161120478
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_jump.3754150544
Short name T202
Test name
Test status
Simulation time 441629344 ps
CPU time 0.79 seconds
Started Mar 07 12:28:59 PM PST 24
Finished Mar 07 12:29:00 PM PST 24
Peak memory 183856 kb
Host smart-25e15a03-a088-4b52-8f02-94148f9f7506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754150544 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.3754150544
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.3522452793
Short name T176
Test name
Test status
Simulation time 59489486530 ps
CPU time 23.42 seconds
Started Mar 07 12:29:04 PM PST 24
Finished Mar 07 12:29:28 PM PST 24
Peak memory 183892 kb
Host smart-5f677405-e285-4097-a647-9796dc7515a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522452793 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.3522452793
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.2623906295
Short name T20
Test name
Test status
Simulation time 397824706 ps
CPU time 1.1 seconds
Started Mar 07 12:29:07 PM PST 24
Finished Mar 07 12:29:08 PM PST 24
Peak memory 183908 kb
Host smart-308a50f5-6f34-4cc3-9332-c541569525e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623906295 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.2623906295
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.3065085220
Short name T101
Test name
Test status
Simulation time 66440344286 ps
CPU time 24.85 seconds
Started Mar 07 12:29:09 PM PST 24
Finished Mar 07 12:29:34 PM PST 24
Peak memory 195292 kb
Host smart-2d9f5b92-7afe-47c7-b2c4-4d4335a1c531
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065085220 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_a
ll.3065085220
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.1056670377
Short name T181
Test name
Test status
Simulation time 392337099542 ps
CPU time 811.88 seconds
Started Mar 07 12:29:09 PM PST 24
Finished Mar 07 12:42:41 PM PST 24
Peak memory 201944 kb
Host smart-9551d370-8142-46b4-a253-ead432281a3a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056670377 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.1056670377
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.aon_timer_jump.1046023197
Short name T53
Test name
Test status
Simulation time 533766090 ps
CPU time 1.39 seconds
Started Mar 07 12:29:06 PM PST 24
Finished Mar 07 12:29:08 PM PST 24
Peak memory 183816 kb
Host smart-c5668f3f-0741-4108-93eb-535d08c8e208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046023197 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.1046023197
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.2237938176
Short name T42
Test name
Test status
Simulation time 46420042968 ps
CPU time 75.42 seconds
Started Mar 07 12:29:05 PM PST 24
Finished Mar 07 12:30:21 PM PST 24
Peak memory 183936 kb
Host smart-3a421287-7326-4ae0-b0ba-4b003fd37009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237938176 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.2237938176
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.3963154934
Short name T7
Test name
Test status
Simulation time 623894011 ps
CPU time 0.8 seconds
Started Mar 07 12:29:02 PM PST 24
Finished Mar 07 12:29:03 PM PST 24
Peak memory 183816 kb
Host smart-06b95847-a8f3-44a6-974b-e176616dac84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963154934 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.3963154934
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.2407881120
Short name T46
Test name
Test status
Simulation time 266816079721 ps
CPU time 105.85 seconds
Started Mar 07 12:29:01 PM PST 24
Finished Mar 07 12:30:47 PM PST 24
Peak memory 190560 kb
Host smart-697594df-ec2d-4a42-9406-6cd0c7eafe27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407881120 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_a
ll.2407881120
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.1221572433
Short name T8
Test name
Test status
Simulation time 167906031362 ps
CPU time 250.03 seconds
Started Mar 07 12:29:10 PM PST 24
Finished Mar 07 12:33:21 PM PST 24
Peak memory 198780 kb
Host smart-aa5a89ac-0169-4b6d-a97e-0ba6ea6caed5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221572433 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.1221572433
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.aon_timer_jump.578204204
Short name T72
Test name
Test status
Simulation time 570457275 ps
CPU time 1.38 seconds
Started Mar 07 12:29:17 PM PST 24
Finished Mar 07 12:29:19 PM PST 24
Peak memory 183784 kb
Host smart-6b5e9bb3-41b8-4486-bb30-4a8cfe925408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578204204 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.578204204
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.1361605316
Short name T182
Test name
Test status
Simulation time 61655224471 ps
CPU time 23.81 seconds
Started Mar 07 12:29:10 PM PST 24
Finished Mar 07 12:29:34 PM PST 24
Peak memory 183740 kb
Host smart-a50b12eb-5d0b-4341-959e-268be64c638d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361605316 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.1361605316
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.1610502750
Short name T240
Test name
Test status
Simulation time 492696864 ps
CPU time 0.93 seconds
Started Mar 07 12:29:16 PM PST 24
Finished Mar 07 12:29:17 PM PST 24
Peak memory 183788 kb
Host smart-fb66a93d-688a-483c-b2f4-e3fe4d507016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610502750 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.1610502750
Directory /workspace/9.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.194705105
Short name T142
Test name
Test status
Simulation time 93316325855 ps
CPU time 31.04 seconds
Started Mar 07 12:29:09 PM PST 24
Finished Mar 07 12:29:40 PM PST 24
Peak memory 194448 kb
Host smart-992ed620-6a32-4cd8-bc07-98388144ac13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194705105 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_al
l.194705105
Directory /workspace/9.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.2153425289
Short name T233
Test name
Test status
Simulation time 71700254882 ps
CPU time 518.02 seconds
Started Mar 07 12:29:02 PM PST 24
Finished Mar 07 12:37:40 PM PST 24
Peak memory 198764 kb
Host smart-e1e4763d-2268-49da-8111-891d7f921ff3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153425289 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.2153425289
Directory /workspace/9.aon_timer_stress_all_with_rand_reset/latest
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