Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
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Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
25.43 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv


Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 173 129 44 25.43


Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
bark_thold_cp 34 32 2 5.88 100 1 1 0
bite_thold_cp 34 32 2 5.88 100 1 1 0
pause_in_sleep_cp 2 1 1 50.00 100 1 1 2
prescale_cp 34 0 34 100.00 100 1 1 0
wdog_regwen_cp 2 0 2 100.00 100 1 1 2
wkup_cause_cp 1 0 1 100.00 100 1 1 0
wkup_thold_cp 66 64 2 3.03 100 1 1 0


Summary for Variable bark_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 32 2 5.88


User Defined Bins for bark_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
bark_max 0 1 1
bark[1] 0 1 1
bark[2] 0 1 1
bark[3] 0 1 1
bark[4] 0 1 1
bark[5] 0 1 1
bark[6] 0 1 1
bark[7] 0 1 1
bark[8] 0 1 1
bark[9] 0 1 1
bark[10] 0 1 1
bark[11] 0 1 1
bark[12] 0 1 1
bark[13] 0 1 1
bark[14] 0 1 1
bark[15] 0 1 1
bark[16] 0 1 1
bark[17] 0 1 1
bark[18] 0 1 1
bark[19] 0 1 1
bark[20] 0 1 1
bark[21] 0 1 1
bark[22] 0 1 1
bark[23] 0 1 1
bark[24] 0 1 1
bark[25] 0 1 1
bark[26] 0 1 1
bark[27] 0 1 1
bark[28] 0 1 1
bark[29] 0 1 1
bark[30] 0 1 1
bark[31] 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
bark[0] 52625 1 T1 1534 T2 288 T3 779
bark_0 4994 1 T1 84 T2 7 T3 98


Summary for Variable bite_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 32 2 5.88


User Defined Bins for bite_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
bite_max 0 1 1
bite[1] 0 1 1
bite[2] 0 1 1
bite[3] 0 1 1
bite[4] 0 1 1
bite[5] 0 1 1
bite[6] 0 1 1
bite[7] 0 1 1
bite[8] 0 1 1
bite[9] 0 1 1
bite[10] 0 1 1
bite[11] 0 1 1
bite[12] 0 1 1
bite[13] 0 1 1
bite[14] 0 1 1
bite[15] 0 1 1
bite[16] 0 1 1
bite[17] 0 1 1
bite[18] 0 1 1
bite[19] 0 1 1
bite[20] 0 1 1
bite[21] 0 1 1
bite[22] 0 1 1
bite[23] 0 1 1
bite[24] 0 1 1
bite[25] 0 1 1
bite[26] 0 1 1
bite[27] 0 1 1
bite[28] 0 1 1
bite[29] 0 1 1
bite[30] 0 1 1
bite[31] 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
bite[0] 52133 1 T1 1524 T2 287 T3 769
bite_0 5486 1 T1 94 T2 8 T3 108


Summary for Variable pause_in_sleep_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for pause_in_sleep_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 57619 1 T1 1618 T2 295 T3 877


Summary for Variable prescale_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 0 34 100.00


User Defined Bins for prescale_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
prescale_max 87 1 T87 76 T84 11 - -
prescale[0] 1530 1 T4 23 T10 24 T27 9
prescale[1] 938 1 T3 44 T39 56 T88 18
prescale[2] 979 1 T1 58 T3 2 T4 9
prescale[3] 1254 1 T1 28 T3 61 T10 19
prescale[4] 1018 1 T1 65 T3 48 T5 23
prescale[5] 1007 1 T1 117 T11 2 T44 23
prescale[6] 848 1 T1 40 T4 75 T8 9
prescale[7] 876 1 T1 62 T5 19 T89 18
prescale[8] 1033 1 T2 91 T3 24 T9 2
prescale[9] 1078 1 T5 29 T45 23 T38 40
prescale[10] 1415 1 T1 2 T9 32 T27 19
prescale[11] 954 1 T1 28 T2 9 T90 9
prescale[12] 622 1 T1 9 T38 54 T91 9
prescale[13] 805 1 T1 19 T3 2 T4 40
prescale[14] 1010 1 T3 96 T9 4 T38 19
prescale[15] 825 1 T2 70 T38 60 T39 52
prescale[16] 634 1 T1 54 T7 19 T44 19
prescale[17] 1003 1 T3 46 T9 2 T45 49
prescale[18] 935 1 T7 23 T9 128 T10 23
prescale[19] 1012 1 T1 55 T3 19 T38 2
prescale[20] 1077 1 T38 363 T40 20 T50 28
prescale[21] 465 1 T80 2 T92 40 T93 19
prescale[22] 1101 1 T1 19 T7 19 T10 44
prescale[23] 413 1 T3 2 T9 79 T45 19
prescale[24] 855 1 T1 175 T9 29 T10 19
prescale[25] 965 1 T1 40 T3 2 T10 19
prescale[26] 1024 1 T1 40 T11 2 T43 9
prescale[27] 940 1 T27 39 T89 40 T39 204
prescale[28] 914 1 T3 9 T38 168 T21 27
prescale[29] 499 1 T3 19 T9 2 T45 19
prescale[30] 941 1 T1 196 T27 2 T38 78
prescale[31] 1071 1 T1 30 T3 19 T27 64
prescale_0 27578 1 T1 581 T2 125 T3 484


Summary for Variable wdog_regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for wdog_regwen_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 43902 1 T1 1293 T2 136 T3 665
auto[1] 13717 1 T1 325 T2 159 T3 212


Summary for Variable wkup_cause_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for wkup_cause_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
wkup_cause_cleared 57619 1 T1 1618 T2 295 T3 877


Summary for Variable wkup_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 66 64 2 3.03


User Defined Bins for wkup_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
wkup_max 0 1 1
wkup[1] 0 1 1
wkup[2] 0 1 1
wkup[3] 0 1 1
wkup[4] 0 1 1
wkup[5] 0 1 1
wkup[6] 0 1 1
wkup[7] 0 1 1
wkup[8] 0 1 1
wkup[9] 0 1 1
wkup[10] 0 1 1
wkup[11] 0 1 1
wkup[12] 0 1 1
wkup[13] 0 1 1
wkup[14] 0 1 1
wkup[15] 0 1 1
wkup[16] 0 1 1
wkup[17] 0 1 1
wkup[18] 0 1 1
wkup[19] 0 1 1
wkup[20] 0 1 1
wkup[21] 0 1 1
wkup[22] 0 1 1
wkup[23] 0 1 1
wkup[24] 0 1 1
wkup[25] 0 1 1
wkup[26] 0 1 1
wkup[27] 0 1 1
wkup[28] 0 1 1
wkup[29] 0 1 1
wkup[30] 0 1 1
wkup[31] 0 1 1
wkup[32] 0 1 1
wkup[33] 0 1 1
wkup[34] 0 1 1
wkup[35] 0 1 1
wkup[36] 0 1 1
wkup[37] 0 1 1
wkup[38] 0 1 1
wkup[39] 0 1 1
wkup[40] 0 1 1
wkup[41] 0 1 1
wkup[42] 0 1 1
wkup[43] 0 1 1
wkup[44] 0 1 1
wkup[45] 0 1 1
wkup[46] 0 1 1
wkup[47] 0 1 1
wkup[48] 0 1 1
wkup[49] 0 1 1
wkup[50] 0 1 1
wkup[51] 0 1 1
wkup[52] 0 1 1
wkup[53] 0 1 1
wkup[54] 0 1 1
wkup[55] 0 1 1
wkup[56] 0 1 1
wkup[57] 0 1 1
wkup[58] 0 1 1
wkup[59] 0 1 1
wkup[60] 0 1 1
wkup[61] 0 1 1
wkup[62] 0 1 1
wkup[63] 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
wkup[0] 53690 1 T1 1554 T2 290 T3 799
wkup_0 3929 1 T1 64 T2 5 T3 78

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