Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
93.02 99.25 93.67 100.00 98.40 99.51 67.30


Total test records in report: 422
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T284 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.2209836639 Mar 10 12:33:45 PM PDT 24 Mar 10 12:33:46 PM PDT 24 328683822 ps
T30 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.30643510 Mar 10 12:30:09 PM PDT 24 Mar 10 12:30:10 PM PDT 24 583867902 ps
T31 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.268923709 Mar 10 12:32:53 PM PDT 24 Mar 10 12:32:53 PM PDT 24 638824199 ps
T285 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.2855211713 Mar 10 12:20:41 PM PDT 24 Mar 10 12:20:43 PM PDT 24 1336802408 ps
T102 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.3166610377 Mar 10 12:24:12 PM PDT 24 Mar 10 12:24:14 PM PDT 24 348808742 ps
T286 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.4190388494 Mar 10 12:24:10 PM PDT 24 Mar 10 12:24:11 PM PDT 24 648541663 ps
T287 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.2111385593 Mar 10 12:33:42 PM PDT 24 Mar 10 12:33:44 PM PDT 24 402422880 ps
T37 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.2145756458 Mar 10 12:19:54 PM PDT 24 Mar 10 12:19:57 PM PDT 24 1083935070 ps
T32 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.679759046 Mar 10 12:22:44 PM PDT 24 Mar 10 12:22:45 PM PDT 24 816451360 ps
T288 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.1736308055 Mar 10 12:32:54 PM PDT 24 Mar 10 12:32:56 PM PDT 24 401458655 ps
T289 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.1579587223 Mar 10 12:23:59 PM PDT 24 Mar 10 12:24:00 PM PDT 24 511448607 ps
T68 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.3396961191 Mar 10 12:32:51 PM PDT 24 Mar 10 12:32:52 PM PDT 24 348509946 ps
T290 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.300269682 Mar 10 12:21:24 PM PDT 24 Mar 10 12:21:25 PM PDT 24 542880908 ps
T69 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.3325837782 Mar 10 12:19:24 PM PDT 24 Mar 10 12:19:26 PM PDT 24 501592020 ps
T59 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.124269623 Mar 10 12:23:39 PM PDT 24 Mar 10 12:23:41 PM PDT 24 358360763 ps
T34 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.3988389504 Mar 10 12:19:15 PM PDT 24 Mar 10 12:19:19 PM PDT 24 4706868186 ps
T60 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.392179190 Mar 10 12:21:02 PM PDT 24 Mar 10 12:21:39 PM PDT 24 9971754006 ps
T63 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.3547148183 Mar 10 12:21:07 PM PDT 24 Mar 10 12:21:08 PM PDT 24 557498297 ps
T70 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.2630584510 Mar 10 12:32:49 PM PDT 24 Mar 10 12:32:50 PM PDT 24 2090119929 ps
T71 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.2345789011 Mar 10 12:24:28 PM PDT 24 Mar 10 12:24:29 PM PDT 24 380502072 ps
T291 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.2273859233 Mar 10 12:18:43 PM PDT 24 Mar 10 12:18:44 PM PDT 24 709153135 ps
T292 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.520325981 Mar 10 12:20:11 PM PDT 24 Mar 10 12:20:13 PM PDT 24 454144780 ps
T293 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.3573391001 Mar 10 12:24:06 PM PDT 24 Mar 10 12:24:08 PM PDT 24 530589893 ps
T72 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.183687401 Mar 10 12:19:51 PM PDT 24 Mar 10 12:19:52 PM PDT 24 1270374050 ps
T294 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.3590247109 Mar 10 12:19:10 PM PDT 24 Mar 10 12:19:12 PM PDT 24 420601115 ps
T295 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.20521682 Mar 10 12:21:07 PM PDT 24 Mar 10 12:21:08 PM PDT 24 323683658 ps
T296 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.4264922244 Mar 10 12:27:05 PM PDT 24 Mar 10 12:27:07 PM PDT 24 617603973 ps
T35 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.2943840645 Mar 10 12:23:50 PM PDT 24 Mar 10 12:23:58 PM PDT 24 4087818805 ps
T297 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.2523770583 Mar 10 12:19:25 PM PDT 24 Mar 10 12:19:28 PM PDT 24 457128071 ps
T298 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.2405430260 Mar 10 12:24:38 PM PDT 24 Mar 10 12:24:39 PM PDT 24 463029024 ps
T73 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.839406359 Mar 10 12:27:37 PM PDT 24 Mar 10 12:27:37 PM PDT 24 338899089 ps
T299 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.405483845 Mar 10 12:19:20 PM PDT 24 Mar 10 12:19:21 PM PDT 24 425137096 ps
T36 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.2514412605 Mar 10 12:24:24 PM PDT 24 Mar 10 12:24:36 PM PDT 24 8144044368 ps
T74 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.1393943614 Mar 10 12:19:16 PM PDT 24 Mar 10 12:19:19 PM PDT 24 1428074966 ps
T300 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.3465312193 Mar 10 12:22:44 PM PDT 24 Mar 10 12:22:44 PM PDT 24 505042048 ps
T94 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.4120327661 Mar 10 12:30:24 PM PDT 24 Mar 10 12:30:27 PM PDT 24 4431958187 ps
T301 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.2922919358 Mar 10 12:27:17 PM PDT 24 Mar 10 12:27:20 PM PDT 24 556587279 ps
T302 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.192639813 Mar 10 12:19:40 PM PDT 24 Mar 10 12:19:41 PM PDT 24 451713066 ps
T303 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.2351713832 Mar 10 12:19:21 PM PDT 24 Mar 10 12:19:25 PM PDT 24 376795882 ps
T304 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.2533846066 Mar 10 12:23:25 PM PDT 24 Mar 10 12:23:26 PM PDT 24 505664613 ps
T305 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.551846559 Mar 10 12:23:50 PM PDT 24 Mar 10 12:23:52 PM PDT 24 490844620 ps
T64 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.550214817 Mar 10 12:23:10 PM PDT 24 Mar 10 12:23:16 PM PDT 24 7784337466 ps
T75 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.4224522414 Mar 10 12:18:43 PM PDT 24 Mar 10 12:18:44 PM PDT 24 1312867898 ps
T306 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.3951984642 Mar 10 12:32:22 PM PDT 24 Mar 10 12:32:23 PM PDT 24 423986706 ps
T307 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.3048775669 Mar 10 12:23:00 PM PDT 24 Mar 10 12:23:02 PM PDT 24 456573426 ps
T308 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.2378877396 Mar 10 12:21:29 PM PDT 24 Mar 10 12:21:30 PM PDT 24 543722876 ps
T95 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.1866234764 Mar 10 12:19:18 PM PDT 24 Mar 10 12:19:21 PM PDT 24 4480372780 ps
T309 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.4064772384 Mar 10 12:24:29 PM PDT 24 Mar 10 12:24:31 PM PDT 24 509850700 ps
T310 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.3986451822 Mar 10 12:24:43 PM PDT 24 Mar 10 12:24:47 PM PDT 24 587521261 ps
T311 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.1278525616 Mar 10 12:20:51 PM PDT 24 Mar 10 12:20:53 PM PDT 24 444516074 ps
T99 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.3936837150 Mar 10 12:18:01 PM PDT 24 Mar 10 12:18:07 PM PDT 24 8287594670 ps
T100 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.1056261542 Mar 10 12:19:25 PM PDT 24 Mar 10 12:19:33 PM PDT 24 8358802034 ps
T312 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.2446060185 Mar 10 12:27:20 PM PDT 24 Mar 10 12:27:22 PM PDT 24 505206882 ps
T313 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.4150982151 Mar 10 12:24:28 PM PDT 24 Mar 10 12:24:30 PM PDT 24 1497255962 ps
T314 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.1862960512 Mar 10 12:24:06 PM PDT 24 Mar 10 12:24:08 PM PDT 24 379804022 ps
T315 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.1795859213 Mar 10 12:32:50 PM PDT 24 Mar 10 12:32:51 PM PDT 24 1100150864 ps
T316 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.4212840956 Mar 10 12:22:53 PM PDT 24 Mar 10 12:22:55 PM PDT 24 511189804 ps
T65 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.845140250 Mar 10 12:23:28 PM PDT 24 Mar 10 12:23:43 PM PDT 24 7601161005 ps
T317 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.4100202281 Mar 10 12:19:29 PM PDT 24 Mar 10 12:19:31 PM PDT 24 574728040 ps
T318 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.2256751019 Mar 10 12:22:44 PM PDT 24 Mar 10 12:22:47 PM PDT 24 1286345022 ps
T319 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.3965106356 Mar 10 12:19:29 PM PDT 24 Mar 10 12:19:31 PM PDT 24 392206972 ps
T320 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.1353183004 Mar 10 12:22:53 PM PDT 24 Mar 10 12:22:54 PM PDT 24 580051582 ps
T321 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.1157438513 Mar 10 12:32:22 PM PDT 24 Mar 10 12:32:24 PM PDT 24 375228307 ps
T322 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.314083707 Mar 10 12:32:53 PM PDT 24 Mar 10 12:32:54 PM PDT 24 369982695 ps
T323 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.4114431477 Mar 10 12:24:12 PM PDT 24 Mar 10 12:24:13 PM PDT 24 459974485 ps
T324 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.1219961214 Mar 10 12:33:46 PM PDT 24 Mar 10 12:33:47 PM PDT 24 337766795 ps
T66 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.2565504844 Mar 10 12:24:31 PM PDT 24 Mar 10 12:24:34 PM PDT 24 4086113274 ps
T325 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.1410439123 Mar 10 12:20:49 PM PDT 24 Mar 10 12:20:52 PM PDT 24 431284974 ps
T326 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.1784092800 Mar 10 12:23:21 PM PDT 24 Mar 10 12:23:23 PM PDT 24 365135394 ps
T101 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.3541655894 Mar 10 12:22:44 PM PDT 24 Mar 10 12:22:47 PM PDT 24 4469708118 ps
T327 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.1147195332 Mar 10 12:22:28 PM PDT 24 Mar 10 12:22:30 PM PDT 24 481302096 ps
T328 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.3283473065 Mar 10 12:18:14 PM PDT 24 Mar 10 12:18:17 PM PDT 24 342925204 ps
T329 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.3828236387 Mar 10 12:19:40 PM PDT 24 Mar 10 12:19:42 PM PDT 24 4421335126 ps
T96 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.2339150891 Mar 10 12:27:22 PM PDT 24 Mar 10 12:27:26 PM PDT 24 8484676536 ps
T330 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.3998916622 Mar 10 12:23:09 PM PDT 24 Mar 10 12:23:11 PM PDT 24 277996550 ps
T331 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.486950548 Mar 10 12:20:18 PM PDT 24 Mar 10 12:20:19 PM PDT 24 417042851 ps
T332 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.3873865603 Mar 10 12:20:58 PM PDT 24 Mar 10 12:21:06 PM PDT 24 8782644082 ps
T333 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.4134221970 Mar 10 12:19:23 PM PDT 24 Mar 10 12:19:26 PM PDT 24 317319638 ps
T61 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.2475402438 Mar 10 12:22:34 PM PDT 24 Mar 10 12:22:36 PM PDT 24 475914904 ps
T334 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.2674964890 Mar 10 12:24:28 PM PDT 24 Mar 10 12:24:30 PM PDT 24 410974061 ps
T335 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.2026630294 Mar 10 12:20:26 PM PDT 24 Mar 10 12:20:27 PM PDT 24 436274033 ps
T336 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.3689352933 Mar 10 12:23:23 PM PDT 24 Mar 10 12:23:24 PM PDT 24 406454260 ps
T337 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.964598767 Mar 10 12:20:47 PM PDT 24 Mar 10 12:20:49 PM PDT 24 295918289 ps
T338 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.649064485 Mar 10 12:21:52 PM PDT 24 Mar 10 12:21:53 PM PDT 24 470039516 ps
T339 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.1464639878 Mar 10 12:27:05 PM PDT 24 Mar 10 12:27:06 PM PDT 24 591204985 ps
T340 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.2140996077 Mar 10 12:19:54 PM PDT 24 Mar 10 12:19:56 PM PDT 24 444227624 ps
T341 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.3834797756 Mar 10 12:24:25 PM PDT 24 Mar 10 12:24:32 PM PDT 24 8539181899 ps
T342 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.1101110920 Mar 10 12:29:20 PM PDT 24 Mar 10 12:29:22 PM PDT 24 1070982288 ps
T343 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.1214094785 Mar 10 12:22:53 PM PDT 24 Mar 10 12:22:54 PM PDT 24 1954140670 ps
T344 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.4070000191 Mar 10 12:22:44 PM PDT 24 Mar 10 12:22:55 PM PDT 24 8260178616 ps
T345 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.1228616139 Mar 10 12:19:48 PM PDT 24 Mar 10 12:19:50 PM PDT 24 1389630790 ps
T346 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.1939595755 Mar 10 12:18:34 PM PDT 24 Mar 10 12:18:35 PM PDT 24 415500169 ps
T347 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.2969921311 Mar 10 12:32:54 PM PDT 24 Mar 10 12:32:55 PM PDT 24 298823814 ps
T348 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.1716015885 Mar 10 12:19:54 PM PDT 24 Mar 10 12:19:55 PM PDT 24 468806304 ps
T349 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.16279549 Mar 10 12:23:14 PM PDT 24 Mar 10 12:23:15 PM PDT 24 315616188 ps
T350 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.2835107348 Mar 10 12:22:53 PM PDT 24 Mar 10 12:22:54 PM PDT 24 342166432 ps
T351 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.2933605844 Mar 10 12:20:25 PM PDT 24 Mar 10 12:20:27 PM PDT 24 390291932 ps
T352 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.175240858 Mar 10 12:20:17 PM PDT 24 Mar 10 12:20:18 PM PDT 24 329872889 ps
T353 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.81148813 Mar 10 12:23:29 PM PDT 24 Mar 10 12:23:30 PM PDT 24 468453660 ps
T354 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.1531675599 Mar 10 12:30:16 PM PDT 24 Mar 10 12:30:18 PM PDT 24 502503987 ps
T97 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.1607709876 Mar 10 12:24:43 PM PDT 24 Mar 10 12:24:49 PM PDT 24 8399153093 ps
T355 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.4118973889 Mar 10 12:24:24 PM PDT 24 Mar 10 12:24:27 PM PDT 24 451010497 ps
T356 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.2217589930 Mar 10 12:19:48 PM PDT 24 Mar 10 12:19:49 PM PDT 24 434755944 ps
T357 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.3286457461 Mar 10 12:19:52 PM PDT 24 Mar 10 12:19:53 PM PDT 24 403307321 ps
T358 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.1585803583 Mar 10 12:32:53 PM PDT 24 Mar 10 12:32:54 PM PDT 24 468009722 ps
T359 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.2734725193 Mar 10 12:19:48 PM PDT 24 Mar 10 12:19:49 PM PDT 24 269646620 ps
T360 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.1280735251 Mar 10 12:22:44 PM PDT 24 Mar 10 12:22:47 PM PDT 24 1404259050 ps
T361 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.3467596194 Mar 10 12:24:05 PM PDT 24 Mar 10 12:24:07 PM PDT 24 744344605 ps
T362 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.1647801846 Mar 10 12:19:21 PM PDT 24 Mar 10 12:19:24 PM PDT 24 516133341 ps
T363 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.1662914741 Mar 10 12:33:38 PM PDT 24 Mar 10 12:33:40 PM PDT 24 527249721 ps
T364 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.188503651 Mar 10 12:20:35 PM PDT 24 Mar 10 12:20:36 PM PDT 24 371505258 ps
T365 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.632485687 Mar 10 12:27:39 PM PDT 24 Mar 10 12:27:40 PM PDT 24 439346817 ps
T366 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.892335259 Mar 10 12:24:05 PM PDT 24 Mar 10 12:24:06 PM PDT 24 383357660 ps
T367 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.2979461337 Mar 10 12:24:12 PM PDT 24 Mar 10 12:24:13 PM PDT 24 1625244494 ps
T368 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.2568760080 Mar 10 12:24:31 PM PDT 24 Mar 10 12:24:32 PM PDT 24 498703208 ps
T369 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.533208570 Mar 10 12:23:19 PM PDT 24 Mar 10 12:23:20 PM PDT 24 369542809 ps
T370 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.1760964629 Mar 10 12:23:59 PM PDT 24 Mar 10 12:24:00 PM PDT 24 277568302 ps
T371 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.3150577193 Mar 10 12:27:05 PM PDT 24 Mar 10 12:27:06 PM PDT 24 529859463 ps
T372 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.283682164 Mar 10 12:33:54 PM PDT 24 Mar 10 12:33:58 PM PDT 24 3202015980 ps
T373 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.1651074136 Mar 10 12:18:43 PM PDT 24 Mar 10 12:18:46 PM PDT 24 463912039 ps
T374 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.142646782 Mar 10 12:19:09 PM PDT 24 Mar 10 12:19:12 PM PDT 24 399564202 ps
T375 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.881365530 Mar 10 12:23:10 PM PDT 24 Mar 10 12:23:12 PM PDT 24 414044032 ps
T376 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.3220251406 Mar 10 12:20:47 PM PDT 24 Mar 10 12:20:48 PM PDT 24 731079442 ps
T377 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.2662734155 Mar 10 12:23:59 PM PDT 24 Mar 10 12:24:00 PM PDT 24 409583929 ps
T378 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.1289429385 Mar 10 12:24:00 PM PDT 24 Mar 10 12:24:02 PM PDT 24 1250735241 ps
T379 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.3160172398 Mar 10 12:17:57 PM PDT 24 Mar 10 12:17:59 PM PDT 24 1442081984 ps
T380 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.914112871 Mar 10 12:23:43 PM PDT 24 Mar 10 12:23:47 PM PDT 24 468299032 ps
T381 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.2917986425 Mar 10 12:23:28 PM PDT 24 Mar 10 12:23:30 PM PDT 24 402188754 ps
T382 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.894427480 Mar 10 12:23:59 PM PDT 24 Mar 10 12:24:00 PM PDT 24 527054676 ps
T383 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.3927727739 Mar 10 12:19:48 PM PDT 24 Mar 10 12:19:49 PM PDT 24 494956085 ps
T384 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.2592332557 Mar 10 12:18:32 PM PDT 24 Mar 10 12:18:35 PM PDT 24 2444316581 ps
T385 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.3744300828 Mar 10 12:19:52 PM PDT 24 Mar 10 12:19:53 PM PDT 24 414532022 ps
T386 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.2707715080 Mar 10 12:19:52 PM PDT 24 Mar 10 12:19:53 PM PDT 24 293050424 ps
T387 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.2641738777 Mar 10 12:22:44 PM PDT 24 Mar 10 12:22:45 PM PDT 24 527741021 ps
T388 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.2018063924 Mar 10 12:19:47 PM PDT 24 Mar 10 12:19:48 PM PDT 24 389930350 ps
T389 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.2436946354 Mar 10 12:20:31 PM PDT 24 Mar 10 12:20:43 PM PDT 24 8124506495 ps
T390 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.2524239760 Mar 10 12:23:38 PM PDT 24 Mar 10 12:23:41 PM PDT 24 1520962237 ps
T391 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.3113065138 Mar 10 12:20:22 PM PDT 24 Mar 10 12:20:37 PM PDT 24 7866687999 ps
T62 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.1467105297 Mar 10 12:29:06 PM PDT 24 Mar 10 12:29:12 PM PDT 24 1249855861 ps
T392 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.2565445603 Mar 10 12:19:03 PM PDT 24 Mar 10 12:19:05 PM PDT 24 2452032672 ps
T393 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.3873858172 Mar 10 12:27:37 PM PDT 24 Mar 10 12:27:39 PM PDT 24 390744282 ps
T394 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.993695222 Mar 10 12:20:49 PM PDT 24 Mar 10 12:20:51 PM PDT 24 324293467 ps
T395 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.2863781978 Mar 10 12:24:43 PM PDT 24 Mar 10 12:24:45 PM PDT 24 543168323 ps
T396 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.3259965677 Mar 10 12:18:39 PM PDT 24 Mar 10 12:18:40 PM PDT 24 539274773 ps
T397 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.2418565675 Mar 10 12:24:05 PM PDT 24 Mar 10 12:24:06 PM PDT 24 369041434 ps
T398 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.2384421137 Mar 10 12:32:22 PM PDT 24 Mar 10 12:32:24 PM PDT 24 386851814 ps
T399 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.3819249534 Mar 10 12:23:09 PM PDT 24 Mar 10 12:23:12 PM PDT 24 4523645874 ps
T400 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.974453899 Mar 10 12:22:53 PM PDT 24 Mar 10 12:22:54 PM PDT 24 372889712 ps
T401 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.184217206 Mar 10 12:27:06 PM PDT 24 Mar 10 12:27:07 PM PDT 24 545507775 ps
T402 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.2015990564 Mar 10 12:26:48 PM PDT 24 Mar 10 12:26:50 PM PDT 24 2306311535 ps
T403 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.695275753 Mar 10 12:20:46 PM PDT 24 Mar 10 12:20:51 PM PDT 24 3994867803 ps
T404 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.4189037471 Mar 10 12:24:28 PM PDT 24 Mar 10 12:24:36 PM PDT 24 3008746014 ps
T405 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.1735218249 Mar 10 12:20:39 PM PDT 24 Mar 10 12:20:40 PM PDT 24 471303488 ps
T98 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.1002975243 Mar 10 12:20:57 PM PDT 24 Mar 10 12:21:12 PM PDT 24 8863217473 ps
T406 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.1257794651 Mar 10 12:19:06 PM PDT 24 Mar 10 12:19:08 PM PDT 24 406963576 ps
T407 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.4044238901 Mar 10 12:20:05 PM PDT 24 Mar 10 12:20:06 PM PDT 24 424801725 ps
T408 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.1306471350 Mar 10 12:19:48 PM PDT 24 Mar 10 12:19:49 PM PDT 24 307388341 ps
T409 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.1556934966 Mar 10 12:23:14 PM PDT 24 Mar 10 12:23:17 PM PDT 24 1247104640 ps
T410 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.1961896431 Mar 10 12:30:11 PM PDT 24 Mar 10 12:30:12 PM PDT 24 397036051 ps
T411 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.1677363349 Mar 10 12:32:22 PM PDT 24 Mar 10 12:32:24 PM PDT 24 364414194 ps
T412 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.4130931647 Mar 10 12:19:54 PM PDT 24 Mar 10 12:19:56 PM PDT 24 321610329 ps
T413 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.954368945 Mar 10 12:22:53 PM PDT 24 Mar 10 12:22:55 PM PDT 24 472855034 ps
T414 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.2226609645 Mar 10 12:19:57 PM PDT 24 Mar 10 12:19:58 PM PDT 24 368158448 ps
T415 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.4194070987 Mar 10 12:32:51 PM PDT 24 Mar 10 12:32:54 PM PDT 24 4222373119 ps
T416 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.766496750 Mar 10 12:24:25 PM PDT 24 Mar 10 12:24:26 PM PDT 24 442661103 ps
T417 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.583729719 Mar 10 12:23:20 PM PDT 24 Mar 10 12:23:21 PM PDT 24 285978638 ps
T418 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.1523718805 Mar 10 12:20:48 PM PDT 24 Mar 10 12:20:50 PM PDT 24 482092750 ps
T419 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.4244939587 Mar 10 12:20:36 PM PDT 24 Mar 10 12:20:38 PM PDT 24 626051652 ps
T420 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.632789901 Mar 10 12:18:33 PM PDT 24 Mar 10 12:18:34 PM PDT 24 1277049885 ps
T421 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.2915762568 Mar 10 12:23:19 PM PDT 24 Mar 10 12:23:22 PM PDT 24 472547591 ps
T67 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.2511921596 Mar 10 12:23:50 PM PDT 24 Mar 10 12:23:51 PM PDT 24 373453708 ps
T422 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.3905047227 Mar 10 12:19:23 PM PDT 24 Mar 10 12:19:30 PM PDT 24 1992654538 ps

Test location /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.4056462185
Short name T3
Test name
Test status
Simulation time 40734498328 ps
CPU time 317.83 seconds
Started Mar 10 12:24:13 PM PDT 24
Finished Mar 10 12:29:31 PM PDT 24
Peak memory 198808 kb
Host smart-f2b63757-fb21-44b3-9fc4-981a3a400237
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056462185 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.4056462185
Directory /workspace/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.3538578356
Short name T11
Test name
Test status
Simulation time 13402927169 ps
CPU time 107.76 seconds
Started Mar 10 12:23:46 PM PDT 24
Finished Mar 10 12:25:34 PM PDT 24
Peak memory 198756 kb
Host smart-36f1f9fd-686f-4191-a61c-2ea3d167e2dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538578356 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.3538578356
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.3988389504
Short name T34
Test name
Test status
Simulation time 4706868186 ps
CPU time 3.82 seconds
Started Mar 10 12:19:15 PM PDT 24
Finished Mar 10 12:19:19 PM PDT 24
Peak memory 196876 kb
Host smart-d04345d4-3828-44cb-a84a-b5bd3d113ccf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988389504 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_t
l_intg_err.3988389504
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.3492844322
Short name T40
Test name
Test status
Simulation time 233715538500 ps
CPU time 207.94 seconds
Started Mar 10 12:24:05 PM PDT 24
Finished Mar 10 12:27:33 PM PDT 24
Peak memory 198736 kb
Host smart-fd7e1fad-f2b9-414b-ab8f-f04db2585079
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492844322 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.3492844322
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.4021301258
Short name T15
Test name
Test status
Simulation time 4370845390 ps
CPU time 2.76 seconds
Started Mar 10 12:22:53 PM PDT 24
Finished Mar 10 12:22:56 PM PDT 24
Peak memory 215516 kb
Host smart-ce381161-10f2-4cd4-b267-ac9700727937
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021301258 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.4021301258
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.3231436356
Short name T5
Test name
Test status
Simulation time 39932579630 ps
CPU time 19.6 seconds
Started Mar 10 12:24:05 PM PDT 24
Finished Mar 10 12:24:24 PM PDT 24
Peak memory 192080 kb
Host smart-8487b537-12ed-40da-9061-fb37a59b4c4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231436356 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_
all.3231436356
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.1202852981
Short name T1
Test name
Test status
Simulation time 78499049745 ps
CPU time 610.84 seconds
Started Mar 10 12:23:09 PM PDT 24
Finished Mar 10 12:33:20 PM PDT 24
Peak memory 199224 kb
Host smart-2f66a950-aa06-4f0e-a1e0-268422737146
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202852981 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.1202852981
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.1607709876
Short name T97
Test name
Test status
Simulation time 8399153093 ps
CPU time 4.72 seconds
Started Mar 10 12:24:43 PM PDT 24
Finished Mar 10 12:24:49 PM PDT 24
Peak memory 197044 kb
Host smart-1d5b759e-8a24-48b4-b33f-40a06fb0bb41
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607709876 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_t
l_intg_err.1607709876
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.124269623
Short name T59
Test name
Test status
Simulation time 358360763 ps
CPU time 1.16 seconds
Started Mar 10 12:23:39 PM PDT 24
Finished Mar 10 12:23:41 PM PDT 24
Peak memory 182916 kb
Host smart-24e6791d-8bf4-4cd2-b9c2-9c134e83ab27
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124269623 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.124269623
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.3004517379
Short name T172
Test name
Test status
Simulation time 45452356760 ps
CPU time 471.31 seconds
Started Mar 10 12:23:44 PM PDT 24
Finished Mar 10 12:31:36 PM PDT 24
Peak memory 198788 kb
Host smart-9dd2c41e-07b1-4737-9418-9947abc56e19
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004517379 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.3004517379
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.520325981
Short name T292
Test name
Test status
Simulation time 454144780 ps
CPU time 1.35 seconds
Started Mar 10 12:20:11 PM PDT 24
Finished Mar 10 12:20:13 PM PDT 24
Peak memory 193496 kb
Host smart-725f2f02-8e0f-4f7a-9946-64aeb915b873
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520325981 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.520325981
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.1124143919
Short name T84
Test name
Test status
Simulation time 192667350404 ps
CPU time 177.94 seconds
Started Mar 10 12:23:44 PM PDT 24
Finished Mar 10 12:26:43 PM PDT 24
Peak memory 198812 kb
Host smart-b2c91d08-7d71-4ad5-86b5-38ed72f04193
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124143919 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.1124143919
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.2405430260
Short name T298
Test name
Test status
Simulation time 463029024 ps
CPU time 0.84 seconds
Started Mar 10 12:24:38 PM PDT 24
Finished Mar 10 12:24:39 PM PDT 24
Peak memory 182924 kb
Host smart-f90719b5-e8e5-4209-aa1a-d6a82bdeb48a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405430260 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_a
liasing.2405430260
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.845140250
Short name T65
Test name
Test status
Simulation time 7601161005 ps
CPU time 14.02 seconds
Started Mar 10 12:23:28 PM PDT 24
Finished Mar 10 12:23:43 PM PDT 24
Peak memory 191484 kb
Host smart-e0e52669-357a-4768-ae84-9890aabda583
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845140250 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_bi
t_bash.845140250
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.2273859233
Short name T291
Test name
Test status
Simulation time 709153135 ps
CPU time 0.88 seconds
Started Mar 10 12:18:43 PM PDT 24
Finished Mar 10 12:18:44 PM PDT 24
Peak memory 183024 kb
Host smart-b02d008f-90b9-4b22-8a25-e1eeb60e3628
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273859233 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_h
w_reset.2273859233
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.2511921596
Short name T67
Test name
Test status
Simulation time 373453708 ps
CPU time 0.7 seconds
Started Mar 10 12:23:50 PM PDT 24
Finished Mar 10 12:23:51 PM PDT 24
Peak memory 182252 kb
Host smart-3e68b5e1-f33c-4ec9-9753-fee22e8303ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511921596 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.2511921596
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.81148813
Short name T353
Test name
Test status
Simulation time 468453660 ps
CPU time 1.22 seconds
Started Mar 10 12:23:29 PM PDT 24
Finished Mar 10 12:23:30 PM PDT 24
Peak memory 182780 kb
Host smart-1eb996b2-f95c-4877-b52f-938164f19f61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81148813 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.81148813
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.2026630294
Short name T335
Test name
Test status
Simulation time 436274033 ps
CPU time 0.54 seconds
Started Mar 10 12:20:26 PM PDT 24
Finished Mar 10 12:20:27 PM PDT 24
Peak memory 181956 kb
Host smart-735e909e-4769-43ae-b069-4fc178e45711
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026630294 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_t
imer_mem_partial_access.2026630294
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.2917986425
Short name T381
Test name
Test status
Simulation time 402188754 ps
CPU time 1.16 seconds
Started Mar 10 12:23:28 PM PDT 24
Finished Mar 10 12:23:30 PM PDT 24
Peak memory 182056 kb
Host smart-97b8753d-cefa-4744-b2d8-534b836d5191
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917986425 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_w
alk.2917986425
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.4224522414
Short name T75
Test name
Test status
Simulation time 1312867898 ps
CPU time 0.97 seconds
Started Mar 10 12:18:43 PM PDT 24
Finished Mar 10 12:18:44 PM PDT 24
Peak memory 183468 kb
Host smart-13163185-f1db-4686-9ed5-1997c5ce3535
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224522414 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon
_timer_same_csr_outstanding.4224522414
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.3283473065
Short name T328
Test name
Test status
Simulation time 342925204 ps
CPU time 1.75 seconds
Started Mar 10 12:18:14 PM PDT 24
Finished Mar 10 12:18:17 PM PDT 24
Peak memory 196848 kb
Host smart-0fea5bba-f597-4af6-8aeb-5a6915e59696
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283473065 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.3283473065
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.3819249534
Short name T399
Test name
Test status
Simulation time 4523645874 ps
CPU time 2.48 seconds
Started Mar 10 12:23:09 PM PDT 24
Finished Mar 10 12:23:12 PM PDT 24
Peak memory 195844 kb
Host smart-5b0c9a15-22f5-4cd7-a959-34207b0b4270
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819249534 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl
_intg_err.3819249534
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.3547148183
Short name T63
Test name
Test status
Simulation time 557498297 ps
CPU time 1.03 seconds
Started Mar 10 12:21:07 PM PDT 24
Finished Mar 10 12:21:08 PM PDT 24
Peak memory 183272 kb
Host smart-e8658d9d-b623-44a7-82ff-ca7270ce9bda
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547148183 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_a
liasing.3547148183
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.392179190
Short name T60
Test name
Test status
Simulation time 9971754006 ps
CPU time 37.62 seconds
Started Mar 10 12:21:02 PM PDT 24
Finished Mar 10 12:21:39 PM PDT 24
Peak memory 191920 kb
Host smart-e6c3ebc4-38f0-4046-8ce5-118eb67d05ad
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392179190 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_bi
t_bash.392179190
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.1795859213
Short name T315
Test name
Test status
Simulation time 1100150864 ps
CPU time 0.96 seconds
Started Mar 10 12:32:50 PM PDT 24
Finished Mar 10 12:32:51 PM PDT 24
Peak memory 183124 kb
Host smart-9a181b52-3bcd-4ef1-a8e1-3ef11f89a528
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795859213 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_h
w_reset.1795859213
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.533208570
Short name T369
Test name
Test status
Simulation time 369542809 ps
CPU time 0.85 seconds
Started Mar 10 12:23:19 PM PDT 24
Finished Mar 10 12:23:20 PM PDT 24
Peak memory 194612 kb
Host smart-42de78dd-23a4-4681-8853-cf88b0d17d03
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533208570 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.533208570
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.649064485
Short name T338
Test name
Test status
Simulation time 470039516 ps
CPU time 0.6 seconds
Started Mar 10 12:21:52 PM PDT 24
Finished Mar 10 12:21:53 PM PDT 24
Peak memory 183144 kb
Host smart-896beedf-29c2-4ba1-ae9a-c688f39a2ff7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649064485 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.649064485
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.2933605844
Short name T351
Test name
Test status
Simulation time 390291932 ps
CPU time 1.09 seconds
Started Mar 10 12:20:25 PM PDT 24
Finished Mar 10 12:20:27 PM PDT 24
Peak memory 182720 kb
Host smart-fc7763ca-abed-44cc-a997-cae3a6bf170a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933605844 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.2933605844
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.4064772384
Short name T309
Test name
Test status
Simulation time 509850700 ps
CPU time 1.19 seconds
Started Mar 10 12:24:29 PM PDT 24
Finished Mar 10 12:24:31 PM PDT 24
Peak memory 182068 kb
Host smart-f78d05ea-57a7-4784-a4c7-4ee44a43dcd2
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064772384 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_t
imer_mem_partial_access.4064772384
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.2568760080
Short name T368
Test name
Test status
Simulation time 498703208 ps
CPU time 1.24 seconds
Started Mar 10 12:24:31 PM PDT 24
Finished Mar 10 12:24:32 PM PDT 24
Peak memory 182044 kb
Host smart-26f01d91-1336-4f91-8474-839ff7e3f00f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568760080 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_w
alk.2568760080
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.2145756458
Short name T37
Test name
Test status
Simulation time 1083935070 ps
CPU time 2.13 seconds
Started Mar 10 12:19:54 PM PDT 24
Finished Mar 10 12:19:57 PM PDT 24
Peak memory 183024 kb
Host smart-451e42d2-993e-43ea-aa0a-f3ea36054474
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145756458 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon
_timer_same_csr_outstanding.2145756458
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.1157438513
Short name T321
Test name
Test status
Simulation time 375228307 ps
CPU time 1.97 seconds
Started Mar 10 12:32:22 PM PDT 24
Finished Mar 10 12:32:24 PM PDT 24
Peak memory 197812 kb
Host smart-2729e4dc-6bb1-4644-9985-404245339f76
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157438513 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.1157438513
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.3873865603
Short name T332
Test name
Test status
Simulation time 8782644082 ps
CPU time 8.56 seconds
Started Mar 10 12:20:58 PM PDT 24
Finished Mar 10 12:21:06 PM PDT 24
Peak memory 197148 kb
Host smart-b57f6a74-12ed-4e8c-beda-4d091cd6b28f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873865603 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl
_intg_err.3873865603
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.1579587223
Short name T289
Test name
Test status
Simulation time 511448607 ps
CPU time 0.65 seconds
Started Mar 10 12:23:59 PM PDT 24
Finished Mar 10 12:24:00 PM PDT 24
Peak memory 194712 kb
Host smart-ff9d7437-d40c-4364-bde5-0c07ce8c03a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579587223 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.1579587223
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.4114431477
Short name T323
Test name
Test status
Simulation time 459974485 ps
CPU time 0.75 seconds
Started Mar 10 12:24:12 PM PDT 24
Finished Mar 10 12:24:13 PM PDT 24
Peak memory 182012 kb
Host smart-910622cc-b2f4-4407-84cc-116f6dc094f2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114431477 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.4114431477
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.632485687
Short name T365
Test name
Test status
Simulation time 439346817 ps
CPU time 0.66 seconds
Started Mar 10 12:27:39 PM PDT 24
Finished Mar 10 12:27:40 PM PDT 24
Peak memory 182772 kb
Host smart-955cc84b-245e-42c5-bc4f-b937e728eb38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632485687 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.632485687
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.1289429385
Short name T378
Test name
Test status
Simulation time 1250735241 ps
CPU time 1.3 seconds
Started Mar 10 12:24:00 PM PDT 24
Finished Mar 10 12:24:02 PM PDT 24
Peak memory 192496 kb
Host smart-05e9e08f-a6c8-411c-8eda-0b8532eb7ca2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289429385 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.ao
n_timer_same_csr_outstanding.1289429385
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.1278525616
Short name T311
Test name
Test status
Simulation time 444516074 ps
CPU time 1.69 seconds
Started Mar 10 12:20:51 PM PDT 24
Finished Mar 10 12:20:53 PM PDT 24
Peak memory 197400 kb
Host smart-306e0da9-62ec-4786-8f2e-48ec26c23197
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278525616 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.1278525616
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.2436946354
Short name T389
Test name
Test status
Simulation time 8124506495 ps
CPU time 12.22 seconds
Started Mar 10 12:20:31 PM PDT 24
Finished Mar 10 12:20:43 PM PDT 24
Peak memory 196952 kb
Host smart-fe00feeb-7520-458d-a4d7-21ec9db98895
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436946354 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_t
l_intg_err.2436946354
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.3590247109
Short name T294
Test name
Test status
Simulation time 420601115 ps
CPU time 1.28 seconds
Started Mar 10 12:19:10 PM PDT 24
Finished Mar 10 12:19:12 PM PDT 24
Peak memory 195024 kb
Host smart-dac180b0-b976-47da-90bc-eff19fc54a59
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590247109 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.3590247109
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.2378877396
Short name T308
Test name
Test status
Simulation time 543722876 ps
CPU time 0.68 seconds
Started Mar 10 12:21:29 PM PDT 24
Finished Mar 10 12:21:30 PM PDT 24
Peak memory 183116 kb
Host smart-552d26c3-66bb-4189-815f-23adf39736a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378877396 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.2378877396
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.1760964629
Short name T370
Test name
Test status
Simulation time 277568302 ps
CPU time 0.92 seconds
Started Mar 10 12:23:59 PM PDT 24
Finished Mar 10 12:24:00 PM PDT 24
Peak memory 182372 kb
Host smart-5d8099cc-45fb-4293-b64c-1634321cdd96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760964629 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.1760964629
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.2524239760
Short name T390
Test name
Test status
Simulation time 1520962237 ps
CPU time 2.44 seconds
Started Mar 10 12:23:38 PM PDT 24
Finished Mar 10 12:23:41 PM PDT 24
Peak memory 192408 kb
Host smart-2c6a6167-3c25-4baa-bfa9-82d49272b1ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524239760 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.ao
n_timer_same_csr_outstanding.2524239760
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.2351713832
Short name T303
Test name
Test status
Simulation time 376795882 ps
CPU time 2.8 seconds
Started Mar 10 12:19:21 PM PDT 24
Finished Mar 10 12:19:25 PM PDT 24
Peak memory 197808 kb
Host smart-2f1212a2-5ecb-4ab1-a7a8-fe6d4f5fb35a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351713832 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.2351713832
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.3113065138
Short name T391
Test name
Test status
Simulation time 7866687999 ps
CPU time 14 seconds
Started Mar 10 12:20:22 PM PDT 24
Finished Mar 10 12:20:37 PM PDT 24
Peak memory 197316 kb
Host smart-003da832-ea55-4963-be3a-e7c73678038a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113065138 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_t
l_intg_err.3113065138
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.679759046
Short name T32
Test name
Test status
Simulation time 816451360 ps
CPU time 0.82 seconds
Started Mar 10 12:22:44 PM PDT 24
Finished Mar 10 12:22:45 PM PDT 24
Peak memory 196560 kb
Host smart-3d72c705-2990-4eee-99a1-cb60dba3ce97
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679759046 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.679759046
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.20521682
Short name T295
Test name
Test status
Simulation time 323683658 ps
CPU time 1.02 seconds
Started Mar 10 12:21:07 PM PDT 24
Finished Mar 10 12:21:08 PM PDT 24
Peak memory 183116 kb
Host smart-c4ed8be7-f4b3-4bd4-906f-3b7016038cf9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20521682 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.20521682
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.2979461337
Short name T367
Test name
Test status
Simulation time 1625244494 ps
CPU time 1.18 seconds
Started Mar 10 12:24:12 PM PDT 24
Finished Mar 10 12:24:13 PM PDT 24
Peak memory 191424 kb
Host smart-9cd20da8-e3e5-420a-93e0-014b808009c6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979461337 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.ao
n_timer_same_csr_outstanding.2979461337
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.4190388494
Short name T286
Test name
Test status
Simulation time 648541663 ps
CPU time 1.31 seconds
Started Mar 10 12:24:10 PM PDT 24
Finished Mar 10 12:24:11 PM PDT 24
Peak memory 197740 kb
Host smart-1f519635-0e42-47c5-b691-9d92e0236d85
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190388494 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.4190388494
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.1002975243
Short name T98
Test name
Test status
Simulation time 8863217473 ps
CPU time 14.51 seconds
Started Mar 10 12:20:57 PM PDT 24
Finished Mar 10 12:21:12 PM PDT 24
Peak memory 197120 kb
Host smart-bfeafbda-66a1-48e2-8fb9-95927ca6ae03
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002975243 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_t
l_intg_err.1002975243
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.3689352933
Short name T336
Test name
Test status
Simulation time 406454260 ps
CPU time 0.96 seconds
Started Mar 10 12:23:23 PM PDT 24
Finished Mar 10 12:23:24 PM PDT 24
Peak memory 194760 kb
Host smart-adea1be0-55ae-443d-a890-59191915bc5f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689352933 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.3689352933
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.2641738777
Short name T387
Test name
Test status
Simulation time 527741021 ps
CPU time 1.23 seconds
Started Mar 10 12:22:44 PM PDT 24
Finished Mar 10 12:22:45 PM PDT 24
Peak memory 183080 kb
Host smart-c7655771-0af8-41eb-9d0e-0e3a7f8aa12f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641738777 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.2641738777
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.1147195332
Short name T327
Test name
Test status
Simulation time 481302096 ps
CPU time 1.41 seconds
Started Mar 10 12:22:28 PM PDT 24
Finished Mar 10 12:22:30 PM PDT 24
Peak memory 182000 kb
Host smart-ce6628ab-c01d-4f67-945d-d843a06a261d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147195332 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.1147195332
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.4150982151
Short name T313
Test name
Test status
Simulation time 1497255962 ps
CPU time 1.32 seconds
Started Mar 10 12:24:28 PM PDT 24
Finished Mar 10 12:24:30 PM PDT 24
Peak memory 192396 kb
Host smart-df6c6152-529e-49ce-bfb8-621961ea743c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150982151 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.ao
n_timer_same_csr_outstanding.4150982151
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.2256751019
Short name T318
Test name
Test status
Simulation time 1286345022 ps
CPU time 2.19 seconds
Started Mar 10 12:22:44 PM PDT 24
Finished Mar 10 12:22:47 PM PDT 24
Peak memory 197784 kb
Host smart-7bc5c1fb-0d25-4d73-8568-0d72a372a049
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256751019 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.2256751019
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.4244939587
Short name T419
Test name
Test status
Simulation time 626051652 ps
CPU time 1.15 seconds
Started Mar 10 12:20:36 PM PDT 24
Finished Mar 10 12:20:38 PM PDT 24
Peak memory 197676 kb
Host smart-02fe55bb-01d0-47ac-b3ca-794bda47fce2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244939587 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.4244939587
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.2345789011
Short name T71
Test name
Test status
Simulation time 380502072 ps
CPU time 0.63 seconds
Started Mar 10 12:24:28 PM PDT 24
Finished Mar 10 12:24:29 PM PDT 24
Peak memory 183004 kb
Host smart-8ca61956-fc08-4f61-a4fa-f0bd3295e729
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345789011 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.2345789011
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.405483845
Short name T299
Test name
Test status
Simulation time 425137096 ps
CPU time 0.67 seconds
Started Mar 10 12:19:20 PM PDT 24
Finished Mar 10 12:19:21 PM PDT 24
Peak memory 182864 kb
Host smart-4dfead65-6040-4163-b6c3-cfe47d9a3d6f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405483845 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.405483845
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.1280735251
Short name T360
Test name
Test status
Simulation time 1404259050 ps
CPU time 2.39 seconds
Started Mar 10 12:22:44 PM PDT 24
Finished Mar 10 12:22:47 PM PDT 24
Peak memory 192804 kb
Host smart-ab84c30b-225e-4ba1-8dfe-73d156563c97
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280735251 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao
n_timer_same_csr_outstanding.1280735251
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.2674964890
Short name T334
Test name
Test status
Simulation time 410974061 ps
CPU time 2.35 seconds
Started Mar 10 12:24:28 PM PDT 24
Finished Mar 10 12:24:30 PM PDT 24
Peak memory 197792 kb
Host smart-9bdd390b-aec1-4425-b4c7-da682231a464
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674964890 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.2674964890
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.3541655894
Short name T101
Test name
Test status
Simulation time 4469708118 ps
CPU time 2.56 seconds
Started Mar 10 12:22:44 PM PDT 24
Finished Mar 10 12:22:47 PM PDT 24
Peak memory 196592 kb
Host smart-a41ea8fc-eebb-4615-b0b8-a763c309bfe9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541655894 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_t
l_intg_err.3541655894
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.3220251406
Short name T376
Test name
Test status
Simulation time 731079442 ps
CPU time 0.95 seconds
Started Mar 10 12:20:47 PM PDT 24
Finished Mar 10 12:20:48 PM PDT 24
Peak memory 196468 kb
Host smart-102eff74-e265-4b69-bef7-e896c54cdbf2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220251406 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.3220251406
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.1862960512
Short name T314
Test name
Test status
Simulation time 379804022 ps
CPU time 1.12 seconds
Started Mar 10 12:24:06 PM PDT 24
Finished Mar 10 12:24:08 PM PDT 24
Peak memory 182024 kb
Host smart-55af1f7a-18da-4b6f-93a7-4002ca46eedb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862960512 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.1862960512
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.3465312193
Short name T300
Test name
Test status
Simulation time 505042048 ps
CPU time 0.65 seconds
Started Mar 10 12:22:44 PM PDT 24
Finished Mar 10 12:22:44 PM PDT 24
Peak memory 182840 kb
Host smart-bd4589e9-9a6c-44fd-b9ce-33a8d5692bd4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465312193 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.3465312193
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.183687401
Short name T72
Test name
Test status
Simulation time 1270374050 ps
CPU time 0.79 seconds
Started Mar 10 12:19:51 PM PDT 24
Finished Mar 10 12:19:52 PM PDT 24
Peak memory 183032 kb
Host smart-31e0ba81-c6b4-40c7-be28-f51a3d18ec67
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183687401 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon
_timer_same_csr_outstanding.183687401
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.2523770583
Short name T297
Test name
Test status
Simulation time 457128071 ps
CPU time 1.96 seconds
Started Mar 10 12:19:25 PM PDT 24
Finished Mar 10 12:19:28 PM PDT 24
Peak memory 197844 kb
Host smart-7985ff1f-6c0c-4d80-a5e7-8561c838878a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523770583 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.2523770583
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.4070000191
Short name T344
Test name
Test status
Simulation time 8260178616 ps
CPU time 10.28 seconds
Started Mar 10 12:22:44 PM PDT 24
Finished Mar 10 12:22:55 PM PDT 24
Peak memory 196988 kb
Host smart-966c4be3-ca63-450f-b760-009b689c5627
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070000191 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_t
l_intg_err.4070000191
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.3573391001
Short name T293
Test name
Test status
Simulation time 530589893 ps
CPU time 1.36 seconds
Started Mar 10 12:24:06 PM PDT 24
Finished Mar 10 12:24:08 PM PDT 24
Peak memory 193804 kb
Host smart-9b1b8c28-ad48-47da-b4e2-22f5301c49cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573391001 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.3573391001
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.1735218249
Short name T405
Test name
Test status
Simulation time 471303488 ps
CPU time 0.72 seconds
Started Mar 10 12:20:39 PM PDT 24
Finished Mar 10 12:20:40 PM PDT 24
Peak memory 191672 kb
Host smart-efb87ad3-e50e-4948-b7b0-b04905e73f85
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735218249 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.1735218249
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.1647801846
Short name T362
Test name
Test status
Simulation time 516133341 ps
CPU time 0.85 seconds
Started Mar 10 12:19:21 PM PDT 24
Finished Mar 10 12:19:24 PM PDT 24
Peak memory 182812 kb
Host smart-9a3e0a18-ee64-40b8-89a2-1f2a09ee0a1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647801846 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.1647801846
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.2630584510
Short name T70
Test name
Test status
Simulation time 2090119929 ps
CPU time 1.06 seconds
Started Mar 10 12:32:49 PM PDT 24
Finished Mar 10 12:32:50 PM PDT 24
Peak memory 193676 kb
Host smart-5a523d0c-1bdc-4d8f-96bf-6725feac4007
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630584510 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.ao
n_timer_same_csr_outstanding.2630584510
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.4118973889
Short name T355
Test name
Test status
Simulation time 451010497 ps
CPU time 2.37 seconds
Started Mar 10 12:24:24 PM PDT 24
Finished Mar 10 12:24:27 PM PDT 24
Peak memory 197584 kb
Host smart-f41d72ef-b82a-43f3-9207-3473051c5fcf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118973889 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.4118973889
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.2514412605
Short name T36
Test name
Test status
Simulation time 8144044368 ps
CPU time 11.33 seconds
Started Mar 10 12:24:24 PM PDT 24
Finished Mar 10 12:24:36 PM PDT 24
Peak memory 196956 kb
Host smart-cc3ce104-7652-4923-ae28-fbd31e18da56
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514412605 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_t
l_intg_err.2514412605
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.894427480
Short name T382
Test name
Test status
Simulation time 527054676 ps
CPU time 1.4 seconds
Started Mar 10 12:23:59 PM PDT 24
Finished Mar 10 12:24:00 PM PDT 24
Peak memory 192488 kb
Host smart-2c45b362-3c4a-4f5e-ac7e-99e1964d1a6c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894427480 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.894427480
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.3325837782
Short name T69
Test name
Test status
Simulation time 501592020 ps
CPU time 1.38 seconds
Started Mar 10 12:19:24 PM PDT 24
Finished Mar 10 12:19:26 PM PDT 24
Peak memory 183112 kb
Host smart-d87d7a8b-c769-49d6-92d4-008e65fe5f80
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325837782 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.3325837782
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.2662734155
Short name T377
Test name
Test status
Simulation time 409583929 ps
CPU time 0.72 seconds
Started Mar 10 12:23:59 PM PDT 24
Finished Mar 10 12:24:00 PM PDT 24
Peak memory 181080 kb
Host smart-e979182b-d3ec-47ed-bf1b-546cf7c3ce37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662734155 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.2662734155
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.1393943614
Short name T74
Test name
Test status
Simulation time 1428074966 ps
CPU time 2.65 seconds
Started Mar 10 12:19:16 PM PDT 24
Finished Mar 10 12:19:19 PM PDT 24
Peak memory 192912 kb
Host smart-49ac453f-b07b-429e-b454-2f528c738626
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393943614 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.ao
n_timer_same_csr_outstanding.1393943614
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.2855211713
Short name T285
Test name
Test status
Simulation time 1336802408 ps
CPU time 2.29 seconds
Started Mar 10 12:20:41 PM PDT 24
Finished Mar 10 12:20:43 PM PDT 24
Peak memory 197824 kb
Host smart-45f3d2d3-fb0d-4a7d-833f-74418ce5363f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855211713 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.2855211713
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.1056261542
Short name T100
Test name
Test status
Simulation time 8358802034 ps
CPU time 7.09 seconds
Started Mar 10 12:19:25 PM PDT 24
Finished Mar 10 12:19:33 PM PDT 24
Peak memory 197824 kb
Host smart-3d3076eb-8f2e-4856-b5dd-becb432d349c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056261542 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_t
l_intg_err.1056261542
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.2863781978
Short name T395
Test name
Test status
Simulation time 543168323 ps
CPU time 1.26 seconds
Started Mar 10 12:24:43 PM PDT 24
Finished Mar 10 12:24:45 PM PDT 24
Peak memory 194504 kb
Host smart-749e5e1a-e556-4ddc-92e8-cb4eab206d51
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863781978 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.2863781978
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.3965106356
Short name T319
Test name
Test status
Simulation time 392206972 ps
CPU time 0.72 seconds
Started Mar 10 12:19:29 PM PDT 24
Finished Mar 10 12:19:31 PM PDT 24
Peak memory 183524 kb
Host smart-44129093-fcf9-4d0d-b672-81669a58961e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965106356 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.3965106356
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.2226609645
Short name T414
Test name
Test status
Simulation time 368158448 ps
CPU time 0.82 seconds
Started Mar 10 12:19:57 PM PDT 24
Finished Mar 10 12:19:58 PM PDT 24
Peak memory 183264 kb
Host smart-0a5bb07f-2ecc-452f-a0bd-fba3b68590e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226609645 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.2226609645
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.3905047227
Short name T422
Test name
Test status
Simulation time 1992654538 ps
CPU time 5.57 seconds
Started Mar 10 12:19:23 PM PDT 24
Finished Mar 10 12:19:30 PM PDT 24
Peak memory 193684 kb
Host smart-fa43e4f0-c4b7-4ae0-80cb-dca4bf3bd7c0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905047227 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.ao
n_timer_same_csr_outstanding.3905047227
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.3986451822
Short name T310
Test name
Test status
Simulation time 587521261 ps
CPU time 1.83 seconds
Started Mar 10 12:24:43 PM PDT 24
Finished Mar 10 12:24:47 PM PDT 24
Peak memory 197716 kb
Host smart-725d7275-c820-4900-99a9-138a7824f390
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986451822 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.3986451822
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.2922919358
Short name T301
Test name
Test status
Simulation time 556587279 ps
CPU time 1.42 seconds
Started Mar 10 12:27:17 PM PDT 24
Finished Mar 10 12:27:20 PM PDT 24
Peak memory 193676 kb
Host smart-0a3cd6a3-27ce-4d16-9f08-5e90404746f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922919358 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.2922919358
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.839406359
Short name T73
Test name
Test status
Simulation time 338899089 ps
CPU time 0.67 seconds
Started Mar 10 12:27:37 PM PDT 24
Finished Mar 10 12:27:37 PM PDT 24
Peak memory 182948 kb
Host smart-fb7ac810-fe0e-48ce-84bf-34ef5125f5dc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839406359 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.839406359
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.4100202281
Short name T317
Test name
Test status
Simulation time 574728040 ps
CPU time 0.63 seconds
Started Mar 10 12:19:29 PM PDT 24
Finished Mar 10 12:19:31 PM PDT 24
Peak memory 183320 kb
Host smart-9f84488b-f6cc-40a9-813f-b68174d17d80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100202281 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.4100202281
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.1228616139
Short name T345
Test name
Test status
Simulation time 1389630790 ps
CPU time 2.32 seconds
Started Mar 10 12:19:48 PM PDT 24
Finished Mar 10 12:19:50 PM PDT 24
Peak memory 183084 kb
Host smart-3b45fa71-09c2-4ba7-aedf-01f7f979bac0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228616139 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao
n_timer_same_csr_outstanding.1228616139
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.1410439123
Short name T325
Test name
Test status
Simulation time 431284974 ps
CPU time 2.29 seconds
Started Mar 10 12:20:49 PM PDT 24
Finished Mar 10 12:20:52 PM PDT 24
Peak memory 197776 kb
Host smart-c498f191-3f93-4555-9b40-270bcc09b2db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410439123 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.1410439123
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.3828236387
Short name T329
Test name
Test status
Simulation time 4421335126 ps
CPU time 1.73 seconds
Started Mar 10 12:19:40 PM PDT 24
Finished Mar 10 12:19:42 PM PDT 24
Peak memory 195884 kb
Host smart-31babf3f-aba8-4732-a851-ddb364e0b0dd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828236387 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_t
l_intg_err.3828236387
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.1353183004
Short name T320
Test name
Test status
Simulation time 580051582 ps
CPU time 0.83 seconds
Started Mar 10 12:22:53 PM PDT 24
Finished Mar 10 12:22:54 PM PDT 24
Peak memory 182824 kb
Host smart-b7940037-6df6-4b5d-b457-b16c7de88e81
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353183004 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_a
liasing.1353183004
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.2565504844
Short name T66
Test name
Test status
Simulation time 4086113274 ps
CPU time 2.72 seconds
Started Mar 10 12:24:31 PM PDT 24
Finished Mar 10 12:24:34 PM PDT 24
Peak memory 191428 kb
Host smart-fcf9e6b4-e413-4515-96cd-de6d4d3cc0e8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565504844 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_b
it_bash.2565504844
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.3467596194
Short name T361
Test name
Test status
Simulation time 744344605 ps
CPU time 1.69 seconds
Started Mar 10 12:24:05 PM PDT 24
Finished Mar 10 12:24:07 PM PDT 24
Peak memory 182832 kb
Host smart-5127e88f-da38-4344-8d97-bf38da0f5e90
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467596194 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_h
w_reset.3467596194
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.2915762568
Short name T421
Test name
Test status
Simulation time 472547591 ps
CPU time 1.5 seconds
Started Mar 10 12:23:19 PM PDT 24
Finished Mar 10 12:23:22 PM PDT 24
Peak memory 194640 kb
Host smart-c768cfa1-40e5-447c-95cc-b44075ef871e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915762568 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.2915762568
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.4134221970
Short name T333
Test name
Test status
Simulation time 317319638 ps
CPU time 1.13 seconds
Started Mar 10 12:19:23 PM PDT 24
Finished Mar 10 12:19:26 PM PDT 24
Peak memory 183028 kb
Host smart-f5403bfd-b275-4b5a-8066-03a8d5611340
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134221970 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.4134221970
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.2418565675
Short name T397
Test name
Test status
Simulation time 369041434 ps
CPU time 1.05 seconds
Started Mar 10 12:24:05 PM PDT 24
Finished Mar 10 12:24:06 PM PDT 24
Peak memory 182696 kb
Host smart-8db260ce-5da2-4048-b3d7-4e5c580540dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418565675 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.2418565675
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.583729719
Short name T417
Test name
Test status
Simulation time 285978638 ps
CPU time 0.98 seconds
Started Mar 10 12:23:20 PM PDT 24
Finished Mar 10 12:23:21 PM PDT 24
Peak memory 182788 kb
Host smart-4010c771-f434-4c42-9768-a4a0cb4abf75
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583729719 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_ti
mer_mem_partial_access.583729719
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.1001272822
Short name T282
Test name
Test status
Simulation time 278130707 ps
CPU time 0.81 seconds
Started Mar 10 12:23:05 PM PDT 24
Finished Mar 10 12:23:06 PM PDT 24
Peak memory 181888 kb
Host smart-37f03ffc-d296-4baa-8995-700c3f862dd2
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001272822 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_w
alk.1001272822
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.3160172398
Short name T379
Test name
Test status
Simulation time 1442081984 ps
CPU time 1.13 seconds
Started Mar 10 12:17:57 PM PDT 24
Finished Mar 10 12:17:59 PM PDT 24
Peak memory 182136 kb
Host smart-77b40e91-dcb8-4f96-a54d-564ab074f3d5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160172398 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon
_timer_same_csr_outstanding.3160172398
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.1784092800
Short name T326
Test name
Test status
Simulation time 365135394 ps
CPU time 2.17 seconds
Started Mar 10 12:23:21 PM PDT 24
Finished Mar 10 12:23:23 PM PDT 24
Peak memory 197688 kb
Host smart-d0b89ab2-ee21-491f-ad4f-7f71f2f1dac8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784092800 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.1784092800
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.2943840645
Short name T35
Test name
Test status
Simulation time 4087818805 ps
CPU time 7.2 seconds
Started Mar 10 12:23:50 PM PDT 24
Finished Mar 10 12:23:58 PM PDT 24
Peak memory 195596 kb
Host smart-d72a527d-9f47-46f9-9199-7513831fcd49
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943840645 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl
_intg_err.2943840645
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.3998916622
Short name T330
Test name
Test status
Simulation time 277996550 ps
CPU time 0.93 seconds
Started Mar 10 12:23:09 PM PDT 24
Finished Mar 10 12:23:11 PM PDT 24
Peak memory 182312 kb
Host smart-7664c3b5-b80a-4c29-9006-efe5e55a9894
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998916622 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.3998916622
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.2217589930
Short name T356
Test name
Test status
Simulation time 434755944 ps
CPU time 1.11 seconds
Started Mar 10 12:19:48 PM PDT 24
Finished Mar 10 12:19:49 PM PDT 24
Peak memory 182896 kb
Host smart-392f1f3d-c9ed-41c2-8ac4-a79750d9842d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217589930 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.2217589930
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.1306471350
Short name T408
Test name
Test status
Simulation time 307388341 ps
CPU time 0.96 seconds
Started Mar 10 12:19:48 PM PDT 24
Finished Mar 10 12:19:49 PM PDT 24
Peak memory 182844 kb
Host smart-7d3b7110-a980-4564-8cdd-43ffb160225e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306471350 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.1306471350
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.2707715080
Short name T386
Test name
Test status
Simulation time 293050424 ps
CPU time 0.99 seconds
Started Mar 10 12:19:52 PM PDT 24
Finished Mar 10 12:19:53 PM PDT 24
Peak memory 182832 kb
Host smart-06d4f327-3a92-479b-90e7-a757bf27ffb0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707715080 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.2707715080
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.192639813
Short name T302
Test name
Test status
Simulation time 451713066 ps
CPU time 1.16 seconds
Started Mar 10 12:19:40 PM PDT 24
Finished Mar 10 12:19:41 PM PDT 24
Peak memory 183080 kb
Host smart-d635edb5-28a2-4255-989e-c3493d77fbca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192639813 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.192639813
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.4130931647
Short name T412
Test name
Test status
Simulation time 321610329 ps
CPU time 1.08 seconds
Started Mar 10 12:19:54 PM PDT 24
Finished Mar 10 12:19:56 PM PDT 24
Peak memory 182864 kb
Host smart-55b546e4-b14e-46f9-8417-9de146b399f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130931647 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.4130931647
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.2018063924
Short name T388
Test name
Test status
Simulation time 389930350 ps
CPU time 0.64 seconds
Started Mar 10 12:19:47 PM PDT 24
Finished Mar 10 12:19:48 PM PDT 24
Peak memory 182836 kb
Host smart-c5bb0d77-3841-41ce-a162-3cfd85d7705e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018063924 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.2018063924
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.881365530
Short name T375
Test name
Test status
Simulation time 414044032 ps
CPU time 1.08 seconds
Started Mar 10 12:23:10 PM PDT 24
Finished Mar 10 12:23:12 PM PDT 24
Peak memory 182880 kb
Host smart-991b63e5-028c-445f-a987-f403b3c8594c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881365530 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.881365530
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.2734725193
Short name T359
Test name
Test status
Simulation time 269646620 ps
CPU time 0.96 seconds
Started Mar 10 12:19:48 PM PDT 24
Finished Mar 10 12:19:49 PM PDT 24
Peak memory 182844 kb
Host smart-d0dc840a-5269-4da8-bc67-2ac98d12048f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734725193 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.2734725193
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.3927727739
Short name T383
Test name
Test status
Simulation time 494956085 ps
CPU time 0.77 seconds
Started Mar 10 12:19:48 PM PDT 24
Finished Mar 10 12:19:49 PM PDT 24
Peak memory 182844 kb
Host smart-b710966c-159c-4357-b668-dcace9653952
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927727739 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.3927727739
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.1464639878
Short name T339
Test name
Test status
Simulation time 591204985 ps
CPU time 0.89 seconds
Started Mar 10 12:27:05 PM PDT 24
Finished Mar 10 12:27:06 PM PDT 24
Peak memory 192400 kb
Host smart-17794a36-97f3-4b84-8b1f-1f43645a08b9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464639878 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_a
liasing.1464639878
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.1467105297
Short name T62
Test name
Test status
Simulation time 1249855861 ps
CPU time 4.52 seconds
Started Mar 10 12:29:06 PM PDT 24
Finished Mar 10 12:29:12 PM PDT 24
Peak memory 190244 kb
Host smart-bd679207-d71f-4009-b19d-6eb6d124a60b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467105297 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_b
it_bash.1467105297
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.1101110920
Short name T342
Test name
Test status
Simulation time 1070982288 ps
CPU time 1 seconds
Started Mar 10 12:29:20 PM PDT 24
Finished Mar 10 12:29:22 PM PDT 24
Peak memory 182956 kb
Host smart-893ef389-af4d-4a90-a6fd-bf5e06cbeae0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101110920 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_h
w_reset.1101110920
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.2384421137
Short name T398
Test name
Test status
Simulation time 386851814 ps
CPU time 1.13 seconds
Started Mar 10 12:32:22 PM PDT 24
Finished Mar 10 12:32:24 PM PDT 24
Peak memory 194588 kb
Host smart-e8a07d16-2f9a-4890-a4b8-c767253a7fc5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384421137 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.2384421137
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.30643510
Short name T30
Test name
Test status
Simulation time 583867902 ps
CPU time 0.65 seconds
Started Mar 10 12:30:09 PM PDT 24
Finished Mar 10 12:30:10 PM PDT 24
Peak memory 182916 kb
Host smart-cbd05710-8779-414f-b6b5-949f3966b6ff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30643510 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.30643510
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.3048775669
Short name T307
Test name
Test status
Simulation time 456573426 ps
CPU time 1.19 seconds
Started Mar 10 12:23:00 PM PDT 24
Finished Mar 10 12:23:02 PM PDT 24
Peak memory 182000 kb
Host smart-5bafd30f-15f5-45dc-8d10-d627e3d800dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048775669 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.3048775669
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.1531675599
Short name T354
Test name
Test status
Simulation time 502503987 ps
CPU time 1.34 seconds
Started Mar 10 12:30:16 PM PDT 24
Finished Mar 10 12:30:18 PM PDT 24
Peak memory 182060 kb
Host smart-00353093-a34f-431c-8c48-a6c3639fed23
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531675599 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_t
imer_mem_partial_access.1531675599
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.1961896431
Short name T410
Test name
Test status
Simulation time 397036051 ps
CPU time 1.1 seconds
Started Mar 10 12:30:11 PM PDT 24
Finished Mar 10 12:30:12 PM PDT 24
Peak memory 182024 kb
Host smart-70e16721-ca59-44d6-8ccb-ab7ac27441dc
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961896431 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_w
alk.1961896431
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.2015990564
Short name T402
Test name
Test status
Simulation time 2306311535 ps
CPU time 1.64 seconds
Started Mar 10 12:26:48 PM PDT 24
Finished Mar 10 12:26:50 PM PDT 24
Peak memory 192608 kb
Host smart-4bee95ef-5a02-42e5-a62e-4d5c4bc4c5da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015990564 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon
_timer_same_csr_outstanding.2015990564
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.4212840956
Short name T316
Test name
Test status
Simulation time 511189804 ps
CPU time 1.99 seconds
Started Mar 10 12:22:53 PM PDT 24
Finished Mar 10 12:22:55 PM PDT 24
Peak memory 197800 kb
Host smart-992bb4c1-bb84-4f30-98ed-61a99e35786c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212840956 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.4212840956
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.695275753
Short name T403
Test name
Test status
Simulation time 3994867803 ps
CPU time 3.82 seconds
Started Mar 10 12:20:46 PM PDT 24
Finished Mar 10 12:20:51 PM PDT 24
Peak memory 196420 kb
Host smart-0bbb0707-601e-418a-a28b-e0cc907869ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695275753 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_
intg_err.695275753
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.551846559
Short name T305
Test name
Test status
Simulation time 490844620 ps
CPU time 0.75 seconds
Started Mar 10 12:23:50 PM PDT 24
Finished Mar 10 12:23:52 PM PDT 24
Peak memory 181548 kb
Host smart-74a35610-62ee-45f0-adcf-0ff9f964d0cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551846559 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.551846559
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.2209836639
Short name T284
Test name
Test status
Simulation time 328683822 ps
CPU time 0.98 seconds
Started Mar 10 12:33:45 PM PDT 24
Finished Mar 10 12:33:46 PM PDT 24
Peak memory 182836 kb
Host smart-7ed34d6c-a6cd-4c1e-866b-47899a0b3409
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209836639 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.2209836639
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.892335259
Short name T366
Test name
Test status
Simulation time 383357660 ps
CPU time 0.57 seconds
Started Mar 10 12:24:05 PM PDT 24
Finished Mar 10 12:24:06 PM PDT 24
Peak memory 182760 kb
Host smart-36487a40-11c1-48bf-901b-32f2af818d80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892335259 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.892335259
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.2111385593
Short name T287
Test name
Test status
Simulation time 402422880 ps
CPU time 0.65 seconds
Started Mar 10 12:33:42 PM PDT 24
Finished Mar 10 12:33:44 PM PDT 24
Peak memory 182912 kb
Host smart-c398ef3f-a1a5-45d1-919e-0189a98f8795
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111385593 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.2111385593
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.2969921311
Short name T347
Test name
Test status
Simulation time 298823814 ps
CPU time 0.78 seconds
Started Mar 10 12:32:54 PM PDT 24
Finished Mar 10 12:32:55 PM PDT 24
Peak memory 182820 kb
Host smart-b27d25fd-7bb6-4b05-9167-88e513a70dbf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969921311 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.2969921311
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.188503651
Short name T364
Test name
Test status
Simulation time 371505258 ps
CPU time 1.15 seconds
Started Mar 10 12:20:35 PM PDT 24
Finished Mar 10 12:20:36 PM PDT 24
Peak memory 183320 kb
Host smart-74e11b16-ecde-43a5-af57-1c9317b1ef74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188503651 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.188503651
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.1585803583
Short name T358
Test name
Test status
Simulation time 468009722 ps
CPU time 0.68 seconds
Started Mar 10 12:32:53 PM PDT 24
Finished Mar 10 12:32:54 PM PDT 24
Peak memory 182900 kb
Host smart-87be526b-2d62-442c-bac2-5f7675e4c134
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585803583 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.1585803583
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.1677363349
Short name T411
Test name
Test status
Simulation time 364414194 ps
CPU time 1.06 seconds
Started Mar 10 12:32:22 PM PDT 24
Finished Mar 10 12:32:24 PM PDT 24
Peak memory 182912 kb
Host smart-30421889-0b3e-4e7f-a0ff-ce6e46c55879
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677363349 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.1677363349
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.3286457461
Short name T357
Test name
Test status
Simulation time 403307321 ps
CPU time 0.84 seconds
Started Mar 10 12:19:52 PM PDT 24
Finished Mar 10 12:19:53 PM PDT 24
Peak memory 182836 kb
Host smart-8ff00ba2-c968-4b88-ac41-c004fcf90e8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286457461 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.3286457461
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.314083707
Short name T322
Test name
Test status
Simulation time 369982695 ps
CPU time 0.8 seconds
Started Mar 10 12:32:53 PM PDT 24
Finished Mar 10 12:32:54 PM PDT 24
Peak memory 182912 kb
Host smart-904f0160-5e97-4c75-9d0d-7b71d0aec04b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314083707 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.314083707
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.3330681638
Short name T29
Test name
Test status
Simulation time 676337112 ps
CPU time 1.32 seconds
Started Mar 10 12:22:57 PM PDT 24
Finished Mar 10 12:22:58 PM PDT 24
Peak memory 182996 kb
Host smart-b8437381-e1c6-4e69-bdf1-e57fec2a33ac
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330681638 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_a
liasing.3330681638
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.550214817
Short name T64
Test name
Test status
Simulation time 7784337466 ps
CPU time 5.83 seconds
Started Mar 10 12:23:10 PM PDT 24
Finished Mar 10 12:23:16 PM PDT 24
Peak memory 191368 kb
Host smart-1006bd12-1f88-4395-8190-a76fa1b58c09
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550214817 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_bi
t_bash.550214817
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.632789901
Short name T420
Test name
Test status
Simulation time 1277049885 ps
CPU time 0.86 seconds
Started Mar 10 12:18:33 PM PDT 24
Finished Mar 10 12:18:34 PM PDT 24
Peak memory 183012 kb
Host smart-712a5982-f1c9-48ed-95cd-35390ae482fe
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632789901 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_hw
_reset.632789901
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.142646782
Short name T374
Test name
Test status
Simulation time 399564202 ps
CPU time 1.08 seconds
Started Mar 10 12:19:09 PM PDT 24
Finished Mar 10 12:19:12 PM PDT 24
Peak memory 195644 kb
Host smart-9a4061cd-3c81-4d88-9761-f5fc5a0f024f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142646782 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.142646782
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.1257794651
Short name T406
Test name
Test status
Simulation time 406963576 ps
CPU time 1.17 seconds
Started Mar 10 12:19:06 PM PDT 24
Finished Mar 10 12:19:08 PM PDT 24
Peak memory 182948 kb
Host smart-0f4308fe-d8c7-41ff-9330-bcc2dae62875
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257794651 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.1257794651
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.300269682
Short name T290
Test name
Test status
Simulation time 542880908 ps
CPU time 0.75 seconds
Started Mar 10 12:21:24 PM PDT 24
Finished Mar 10 12:21:25 PM PDT 24
Peak memory 183076 kb
Host smart-8feb54c4-3336-4a44-aef3-6cd8472c7838
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300269682 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.300269682
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.1939595755
Short name T346
Test name
Test status
Simulation time 415500169 ps
CPU time 1.18 seconds
Started Mar 10 12:18:34 PM PDT 24
Finished Mar 10 12:18:35 PM PDT 24
Peak memory 182828 kb
Host smart-7f660dce-375a-4f95-ae9e-e1ae33a70d09
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939595755 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_t
imer_mem_partial_access.1939595755
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.2533846066
Short name T304
Test name
Test status
Simulation time 505664613 ps
CPU time 0.62 seconds
Started Mar 10 12:23:25 PM PDT 24
Finished Mar 10 12:23:26 PM PDT 24
Peak memory 182792 kb
Host smart-cecae758-4ef8-476a-a431-08d317a57511
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533846066 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_w
alk.2533846066
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.1556934966
Short name T409
Test name
Test status
Simulation time 1247104640 ps
CPU time 1.97 seconds
Started Mar 10 12:23:14 PM PDT 24
Finished Mar 10 12:23:17 PM PDT 24
Peak memory 183028 kb
Host smart-d65668d5-3480-4eeb-aeee-1b500fbdab3c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556934966 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon
_timer_same_csr_outstanding.1556934966
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.3150577193
Short name T371
Test name
Test status
Simulation time 529859463 ps
CPU time 0.88 seconds
Started Mar 10 12:27:05 PM PDT 24
Finished Mar 10 12:27:06 PM PDT 24
Peak memory 196396 kb
Host smart-e5591eb9-d1cf-4e7e-ba9f-31d0c0ea034f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150577193 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.3150577193
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.4120327661
Short name T94
Test name
Test status
Simulation time 4431958187 ps
CPU time 2.46 seconds
Started Mar 10 12:30:24 PM PDT 24
Finished Mar 10 12:30:27 PM PDT 24
Peak memory 196444 kb
Host smart-55bf5cb6-feec-4e74-bd5b-8dc7db9e11ea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120327661 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl
_intg_err.4120327661
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.2140996077
Short name T340
Test name
Test status
Simulation time 444227624 ps
CPU time 1.19 seconds
Started Mar 10 12:19:54 PM PDT 24
Finished Mar 10 12:19:56 PM PDT 24
Peak memory 182864 kb
Host smart-4dd2e20f-346a-4f46-af47-395bad30ee22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140996077 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.2140996077
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.1523718805
Short name T418
Test name
Test status
Simulation time 482092750 ps
CPU time 0.64 seconds
Started Mar 10 12:20:48 PM PDT 24
Finished Mar 10 12:20:50 PM PDT 24
Peak memory 182796 kb
Host smart-6383c67e-7a68-4c85-b20b-4f407a56e475
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523718805 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.1523718805
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.175240858
Short name T352
Test name
Test status
Simulation time 329872889 ps
CPU time 0.6 seconds
Started Mar 10 12:20:17 PM PDT 24
Finished Mar 10 12:20:18 PM PDT 24
Peak memory 182808 kb
Host smart-01397dff-93b4-414f-8ce6-8219d929ee74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175240858 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.175240858
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.1219961214
Short name T324
Test name
Test status
Simulation time 337766795 ps
CPU time 1.02 seconds
Started Mar 10 12:33:46 PM PDT 24
Finished Mar 10 12:33:47 PM PDT 24
Peak memory 182992 kb
Host smart-521a55e1-99d5-42df-a1dc-71d86ec6a9b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219961214 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.1219961214
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.1716015885
Short name T348
Test name
Test status
Simulation time 468806304 ps
CPU time 0.76 seconds
Started Mar 10 12:19:54 PM PDT 24
Finished Mar 10 12:19:55 PM PDT 24
Peak memory 182812 kb
Host smart-2940e64c-20ff-4629-9382-5859b8c37ce4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716015885 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.1716015885
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.486950548
Short name T331
Test name
Test status
Simulation time 417042851 ps
CPU time 1.18 seconds
Started Mar 10 12:20:18 PM PDT 24
Finished Mar 10 12:20:19 PM PDT 24
Peak memory 182812 kb
Host smart-49b29b16-8ed1-46da-83b0-c9fd334d8c03
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486950548 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.486950548
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.4044238901
Short name T407
Test name
Test status
Simulation time 424801725 ps
CPU time 0.66 seconds
Started Mar 10 12:20:05 PM PDT 24
Finished Mar 10 12:20:06 PM PDT 24
Peak memory 182844 kb
Host smart-74899e8a-4113-4a74-b389-c278ddd51bb5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044238901 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.4044238901
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.3744300828
Short name T385
Test name
Test status
Simulation time 414532022 ps
CPU time 0.62 seconds
Started Mar 10 12:19:52 PM PDT 24
Finished Mar 10 12:19:53 PM PDT 24
Peak memory 182888 kb
Host smart-df6fb344-f5fd-4663-b426-abceab86f57b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744300828 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.3744300828
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.993695222
Short name T394
Test name
Test status
Simulation time 324293467 ps
CPU time 0.64 seconds
Started Mar 10 12:20:49 PM PDT 24
Finished Mar 10 12:20:51 PM PDT 24
Peak memory 183320 kb
Host smart-4fca0cef-d53c-41df-b992-5cf597810205
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993695222 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.993695222
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.1854649782
Short name T283
Test name
Test status
Simulation time 432324499 ps
CPU time 0.69 seconds
Started Mar 10 12:19:54 PM PDT 24
Finished Mar 10 12:19:55 PM PDT 24
Peak memory 182824 kb
Host smart-4f001c94-33f8-4aa0-92b1-37e24f5b960b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854649782 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.1854649782
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.268923709
Short name T31
Test name
Test status
Simulation time 638824199 ps
CPU time 0.89 seconds
Started Mar 10 12:32:53 PM PDT 24
Finished Mar 10 12:32:53 PM PDT 24
Peak memory 195332 kb
Host smart-30d222dc-d435-4fde-a8d0-d1c58b3ecc8f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268923709 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.268923709
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.3396961191
Short name T68
Test name
Test status
Simulation time 348509946 ps
CPU time 1.08 seconds
Started Mar 10 12:32:51 PM PDT 24
Finished Mar 10 12:32:52 PM PDT 24
Peak memory 183600 kb
Host smart-76c76978-e2e7-4086-a211-47a2f19d7856
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396961191 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.3396961191
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.16279549
Short name T349
Test name
Test status
Simulation time 315616188 ps
CPU time 0.58 seconds
Started Mar 10 12:23:14 PM PDT 24
Finished Mar 10 12:23:15 PM PDT 24
Peak memory 182788 kb
Host smart-6f8e281f-d845-4845-af6b-e33cfd909d4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16279549 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.16279549
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.2592332557
Short name T384
Test name
Test status
Simulation time 2444316581 ps
CPU time 2.18 seconds
Started Mar 10 12:18:32 PM PDT 24
Finished Mar 10 12:18:35 PM PDT 24
Peak memory 193604 kb
Host smart-20aff1da-e234-44a0-b642-0f388f2b9670
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592332557 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon
_timer_same_csr_outstanding.2592332557
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.1651074136
Short name T373
Test name
Test status
Simulation time 463912039 ps
CPU time 2.74 seconds
Started Mar 10 12:18:43 PM PDT 24
Finished Mar 10 12:18:46 PM PDT 24
Peak memory 197812 kb
Host smart-6564159a-bc0d-413f-a582-aa6855e44b10
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651074136 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.1651074136
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.1866234764
Short name T95
Test name
Test status
Simulation time 4480372780 ps
CPU time 3.14 seconds
Started Mar 10 12:19:18 PM PDT 24
Finished Mar 10 12:19:21 PM PDT 24
Peak memory 197156 kb
Host smart-b7708c42-7e5f-4f65-859f-339519a4b9db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866234764 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl
_intg_err.1866234764
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.184217206
Short name T401
Test name
Test status
Simulation time 545507775 ps
CPU time 1.46 seconds
Started Mar 10 12:27:06 PM PDT 24
Finished Mar 10 12:27:07 PM PDT 24
Peak memory 195392 kb
Host smart-67d6cb49-5470-49f6-b12e-12224b366ff2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184217206 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.184217206
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.3166610377
Short name T102
Test name
Test status
Simulation time 348808742 ps
CPU time 1.13 seconds
Started Mar 10 12:24:12 PM PDT 24
Finished Mar 10 12:24:14 PM PDT 24
Peak memory 181196 kb
Host smart-75060f02-73c3-4218-95d9-29c4268baa76
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166610377 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.3166610377
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.3951984642
Short name T306
Test name
Test status
Simulation time 423986706 ps
CPU time 0.71 seconds
Started Mar 10 12:32:22 PM PDT 24
Finished Mar 10 12:32:23 PM PDT 24
Peak memory 182820 kb
Host smart-0fe4abd9-f81d-4362-b956-ab14d9e3aa7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951984642 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.3951984642
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.4189037471
Short name T404
Test name
Test status
Simulation time 3008746014 ps
CPU time 8.22 seconds
Started Mar 10 12:24:28 PM PDT 24
Finished Mar 10 12:24:36 PM PDT 24
Peak memory 183040 kb
Host smart-1cb067c9-d71c-40d4-96b2-5976038b9ec4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189037471 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon
_timer_same_csr_outstanding.4189037471
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.1736308055
Short name T288
Test name
Test status
Simulation time 401458655 ps
CPU time 1.57 seconds
Started Mar 10 12:32:54 PM PDT 24
Finished Mar 10 12:32:56 PM PDT 24
Peak memory 197916 kb
Host smart-7b0b8e50-0986-4593-a1d1-44f4cfa892dc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736308055 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.1736308055
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.4194070987
Short name T415
Test name
Test status
Simulation time 4222373119 ps
CPU time 2.19 seconds
Started Mar 10 12:32:51 PM PDT 24
Finished Mar 10 12:32:54 PM PDT 24
Peak memory 195660 kb
Host smart-dba91fdf-11c8-43ea-b0af-1fe987deea34
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194070987 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl
_intg_err.4194070987
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.4264922244
Short name T296
Test name
Test status
Simulation time 617603973 ps
CPU time 1.01 seconds
Started Mar 10 12:27:05 PM PDT 24
Finished Mar 10 12:27:07 PM PDT 24
Peak memory 194956 kb
Host smart-d978ce03-3cff-40c0-bbe8-87a87c23d6cf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264922244 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.4264922244
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.2446060185
Short name T312
Test name
Test status
Simulation time 505206882 ps
CPU time 0.75 seconds
Started Mar 10 12:27:20 PM PDT 24
Finished Mar 10 12:27:22 PM PDT 24
Peak memory 183000 kb
Host smart-0bdebd20-6534-4dc2-818d-9783c2ee537f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446060185 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.2446060185
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.766496750
Short name T416
Test name
Test status
Simulation time 442661103 ps
CPU time 1.16 seconds
Started Mar 10 12:24:25 PM PDT 24
Finished Mar 10 12:24:26 PM PDT 24
Peak memory 182688 kb
Host smart-00c41230-3724-466c-8df4-311ec2185e68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766496750 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.766496750
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.2565445603
Short name T392
Test name
Test status
Simulation time 2452032672 ps
CPU time 2.09 seconds
Started Mar 10 12:19:03 PM PDT 24
Finished Mar 10 12:19:05 PM PDT 24
Peak memory 193632 kb
Host smart-82053cfd-874f-41f5-9378-97313696ebaf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565445603 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon
_timer_same_csr_outstanding.2565445603
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.3873858172
Short name T393
Test name
Test status
Simulation time 390744282 ps
CPU time 1.85 seconds
Started Mar 10 12:27:37 PM PDT 24
Finished Mar 10 12:27:39 PM PDT 24
Peak memory 196532 kb
Host smart-1d5d4d59-6d1e-4c5d-bae3-b283a0c7d6f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873858172 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.3873858172
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.2339150891
Short name T96
Test name
Test status
Simulation time 8484676536 ps
CPU time 4.18 seconds
Started Mar 10 12:27:22 PM PDT 24
Finished Mar 10 12:27:26 PM PDT 24
Peak memory 196824 kb
Host smart-6c9ef9c1-5d75-4234-82c2-dc539f24ddad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339150891 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl
_intg_err.2339150891
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.3259965677
Short name T396
Test name
Test status
Simulation time 539274773 ps
CPU time 1.52 seconds
Started Mar 10 12:18:39 PM PDT 24
Finished Mar 10 12:18:40 PM PDT 24
Peak memory 194320 kb
Host smart-5980285a-c240-4828-8f1e-0d331364c7df
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259965677 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.3259965677
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.2475402438
Short name T61
Test name
Test status
Simulation time 475914904 ps
CPU time 1.23 seconds
Started Mar 10 12:22:34 PM PDT 24
Finished Mar 10 12:22:36 PM PDT 24
Peak memory 182332 kb
Host smart-8ddf10b3-3ec9-4110-ac03-6d4777d16036
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475402438 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.2475402438
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.974453899
Short name T400
Test name
Test status
Simulation time 372889712 ps
CPU time 0.65 seconds
Started Mar 10 12:22:53 PM PDT 24
Finished Mar 10 12:22:54 PM PDT 24
Peak memory 182772 kb
Host smart-494321dc-8139-407d-aee6-b16ea03378a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974453899 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.974453899
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.283682164
Short name T372
Test name
Test status
Simulation time 3202015980 ps
CPU time 3.91 seconds
Started Mar 10 12:33:54 PM PDT 24
Finished Mar 10 12:33:58 PM PDT 24
Peak memory 193968 kb
Host smart-d0e3c004-46ac-4f45-baf8-00f804bc99de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283682164 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_
timer_same_csr_outstanding.283682164
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.1662914741
Short name T363
Test name
Test status
Simulation time 527249721 ps
CPU time 1.4 seconds
Started Mar 10 12:33:38 PM PDT 24
Finished Mar 10 12:33:40 PM PDT 24
Peak memory 198228 kb
Host smart-dce7b2b1-1b89-4872-8b42-7bc1a6609ec6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662914741 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.1662914741
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.3834797756
Short name T341
Test name
Test status
Simulation time 8539181899 ps
CPU time 7.28 seconds
Started Mar 10 12:24:25 PM PDT 24
Finished Mar 10 12:24:32 PM PDT 24
Peak memory 196972 kb
Host smart-9701f044-dcdf-4d93-96c0-fbcd226e869c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834797756 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl
_intg_err.3834797756
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.954368945
Short name T413
Test name
Test status
Simulation time 472855034 ps
CPU time 1.44 seconds
Started Mar 10 12:22:53 PM PDT 24
Finished Mar 10 12:22:55 PM PDT 24
Peak memory 195608 kb
Host smart-7bc8dd84-49dd-42f7-9ad7-f62790fd9189
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954368945 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.954368945
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.2835107348
Short name T350
Test name
Test status
Simulation time 342166432 ps
CPU time 0.68 seconds
Started Mar 10 12:22:53 PM PDT 24
Finished Mar 10 12:22:54 PM PDT 24
Peak memory 182896 kb
Host smart-c72704c4-e229-4587-aea9-043e858eefa2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835107348 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.2835107348
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.964598767
Short name T337
Test name
Test status
Simulation time 295918289 ps
CPU time 0.68 seconds
Started Mar 10 12:20:47 PM PDT 24
Finished Mar 10 12:20:49 PM PDT 24
Peak memory 182808 kb
Host smart-7fe3d082-759d-425c-bbb7-3adada0adae2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964598767 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.964598767
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.1214094785
Short name T343
Test name
Test status
Simulation time 1954140670 ps
CPU time 1.36 seconds
Started Mar 10 12:22:53 PM PDT 24
Finished Mar 10 12:22:54 PM PDT 24
Peak memory 192540 kb
Host smart-46610d5a-2941-403d-b4df-217517b55249
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214094785 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon
_timer_same_csr_outstanding.1214094785
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.914112871
Short name T380
Test name
Test status
Simulation time 468299032 ps
CPU time 1.96 seconds
Started Mar 10 12:23:43 PM PDT 24
Finished Mar 10 12:23:47 PM PDT 24
Peak memory 196716 kb
Host smart-aae12c0d-bcc3-4960-8538-99022e50a7a7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914112871 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.914112871
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.3936837150
Short name T99
Test name
Test status
Simulation time 8287594670 ps
CPU time 4.99 seconds
Started Mar 10 12:18:01 PM PDT 24
Finished Mar 10 12:18:07 PM PDT 24
Peak memory 197328 kb
Host smart-687ddaf2-9126-4b67-a494-a9376666dc2e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936837150 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl
_intg_err.3936837150
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_jump.2801508243
Short name T117
Test name
Test status
Simulation time 522400136 ps
CPU time 1.26 seconds
Started Mar 10 12:33:42 PM PDT 24
Finished Mar 10 12:33:44 PM PDT 24
Peak memory 183812 kb
Host smart-ac522156-2ef8-4758-8098-d958ae4ebab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801508243 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.2801508243
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.3563763471
Short name T103
Test name
Test status
Simulation time 19304948978 ps
CPU time 7.92 seconds
Started Mar 10 12:30:28 PM PDT 24
Finished Mar 10 12:30:37 PM PDT 24
Peak memory 182784 kb
Host smart-ac36a20c-8ec8-494d-bcaf-748bb8bc0e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563763471 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.3563763471
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.832041790
Short name T106
Test name
Test status
Simulation time 485509032 ps
CPU time 1.32 seconds
Started Mar 10 12:20:42 PM PDT 24
Finished Mar 10 12:20:44 PM PDT 24
Peak memory 183836 kb
Host smart-23427e25-39b0-4001-bdb8-e0cad06c523c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832041790 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.832041790
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.483275997
Short name T270
Test name
Test status
Simulation time 91754433290 ps
CPU time 141.3 seconds
Started Mar 10 12:23:57 PM PDT 24
Finished Mar 10 12:26:19 PM PDT 24
Peak memory 194408 kb
Host smart-f372e615-ecb8-4ad0-854e-bf04610cf0ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483275997 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_al
l.483275997
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.1515531392
Short name T184
Test name
Test status
Simulation time 24197728785 ps
CPU time 183.91 seconds
Started Mar 10 12:23:57 PM PDT 24
Finished Mar 10 12:27:02 PM PDT 24
Peak memory 198596 kb
Host smart-bdd1c959-eaee-4023-b126-f5ba3acf06c0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515531392 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.1515531392
Directory /workspace/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.aon_timer_jump.1592698568
Short name T133
Test name
Test status
Simulation time 583233025 ps
CPU time 1.05 seconds
Started Mar 10 12:23:36 PM PDT 24
Finished Mar 10 12:23:37 PM PDT 24
Peak memory 183760 kb
Host smart-016fa0b4-40b6-4d15-8ada-f5016ab2cf93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592698568 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.1592698568
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.2794878813
Short name T200
Test name
Test status
Simulation time 34997196854 ps
CPU time 14.7 seconds
Started Mar 10 12:24:43 PM PDT 24
Finished Mar 10 12:24:59 PM PDT 24
Peak memory 183828 kb
Host smart-ab151394-e797-4518-a3e4-4da76c358d60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794878813 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.2794878813
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.2887597691
Short name T16
Test name
Test status
Simulation time 4228268602 ps
CPU time 2.54 seconds
Started Mar 10 12:33:06 PM PDT 24
Finished Mar 10 12:33:09 PM PDT 24
Peak memory 215152 kb
Host smart-dac2d1a5-22f0-436c-a22c-a57e71041347
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887597691 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.2887597691
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.2078932855
Short name T167
Test name
Test status
Simulation time 409847057 ps
CPU time 1.17 seconds
Started Mar 10 12:33:05 PM PDT 24
Finished Mar 10 12:33:06 PM PDT 24
Peak memory 183624 kb
Host smart-5593e9ff-ceb6-4263-b3ca-5d71eab48717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078932855 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.2078932855
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.336781100
Short name T163
Test name
Test status
Simulation time 40268999853 ps
CPU time 26.48 seconds
Started Mar 10 12:24:22 PM PDT 24
Finished Mar 10 12:24:49 PM PDT 24
Peak memory 183852 kb
Host smart-bb178df4-6a96-44ff-b090-814ce87d8eda
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336781100 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_al
l.336781100
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.2750412878
Short name T242
Test name
Test status
Simulation time 210345796325 ps
CPU time 469.25 seconds
Started Mar 10 12:33:05 PM PDT 24
Finished Mar 10 12:40:55 PM PDT 24
Peak memory 198616 kb
Host smart-8048ba8a-4fdb-4796-b262-f0ce70fa8827
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750412878 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.2750412878
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.aon_timer_jump.3841620470
Short name T205
Test name
Test status
Simulation time 528805903 ps
CPU time 1.03 seconds
Started Mar 10 12:22:57 PM PDT 24
Finished Mar 10 12:22:58 PM PDT 24
Peak memory 183804 kb
Host smart-78027cfe-6503-49ab-b392-8f2051dd346e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841620470 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.3841620470
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.4247244965
Short name T215
Test name
Test status
Simulation time 40943236249 ps
CPU time 56.22 seconds
Started Mar 10 12:23:01 PM PDT 24
Finished Mar 10 12:23:57 PM PDT 24
Peak memory 192008 kb
Host smart-a602cb23-e427-4b05-997a-386297699553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247244965 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.4247244965
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.508528494
Short name T251
Test name
Test status
Simulation time 557514434 ps
CPU time 0.76 seconds
Started Mar 10 12:22:51 PM PDT 24
Finished Mar 10 12:22:52 PM PDT 24
Peak memory 183816 kb
Host smart-08ebcb90-40b3-4011-8eba-ea56f0fff0ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508528494 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.508528494
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.1794015221
Short name T261
Test name
Test status
Simulation time 331833941598 ps
CPU time 60.31 seconds
Started Mar 10 12:23:14 PM PDT 24
Finished Mar 10 12:24:14 PM PDT 24
Peak memory 183964 kb
Host smart-12083e3e-a08e-4f93-8a04-72fb2ab2fa8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794015221 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_
all.1794015221
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_jump.1609981751
Short name T236
Test name
Test status
Simulation time 527280085 ps
CPU time 1.4 seconds
Started Mar 10 12:23:06 PM PDT 24
Finished Mar 10 12:23:08 PM PDT 24
Peak memory 183804 kb
Host smart-fa973415-9fdc-4b60-99f1-287d331d5783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609981751 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.1609981751
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.3008036166
Short name T260
Test name
Test status
Simulation time 26655693084 ps
CPU time 18.28 seconds
Started Mar 10 12:23:06 PM PDT 24
Finished Mar 10 12:23:25 PM PDT 24
Peak memory 183796 kb
Host smart-1fe4f98b-aed1-46d5-803f-e7067484b1a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008036166 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.3008036166
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.603351119
Short name T137
Test name
Test status
Simulation time 518822450 ps
CPU time 0.76 seconds
Started Mar 10 12:23:06 PM PDT 24
Finished Mar 10 12:23:07 PM PDT 24
Peak memory 183688 kb
Host smart-e8f0d367-564d-4023-9dc2-e137d87f0860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603351119 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.603351119
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.3473737933
Short name T272
Test name
Test status
Simulation time 139409968573 ps
CPU time 39.25 seconds
Started Mar 10 12:22:59 PM PDT 24
Finished Mar 10 12:23:39 PM PDT 24
Peak memory 194844 kb
Host smart-95f61168-e285-46f9-8557-cb87e3bcccd0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473737933 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_
all.3473737933
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.1582672799
Short name T241
Test name
Test status
Simulation time 678712489853 ps
CPU time 287.11 seconds
Started Mar 10 12:23:06 PM PDT 24
Finished Mar 10 12:27:54 PM PDT 24
Peak memory 198704 kb
Host smart-bcc834da-a3c8-47f7-8232-02d644c63ed3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582672799 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand_reset.1582672799
Directory /workspace/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.aon_timer_jump.3926981339
Short name T233
Test name
Test status
Simulation time 493049304 ps
CPU time 0.67 seconds
Started Mar 10 12:23:02 PM PDT 24
Finished Mar 10 12:23:03 PM PDT 24
Peak memory 183320 kb
Host smart-926f9826-42a4-4921-9ad4-a5f16b0be1dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926981339 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.3926981339
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.1120700743
Short name T139
Test name
Test status
Simulation time 9554338499 ps
CPU time 4.68 seconds
Started Mar 10 12:23:01 PM PDT 24
Finished Mar 10 12:23:06 PM PDT 24
Peak memory 183812 kb
Host smart-a50d8117-6aff-4fb4-8fe2-140d17ec12ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120700743 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.1120700743
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.1031029820
Short name T170
Test name
Test status
Simulation time 514061097 ps
CPU time 0.87 seconds
Started Mar 10 12:23:06 PM PDT 24
Finished Mar 10 12:23:08 PM PDT 24
Peak memory 183728 kb
Host smart-e8310c06-2c93-4e4e-8327-adb03d88f231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031029820 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.1031029820
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.1281937736
Short name T138
Test name
Test status
Simulation time 151045894549 ps
CPU time 48.67 seconds
Started Mar 10 12:23:09 PM PDT 24
Finished Mar 10 12:23:58 PM PDT 24
Peak memory 184052 kb
Host smart-470d8441-ce12-410d-bf89-7d9c7944afea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281937736 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_
all.1281937736
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.3097304012
Short name T57
Test name
Test status
Simulation time 95829909597 ps
CPU time 256.3 seconds
Started Mar 10 12:23:09 PM PDT 24
Finished Mar 10 12:27:26 PM PDT 24
Peak memory 198924 kb
Host smart-edd6aeec-a564-4bd2-9af4-e1f5555e95a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097304012 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.3097304012
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_jump.3120498627
Short name T273
Test name
Test status
Simulation time 517487846 ps
CPU time 0.76 seconds
Started Mar 10 12:23:01 PM PDT 24
Finished Mar 10 12:23:02 PM PDT 24
Peak memory 183708 kb
Host smart-6bd9f4f2-3fa8-4636-9fac-10987df075f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120498627 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.3120498627
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.3704361608
Short name T23
Test name
Test status
Simulation time 1475105791 ps
CPU time 1 seconds
Started Mar 10 12:23:02 PM PDT 24
Finished Mar 10 12:23:03 PM PDT 24
Peak memory 183412 kb
Host smart-dc70f964-0bd6-4d3a-b97f-4751cb05d8fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704361608 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.3704361608
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.1976565077
Short name T218
Test name
Test status
Simulation time 501334618 ps
CPU time 1.43 seconds
Started Mar 10 12:23:09 PM PDT 24
Finished Mar 10 12:23:11 PM PDT 24
Peak memory 183928 kb
Host smart-e22b6ca3-db93-44d2-91b1-002457b575e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976565077 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.1976565077
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.2040271207
Short name T136
Test name
Test status
Simulation time 109724075852 ps
CPU time 165.32 seconds
Started Mar 10 12:23:14 PM PDT 24
Finished Mar 10 12:26:00 PM PDT 24
Peak memory 194280 kb
Host smart-414ca9b2-43e1-4c5d-841f-6c7c26ab2e82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040271207 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_
all.2040271207
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.3495262500
Short name T119
Test name
Test status
Simulation time 96387066888 ps
CPU time 198.04 seconds
Started Mar 10 12:23:09 PM PDT 24
Finished Mar 10 12:26:27 PM PDT 24
Peak memory 198868 kb
Host smart-9412500a-ed95-4dea-8523-c96aa6364d09
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495262500 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.3495262500
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.aon_timer_jump.237529777
Short name T160
Test name
Test status
Simulation time 437047228 ps
CPU time 0.66 seconds
Started Mar 10 12:23:14 PM PDT 24
Finished Mar 10 12:23:15 PM PDT 24
Peak memory 184004 kb
Host smart-945d311f-5c2d-43c2-8b56-b2c13cfc1040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237529777 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.237529777
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.3074071061
Short name T178
Test name
Test status
Simulation time 10423041993 ps
CPU time 4.46 seconds
Started Mar 10 12:23:14 PM PDT 24
Finished Mar 10 12:23:19 PM PDT 24
Peak memory 184136 kb
Host smart-4126ebe6-01a7-40ab-b03b-a28873bab1c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074071061 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.3074071061
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.3655027766
Short name T116
Test name
Test status
Simulation time 405533237 ps
CPU time 0.71 seconds
Started Mar 10 12:23:09 PM PDT 24
Finished Mar 10 12:23:10 PM PDT 24
Peak memory 183816 kb
Host smart-1aabe7a3-d357-4ae7-8922-98f7d46e9228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655027766 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.3655027766
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.1942459763
Short name T166
Test name
Test status
Simulation time 85148789051 ps
CPU time 70.15 seconds
Started Mar 10 12:23:12 PM PDT 24
Finished Mar 10 12:24:22 PM PDT 24
Peak memory 183824 kb
Host smart-b38df1f0-80db-48d0-841b-274532253391
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942459763 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_
all.1942459763
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.1071332843
Short name T188
Test name
Test status
Simulation time 51833835801 ps
CPU time 110.56 seconds
Started Mar 10 12:23:18 PM PDT 24
Finished Mar 10 12:25:09 PM PDT 24
Peak memory 198752 kb
Host smart-5d6f56b9-b1bf-4c54-a8c1-daaaab1f145b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071332843 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.1071332843
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.aon_timer_jump.1718346327
Short name T191
Test name
Test status
Simulation time 496914926 ps
CPU time 1.19 seconds
Started Mar 10 12:23:11 PM PDT 24
Finished Mar 10 12:23:12 PM PDT 24
Peak memory 183708 kb
Host smart-5d894a88-2e3c-4bde-acd9-b8e5658d026a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718346327 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.1718346327
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.875889757
Short name T153
Test name
Test status
Simulation time 36878011663 ps
CPU time 15.73 seconds
Started Mar 10 12:23:14 PM PDT 24
Finished Mar 10 12:23:30 PM PDT 24
Peak memory 184128 kb
Host smart-34531088-8b3f-488b-872b-ad3e5241fd80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875889757 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.875889757
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.3339245107
Short name T210
Test name
Test status
Simulation time 353119810 ps
CPU time 0.65 seconds
Started Mar 10 12:23:15 PM PDT 24
Finished Mar 10 12:23:16 PM PDT 24
Peak memory 183840 kb
Host smart-1e93d7a6-0f70-4704-a8a6-8694d8ffa61f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339245107 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.3339245107
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.319821055
Short name T18
Test name
Test status
Simulation time 145073012517 ps
CPU time 231.91 seconds
Started Mar 10 12:23:08 PM PDT 24
Finished Mar 10 12:27:00 PM PDT 24
Peak memory 195296 kb
Host smart-081582cb-4d2f-4a9e-ba64-5d56cc5afc5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319821055 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_a
ll.319821055
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.1841602138
Short name T216
Test name
Test status
Simulation time 107543226398 ps
CPU time 477.8 seconds
Started Mar 10 12:23:09 PM PDT 24
Finished Mar 10 12:31:07 PM PDT 24
Peak memory 198924 kb
Host smart-81963a91-6262-486d-8e68-46e98b061899
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841602138 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.1841602138
Directory /workspace/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.aon_timer_jump.3526707277
Short name T217
Test name
Test status
Simulation time 488646907 ps
CPU time 1.23 seconds
Started Mar 10 12:23:17 PM PDT 24
Finished Mar 10 12:23:19 PM PDT 24
Peak memory 183764 kb
Host smart-5a62dfcd-6159-4e95-ab9b-6417ca4ed1cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526707277 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.3526707277
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.3914190312
Short name T49
Test name
Test status
Simulation time 23980802187 ps
CPU time 3.3 seconds
Started Mar 10 12:23:30 PM PDT 24
Finished Mar 10 12:23:33 PM PDT 24
Peak memory 192520 kb
Host smart-36350906-fb7c-4eaf-9238-f751077d52a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914190312 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.3914190312
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.38408278
Short name T158
Test name
Test status
Simulation time 602970525 ps
CPU time 0.7 seconds
Started Mar 10 12:23:18 PM PDT 24
Finished Mar 10 12:23:19 PM PDT 24
Peak memory 183764 kb
Host smart-90f1713d-907c-410c-90e8-5a0a3a7f0490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38408278 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.38408278
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.1344677178
Short name T278
Test name
Test status
Simulation time 38903152465 ps
CPU time 15.14 seconds
Started Mar 10 12:23:09 PM PDT 24
Finished Mar 10 12:23:24 PM PDT 24
Peak memory 183932 kb
Host smart-9db1f3b1-1798-41c6-9e07-07c281ea9a4c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344677178 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_
all.1344677178
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/17.aon_timer_jump.130118498
Short name T28
Test name
Test status
Simulation time 400135599 ps
CPU time 0.67 seconds
Started Mar 10 12:23:14 PM PDT 24
Finished Mar 10 12:23:16 PM PDT 24
Peak memory 184004 kb
Host smart-2f514e0e-6c09-40ed-a2e4-8a007981786f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130118498 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.130118498
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.1857309514
Short name T168
Test name
Test status
Simulation time 3423599748 ps
CPU time 5.85 seconds
Started Mar 10 12:23:18 PM PDT 24
Finished Mar 10 12:23:24 PM PDT 24
Peak memory 183880 kb
Host smart-10fd054e-d642-4ab9-af80-995e5a6e5fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857309514 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.1857309514
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.827857539
Short name T127
Test name
Test status
Simulation time 341927571 ps
CPU time 1.08 seconds
Started Mar 10 12:23:15 PM PDT 24
Finished Mar 10 12:23:17 PM PDT 24
Peak memory 184020 kb
Host smart-8cbff6a3-ec17-4640-88e0-a89c638dd75a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827857539 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.827857539
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.4149916622
Short name T165
Test name
Test status
Simulation time 123195156623 ps
CPU time 158.16 seconds
Started Mar 10 12:23:14 PM PDT 24
Finished Mar 10 12:25:53 PM PDT 24
Peak memory 194400 kb
Host smart-e4308bc3-532d-4a9f-9665-8b0843f4c603
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149916622 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_
all.4149916622
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.4051990975
Short name T126
Test name
Test status
Simulation time 21193521135 ps
CPU time 211.95 seconds
Started Mar 10 12:23:55 PM PDT 24
Finished Mar 10 12:27:27 PM PDT 24
Peak memory 198740 kb
Host smart-74859d35-993e-4d8c-b7aa-a0a7afdd1141
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051990975 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.4051990975
Directory /workspace/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.aon_timer_jump.1370169361
Short name T140
Test name
Test status
Simulation time 448973092 ps
CPU time 1.27 seconds
Started Mar 10 12:23:14 PM PDT 24
Finished Mar 10 12:23:16 PM PDT 24
Peak memory 183840 kb
Host smart-5329ded4-9ff3-4815-94a9-6505e74b8867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370169361 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.1370169361
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.825222976
Short name T43
Test name
Test status
Simulation time 33922765292 ps
CPU time 45.87 seconds
Started Mar 10 12:23:14 PM PDT 24
Finished Mar 10 12:24:00 PM PDT 24
Peak memory 192140 kb
Host smart-1a15b49c-ede1-4051-99e6-6457234e6880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825222976 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.825222976
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.779469839
Short name T121
Test name
Test status
Simulation time 364679895 ps
CPU time 1.05 seconds
Started Mar 10 12:23:17 PM PDT 24
Finished Mar 10 12:23:19 PM PDT 24
Peak memory 183764 kb
Host smart-3c863081-0c18-415c-b806-addcf45c9bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779469839 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.779469839
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.2147954512
Short name T93
Test name
Test status
Simulation time 256627570089 ps
CPU time 184.59 seconds
Started Mar 10 12:23:14 PM PDT 24
Finished Mar 10 12:26:19 PM PDT 24
Peak memory 183944 kb
Host smart-884916d0-9eec-4e1d-8519-ac02e80f2b71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147954512 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_
all.2147954512
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.1551095161
Short name T27
Test name
Test status
Simulation time 4720131574 ps
CPU time 25.83 seconds
Started Mar 10 12:23:15 PM PDT 24
Finished Mar 10 12:23:41 PM PDT 24
Peak memory 198996 kb
Host smart-bd3efdcc-216a-41af-80d9-6366c0ac83ce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551095161 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.1551095161
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.aon_timer_jump.818882433
Short name T249
Test name
Test status
Simulation time 355304374 ps
CPU time 0.84 seconds
Started Mar 10 12:23:17 PM PDT 24
Finished Mar 10 12:23:18 PM PDT 24
Peak memory 183764 kb
Host smart-3e7ebf28-5ba7-4b7d-9339-ecbf0c7cab43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818882433 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.818882433
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.1125370197
Short name T26
Test name
Test status
Simulation time 15270322043 ps
CPU time 23.73 seconds
Started Mar 10 12:23:15 PM PDT 24
Finished Mar 10 12:23:39 PM PDT 24
Peak memory 184120 kb
Host smart-07b66f0b-3178-4cb5-8304-679798d484ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125370197 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.1125370197
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.1438188059
Short name T186
Test name
Test status
Simulation time 369207139 ps
CPU time 0.83 seconds
Started Mar 10 12:23:15 PM PDT 24
Finished Mar 10 12:23:16 PM PDT 24
Peak memory 183824 kb
Host smart-06058a72-a609-40bc-be0f-fc5c086ed9c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438188059 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.1438188059
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.2723429876
Short name T183
Test name
Test status
Simulation time 167294745202 ps
CPU time 56.4 seconds
Started Mar 10 12:23:15 PM PDT 24
Finished Mar 10 12:24:12 PM PDT 24
Peak memory 184336 kb
Host smart-4cc06d8d-bf4c-4d64-9862-96edc66fcb8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723429876 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_
all.2723429876
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.566435376
Short name T21
Test name
Test status
Simulation time 66241106039 ps
CPU time 600.19 seconds
Started Mar 10 12:23:30 PM PDT 24
Finished Mar 10 12:33:30 PM PDT 24
Peak memory 199224 kb
Host smart-8ad222eb-9cb8-4e1d-b34f-14187d532410
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566435376 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.566435376
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_jump.1338485950
Short name T135
Test name
Test status
Simulation time 436529188 ps
CPU time 1.18 seconds
Started Mar 10 12:23:19 PM PDT 24
Finished Mar 10 12:23:20 PM PDT 24
Peak memory 183760 kb
Host smart-6204671a-104b-4e3e-a6e5-117f839501f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338485950 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.1338485950
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.389727129
Short name T118
Test name
Test status
Simulation time 14769997935 ps
CPU time 2.31 seconds
Started Mar 10 12:23:19 PM PDT 24
Finished Mar 10 12:23:22 PM PDT 24
Peak memory 183896 kb
Host smart-44f008b8-a486-4744-9334-0fc341bce5dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389727129 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.389727129
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.1956904524
Short name T17
Test name
Test status
Simulation time 4032806723 ps
CPU time 6.93 seconds
Started Mar 10 12:23:57 PM PDT 24
Finished Mar 10 12:24:04 PM PDT 24
Peak memory 214128 kb
Host smart-ef2c3b25-d8c2-4543-80be-6d7624df2a39
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956904524 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.1956904524
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.2822123078
Short name T51
Test name
Test status
Simulation time 580093476 ps
CPU time 0.68 seconds
Started Mar 10 12:33:54 PM PDT 24
Finished Mar 10 12:33:55 PM PDT 24
Peak memory 183784 kb
Host smart-1588ebfe-08af-4429-bb34-fd2fcf5d60c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822123078 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.2822123078
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.1524844098
Short name T89
Test name
Test status
Simulation time 36758696698 ps
CPU time 13.35 seconds
Started Mar 10 12:33:48 PM PDT 24
Finished Mar 10 12:34:01 PM PDT 24
Peak memory 195520 kb
Host smart-69075d5a-adae-42b7-aa2d-eeb4c80b639f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524844098 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_a
ll.1524844098
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.13548518
Short name T248
Test name
Test status
Simulation time 82495384156 ps
CPU time 443.6 seconds
Started Mar 10 12:23:18 PM PDT 24
Finished Mar 10 12:30:42 PM PDT 24
Peak memory 198756 kb
Host smart-e6b6e480-46b1-4863-91f0-8bcfa04e13da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13548518 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.13548518
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.aon_timer_jump.3222697156
Short name T267
Test name
Test status
Simulation time 459012788 ps
CPU time 1.26 seconds
Started Mar 10 12:23:18 PM PDT 24
Finished Mar 10 12:23:20 PM PDT 24
Peak memory 183832 kb
Host smart-99e1fd69-ad8d-466a-bb0b-068de45629c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222697156 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.3222697156
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.1593252763
Short name T91
Test name
Test status
Simulation time 16166461142 ps
CPU time 6.88 seconds
Started Mar 10 12:23:16 PM PDT 24
Finished Mar 10 12:23:23 PM PDT 24
Peak memory 192144 kb
Host smart-b0024c3f-1e2d-4b86-b7ec-6746827489b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593252763 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.1593252763
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.3390209648
Short name T76
Test name
Test status
Simulation time 390132362 ps
CPU time 0.69 seconds
Started Mar 10 12:23:16 PM PDT 24
Finished Mar 10 12:23:17 PM PDT 24
Peak memory 183832 kb
Host smart-3de78960-ed38-4088-877a-bacf716d2c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390209648 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.3390209648
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.103037602
Short name T45
Test name
Test status
Simulation time 133449941300 ps
CPU time 90.93 seconds
Started Mar 10 12:23:16 PM PDT 24
Finished Mar 10 12:24:48 PM PDT 24
Peak memory 183948 kb
Host smart-a147d417-6642-4e52-92c9-48575a8bd3cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103037602 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_a
ll.103037602
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.2527425636
Short name T244
Test name
Test status
Simulation time 167101617124 ps
CPU time 445.78 seconds
Started Mar 10 12:23:25 PM PDT 24
Finished Mar 10 12:30:51 PM PDT 24
Peak memory 198912 kb
Host smart-a8cb62cf-414b-47d6-b650-9b3e33612c5b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527425636 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.2527425636
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_jump.3858516876
Short name T240
Test name
Test status
Simulation time 570444927 ps
CPU time 1.28 seconds
Started Mar 10 12:24:05 PM PDT 24
Finished Mar 10 12:24:06 PM PDT 24
Peak memory 183756 kb
Host smart-f37b9e5c-6a33-4bf8-bf95-bd68d6170bea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858516876 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.3858516876
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.569455937
Short name T274
Test name
Test status
Simulation time 12476997751 ps
CPU time 16.41 seconds
Started Mar 10 12:23:16 PM PDT 24
Finished Mar 10 12:23:32 PM PDT 24
Peak memory 192140 kb
Host smart-510ddf31-509c-4a43-8ec7-d9088df19a47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569455937 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.569455937
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.593175147
Short name T219
Test name
Test status
Simulation time 423240760 ps
CPU time 0.72 seconds
Started Mar 10 12:23:55 PM PDT 24
Finished Mar 10 12:23:56 PM PDT 24
Peak memory 183732 kb
Host smart-d0c95258-320a-4c55-9930-b1271475b0d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593175147 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.593175147
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.3468327634
Short name T107
Test name
Test status
Simulation time 90478413122 ps
CPU time 31.42 seconds
Started Mar 10 12:23:14 PM PDT 24
Finished Mar 10 12:23:47 PM PDT 24
Peak memory 194320 kb
Host smart-7c548a08-9963-4390-abf4-51a073858b3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468327634 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_
all.3468327634
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_jump.56593495
Short name T203
Test name
Test status
Simulation time 560955738 ps
CPU time 1.4 seconds
Started Mar 10 12:23:15 PM PDT 24
Finished Mar 10 12:23:17 PM PDT 24
Peak memory 184220 kb
Host smart-e743d471-0e55-40dd-9588-10ff85e57dbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56593495 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.56593495
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.3494933596
Short name T171
Test name
Test status
Simulation time 5617304359 ps
CPU time 9.84 seconds
Started Mar 10 12:23:25 PM PDT 24
Finished Mar 10 12:23:35 PM PDT 24
Peak memory 192252 kb
Host smart-62d0f70e-cff6-446c-b4d2-bd8d4e45f45f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494933596 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.3494933596
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.33621671
Short name T279
Test name
Test status
Simulation time 522987047 ps
CPU time 1.31 seconds
Started Mar 10 12:23:25 PM PDT 24
Finished Mar 10 12:23:27 PM PDT 24
Peak memory 183928 kb
Host smart-a1a5fbfe-d738-4adb-b099-6e44c1d1c34b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33621671 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.33621671
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.564141895
Short name T204
Test name
Test status
Simulation time 193277132455 ps
CPU time 71.94 seconds
Started Mar 10 12:23:55 PM PDT 24
Finished Mar 10 12:25:07 PM PDT 24
Peak memory 183860 kb
Host smart-f0deccb9-68e2-44fe-83c9-e3788dcb877c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564141895 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_a
ll.564141895
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.3008036059
Short name T83
Test name
Test status
Simulation time 73461303989 ps
CPU time 147.66 seconds
Started Mar 10 12:23:25 PM PDT 24
Finished Mar 10 12:25:53 PM PDT 24
Peak memory 198924 kb
Host smart-4573bafb-2843-402e-8a28-5edaa9dbc6ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008036059 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.3008036059
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.aon_timer_jump.1334494131
Short name T258
Test name
Test status
Simulation time 583318894 ps
CPU time 1.33 seconds
Started Mar 10 12:23:25 PM PDT 24
Finished Mar 10 12:23:26 PM PDT 24
Peak memory 184020 kb
Host smart-3441289a-3bd4-4027-97dc-ba3a81fb3828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334494131 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.1334494131
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.2153361651
Short name T246
Test name
Test status
Simulation time 14379122509 ps
CPU time 2.53 seconds
Started Mar 10 12:23:23 PM PDT 24
Finished Mar 10 12:23:26 PM PDT 24
Peak memory 183952 kb
Host smart-849c8944-6bd8-4122-87e9-ad73549fc158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153361651 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.2153361651
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.2537362574
Short name T48
Test name
Test status
Simulation time 475697573 ps
CPU time 1.32 seconds
Started Mar 10 12:23:22 PM PDT 24
Finished Mar 10 12:23:23 PM PDT 24
Peak memory 183824 kb
Host smart-631367ba-23e6-4207-b34b-3b3672108b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537362574 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.2537362574
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.3363428229
Short name T19
Test name
Test status
Simulation time 199547359760 ps
CPU time 145.25 seconds
Started Mar 10 12:23:27 PM PDT 24
Finished Mar 10 12:25:53 PM PDT 24
Peak memory 183972 kb
Host smart-abd0cd0e-d8ad-4305-9ddd-b878d8a90282
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363428229 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_
all.3363428229
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.3028905347
Short name T228
Test name
Test status
Simulation time 177480537951 ps
CPU time 544.9 seconds
Started Mar 10 12:23:34 PM PDT 24
Finished Mar 10 12:32:40 PM PDT 24
Peak memory 199444 kb
Host smart-0dabff0e-fc73-41a4-b31e-0ea7e0f9ffec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028905347 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.3028905347
Directory /workspace/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.aon_timer_jump.1716965599
Short name T245
Test name
Test status
Simulation time 594719946 ps
CPU time 1.48 seconds
Started Mar 10 12:23:23 PM PDT 24
Finished Mar 10 12:23:24 PM PDT 24
Peak memory 183816 kb
Host smart-4d3a1a59-2844-4abb-bf58-985a99d12405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716965599 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.1716965599
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.3926616974
Short name T224
Test name
Test status
Simulation time 18491200117 ps
CPU time 10.42 seconds
Started Mar 10 12:23:27 PM PDT 24
Finished Mar 10 12:23:38 PM PDT 24
Peak memory 183876 kb
Host smart-f2878ac7-2f57-475e-b8dc-effddbd72fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926616974 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.3926616974
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.4147986219
Short name T108
Test name
Test status
Simulation time 588449119 ps
CPU time 1.38 seconds
Started Mar 10 12:23:32 PM PDT 24
Finished Mar 10 12:23:34 PM PDT 24
Peak memory 183848 kb
Host smart-3ad53da9-5cb3-4b0c-9b78-442670fc3c74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147986219 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.4147986219
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.2333164756
Short name T88
Test name
Test status
Simulation time 88629711610 ps
CPU time 27.42 seconds
Started Mar 10 12:23:27 PM PDT 24
Finished Mar 10 12:23:54 PM PDT 24
Peak memory 195864 kb
Host smart-e3f8e4f8-acc3-42a3-8ec6-5b60569e5934
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333164756 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_
all.2333164756
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.655997252
Short name T234
Test name
Test status
Simulation time 763453993041 ps
CPU time 751.49 seconds
Started Mar 10 12:23:22 PM PDT 24
Finished Mar 10 12:35:54 PM PDT 24
Peak memory 202416 kb
Host smart-39ab93c3-5a9a-44e7-802b-5c72172833a0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655997252 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand_reset.655997252
Directory /workspace/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.aon_timer_jump.1570184897
Short name T169
Test name
Test status
Simulation time 466356420 ps
CPU time 1.18 seconds
Started Mar 10 12:23:30 PM PDT 24
Finished Mar 10 12:23:31 PM PDT 24
Peak memory 183804 kb
Host smart-3d504bad-ba35-4a0c-a458-7e19ca56ddac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570184897 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.1570184897
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.1795718579
Short name T280
Test name
Test status
Simulation time 40678782033 ps
CPU time 6.77 seconds
Started Mar 10 12:23:30 PM PDT 24
Finished Mar 10 12:23:38 PM PDT 24
Peak memory 183912 kb
Host smart-3e882ba4-4bf8-47e0-adfb-99b64e1f8a56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795718579 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.1795718579
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.4166328297
Short name T131
Test name
Test status
Simulation time 326086064 ps
CPU time 1 seconds
Started Mar 10 12:23:29 PM PDT 24
Finished Mar 10 12:23:31 PM PDT 24
Peak memory 183800 kb
Host smart-8014bc41-5d3a-4719-9153-1bb5eb49d7ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166328297 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.4166328297
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.925428441
Short name T104
Test name
Test status
Simulation time 119260666539 ps
CPU time 170.21 seconds
Started Mar 10 12:23:28 PM PDT 24
Finished Mar 10 12:26:19 PM PDT 24
Peak memory 194436 kb
Host smart-9f88e849-f9b3-4bbb-b02a-ddcfbc52c520
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925428441 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_a
ll.925428441
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.1797776288
Short name T82
Test name
Test status
Simulation time 274757643274 ps
CPU time 292.84 seconds
Started Mar 10 12:23:31 PM PDT 24
Finished Mar 10 12:28:24 PM PDT 24
Peak memory 198788 kb
Host smart-d3d15508-2df9-409d-81b9-e116a4fac597
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797776288 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.1797776288
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.aon_timer_jump.3583854906
Short name T208
Test name
Test status
Simulation time 395600831 ps
CPU time 0.7 seconds
Started Mar 10 12:23:51 PM PDT 24
Finished Mar 10 12:23:52 PM PDT 24
Peak memory 183760 kb
Host smart-390e4166-6d48-402f-a6e8-5bc99728d285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583854906 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.3583854906
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.1836159026
Short name T220
Test name
Test status
Simulation time 38011628817 ps
CPU time 60.69 seconds
Started Mar 10 12:23:32 PM PDT 24
Finished Mar 10 12:24:33 PM PDT 24
Peak memory 183924 kb
Host smart-de963ba2-0883-4b71-9c4a-ceefc1f6b29b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836159026 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.1836159026
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.1959957218
Short name T46
Test name
Test status
Simulation time 432479754 ps
CPU time 0.69 seconds
Started Mar 10 12:23:31 PM PDT 24
Finished Mar 10 12:23:32 PM PDT 24
Peak memory 183848 kb
Host smart-3a379bbe-02ad-4f2a-addc-36df7bee8ee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959957218 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.1959957218
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_jump.2189113115
Short name T202
Test name
Test status
Simulation time 560053185 ps
CPU time 1.47 seconds
Started Mar 10 12:23:40 PM PDT 24
Finished Mar 10 12:23:42 PM PDT 24
Peak memory 183836 kb
Host smart-4b13f41f-9da3-4682-adaa-9da6ff4db006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189113115 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.2189113115
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.3051394315
Short name T190
Test name
Test status
Simulation time 30126897327 ps
CPU time 24.43 seconds
Started Mar 10 12:23:40 PM PDT 24
Finished Mar 10 12:24:05 PM PDT 24
Peak memory 183952 kb
Host smart-c087e10d-2172-4db7-a4fc-74f3e2a31a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051394315 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.3051394315
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.3661769816
Short name T20
Test name
Test status
Simulation time 477537569 ps
CPU time 1.1 seconds
Started Mar 10 12:23:51 PM PDT 24
Finished Mar 10 12:23:52 PM PDT 24
Peak memory 183764 kb
Host smart-b6a60395-c494-4917-abcc-0ab40b0f17b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661769816 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.3661769816
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.1436291744
Short name T145
Test name
Test status
Simulation time 105278472816 ps
CPU time 47.97 seconds
Started Mar 10 12:23:50 PM PDT 24
Finished Mar 10 12:24:38 PM PDT 24
Peak memory 193292 kb
Host smart-4f04f07a-408e-4c20-9b2d-e8b808984de4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436291744 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_
all.1436291744
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.3511064641
Short name T41
Test name
Test status
Simulation time 21969672291 ps
CPU time 160.73 seconds
Started Mar 10 12:23:44 PM PDT 24
Finished Mar 10 12:26:26 PM PDT 24
Peak memory 198524 kb
Host smart-b421ed77-31c9-4389-9c3c-b51485d3935e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511064641 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.3511064641
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_jump.3768401168
Short name T195
Test name
Test status
Simulation time 497247088 ps
CPU time 1.3 seconds
Started Mar 10 12:24:03 PM PDT 24
Finished Mar 10 12:24:04 PM PDT 24
Peak memory 183792 kb
Host smart-4abd1da0-8b9b-4229-9981-76b992320a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768401168 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.3768401168
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.3599270303
Short name T207
Test name
Test status
Simulation time 4338029264 ps
CPU time 6.42 seconds
Started Mar 10 12:23:51 PM PDT 24
Finished Mar 10 12:23:57 PM PDT 24
Peak memory 183880 kb
Host smart-dc2144c1-817a-448c-a042-a17ef6a24d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599270303 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.3599270303
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.2566958203
Short name T255
Test name
Test status
Simulation time 401035264 ps
CPU time 1.1 seconds
Started Mar 10 12:23:43 PM PDT 24
Finished Mar 10 12:23:46 PM PDT 24
Peak memory 183760 kb
Host smart-290e48e0-74d7-4345-8692-f69e3c586b6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566958203 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.2566958203
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.2116297986
Short name T199
Test name
Test status
Simulation time 199071445853 ps
CPU time 76.79 seconds
Started Mar 10 12:23:31 PM PDT 24
Finished Mar 10 12:24:48 PM PDT 24
Peak memory 195468 kb
Host smart-53b89bce-26ca-4f45-8c90-3c610ea2277c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116297986 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_
all.2116297986
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/29.aon_timer_jump.1613854293
Short name T156
Test name
Test status
Simulation time 579144344 ps
CPU time 1.55 seconds
Started Mar 10 12:23:40 PM PDT 24
Finished Mar 10 12:23:42 PM PDT 24
Peak memory 183836 kb
Host smart-a148d85f-2c62-480a-9995-fc52dd9a3e6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613854293 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.1613854293
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.2502048045
Short name T85
Test name
Test status
Simulation time 36460413504 ps
CPU time 52.39 seconds
Started Mar 10 12:23:40 PM PDT 24
Finished Mar 10 12:24:33 PM PDT 24
Peak memory 183924 kb
Host smart-e3bc7bc5-ee80-49fe-ab16-1e067ba54cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502048045 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.2502048045
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.252108329
Short name T201
Test name
Test status
Simulation time 456786728 ps
CPU time 1.11 seconds
Started Mar 10 12:24:10 PM PDT 24
Finished Mar 10 12:24:11 PM PDT 24
Peak memory 183796 kb
Host smart-74a20cfa-545b-4dfe-995f-8be375bfd2df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252108329 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.252108329
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.3953373353
Short name T269
Test name
Test status
Simulation time 64320091513 ps
CPU time 623.68 seconds
Started Mar 10 12:23:40 PM PDT 24
Finished Mar 10 12:34:04 PM PDT 24
Peak memory 198904 kb
Host smart-4cb9d02b-6ccb-468a-af6d-0d47105bd384
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953373353 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.3953373353
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.aon_timer_jump.2891536008
Short name T176
Test name
Test status
Simulation time 543634557 ps
CPU time 1.36 seconds
Started Mar 10 12:21:38 PM PDT 24
Finished Mar 10 12:21:40 PM PDT 24
Peak memory 183764 kb
Host smart-59ceef5a-2f6a-4b94-9ece-fa362827bc40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891536008 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.2891536008
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.2325723177
Short name T114
Test name
Test status
Simulation time 49133984710 ps
CPU time 74.42 seconds
Started Mar 10 12:33:53 PM PDT 24
Finished Mar 10 12:35:08 PM PDT 24
Peak memory 183924 kb
Host smart-697dec80-0131-4855-8177-d63a49675b10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325723177 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.2325723177
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.1353742872
Short name T14
Test name
Test status
Simulation time 7535304729 ps
CPU time 11.88 seconds
Started Mar 10 12:21:29 PM PDT 24
Finished Mar 10 12:21:41 PM PDT 24
Peak memory 215696 kb
Host smart-1970b05f-3b1d-4241-a4ce-fe2b2480f6cf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353742872 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.1353742872
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.194528400
Short name T181
Test name
Test status
Simulation time 565110669 ps
CPU time 0.66 seconds
Started Mar 10 12:32:22 PM PDT 24
Finished Mar 10 12:32:23 PM PDT 24
Peak memory 183784 kb
Host smart-b646b6ed-11b7-4e03-8c62-31d33d94a512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194528400 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.194528400
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.3602044476
Short name T275
Test name
Test status
Simulation time 203051089607 ps
CPU time 156.99 seconds
Started Mar 10 12:21:05 PM PDT 24
Finished Mar 10 12:23:42 PM PDT 24
Peak memory 195780 kb
Host smart-60e8c004-4767-4ff1-b812-07fc9f17f80a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602044476 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_a
ll.3602044476
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.3884976370
Short name T79
Test name
Test status
Simulation time 155171330213 ps
CPU time 366.09 seconds
Started Mar 10 12:22:54 PM PDT 24
Finished Mar 10 12:29:00 PM PDT 24
Peak memory 198752 kb
Host smart-53750d29-3b5a-4f43-911c-7644492b18e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884976370 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.3884976370
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_jump.3486211451
Short name T222
Test name
Test status
Simulation time 410850570 ps
CPU time 0.69 seconds
Started Mar 10 12:23:39 PM PDT 24
Finished Mar 10 12:23:40 PM PDT 24
Peak memory 183820 kb
Host smart-11538ccd-e416-4150-aea3-02981c749fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486211451 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.3486211451
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.1466017998
Short name T239
Test name
Test status
Simulation time 3735222667 ps
CPU time 1.84 seconds
Started Mar 10 12:23:35 PM PDT 24
Finished Mar 10 12:23:37 PM PDT 24
Peak memory 183944 kb
Host smart-d2d3c3f1-f8ae-4564-979d-308d0fc2cc33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466017998 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.1466017998
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.2150542260
Short name T128
Test name
Test status
Simulation time 392411030 ps
CPU time 0.74 seconds
Started Mar 10 12:23:35 PM PDT 24
Finished Mar 10 12:23:36 PM PDT 24
Peak memory 183816 kb
Host smart-ec712cbc-b44b-4d4a-961b-58155cd65e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150542260 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.2150542260
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.39229270
Short name T4
Test name
Test status
Simulation time 78242092155 ps
CPU time 124.98 seconds
Started Mar 10 12:23:49 PM PDT 24
Finished Mar 10 12:25:54 PM PDT 24
Peak memory 195468 kb
Host smart-d523e089-7e88-4141-88e1-96d8a6163485
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39229270 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_al
l.39229270
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.23830229
Short name T92
Test name
Test status
Simulation time 1042827119923 ps
CPU time 934.98 seconds
Started Mar 10 12:23:49 PM PDT 24
Finished Mar 10 12:39:24 PM PDT 24
Peak memory 204292 kb
Host smart-05004a5d-9284-4532-804a-c7c2d0d87556
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23830229 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.23830229
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.aon_timer_jump.17930023
Short name T223
Test name
Test status
Simulation time 551281278 ps
CPU time 0.57 seconds
Started Mar 10 12:23:44 PM PDT 24
Finished Mar 10 12:23:45 PM PDT 24
Peak memory 183844 kb
Host smart-b801496a-8bfb-4fde-a305-1dde5661697c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17930023 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.17930023
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.1750204126
Short name T193
Test name
Test status
Simulation time 18335555036 ps
CPU time 28.71 seconds
Started Mar 10 12:23:44 PM PDT 24
Finished Mar 10 12:24:14 PM PDT 24
Peak memory 183964 kb
Host smart-32566a32-781d-4840-b80d-c1f55963fd54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750204126 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.1750204126
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.943140292
Short name T151
Test name
Test status
Simulation time 356657140 ps
CPU time 0.79 seconds
Started Mar 10 12:23:51 PM PDT 24
Finished Mar 10 12:23:52 PM PDT 24
Peak memory 183760 kb
Host smart-aa3e3097-b099-4bf5-84b8-b13ca8eef625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943140292 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.943140292
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.1936099960
Short name T256
Test name
Test status
Simulation time 135570852431 ps
CPU time 18.44 seconds
Started Mar 10 12:23:44 PM PDT 24
Finished Mar 10 12:24:03 PM PDT 24
Peak memory 183964 kb
Host smart-e71cbc3a-0fba-4227-8061-b1d552b6e32d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936099960 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_
all.1936099960
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.4223696244
Short name T252
Test name
Test status
Simulation time 122147539067 ps
CPU time 296.26 seconds
Started Mar 10 12:24:03 PM PDT 24
Finished Mar 10 12:29:00 PM PDT 24
Peak memory 198736 kb
Host smart-93e93d9f-3c8d-4091-98d8-e61f1fef9bff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223696244 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.4223696244
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.aon_timer_jump.1292124642
Short name T243
Test name
Test status
Simulation time 413192960 ps
CPU time 0.75 seconds
Started Mar 10 12:24:03 PM PDT 24
Finished Mar 10 12:24:04 PM PDT 24
Peak memory 183792 kb
Host smart-6cc386a0-2892-4dbe-ac50-fb211d01362b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292124642 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.1292124642
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.1783925624
Short name T159
Test name
Test status
Simulation time 14606616088 ps
CPU time 22.9 seconds
Started Mar 10 12:23:30 PM PDT 24
Finished Mar 10 12:23:53 PM PDT 24
Peak memory 183860 kb
Host smart-67e45230-552b-4341-a17a-d364c81f4fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783925624 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.1783925624
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.2396502593
Short name T277
Test name
Test status
Simulation time 362086989 ps
CPU time 0.72 seconds
Started Mar 10 12:24:03 PM PDT 24
Finished Mar 10 12:24:04 PM PDT 24
Peak memory 183792 kb
Host smart-36e2a9e2-c7f3-4f19-a979-4199241db7b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396502593 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.2396502593
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.3130343140
Short name T2
Test name
Test status
Simulation time 65885704879 ps
CPU time 44.1 seconds
Started Mar 10 12:23:49 PM PDT 24
Finished Mar 10 12:24:33 PM PDT 24
Peak memory 183880 kb
Host smart-59d6ef15-7c27-470b-bc1e-25ff6f463fe9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130343140 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_
all.3130343140
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.3792931922
Short name T39
Test name
Test status
Simulation time 404393008307 ps
CPU time 725.84 seconds
Started Mar 10 12:23:35 PM PDT 24
Finished Mar 10 12:35:41 PM PDT 24
Peak memory 201180 kb
Host smart-8b8bf730-2f06-45d3-9a98-88045090a1da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792931922 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_reset.3792931922
Directory /workspace/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.aon_timer_jump.806958317
Short name T134
Test name
Test status
Simulation time 518771256 ps
CPU time 0.73 seconds
Started Mar 10 12:23:49 PM PDT 24
Finished Mar 10 12:23:49 PM PDT 24
Peak memory 183812 kb
Host smart-840faac4-5ede-4af0-a3f7-3f4d5fee9781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806958317 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.806958317
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.871387789
Short name T227
Test name
Test status
Simulation time 37313374065 ps
CPU time 12.81 seconds
Started Mar 10 12:23:44 PM PDT 24
Finished Mar 10 12:23:58 PM PDT 24
Peak memory 183960 kb
Host smart-4a0c047c-ea90-499d-869e-43da72f25527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871387789 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.871387789
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.907327085
Short name T162
Test name
Test status
Simulation time 570333139 ps
CPU time 1.41 seconds
Started Mar 10 12:23:51 PM PDT 24
Finished Mar 10 12:23:52 PM PDT 24
Peak memory 183760 kb
Host smart-f9f20bfc-3fc8-4ae8-ba63-4139f9f91872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907327085 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.907327085
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_jump.2238993286
Short name T247
Test name
Test status
Simulation time 401430512 ps
CPU time 0.69 seconds
Started Mar 10 12:23:41 PM PDT 24
Finished Mar 10 12:23:42 PM PDT 24
Peak memory 183804 kb
Host smart-6fb7e253-c41a-446a-af34-ef726a17c480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238993286 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.2238993286
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.2678483526
Short name T182
Test name
Test status
Simulation time 36363507598 ps
CPU time 55.22 seconds
Started Mar 10 12:24:08 PM PDT 24
Finished Mar 10 12:25:03 PM PDT 24
Peak memory 183856 kb
Host smart-6f255eb2-7fca-41f6-8ee4-9c6d2737af2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678483526 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.2678483526
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.3295550815
Short name T262
Test name
Test status
Simulation time 619772311 ps
CPU time 0.81 seconds
Started Mar 10 12:23:45 PM PDT 24
Finished Mar 10 12:23:46 PM PDT 24
Peak memory 183840 kb
Host smart-3749237c-6d5e-430b-911e-f1892d0ad80a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295550815 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.3295550815
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.2688594593
Short name T187
Test name
Test status
Simulation time 30556698854 ps
CPU time 46.34 seconds
Started Mar 10 12:23:44 PM PDT 24
Finished Mar 10 12:24:31 PM PDT 24
Peak memory 183676 kb
Host smart-dd59f8b4-78db-4903-9a5a-3a79ab4db9f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688594593 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_
all.2688594593
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.4156592267
Short name T56
Test name
Test status
Simulation time 848971516769 ps
CPU time 557.13 seconds
Started Mar 10 12:23:44 PM PDT 24
Finished Mar 10 12:33:02 PM PDT 24
Peak memory 199360 kb
Host smart-e2b0a0e4-76e3-4b0b-b306-bc64404dc6ab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156592267 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.4156592267
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.aon_timer_jump.630711939
Short name T12
Test name
Test status
Simulation time 483979538 ps
CPU time 0.72 seconds
Started Mar 10 12:23:37 PM PDT 24
Finished Mar 10 12:23:38 PM PDT 24
Peak memory 183700 kb
Host smart-b7abd402-bec7-4bda-b85b-55f02f2c37d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630711939 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.630711939
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.712444113
Short name T231
Test name
Test status
Simulation time 29490737478 ps
CPU time 46.77 seconds
Started Mar 10 12:24:20 PM PDT 24
Finished Mar 10 12:25:06 PM PDT 24
Peak memory 183916 kb
Host smart-c3663f3d-eba1-4744-93eb-013a90ae2697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712444113 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.712444113
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.2245553420
Short name T33
Test name
Test status
Simulation time 637483548 ps
CPU time 0.61 seconds
Started Mar 10 12:23:39 PM PDT 24
Finished Mar 10 12:23:40 PM PDT 24
Peak memory 183832 kb
Host smart-d88e7832-0251-4482-917d-534336b3690b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245553420 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.2245553420
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.3032657442
Short name T196
Test name
Test status
Simulation time 125129244614 ps
CPU time 45.23 seconds
Started Mar 10 12:23:45 PM PDT 24
Finished Mar 10 12:24:30 PM PDT 24
Peak memory 183972 kb
Host smart-32fdbc83-6101-4307-8139-933e5e5e4631
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032657442 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_
all.3032657442
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.886169153
Short name T55
Test name
Test status
Simulation time 162221149769 ps
CPU time 423.08 seconds
Started Mar 10 12:23:47 PM PDT 24
Finished Mar 10 12:30:51 PM PDT 24
Peak memory 198708 kb
Host smart-facf8217-2769-41fa-8ce8-c7e220d52c4f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886169153 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.886169153
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.aon_timer_jump.720240083
Short name T185
Test name
Test status
Simulation time 513807994 ps
CPU time 1.01 seconds
Started Mar 10 12:24:48 PM PDT 24
Finished Mar 10 12:24:50 PM PDT 24
Peak memory 183808 kb
Host smart-22c5e87c-3cc7-4e0c-890d-b2d30af3504d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720240083 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.720240083
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.2317418086
Short name T8
Test name
Test status
Simulation time 12031093279 ps
CPU time 18.87 seconds
Started Mar 10 12:23:51 PM PDT 24
Finished Mar 10 12:24:10 PM PDT 24
Peak memory 183928 kb
Host smart-c58b26cd-18c1-4cf0-9e4d-b8b05aa10739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317418086 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.2317418086
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.2759502688
Short name T211
Test name
Test status
Simulation time 439754729 ps
CPU time 0.88 seconds
Started Mar 10 12:23:47 PM PDT 24
Finished Mar 10 12:23:48 PM PDT 24
Peak memory 183768 kb
Host smart-b5807b9b-2615-4d1c-9ffd-f5890314ebf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759502688 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.2759502688
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.1494092365
Short name T122
Test name
Test status
Simulation time 192941257150 ps
CPU time 219.7 seconds
Started Mar 10 12:23:51 PM PDT 24
Finished Mar 10 12:27:31 PM PDT 24
Peak memory 195364 kb
Host smart-907a1124-bde5-4938-98c7-049ed3ada899
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494092365 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_
all.1494092365
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_jump.8968607
Short name T146
Test name
Test status
Simulation time 442416362 ps
CPU time 1.18 seconds
Started Mar 10 12:23:54 PM PDT 24
Finished Mar 10 12:23:56 PM PDT 24
Peak memory 183836 kb
Host smart-75166b20-5658-4027-be74-421efe8631f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8968607 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.8968607
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.2196232687
Short name T212
Test name
Test status
Simulation time 5272604947 ps
CPU time 4.33 seconds
Started Mar 10 12:23:52 PM PDT 24
Finished Mar 10 12:23:57 PM PDT 24
Peak memory 183928 kb
Host smart-bc7d4633-ebd5-423b-812e-553b8ee369e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196232687 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.2196232687
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.1779669815
Short name T132
Test name
Test status
Simulation time 582189915 ps
CPU time 0.61 seconds
Started Mar 10 12:23:50 PM PDT 24
Finished Mar 10 12:23:50 PM PDT 24
Peak memory 183832 kb
Host smart-37581504-d5a7-4776-a770-68d0787aae7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779669815 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.1779669815
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.2632703208
Short name T266
Test name
Test status
Simulation time 4942817933 ps
CPU time 3.21 seconds
Started Mar 10 12:24:03 PM PDT 24
Finished Mar 10 12:24:06 PM PDT 24
Peak memory 183912 kb
Host smart-f60509d0-911b-4e1e-817e-32d9bdd3f3f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632703208 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_
all.2632703208
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.749968620
Short name T58
Test name
Test status
Simulation time 49767155649 ps
CPU time 347.18 seconds
Started Mar 10 12:23:51 PM PDT 24
Finished Mar 10 12:29:38 PM PDT 24
Peak memory 198872 kb
Host smart-d1a876b5-f6c8-4fa7-990a-940abbdfccdf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749968620 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.749968620
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.aon_timer_jump.340507226
Short name T226
Test name
Test status
Simulation time 590317813 ps
CPU time 0.75 seconds
Started Mar 10 12:23:52 PM PDT 24
Finished Mar 10 12:23:53 PM PDT 24
Peak memory 183812 kb
Host smart-63042c3b-133b-4822-b5d4-90fb02b5f8bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340507226 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.340507226
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.3504648173
Short name T123
Test name
Test status
Simulation time 26230197092 ps
CPU time 11.57 seconds
Started Mar 10 12:23:47 PM PDT 24
Finished Mar 10 12:23:59 PM PDT 24
Peak memory 192012 kb
Host smart-1fa7d0b2-6384-40c4-859a-c4d38d61b3bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504648173 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.3504648173
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.1254490883
Short name T192
Test name
Test status
Simulation time 403235441 ps
CPU time 0.72 seconds
Started Mar 10 12:23:50 PM PDT 24
Finished Mar 10 12:23:51 PM PDT 24
Peak memory 183936 kb
Host smart-db0d5ce5-30d3-49a1-bbd0-6c115f1317f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254490883 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.1254490883
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.133642271
Short name T78
Test name
Test status
Simulation time 148361580978 ps
CPU time 440.97 seconds
Started Mar 10 12:23:54 PM PDT 24
Finished Mar 10 12:31:15 PM PDT 24
Peak memory 198772 kb
Host smart-d97bb8a7-3d27-4c60-b366-fc5007c9b81e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133642271 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand_reset.133642271
Directory /workspace/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.aon_timer_jump.2753863241
Short name T105
Test name
Test status
Simulation time 463736653 ps
CPU time 0.94 seconds
Started Mar 10 12:24:05 PM PDT 24
Finished Mar 10 12:24:06 PM PDT 24
Peak memory 183760 kb
Host smart-94210e11-aff1-441c-b6e5-201ad6744e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753863241 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.2753863241
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.4272588109
Short name T179
Test name
Test status
Simulation time 7015456181 ps
CPU time 4.75 seconds
Started Mar 10 12:23:47 PM PDT 24
Finished Mar 10 12:23:52 PM PDT 24
Peak memory 192012 kb
Host smart-36f98894-827f-498e-a752-9f577691bed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272588109 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.4272588109
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.1150857695
Short name T130
Test name
Test status
Simulation time 603501170 ps
CPU time 0.67 seconds
Started Mar 10 12:23:47 PM PDT 24
Finished Mar 10 12:23:48 PM PDT 24
Peak memory 183708 kb
Host smart-2b8f7424-6b22-4eb3-8c1c-4c9c7bc5f5e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150857695 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.1150857695
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.1301593955
Short name T120
Test name
Test status
Simulation time 118589446616 ps
CPU time 125.76 seconds
Started Mar 10 12:24:05 PM PDT 24
Finished Mar 10 12:26:11 PM PDT 24
Peak memory 183880 kb
Host smart-6feb9972-d8df-44ea-8d5f-b8adaa61aa27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301593955 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_
all.1301593955
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.2093932246
Short name T149
Test name
Test status
Simulation time 25034072466 ps
CPU time 246.45 seconds
Started Mar 10 12:23:52 PM PDT 24
Finished Mar 10 12:27:59 PM PDT 24
Peak memory 198744 kb
Host smart-1d98fd4e-c30e-4537-a0b4-ac6f1d1d32a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093932246 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.2093932246
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_jump.1794324625
Short name T150
Test name
Test status
Simulation time 404183391 ps
CPU time 1.22 seconds
Started Mar 10 12:24:43 PM PDT 24
Finished Mar 10 12:24:45 PM PDT 24
Peak memory 183680 kb
Host smart-ab0909fb-b04f-4d98-81e1-ac3fede642c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794324625 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.1794324625
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.906878751
Short name T53
Test name
Test status
Simulation time 18511263304 ps
CPU time 28.9 seconds
Started Mar 10 12:24:06 PM PDT 24
Finished Mar 10 12:24:35 PM PDT 24
Peak memory 182772 kb
Host smart-d1d83028-65cb-4f71-a4cc-5c1ab089d054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906878751 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.906878751
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.2040000308
Short name T13
Test name
Test status
Simulation time 8246136749 ps
CPU time 1.45 seconds
Started Mar 10 12:24:23 PM PDT 24
Finished Mar 10 12:24:24 PM PDT 24
Peak memory 215620 kb
Host smart-6569c7da-2fcc-4f9f-a43b-bd3ccdf5c40e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040000308 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.2040000308
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.2871160886
Short name T254
Test name
Test status
Simulation time 456220083 ps
CPU time 1.56 seconds
Started Mar 10 12:20:31 PM PDT 24
Finished Mar 10 12:20:32 PM PDT 24
Peak memory 183752 kb
Host smart-afddda3a-9240-426b-b836-270e2d9b9f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871160886 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.2871160886
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.3804688623
Short name T50
Test name
Test status
Simulation time 106895996971 ps
CPU time 128.18 seconds
Started Mar 10 12:23:18 PM PDT 24
Finished Mar 10 12:25:27 PM PDT 24
Peak memory 195392 kb
Host smart-8f7ca4b2-6f69-44eb-bb74-f7bbdaab5540
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804688623 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_a
ll.3804688623
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.628050788
Short name T81
Test name
Test status
Simulation time 99863919429 ps
CPU time 369.71 seconds
Started Mar 10 12:20:48 PM PDT 24
Finished Mar 10 12:26:59 PM PDT 24
Peak memory 198752 kb
Host smart-18b03f78-42df-4306-b73d-8af642ba7524
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628050788 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.628050788
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.aon_timer_jump.4235973124
Short name T235
Test name
Test status
Simulation time 534367736 ps
CPU time 1.24 seconds
Started Mar 10 12:23:43 PM PDT 24
Finished Mar 10 12:23:45 PM PDT 24
Peak memory 183804 kb
Host smart-7579772c-c905-4ff1-a6ca-9199cea897e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235973124 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.4235973124
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.940232436
Short name T22
Test name
Test status
Simulation time 17525611382 ps
CPU time 12.14 seconds
Started Mar 10 12:24:04 PM PDT 24
Finished Mar 10 12:24:16 PM PDT 24
Peak memory 183912 kb
Host smart-4c426719-e7e1-4953-b04b-5d2bc54483a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940232436 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.940232436
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.4070388485
Short name T6
Test name
Test status
Simulation time 440134785 ps
CPU time 0.84 seconds
Started Mar 10 12:24:05 PM PDT 24
Finished Mar 10 12:24:06 PM PDT 24
Peak memory 183764 kb
Host smart-cfe0f7e5-6c8f-4640-b003-c873302afcf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070388485 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.4070388485
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.4256091068
Short name T143
Test name
Test status
Simulation time 179492793191 ps
CPU time 34.48 seconds
Started Mar 10 12:23:51 PM PDT 24
Finished Mar 10 12:24:25 PM PDT 24
Peak memory 192252 kb
Host smart-5094f106-3092-406e-9c76-8cd8b788524a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256091068 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_
all.4256091068
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.3059954090
Short name T38
Test name
Test status
Simulation time 474918125189 ps
CPU time 939.67 seconds
Started Mar 10 12:23:52 PM PDT 24
Finished Mar 10 12:39:32 PM PDT 24
Peak memory 204252 kb
Host smart-183b6811-5e40-49cd-8209-a699478cc5e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059954090 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.3059954090
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.aon_timer_jump.1046336856
Short name T180
Test name
Test status
Simulation time 401930083 ps
CPU time 0.64 seconds
Started Mar 10 12:24:05 PM PDT 24
Finished Mar 10 12:24:05 PM PDT 24
Peak memory 183836 kb
Host smart-dcaf9a32-4f3c-4f73-a02e-20330ed44325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046336856 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.1046336856
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.433049974
Short name T229
Test name
Test status
Simulation time 20385827122 ps
CPU time 17.26 seconds
Started Mar 10 12:23:55 PM PDT 24
Finished Mar 10 12:24:12 PM PDT 24
Peak memory 192164 kb
Host smart-1af8e065-a45f-4b0b-9d33-ac6001481ffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433049974 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.433049974
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.3928431178
Short name T206
Test name
Test status
Simulation time 528614702 ps
CPU time 0.66 seconds
Started Mar 10 12:23:48 PM PDT 24
Finished Mar 10 12:23:49 PM PDT 24
Peak memory 183816 kb
Host smart-786ce35a-b3bf-4b80-8276-217f000e883c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928431178 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.3928431178
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.4031294631
Short name T110
Test name
Test status
Simulation time 97559007649 ps
CPU time 36.34 seconds
Started Mar 10 12:23:52 PM PDT 24
Finished Mar 10 12:24:28 PM PDT 24
Peak memory 183900 kb
Host smart-58d27ae0-d95c-414b-93ec-eac8c9ff11bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031294631 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_
all.4031294631
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.199493662
Short name T221
Test name
Test status
Simulation time 217926332072 ps
CPU time 1161.7 seconds
Started Mar 10 12:23:56 PM PDT 24
Finished Mar 10 12:43:18 PM PDT 24
Peak memory 207684 kb
Host smart-c4bb989f-4c25-4618-985c-9e6a5501af30
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199493662 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.199493662
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.aon_timer_jump.2808792433
Short name T232
Test name
Test status
Simulation time 488318110 ps
CPU time 0.7 seconds
Started Mar 10 12:23:48 PM PDT 24
Finished Mar 10 12:23:49 PM PDT 24
Peak memory 183816 kb
Host smart-bde338ac-b4fb-4ad7-8680-da414400e21a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808792433 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.2808792433
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.2829142619
Short name T109
Test name
Test status
Simulation time 1669539807 ps
CPU time 3.04 seconds
Started Mar 10 12:23:51 PM PDT 24
Finished Mar 10 12:23:54 PM PDT 24
Peak memory 184204 kb
Host smart-2b1428a6-5b4c-4713-8c87-5ba5d192be2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829142619 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.2829142619
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.458666466
Short name T157
Test name
Test status
Simulation time 569612770 ps
CPU time 0.73 seconds
Started Mar 10 12:23:48 PM PDT 24
Finished Mar 10 12:23:49 PM PDT 24
Peak memory 183708 kb
Host smart-5e5cc3b9-ed40-4d35-8c0c-ff67024df45a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458666466 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.458666466
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.1670749986
Short name T238
Test name
Test status
Simulation time 160664784722 ps
CPU time 624.53 seconds
Started Mar 10 12:24:05 PM PDT 24
Finished Mar 10 12:34:30 PM PDT 24
Peak memory 200312 kb
Host smart-f3d1e7d0-ec80-4f1a-bc0e-d35fc95c77ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670749986 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.1670749986
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.aon_timer_jump.2077433422
Short name T115
Test name
Test status
Simulation time 534668433 ps
CPU time 0.68 seconds
Started Mar 10 12:24:05 PM PDT 24
Finished Mar 10 12:24:05 PM PDT 24
Peak memory 183756 kb
Host smart-167fb146-24a1-4708-a3f9-66f7cb78f89f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077433422 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.2077433422
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.2220794104
Short name T189
Test name
Test status
Simulation time 12700743942 ps
CPU time 9.53 seconds
Started Mar 10 12:23:51 PM PDT 24
Finished Mar 10 12:24:00 PM PDT 24
Peak memory 183912 kb
Host smart-b1e6b96a-99c7-4e2a-a831-aae25ed4a2b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220794104 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.2220794104
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.2869181107
Short name T52
Test name
Test status
Simulation time 373660768 ps
CPU time 0.84 seconds
Started Mar 10 12:23:50 PM PDT 24
Finished Mar 10 12:23:51 PM PDT 24
Peak memory 183800 kb
Host smart-430d24fc-a81e-443a-84de-47a51a08ae05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869181107 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.2869181107
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.3836648803
Short name T175
Test name
Test status
Simulation time 269555034144 ps
CPU time 432.06 seconds
Started Mar 10 12:24:10 PM PDT 24
Finished Mar 10 12:31:22 PM PDT 24
Peak memory 195028 kb
Host smart-ead473fb-a973-40d5-b59a-abc7d5d55a83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836648803 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_
all.3836648803
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.3260737892
Short name T148
Test name
Test status
Simulation time 46762234740 ps
CPU time 245.45 seconds
Started Mar 10 12:24:05 PM PDT 24
Finished Mar 10 12:28:11 PM PDT 24
Peak memory 198792 kb
Host smart-516acf3b-1ad1-49f6-9d9f-55ad76c25dc3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260737892 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.3260737892
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.aon_timer_jump.159448432
Short name T47
Test name
Test status
Simulation time 350870083 ps
CPU time 1.11 seconds
Started Mar 10 12:24:13 PM PDT 24
Finished Mar 10 12:24:14 PM PDT 24
Peak memory 183748 kb
Host smart-7037b17b-3380-4c10-b6c9-9d91f8b152ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159448432 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.159448432
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.2448211695
Short name T237
Test name
Test status
Simulation time 55758114757 ps
CPU time 93.99 seconds
Started Mar 10 12:24:13 PM PDT 24
Finished Mar 10 12:25:47 PM PDT 24
Peak memory 183856 kb
Host smart-d1526770-271c-491a-a5ff-1915676d3cdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448211695 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.2448211695
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.423729404
Short name T225
Test name
Test status
Simulation time 385072193 ps
CPU time 0.72 seconds
Started Mar 10 12:23:51 PM PDT 24
Finished Mar 10 12:23:51 PM PDT 24
Peak memory 183748 kb
Host smart-f93379f1-fd19-4682-a265-566be52d0276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423729404 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.423729404
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_jump.786137670
Short name T112
Test name
Test status
Simulation time 537197184 ps
CPU time 0.72 seconds
Started Mar 10 12:23:59 PM PDT 24
Finished Mar 10 12:24:00 PM PDT 24
Peak memory 183744 kb
Host smart-9bc736ae-24f6-478c-89db-54ef2b267a38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786137670 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.786137670
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.3009054723
Short name T161
Test name
Test status
Simulation time 14511744922 ps
CPU time 4.72 seconds
Started Mar 10 12:24:13 PM PDT 24
Finished Mar 10 12:24:18 PM PDT 24
Peak memory 191592 kb
Host smart-3f037326-9e69-4541-92a6-654c10213fcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009054723 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.3009054723
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.2640718028
Short name T214
Test name
Test status
Simulation time 566874553 ps
CPU time 0.75 seconds
Started Mar 10 12:24:13 PM PDT 24
Finished Mar 10 12:24:14 PM PDT 24
Peak memory 183752 kb
Host smart-d00f7da2-e068-4f63-bcd4-a145c16b9535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640718028 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.2640718028
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.2938582758
Short name T276
Test name
Test status
Simulation time 365110171806 ps
CPU time 118.91 seconds
Started Mar 10 12:24:11 PM PDT 24
Finished Mar 10 12:26:10 PM PDT 24
Peak memory 194368 kb
Host smart-29265d73-12e6-4719-a5f6-8aad119212af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938582758 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_
all.2938582758
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.1229153481
Short name T209
Test name
Test status
Simulation time 305672536064 ps
CPU time 1009.15 seconds
Started Mar 10 12:24:13 PM PDT 24
Finished Mar 10 12:41:02 PM PDT 24
Peak memory 205244 kb
Host smart-67ede0d1-2a8e-488d-b95a-187d26ae2b79
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229153481 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.1229153481
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.aon_timer_jump.310680133
Short name T253
Test name
Test status
Simulation time 396999310 ps
CPU time 0.86 seconds
Started Mar 10 12:24:13 PM PDT 24
Finished Mar 10 12:24:14 PM PDT 24
Peak memory 183836 kb
Host smart-167e003a-e324-4546-ac82-80859f264313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310680133 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.310680133
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.3788601055
Short name T129
Test name
Test status
Simulation time 26281978035 ps
CPU time 9.9 seconds
Started Mar 10 12:24:06 PM PDT 24
Finished Mar 10 12:24:16 PM PDT 24
Peak memory 183896 kb
Host smart-dcfb0173-d863-4bb3-ac18-7ac74efcefed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788601055 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.3788601055
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.3804341175
Short name T257
Test name
Test status
Simulation time 463729813 ps
CPU time 1.25 seconds
Started Mar 10 12:23:55 PM PDT 24
Finished Mar 10 12:23:56 PM PDT 24
Peak memory 183832 kb
Host smart-7a3f886d-a3dc-4223-ae11-62d5bc6523d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804341175 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.3804341175
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.391586995
Short name T230
Test name
Test status
Simulation time 262504508611 ps
CPU time 375.92 seconds
Started Mar 10 12:24:06 PM PDT 24
Finished Mar 10 12:30:22 PM PDT 24
Peak memory 193348 kb
Host smart-42aa95b8-a528-4c63-89be-27f6e1a5f26f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391586995 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_a
ll.391586995
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.3848596708
Short name T54
Test name
Test status
Simulation time 73788409888 ps
CPU time 775.8 seconds
Started Mar 10 12:24:04 PM PDT 24
Finished Mar 10 12:37:00 PM PDT 24
Peak memory 201436 kb
Host smart-857c5b94-5d3a-4fac-8304-a145392cb1e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848596708 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.3848596708
Directory /workspace/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.aon_timer_jump.3952229568
Short name T197
Test name
Test status
Simulation time 549331794 ps
CPU time 1.3 seconds
Started Mar 10 12:24:05 PM PDT 24
Finished Mar 10 12:24:06 PM PDT 24
Peak memory 183772 kb
Host smart-ce70a492-82f2-47ea-9107-e8a7bee20ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952229568 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.3952229568
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.1407799765
Short name T268
Test name
Test status
Simulation time 39176694205 ps
CPU time 7.79 seconds
Started Mar 10 12:24:13 PM PDT 24
Finished Mar 10 12:24:21 PM PDT 24
Peak memory 183808 kb
Host smart-1d69ca21-ad46-4d67-bce0-2845368e98eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407799765 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.1407799765
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.3613291664
Short name T250
Test name
Test status
Simulation time 473740733 ps
CPU time 0.72 seconds
Started Mar 10 12:24:13 PM PDT 24
Finished Mar 10 12:24:14 PM PDT 24
Peak memory 183752 kb
Host smart-f0c93ea6-c050-408b-8277-73e4ac1231d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613291664 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.3613291664
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.737725404
Short name T44
Test name
Test status
Simulation time 304104107665 ps
CPU time 40.99 seconds
Started Mar 10 12:24:06 PM PDT 24
Finished Mar 10 12:24:47 PM PDT 24
Peak memory 195892 kb
Host smart-1b9e74ff-75ef-42ca-a5f7-873e4c8bfaa4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737725404 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_a
ll.737725404
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_jump.3093649738
Short name T198
Test name
Test status
Simulation time 701558186 ps
CPU time 0.65 seconds
Started Mar 10 12:24:05 PM PDT 24
Finished Mar 10 12:24:06 PM PDT 24
Peak memory 183776 kb
Host smart-51756b0c-cd35-4cfd-b2d7-a4732da5bfbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093649738 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.3093649738
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.2151887175
Short name T174
Test name
Test status
Simulation time 8711915465 ps
CPU time 3.14 seconds
Started Mar 10 12:24:13 PM PDT 24
Finished Mar 10 12:24:16 PM PDT 24
Peak memory 183380 kb
Host smart-d0244106-dbc1-4800-bed6-a3a29371126d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151887175 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.2151887175
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.4060982973
Short name T154
Test name
Test status
Simulation time 499210365 ps
CPU time 0.88 seconds
Started Mar 10 12:24:13 PM PDT 24
Finished Mar 10 12:24:14 PM PDT 24
Peak memory 183780 kb
Host smart-0f30c6b7-81c3-4e53-9abc-532d5fbd59ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060982973 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.4060982973
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.531102737
Short name T10
Test name
Test status
Simulation time 236075098403 ps
CPU time 401.67 seconds
Started Mar 10 12:24:13 PM PDT 24
Finished Mar 10 12:30:55 PM PDT 24
Peak memory 183884 kb
Host smart-7a2c7e61-c4c7-4b59-962a-58c27b6cd4d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531102737 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_a
ll.531102737
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.1367756868
Short name T80
Test name
Test status
Simulation time 110886945023 ps
CPU time 815.31 seconds
Started Mar 10 12:24:13 PM PDT 24
Finished Mar 10 12:37:48 PM PDT 24
Peak memory 202336 kb
Host smart-89acda6a-5594-4cc8-bea0-94b820873f9b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367756868 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.1367756868
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.aon_timer_jump.1771420417
Short name T142
Test name
Test status
Simulation time 430436971 ps
CPU time 1.32 seconds
Started Mar 10 12:24:13 PM PDT 24
Finished Mar 10 12:24:14 PM PDT 24
Peak memory 183760 kb
Host smart-cf7b3c79-7586-44b6-8053-58ac10f8ace5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771420417 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.1771420417
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.3922577219
Short name T125
Test name
Test status
Simulation time 15636831606 ps
CPU time 12.15 seconds
Started Mar 10 12:24:13 PM PDT 24
Finished Mar 10 12:24:25 PM PDT 24
Peak memory 183860 kb
Host smart-08e20c10-840e-449e-8fe5-decdd75518f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922577219 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.3922577219
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.1174147070
Short name T147
Test name
Test status
Simulation time 588619516 ps
CPU time 0.65 seconds
Started Mar 10 12:24:13 PM PDT 24
Finished Mar 10 12:24:14 PM PDT 24
Peak memory 183752 kb
Host smart-611bc4f4-87f2-4251-b1e4-d34d685b5e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174147070 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.1174147070
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.4152004053
Short name T7
Test name
Test status
Simulation time 107435727311 ps
CPU time 92.15 seconds
Started Mar 10 12:24:13 PM PDT 24
Finished Mar 10 12:25:45 PM PDT 24
Peak memory 183880 kb
Host smart-ab1b94ff-721f-435d-98b9-95445b9bb5f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152004053 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_
all.4152004053
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.1252082080
Short name T265
Test name
Test status
Simulation time 74370057149 ps
CPU time 512.73 seconds
Started Mar 10 12:24:13 PM PDT 24
Finished Mar 10 12:32:46 PM PDT 24
Peak memory 198772 kb
Host smart-30497ee8-d554-4114-87b1-8d6a0a148598
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252082080 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.1252082080
Directory /workspace/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.aon_timer_jump.2073502230
Short name T42
Test name
Test status
Simulation time 580655064 ps
CPU time 0.7 seconds
Started Mar 10 12:22:35 PM PDT 24
Finished Mar 10 12:22:36 PM PDT 24
Peak memory 184208 kb
Host smart-42401354-e8e1-4557-a65e-d7eb6dfbacd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073502230 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.2073502230
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.1319160830
Short name T25
Test name
Test status
Simulation time 7394636235 ps
CPU time 7.03 seconds
Started Mar 10 12:30:26 PM PDT 24
Finished Mar 10 12:30:33 PM PDT 24
Peak memory 183872 kb
Host smart-60a11fb6-fd11-4080-9564-a44d749605d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319160830 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.1319160830
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.1969909570
Short name T111
Test name
Test status
Simulation time 382849914 ps
CPU time 1.17 seconds
Started Mar 10 12:24:43 PM PDT 24
Finished Mar 10 12:24:46 PM PDT 24
Peak memory 183708 kb
Host smart-beaf0c48-c840-4eb7-a58d-7ff1437f2285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969909570 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.1969909570
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.3184596644
Short name T113
Test name
Test status
Simulation time 119918004195 ps
CPU time 21.59 seconds
Started Mar 10 12:22:42 PM PDT 24
Finished Mar 10 12:23:04 PM PDT 24
Peak memory 194432 kb
Host smart-c043d446-5e5d-47bb-aa28-a1572ac44625
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184596644 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_a
ll.3184596644
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.3410810257
Short name T9
Test name
Test status
Simulation time 68152158148 ps
CPU time 394.62 seconds
Started Mar 10 12:22:42 PM PDT 24
Finished Mar 10 12:29:17 PM PDT 24
Peak memory 198776 kb
Host smart-83b95c90-32a3-4c43-9b51-d841a699b3b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410810257 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.3410810257
Directory /workspace/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.aon_timer_jump.3192349895
Short name T213
Test name
Test status
Simulation time 416941699 ps
CPU time 0.83 seconds
Started Mar 10 12:22:44 PM PDT 24
Finished Mar 10 12:22:45 PM PDT 24
Peak memory 183840 kb
Host smart-3cab359b-b28d-4ef2-8579-317d82ac7d0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192349895 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.3192349895
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.445032811
Short name T281
Test name
Test status
Simulation time 19409337154 ps
CPU time 27.71 seconds
Started Mar 10 12:22:37 PM PDT 24
Finished Mar 10 12:23:05 PM PDT 24
Peak memory 183928 kb
Host smart-cccef935-8553-49fb-9bbc-46d91ec9373f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445032811 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.445032811
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.1734515549
Short name T144
Test name
Test status
Simulation time 364870143 ps
CPU time 1.1 seconds
Started Mar 10 12:22:44 PM PDT 24
Finished Mar 10 12:22:45 PM PDT 24
Peak memory 183836 kb
Host smart-44ca0f04-5213-43dd-9955-4289c64f92c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734515549 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.1734515549
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.3224148428
Short name T141
Test name
Test status
Simulation time 81777496455 ps
CPU time 16.5 seconds
Started Mar 10 12:22:40 PM PDT 24
Finished Mar 10 12:22:57 PM PDT 24
Peak memory 193576 kb
Host smart-db03397c-b1c5-4fac-97ba-a56bc3670044
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224148428 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_a
ll.3224148428
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.1836244414
Short name T77
Test name
Test status
Simulation time 57307123571 ps
CPU time 148.29 seconds
Started Mar 10 12:22:44 PM PDT 24
Finished Mar 10 12:25:12 PM PDT 24
Peak memory 198792 kb
Host smart-c168bee2-6c82-4eaf-a3fb-e102f4692700
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836244414 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.1836244414
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.aon_timer_jump.3398307840
Short name T177
Test name
Test status
Simulation time 385433697 ps
CPU time 0.87 seconds
Started Mar 10 12:22:54 PM PDT 24
Finished Mar 10 12:22:55 PM PDT 24
Peak memory 183836 kb
Host smart-42d397b9-6e6c-45ba-8f50-e26ea719fb2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398307840 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.3398307840
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.51767554
Short name T90
Test name
Test status
Simulation time 15316307579 ps
CPU time 2.73 seconds
Started Mar 10 12:22:41 PM PDT 24
Finished Mar 10 12:22:44 PM PDT 24
Peak memory 183952 kb
Host smart-b0adfba0-55ef-40f8-b00a-498d9f5546f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51767554 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.51767554
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.2087057897
Short name T86
Test name
Test status
Simulation time 446547906 ps
CPU time 1.14 seconds
Started Mar 10 12:22:44 PM PDT 24
Finished Mar 10 12:22:45 PM PDT 24
Peak memory 183836 kb
Host smart-28cd704a-042c-483d-b06f-a6c47427d399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087057897 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.2087057897
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.2689686515
Short name T259
Test name
Test status
Simulation time 182125792666 ps
CPU time 133.09 seconds
Started Mar 10 12:22:49 PM PDT 24
Finished Mar 10 12:25:03 PM PDT 24
Peak memory 183932 kb
Host smart-bbc2c361-d855-4014-83a4-7f9378b2b6b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689686515 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_a
ll.2689686515
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.3930869043
Short name T87
Test name
Test status
Simulation time 451672127318 ps
CPU time 188.9 seconds
Started Mar 10 12:22:49 PM PDT 24
Finished Mar 10 12:25:58 PM PDT 24
Peak memory 198744 kb
Host smart-ffc130eb-2d2d-4e42-82fe-db2debc90863
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930869043 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.3930869043
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.aon_timer_jump.1130470798
Short name T264
Test name
Test status
Simulation time 532054380 ps
CPU time 0.96 seconds
Started Mar 10 12:22:56 PM PDT 24
Finished Mar 10 12:22:57 PM PDT 24
Peak memory 183764 kb
Host smart-379634e6-6539-4d3c-8c5a-da815dc058f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130470798 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.1130470798
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.3264982259
Short name T194
Test name
Test status
Simulation time 3286811529 ps
CPU time 5.05 seconds
Started Mar 10 12:22:54 PM PDT 24
Finished Mar 10 12:22:59 PM PDT 24
Peak memory 183948 kb
Host smart-a9637d89-a659-43bd-a849-3453d144aee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264982259 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.3264982259
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.3159554931
Short name T164
Test name
Test status
Simulation time 382601026 ps
CPU time 0.68 seconds
Started Mar 10 12:22:56 PM PDT 24
Finished Mar 10 12:22:57 PM PDT 24
Peak memory 183764 kb
Host smart-7496d5b4-a1a4-4254-bd89-53c91b0b7dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159554931 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.3159554931
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.2900112062
Short name T24
Test name
Test status
Simulation time 56958990069 ps
CPU time 75.4 seconds
Started Mar 10 12:22:56 PM PDT 24
Finished Mar 10 12:24:12 PM PDT 24
Peak memory 184120 kb
Host smart-36a129d0-5de2-47f4-b148-d5ad73e4699a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900112062 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_a
ll.2900112062
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.3033032614
Short name T173
Test name
Test status
Simulation time 25225726500 ps
CPU time 187.44 seconds
Started Mar 10 12:23:01 PM PDT 24
Finished Mar 10 12:26:08 PM PDT 24
Peak memory 198628 kb
Host smart-22c95308-f55e-4d7e-9787-363809ffdc9b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033032614 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.3033032614
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.aon_timer_jump.3727378520
Short name T152
Test name
Test status
Simulation time 584724681 ps
CPU time 1.49 seconds
Started Mar 10 12:23:09 PM PDT 24
Finished Mar 10 12:23:11 PM PDT 24
Peak memory 183924 kb
Host smart-5f9120ab-37c5-4f36-bbb2-611a7321fd7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727378520 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.3727378520
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.1629839103
Short name T124
Test name
Test status
Simulation time 25704668426 ps
CPU time 7.64 seconds
Started Mar 10 12:23:03 PM PDT 24
Finished Mar 10 12:23:11 PM PDT 24
Peak memory 192140 kb
Host smart-b231ae01-167d-4a6f-9012-ea70e97bd27b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629839103 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.1629839103
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.2701928178
Short name T271
Test name
Test status
Simulation time 453326297 ps
CPU time 0.78 seconds
Started Mar 10 12:23:09 PM PDT 24
Finished Mar 10 12:23:10 PM PDT 24
Peak memory 183924 kb
Host smart-51456264-18a3-4781-8a59-bafa08e74a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701928178 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.2701928178
Directory /workspace/9.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.3902599529
Short name T155
Test name
Test status
Simulation time 246783671205 ps
CPU time 57.55 seconds
Started Mar 10 12:23:14 PM PDT 24
Finished Mar 10 12:24:11 PM PDT 24
Peak memory 192156 kb
Host smart-60e16641-0e04-45c2-b1ed-a083dc154ed6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902599529 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_a
ll.3902599529
Directory /workspace/9.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.3926486425
Short name T263
Test name
Test status
Simulation time 146663412790 ps
CPU time 261.14 seconds
Started Mar 10 12:23:01 PM PDT 24
Finished Mar 10 12:27:22 PM PDT 24
Peak memory 198628 kb
Host smart-f949b793-a080-4f6e-bbdf-bbe889f6dcd7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926486425 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.3926486425
Directory /workspace/9.aon_timer_stress_all_with_rand_reset/latest
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