Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
92.98 99.25 93.67 100.00 98.40 99.51 67.06


Total test records in report: 419
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T34 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.73990768 Mar 12 12:28:04 PM PDT 24 Mar 12 12:28:05 PM PDT 24 1767696061 ps
T35 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.1554706390 Mar 12 12:28:14 PM PDT 24 Mar 12 12:28:15 PM PDT 24 516981741 ps
T285 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.1026132105 Mar 12 12:27:43 PM PDT 24 Mar 12 12:27:44 PM PDT 24 502896105 ps
T38 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.2008890181 Mar 12 12:27:49 PM PDT 24 Mar 12 12:27:50 PM PDT 24 466762532 ps
T286 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.4029509486 Mar 12 12:28:00 PM PDT 24 Mar 12 12:28:02 PM PDT 24 453760335 ps
T39 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.4190005218 Mar 12 12:28:16 PM PDT 24 Mar 12 12:28:18 PM PDT 24 2195478234 ps
T287 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.5754760 Mar 12 12:28:00 PM PDT 24 Mar 12 12:28:02 PM PDT 24 366061707 ps
T288 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.3280665766 Mar 12 12:28:23 PM PDT 24 Mar 12 12:28:23 PM PDT 24 310554153 ps
T49 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.3709461341 Mar 12 12:27:56 PM PDT 24 Mar 12 12:27:58 PM PDT 24 1069654531 ps
T40 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.927366242 Mar 12 12:27:58 PM PDT 24 Mar 12 12:28:06 PM PDT 24 4404390332 ps
T289 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.32381399 Mar 12 12:28:23 PM PDT 24 Mar 12 12:28:24 PM PDT 24 363207814 ps
T290 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.1136413165 Mar 12 12:27:59 PM PDT 24 Mar 12 12:28:01 PM PDT 24 707641800 ps
T291 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.3469901045 Mar 12 12:27:59 PM PDT 24 Mar 12 12:28:02 PM PDT 24 350915645 ps
T292 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.2934607022 Mar 12 12:28:26 PM PDT 24 Mar 12 12:28:27 PM PDT 24 335644280 ps
T293 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.110523998 Mar 12 12:28:02 PM PDT 24 Mar 12 12:28:03 PM PDT 24 482647373 ps
T73 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.1937997825 Mar 12 12:27:49 PM PDT 24 Mar 12 12:27:53 PM PDT 24 1821583574 ps
T50 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.1501709864 Mar 12 12:27:51 PM PDT 24 Mar 12 12:27:58 PM PDT 24 10529998028 ps
T294 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.1899068588 Mar 12 12:28:24 PM PDT 24 Mar 12 12:28:25 PM PDT 24 519292344 ps
T74 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.2748508708 Mar 12 12:28:10 PM PDT 24 Mar 12 12:28:14 PM PDT 24 2504850900 ps
T41 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.570059682 Mar 12 12:28:20 PM PDT 24 Mar 12 12:28:25 PM PDT 24 8352249593 ps
T295 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.3383588126 Mar 12 12:28:23 PM PDT 24 Mar 12 12:28:24 PM PDT 24 285766080 ps
T296 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.1610056427 Mar 12 12:28:20 PM PDT 24 Mar 12 12:28:21 PM PDT 24 337461809 ps
T75 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.2788941773 Mar 12 12:28:09 PM PDT 24 Mar 12 12:28:11 PM PDT 24 2354932633 ps
T297 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.3729752076 Mar 12 12:28:11 PM PDT 24 Mar 12 12:28:14 PM PDT 24 508188423 ps
T76 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.169354863 Mar 12 12:28:04 PM PDT 24 Mar 12 12:28:08 PM PDT 24 1313832063 ps
T77 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.800670475 Mar 12 12:27:52 PM PDT 24 Mar 12 12:27:55 PM PDT 24 1199243946 ps
T51 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.159600935 Mar 12 12:27:49 PM PDT 24 Mar 12 12:27:50 PM PDT 24 619165822 ps
T42 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.472343791 Mar 12 12:28:11 PM PDT 24 Mar 12 12:28:19 PM PDT 24 4332431344 ps
T298 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.1326746719 Mar 12 12:28:13 PM PDT 24 Mar 12 12:28:14 PM PDT 24 517964423 ps
T52 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.250944791 Mar 12 12:28:10 PM PDT 24 Mar 12 12:28:11 PM PDT 24 358977870 ps
T299 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.3845638076 Mar 12 12:27:55 PM PDT 24 Mar 12 12:27:56 PM PDT 24 363093939 ps
T300 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.1240310152 Mar 12 12:28:02 PM PDT 24 Mar 12 12:28:04 PM PDT 24 526577911 ps
T301 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.3990529673 Mar 12 12:28:27 PM PDT 24 Mar 12 12:28:28 PM PDT 24 552385010 ps
T98 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.2120852762 Mar 12 12:28:14 PM PDT 24 Mar 12 12:28:16 PM PDT 24 4109164149 ps
T302 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.363282628 Mar 12 12:28:11 PM PDT 24 Mar 12 12:28:12 PM PDT 24 622207309 ps
T78 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.904387919 Mar 12 12:28:01 PM PDT 24 Mar 12 12:28:02 PM PDT 24 399752758 ps
T303 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.1511418016 Mar 12 12:28:13 PM PDT 24 Mar 12 12:28:14 PM PDT 24 427910942 ps
T304 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.2219109626 Mar 12 12:27:55 PM PDT 24 Mar 12 12:27:56 PM PDT 24 331460528 ps
T305 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.669660344 Mar 12 12:28:04 PM PDT 24 Mar 12 12:28:07 PM PDT 24 8186108380 ps
T79 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.3477854540 Mar 12 12:28:12 PM PDT 24 Mar 12 12:28:15 PM PDT 24 1899339514 ps
T306 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.1543941601 Mar 12 12:28:05 PM PDT 24 Mar 12 12:28:09 PM PDT 24 421594890 ps
T53 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.3148468489 Mar 12 12:27:52 PM PDT 24 Mar 12 12:27:55 PM PDT 24 1115236427 ps
T101 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.3608283237 Mar 12 12:27:59 PM PDT 24 Mar 12 12:28:02 PM PDT 24 4284099329 ps
T307 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.2590975469 Mar 12 12:28:22 PM PDT 24 Mar 12 12:28:23 PM PDT 24 1717386177 ps
T308 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.1179294394 Mar 12 12:28:15 PM PDT 24 Mar 12 12:28:16 PM PDT 24 506988117 ps
T309 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.2385314239 Mar 12 12:27:56 PM PDT 24 Mar 12 12:27:57 PM PDT 24 377220178 ps
T62 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.568459342 Mar 12 12:27:42 PM PDT 24 Mar 12 12:27:43 PM PDT 24 482880184 ps
T310 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.2178024547 Mar 12 12:27:53 PM PDT 24 Mar 12 12:27:55 PM PDT 24 511487361 ps
T102 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.803413996 Mar 12 12:27:58 PM PDT 24 Mar 12 12:28:06 PM PDT 24 4212679289 ps
T311 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.512013374 Mar 12 12:28:20 PM PDT 24 Mar 12 12:28:20 PM PDT 24 514582415 ps
T312 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.282099922 Mar 12 12:28:01 PM PDT 24 Mar 12 12:28:03 PM PDT 24 484065410 ps
T313 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.1428388320 Mar 12 12:27:52 PM PDT 24 Mar 12 12:27:53 PM PDT 24 419167080 ps
T63 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.2487248960 Mar 12 12:27:56 PM PDT 24 Mar 12 12:27:57 PM PDT 24 400035091 ps
T314 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.3865781617 Mar 12 12:28:18 PM PDT 24 Mar 12 12:28:20 PM PDT 24 315105446 ps
T315 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.595913917 Mar 12 12:28:26 PM PDT 24 Mar 12 12:28:27 PM PDT 24 387244545 ps
T316 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.3354631711 Mar 12 12:28:13 PM PDT 24 Mar 12 12:28:13 PM PDT 24 425179330 ps
T317 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.1799258805 Mar 12 12:27:43 PM PDT 24 Mar 12 12:27:44 PM PDT 24 451583054 ps
T318 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.3364801771 Mar 12 12:27:59 PM PDT 24 Mar 12 12:28:00 PM PDT 24 347503471 ps
T319 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.1336357620 Mar 12 12:28:02 PM PDT 24 Mar 12 12:28:04 PM PDT 24 586496526 ps
T320 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.1692015235 Mar 12 12:27:51 PM PDT 24 Mar 12 12:27:53 PM PDT 24 379805504 ps
T321 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.3573054644 Mar 12 12:28:00 PM PDT 24 Mar 12 12:28:02 PM PDT 24 546197315 ps
T322 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.1332144238 Mar 12 12:34:55 PM PDT 24 Mar 12 12:35:01 PM PDT 24 4672372690 ps
T323 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.574218045 Mar 12 12:28:26 PM PDT 24 Mar 12 12:28:28 PM PDT 24 372126151 ps
T64 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.3064640376 Mar 12 12:28:00 PM PDT 24 Mar 12 12:28:01 PM PDT 24 403176783 ps
T65 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.1296923367 Mar 12 12:27:50 PM PDT 24 Mar 12 12:28:06 PM PDT 24 11097951545 ps
T103 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.647869041 Mar 12 12:28:09 PM PDT 24 Mar 12 12:28:17 PM PDT 24 4107720146 ps
T66 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.3680436197 Mar 12 12:28:14 PM PDT 24 Mar 12 12:28:15 PM PDT 24 488121080 ps
T324 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.742558256 Mar 12 12:28:25 PM PDT 24 Mar 12 12:28:26 PM PDT 24 488279812 ps
T325 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.3044148727 Mar 12 12:28:22 PM PDT 24 Mar 12 12:28:23 PM PDT 24 308438142 ps
T326 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.2191150889 Mar 12 12:27:46 PM PDT 24 Mar 12 12:27:47 PM PDT 24 506884205 ps
T327 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.1639098423 Mar 12 12:28:24 PM PDT 24 Mar 12 12:28:25 PM PDT 24 494340689 ps
T328 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.3195195827 Mar 12 12:27:59 PM PDT 24 Mar 12 12:28:00 PM PDT 24 353423004 ps
T329 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.3594305025 Mar 12 12:27:52 PM PDT 24 Mar 12 12:27:54 PM PDT 24 336141092 ps
T99 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.4216067032 Mar 12 12:27:52 PM PDT 24 Mar 12 12:28:07 PM PDT 24 8661150826 ps
T330 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.3528014367 Mar 12 12:27:44 PM PDT 24 Mar 12 12:27:46 PM PDT 24 1026946625 ps
T331 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.2814812368 Mar 12 12:28:09 PM PDT 24 Mar 12 12:28:10 PM PDT 24 505584854 ps
T332 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.3321704967 Mar 12 12:27:48 PM PDT 24 Mar 12 12:27:49 PM PDT 24 371651887 ps
T333 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.1611867394 Mar 12 12:27:49 PM PDT 24 Mar 12 12:27:49 PM PDT 24 2187431003 ps
T334 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.1852158646 Mar 12 12:28:09 PM PDT 24 Mar 12 12:28:11 PM PDT 24 353320429 ps
T335 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.432244275 Mar 12 12:28:29 PM PDT 24 Mar 12 12:28:30 PM PDT 24 492019376 ps
T336 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.3207543033 Mar 12 12:28:23 PM PDT 24 Mar 12 12:28:24 PM PDT 24 304938935 ps
T100 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.3005607748 Mar 12 12:28:20 PM PDT 24 Mar 12 12:28:23 PM PDT 24 8976144988 ps
T337 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.739109197 Mar 12 12:28:00 PM PDT 24 Mar 12 12:28:02 PM PDT 24 319626333 ps
T338 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.2160678406 Mar 12 12:28:08 PM PDT 24 Mar 12 12:28:15 PM PDT 24 4433500365 ps
T54 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.1267754260 Mar 12 12:27:45 PM PDT 24 Mar 12 12:27:47 PM PDT 24 469834843 ps
T339 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.1639309631 Mar 12 12:27:49 PM PDT 24 Mar 12 12:27:50 PM PDT 24 496111834 ps
T340 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.3243153515 Mar 12 12:28:13 PM PDT 24 Mar 12 12:28:15 PM PDT 24 486245099 ps
T341 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.3911051444 Mar 12 12:28:13 PM PDT 24 Mar 12 12:28:14 PM PDT 24 422288004 ps
T342 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.1416120817 Mar 12 12:28:11 PM PDT 24 Mar 12 12:28:12 PM PDT 24 426799468 ps
T343 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.305891052 Mar 12 12:28:11 PM PDT 24 Mar 12 12:28:13 PM PDT 24 1151904139 ps
T344 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.1887619890 Mar 12 12:28:11 PM PDT 24 Mar 12 12:28:12 PM PDT 24 601038438 ps
T72 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.2073154605 Mar 12 12:27:49 PM PDT 24 Mar 12 12:27:50 PM PDT 24 549187152 ps
T345 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.3738909245 Mar 12 12:28:17 PM PDT 24 Mar 12 12:28:19 PM PDT 24 430889237 ps
T346 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.1645416994 Mar 12 12:28:22 PM PDT 24 Mar 12 12:28:23 PM PDT 24 601888929 ps
T347 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.2868416621 Mar 12 12:27:52 PM PDT 24 Mar 12 12:27:53 PM PDT 24 348544745 ps
T348 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.4055370860 Mar 12 12:28:16 PM PDT 24 Mar 12 12:28:17 PM PDT 24 345309037 ps
T349 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.3149147957 Mar 12 12:28:02 PM PDT 24 Mar 12 12:28:03 PM PDT 24 387013356 ps
T350 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.879865858 Mar 12 12:28:00 PM PDT 24 Mar 12 12:28:02 PM PDT 24 689233375 ps
T351 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.4251227453 Mar 12 12:27:59 PM PDT 24 Mar 12 12:28:00 PM PDT 24 433408719 ps
T352 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.2009967479 Mar 12 12:28:00 PM PDT 24 Mar 12 12:28:01 PM PDT 24 333799311 ps
T353 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.2155563084 Mar 12 12:28:05 PM PDT 24 Mar 12 12:28:08 PM PDT 24 2194036302 ps
T354 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.487390499 Mar 12 12:27:52 PM PDT 24 Mar 12 12:27:54 PM PDT 24 1524357319 ps
T355 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.2367325583 Mar 12 12:28:17 PM PDT 24 Mar 12 12:28:19 PM PDT 24 1296800794 ps
T356 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.91959987 Mar 12 12:28:03 PM PDT 24 Mar 12 12:28:10 PM PDT 24 4192146657 ps
T357 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.1942266721 Mar 12 12:28:23 PM PDT 24 Mar 12 12:28:25 PM PDT 24 427026067 ps
T358 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.1665433043 Mar 12 12:27:54 PM PDT 24 Mar 12 12:27:56 PM PDT 24 702704075 ps
T359 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.2525630691 Mar 12 12:27:56 PM PDT 24 Mar 12 12:27:58 PM PDT 24 455040170 ps
T360 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.1984658064 Mar 12 12:28:03 PM PDT 24 Mar 12 12:28:04 PM PDT 24 545928420 ps
T361 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.3344181856 Mar 12 12:28:08 PM PDT 24 Mar 12 12:28:10 PM PDT 24 419702509 ps
T67 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.1548605356 Mar 12 12:27:56 PM PDT 24 Mar 12 12:27:57 PM PDT 24 571295605 ps
T362 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.1185931041 Mar 12 12:28:02 PM PDT 24 Mar 12 12:28:04 PM PDT 24 368972492 ps
T363 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.1208186474 Mar 12 12:28:11 PM PDT 24 Mar 12 12:28:12 PM PDT 24 1207990517 ps
T364 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.72903639 Mar 12 12:28:13 PM PDT 24 Mar 12 12:28:14 PM PDT 24 377272176 ps
T365 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.382005127 Mar 12 12:27:54 PM PDT 24 Mar 12 12:27:55 PM PDT 24 482700081 ps
T366 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.741584019 Mar 12 12:28:10 PM PDT 24 Mar 12 12:28:13 PM PDT 24 538149719 ps
T367 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.2876502087 Mar 12 12:27:51 PM PDT 24 Mar 12 12:27:56 PM PDT 24 4754171910 ps
T368 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.574922014 Mar 12 12:27:55 PM PDT 24 Mar 12 12:27:56 PM PDT 24 405305920 ps
T369 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.664593519 Mar 12 12:28:11 PM PDT 24 Mar 12 12:28:19 PM PDT 24 4587361952 ps
T370 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.1021807874 Mar 12 12:28:02 PM PDT 24 Mar 12 12:28:04 PM PDT 24 748661993 ps
T371 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.3474929825 Mar 12 12:27:53 PM PDT 24 Mar 12 12:27:56 PM PDT 24 1314780774 ps
T372 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.3345191410 Mar 12 12:27:50 PM PDT 24 Mar 12 12:27:52 PM PDT 24 626846836 ps
T373 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.2793571250 Mar 12 12:28:02 PM PDT 24 Mar 12 12:28:04 PM PDT 24 510790682 ps
T374 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.1853856309 Mar 12 12:27:51 PM PDT 24 Mar 12 12:27:59 PM PDT 24 8459491567 ps
T375 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.471849278 Mar 12 12:28:00 PM PDT 24 Mar 12 12:28:02 PM PDT 24 552171512 ps
T376 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.1506250351 Mar 12 12:27:52 PM PDT 24 Mar 12 12:27:55 PM PDT 24 1177949646 ps
T377 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.3027780723 Mar 12 12:28:02 PM PDT 24 Mar 12 12:28:04 PM PDT 24 497642619 ps
T378 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.910838496 Mar 12 12:28:03 PM PDT 24 Mar 12 12:28:03 PM PDT 24 398002791 ps
T379 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.4263903909 Mar 12 12:28:24 PM PDT 24 Mar 12 12:28:25 PM PDT 24 471178131 ps
T380 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.4010509620 Mar 12 12:28:00 PM PDT 24 Mar 12 12:28:01 PM PDT 24 394445591 ps
T381 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.2494791637 Mar 12 12:28:14 PM PDT 24 Mar 12 12:28:15 PM PDT 24 287527428 ps
T382 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.3361662427 Mar 12 12:28:28 PM PDT 24 Mar 12 12:28:29 PM PDT 24 442297590 ps
T383 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.4108155798 Mar 12 12:28:21 PM PDT 24 Mar 12 12:28:22 PM PDT 24 387821408 ps
T384 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.2086571078 Mar 12 12:28:14 PM PDT 24 Mar 12 12:28:16 PM PDT 24 587157684 ps
T385 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.1944156927 Mar 12 12:28:18 PM PDT 24 Mar 12 12:28:19 PM PDT 24 548451000 ps
T386 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.4148570404 Mar 12 12:28:14 PM PDT 24 Mar 12 12:28:15 PM PDT 24 975435693 ps
T387 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.972060354 Mar 12 12:28:04 PM PDT 24 Mar 12 12:28:05 PM PDT 24 1402094932 ps
T388 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.2943325085 Mar 12 12:28:22 PM PDT 24 Mar 12 12:28:23 PM PDT 24 423086252 ps
T389 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.2453989242 Mar 12 12:28:12 PM PDT 24 Mar 12 12:28:13 PM PDT 24 538594109 ps
T390 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.3666255750 Mar 12 12:27:51 PM PDT 24 Mar 12 12:27:54 PM PDT 24 3905686481 ps
T391 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.2983231348 Mar 12 12:28:27 PM PDT 24 Mar 12 12:28:28 PM PDT 24 380529080 ps
T392 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.978940100 Mar 12 12:27:52 PM PDT 24 Mar 12 12:27:53 PM PDT 24 374433156 ps
T393 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.3385556923 Mar 12 12:28:02 PM PDT 24 Mar 12 12:28:04 PM PDT 24 1172566512 ps
T394 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.4268845689 Mar 12 12:28:00 PM PDT 24 Mar 12 12:28:15 PM PDT 24 8760178232 ps
T395 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.2228200519 Mar 12 12:28:17 PM PDT 24 Mar 12 12:28:17 PM PDT 24 304351058 ps
T396 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.186740308 Mar 12 12:28:11 PM PDT 24 Mar 12 12:28:12 PM PDT 24 428039071 ps
T68 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.148811043 Mar 12 12:28:01 PM PDT 24 Mar 12 12:28:04 PM PDT 24 671129617 ps
T397 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.2063966337 Mar 12 12:28:19 PM PDT 24 Mar 12 12:28:22 PM PDT 24 494199654 ps
T398 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.618775363 Mar 12 12:28:02 PM PDT 24 Mar 12 12:28:03 PM PDT 24 1508511045 ps
T399 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.3381054578 Mar 12 12:28:04 PM PDT 24 Mar 12 12:28:07 PM PDT 24 2829931818 ps
T400 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.689353551 Mar 12 12:28:11 PM PDT 24 Mar 12 12:28:12 PM PDT 24 385569512 ps
T401 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.430293894 Mar 12 12:38:04 PM PDT 24 Mar 12 12:38:05 PM PDT 24 358429226 ps
T402 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.2517444289 Mar 12 12:27:50 PM PDT 24 Mar 12 12:27:52 PM PDT 24 489891954 ps
T403 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.586738262 Mar 12 12:27:51 PM PDT 24 Mar 12 12:27:55 PM PDT 24 2143870855 ps
T404 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.2276008844 Mar 12 12:28:30 PM PDT 24 Mar 12 12:28:31 PM PDT 24 331852144 ps
T405 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.2989335371 Mar 12 12:28:03 PM PDT 24 Mar 12 12:28:04 PM PDT 24 438620481 ps
T406 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.14507859 Mar 12 12:27:59 PM PDT 24 Mar 12 12:28:01 PM PDT 24 503749864 ps
T407 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.4035900236 Mar 12 12:27:50 PM PDT 24 Mar 12 12:27:58 PM PDT 24 7213978530 ps
T408 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.2735002630 Mar 12 12:28:18 PM PDT 24 Mar 12 12:28:20 PM PDT 24 476953936 ps
T409 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.3563460198 Mar 12 12:27:56 PM PDT 24 Mar 12 12:27:59 PM PDT 24 1162404793 ps
T410 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.4156414191 Mar 12 12:27:59 PM PDT 24 Mar 12 12:28:01 PM PDT 24 492913232 ps
T411 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.24297946 Mar 12 12:28:12 PM PDT 24 Mar 12 12:28:13 PM PDT 24 520758537 ps
T412 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.932278279 Mar 12 12:27:40 PM PDT 24 Mar 12 12:27:41 PM PDT 24 288241844 ps
T413 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.343208374 Mar 12 12:28:11 PM PDT 24 Mar 12 12:28:12 PM PDT 24 478970561 ps
T414 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.4253334395 Mar 12 12:28:01 PM PDT 24 Mar 12 12:28:02 PM PDT 24 518507007 ps
T415 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.443936224 Mar 12 12:28:08 PM PDT 24 Mar 12 12:28:16 PM PDT 24 2089937065 ps
T416 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.3128230376 Mar 12 12:28:09 PM PDT 24 Mar 12 12:28:10 PM PDT 24 481643409 ps
T417 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.202442696 Mar 12 12:27:52 PM PDT 24 Mar 12 12:27:58 PM PDT 24 7094876465 ps
T418 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.259439489 Mar 12 12:28:02 PM PDT 24 Mar 12 12:28:14 PM PDT 24 8287811019 ps
T419 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.806229959 Mar 12 12:27:41 PM PDT 24 Mar 12 12:27:49 PM PDT 24 4240009556 ps

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.713036889
Short name T5
Test name
Test status
Simulation time 571058691044 ps
CPU time 748.25 seconds
Started Mar 12 12:52:31 PM PDT 24
Finished Mar 12 01:04:59 PM PDT 24
Peak memory 200900 kb
Host smart-88bf9ed8-cba5-4def-a4fa-cbdff7e9caf0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713036889 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.713036889
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.927366242
Short name T40
Test name
Test status
Simulation time 4404390332 ps
CPU time 8.06 seconds
Started Mar 12 12:27:58 PM PDT 24
Finished Mar 12 12:28:06 PM PDT 24
Peak memory 196772 kb
Host smart-66a99e48-d28c-4193-8b34-a8affc5dc921
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927366242 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_
intg_err.927366242
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/9.aon_timer_jump.1626072154
Short name T10
Test name
Test status
Simulation time 391538572 ps
CPU time 1.19 seconds
Started Mar 12 12:52:31 PM PDT 24
Finished Mar 12 12:52:33 PM PDT 24
Peak memory 183988 kb
Host smart-6b9d8aa9-cd6c-44ec-a81b-5635b50103b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626072154 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.1626072154
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.2195739854
Short name T32
Test name
Test status
Simulation time 300917501306 ps
CPU time 461.58 seconds
Started Mar 12 12:52:47 PM PDT 24
Finished Mar 12 01:00:28 PM PDT 24
Peak memory 198960 kb
Host smart-05b77298-59dd-4977-a7d5-b591e4d05462
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195739854 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.2195739854
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.107846848
Short name T24
Test name
Test status
Simulation time 319872943848 ps
CPU time 455 seconds
Started Mar 12 12:52:31 PM PDT 24
Finished Mar 12 01:00:07 PM PDT 24
Peak memory 198900 kb
Host smart-ab880516-fbd4-40bd-94e0-fb9623401531
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107846848 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.107846848
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.4018784433
Short name T16
Test name
Test status
Simulation time 7676307505 ps
CPU time 3.85 seconds
Started Mar 12 12:52:25 PM PDT 24
Finished Mar 12 12:52:29 PM PDT 24
Peak memory 215824 kb
Host smart-c3a978ea-e3e2-4b4a-8d25-31a180cf21a4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018784433 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.4018784433
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.468797311
Short name T91
Test name
Test status
Simulation time 143696451942 ps
CPU time 197.09 seconds
Started Mar 12 12:52:52 PM PDT 24
Finished Mar 12 12:56:10 PM PDT 24
Peak memory 184028 kb
Host smart-9b15ba77-efa2-4dd8-846f-26d0a73b85da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468797311 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_a
ll.468797311
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.803413996
Short name T102
Test name
Test status
Simulation time 4212679289 ps
CPU time 7.66 seconds
Started Mar 12 12:27:58 PM PDT 24
Finished Mar 12 12:28:06 PM PDT 24
Peak memory 196692 kb
Host smart-a7b6e5f4-8a8f-441b-aa06-57778aa24778
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803413996 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl
_intg_err.803413996
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.1267754260
Short name T54
Test name
Test status
Simulation time 469834843 ps
CPU time 1.96 seconds
Started Mar 12 12:27:45 PM PDT 24
Finished Mar 12 12:27:47 PM PDT 24
Peak memory 191540 kb
Host smart-0c7109eb-6960-406f-92be-243c89ff974a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267754260 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_b
it_bash.1267754260
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.1937997825
Short name T73
Test name
Test status
Simulation time 1821583574 ps
CPU time 3.6 seconds
Started Mar 12 12:27:49 PM PDT 24
Finished Mar 12 12:27:53 PM PDT 24
Peak memory 193928 kb
Host smart-4ed68f47-7310-4a3b-9406-076c40273a0e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937997825 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon
_timer_same_csr_outstanding.1937997825
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.259439489
Short name T418
Test name
Test status
Simulation time 8287811019 ps
CPU time 11.48 seconds
Started Mar 12 12:28:02 PM PDT 24
Finished Mar 12 12:28:14 PM PDT 24
Peak memory 197232 kb
Host smart-adeee2f2-8cea-45be-a5e3-238f42261b38
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259439489 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl
_intg_err.259439489
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.730740505
Short name T140
Test name
Test status
Simulation time 241631630981 ps
CPU time 83.2 seconds
Started Mar 12 12:52:45 PM PDT 24
Finished Mar 12 12:54:08 PM PDT 24
Peak memory 195600 kb
Host smart-102ce72d-6d9d-40b3-97da-a62156673b7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730740505 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_a
ll.730740505
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.1799258805
Short name T317
Test name
Test status
Simulation time 451583054 ps
CPU time 1.07 seconds
Started Mar 12 12:27:43 PM PDT 24
Finished Mar 12 12:27:44 PM PDT 24
Peak memory 183192 kb
Host smart-168a60b0-dfec-4c71-ae8c-1436d1796936
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799258805 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_a
liasing.1799258805
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.3528014367
Short name T330
Test name
Test status
Simulation time 1026946625 ps
CPU time 1.02 seconds
Started Mar 12 12:27:44 PM PDT 24
Finished Mar 12 12:27:46 PM PDT 24
Peak memory 183196 kb
Host smart-833fbfe7-cd93-4c80-b52b-9c7dfb94f4b3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528014367 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_h
w_reset.3528014367
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.2008890181
Short name T38
Test name
Test status
Simulation time 466762532 ps
CPU time 0.8 seconds
Started Mar 12 12:27:49 PM PDT 24
Finished Mar 12 12:27:50 PM PDT 24
Peak memory 195036 kb
Host smart-78994894-48f0-4a21-99ce-48bbd4a31547
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008890181 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.2008890181
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.568459342
Short name T62
Test name
Test status
Simulation time 482880184 ps
CPU time 0.62 seconds
Started Mar 12 12:27:42 PM PDT 24
Finished Mar 12 12:27:43 PM PDT 24
Peak memory 192388 kb
Host smart-7a756227-ce32-4769-b833-a5a63eaf1f66
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568459342 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.568459342
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.2191150889
Short name T326
Test name
Test status
Simulation time 506884205 ps
CPU time 1.28 seconds
Started Mar 12 12:27:46 PM PDT 24
Finished Mar 12 12:27:47 PM PDT 24
Peak memory 183164 kb
Host smart-55d0b83b-7adf-4808-aec4-855fdebc6fab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191150889 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.2191150889
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.932278279
Short name T412
Test name
Test status
Simulation time 288241844 ps
CPU time 0.99 seconds
Started Mar 12 12:27:40 PM PDT 24
Finished Mar 12 12:27:41 PM PDT 24
Peak memory 183300 kb
Host smart-b8a3c077-7949-483f-86c7-157bb93329ee
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932278279 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_ti
mer_mem_partial_access.932278279
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.1026132105
Short name T285
Test name
Test status
Simulation time 502896105 ps
CPU time 1.33 seconds
Started Mar 12 12:27:43 PM PDT 24
Finished Mar 12 12:27:44 PM PDT 24
Peak memory 182296 kb
Host smart-e69141e6-6ba0-43d6-95c7-8337646feffc
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026132105 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_w
alk.1026132105
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.586738262
Short name T403
Test name
Test status
Simulation time 2143870855 ps
CPU time 3.35 seconds
Started Mar 12 12:27:51 PM PDT 24
Finished Mar 12 12:27:55 PM PDT 24
Peak memory 191472 kb
Host smart-8f46e614-1393-4357-9d71-bc0d00b73661
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586738262 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_
timer_same_csr_outstanding.586738262
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.3345191410
Short name T372
Test name
Test status
Simulation time 626846836 ps
CPU time 1.69 seconds
Started Mar 12 12:27:50 PM PDT 24
Finished Mar 12 12:27:52 PM PDT 24
Peak memory 198100 kb
Host smart-8b7d59ad-d1c2-4de0-b105-4b3d51895689
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345191410 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.3345191410
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.806229959
Short name T419
Test name
Test status
Simulation time 4240009556 ps
CPU time 7.59 seconds
Started Mar 12 12:27:41 PM PDT 24
Finished Mar 12 12:27:49 PM PDT 24
Peak memory 196912 kb
Host smart-36b1e30f-83b4-408b-8f6d-c343629459bf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806229959 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_
intg_err.806229959
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.382005127
Short name T365
Test name
Test status
Simulation time 482700081 ps
CPU time 1.12 seconds
Started Mar 12 12:27:54 PM PDT 24
Finished Mar 12 12:27:55 PM PDT 24
Peak memory 193360 kb
Host smart-0d24ea67-2d11-4afc-854b-1e57bc997f19
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382005127 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_al
iasing.382005127
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.1296923367
Short name T65
Test name
Test status
Simulation time 11097951545 ps
CPU time 15.04 seconds
Started Mar 12 12:27:50 PM PDT 24
Finished Mar 12 12:28:06 PM PDT 24
Peak memory 195156 kb
Host smart-c0ca1347-804e-4a57-84dd-68dcd010afdb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296923367 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_b
it_bash.1296923367
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.3474929825
Short name T371
Test name
Test status
Simulation time 1314780774 ps
CPU time 2.95 seconds
Started Mar 12 12:27:53 PM PDT 24
Finished Mar 12 12:27:56 PM PDT 24
Peak memory 183228 kb
Host smart-a44015d6-68c9-4da1-a18a-afbdd224090d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474929825 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_h
w_reset.3474929825
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.2525630691
Short name T359
Test name
Test status
Simulation time 455040170 ps
CPU time 1.38 seconds
Started Mar 12 12:27:56 PM PDT 24
Finished Mar 12 12:27:58 PM PDT 24
Peak memory 195508 kb
Host smart-bc8509e2-d8f4-4f42-986a-5767bdcc9670
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525630691 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.2525630691
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.2073154605
Short name T72
Test name
Test status
Simulation time 549187152 ps
CPU time 0.76 seconds
Started Mar 12 12:27:49 PM PDT 24
Finished Mar 12 12:27:50 PM PDT 24
Peak memory 183364 kb
Host smart-dc9806a6-bdfa-4edd-963f-c1626d8d094f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073154605 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.2073154605
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.746841760
Short name T280
Test name
Test status
Simulation time 288583221 ps
CPU time 0.74 seconds
Started Mar 12 12:27:50 PM PDT 24
Finished Mar 12 12:27:51 PM PDT 24
Peak memory 183160 kb
Host smart-181e6010-18f6-49df-8025-5baee47fa7c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746841760 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.746841760
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.3321704967
Short name T332
Test name
Test status
Simulation time 371651887 ps
CPU time 0.7 seconds
Started Mar 12 12:27:48 PM PDT 24
Finished Mar 12 12:27:49 PM PDT 24
Peak memory 183164 kb
Host smart-759121e6-0ad3-4a16-91cf-701194f4bc93
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321704967 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_t
imer_mem_partial_access.3321704967
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.978940100
Short name T392
Test name
Test status
Simulation time 374433156 ps
CPU time 0.8 seconds
Started Mar 12 12:27:52 PM PDT 24
Finished Mar 12 12:27:53 PM PDT 24
Peak memory 182148 kb
Host smart-2d1cc3a9-9841-43e7-af75-122dda305c45
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978940100 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_wa
lk.978940100
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.487390499
Short name T354
Test name
Test status
Simulation time 1524357319 ps
CPU time 1.39 seconds
Started Mar 12 12:27:52 PM PDT 24
Finished Mar 12 12:27:54 PM PDT 24
Peak memory 198100 kb
Host smart-66e43617-db2d-4a2f-982e-a18f01c74b7c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487390499 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.487390499
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.2876502087
Short name T367
Test name
Test status
Simulation time 4754171910 ps
CPU time 4.06 seconds
Started Mar 12 12:27:51 PM PDT 24
Finished Mar 12 12:27:56 PM PDT 24
Peak memory 196868 kb
Host smart-4d6c77e8-e35b-4a1d-90ad-123df092e0c3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876502087 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl
_intg_err.2876502087
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.3149147957
Short name T349
Test name
Test status
Simulation time 387013356 ps
CPU time 0.81 seconds
Started Mar 12 12:28:02 PM PDT 24
Finished Mar 12 12:28:03 PM PDT 24
Peak memory 195176 kb
Host smart-79781297-3482-4c07-8188-822fd2d8f77a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149147957 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.3149147957
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.2989335371
Short name T405
Test name
Test status
Simulation time 438620481 ps
CPU time 0.94 seconds
Started Mar 12 12:28:03 PM PDT 24
Finished Mar 12 12:28:04 PM PDT 24
Peak memory 183332 kb
Host smart-a68479b6-5d22-4282-85b7-900594c0c2a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989335371 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.2989335371
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.2009967479
Short name T352
Test name
Test status
Simulation time 333799311 ps
CPU time 0.62 seconds
Started Mar 12 12:28:00 PM PDT 24
Finished Mar 12 12:28:01 PM PDT 24
Peak memory 183220 kb
Host smart-8dc69859-e047-48cb-901e-d5af13967fa7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009967479 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.2009967479
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.972060354
Short name T387
Test name
Test status
Simulation time 1402094932 ps
CPU time 1.17 seconds
Started Mar 12 12:28:04 PM PDT 24
Finished Mar 12 12:28:05 PM PDT 24
Peak memory 192692 kb
Host smart-fc892381-cfb6-44eb-b973-7ad05b9e2250
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972060354 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon
_timer_same_csr_outstanding.972060354
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.3573054644
Short name T321
Test name
Test status
Simulation time 546197315 ps
CPU time 1.95 seconds
Started Mar 12 12:28:00 PM PDT 24
Finished Mar 12 12:28:02 PM PDT 24
Peak memory 198024 kb
Host smart-816097f3-d77a-440f-9946-40368e67d1db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573054644 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.3573054644
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.669660344
Short name T305
Test name
Test status
Simulation time 8186108380 ps
CPU time 2.8 seconds
Started Mar 12 12:28:04 PM PDT 24
Finished Mar 12 12:28:07 PM PDT 24
Peak memory 197436 kb
Host smart-5db3b4d5-270a-4eac-8142-ca5173d31fdd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669660344 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl
_intg_err.669660344
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.4156414191
Short name T410
Test name
Test status
Simulation time 492913232 ps
CPU time 0.87 seconds
Started Mar 12 12:27:59 PM PDT 24
Finished Mar 12 12:28:01 PM PDT 24
Peak memory 196108 kb
Host smart-01d9f17e-a361-4652-a670-d0ed41bd9493
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156414191 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.4156414191
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.3064640376
Short name T64
Test name
Test status
Simulation time 403176783 ps
CPU time 0.76 seconds
Started Mar 12 12:28:00 PM PDT 24
Finished Mar 12 12:28:01 PM PDT 24
Peak memory 183196 kb
Host smart-0e329d18-92c6-46ce-a48f-6aa4a92de572
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064640376 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.3064640376
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.3195195827
Short name T328
Test name
Test status
Simulation time 353423004 ps
CPU time 1.11 seconds
Started Mar 12 12:27:59 PM PDT 24
Finished Mar 12 12:28:00 PM PDT 24
Peak memory 183124 kb
Host smart-511201ed-7a68-4ae4-9fbe-9c83e45ea4d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195195827 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.3195195827
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.618775363
Short name T398
Test name
Test status
Simulation time 1508511045 ps
CPU time 1.12 seconds
Started Mar 12 12:28:02 PM PDT 24
Finished Mar 12 12:28:03 PM PDT 24
Peak memory 183304 kb
Host smart-c27dfa43-09c9-4c7e-b709-d37af0e37b89
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618775363 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon
_timer_same_csr_outstanding.618775363
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.1852158646
Short name T334
Test name
Test status
Simulation time 353320429 ps
CPU time 1.85 seconds
Started Mar 12 12:28:09 PM PDT 24
Finished Mar 12 12:28:11 PM PDT 24
Peak memory 198104 kb
Host smart-31d11686-f573-494e-92e1-30c02ec84d1f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852158646 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.1852158646
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.2793571250
Short name T373
Test name
Test status
Simulation time 510790682 ps
CPU time 1.11 seconds
Started Mar 12 12:28:02 PM PDT 24
Finished Mar 12 12:28:04 PM PDT 24
Peak memory 196520 kb
Host smart-137a2c72-c42c-4c85-813f-4c667f3af7f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793571250 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.2793571250
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.1984658064
Short name T360
Test name
Test status
Simulation time 545928420 ps
CPU time 0.75 seconds
Started Mar 12 12:28:03 PM PDT 24
Finished Mar 12 12:28:04 PM PDT 24
Peak memory 183184 kb
Host smart-67a6350d-354c-4fd7-92d8-806a21b53bf5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984658064 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.1984658064
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.4029509486
Short name T286
Test name
Test status
Simulation time 453760335 ps
CPU time 0.97 seconds
Started Mar 12 12:28:00 PM PDT 24
Finished Mar 12 12:28:02 PM PDT 24
Peak memory 183132 kb
Host smart-bec2b150-1521-4c3f-a003-1746308e76a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029509486 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.4029509486
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.169354863
Short name T76
Test name
Test status
Simulation time 1313832063 ps
CPU time 3.3 seconds
Started Mar 12 12:28:04 PM PDT 24
Finished Mar 12 12:28:08 PM PDT 24
Peak memory 192716 kb
Host smart-6bf22677-f83a-4c9f-8084-13013f802a5e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169354863 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon
_timer_same_csr_outstanding.169354863
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.3276524219
Short name T282
Test name
Test status
Simulation time 866431021 ps
CPU time 1.95 seconds
Started Mar 12 12:28:02 PM PDT 24
Finished Mar 12 12:28:04 PM PDT 24
Peak memory 198024 kb
Host smart-d8142f6d-c2af-4e7a-ae14-6a7cfea66046
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276524219 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.3276524219
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.4268845689
Short name T394
Test name
Test status
Simulation time 8760178232 ps
CPU time 15.07 seconds
Started Mar 12 12:28:00 PM PDT 24
Finished Mar 12 12:28:15 PM PDT 24
Peak memory 197248 kb
Host smart-e07114bd-72c3-42fe-a744-4776b8be4f87
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268845689 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_t
l_intg_err.4268845689
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.282099922
Short name T312
Test name
Test status
Simulation time 484065410 ps
CPU time 1.46 seconds
Started Mar 12 12:28:01 PM PDT 24
Finished Mar 12 12:28:03 PM PDT 24
Peak memory 196248 kb
Host smart-305bca50-cb9b-428e-9fe8-509a15d0da03
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282099922 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.282099922
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.4010509620
Short name T380
Test name
Test status
Simulation time 394445591 ps
CPU time 0.71 seconds
Started Mar 12 12:28:00 PM PDT 24
Finished Mar 12 12:28:01 PM PDT 24
Peak memory 183240 kb
Host smart-6d7a5eed-a39e-4d69-9dd0-b781f471ead3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010509620 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.4010509620
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.343208374
Short name T413
Test name
Test status
Simulation time 478970561 ps
CPU time 1.33 seconds
Started Mar 12 12:28:11 PM PDT 24
Finished Mar 12 12:28:12 PM PDT 24
Peak memory 183096 kb
Host smart-7380be63-961d-40e2-808e-a2af069ff26e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343208374 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.343208374
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.3477854540
Short name T79
Test name
Test status
Simulation time 1899339514 ps
CPU time 2.28 seconds
Started Mar 12 12:28:12 PM PDT 24
Finished Mar 12 12:28:15 PM PDT 24
Peak memory 194108 kb
Host smart-773b999b-6abb-49f9-a845-e72e59662236
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477854540 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.ao
n_timer_same_csr_outstanding.3477854540
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.3729752076
Short name T297
Test name
Test status
Simulation time 508188423 ps
CPU time 2.74 seconds
Started Mar 12 12:28:11 PM PDT 24
Finished Mar 12 12:28:14 PM PDT 24
Peak memory 198104 kb
Host smart-9d6f90e3-de01-49f3-b380-c2de95cbe8a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729752076 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.3729752076
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.4148570404
Short name T386
Test name
Test status
Simulation time 975435693 ps
CPU time 1.26 seconds
Started Mar 12 12:28:14 PM PDT 24
Finished Mar 12 12:28:15 PM PDT 24
Peak memory 198096 kb
Host smart-408beb3e-e9da-4dfe-b42c-cb0a34083779
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148570404 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.4148570404
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.3344181856
Short name T361
Test name
Test status
Simulation time 419702509 ps
CPU time 1.18 seconds
Started Mar 12 12:28:08 PM PDT 24
Finished Mar 12 12:28:10 PM PDT 24
Peak memory 183252 kb
Host smart-fcbd034d-711c-4123-a6aa-d28e4fe1fe7e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344181856 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.3344181856
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.4253334395
Short name T414
Test name
Test status
Simulation time 518507007 ps
CPU time 0.72 seconds
Started Mar 12 12:28:01 PM PDT 24
Finished Mar 12 12:28:02 PM PDT 24
Peak memory 183164 kb
Host smart-50419e6c-76cb-42d8-b22a-e3a610eeefb7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253334395 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.4253334395
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.73990768
Short name T34
Test name
Test status
Simulation time 1767696061 ps
CPU time 1.64 seconds
Started Mar 12 12:28:04 PM PDT 24
Finished Mar 12 12:28:05 PM PDT 24
Peak memory 192868 kb
Host smart-66602a2e-10d8-42da-90a9-b969373503a5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73990768 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_
timer_same_csr_outstanding.73990768
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.3469901045
Short name T291
Test name
Test status
Simulation time 350915645 ps
CPU time 2.15 seconds
Started Mar 12 12:27:59 PM PDT 24
Finished Mar 12 12:28:02 PM PDT 24
Peak memory 198096 kb
Host smart-3cf795bf-d217-4f5d-8a7d-19b8a4028f8e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469901045 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.3469901045
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.91959987
Short name T356
Test name
Test status
Simulation time 4192146657 ps
CPU time 7.34 seconds
Started Mar 12 12:28:03 PM PDT 24
Finished Mar 12 12:28:10 PM PDT 24
Peak memory 196796 kb
Host smart-662a8d2f-928d-4c78-bdf2-be531dcb4317
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91959987 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_
intg_err.91959987
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.1511418016
Short name T303
Test name
Test status
Simulation time 427910942 ps
CPU time 0.94 seconds
Started Mar 12 12:28:13 PM PDT 24
Finished Mar 12 12:28:14 PM PDT 24
Peak memory 196604 kb
Host smart-55e17c27-38f8-4e1c-9553-60c10b536e4a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511418016 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.1511418016
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.1326746719
Short name T298
Test name
Test status
Simulation time 517964423 ps
CPU time 0.73 seconds
Started Mar 12 12:28:13 PM PDT 24
Finished Mar 12 12:28:14 PM PDT 24
Peak memory 183220 kb
Host smart-7216c2e1-5006-4bce-a600-65993ef4a779
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326746719 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.1326746719
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.3990529673
Short name T301
Test name
Test status
Simulation time 552385010 ps
CPU time 0.67 seconds
Started Mar 12 12:28:27 PM PDT 24
Finished Mar 12 12:28:28 PM PDT 24
Peak memory 183236 kb
Host smart-d90cb0b8-5adf-401f-9c51-5dda2eafceba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990529673 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.3990529673
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.2367325583
Short name T355
Test name
Test status
Simulation time 1296800794 ps
CPU time 1.25 seconds
Started Mar 12 12:28:17 PM PDT 24
Finished Mar 12 12:28:19 PM PDT 24
Peak memory 183308 kb
Host smart-8db8f6e2-5f52-4544-8ccd-137612eea4be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367325583 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.ao
n_timer_same_csr_outstanding.2367325583
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.305891052
Short name T343
Test name
Test status
Simulation time 1151904139 ps
CPU time 1.49 seconds
Started Mar 12 12:28:11 PM PDT 24
Finished Mar 12 12:28:13 PM PDT 24
Peak memory 198176 kb
Host smart-bae31779-62cc-4894-9ec1-718a2d6987c3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305891052 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.305891052
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.3005607748
Short name T100
Test name
Test status
Simulation time 8976144988 ps
CPU time 2.86 seconds
Started Mar 12 12:28:20 PM PDT 24
Finished Mar 12 12:28:23 PM PDT 24
Peak memory 197304 kb
Host smart-c4ae76f3-64c0-4257-8b71-d731979dad0f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005607748 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_t
l_intg_err.3005607748
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.1944156927
Short name T385
Test name
Test status
Simulation time 548451000 ps
CPU time 1.21 seconds
Started Mar 12 12:28:18 PM PDT 24
Finished Mar 12 12:28:19 PM PDT 24
Peak memory 195716 kb
Host smart-1be930d3-3edd-4bf9-8588-2996ca415903
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944156927 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.1944156927
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.3680436197
Short name T66
Test name
Test status
Simulation time 488121080 ps
CPU time 1.01 seconds
Started Mar 12 12:28:14 PM PDT 24
Finished Mar 12 12:28:15 PM PDT 24
Peak memory 183188 kb
Host smart-91cbb4ad-412c-4a79-b189-625adb7781d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680436197 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.3680436197
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.3354631711
Short name T316
Test name
Test status
Simulation time 425179330 ps
CPU time 0.71 seconds
Started Mar 12 12:28:13 PM PDT 24
Finished Mar 12 12:28:13 PM PDT 24
Peak memory 183156 kb
Host smart-fe6729c8-0407-4bdf-992d-2a63a3f09820
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354631711 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.3354631711
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.2590975469
Short name T307
Test name
Test status
Simulation time 1717386177 ps
CPU time 1.18 seconds
Started Mar 12 12:28:22 PM PDT 24
Finished Mar 12 12:28:23 PM PDT 24
Peak memory 192824 kb
Host smart-9ece1a74-75c9-48f3-b5c3-522713d1af57
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590975469 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.ao
n_timer_same_csr_outstanding.2590975469
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.741584019
Short name T366
Test name
Test status
Simulation time 538149719 ps
CPU time 2.89 seconds
Started Mar 12 12:28:10 PM PDT 24
Finished Mar 12 12:28:13 PM PDT 24
Peak memory 198096 kb
Host smart-954d2ec9-c29c-4484-8d02-e2a1fb6d5d22
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741584019 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.741584019
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.647869041
Short name T103
Test name
Test status
Simulation time 4107720146 ps
CPU time 8.51 seconds
Started Mar 12 12:28:09 PM PDT 24
Finished Mar 12 12:28:17 PM PDT 24
Peak memory 197180 kb
Host smart-6629927e-ffb7-44b7-b87b-fdfff0889d30
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647869041 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl
_intg_err.647869041
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.1179294394
Short name T308
Test name
Test status
Simulation time 506988117 ps
CPU time 1.05 seconds
Started Mar 12 12:28:15 PM PDT 24
Finished Mar 12 12:28:16 PM PDT 24
Peak memory 195252 kb
Host smart-70ed08ac-f83d-43fc-92fb-a7e179c1cf17
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179294394 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.1179294394
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.1554706390
Short name T35
Test name
Test status
Simulation time 516981741 ps
CPU time 0.64 seconds
Started Mar 12 12:28:14 PM PDT 24
Finished Mar 12 12:28:15 PM PDT 24
Peak memory 183240 kb
Host smart-80c58e11-7622-4a66-8c9f-a848f408d61c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554706390 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.1554706390
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.186740308
Short name T396
Test name
Test status
Simulation time 428039071 ps
CPU time 0.7 seconds
Started Mar 12 12:28:11 PM PDT 24
Finished Mar 12 12:28:12 PM PDT 24
Peak memory 183168 kb
Host smart-4e96cd60-6994-418b-a8c6-1a7ab80e5d9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186740308 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.186740308
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.443936224
Short name T415
Test name
Test status
Simulation time 2089937065 ps
CPU time 6.79 seconds
Started Mar 12 12:28:08 PM PDT 24
Finished Mar 12 12:28:16 PM PDT 24
Peak memory 194276 kb
Host smart-864339c3-f49d-431d-b5bc-a90aa1812bba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443936224 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon
_timer_same_csr_outstanding.443936224
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.2086571078
Short name T384
Test name
Test status
Simulation time 587157684 ps
CPU time 1.18 seconds
Started Mar 12 12:28:14 PM PDT 24
Finished Mar 12 12:28:16 PM PDT 24
Peak memory 197960 kb
Host smart-de19fe2d-6d22-485e-9958-7af5eb5036ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086571078 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.2086571078
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.2120852762
Short name T98
Test name
Test status
Simulation time 4109164149 ps
CPU time 2.19 seconds
Started Mar 12 12:28:14 PM PDT 24
Finished Mar 12 12:28:16 PM PDT 24
Peak memory 196920 kb
Host smart-880cfed3-63a1-4bfb-9a28-efb3f2ff4dcd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120852762 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_t
l_intg_err.2120852762
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.2735002630
Short name T408
Test name
Test status
Simulation time 476953936 ps
CPU time 1.03 seconds
Started Mar 12 12:28:18 PM PDT 24
Finished Mar 12 12:28:20 PM PDT 24
Peak memory 195268 kb
Host smart-a19026c7-e472-439d-b054-ffcfdfef9756
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735002630 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.2735002630
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.4108155798
Short name T383
Test name
Test status
Simulation time 387821408 ps
CPU time 0.64 seconds
Started Mar 12 12:28:21 PM PDT 24
Finished Mar 12 12:28:22 PM PDT 24
Peak memory 192680 kb
Host smart-beaee92e-c6e0-48de-ab26-aced8493879f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108155798 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.4108155798
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.742558256
Short name T324
Test name
Test status
Simulation time 488279812 ps
CPU time 0.95 seconds
Started Mar 12 12:28:25 PM PDT 24
Finished Mar 12 12:28:26 PM PDT 24
Peak memory 183148 kb
Host smart-4ade2cac-ab46-4909-b4c4-66c67030923c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742558256 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.742558256
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.1208186474
Short name T363
Test name
Test status
Simulation time 1207990517 ps
CPU time 1.15 seconds
Started Mar 12 12:28:11 PM PDT 24
Finished Mar 12 12:28:12 PM PDT 24
Peak memory 192780 kb
Host smart-720b3d15-35c7-4def-8c23-199bb165c6d6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208186474 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.ao
n_timer_same_csr_outstanding.1208186474
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.3214572896
Short name T284
Test name
Test status
Simulation time 445074371 ps
CPU time 1.91 seconds
Started Mar 12 12:28:20 PM PDT 24
Finished Mar 12 12:28:22 PM PDT 24
Peak memory 198000 kb
Host smart-01d7beee-62a0-4a46-a742-b4c88f071d1d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214572896 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.3214572896
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.570059682
Short name T41
Test name
Test status
Simulation time 8352249593 ps
CPU time 4.76 seconds
Started Mar 12 12:28:20 PM PDT 24
Finished Mar 12 12:28:25 PM PDT 24
Peak memory 197264 kb
Host smart-d4210b09-d2eb-46e5-b253-9124925360ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570059682 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl
_intg_err.570059682
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.3128230376
Short name T416
Test name
Test status
Simulation time 481643409 ps
CPU time 0.77 seconds
Started Mar 12 12:28:09 PM PDT 24
Finished Mar 12 12:28:10 PM PDT 24
Peak memory 194856 kb
Host smart-3800cc65-507c-4ce2-9ca9-4d6c468e2b41
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128230376 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.3128230376
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.2453989242
Short name T389
Test name
Test status
Simulation time 538594109 ps
CPU time 0.76 seconds
Started Mar 12 12:28:12 PM PDT 24
Finished Mar 12 12:28:13 PM PDT 24
Peak memory 183260 kb
Host smart-82008a15-74e8-454a-9c20-62c5c5b53192
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453989242 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.2453989242
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.3044148727
Short name T325
Test name
Test status
Simulation time 308438142 ps
CPU time 0.67 seconds
Started Mar 12 12:28:22 PM PDT 24
Finished Mar 12 12:28:23 PM PDT 24
Peak memory 183088 kb
Host smart-6bc28890-2224-45a0-891c-d348470b6a96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044148727 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.3044148727
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.2748508708
Short name T74
Test name
Test status
Simulation time 2504850900 ps
CPU time 3.92 seconds
Started Mar 12 12:28:10 PM PDT 24
Finished Mar 12 12:28:14 PM PDT 24
Peak memory 193644 kb
Host smart-ec22cb76-6019-4de4-8c13-e4dc1e773a25
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748508708 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao
n_timer_same_csr_outstanding.2748508708
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.2063966337
Short name T397
Test name
Test status
Simulation time 494199654 ps
CPU time 1.9 seconds
Started Mar 12 12:28:19 PM PDT 24
Finished Mar 12 12:28:22 PM PDT 24
Peak memory 198044 kb
Host smart-a78e94ac-a06c-49a8-a70c-0dd0f9ef6f6b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063966337 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.2063966337
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.472343791
Short name T42
Test name
Test status
Simulation time 4332431344 ps
CPU time 7.38 seconds
Started Mar 12 12:28:11 PM PDT 24
Finished Mar 12 12:28:19 PM PDT 24
Peak memory 195824 kb
Host smart-52bc2791-eac4-4706-ac82-7ec54b54d783
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472343791 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl
_intg_err.472343791
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.148811043
Short name T68
Test name
Test status
Simulation time 671129617 ps
CPU time 1.83 seconds
Started Mar 12 12:28:01 PM PDT 24
Finished Mar 12 12:28:04 PM PDT 24
Peak memory 183192 kb
Host smart-7bd6e397-edf2-4180-b64f-3b46e779a583
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148811043 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_al
iasing.148811043
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.4035900236
Short name T407
Test name
Test status
Simulation time 7213978530 ps
CPU time 6.92 seconds
Started Mar 12 12:27:50 PM PDT 24
Finished Mar 12 12:27:58 PM PDT 24
Peak memory 191688 kb
Host smart-d28189e2-2a47-4875-acee-f7f739418fef
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035900236 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_b
it_bash.4035900236
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.1506250351
Short name T376
Test name
Test status
Simulation time 1177949646 ps
CPU time 2.62 seconds
Started Mar 12 12:27:52 PM PDT 24
Finished Mar 12 12:27:55 PM PDT 24
Peak memory 183208 kb
Host smart-c824bd38-10f2-4218-b45e-f12a1759fca8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506250351 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_h
w_reset.1506250351
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.2517444289
Short name T402
Test name
Test status
Simulation time 489891954 ps
CPU time 0.78 seconds
Started Mar 12 12:27:50 PM PDT 24
Finished Mar 12 12:27:52 PM PDT 24
Peak memory 194812 kb
Host smart-6d9662f0-45cc-4552-b262-4825a03aed60
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517444289 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.2517444289
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.2487248960
Short name T63
Test name
Test status
Simulation time 400035091 ps
CPU time 1.27 seconds
Started Mar 12 12:27:56 PM PDT 24
Finished Mar 12 12:27:57 PM PDT 24
Peak memory 183440 kb
Host smart-9200122d-a39a-4051-987a-eab10b0f8fc6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487248960 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.2487248960
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.24297946
Short name T411
Test name
Test status
Simulation time 520758537 ps
CPU time 1.32 seconds
Started Mar 12 12:28:12 PM PDT 24
Finished Mar 12 12:28:13 PM PDT 24
Peak memory 183172 kb
Host smart-da13a936-4b0c-42d6-bfba-53231aa9ef31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24297946 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.24297946
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.3594305025
Short name T329
Test name
Test status
Simulation time 336141092 ps
CPU time 1.01 seconds
Started Mar 12 12:27:52 PM PDT 24
Finished Mar 12 12:27:54 PM PDT 24
Peak memory 183168 kb
Host smart-5a85b968-28e9-4d08-8590-7207555d3cd2
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594305025 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_t
imer_mem_partial_access.3594305025
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.4251227453
Short name T351
Test name
Test status
Simulation time 433408719 ps
CPU time 1.13 seconds
Started Mar 12 12:27:59 PM PDT 24
Finished Mar 12 12:28:00 PM PDT 24
Peak memory 182332 kb
Host smart-fa15557a-ca93-468e-abc5-b8a0ac545a96
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251227453 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_w
alk.4251227453
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.1611867394
Short name T333
Test name
Test status
Simulation time 2187431003 ps
CPU time 0.91 seconds
Started Mar 12 12:27:49 PM PDT 24
Finished Mar 12 12:27:49 PM PDT 24
Peak memory 194000 kb
Host smart-1ab76984-7f38-4343-8281-06493a7bd4ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611867394 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon
_timer_same_csr_outstanding.1611867394
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.1665433043
Short name T358
Test name
Test status
Simulation time 702704075 ps
CPU time 2.07 seconds
Started Mar 12 12:27:54 PM PDT 24
Finished Mar 12 12:27:56 PM PDT 24
Peak memory 198088 kb
Host smart-34f63d30-00ba-438a-814a-ed2ae1ffa47e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665433043 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.1665433043
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.3666255750
Short name T390
Test name
Test status
Simulation time 3905686481 ps
CPU time 2.17 seconds
Started Mar 12 12:27:51 PM PDT 24
Finished Mar 12 12:27:54 PM PDT 24
Peak memory 195816 kb
Host smart-1a6e3b5f-ff1b-4749-bdb5-a07b1aab608a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666255750 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl
_intg_err.3666255750
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.3243153515
Short name T340
Test name
Test status
Simulation time 486245099 ps
CPU time 1.32 seconds
Started Mar 12 12:28:13 PM PDT 24
Finished Mar 12 12:28:15 PM PDT 24
Peak memory 183124 kb
Host smart-8fcde4a3-3436-4173-8e09-a1ddbca8a25c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243153515 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.3243153515
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.689353551
Short name T400
Test name
Test status
Simulation time 385569512 ps
CPU time 0.77 seconds
Started Mar 12 12:28:11 PM PDT 24
Finished Mar 12 12:28:12 PM PDT 24
Peak memory 183192 kb
Host smart-f5179d06-4b57-444f-ab51-6bc7b3a512bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689353551 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.689353551
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.2943325085
Short name T388
Test name
Test status
Simulation time 423086252 ps
CPU time 0.77 seconds
Started Mar 12 12:28:22 PM PDT 24
Finished Mar 12 12:28:23 PM PDT 24
Peak memory 183076 kb
Host smart-8b5f29a0-8ad3-4e5b-85dd-22c0c9376791
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943325085 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.2943325085
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.3865781617
Short name T314
Test name
Test status
Simulation time 315105446 ps
CPU time 1.03 seconds
Started Mar 12 12:28:18 PM PDT 24
Finished Mar 12 12:28:20 PM PDT 24
Peak memory 183228 kb
Host smart-ae3f566a-ca15-4b69-badc-bb88b8d3a819
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865781617 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.3865781617
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.2228200519
Short name T395
Test name
Test status
Simulation time 304351058 ps
CPU time 0.67 seconds
Started Mar 12 12:28:17 PM PDT 24
Finished Mar 12 12:28:17 PM PDT 24
Peak memory 183296 kb
Host smart-2cec93f7-a3f4-4da9-b5be-c5819aaffbdf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228200519 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.2228200519
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.2494791637
Short name T381
Test name
Test status
Simulation time 287527428 ps
CPU time 0.64 seconds
Started Mar 12 12:28:14 PM PDT 24
Finished Mar 12 12:28:15 PM PDT 24
Peak memory 183208 kb
Host smart-b27a0bdd-7845-4719-bb06-2dbec5d31626
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494791637 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.2494791637
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.3738909245
Short name T345
Test name
Test status
Simulation time 430889237 ps
CPU time 1.23 seconds
Started Mar 12 12:28:17 PM PDT 24
Finished Mar 12 12:28:19 PM PDT 24
Peak memory 183196 kb
Host smart-64c6537b-445f-4857-940c-fbb366de6be7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738909245 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.3738909245
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.2814812368
Short name T331
Test name
Test status
Simulation time 505584854 ps
CPU time 1.31 seconds
Started Mar 12 12:28:09 PM PDT 24
Finished Mar 12 12:28:10 PM PDT 24
Peak memory 183168 kb
Host smart-7280b265-0f3a-4373-a616-918377d94c6d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814812368 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.2814812368
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.1416120817
Short name T342
Test name
Test status
Simulation time 426799468 ps
CPU time 0.65 seconds
Started Mar 12 12:28:11 PM PDT 24
Finished Mar 12 12:28:12 PM PDT 24
Peak memory 183192 kb
Host smart-a656fbf7-7463-4ca3-84e5-a004dac82cb2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416120817 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.1416120817
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.1610056427
Short name T296
Test name
Test status
Simulation time 337461809 ps
CPU time 0.96 seconds
Started Mar 12 12:28:20 PM PDT 24
Finished Mar 12 12:28:21 PM PDT 24
Peak memory 183208 kb
Host smart-5c641a29-ec2c-4ee7-b6b5-f7a92c9f999d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610056427 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.1610056427
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.159600935
Short name T51
Test name
Test status
Simulation time 619165822 ps
CPU time 0.85 seconds
Started Mar 12 12:27:49 PM PDT 24
Finished Mar 12 12:27:50 PM PDT 24
Peak memory 183388 kb
Host smart-211911e6-8bea-4062-aa70-c559ec5b13e0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159600935 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_al
iasing.159600935
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.1501709864
Short name T50
Test name
Test status
Simulation time 10529998028 ps
CPU time 5.73 seconds
Started Mar 12 12:27:51 PM PDT 24
Finished Mar 12 12:27:58 PM PDT 24
Peak memory 191600 kb
Host smart-ca4171d7-9b07-4f40-8b94-c1d51f55a8d4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501709864 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_b
it_bash.1501709864
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.3148468489
Short name T53
Test name
Test status
Simulation time 1115236427 ps
CPU time 2.29 seconds
Started Mar 12 12:27:52 PM PDT 24
Finished Mar 12 12:27:55 PM PDT 24
Peak memory 192560 kb
Host smart-a03e02c0-901c-49cd-9e15-c2238fbb8aaa
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148468489 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_h
w_reset.3148468489
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.1336357620
Short name T319
Test name
Test status
Simulation time 586496526 ps
CPU time 1.72 seconds
Started Mar 12 12:28:02 PM PDT 24
Finished Mar 12 12:28:04 PM PDT 24
Peak memory 196412 kb
Host smart-599a3d08-d57a-4a71-8218-e38fb71c4be5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336357620 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.1336357620
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.250944791
Short name T52
Test name
Test status
Simulation time 358977870 ps
CPU time 1.02 seconds
Started Mar 12 12:28:10 PM PDT 24
Finished Mar 12 12:28:11 PM PDT 24
Peak memory 183288 kb
Host smart-1cd59739-d94b-41e6-9ff0-7070a1d23a4e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250944791 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.250944791
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.1639309631
Short name T339
Test name
Test status
Simulation time 496111834 ps
CPU time 1.25 seconds
Started Mar 12 12:27:49 PM PDT 24
Finished Mar 12 12:27:50 PM PDT 24
Peak memory 183116 kb
Host smart-a08f5f2f-cc7f-4e4f-bf8f-54fffc94c894
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639309631 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.1639309631
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.2219109626
Short name T304
Test name
Test status
Simulation time 331460528 ps
CPU time 1.04 seconds
Started Mar 12 12:27:55 PM PDT 24
Finished Mar 12 12:27:56 PM PDT 24
Peak memory 182400 kb
Host smart-8c5207f4-60d2-4ac9-ac75-52d438e6edb4
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219109626 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_t
imer_mem_partial_access.2219109626
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.574922014
Short name T368
Test name
Test status
Simulation time 405305920 ps
CPU time 0.58 seconds
Started Mar 12 12:27:55 PM PDT 24
Finished Mar 12 12:27:56 PM PDT 24
Peak memory 182272 kb
Host smart-1aac25ab-333b-413c-b930-45d31f6593bf
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574922014 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_wa
lk.574922014
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.800670475
Short name T77
Test name
Test status
Simulation time 1199243946 ps
CPU time 2.36 seconds
Started Mar 12 12:27:52 PM PDT 24
Finished Mar 12 12:27:55 PM PDT 24
Peak memory 192896 kb
Host smart-dc0559d7-a17a-4719-9b5c-5151ebccfd1a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800670475 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_
timer_same_csr_outstanding.800670475
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.1136413165
Short name T290
Test name
Test status
Simulation time 707641800 ps
CPU time 2.25 seconds
Started Mar 12 12:27:59 PM PDT 24
Finished Mar 12 12:28:01 PM PDT 24
Peak memory 198076 kb
Host smart-c9a332f5-db5b-4afa-9c1b-6a9f4736d38a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136413165 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.1136413165
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.4216067032
Short name T99
Test name
Test status
Simulation time 8661150826 ps
CPU time 14.29 seconds
Started Mar 12 12:27:52 PM PDT 24
Finished Mar 12 12:28:07 PM PDT 24
Peak memory 197208 kb
Host smart-4186d58f-6479-46ed-8c66-b10ebfc9db03
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216067032 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl
_intg_err.4216067032
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.72903639
Short name T364
Test name
Test status
Simulation time 377272176 ps
CPU time 1.08 seconds
Started Mar 12 12:28:13 PM PDT 24
Finished Mar 12 12:28:14 PM PDT 24
Peak memory 183144 kb
Host smart-55fce8e0-a2c8-4e73-9cb5-8e865cc069cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72903639 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.72903639
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.512013374
Short name T311
Test name
Test status
Simulation time 514582415 ps
CPU time 0.71 seconds
Started Mar 12 12:28:20 PM PDT 24
Finished Mar 12 12:28:20 PM PDT 24
Peak memory 183168 kb
Host smart-a62efcc4-e654-49d4-bce2-3a48e55b9d5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512013374 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.512013374
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.3911051444
Short name T341
Test name
Test status
Simulation time 422288004 ps
CPU time 0.55 seconds
Started Mar 12 12:28:13 PM PDT 24
Finished Mar 12 12:28:14 PM PDT 24
Peak memory 183212 kb
Host smart-7c4ffe6d-260a-4ffb-aefe-df5749bc167e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911051444 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.3911051444
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.2276008844
Short name T404
Test name
Test status
Simulation time 331852144 ps
CPU time 0.76 seconds
Started Mar 12 12:28:30 PM PDT 24
Finished Mar 12 12:28:31 PM PDT 24
Peak memory 183148 kb
Host smart-483bb9bf-a768-4b08-bc42-030d197197b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276008844 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.2276008844
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.1899068588
Short name T294
Test name
Test status
Simulation time 519292344 ps
CPU time 0.92 seconds
Started Mar 12 12:28:24 PM PDT 24
Finished Mar 12 12:28:25 PM PDT 24
Peak memory 183152 kb
Host smart-624b8372-1f2f-4edb-814f-1e1a205fa405
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899068588 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.1899068588
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.2934607022
Short name T292
Test name
Test status
Simulation time 335644280 ps
CPU time 1 seconds
Started Mar 12 12:28:26 PM PDT 24
Finished Mar 12 12:28:27 PM PDT 24
Peak memory 183148 kb
Host smart-a1ed7df7-f8e3-4512-a194-c74f6bbb5081
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934607022 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.2934607022
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.1639098423
Short name T327
Test name
Test status
Simulation time 494340689 ps
CPU time 1.35 seconds
Started Mar 12 12:28:24 PM PDT 24
Finished Mar 12 12:28:25 PM PDT 24
Peak memory 183168 kb
Host smart-724512af-c554-4c79-a26a-ef820a1df776
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639098423 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.1639098423
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.432244275
Short name T335
Test name
Test status
Simulation time 492019376 ps
CPU time 0.71 seconds
Started Mar 12 12:28:29 PM PDT 24
Finished Mar 12 12:28:30 PM PDT 24
Peak memory 183168 kb
Host smart-da34f919-dcce-4090-825a-a098939ca62f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432244275 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.432244275
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.4263903909
Short name T379
Test name
Test status
Simulation time 471178131 ps
CPU time 1.26 seconds
Started Mar 12 12:28:24 PM PDT 24
Finished Mar 12 12:28:25 PM PDT 24
Peak memory 183192 kb
Host smart-2eef6e62-5ac5-409e-9d5e-22ee48f095a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263903909 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.4263903909
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.1942266721
Short name T357
Test name
Test status
Simulation time 427026067 ps
CPU time 1.24 seconds
Started Mar 12 12:28:23 PM PDT 24
Finished Mar 12 12:28:25 PM PDT 24
Peak memory 183236 kb
Host smart-585484bb-0358-4474-846e-81ffba6704ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942266721 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.1942266721
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.1548605356
Short name T67
Test name
Test status
Simulation time 571295605 ps
CPU time 1.58 seconds
Started Mar 12 12:27:56 PM PDT 24
Finished Mar 12 12:27:57 PM PDT 24
Peak memory 183240 kb
Host smart-4809627a-6ff6-4534-a9b7-ef00c108ae74
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548605356 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_a
liasing.1548605356
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.202442696
Short name T417
Test name
Test status
Simulation time 7094876465 ps
CPU time 5.03 seconds
Started Mar 12 12:27:52 PM PDT 24
Finished Mar 12 12:27:58 PM PDT 24
Peak memory 195072 kb
Host smart-93e13efb-050a-441a-9d5c-23f5318212f9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202442696 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_bi
t_bash.202442696
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.3709461341
Short name T49
Test name
Test status
Simulation time 1069654531 ps
CPU time 2.37 seconds
Started Mar 12 12:27:56 PM PDT 24
Finished Mar 12 12:27:58 PM PDT 24
Peak memory 183236 kb
Host smart-26d14b8d-33b9-4e65-b47f-931e77c55217
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709461341 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_h
w_reset.3709461341
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.1240310152
Short name T300
Test name
Test status
Simulation time 526577911 ps
CPU time 1.56 seconds
Started Mar 12 12:28:02 PM PDT 24
Finished Mar 12 12:28:04 PM PDT 24
Peak memory 195304 kb
Host smart-71ac4e63-7b51-4e37-9ada-4444f602d9f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240310152 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.1240310152
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.2868416621
Short name T347
Test name
Test status
Simulation time 348544745 ps
CPU time 0.76 seconds
Started Mar 12 12:27:52 PM PDT 24
Finished Mar 12 12:27:53 PM PDT 24
Peak memory 183184 kb
Host smart-a8e63ce8-1875-431f-b5c0-186100e17f17
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868416621 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.2868416621
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.3845638076
Short name T299
Test name
Test status
Simulation time 363093939 ps
CPU time 1.07 seconds
Started Mar 12 12:27:55 PM PDT 24
Finished Mar 12 12:27:56 PM PDT 24
Peak memory 183196 kb
Host smart-1e4a34d1-bd36-48b0-a4cd-44de9f4a4a6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845638076 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.3845638076
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.1428388320
Short name T313
Test name
Test status
Simulation time 419167080 ps
CPU time 0.67 seconds
Started Mar 12 12:27:52 PM PDT 24
Finished Mar 12 12:27:53 PM PDT 24
Peak memory 183320 kb
Host smart-2c83b728-2f43-4cfc-8db7-1e0f58c6cb7a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428388320 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_t
imer_mem_partial_access.1428388320
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.1692015235
Short name T320
Test name
Test status
Simulation time 379805504 ps
CPU time 1.05 seconds
Started Mar 12 12:27:51 PM PDT 24
Finished Mar 12 12:27:53 PM PDT 24
Peak memory 182336 kb
Host smart-7c6a8529-b91a-477e-97c9-954aa17a540e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692015235 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_w
alk.1692015235
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.3563460198
Short name T409
Test name
Test status
Simulation time 1162404793 ps
CPU time 2.73 seconds
Started Mar 12 12:27:56 PM PDT 24
Finished Mar 12 12:27:59 PM PDT 24
Peak memory 192724 kb
Host smart-ec660c9e-62cf-478a-b1cb-96a94d42812d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563460198 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon
_timer_same_csr_outstanding.3563460198
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.2544005964
Short name T281
Test name
Test status
Simulation time 356319502 ps
CPU time 2.46 seconds
Started Mar 12 12:27:50 PM PDT 24
Finished Mar 12 12:27:53 PM PDT 24
Peak memory 198060 kb
Host smart-97946631-fec6-4622-9c46-7962406ea17b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544005964 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.2544005964
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.1332144238
Short name T322
Test name
Test status
Simulation time 4672372690 ps
CPU time 2.01 seconds
Started Mar 12 12:34:55 PM PDT 24
Finished Mar 12 12:35:01 PM PDT 24
Peak memory 196752 kb
Host smart-e100eee7-46fa-4292-bd3e-7c58a0a1ac50
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332144238 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl
_intg_err.1332144238
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.1235156124
Short name T283
Test name
Test status
Simulation time 398847459 ps
CPU time 0.82 seconds
Started Mar 12 12:28:21 PM PDT 24
Finished Mar 12 12:28:22 PM PDT 24
Peak memory 183112 kb
Host smart-c8891c9a-a7c8-4530-89c6-cb92d7d7f5f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235156124 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.1235156124
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.2983231348
Short name T391
Test name
Test status
Simulation time 380529080 ps
CPU time 0.68 seconds
Started Mar 12 12:28:27 PM PDT 24
Finished Mar 12 12:28:28 PM PDT 24
Peak memory 183136 kb
Host smart-7b53e0e1-eb4e-4107-bf9a-e07e834bb868
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983231348 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.2983231348
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.3383588126
Short name T295
Test name
Test status
Simulation time 285766080 ps
CPU time 0.67 seconds
Started Mar 12 12:28:23 PM PDT 24
Finished Mar 12 12:28:24 PM PDT 24
Peak memory 183168 kb
Host smart-87ce650b-3c35-4686-9ed1-d531ebce9c57
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383588126 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.3383588126
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.1645416994
Short name T346
Test name
Test status
Simulation time 601888929 ps
CPU time 0.58 seconds
Started Mar 12 12:28:22 PM PDT 24
Finished Mar 12 12:28:23 PM PDT 24
Peak memory 183168 kb
Host smart-d8b811db-10a8-4321-949e-e9a8452024f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645416994 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.1645416994
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.3207543033
Short name T336
Test name
Test status
Simulation time 304938935 ps
CPU time 0.95 seconds
Started Mar 12 12:28:23 PM PDT 24
Finished Mar 12 12:28:24 PM PDT 24
Peak memory 183232 kb
Host smart-11ce3d7f-5d6f-4ef3-acc3-07640ddb1c6d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207543033 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.3207543033
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.3280665766
Short name T288
Test name
Test status
Simulation time 310554153 ps
CPU time 0.6 seconds
Started Mar 12 12:28:23 PM PDT 24
Finished Mar 12 12:28:23 PM PDT 24
Peak memory 183212 kb
Host smart-5f04487c-46b8-4ffa-8403-b1d726143bb0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280665766 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.3280665766
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.32381399
Short name T289
Test name
Test status
Simulation time 363207814 ps
CPU time 1.11 seconds
Started Mar 12 12:28:23 PM PDT 24
Finished Mar 12 12:28:24 PM PDT 24
Peak memory 183324 kb
Host smart-45cb604e-3c4c-4590-849f-a0008b42cd11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32381399 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.32381399
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.3361662427
Short name T382
Test name
Test status
Simulation time 442297590 ps
CPU time 0.75 seconds
Started Mar 12 12:28:28 PM PDT 24
Finished Mar 12 12:28:29 PM PDT 24
Peak memory 183264 kb
Host smart-2de1803b-a24f-4eea-9551-e2e344648421
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361662427 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.3361662427
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.595913917
Short name T315
Test name
Test status
Simulation time 387244545 ps
CPU time 0.74 seconds
Started Mar 12 12:28:26 PM PDT 24
Finished Mar 12 12:28:27 PM PDT 24
Peak memory 183132 kb
Host smart-92bcbf7f-ac2a-4bf4-bfd8-8312c5e92ee9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595913917 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.595913917
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.574218045
Short name T323
Test name
Test status
Simulation time 372126151 ps
CPU time 0.98 seconds
Started Mar 12 12:28:26 PM PDT 24
Finished Mar 12 12:28:28 PM PDT 24
Peak memory 183132 kb
Host smart-7df0ba85-7c51-49c3-a3b6-eeb3cb1eddac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574218045 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.574218045
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.879865858
Short name T350
Test name
Test status
Simulation time 689233375 ps
CPU time 0.93 seconds
Started Mar 12 12:28:00 PM PDT 24
Finished Mar 12 12:28:02 PM PDT 24
Peak memory 197584 kb
Host smart-c6941350-d08c-464d-8bed-78322b075757
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879865858 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.879865858
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.14507859
Short name T406
Test name
Test status
Simulation time 503749864 ps
CPU time 1.37 seconds
Started Mar 12 12:27:59 PM PDT 24
Finished Mar 12 12:28:01 PM PDT 24
Peak memory 183360 kb
Host smart-89225cbc-324f-44da-9702-cd36b4f6cc55
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14507859 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.14507859
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.2385314239
Short name T309
Test name
Test status
Simulation time 377220178 ps
CPU time 1.08 seconds
Started Mar 12 12:27:56 PM PDT 24
Finished Mar 12 12:27:57 PM PDT 24
Peak memory 183136 kb
Host smart-7fdee5c5-a862-4fc0-8fee-65b2f100b818
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385314239 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.2385314239
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.2788941773
Short name T75
Test name
Test status
Simulation time 2354932633 ps
CPU time 1.74 seconds
Started Mar 12 12:28:09 PM PDT 24
Finished Mar 12 12:28:11 PM PDT 24
Peak memory 194236 kb
Host smart-df5ee212-7a0e-40e0-a5cb-6df63aa29b5b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788941773 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon
_timer_same_csr_outstanding.2788941773
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.2178024547
Short name T310
Test name
Test status
Simulation time 511487361 ps
CPU time 1.62 seconds
Started Mar 12 12:27:53 PM PDT 24
Finished Mar 12 12:27:55 PM PDT 24
Peak memory 198620 kb
Host smart-bafcb1f8-5e62-4940-8fd4-dc8e310fe81f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178024547 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.2178024547
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.1853856309
Short name T374
Test name
Test status
Simulation time 8459491567 ps
CPU time 6.86 seconds
Started Mar 12 12:27:51 PM PDT 24
Finished Mar 12 12:27:59 PM PDT 24
Peak memory 197572 kb
Host smart-65b2460f-19a7-4498-a98f-f8958164a553
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853856309 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl
_intg_err.1853856309
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.471849278
Short name T375
Test name
Test status
Simulation time 552171512 ps
CPU time 1.63 seconds
Started Mar 12 12:28:00 PM PDT 24
Finished Mar 12 12:28:02 PM PDT 24
Peak memory 195476 kb
Host smart-54c60672-7eb1-43e3-a6f0-07dbc09a350c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471849278 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.471849278
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.3364801771
Short name T318
Test name
Test status
Simulation time 347503471 ps
CPU time 0.92 seconds
Started Mar 12 12:27:59 PM PDT 24
Finished Mar 12 12:28:00 PM PDT 24
Peak memory 183416 kb
Host smart-454a34ea-7a7e-43b6-a3e9-49ccdf72ec40
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364801771 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.3364801771
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.910838496
Short name T378
Test name
Test status
Simulation time 398002791 ps
CPU time 0.83 seconds
Started Mar 12 12:28:03 PM PDT 24
Finished Mar 12 12:28:03 PM PDT 24
Peak memory 183104 kb
Host smart-b3995da2-d9c3-47c7-85e9-72b228fa4f65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910838496 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.910838496
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.3385556923
Short name T393
Test name
Test status
Simulation time 1172566512 ps
CPU time 1.64 seconds
Started Mar 12 12:28:02 PM PDT 24
Finished Mar 12 12:28:04 PM PDT 24
Peak memory 192656 kb
Host smart-cc97ba54-d125-4da3-afa0-c584d3734dd4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385556923 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon
_timer_same_csr_outstanding.3385556923
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.1021807874
Short name T370
Test name
Test status
Simulation time 748661993 ps
CPU time 1.68 seconds
Started Mar 12 12:28:02 PM PDT 24
Finished Mar 12 12:28:04 PM PDT 24
Peak memory 198040 kb
Host smart-d273c5b9-f4fb-4647-b905-dffd52fcfc21
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021807874 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.1021807874
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.1887619890
Short name T344
Test name
Test status
Simulation time 601038438 ps
CPU time 0.85 seconds
Started Mar 12 12:28:11 PM PDT 24
Finished Mar 12 12:28:12 PM PDT 24
Peak memory 194940 kb
Host smart-f7353681-57f8-4094-b8af-bdb9327f82df
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887619890 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.1887619890
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.904387919
Short name T78
Test name
Test status
Simulation time 399752758 ps
CPU time 0.72 seconds
Started Mar 12 12:28:01 PM PDT 24
Finished Mar 12 12:28:02 PM PDT 24
Peak memory 183284 kb
Host smart-b572b2f4-25a1-495b-86b2-61c7d8547d93
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904387919 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.904387919
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.739109197
Short name T337
Test name
Test status
Simulation time 319626333 ps
CPU time 1.01 seconds
Started Mar 12 12:28:00 PM PDT 24
Finished Mar 12 12:28:02 PM PDT 24
Peak memory 183160 kb
Host smart-728b5ae5-8cd6-4ec7-87db-17f7cb161320
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739109197 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.739109197
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.4190005218
Short name T39
Test name
Test status
Simulation time 2195478234 ps
CPU time 1.98 seconds
Started Mar 12 12:28:16 PM PDT 24
Finished Mar 12 12:28:18 PM PDT 24
Peak memory 194244 kb
Host smart-d000ddb1-382c-4a4a-8a3d-90fbc0bff728
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190005218 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon
_timer_same_csr_outstanding.4190005218
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.1543941601
Short name T306
Test name
Test status
Simulation time 421594890 ps
CPU time 2.53 seconds
Started Mar 12 12:28:05 PM PDT 24
Finished Mar 12 12:28:09 PM PDT 24
Peak memory 197012 kb
Host smart-b389c8e1-95e4-4e23-aab9-fe62bb26c741
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543941601 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.1543941601
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.2160678406
Short name T338
Test name
Test status
Simulation time 4433500365 ps
CPU time 7.13 seconds
Started Mar 12 12:28:08 PM PDT 24
Finished Mar 12 12:28:15 PM PDT 24
Peak memory 197044 kb
Host smart-4498245b-53b8-471a-b36a-1c659a40507b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160678406 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl
_intg_err.2160678406
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.4055370860
Short name T348
Test name
Test status
Simulation time 345309037 ps
CPU time 1.26 seconds
Started Mar 12 12:28:16 PM PDT 24
Finished Mar 12 12:28:17 PM PDT 24
Peak memory 195600 kb
Host smart-7cb4cfe2-9e09-47f5-9399-6afe65d4cfac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055370860 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.4055370860
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.430293894
Short name T401
Test name
Test status
Simulation time 358429226 ps
CPU time 0.81 seconds
Started Mar 12 12:38:04 PM PDT 24
Finished Mar 12 12:38:05 PM PDT 24
Peak memory 183428 kb
Host smart-dbc4116b-54cc-477a-a82a-f1d3c679f138
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430293894 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.430293894
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.110523998
Short name T293
Test name
Test status
Simulation time 482647373 ps
CPU time 0.59 seconds
Started Mar 12 12:28:02 PM PDT 24
Finished Mar 12 12:28:03 PM PDT 24
Peak memory 183168 kb
Host smart-f1dc0bb7-7381-49e3-858b-64f6de472e68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110523998 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.110523998
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.3381054578
Short name T399
Test name
Test status
Simulation time 2829931818 ps
CPU time 2.55 seconds
Started Mar 12 12:28:04 PM PDT 24
Finished Mar 12 12:28:07 PM PDT 24
Peak memory 194100 kb
Host smart-81f0272f-63eb-4029-8dec-f9bfc641a154
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381054578 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon
_timer_same_csr_outstanding.3381054578
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.1185931041
Short name T362
Test name
Test status
Simulation time 368972492 ps
CPU time 1.37 seconds
Started Mar 12 12:28:02 PM PDT 24
Finished Mar 12 12:28:04 PM PDT 24
Peak memory 197964 kb
Host smart-30caa451-0053-45dd-afb3-a4b37e47b1e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185931041 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.1185931041
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.3608283237
Short name T101
Test name
Test status
Simulation time 4284099329 ps
CPU time 2.62 seconds
Started Mar 12 12:27:59 PM PDT 24
Finished Mar 12 12:28:02 PM PDT 24
Peak memory 196908 kb
Host smart-a4c8efad-5f4f-409a-95f4-6be454d44cda
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608283237 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl
_intg_err.3608283237
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.363282628
Short name T302
Test name
Test status
Simulation time 622207309 ps
CPU time 1.2 seconds
Started Mar 12 12:28:11 PM PDT 24
Finished Mar 12 12:28:12 PM PDT 24
Peak memory 197964 kb
Host smart-8a3eda78-f0f8-4d50-902f-d74b75f1ad5a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363282628 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.363282628
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.2300665327
Short name T33
Test name
Test status
Simulation time 635422610 ps
CPU time 0.66 seconds
Started Mar 12 12:28:00 PM PDT 24
Finished Mar 12 12:28:01 PM PDT 24
Peak memory 183372 kb
Host smart-34bb722e-be5e-4f03-9ba0-0dab28169a9e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300665327 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.2300665327
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.3027780723
Short name T377
Test name
Test status
Simulation time 497642619 ps
CPU time 1.27 seconds
Started Mar 12 12:28:02 PM PDT 24
Finished Mar 12 12:28:04 PM PDT 24
Peak memory 183112 kb
Host smart-8f9521e8-e24d-4776-af25-5b5dfbb6ed6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027780723 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.3027780723
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.2155563084
Short name T353
Test name
Test status
Simulation time 2194036302 ps
CPU time 1.93 seconds
Started Mar 12 12:28:05 PM PDT 24
Finished Mar 12 12:28:08 PM PDT 24
Peak memory 191984 kb
Host smart-21322fb6-7894-4b7c-807a-52d9525b5324
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155563084 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon
_timer_same_csr_outstanding.2155563084
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.5754760
Short name T287
Test name
Test status
Simulation time 366061707 ps
CPU time 2 seconds
Started Mar 12 12:28:00 PM PDT 24
Finished Mar 12 12:28:02 PM PDT 24
Peak memory 198040 kb
Host smart-be489bc8-3b9c-4a00-bf58-c3a456695754
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5754760 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.5754760
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.664593519
Short name T369
Test name
Test status
Simulation time 4587361952 ps
CPU time 8.49 seconds
Started Mar 12 12:28:11 PM PDT 24
Finished Mar 12 12:28:19 PM PDT 24
Peak memory 197188 kb
Host smart-84cd2509-b152-4609-8658-3437db004341
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664593519 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_
intg_err.664593519
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_jump.1735085855
Short name T47
Test name
Test status
Simulation time 469411088 ps
CPU time 0.95 seconds
Started Mar 12 12:52:12 PM PDT 24
Finished Mar 12 12:52:13 PM PDT 24
Peak memory 183964 kb
Host smart-3282ccb7-f5ad-4e77-9d1c-6d744daa3b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735085855 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.1735085855
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.1429234104
Short name T234
Test name
Test status
Simulation time 60138383252 ps
CPU time 76.22 seconds
Started Mar 12 12:52:14 PM PDT 24
Finished Mar 12 12:53:31 PM PDT 24
Peak memory 184080 kb
Host smart-79944b1a-ece5-49b5-b5ec-51ec77166eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429234104 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.1429234104
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.2540537464
Short name T272
Test name
Test status
Simulation time 427354429 ps
CPU time 1.22 seconds
Started Mar 12 12:52:15 PM PDT 24
Finished Mar 12 12:52:16 PM PDT 24
Peak memory 183832 kb
Host smart-f2a802d2-f748-4444-ba6a-4608ae54f079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540537464 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.2540537464
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.617763786
Short name T181
Test name
Test status
Simulation time 92521292061 ps
CPU time 69.54 seconds
Started Mar 12 12:52:22 PM PDT 24
Finished Mar 12 12:53:32 PM PDT 24
Peak memory 183952 kb
Host smart-01d55a80-2855-400c-b711-0ce50bdc351b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617763786 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_al
l.617763786
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_jump.2412540058
Short name T252
Test name
Test status
Simulation time 396443209 ps
CPU time 1.16 seconds
Started Mar 12 12:52:19 PM PDT 24
Finished Mar 12 12:52:20 PM PDT 24
Peak memory 183952 kb
Host smart-cf99de60-6277-4d36-8a3c-f017db8bfb7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412540058 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.2412540058
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.2579424665
Short name T129
Test name
Test status
Simulation time 3902198268 ps
CPU time 3.3 seconds
Started Mar 12 12:52:15 PM PDT 24
Finished Mar 12 12:52:19 PM PDT 24
Peak memory 183952 kb
Host smart-8e3d726c-2caf-47a4-9f5b-c389517760ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579424665 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.2579424665
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.3016402720
Short name T15
Test name
Test status
Simulation time 7996123632 ps
CPU time 6.31 seconds
Started Mar 12 12:52:24 PM PDT 24
Finished Mar 12 12:52:31 PM PDT 24
Peak memory 215876 kb
Host smart-4f831c51-0f16-4bf0-8391-26beb6630ffa
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016402720 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.3016402720
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.2128610569
Short name T105
Test name
Test status
Simulation time 541600244 ps
CPU time 1.21 seconds
Started Mar 12 12:52:14 PM PDT 24
Finished Mar 12 12:52:15 PM PDT 24
Peak memory 183980 kb
Host smart-b60c0b4b-9c7a-49c4-a876-637976be8278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128610569 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.2128610569
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.457277896
Short name T111
Test name
Test status
Simulation time 68866344467 ps
CPU time 46.43 seconds
Started Mar 12 12:52:25 PM PDT 24
Finished Mar 12 12:53:11 PM PDT 24
Peak memory 184096 kb
Host smart-936210ca-5acf-4e77-9718-739e82e3b4c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457277896 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_al
l.457277896
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.1522077503
Short name T87
Test name
Test status
Simulation time 61110358832 ps
CPU time 335.43 seconds
Started Mar 12 12:52:10 PM PDT 24
Finished Mar 12 12:57:45 PM PDT 24
Peak memory 198924 kb
Host smart-2dbb6991-2525-4f34-a4a9-c5662245e3c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522077503 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.1522077503
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.aon_timer_jump.1310053268
Short name T26
Test name
Test status
Simulation time 438452318 ps
CPU time 0.69 seconds
Started Mar 12 12:52:45 PM PDT 24
Finished Mar 12 12:52:46 PM PDT 24
Peak memory 183952 kb
Host smart-56616d57-e7f5-4528-900f-bd3e4b41493a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310053268 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.1310053268
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.840089962
Short name T203
Test name
Test status
Simulation time 13564084612 ps
CPU time 5.15 seconds
Started Mar 12 12:52:13 PM PDT 24
Finished Mar 12 12:52:19 PM PDT 24
Peak memory 192304 kb
Host smart-69640b1d-da96-4fc6-b5fd-59a232bd6d60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840089962 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.840089962
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.3778875321
Short name T187
Test name
Test status
Simulation time 525654228 ps
CPU time 0.72 seconds
Started Mar 12 12:52:32 PM PDT 24
Finished Mar 12 12:52:33 PM PDT 24
Peak memory 183940 kb
Host smart-99e0b96f-d818-4966-86c8-7c7855e11604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778875321 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.3778875321
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.2607632392
Short name T157
Test name
Test status
Simulation time 93029902857 ps
CPU time 14.78 seconds
Started Mar 12 12:52:33 PM PDT 24
Finished Mar 12 12:52:49 PM PDT 24
Peak memory 183904 kb
Host smart-0ae8f551-8252-41d2-8243-9ce47a2e0ae7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607632392 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_
all.2607632392
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.2284075202
Short name T152
Test name
Test status
Simulation time 197205842246 ps
CPU time 374.42 seconds
Started Mar 12 12:52:48 PM PDT 24
Finished Mar 12 12:59:02 PM PDT 24
Peak memory 198868 kb
Host smart-8e1d4260-8e4f-4f26-8239-b7b830b21e6a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284075202 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.2284075202
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.aon_timer_jump.2347181289
Short name T179
Test name
Test status
Simulation time 459477984 ps
CPU time 0.92 seconds
Started Mar 12 12:52:28 PM PDT 24
Finished Mar 12 12:52:29 PM PDT 24
Peak memory 183888 kb
Host smart-db7c11c4-be2f-4ba2-b979-127807498233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347181289 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.2347181289
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.3246625620
Short name T259
Test name
Test status
Simulation time 32270036433 ps
CPU time 45.07 seconds
Started Mar 12 12:52:13 PM PDT 24
Finished Mar 12 12:52:58 PM PDT 24
Peak memory 184108 kb
Host smart-94a28b5c-14c4-4704-a831-2478b6e6a709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246625620 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.3246625620
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.2655969382
Short name T104
Test name
Test status
Simulation time 490352724 ps
CPU time 0.73 seconds
Started Mar 12 12:52:27 PM PDT 24
Finished Mar 12 12:52:28 PM PDT 24
Peak memory 183952 kb
Host smart-bffaca53-ab3b-45d8-a766-53b7785864df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655969382 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.2655969382
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.1882659992
Short name T11
Test name
Test status
Simulation time 11581869594 ps
CPU time 17.7 seconds
Started Mar 12 12:52:34 PM PDT 24
Finished Mar 12 12:52:52 PM PDT 24
Peak memory 194536 kb
Host smart-e094a541-7270-40a1-ade4-fcfcb76196fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882659992 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_
all.1882659992
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.3326397925
Short name T249
Test name
Test status
Simulation time 71040642388 ps
CPU time 530.59 seconds
Started Mar 12 12:52:23 PM PDT 24
Finished Mar 12 01:01:14 PM PDT 24
Peak memory 198932 kb
Host smart-7f5a8af3-85c0-4387-86b1-75548d4bc47b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326397925 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand_reset.3326397925
Directory /workspace/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.aon_timer_jump.294358873
Short name T29
Test name
Test status
Simulation time 423579466 ps
CPU time 0.72 seconds
Started Mar 12 12:52:33 PM PDT 24
Finished Mar 12 12:52:34 PM PDT 24
Peak memory 183972 kb
Host smart-6340c384-f0f3-4f22-a06c-6ead8ee94342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294358873 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.294358873
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.555742211
Short name T148
Test name
Test status
Simulation time 7269492157 ps
CPU time 1.18 seconds
Started Mar 12 12:52:31 PM PDT 24
Finished Mar 12 12:52:33 PM PDT 24
Peak memory 184068 kb
Host smart-de9ee6df-03d3-4598-abdc-70e58f5538aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555742211 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.555742211
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.4018246382
Short name T57
Test name
Test status
Simulation time 453123634 ps
CPU time 0.89 seconds
Started Mar 12 12:52:31 PM PDT 24
Finished Mar 12 12:52:32 PM PDT 24
Peak memory 183776 kb
Host smart-93fb8e5f-da69-41f6-bfc7-39ba9d6be5ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018246382 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.4018246382
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.2444189550
Short name T197
Test name
Test status
Simulation time 118916429868 ps
CPU time 40.47 seconds
Started Mar 12 12:52:22 PM PDT 24
Finished Mar 12 12:53:03 PM PDT 24
Peak memory 184136 kb
Host smart-cdcf3ce9-e022-42e2-bec9-18e3f01e41ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444189550 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_
all.2444189550
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/13.aon_timer_jump.2316742841
Short name T3
Test name
Test status
Simulation time 477874885 ps
CPU time 0.71 seconds
Started Mar 12 12:52:33 PM PDT 24
Finished Mar 12 12:52:34 PM PDT 24
Peak memory 183948 kb
Host smart-cd51061c-eac9-4a63-83b8-7b2135e0e71f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316742841 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.2316742841
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.3022099646
Short name T109
Test name
Test status
Simulation time 36387847270 ps
CPU time 29.54 seconds
Started Mar 12 12:52:28 PM PDT 24
Finished Mar 12 12:52:58 PM PDT 24
Peak memory 184056 kb
Host smart-9f8a2e57-7038-4e1b-ad7d-6e1e5d339be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022099646 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.3022099646
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.2122573926
Short name T55
Test name
Test status
Simulation time 603589682 ps
CPU time 0.75 seconds
Started Mar 12 12:52:24 PM PDT 24
Finished Mar 12 12:52:25 PM PDT 24
Peak memory 183900 kb
Host smart-c2b0b781-17d0-41ac-b270-760311c7c9ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122573926 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.2122573926
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.3804277281
Short name T155
Test name
Test status
Simulation time 89722876369 ps
CPU time 142.6 seconds
Started Mar 12 12:52:32 PM PDT 24
Finished Mar 12 12:54:55 PM PDT 24
Peak memory 184092 kb
Host smart-5938ef2c-25e8-4730-abcc-0b9c84a7e21c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804277281 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_
all.3804277281
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.1190754369
Short name T263
Test name
Test status
Simulation time 283215468191 ps
CPU time 548.52 seconds
Started Mar 12 12:52:34 PM PDT 24
Finished Mar 12 01:01:43 PM PDT 24
Peak memory 215108 kb
Host smart-4529807a-71a7-400e-8e19-515b0fcd66b9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190754369 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.1190754369
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.aon_timer_jump.3739690245
Short name T106
Test name
Test status
Simulation time 560595421 ps
CPU time 0.75 seconds
Started Mar 12 12:52:33 PM PDT 24
Finished Mar 12 12:52:34 PM PDT 24
Peak memory 183968 kb
Host smart-dd30a093-c02b-4c2a-bc42-3ba7b96532fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739690245 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.3739690245
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.3198810756
Short name T198
Test name
Test status
Simulation time 8887401615 ps
CPU time 3.37 seconds
Started Mar 12 12:52:30 PM PDT 24
Finished Mar 12 12:52:33 PM PDT 24
Peak memory 192196 kb
Host smart-3a49f9b5-8a7b-494f-a17e-b995c8cfa9d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198810756 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.3198810756
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.911394972
Short name T149
Test name
Test status
Simulation time 584114250 ps
CPU time 0.65 seconds
Started Mar 12 12:52:32 PM PDT 24
Finished Mar 12 12:52:33 PM PDT 24
Peak memory 183788 kb
Host smart-41e2607d-595e-43ac-ad7e-569e806cf8df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911394972 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.911394972
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.1070781797
Short name T90
Test name
Test status
Simulation time 54479065490 ps
CPU time 20.84 seconds
Started Mar 12 12:52:33 PM PDT 24
Finished Mar 12 12:52:54 PM PDT 24
Peak memory 195552 kb
Host smart-759c289f-e89a-4d95-b68b-d92c386f23f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070781797 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_
all.1070781797
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.159481825
Short name T141
Test name
Test status
Simulation time 96556323692 ps
CPU time 258.79 seconds
Started Mar 12 12:52:36 PM PDT 24
Finished Mar 12 12:56:55 PM PDT 24
Peak memory 198868 kb
Host smart-5887a209-4ab0-4e87-a749-8c86e3609374
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159481825 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.159481825
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.aon_timer_jump.2813661599
Short name T14
Test name
Test status
Simulation time 519637738 ps
CPU time 0.63 seconds
Started Mar 12 12:52:35 PM PDT 24
Finished Mar 12 12:52:36 PM PDT 24
Peak memory 183992 kb
Host smart-bbe4ac89-66dd-4c27-9e02-36a4e935a649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813661599 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.2813661599
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.3624727052
Short name T196
Test name
Test status
Simulation time 61077387229 ps
CPU time 93.26 seconds
Started Mar 12 12:52:28 PM PDT 24
Finished Mar 12 12:54:01 PM PDT 24
Peak memory 192252 kb
Host smart-b67c3b97-e64f-42c6-80c5-fc2a7ec52d9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624727052 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.3624727052
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.16330443
Short name T264
Test name
Test status
Simulation time 348514699 ps
CPU time 0.7 seconds
Started Mar 12 12:52:32 PM PDT 24
Finished Mar 12 12:52:33 PM PDT 24
Peak memory 183900 kb
Host smart-0c917d04-4901-498e-9a7b-8db5f87c2174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16330443 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.16330443
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.2686584084
Short name T182
Test name
Test status
Simulation time 112779373898 ps
CPU time 181.23 seconds
Started Mar 12 12:52:34 PM PDT 24
Finished Mar 12 12:55:35 PM PDT 24
Peak memory 184032 kb
Host smart-6327c6e0-6865-4e81-ab8c-75e64c283dd4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686584084 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_
all.2686584084
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.2661616795
Short name T46
Test name
Test status
Simulation time 46289620471 ps
CPU time 460.67 seconds
Started Mar 12 12:52:32 PM PDT 24
Finished Mar 12 01:00:13 PM PDT 24
Peak memory 198944 kb
Host smart-c5b8b084-3890-49bb-ba3b-5c9ab9c25547
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661616795 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.2661616795
Directory /workspace/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.aon_timer_jump.1907862325
Short name T112
Test name
Test status
Simulation time 510021027 ps
CPU time 0.7 seconds
Started Mar 12 12:52:34 PM PDT 24
Finished Mar 12 12:52:35 PM PDT 24
Peak memory 183952 kb
Host smart-ff98d528-ae55-430f-a032-a4c0580bbbc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907862325 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.1907862325
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.3521560813
Short name T242
Test name
Test status
Simulation time 1129597375 ps
CPU time 1.23 seconds
Started Mar 12 12:52:47 PM PDT 24
Finished Mar 12 12:52:49 PM PDT 24
Peak memory 184004 kb
Host smart-0b377092-0b61-44af-958b-8582814e82c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521560813 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.3521560813
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.2354330053
Short name T58
Test name
Test status
Simulation time 480568807 ps
CPU time 1.22 seconds
Started Mar 12 12:52:29 PM PDT 24
Finished Mar 12 12:52:30 PM PDT 24
Peak memory 183864 kb
Host smart-1f71cca8-0782-4325-9775-16041a385928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354330053 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.2354330053
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.4087091172
Short name T86
Test name
Test status
Simulation time 789121445023 ps
CPU time 608.93 seconds
Started Mar 12 12:52:29 PM PDT 24
Finished Mar 12 01:02:38 PM PDT 24
Peak memory 199528 kb
Host smart-462dc361-085a-47d8-ba75-ef6225fea952
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087091172 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.4087091172
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.aon_timer_jump.211514085
Short name T36
Test name
Test status
Simulation time 419431024 ps
CPU time 0.82 seconds
Started Mar 12 12:52:26 PM PDT 24
Finished Mar 12 12:52:27 PM PDT 24
Peak memory 183988 kb
Host smart-a8769bef-5233-463b-9179-7e79de2d0a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211514085 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.211514085
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.3298417539
Short name T59
Test name
Test status
Simulation time 35803690996 ps
CPU time 48.73 seconds
Started Mar 12 12:52:35 PM PDT 24
Finished Mar 12 12:53:24 PM PDT 24
Peak memory 184108 kb
Host smart-23785165-71f2-4a30-8f24-7bd55e68cc91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298417539 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.3298417539
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.3572504296
Short name T169
Test name
Test status
Simulation time 332466537 ps
CPU time 0.95 seconds
Started Mar 12 12:52:43 PM PDT 24
Finished Mar 12 12:52:44 PM PDT 24
Peak memory 183964 kb
Host smart-2b25178c-0da3-498c-b53b-cf63d0ee24ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572504296 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.3572504296
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.2965347270
Short name T261
Test name
Test status
Simulation time 324562963104 ps
CPU time 476.89 seconds
Started Mar 12 12:52:33 PM PDT 24
Finished Mar 12 01:00:31 PM PDT 24
Peak memory 194272 kb
Host smart-8547982a-5f58-4473-a206-f68af55fa11f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965347270 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_
all.2965347270
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_jump.2875161720
Short name T132
Test name
Test status
Simulation time 514370046 ps
CPU time 0.94 seconds
Started Mar 12 12:52:25 PM PDT 24
Finished Mar 12 12:52:27 PM PDT 24
Peak memory 183948 kb
Host smart-9b53b999-fcdc-4e3b-be80-5f16d88792a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875161720 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.2875161720
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.3758182488
Short name T128
Test name
Test status
Simulation time 11451904032 ps
CPU time 3.24 seconds
Started Mar 12 12:52:33 PM PDT 24
Finished Mar 12 12:52:37 PM PDT 24
Peak memory 184108 kb
Host smart-eb809e05-ad9f-4615-9de3-b74f1c23b6c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758182488 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.3758182488
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.2842582628
Short name T56
Test name
Test status
Simulation time 415672243 ps
CPU time 0.7 seconds
Started Mar 12 12:52:31 PM PDT 24
Finished Mar 12 12:52:32 PM PDT 24
Peak memory 183932 kb
Host smart-3a843ce8-1a5b-425e-8d5d-48c97af51634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842582628 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.2842582628
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.2937025860
Short name T96
Test name
Test status
Simulation time 64703781966 ps
CPU time 91.74 seconds
Started Mar 12 12:52:36 PM PDT 24
Finished Mar 12 12:54:09 PM PDT 24
Peak memory 184076 kb
Host smart-09dd9b39-6e55-4955-bacb-a9adaa04157f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937025860 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_
all.2937025860
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.525280477
Short name T45
Test name
Test status
Simulation time 138514846143 ps
CPU time 267.78 seconds
Started Mar 12 12:52:42 PM PDT 24
Finished Mar 12 12:57:10 PM PDT 24
Peak memory 198880 kb
Host smart-1091fc0f-5899-4725-95dc-3276429e24ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525280477 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.525280477
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.aon_timer_jump.488229213
Short name T257
Test name
Test status
Simulation time 467380951 ps
CPU time 1.24 seconds
Started Mar 12 12:52:40 PM PDT 24
Finished Mar 12 12:52:41 PM PDT 24
Peak memory 183964 kb
Host smart-5e684c20-5833-47e0-aafb-738dcd62a5cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488229213 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.488229213
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.1055487078
Short name T247
Test name
Test status
Simulation time 61880817971 ps
CPU time 90.45 seconds
Started Mar 12 12:52:31 PM PDT 24
Finished Mar 12 12:54:02 PM PDT 24
Peak memory 184076 kb
Host smart-c22c6de1-db02-40f8-ae58-820dfb023ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055487078 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.1055487078
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.1745491674
Short name T154
Test name
Test status
Simulation time 596057242 ps
CPU time 0.97 seconds
Started Mar 12 12:52:34 PM PDT 24
Finished Mar 12 12:52:36 PM PDT 24
Peak memory 183956 kb
Host smart-d5da3f8a-72c2-45a8-9b20-1646c1b09750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745491674 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.1745491674
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.3346004547
Short name T214
Test name
Test status
Simulation time 212171879595 ps
CPU time 307.11 seconds
Started Mar 12 12:52:41 PM PDT 24
Finished Mar 12 12:57:48 PM PDT 24
Peak memory 184028 kb
Host smart-503c72b1-d441-438b-ba6e-e6c0d46eaa30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346004547 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_
all.3346004547
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.1360875154
Short name T162
Test name
Test status
Simulation time 169800595740 ps
CPU time 352.98 seconds
Started Mar 12 12:52:30 PM PDT 24
Finished Mar 12 12:58:23 PM PDT 24
Peak memory 198940 kb
Host smart-a9b754ea-a409-4151-981e-87a9c6713ce0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360875154 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.1360875154
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_jump.2451517698
Short name T176
Test name
Test status
Simulation time 605622943 ps
CPU time 0.62 seconds
Started Mar 12 12:52:09 PM PDT 24
Finished Mar 12 12:52:09 PM PDT 24
Peak memory 184000 kb
Host smart-190c54c2-0dd5-4e50-9a4e-0c7d5f7a3127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451517698 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.2451517698
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.1390833936
Short name T230
Test name
Test status
Simulation time 35578931813 ps
CPU time 26.05 seconds
Started Mar 12 12:52:07 PM PDT 24
Finished Mar 12 12:52:34 PM PDT 24
Peak memory 192304 kb
Host smart-620f708d-f62b-4b06-99ec-9b0882c42f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390833936 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.1390833936
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.1577563723
Short name T20
Test name
Test status
Simulation time 7868858681 ps
CPU time 6.67 seconds
Started Mar 12 12:52:08 PM PDT 24
Finished Mar 12 12:52:15 PM PDT 24
Peak memory 215824 kb
Host smart-c00dab4a-eb0c-465c-aa7b-a9930413e54b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577563723 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.1577563723
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.3278062995
Short name T277
Test name
Test status
Simulation time 492312664 ps
CPU time 0.87 seconds
Started Mar 12 12:52:05 PM PDT 24
Finished Mar 12 12:52:16 PM PDT 24
Peak memory 183956 kb
Host smart-1cea0a2d-9739-45a6-906a-16e85c279878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278062995 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.3278062995
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.4101920998
Short name T18
Test name
Test status
Simulation time 55355331353 ps
CPU time 21.08 seconds
Started Mar 12 12:52:14 PM PDT 24
Finished Mar 12 12:52:36 PM PDT 24
Peak memory 184024 kb
Host smart-27404972-a31d-4116-9b4f-e1ae02abe3d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101920998 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_a
ll.4101920998
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.4233548843
Short name T21
Test name
Test status
Simulation time 53500532980 ps
CPU time 301.15 seconds
Started Mar 12 12:52:13 PM PDT 24
Finished Mar 12 12:57:14 PM PDT 24
Peak memory 198924 kb
Host smart-925618b1-3c19-4360-a6fd-18bbc4197812
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233548843 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.4233548843
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.aon_timer_jump.4188074573
Short name T271
Test name
Test status
Simulation time 544063996 ps
CPU time 0.74 seconds
Started Mar 12 12:52:50 PM PDT 24
Finished Mar 12 12:52:51 PM PDT 24
Peak memory 183952 kb
Host smart-f902eb38-1914-4a9f-a5fd-866d459f28cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188074573 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.4188074573
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.2522986959
Short name T222
Test name
Test status
Simulation time 20964112151 ps
CPU time 15.06 seconds
Started Mar 12 12:52:31 PM PDT 24
Finished Mar 12 12:52:46 PM PDT 24
Peak memory 192296 kb
Host smart-8d7f2092-ff8f-453e-a5a6-58a14ede992f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522986959 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.2522986959
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.2351844428
Short name T156
Test name
Test status
Simulation time 521085780 ps
CPU time 0.72 seconds
Started Mar 12 12:52:32 PM PDT 24
Finished Mar 12 12:52:33 PM PDT 24
Peak memory 183940 kb
Host smart-34f64ef3-3721-45c4-b7f3-0bba56761565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351844428 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.2351844428
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.3617684334
Short name T235
Test name
Test status
Simulation time 91111628390 ps
CPU time 27.16 seconds
Started Mar 12 12:52:40 PM PDT 24
Finished Mar 12 12:53:07 PM PDT 24
Peak memory 184060 kb
Host smart-5ef1bd6d-3d0d-4818-86bc-0340a795d6d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617684334 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_
all.3617684334
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/21.aon_timer_jump.3815919544
Short name T241
Test name
Test status
Simulation time 366370063 ps
CPU time 0.68 seconds
Started Mar 12 12:52:34 PM PDT 24
Finished Mar 12 12:52:35 PM PDT 24
Peak memory 183956 kb
Host smart-f66112cc-1337-420f-8272-060f3641b0ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815919544 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.3815919544
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.224030815
Short name T12
Test name
Test status
Simulation time 22227771375 ps
CPU time 34.73 seconds
Started Mar 12 12:52:33 PM PDT 24
Finished Mar 12 12:53:08 PM PDT 24
Peak memory 192280 kb
Host smart-258a39f4-b74a-4425-a76c-49676954b76c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224030815 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.224030815
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.2463761986
Short name T265
Test name
Test status
Simulation time 423952988 ps
CPU time 0.65 seconds
Started Mar 12 12:52:31 PM PDT 24
Finished Mar 12 12:52:32 PM PDT 24
Peak memory 183980 kb
Host smart-51c4811e-0128-4fe1-b7bc-8815de97217f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463761986 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.2463761986
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.4105318425
Short name T228
Test name
Test status
Simulation time 78807563566 ps
CPU time 8 seconds
Started Mar 12 12:52:30 PM PDT 24
Finished Mar 12 12:52:38 PM PDT 24
Peak memory 184104 kb
Host smart-fc488c73-ce00-475c-8245-c8612b1862df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105318425 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_
all.4105318425
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.2488607512
Short name T184
Test name
Test status
Simulation time 54515238099 ps
CPU time 220.7 seconds
Started Mar 12 12:52:32 PM PDT 24
Finished Mar 12 12:56:14 PM PDT 24
Peak memory 198872 kb
Host smart-201ceefe-cf07-44d1-b695-59c0dba53f0a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488607512 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.2488607512
Directory /workspace/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.aon_timer_jump.3371499753
Short name T260
Test name
Test status
Simulation time 602518173 ps
CPU time 0.74 seconds
Started Mar 12 12:52:30 PM PDT 24
Finished Mar 12 12:52:31 PM PDT 24
Peak memory 183840 kb
Host smart-1cc52dc1-ee6b-425a-88b4-26e7bd6f8402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371499753 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.3371499753
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.1321542400
Short name T236
Test name
Test status
Simulation time 11074787471 ps
CPU time 18.63 seconds
Started Mar 12 12:52:32 PM PDT 24
Finished Mar 12 12:52:51 PM PDT 24
Peak memory 192296 kb
Host smart-a64529fc-8cea-4929-bfdb-c9ac84ed8e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321542400 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.1321542400
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.4043821840
Short name T216
Test name
Test status
Simulation time 535616263 ps
CPU time 0.64 seconds
Started Mar 12 12:52:37 PM PDT 24
Finished Mar 12 12:52:38 PM PDT 24
Peak memory 183924 kb
Host smart-6ec3e12b-3a22-4c0a-adc6-26ba39614468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043821840 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.4043821840
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.528786895
Short name T223
Test name
Test status
Simulation time 42706831935 ps
CPU time 73.46 seconds
Started Mar 12 12:52:32 PM PDT 24
Finished Mar 12 12:53:46 PM PDT 24
Peak memory 184100 kb
Host smart-14858a7c-50f9-4a92-a339-8a16868d7450
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528786895 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_a
ll.528786895
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.3898584563
Short name T174
Test name
Test status
Simulation time 93403342165 ps
CPU time 1016.7 seconds
Started Mar 12 12:52:34 PM PDT 24
Finished Mar 12 01:09:31 PM PDT 24
Peak memory 205372 kb
Host smart-748ea0ad-6a0c-461d-abf8-4889c0cb682e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898584563 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.3898584563
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.aon_timer_jump.747591918
Short name T229
Test name
Test status
Simulation time 601452081 ps
CPU time 0.7 seconds
Started Mar 12 12:52:41 PM PDT 24
Finished Mar 12 12:52:41 PM PDT 24
Peak memory 183776 kb
Host smart-e5f07f5f-ab39-427d-beb9-3c3bc18dd72e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747591918 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.747591918
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.2850224527
Short name T117
Test name
Test status
Simulation time 61024055490 ps
CPU time 22.91 seconds
Started Mar 12 12:52:34 PM PDT 24
Finished Mar 12 12:52:57 PM PDT 24
Peak memory 184056 kb
Host smart-810a388d-9985-4a0d-bae7-93d580db20b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850224527 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.2850224527
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.111639549
Short name T145
Test name
Test status
Simulation time 469097682 ps
CPU time 0.92 seconds
Started Mar 12 12:52:53 PM PDT 24
Finished Mar 12 12:52:54 PM PDT 24
Peak memory 184008 kb
Host smart-46a31a10-42cc-442e-9bc7-6ddd09845809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111639549 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.111639549
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.3864685464
Short name T144
Test name
Test status
Simulation time 80114140937 ps
CPU time 123 seconds
Started Mar 12 12:52:34 PM PDT 24
Finished Mar 12 12:54:37 PM PDT 24
Peak memory 184088 kb
Host smart-ee977d34-7f1c-40fe-a132-0d24f18a6bd3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864685464 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_
all.3864685464
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.3715604829
Short name T219
Test name
Test status
Simulation time 54262714694 ps
CPU time 430.21 seconds
Started Mar 12 12:52:50 PM PDT 24
Finished Mar 12 01:00:01 PM PDT 24
Peak memory 198844 kb
Host smart-036f2dfe-0b45-4c38-b03a-7071b8e7c7c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715604829 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.3715604829
Directory /workspace/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.aon_timer_jump.929909865
Short name T250
Test name
Test status
Simulation time 576734989 ps
CPU time 1.11 seconds
Started Mar 12 12:52:42 PM PDT 24
Finished Mar 12 12:52:44 PM PDT 24
Peak memory 183896 kb
Host smart-61251426-cde4-41f3-a214-3c557b8c23a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929909865 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.929909865
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.2869891208
Short name T186
Test name
Test status
Simulation time 14997773490 ps
CPU time 21.62 seconds
Started Mar 12 12:52:34 PM PDT 24
Finished Mar 12 12:52:56 PM PDT 24
Peak memory 184072 kb
Host smart-637e36de-0616-4231-b615-2502a11ed228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869891208 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.2869891208
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.2331116582
Short name T30
Test name
Test status
Simulation time 342515413 ps
CPU time 1.02 seconds
Started Mar 12 12:52:51 PM PDT 24
Finished Mar 12 12:52:53 PM PDT 24
Peak memory 183932 kb
Host smart-e17c1c52-14a2-4e90-b8a4-3199946c3210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331116582 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.2331116582
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.1545239977
Short name T134
Test name
Test status
Simulation time 402525661898 ps
CPU time 663.39 seconds
Started Mar 12 12:52:40 PM PDT 24
Finished Mar 12 01:03:44 PM PDT 24
Peak memory 184104 kb
Host smart-427a9805-0758-463a-b839-100211d42cdd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545239977 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_
all.1545239977
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.1182279315
Short name T159
Test name
Test status
Simulation time 19742308748 ps
CPU time 119.42 seconds
Started Mar 12 12:52:49 PM PDT 24
Finished Mar 12 12:54:49 PM PDT 24
Peak memory 198980 kb
Host smart-185f1f55-1973-4b58-a539-fbd8f69f79a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182279315 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand_reset.1182279315
Directory /workspace/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.aon_timer_jump.3824367259
Short name T143
Test name
Test status
Simulation time 575242123 ps
CPU time 0.61 seconds
Started Mar 12 12:53:02 PM PDT 24
Finished Mar 12 12:53:03 PM PDT 24
Peak memory 183960 kb
Host smart-26cee9fa-9599-4b5a-a797-30818aaf2213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824367259 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.3824367259
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.380605750
Short name T238
Test name
Test status
Simulation time 651578697 ps
CPU time 1.04 seconds
Started Mar 12 12:52:49 PM PDT 24
Finished Mar 12 12:52:50 PM PDT 24
Peak memory 183896 kb
Host smart-3e77fdaf-243a-43c5-9d3a-46c37a22d3a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380605750 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.380605750
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.1051425205
Short name T243
Test name
Test status
Simulation time 570533579 ps
CPU time 0.64 seconds
Started Mar 12 12:52:50 PM PDT 24
Finished Mar 12 12:52:52 PM PDT 24
Peak memory 183900 kb
Host smart-71cb445b-fa0d-47d7-81ff-eca178d6f0c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051425205 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.1051425205
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.643008102
Short name T210
Test name
Test status
Simulation time 20182260358 ps
CPU time 8.8 seconds
Started Mar 12 12:52:45 PM PDT 24
Finished Mar 12 12:52:55 PM PDT 24
Peak memory 195376 kb
Host smart-b33deb40-0cb2-48ac-8ac5-98587b042f98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643008102 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_a
ll.643008102
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_jump.3879847249
Short name T227
Test name
Test status
Simulation time 387706735 ps
CPU time 0.67 seconds
Started Mar 12 12:52:39 PM PDT 24
Finished Mar 12 12:52:40 PM PDT 24
Peak memory 183952 kb
Host smart-c28ef68c-f0ba-4e05-a3f2-2c64eea83be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879847249 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.3879847249
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.74611662
Short name T120
Test name
Test status
Simulation time 25575416067 ps
CPU time 19.37 seconds
Started Mar 12 12:53:02 PM PDT 24
Finished Mar 12 12:53:22 PM PDT 24
Peak memory 184068 kb
Host smart-aaa1fce7-e912-4e71-82f3-5db7e2ace8a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74611662 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.74611662
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.2427956577
Short name T1
Test name
Test status
Simulation time 558893971 ps
CPU time 1.29 seconds
Started Mar 12 12:52:36 PM PDT 24
Finished Mar 12 12:52:37 PM PDT 24
Peak memory 183980 kb
Host smart-f1a9e82d-e10f-4ac2-81c2-a4f68fef75f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427956577 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.2427956577
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.1987200465
Short name T124
Test name
Test status
Simulation time 83287729655 ps
CPU time 33.75 seconds
Started Mar 12 12:52:45 PM PDT 24
Finished Mar 12 12:53:19 PM PDT 24
Peak memory 184068 kb
Host smart-40b4f9ea-20b3-4beb-8d40-53002f347e12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987200465 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_
all.1987200465
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/27.aon_timer_jump.1680829166
Short name T122
Test name
Test status
Simulation time 645831137 ps
CPU time 0.67 seconds
Started Mar 12 12:52:43 PM PDT 24
Finished Mar 12 12:52:44 PM PDT 24
Peak memory 183840 kb
Host smart-7783c880-3601-4473-9cb1-32077c794bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680829166 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.1680829166
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.2646640454
Short name T258
Test name
Test status
Simulation time 33643994963 ps
CPU time 15.03 seconds
Started Mar 12 12:52:36 PM PDT 24
Finished Mar 12 12:52:52 PM PDT 24
Peak memory 192268 kb
Host smart-40d22397-814f-4249-9d0c-af6d1e7da63c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646640454 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.2646640454
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.2562633676
Short name T166
Test name
Test status
Simulation time 605700335 ps
CPU time 1.48 seconds
Started Mar 12 12:52:44 PM PDT 24
Finished Mar 12 12:52:46 PM PDT 24
Peak memory 183932 kb
Host smart-37172bd2-daf9-4d0f-8963-dd2bc3a04842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562633676 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.2562633676
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.1213817223
Short name T239
Test name
Test status
Simulation time 8282240702 ps
CPU time 38.15 seconds
Started Mar 12 12:52:59 PM PDT 24
Finished Mar 12 12:53:37 PM PDT 24
Peak memory 198916 kb
Host smart-b2f118d4-e7f2-4e4f-9cf2-cd00f6d39524
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213817223 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.1213817223
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_jump.2107160368
Short name T114
Test name
Test status
Simulation time 498654402 ps
CPU time 1.29 seconds
Started Mar 12 12:52:34 PM PDT 24
Finished Mar 12 12:52:36 PM PDT 24
Peak memory 183968 kb
Host smart-994caf38-6618-4a02-8414-3124bf344ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107160368 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.2107160368
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.1513662587
Short name T262
Test name
Test status
Simulation time 24273334842 ps
CPU time 17.15 seconds
Started Mar 12 12:52:36 PM PDT 24
Finished Mar 12 12:52:54 PM PDT 24
Peak memory 184072 kb
Host smart-9f5f7771-549a-4199-b187-f1aea42b7a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513662587 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.1513662587
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.3371646791
Short name T226
Test name
Test status
Simulation time 426271588 ps
CPU time 0.67 seconds
Started Mar 12 12:52:50 PM PDT 24
Finished Mar 12 12:52:51 PM PDT 24
Peak memory 183992 kb
Host smart-4aaefd36-5f9e-49fe-be84-96849ce7bc2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371646791 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.3371646791
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.3997362914
Short name T206
Test name
Test status
Simulation time 289595539236 ps
CPU time 423.07 seconds
Started Mar 12 12:52:56 PM PDT 24
Finished Mar 12 01:00:00 PM PDT 24
Peak memory 184072 kb
Host smart-86ca84e2-09b1-4d7e-bd47-9fde1ed575a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997362914 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_
all.3997362914
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.1216658148
Short name T6
Test name
Test status
Simulation time 649491082205 ps
CPU time 234.91 seconds
Started Mar 12 12:52:47 PM PDT 24
Finished Mar 12 12:56:42 PM PDT 24
Peak memory 198936 kb
Host smart-36480f25-b326-4cbe-8700-f9e881576bf3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216658148 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.1216658148
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.aon_timer_jump.1316901654
Short name T269
Test name
Test status
Simulation time 380076004 ps
CPU time 0.68 seconds
Started Mar 12 12:52:49 PM PDT 24
Finished Mar 12 12:52:50 PM PDT 24
Peak memory 183960 kb
Host smart-856f8479-e382-4b2b-b5e8-cab8e16e558b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316901654 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.1316901654
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.489169352
Short name T212
Test name
Test status
Simulation time 18727611478 ps
CPU time 4.25 seconds
Started Mar 12 12:52:43 PM PDT 24
Finished Mar 12 12:52:48 PM PDT 24
Peak memory 184116 kb
Host smart-60b509cd-dc06-4b7c-8018-3a4bcd1174cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489169352 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.489169352
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.4173551202
Short name T167
Test name
Test status
Simulation time 570797919 ps
CPU time 0.98 seconds
Started Mar 12 12:52:50 PM PDT 24
Finished Mar 12 12:52:51 PM PDT 24
Peak memory 183992 kb
Host smart-4c3628e0-34c0-4a8f-93b0-4b97416844a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173551202 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.4173551202
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.4222055396
Short name T80
Test name
Test status
Simulation time 200587030259 ps
CPU time 452.69 seconds
Started Mar 12 12:52:34 PM PDT 24
Finished Mar 12 01:00:06 PM PDT 24
Peak memory 198928 kb
Host smart-79b92989-7981-4f18-ab47-c0e01dd5a249
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222055396 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.4222055396
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.aon_timer_jump.1421199831
Short name T43
Test name
Test status
Simulation time 477147103 ps
CPU time 1.32 seconds
Started Mar 12 12:52:32 PM PDT 24
Finished Mar 12 12:52:34 PM PDT 24
Peak memory 183960 kb
Host smart-626b91bb-e5ce-4e8e-91ba-55ca152da03f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421199831 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.1421199831
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.3706951806
Short name T190
Test name
Test status
Simulation time 36918866223 ps
CPU time 25.3 seconds
Started Mar 12 12:52:08 PM PDT 24
Finished Mar 12 12:52:34 PM PDT 24
Peak memory 184060 kb
Host smart-8a1e5c0f-8e1f-44bc-b873-bc35e3a1be90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706951806 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.3706951806
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.3483368685
Short name T17
Test name
Test status
Simulation time 4027678428 ps
CPU time 6.58 seconds
Started Mar 12 12:52:32 PM PDT 24
Finished Mar 12 12:52:39 PM PDT 24
Peak memory 215400 kb
Host smart-794bb766-ca34-4ed0-966c-6383a8c7e7bc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483368685 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.3483368685
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.1052725862
Short name T60
Test name
Test status
Simulation time 549726093 ps
CPU time 0.81 seconds
Started Mar 12 12:52:08 PM PDT 24
Finished Mar 12 12:52:09 PM PDT 24
Peak memory 183988 kb
Host smart-4ecb6de4-6ab4-41ad-b324-933907221933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052725862 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.1052725862
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.1098631385
Short name T232
Test name
Test status
Simulation time 161454039833 ps
CPU time 65.52 seconds
Started Mar 12 12:52:27 PM PDT 24
Finished Mar 12 12:53:32 PM PDT 24
Peak memory 194608 kb
Host smart-1bc0b30e-61d3-42d5-9584-2200c721b5bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098631385 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_a
ll.1098631385
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.736053603
Short name T150
Test name
Test status
Simulation time 155464878643 ps
CPU time 638.54 seconds
Started Mar 12 12:52:37 PM PDT 24
Finished Mar 12 01:03:16 PM PDT 24
Peak memory 200080 kb
Host smart-d35c7100-a7bd-4efd-833a-2a9e22503d78
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736053603 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.736053603
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_jump.2884473187
Short name T183
Test name
Test status
Simulation time 540588152 ps
CPU time 0.92 seconds
Started Mar 12 12:52:49 PM PDT 24
Finished Mar 12 12:52:50 PM PDT 24
Peak memory 183936 kb
Host smart-5ab733ca-905d-4222-94ec-6d7f695e8e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884473187 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.2884473187
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.3669517115
Short name T94
Test name
Test status
Simulation time 16395461092 ps
CPU time 23.87 seconds
Started Mar 12 12:52:58 PM PDT 24
Finished Mar 12 12:53:22 PM PDT 24
Peak memory 184100 kb
Host smart-2853b999-270b-402b-9265-52c7f082f261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669517115 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.3669517115
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.2921380875
Short name T255
Test name
Test status
Simulation time 395792856 ps
CPU time 0.65 seconds
Started Mar 12 12:52:34 PM PDT 24
Finished Mar 12 12:52:35 PM PDT 24
Peak memory 183940 kb
Host smart-187f53ce-9286-4dcb-b28c-3e3242280d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921380875 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.2921380875
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.4189585172
Short name T83
Test name
Test status
Simulation time 86116514114 ps
CPU time 443.86 seconds
Started Mar 12 12:52:49 PM PDT 24
Finished Mar 12 01:00:13 PM PDT 24
Peak memory 198852 kb
Host smart-43620b60-590d-40ae-ad17-6eb74bd1301a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189585172 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.4189585172
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.aon_timer_jump.3669377032
Short name T110
Test name
Test status
Simulation time 437624706 ps
CPU time 0.69 seconds
Started Mar 12 12:52:45 PM PDT 24
Finished Mar 12 12:52:46 PM PDT 24
Peak memory 183952 kb
Host smart-f7308e6e-4f6c-4586-864a-3f53ea0668d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669377032 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.3669377032
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.3272126447
Short name T61
Test name
Test status
Simulation time 36797659127 ps
CPU time 59.5 seconds
Started Mar 12 12:52:51 PM PDT 24
Finished Mar 12 12:53:51 PM PDT 24
Peak memory 184112 kb
Host smart-0a250f57-cbc4-48cb-8bed-7a9da9aeb716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272126447 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.3272126447
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.3862336010
Short name T225
Test name
Test status
Simulation time 422281884 ps
CPU time 1.15 seconds
Started Mar 12 12:52:35 PM PDT 24
Finished Mar 12 12:52:36 PM PDT 24
Peak memory 183944 kb
Host smart-bfba2c59-d4e1-452a-9915-b23b2e3999e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862336010 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.3862336010
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.2526881052
Short name T221
Test name
Test status
Simulation time 15318610296 ps
CPU time 11.69 seconds
Started Mar 12 12:52:55 PM PDT 24
Finished Mar 12 12:53:07 PM PDT 24
Peak memory 184064 kb
Host smart-b4c5836c-e529-42d6-bea2-1fbfa366d706
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526881052 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_
all.2526881052
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.3241651900
Short name T193
Test name
Test status
Simulation time 28676957180 ps
CPU time 222.72 seconds
Started Mar 12 12:52:49 PM PDT 24
Finished Mar 12 12:56:31 PM PDT 24
Peak memory 198916 kb
Host smart-4c6626fa-478c-4522-a3e4-1c06c1e45484
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241651900 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.3241651900
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.aon_timer_jump.1856147649
Short name T195
Test name
Test status
Simulation time 380701539 ps
CPU time 0.68 seconds
Started Mar 12 12:52:30 PM PDT 24
Finished Mar 12 12:52:30 PM PDT 24
Peak memory 183928 kb
Host smart-8fcaa82e-5d95-4130-a5fb-d85acbcf672c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856147649 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.1856147649
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.356864849
Short name T178
Test name
Test status
Simulation time 37777130586 ps
CPU time 58.14 seconds
Started Mar 12 12:52:58 PM PDT 24
Finished Mar 12 12:53:56 PM PDT 24
Peak memory 184044 kb
Host smart-2b80451d-8987-4b89-afe5-77f50f959299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356864849 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.356864849
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.3563578197
Short name T31
Test name
Test status
Simulation time 420929012 ps
CPU time 1.3 seconds
Started Mar 12 12:52:47 PM PDT 24
Finished Mar 12 12:52:48 PM PDT 24
Peak memory 183928 kb
Host smart-4d1893a9-f7d1-42a7-8870-c09d243823b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563578197 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.3563578197
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.349118715
Short name T211
Test name
Test status
Simulation time 206239439746 ps
CPU time 311.59 seconds
Started Mar 12 12:52:35 PM PDT 24
Finished Mar 12 12:57:47 PM PDT 24
Peak memory 195780 kb
Host smart-c18b717f-7efa-48ca-848a-c1fb1550d735
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349118715 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_a
ll.349118715
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.1946145094
Short name T88
Test name
Test status
Simulation time 27839927571 ps
CPU time 214.82 seconds
Started Mar 12 12:52:40 PM PDT 24
Finished Mar 12 12:56:15 PM PDT 24
Peak memory 198916 kb
Host smart-d40fa69d-4590-462d-bc62-09c6f5547734
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946145094 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_reset.1946145094
Directory /workspace/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.aon_timer_jump.1838310746
Short name T164
Test name
Test status
Simulation time 385061644 ps
CPU time 0.69 seconds
Started Mar 12 12:52:54 PM PDT 24
Finished Mar 12 12:52:55 PM PDT 24
Peak memory 183948 kb
Host smart-1e452c48-e0b2-49e5-9ddc-afb7e95f18d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838310746 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.1838310746
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.1483870324
Short name T202
Test name
Test status
Simulation time 52098448822 ps
CPU time 44.36 seconds
Started Mar 12 12:52:36 PM PDT 24
Finished Mar 12 12:53:20 PM PDT 24
Peak memory 184096 kb
Host smart-e522930e-842d-4fbe-b1df-f5140bd30be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483870324 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.1483870324
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.3361041325
Short name T137
Test name
Test status
Simulation time 568461585 ps
CPU time 1.45 seconds
Started Mar 12 12:52:51 PM PDT 24
Finished Mar 12 12:52:53 PM PDT 24
Peak memory 183940 kb
Host smart-f0c8a6eb-6cb7-4fcd-9dc8-805af2e559f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361041325 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.3361041325
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.2587048985
Short name T118
Test name
Test status
Simulation time 369479536608 ps
CPU time 140.4 seconds
Started Mar 12 12:52:51 PM PDT 24
Finished Mar 12 12:55:12 PM PDT 24
Peak memory 184012 kb
Host smart-751015fe-abfb-4992-88a7-d366d02e6d12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587048985 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_
all.2587048985
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_jump.3755607618
Short name T276
Test name
Test status
Simulation time 434109060 ps
CPU time 0.77 seconds
Started Mar 12 12:52:51 PM PDT 24
Finished Mar 12 12:52:52 PM PDT 24
Peak memory 183984 kb
Host smart-e2c3c0a2-2339-4460-abb0-a09a83cfb4d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755607618 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.3755607618
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.477735407
Short name T237
Test name
Test status
Simulation time 7969265270 ps
CPU time 2.3 seconds
Started Mar 12 12:52:53 PM PDT 24
Finished Mar 12 12:52:55 PM PDT 24
Peak memory 192268 kb
Host smart-b530b6f2-0d48-438c-bc8a-2b0095b72c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477735407 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.477735407
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.1755494277
Short name T209
Test name
Test status
Simulation time 399216719 ps
CPU time 0.88 seconds
Started Mar 12 12:52:39 PM PDT 24
Finished Mar 12 12:52:40 PM PDT 24
Peak memory 183932 kb
Host smart-2791e375-94a4-4741-8d38-3fd5d38b2832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755494277 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.1755494277
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.3826330287
Short name T185
Test name
Test status
Simulation time 370100273747 ps
CPU time 140.7 seconds
Started Mar 12 12:52:59 PM PDT 24
Finished Mar 12 12:55:20 PM PDT 24
Peak memory 184016 kb
Host smart-87d5dc42-f178-4bde-91d2-876ddd87fd5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826330287 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_
all.3826330287
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.1576636598
Short name T81
Test name
Test status
Simulation time 33111637601 ps
CPU time 341.54 seconds
Started Mar 12 12:52:55 PM PDT 24
Finished Mar 12 12:58:37 PM PDT 24
Peak memory 198936 kb
Host smart-0f5f6691-ec7a-4fa1-bf61-c1296adb152f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576636598 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.1576636598
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.aon_timer_jump.3610294606
Short name T136
Test name
Test status
Simulation time 583240006 ps
CPU time 0.78 seconds
Started Mar 12 12:52:50 PM PDT 24
Finished Mar 12 12:52:51 PM PDT 24
Peak memory 184000 kb
Host smart-68adc695-1222-41dd-91e1-748c123b1650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610294606 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.3610294606
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.21417986
Short name T138
Test name
Test status
Simulation time 24118053483 ps
CPU time 32.39 seconds
Started Mar 12 12:52:54 PM PDT 24
Finished Mar 12 12:53:27 PM PDT 24
Peak memory 184060 kb
Host smart-d769409f-9c48-4dca-a1dc-508eb5562dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21417986 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.21417986
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.1044415844
Short name T189
Test name
Test status
Simulation time 371343283 ps
CPU time 1.12 seconds
Started Mar 12 12:52:53 PM PDT 24
Finished Mar 12 12:52:55 PM PDT 24
Peak memory 184000 kb
Host smart-0ec71e97-a773-4ced-b972-f22a6273e0f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044415844 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.1044415844
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.2243677312
Short name T37
Test name
Test status
Simulation time 483515623856 ps
CPU time 183.71 seconds
Started Mar 12 12:52:55 PM PDT 24
Finished Mar 12 12:56:00 PM PDT 24
Peak memory 198912 kb
Host smart-7c94f0a5-178b-42b2-86e3-915313d79dc5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243677312 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.2243677312
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.aon_timer_jump.3010214975
Short name T28
Test name
Test status
Simulation time 566098802 ps
CPU time 1.03 seconds
Started Mar 12 12:52:46 PM PDT 24
Finished Mar 12 12:52:47 PM PDT 24
Peak memory 183888 kb
Host smart-f9e84cd9-d941-428f-9c1b-c26e43fd4ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010214975 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.3010214975
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.4146097029
Short name T131
Test name
Test status
Simulation time 6854423852 ps
CPU time 10.95 seconds
Started Mar 12 12:52:55 PM PDT 24
Finished Mar 12 12:53:06 PM PDT 24
Peak memory 192292 kb
Host smart-e3d3966e-4efa-49db-9c18-a09e57c4461c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146097029 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.4146097029
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.2905815111
Short name T9
Test name
Test status
Simulation time 600665701 ps
CPU time 0.75 seconds
Started Mar 12 12:52:51 PM PDT 24
Finished Mar 12 12:52:52 PM PDT 24
Peak memory 184000 kb
Host smart-6e160415-3ff5-4aee-be99-aa6e014e0d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905815111 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.2905815111
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.1982349282
Short name T274
Test name
Test status
Simulation time 304709855827 ps
CPU time 223.6 seconds
Started Mar 12 12:52:50 PM PDT 24
Finished Mar 12 12:56:34 PM PDT 24
Peak memory 192288 kb
Host smart-cbb532bd-4f1f-427a-bd5d-64923d1065d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982349282 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_
all.1982349282
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_jump.35317987
Short name T204
Test name
Test status
Simulation time 461926304 ps
CPU time 1.26 seconds
Started Mar 12 12:52:55 PM PDT 24
Finished Mar 12 12:52:56 PM PDT 24
Peak memory 183912 kb
Host smart-3958baf2-2a45-431d-b225-7a4b496adc82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35317987 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.35317987
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.1453452304
Short name T224
Test name
Test status
Simulation time 40166350593 ps
CPU time 14.94 seconds
Started Mar 12 12:52:55 PM PDT 24
Finished Mar 12 12:53:11 PM PDT 24
Peak memory 192272 kb
Host smart-543af697-fddb-4de3-8048-f8f473521b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453452304 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.1453452304
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.2605248907
Short name T278
Test name
Test status
Simulation time 456019378 ps
CPU time 0.84 seconds
Started Mar 12 12:52:53 PM PDT 24
Finished Mar 12 12:52:54 PM PDT 24
Peak memory 183956 kb
Host smart-697f01ac-ac99-40f7-8be6-e53842abd80b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605248907 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.2605248907
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.1268478630
Short name T93
Test name
Test status
Simulation time 224032152837 ps
CPU time 99.63 seconds
Started Mar 12 12:52:57 PM PDT 24
Finished Mar 12 12:54:37 PM PDT 24
Peak memory 184016 kb
Host smart-fe8dd65e-5c1d-42a3-9435-9a46351c793e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268478630 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_
all.1268478630
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.569054295
Short name T84
Test name
Test status
Simulation time 68475149107 ps
CPU time 423.13 seconds
Started Mar 12 12:53:09 PM PDT 24
Finished Mar 12 01:00:13 PM PDT 24
Peak memory 198928 kb
Host smart-a3c2b350-6cd7-4a63-8340-37ad5fd5ed36
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569054295 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.569054295
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.aon_timer_jump.1607817943
Short name T25
Test name
Test status
Simulation time 582632213 ps
CPU time 0.75 seconds
Started Mar 12 12:52:56 PM PDT 24
Finished Mar 12 12:52:57 PM PDT 24
Peak memory 183948 kb
Host smart-0bd18b03-d144-45d4-9152-fdeb468e1c5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607817943 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.1607817943
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.29197944
Short name T266
Test name
Test status
Simulation time 13601414803 ps
CPU time 5.74 seconds
Started Mar 12 12:52:44 PM PDT 24
Finished Mar 12 12:52:50 PM PDT 24
Peak memory 192232 kb
Host smart-9f219aa3-cbd8-47b1-8d81-ffc5e4f59c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29197944 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.29197944
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.3707444228
Short name T121
Test name
Test status
Simulation time 442245826 ps
CPU time 0.73 seconds
Started Mar 12 12:52:56 PM PDT 24
Finished Mar 12 12:52:57 PM PDT 24
Peak memory 183940 kb
Host smart-9157291c-455d-4f0c-ba08-d88938464ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707444228 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.3707444228
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.81339554
Short name T13
Test name
Test status
Simulation time 5294062730 ps
CPU time 2.21 seconds
Started Mar 12 12:53:05 PM PDT 24
Finished Mar 12 12:53:07 PM PDT 24
Peak memory 184076 kb
Host smart-05749fbd-4112-41f0-996e-449fb9d4345b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81339554 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_al
l.81339554
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.3740677235
Short name T85
Test name
Test status
Simulation time 33231333054 ps
CPU time 41.73 seconds
Started Mar 12 12:52:48 PM PDT 24
Finished Mar 12 12:53:30 PM PDT 24
Peak memory 198980 kb
Host smart-28aa2310-82a4-4e17-b3ba-012911f31f87
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740677235 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand_reset.3740677235
Directory /workspace/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.aon_timer_jump.712299638
Short name T218
Test name
Test status
Simulation time 436206645 ps
CPU time 0.77 seconds
Started Mar 12 12:52:58 PM PDT 24
Finished Mar 12 12:52:59 PM PDT 24
Peak memory 183980 kb
Host smart-6f6b7652-7712-46b2-9b45-2ccd02fc9616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712299638 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.712299638
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.3916250929
Short name T245
Test name
Test status
Simulation time 2728255193 ps
CPU time 1.56 seconds
Started Mar 12 12:53:01 PM PDT 24
Finished Mar 12 12:53:03 PM PDT 24
Peak memory 184096 kb
Host smart-cfa2a71f-9028-4756-89ff-04e5abf27458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916250929 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.3916250929
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.300445033
Short name T177
Test name
Test status
Simulation time 447964039 ps
CPU time 0.67 seconds
Started Mar 12 12:52:56 PM PDT 24
Finished Mar 12 12:52:57 PM PDT 24
Peak memory 183948 kb
Host smart-c3a79034-47a2-4af7-b1a1-52fe5dce9aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300445033 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.300445033
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.1015823048
Short name T146
Test name
Test status
Simulation time 3243649919 ps
CPU time 3.28 seconds
Started Mar 12 12:52:58 PM PDT 24
Finished Mar 12 12:53:02 PM PDT 24
Peak memory 184052 kb
Host smart-bc8c2ea8-1a2f-42f6-b334-78388fddf496
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015823048 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_
all.1015823048
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.133742342
Short name T200
Test name
Test status
Simulation time 175452393549 ps
CPU time 130.02 seconds
Started Mar 12 12:52:49 PM PDT 24
Finished Mar 12 12:55:00 PM PDT 24
Peak memory 198868 kb
Host smart-87a5aa02-7b81-46ef-bacc-372412a7ffa2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133742342 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.133742342
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_jump.489391843
Short name T127
Test name
Test status
Simulation time 494984035 ps
CPU time 1.26 seconds
Started Mar 12 12:52:47 PM PDT 24
Finished Mar 12 12:52:48 PM PDT 24
Peak memory 183964 kb
Host smart-5160fdaf-3208-448e-803f-20030e9313a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489391843 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.489391843
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.3785048488
Short name T153
Test name
Test status
Simulation time 22360102429 ps
CPU time 8.63 seconds
Started Mar 12 12:52:26 PM PDT 24
Finished Mar 12 12:52:35 PM PDT 24
Peak memory 184056 kb
Host smart-beab1b55-c9e5-4a62-a4cd-f5a9d393769d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785048488 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.3785048488
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.2137293837
Short name T19
Test name
Test status
Simulation time 4081558955 ps
CPU time 1.97 seconds
Started Mar 12 12:52:36 PM PDT 24
Finished Mar 12 12:52:38 PM PDT 24
Peak memory 215464 kb
Host smart-70f68276-0b93-4db0-888d-00dd21f1e293
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137293837 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.2137293837
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.3233057084
Short name T107
Test name
Test status
Simulation time 509382770 ps
CPU time 1.4 seconds
Started Mar 12 12:52:13 PM PDT 24
Finished Mar 12 12:52:15 PM PDT 24
Peak memory 183956 kb
Host smart-eb389ce8-4abb-4db8-82be-3127bd504ff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233057084 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.3233057084
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.2340293820
Short name T70
Test name
Test status
Simulation time 79972137955 ps
CPU time 132.22 seconds
Started Mar 12 12:52:41 PM PDT 24
Finished Mar 12 12:54:54 PM PDT 24
Peak memory 194280 kb
Host smart-1b442946-2cec-4da7-980e-4ec2002bf13b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340293820 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_a
ll.2340293820
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.3895118493
Short name T82
Test name
Test status
Simulation time 98092091851 ps
CPU time 186.4 seconds
Started Mar 12 12:52:15 PM PDT 24
Finished Mar 12 12:55:21 PM PDT 24
Peak memory 198936 kb
Host smart-70bcfdbf-3135-432c-92ae-2dd8069e05d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895118493 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.3895118493
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.aon_timer_jump.54186670
Short name T22
Test name
Test status
Simulation time 581075110 ps
CPU time 0.82 seconds
Started Mar 12 12:52:50 PM PDT 24
Finished Mar 12 12:52:51 PM PDT 24
Peak memory 184004 kb
Host smart-2ce62061-6b8d-4c86-9bea-9803e3cf62e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54186670 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.54186670
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.2248583684
Short name T2
Test name
Test status
Simulation time 34921756529 ps
CPU time 11.63 seconds
Started Mar 12 12:52:51 PM PDT 24
Finished Mar 12 12:53:03 PM PDT 24
Peak memory 184112 kb
Host smart-f8b96b17-1fd8-4525-a782-1fd1aadb0e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248583684 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.2248583684
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.2499413239
Short name T205
Test name
Test status
Simulation time 471152151 ps
CPU time 1.15 seconds
Started Mar 12 12:52:51 PM PDT 24
Finished Mar 12 12:52:53 PM PDT 24
Peak memory 183988 kb
Host smart-c3b49daa-17b4-43fd-b3f8-806c6772c3d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499413239 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.2499413239
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.3669920977
Short name T161
Test name
Test status
Simulation time 123397061933 ps
CPU time 42.74 seconds
Started Mar 12 12:52:53 PM PDT 24
Finished Mar 12 12:53:36 PM PDT 24
Peak memory 184096 kb
Host smart-70a72cc8-0938-4e1b-a360-41639f64b138
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669920977 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_
all.3669920977
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.3517355810
Short name T172
Test name
Test status
Simulation time 297185036463 ps
CPU time 796.09 seconds
Started Mar 12 12:52:50 PM PDT 24
Finished Mar 12 01:06:07 PM PDT 24
Peak memory 202988 kb
Host smart-b31619de-a112-4209-b742-e48dce420f17
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517355810 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.3517355810
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.aon_timer_jump.2497191131
Short name T279
Test name
Test status
Simulation time 553180633 ps
CPU time 0.72 seconds
Started Mar 12 12:52:56 PM PDT 24
Finished Mar 12 12:52:58 PM PDT 24
Peak memory 183900 kb
Host smart-a286976a-49d7-48fd-a5a2-c2c0e5078eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497191131 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.2497191131
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.2034670394
Short name T201
Test name
Test status
Simulation time 20924307676 ps
CPU time 31.32 seconds
Started Mar 12 12:52:49 PM PDT 24
Finished Mar 12 12:53:21 PM PDT 24
Peak memory 184100 kb
Host smart-66c59d04-c51c-4699-9cc6-c1a51cb05172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034670394 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.2034670394
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.1410910113
Short name T113
Test name
Test status
Simulation time 405258497 ps
CPU time 1.12 seconds
Started Mar 12 12:52:51 PM PDT 24
Finished Mar 12 12:52:52 PM PDT 24
Peak memory 184008 kb
Host smart-365ad8f4-280c-443a-979f-ff41ad7c12c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410910113 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.1410910113
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.776796364
Short name T199
Test name
Test status
Simulation time 5507212688 ps
CPU time 8.8 seconds
Started Mar 12 12:52:53 PM PDT 24
Finished Mar 12 12:53:02 PM PDT 24
Peak memory 184032 kb
Host smart-ea4a8826-cdf5-4614-bfd8-c6a822fee8af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776796364 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_a
ll.776796364
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.4039320675
Short name T44
Test name
Test status
Simulation time 433956939209 ps
CPU time 901.65 seconds
Started Mar 12 12:52:51 PM PDT 24
Finished Mar 12 01:07:53 PM PDT 24
Peak memory 203260 kb
Host smart-1581bdfd-b744-4822-809e-407b3f44d068
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039320675 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.4039320675
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.aon_timer_jump.1844005110
Short name T147
Test name
Test status
Simulation time 544281978 ps
CPU time 0.84 seconds
Started Mar 12 12:53:06 PM PDT 24
Finished Mar 12 12:53:07 PM PDT 24
Peak memory 183956 kb
Host smart-4d7f76e8-a947-42a8-ad97-2cb347def83c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844005110 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.1844005110
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.3731314076
Short name T188
Test name
Test status
Simulation time 50405466554 ps
CPU time 41.62 seconds
Started Mar 12 12:53:05 PM PDT 24
Finished Mar 12 12:53:46 PM PDT 24
Peak memory 184068 kb
Host smart-a3f226b2-e772-42bb-8f62-265bb308a574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731314076 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.3731314076
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.2215247172
Short name T275
Test name
Test status
Simulation time 401797851 ps
CPU time 0.68 seconds
Started Mar 12 12:52:51 PM PDT 24
Finished Mar 12 12:52:52 PM PDT 24
Peak memory 183916 kb
Host smart-438d4ad6-271e-4c6f-bb30-522e2e93111a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215247172 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.2215247172
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.3456176241
Short name T163
Test name
Test status
Simulation time 93187460543 ps
CPU time 74.71 seconds
Started Mar 12 12:52:50 PM PDT 24
Finished Mar 12 12:54:05 PM PDT 24
Peak memory 184120 kb
Host smart-8068530c-cc41-47dd-98b3-97ca52e5bdf3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456176241 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_
all.3456176241
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.1085721610
Short name T267
Test name
Test status
Simulation time 100034517820 ps
CPU time 368.79 seconds
Started Mar 12 12:52:50 PM PDT 24
Finished Mar 12 12:59:00 PM PDT 24
Peak memory 198864 kb
Host smart-f2d5a39f-06f2-479b-81dd-06ba9649af53
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085721610 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.1085721610
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.aon_timer_jump.2180330759
Short name T207
Test name
Test status
Simulation time 377586983 ps
CPU time 1.1 seconds
Started Mar 12 12:52:54 PM PDT 24
Finished Mar 12 12:52:55 PM PDT 24
Peak memory 183948 kb
Host smart-1c533fad-4d8e-4514-80f0-e118e8287588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180330759 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.2180330759
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.1568977347
Short name T97
Test name
Test status
Simulation time 60712654903 ps
CPU time 98.03 seconds
Started Mar 12 12:52:53 PM PDT 24
Finished Mar 12 12:54:32 PM PDT 24
Peak memory 192316 kb
Host smart-6bc42f71-a39e-4800-ab4f-3f485a9b5d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568977347 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.1568977347
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.2929829746
Short name T248
Test name
Test status
Simulation time 602376831 ps
CPU time 0.77 seconds
Started Mar 12 12:52:51 PM PDT 24
Finished Mar 12 12:52:52 PM PDT 24
Peak memory 183964 kb
Host smart-0e1f62c9-17ae-424e-a4a7-cf5baf29ba06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929829746 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.2929829746
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.570494411
Short name T217
Test name
Test status
Simulation time 154416932430 ps
CPU time 248.58 seconds
Started Mar 12 12:52:53 PM PDT 24
Finished Mar 12 12:57:03 PM PDT 24
Peak memory 195644 kb
Host smart-5d23fa59-5bb7-498f-be93-a2a84c9e0252
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570494411 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_a
ll.570494411
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.3728803587
Short name T231
Test name
Test status
Simulation time 103065477238 ps
CPU time 546.63 seconds
Started Mar 12 12:53:05 PM PDT 24
Finished Mar 12 01:02:12 PM PDT 24
Peak memory 207960 kb
Host smart-cb255ed9-6245-4c0a-8a06-aada0e4fb850
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728803587 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.3728803587
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.aon_timer_jump.2585026375
Short name T133
Test name
Test status
Simulation time 408599486 ps
CPU time 1.2 seconds
Started Mar 12 12:52:56 PM PDT 24
Finished Mar 12 12:52:57 PM PDT 24
Peak memory 183900 kb
Host smart-4112b233-ae99-4f18-b434-c52647b16c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585026375 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.2585026375
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.3863135977
Short name T268
Test name
Test status
Simulation time 21871609906 ps
CPU time 7.59 seconds
Started Mar 12 12:52:52 PM PDT 24
Finished Mar 12 12:53:00 PM PDT 24
Peak memory 184116 kb
Host smart-6a87e606-bcc4-4919-962b-c96772cd06d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863135977 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.3863135977
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.3241868321
Short name T215
Test name
Test status
Simulation time 358546795 ps
CPU time 1.11 seconds
Started Mar 12 12:52:47 PM PDT 24
Finished Mar 12 12:52:49 PM PDT 24
Peak memory 184008 kb
Host smart-78302f6c-d953-49a7-bf88-9ba34fdc94ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241868321 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.3241868321
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.3939449613
Short name T27
Test name
Test status
Simulation time 224620801676 ps
CPU time 354.91 seconds
Started Mar 12 12:52:51 PM PDT 24
Finished Mar 12 12:58:47 PM PDT 24
Peak memory 193740 kb
Host smart-8dd209ea-ec9d-49d5-8aa7-3f2c8a8024dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939449613 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_
all.3939449613
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.2948103526
Short name T130
Test name
Test status
Simulation time 15731482804 ps
CPU time 121.58 seconds
Started Mar 12 12:52:56 PM PDT 24
Finished Mar 12 12:54:58 PM PDT 24
Peak memory 198872 kb
Host smart-339262a2-df78-4150-b243-7de18381326c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948103526 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.2948103526
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.aon_timer_jump.497001645
Short name T151
Test name
Test status
Simulation time 553577997 ps
CPU time 0.76 seconds
Started Mar 12 12:52:55 PM PDT 24
Finished Mar 12 12:52:57 PM PDT 24
Peak memory 183928 kb
Host smart-7b39a011-e91e-4141-be20-4285d7fe58ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497001645 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.497001645
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.450638233
Short name T135
Test name
Test status
Simulation time 12656820748 ps
CPU time 5.01 seconds
Started Mar 12 12:52:58 PM PDT 24
Finished Mar 12 12:53:03 PM PDT 24
Peak memory 184064 kb
Host smart-04d7b489-30f1-4aab-a2d6-794f0155eb47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450638233 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.450638233
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.103620071
Short name T115
Test name
Test status
Simulation time 566767344 ps
CPU time 0.91 seconds
Started Mar 12 12:52:56 PM PDT 24
Finished Mar 12 12:52:57 PM PDT 24
Peak memory 183904 kb
Host smart-96fd0aee-34f8-4410-9788-77c34867fc8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103620071 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.103620071
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.140754614
Short name T158
Test name
Test status
Simulation time 110730747771 ps
CPU time 15.58 seconds
Started Mar 12 12:52:52 PM PDT 24
Finished Mar 12 12:53:07 PM PDT 24
Peak memory 195792 kb
Host smart-c38947d5-538c-4bc1-aa7a-fcfa3cb274a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140754614 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_a
ll.140754614
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/46.aon_timer_jump.891253685
Short name T125
Test name
Test status
Simulation time 551522003 ps
CPU time 0.99 seconds
Started Mar 12 12:52:49 PM PDT 24
Finished Mar 12 12:52:50 PM PDT 24
Peak memory 183920 kb
Host smart-b804fb28-7a15-45c2-9ee0-d0baef33bf5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891253685 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.891253685
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.433000678
Short name T173
Test name
Test status
Simulation time 18883543084 ps
CPU time 15.27 seconds
Started Mar 12 12:52:51 PM PDT 24
Finished Mar 12 12:53:06 PM PDT 24
Peak memory 184044 kb
Host smart-6b1152fd-5e68-40ae-a1dc-4ef5d7542917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433000678 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.433000678
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.4154020690
Short name T126
Test name
Test status
Simulation time 597589314 ps
CPU time 1.08 seconds
Started Mar 12 12:52:56 PM PDT 24
Finished Mar 12 12:52:58 PM PDT 24
Peak memory 183932 kb
Host smart-68ebb195-d799-4a02-91fb-2395e9355dad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154020690 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.4154020690
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.2537661061
Short name T213
Test name
Test status
Simulation time 202769474933 ps
CPU time 161.48 seconds
Started Mar 12 12:52:49 PM PDT 24
Finished Mar 12 12:55:30 PM PDT 24
Peak memory 184108 kb
Host smart-3ffcef8f-0b39-466d-a0c5-ea74e713c241
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537661061 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_
all.2537661061
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.515391319
Short name T4
Test name
Test status
Simulation time 31161985273 ps
CPU time 173.56 seconds
Started Mar 12 12:52:57 PM PDT 24
Finished Mar 12 12:55:51 PM PDT 24
Peak memory 198900 kb
Host smart-6ec0d553-a344-4d72-9816-36c6f8326e8c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515391319 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.515391319
Directory /workspace/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.aon_timer_jump.2276835388
Short name T123
Test name
Test status
Simulation time 479570179 ps
CPU time 0.87 seconds
Started Mar 12 12:52:55 PM PDT 24
Finished Mar 12 12:52:56 PM PDT 24
Peak memory 183888 kb
Host smart-2a84c36c-d141-49be-9213-e6557df3c302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276835388 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.2276835388
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.2371620875
Short name T194
Test name
Test status
Simulation time 14463730133 ps
CPU time 4.09 seconds
Started Mar 12 12:52:59 PM PDT 24
Finished Mar 12 12:53:03 PM PDT 24
Peak memory 192264 kb
Host smart-6a141e57-d057-46be-8d13-7e440f89d98e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371620875 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.2371620875
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.1007029237
Short name T251
Test name
Test status
Simulation time 534832121 ps
CPU time 1.06 seconds
Started Mar 12 12:53:00 PM PDT 24
Finished Mar 12 12:53:01 PM PDT 24
Peak memory 183968 kb
Host smart-f496a45d-d947-4e9b-9ec8-36cbc48cd450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007029237 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.1007029237
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.3758221897
Short name T254
Test name
Test status
Simulation time 66098819992 ps
CPU time 103.63 seconds
Started Mar 12 12:53:05 PM PDT 24
Finished Mar 12 12:54:49 PM PDT 24
Peak memory 184064 kb
Host smart-935d889c-52c0-4b83-bf95-4645ca739300
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758221897 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_
all.3758221897
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.61003692
Short name T270
Test name
Test status
Simulation time 6076198950 ps
CPU time 11.28 seconds
Started Mar 12 12:52:59 PM PDT 24
Finished Mar 12 12:53:11 PM PDT 24
Peak memory 198868 kb
Host smart-132aca31-a29f-4ca5-8143-43749be59135
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61003692 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.61003692
Directory /workspace/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_jump.2989769377
Short name T139
Test name
Test status
Simulation time 508924706 ps
CPU time 1.28 seconds
Started Mar 12 12:52:51 PM PDT 24
Finished Mar 12 12:52:52 PM PDT 24
Peak memory 183956 kb
Host smart-ad819483-07ff-49b7-8e1e-518e087d1fe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989769377 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.2989769377
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.1934289011
Short name T256
Test name
Test status
Simulation time 59781014227 ps
CPU time 17.27 seconds
Started Mar 12 12:52:52 PM PDT 24
Finished Mar 12 12:53:10 PM PDT 24
Peak memory 184116 kb
Host smart-9181f0b9-5b3f-4635-80a2-1d44a52d171d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934289011 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.1934289011
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.2413658765
Short name T170
Test name
Test status
Simulation time 506945162 ps
CPU time 1.26 seconds
Started Mar 12 12:52:54 PM PDT 24
Finished Mar 12 12:52:56 PM PDT 24
Peak memory 183964 kb
Host smart-7d99c480-6067-42da-9abd-02f00337a373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413658765 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.2413658765
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.2557334319
Short name T116
Test name
Test status
Simulation time 255303660710 ps
CPU time 339.77 seconds
Started Mar 12 12:52:56 PM PDT 24
Finished Mar 12 12:58:36 PM PDT 24
Peak memory 184064 kb
Host smart-7691b7b4-9516-4179-a2f0-396d7e3ce2d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557334319 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_
all.2557334319
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.2632392525
Short name T191
Test name
Test status
Simulation time 106300573963 ps
CPU time 163.38 seconds
Started Mar 12 12:53:01 PM PDT 24
Finished Mar 12 12:55:45 PM PDT 24
Peak memory 198960 kb
Host smart-a13587ba-bcce-48a6-ab72-7c30d73f62af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632392525 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.2632392525
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.aon_timer_jump.2067027103
Short name T23
Test name
Test status
Simulation time 565239013 ps
CPU time 1.35 seconds
Started Mar 12 12:53:03 PM PDT 24
Finished Mar 12 12:53:04 PM PDT 24
Peak memory 183972 kb
Host smart-b0024b9f-ce99-4fe6-ae24-fc0b1f98784b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067027103 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.2067027103
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.3644282549
Short name T208
Test name
Test status
Simulation time 48876700395 ps
CPU time 8.81 seconds
Started Mar 12 12:52:54 PM PDT 24
Finished Mar 12 12:53:04 PM PDT 24
Peak memory 192316 kb
Host smart-cd09edef-7c88-4f68-b2d6-0f277f47def5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644282549 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.3644282549
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.741926256
Short name T69
Test name
Test status
Simulation time 491940590 ps
CPU time 0.79 seconds
Started Mar 12 12:53:01 PM PDT 24
Finished Mar 12 12:53:02 PM PDT 24
Peak memory 183972 kb
Host smart-b3b79a32-7260-4eff-bba3-ffcba0ecb058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741926256 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.741926256
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.645999510
Short name T95
Test name
Test status
Simulation time 107224520841 ps
CPU time 46.39 seconds
Started Mar 12 12:53:03 PM PDT 24
Finished Mar 12 12:53:50 PM PDT 24
Peak memory 184088 kb
Host smart-adf91ab5-8c83-4a09-b4ac-f74c5c751ed3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645999510 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_a
ll.645999510
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.489387994
Short name T89
Test name
Test status
Simulation time 83599638491 ps
CPU time 638.57 seconds
Started Mar 12 12:52:55 PM PDT 24
Finished Mar 12 01:03:34 PM PDT 24
Peak memory 199668 kb
Host smart-0394336f-2671-499d-8954-dea72b95b9ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489387994 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.489387994
Directory /workspace/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.aon_timer_jump.1565589209
Short name T108
Test name
Test status
Simulation time 548612048 ps
CPU time 0.96 seconds
Started Mar 12 12:52:21 PM PDT 24
Finished Mar 12 12:52:22 PM PDT 24
Peak memory 183984 kb
Host smart-0dc0de81-0406-482c-9a58-9bffbaafe6de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565589209 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.1565589209
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.1495728308
Short name T142
Test name
Test status
Simulation time 24570501007 ps
CPU time 10.06 seconds
Started Mar 12 12:52:26 PM PDT 24
Finished Mar 12 12:52:36 PM PDT 24
Peak memory 192260 kb
Host smart-6b5c87e0-6c91-4610-baf8-4ebdf5f33b58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495728308 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.1495728308
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.3021851342
Short name T71
Test name
Test status
Simulation time 407947799 ps
CPU time 0.68 seconds
Started Mar 12 12:52:17 PM PDT 24
Finished Mar 12 12:52:18 PM PDT 24
Peak memory 183956 kb
Host smart-c3616ea4-1426-4bc8-92b2-24d9bbe3b880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021851342 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.3021851342
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.3346149715
Short name T253
Test name
Test status
Simulation time 202705696188 ps
CPU time 81.56 seconds
Started Mar 12 12:52:31 PM PDT 24
Finished Mar 12 12:53:52 PM PDT 24
Peak memory 194268 kb
Host smart-74929e06-bd0c-4444-a0f7-a657e5d69a82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346149715 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_a
ll.3346149715
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.3954099843
Short name T48
Test name
Test status
Simulation time 269595350640 ps
CPU time 673.52 seconds
Started Mar 12 12:52:22 PM PDT 24
Finished Mar 12 01:03:35 PM PDT 24
Peak memory 200912 kb
Host smart-837e8cf3-44a7-4c24-b250-71cde4226f85
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954099843 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.3954099843
Directory /workspace/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.aon_timer_jump.445079768
Short name T244
Test name
Test status
Simulation time 509767493 ps
CPU time 0.78 seconds
Started Mar 12 12:52:25 PM PDT 24
Finished Mar 12 12:52:26 PM PDT 24
Peak memory 184000 kb
Host smart-fa951a8c-1a0e-441d-93f1-22b74384bc99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445079768 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.445079768
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.1370703548
Short name T233
Test name
Test status
Simulation time 8315672947 ps
CPU time 13.86 seconds
Started Mar 12 12:52:18 PM PDT 24
Finished Mar 12 12:52:32 PM PDT 24
Peak memory 184060 kb
Host smart-cf4795b5-749c-4960-a0a2-d86cf992d694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370703548 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.1370703548
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.1148991634
Short name T246
Test name
Test status
Simulation time 382335556 ps
CPU time 0.68 seconds
Started Mar 12 12:52:22 PM PDT 24
Finished Mar 12 12:52:23 PM PDT 24
Peak memory 183772 kb
Host smart-92c42702-0bfa-464e-9c8b-c47d7cc25e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148991634 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.1148991634
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.1331304166
Short name T92
Test name
Test status
Simulation time 129289043690 ps
CPU time 194.62 seconds
Started Mar 12 12:52:19 PM PDT 24
Finished Mar 12 12:55:34 PM PDT 24
Peak memory 184024 kb
Host smart-9e9bcc99-6296-4501-96cc-59b2b9cd7331
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331304166 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_a
ll.1331304166
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_jump.1913872663
Short name T119
Test name
Test status
Simulation time 584056099 ps
CPU time 0.58 seconds
Started Mar 12 12:52:18 PM PDT 24
Finished Mar 12 12:52:18 PM PDT 24
Peak memory 183884 kb
Host smart-050e05a1-fd31-4beb-babb-92b4d62a348b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913872663 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.1913872663
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.3194204102
Short name T160
Test name
Test status
Simulation time 27497427829 ps
CPU time 12.82 seconds
Started Mar 12 12:52:31 PM PDT 24
Finished Mar 12 12:52:44 PM PDT 24
Peak memory 192216 kb
Host smart-ab3f40c2-c38b-48b6-891d-8bea84730859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194204102 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.3194204102
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.1846042947
Short name T192
Test name
Test status
Simulation time 450622231 ps
CPU time 1.24 seconds
Started Mar 12 12:52:31 PM PDT 24
Finished Mar 12 12:52:32 PM PDT 24
Peak memory 183948 kb
Host smart-d8c6cbb8-3375-4611-8833-96523ebef83a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846042947 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.1846042947
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.4202513868
Short name T273
Test name
Test status
Simulation time 9504149792 ps
CPU time 1.77 seconds
Started Mar 12 12:52:08 PM PDT 24
Finished Mar 12 12:52:11 PM PDT 24
Peak memory 184132 kb
Host smart-a23ead6f-b57d-4dfb-9d5d-6eafba0ca6d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202513868 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_a
ll.4202513868
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.2802579089
Short name T171
Test name
Test status
Simulation time 79317541217 ps
CPU time 443.76 seconds
Started Mar 12 12:52:16 PM PDT 24
Finished Mar 12 12:59:40 PM PDT 24
Peak memory 198844 kb
Host smart-a88b47df-2f49-4e04-828e-634f6e1551c3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802579089 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.2802579089
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.aon_timer_jump.3891049776
Short name T180
Test name
Test status
Simulation time 577439384 ps
CPU time 1.45 seconds
Started Mar 12 12:52:09 PM PDT 24
Finished Mar 12 12:52:11 PM PDT 24
Peak memory 183920 kb
Host smart-ad819afb-2734-4969-a19e-0c5091e841c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891049776 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.3891049776
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.524698173
Short name T8
Test name
Test status
Simulation time 22100182154 ps
CPU time 27.85 seconds
Started Mar 12 12:52:21 PM PDT 24
Finished Mar 12 12:52:49 PM PDT 24
Peak memory 184060 kb
Host smart-765e6355-42d7-4043-b9eb-e35edaac97d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524698173 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.524698173
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.3973369766
Short name T175
Test name
Test status
Simulation time 371418878 ps
CPU time 0.83 seconds
Started Mar 12 12:52:33 PM PDT 24
Finished Mar 12 12:52:40 PM PDT 24
Peak memory 183988 kb
Host smart-8c3296a9-9b95-4901-b024-38469fcd3b8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973369766 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.3973369766
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.2749963103
Short name T168
Test name
Test status
Simulation time 6227756675 ps
CPU time 9.44 seconds
Started Mar 12 12:52:33 PM PDT 24
Finished Mar 12 12:52:43 PM PDT 24
Peak memory 195408 kb
Host smart-8b2445ff-a5fb-4cb6-9fb5-db75d42a9b2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749963103 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_a
ll.2749963103
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.2306674892
Short name T165
Test name
Test status
Simulation time 6482418480 ps
CPU time 60.88 seconds
Started Mar 12 12:52:36 PM PDT 24
Finished Mar 12 12:53:38 PM PDT 24
Peak memory 198848 kb
Host smart-7a105d03-08bf-4c23-8713-1fe95ab0bd6a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306674892 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.2306674892
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.2537717912
Short name T7
Test name
Test status
Simulation time 27443254318 ps
CPU time 9.81 seconds
Started Mar 12 12:52:30 PM PDT 24
Finished Mar 12 12:52:40 PM PDT 24
Peak memory 184004 kb
Host smart-0c5b5a1c-3ae9-4d6e-af19-c671ddfb64e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537717912 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.2537717912
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.1909938988
Short name T240
Test name
Test status
Simulation time 599199529 ps
CPU time 0.75 seconds
Started Mar 12 12:52:13 PM PDT 24
Finished Mar 12 12:52:14 PM PDT 24
Peak memory 183828 kb
Host smart-d20c670b-6240-4ff3-b189-0a1bde7aacc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909938988 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.1909938988
Directory /workspace/9.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.3481788274
Short name T220
Test name
Test status
Simulation time 122349187506 ps
CPU time 143.57 seconds
Started Mar 12 12:52:24 PM PDT 24
Finished Mar 12 12:54:48 PM PDT 24
Peak memory 198908 kb
Host smart-7c5e25b4-1c94-4466-a0d2-d1a255848e9b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481788274 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.3481788274
Directory /workspace/9.aon_timer_stress_all_with_rand_reset/latest
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