Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
92.98 99.25 93.67 100.00 98.40 99.51 67.06


Total test records in report: 422
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T30 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.4024383840 Mar 14 12:23:37 PM PDT 24 Mar 14 12:23:38 PM PDT 24 520300337 ps
T32 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.2727892078 Mar 14 12:23:31 PM PDT 24 Mar 14 12:23:38 PM PDT 24 2728200281 ps
T96 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.2548509403 Mar 14 12:23:29 PM PDT 24 Mar 14 12:23:29 PM PDT 24 504507770 ps
T288 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.3070624593 Mar 14 12:24:47 PM PDT 24 Mar 14 12:24:48 PM PDT 24 348000342 ps
T289 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.964004122 Mar 14 12:24:45 PM PDT 24 Mar 14 12:24:46 PM PDT 24 333033024 ps
T33 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.2330652232 Mar 14 12:23:44 PM PDT 24 Mar 14 12:23:48 PM PDT 24 8216199245 ps
T95 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.1070732417 Mar 14 12:24:57 PM PDT 24 Mar 14 12:24:59 PM PDT 24 427019729 ps
T290 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.2207048925 Mar 14 12:24:51 PM PDT 24 Mar 14 12:24:52 PM PDT 24 354266577 ps
T74 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.990984793 Mar 14 12:23:43 PM PDT 24 Mar 14 12:23:48 PM PDT 24 1721535970 ps
T291 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.1910129833 Mar 14 12:23:26 PM PDT 24 Mar 14 12:23:27 PM PDT 24 511230618 ps
T292 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.1487204217 Mar 14 12:24:02 PM PDT 24 Mar 14 12:24:05 PM PDT 24 679998665 ps
T293 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.484074951 Mar 14 12:24:48 PM PDT 24 Mar 14 12:24:49 PM PDT 24 387952027 ps
T75 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.1453741281 Mar 14 12:24:25 PM PDT 24 Mar 14 12:24:26 PM PDT 24 320690364 ps
T294 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.1616495387 Mar 14 12:24:25 PM PDT 24 Mar 14 12:24:27 PM PDT 24 569860356 ps
T76 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.322343084 Mar 14 12:24:25 PM PDT 24 Mar 14 12:24:27 PM PDT 24 419266479 ps
T34 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.241977674 Mar 14 12:24:31 PM PDT 24 Mar 14 12:24:32 PM PDT 24 4611798217 ps
T35 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.3093747096 Mar 14 12:23:44 PM PDT 24 Mar 14 12:23:58 PM PDT 24 8297054117 ps
T295 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.2950678762 Mar 14 12:23:27 PM PDT 24 Mar 14 12:23:28 PM PDT 24 825554075 ps
T58 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.2191526935 Mar 14 12:24:00 PM PDT 24 Mar 14 12:24:01 PM PDT 24 484400619 ps
T296 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.374054675 Mar 14 12:24:45 PM PDT 24 Mar 14 12:24:51 PM PDT 24 530715419 ps
T297 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.860748251 Mar 14 12:23:24 PM PDT 24 Mar 14 12:23:27 PM PDT 24 911917453 ps
T298 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.1803531736 Mar 14 12:24:38 PM PDT 24 Mar 14 12:24:39 PM PDT 24 485195206 ps
T77 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.2907754643 Mar 14 12:24:00 PM PDT 24 Mar 14 12:24:04 PM PDT 24 2629520347 ps
T299 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.1993631863 Mar 14 12:24:41 PM PDT 24 Mar 14 12:24:42 PM PDT 24 527872377 ps
T300 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.412799536 Mar 14 12:24:46 PM PDT 24 Mar 14 12:24:48 PM PDT 24 495646709 ps
T59 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.2675541883 Mar 14 12:24:31 PM PDT 24 Mar 14 12:24:32 PM PDT 24 515128433 ps
T301 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.1146756601 Mar 14 12:24:49 PM PDT 24 Mar 14 12:24:51 PM PDT 24 424143369 ps
T78 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.3255922835 Mar 14 12:24:24 PM PDT 24 Mar 14 12:24:27 PM PDT 24 2300253565 ps
T60 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.1756598167 Mar 14 12:21:34 PM PDT 24 Mar 14 12:21:36 PM PDT 24 498233248 ps
T302 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.2412271250 Mar 14 12:24:47 PM PDT 24 Mar 14 12:24:50 PM PDT 24 573449062 ps
T303 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.1499100245 Mar 14 12:24:26 PM PDT 24 Mar 14 12:24:29 PM PDT 24 889372040 ps
T304 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.1945877085 Mar 14 12:23:43 PM PDT 24 Mar 14 12:23:44 PM PDT 24 563403538 ps
T305 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.1058366439 Mar 14 12:24:40 PM PDT 24 Mar 14 12:24:41 PM PDT 24 503574094 ps
T306 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.76331107 Mar 14 12:23:37 PM PDT 24 Mar 14 12:23:38 PM PDT 24 292549019 ps
T307 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.1465969062 Mar 14 12:24:48 PM PDT 24 Mar 14 12:24:49 PM PDT 24 721070098 ps
T308 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.224324341 Mar 14 12:24:18 PM PDT 24 Mar 14 12:24:19 PM PDT 24 396637537 ps
T61 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.17714281 Mar 14 12:24:24 PM PDT 24 Mar 14 12:24:25 PM PDT 24 340488589 ps
T309 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.3852917208 Mar 14 12:24:23 PM PDT 24 Mar 14 12:24:25 PM PDT 24 365918280 ps
T310 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.2523735141 Mar 14 12:24:57 PM PDT 24 Mar 14 12:25:00 PM PDT 24 445505486 ps
T62 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.3429638191 Mar 14 12:19:08 PM PDT 24 Mar 14 12:19:09 PM PDT 24 1221141817 ps
T63 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.3878512817 Mar 14 12:24:48 PM PDT 24 Mar 14 12:24:52 PM PDT 24 4406102291 ps
T311 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.1481922006 Mar 14 12:23:39 PM PDT 24 Mar 14 12:23:40 PM PDT 24 426654595 ps
T89 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.2077709315 Mar 14 12:24:31 PM PDT 24 Mar 14 12:24:39 PM PDT 24 4157967758 ps
T312 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.3517021218 Mar 14 12:24:24 PM PDT 24 Mar 14 12:24:25 PM PDT 24 533211186 ps
T313 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.2645861169 Mar 14 12:20:02 PM PDT 24 Mar 14 12:20:04 PM PDT 24 501777722 ps
T314 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.591113068 Mar 14 12:24:31 PM PDT 24 Mar 14 12:24:32 PM PDT 24 398009665 ps
T92 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.811477333 Mar 14 12:24:26 PM PDT 24 Mar 14 12:24:30 PM PDT 24 4207929237 ps
T315 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.2339324587 Mar 14 12:23:56 PM PDT 24 Mar 14 12:23:59 PM PDT 24 520224853 ps
T316 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.1404658954 Mar 14 12:24:48 PM PDT 24 Mar 14 12:24:49 PM PDT 24 588031513 ps
T93 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.2403876764 Mar 14 12:24:02 PM PDT 24 Mar 14 12:24:10 PM PDT 24 4530470241 ps
T317 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.1958420788 Mar 14 12:23:47 PM PDT 24 Mar 14 12:23:50 PM PDT 24 600777485 ps
T318 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.1328659963 Mar 14 12:24:04 PM PDT 24 Mar 14 12:24:06 PM PDT 24 456572074 ps
T319 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.181055149 Mar 14 12:23:24 PM PDT 24 Mar 14 12:23:26 PM PDT 24 315415944 ps
T90 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.3283036995 Mar 14 12:24:01 PM PDT 24 Mar 14 12:24:06 PM PDT 24 8237972609 ps
T320 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.1581549322 Mar 14 12:24:46 PM PDT 24 Mar 14 12:24:48 PM PDT 24 479426902 ps
T321 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.1621485087 Mar 14 12:24:57 PM PDT 24 Mar 14 12:24:59 PM PDT 24 487669424 ps
T322 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.4109028519 Mar 14 12:24:00 PM PDT 24 Mar 14 12:24:01 PM PDT 24 446023050 ps
T323 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.215822746 Mar 14 12:23:25 PM PDT 24 Mar 14 12:23:26 PM PDT 24 324699169 ps
T79 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.853438119 Mar 14 12:24:25 PM PDT 24 Mar 14 12:24:30 PM PDT 24 1259173937 ps
T324 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.243656275 Mar 14 12:24:51 PM PDT 24 Mar 14 12:24:52 PM PDT 24 322421670 ps
T80 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.404177488 Mar 14 12:24:29 PM PDT 24 Mar 14 12:24:30 PM PDT 24 2084166619 ps
T325 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.529505210 Mar 14 12:24:22 PM PDT 24 Mar 14 12:24:24 PM PDT 24 498667157 ps
T64 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.343664248 Mar 14 12:24:49 PM PDT 24 Mar 14 12:25:00 PM PDT 24 6926672522 ps
T91 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.878623143 Mar 14 12:24:06 PM PDT 24 Mar 14 12:24:14 PM PDT 24 8171056480 ps
T326 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.1822438447 Mar 14 12:23:34 PM PDT 24 Mar 14 12:23:35 PM PDT 24 1321522982 ps
T327 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.1614249781 Mar 14 12:23:22 PM PDT 24 Mar 14 12:23:24 PM PDT 24 511993669 ps
T81 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.4091339285 Mar 14 12:24:28 PM PDT 24 Mar 14 12:24:29 PM PDT 24 1341381060 ps
T328 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.1645060297 Mar 14 12:24:31 PM PDT 24 Mar 14 12:24:32 PM PDT 24 529605008 ps
T329 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.2339361767 Mar 14 12:23:33 PM PDT 24 Mar 14 12:23:36 PM PDT 24 4548036006 ps
T330 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.3042777708 Mar 14 12:23:32 PM PDT 24 Mar 14 12:23:38 PM PDT 24 4190356605 ps
T331 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.3428954078 Mar 14 12:24:27 PM PDT 24 Mar 14 12:24:28 PM PDT 24 388617332 ps
T332 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.2084903205 Mar 14 12:23:34 PM PDT 24 Mar 14 12:23:35 PM PDT 24 445728010 ps
T333 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.4033563491 Mar 14 12:24:30 PM PDT 24 Mar 14 12:24:31 PM PDT 24 396165115 ps
T334 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.2328138812 Mar 14 12:20:01 PM PDT 24 Mar 14 12:20:04 PM PDT 24 433991031 ps
T66 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.4268823975 Mar 14 12:24:31 PM PDT 24 Mar 14 12:24:32 PM PDT 24 394928773 ps
T335 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.3042192252 Mar 14 12:24:26 PM PDT 24 Mar 14 12:24:27 PM PDT 24 546635124 ps
T67 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.3848504009 Mar 14 12:19:34 PM PDT 24 Mar 14 12:19:36 PM PDT 24 458798788 ps
T336 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.974628224 Mar 14 12:23:36 PM PDT 24 Mar 14 12:23:37 PM PDT 24 381627006 ps
T337 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.2497986114 Mar 14 12:24:41 PM PDT 24 Mar 14 12:24:41 PM PDT 24 559539492 ps
T338 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.2116473586 Mar 14 12:24:50 PM PDT 24 Mar 14 12:24:53 PM PDT 24 4300957223 ps
T339 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.2631750862 Mar 14 12:24:30 PM PDT 24 Mar 14 12:24:32 PM PDT 24 507962495 ps
T340 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.99747209 Mar 14 12:24:45 PM PDT 24 Mar 14 12:24:47 PM PDT 24 441512811 ps
T341 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.1432420870 Mar 14 12:24:28 PM PDT 24 Mar 14 12:24:32 PM PDT 24 1508879071 ps
T342 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.1098456336 Mar 14 12:23:29 PM PDT 24 Mar 14 12:23:30 PM PDT 24 340026362 ps
T343 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.4153464985 Mar 14 12:24:22 PM PDT 24 Mar 14 12:24:23 PM PDT 24 385972546 ps
T344 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.1227022470 Mar 14 12:24:25 PM PDT 24 Mar 14 12:24:26 PM PDT 24 311529383 ps
T345 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.3159762829 Mar 14 12:24:18 PM PDT 24 Mar 14 12:24:19 PM PDT 24 1223186625 ps
T346 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.3499239306 Mar 14 12:24:25 PM PDT 24 Mar 14 12:24:28 PM PDT 24 4115538740 ps
T94 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.430050442 Mar 14 12:24:00 PM PDT 24 Mar 14 12:24:08 PM PDT 24 8225565055 ps
T347 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.576860022 Mar 14 12:24:30 PM PDT 24 Mar 14 12:24:33 PM PDT 24 2589010831 ps
T348 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.2925818589 Mar 14 12:24:25 PM PDT 24 Mar 14 12:24:25 PM PDT 24 537959210 ps
T349 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.3487961490 Mar 14 12:24:26 PM PDT 24 Mar 14 12:24:27 PM PDT 24 410278703 ps
T350 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.1484835556 Mar 14 12:19:59 PM PDT 24 Mar 14 12:20:01 PM PDT 24 369224470 ps
T351 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.525610290 Mar 14 12:24:01 PM PDT 24 Mar 14 12:24:02 PM PDT 24 482577576 ps
T352 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.1841393346 Mar 14 12:24:01 PM PDT 24 Mar 14 12:24:03 PM PDT 24 811247447 ps
T353 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.2984358780 Mar 14 12:24:26 PM PDT 24 Mar 14 12:24:28 PM PDT 24 1351160392 ps
T354 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.780566789 Mar 14 12:23:42 PM PDT 24 Mar 14 12:23:44 PM PDT 24 594504484 ps
T355 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.1381830031 Mar 14 12:24:25 PM PDT 24 Mar 14 12:24:39 PM PDT 24 7616117313 ps
T68 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.2606982289 Mar 14 12:23:24 PM PDT 24 Mar 14 12:23:25 PM PDT 24 647974646 ps
T356 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.1269790401 Mar 14 12:24:36 PM PDT 24 Mar 14 12:24:37 PM PDT 24 464066177 ps
T357 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.1400585797 Mar 14 12:23:25 PM PDT 24 Mar 14 12:23:33 PM PDT 24 4481553941 ps
T358 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.3083171253 Mar 14 12:24:28 PM PDT 24 Mar 14 12:24:29 PM PDT 24 395274422 ps
T359 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.2015612519 Mar 14 12:24:25 PM PDT 24 Mar 14 12:24:26 PM PDT 24 333734563 ps
T360 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.1785008811 Mar 14 12:24:29 PM PDT 24 Mar 14 12:24:30 PM PDT 24 379886809 ps
T69 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.3418968474 Mar 14 12:23:31 PM PDT 24 Mar 14 12:23:42 PM PDT 24 13843107883 ps
T361 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.2707259580 Mar 14 12:24:58 PM PDT 24 Mar 14 12:24:59 PM PDT 24 452319381 ps
T362 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.1995466052 Mar 14 12:24:57 PM PDT 24 Mar 14 12:25:01 PM PDT 24 434258620 ps
T363 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.450342423 Mar 14 12:23:47 PM PDT 24 Mar 14 12:23:50 PM PDT 24 504322283 ps
T364 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.4266770917 Mar 14 12:24:02 PM PDT 24 Mar 14 12:24:03 PM PDT 24 390605833 ps
T365 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.4231573015 Mar 14 12:23:37 PM PDT 24 Mar 14 12:23:45 PM PDT 24 8458413254 ps
T366 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.682423678 Mar 14 12:24:46 PM PDT 24 Mar 14 12:24:47 PM PDT 24 279101961 ps
T367 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.1747650854 Mar 14 12:24:47 PM PDT 24 Mar 14 12:24:47 PM PDT 24 530932039 ps
T368 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.4264644217 Mar 14 12:23:59 PM PDT 24 Mar 14 12:23:59 PM PDT 24 299175688 ps
T369 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.259965022 Mar 14 12:24:36 PM PDT 24 Mar 14 12:24:37 PM PDT 24 407615952 ps
T370 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.548837195 Mar 14 12:24:46 PM PDT 24 Mar 14 12:24:47 PM PDT 24 507761748 ps
T371 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.3562074081 Mar 14 12:24:20 PM PDT 24 Mar 14 12:24:23 PM PDT 24 984294756 ps
T372 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.3097525783 Mar 14 12:21:06 PM PDT 24 Mar 14 12:21:07 PM PDT 24 485927587 ps
T373 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.2871847624 Mar 14 12:23:36 PM PDT 24 Mar 14 12:23:39 PM PDT 24 421673983 ps
T374 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.3348684862 Mar 14 12:23:44 PM PDT 24 Mar 14 12:23:45 PM PDT 24 401282488 ps
T375 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.1795108536 Mar 14 12:24:39 PM PDT 24 Mar 14 12:24:40 PM PDT 24 457839721 ps
T376 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.3706121211 Mar 14 12:24:25 PM PDT 24 Mar 14 12:24:27 PM PDT 24 491021059 ps
T377 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.3132023248 Mar 14 12:24:22 PM PDT 24 Mar 14 12:24:23 PM PDT 24 529856550 ps
T378 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.2455388957 Mar 14 12:24:26 PM PDT 24 Mar 14 12:24:28 PM PDT 24 486544892 ps
T379 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.3079339722 Mar 14 12:24:35 PM PDT 24 Mar 14 12:24:36 PM PDT 24 391164370 ps
T380 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.18764785 Mar 14 12:23:32 PM PDT 24 Mar 14 12:23:33 PM PDT 24 294923030 ps
T381 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.1064670282 Mar 14 12:21:05 PM PDT 24 Mar 14 12:21:06 PM PDT 24 430831950 ps
T382 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.436487819 Mar 14 12:24:01 PM PDT 24 Mar 14 12:24:02 PM PDT 24 408697062 ps
T383 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.1313051264 Mar 14 12:24:19 PM PDT 24 Mar 14 12:24:21 PM PDT 24 741158338 ps
T384 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.4100974510 Mar 14 12:24:57 PM PDT 24 Mar 14 12:24:58 PM PDT 24 499658161 ps
T385 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.1117814841 Mar 14 12:24:44 PM PDT 24 Mar 14 12:24:45 PM PDT 24 364135822 ps
T386 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.1415783839 Mar 14 12:24:40 PM PDT 24 Mar 14 12:24:42 PM PDT 24 348900827 ps
T70 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.222983405 Mar 14 12:19:09 PM PDT 24 Mar 14 12:19:10 PM PDT 24 920856575 ps
T387 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.2567102024 Mar 14 12:23:44 PM PDT 24 Mar 14 12:23:48 PM PDT 24 1451882334 ps
T388 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.53164071 Mar 14 12:21:23 PM PDT 24 Mar 14 12:21:25 PM PDT 24 502275270 ps
T389 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.2143541616 Mar 14 12:24:19 PM PDT 24 Mar 14 12:24:32 PM PDT 24 8491266524 ps
T390 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.3414107456 Mar 14 12:24:30 PM PDT 24 Mar 14 12:24:31 PM PDT 24 427453296 ps
T391 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.580175788 Mar 14 12:24:23 PM PDT 24 Mar 14 12:24:25 PM PDT 24 2205361326 ps
T392 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.3568422553 Mar 14 12:24:25 PM PDT 24 Mar 14 12:24:27 PM PDT 24 506967784 ps
T393 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.2571873428 Mar 14 12:21:57 PM PDT 24 Mar 14 12:21:59 PM PDT 24 1137937184 ps
T71 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.4183232195 Mar 14 12:21:34 PM PDT 24 Mar 14 12:21:36 PM PDT 24 443239731 ps
T394 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.2505376508 Mar 14 12:24:31 PM PDT 24 Mar 14 12:24:32 PM PDT 24 927265776 ps
T395 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.660427416 Mar 14 12:24:23 PM PDT 24 Mar 14 12:24:25 PM PDT 24 3003078431 ps
T396 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.1235052143 Mar 14 12:23:36 PM PDT 24 Mar 14 12:23:37 PM PDT 24 1604101801 ps
T397 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.3623745242 Mar 14 12:24:25 PM PDT 24 Mar 14 12:24:26 PM PDT 24 338714233 ps
T398 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.1220692325 Mar 14 12:23:48 PM PDT 24 Mar 14 12:23:51 PM PDT 24 891892073 ps
T399 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.1353492793 Mar 14 12:24:57 PM PDT 24 Mar 14 12:24:59 PM PDT 24 438015659 ps
T400 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.3772872867 Mar 14 12:24:31 PM PDT 24 Mar 14 12:24:34 PM PDT 24 8667633107 ps
T401 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.3698087128 Mar 14 12:24:47 PM PDT 24 Mar 14 12:24:49 PM PDT 24 4605839121 ps
T402 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.1569672668 Mar 14 12:23:36 PM PDT 24 Mar 14 12:23:39 PM PDT 24 1296120267 ps
T403 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.373559386 Mar 14 12:24:47 PM PDT 24 Mar 14 12:24:48 PM PDT 24 465259869 ps
T72 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.1817708584 Mar 14 12:24:18 PM PDT 24 Mar 14 12:24:20 PM PDT 24 442150765 ps
T404 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.4176541154 Mar 14 12:24:42 PM PDT 24 Mar 14 12:24:43 PM PDT 24 348267397 ps
T405 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.3318927964 Mar 14 12:23:24 PM PDT 24 Mar 14 12:23:29 PM PDT 24 4457788849 ps
T406 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.20482398 Mar 14 12:23:29 PM PDT 24 Mar 14 12:23:30 PM PDT 24 537791209 ps
T407 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.1297590775 Mar 14 12:24:25 PM PDT 24 Mar 14 12:24:27 PM PDT 24 514710108 ps
T73 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.37744154 Mar 14 12:23:34 PM PDT 24 Mar 14 12:23:38 PM PDT 24 6859728945 ps
T408 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.2654432595 Mar 14 12:23:49 PM PDT 24 Mar 14 12:23:57 PM PDT 24 2414591624 ps
T409 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.2875094166 Mar 14 12:25:00 PM PDT 24 Mar 14 12:25:01 PM PDT 24 457889015 ps
T410 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.1107750327 Mar 14 12:23:25 PM PDT 24 Mar 14 12:23:26 PM PDT 24 332337715 ps
T411 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.1478461413 Mar 14 12:25:00 PM PDT 24 Mar 14 12:25:01 PM PDT 24 2498883332 ps
T412 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.4149925045 Mar 14 12:24:17 PM PDT 24 Mar 14 12:24:18 PM PDT 24 288368424 ps
T413 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.1606337776 Mar 14 12:24:25 PM PDT 24 Mar 14 12:24:27 PM PDT 24 304209063 ps
T414 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.1090480730 Mar 14 12:24:25 PM PDT 24 Mar 14 12:24:26 PM PDT 24 457504266 ps
T65 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.3236839434 Mar 14 12:24:23 PM PDT 24 Mar 14 12:24:24 PM PDT 24 488651671 ps
T415 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.3204086911 Mar 14 12:23:44 PM PDT 24 Mar 14 12:23:45 PM PDT 24 424761774 ps
T416 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.2763592822 Mar 14 12:24:46 PM PDT 24 Mar 14 12:24:47 PM PDT 24 353766893 ps
T417 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.1295749028 Mar 14 12:24:19 PM PDT 24 Mar 14 12:24:20 PM PDT 24 542987343 ps
T418 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.1193859827 Mar 14 12:24:51 PM PDT 24 Mar 14 12:24:52 PM PDT 24 580999727 ps
T419 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.368379253 Mar 14 12:23:27 PM PDT 24 Mar 14 12:23:28 PM PDT 24 2538123755 ps
T420 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.2634203344 Mar 14 12:22:21 PM PDT 24 Mar 14 12:22:22 PM PDT 24 457471012 ps
T421 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.218255677 Mar 14 12:24:45 PM PDT 24 Mar 14 12:24:46 PM PDT 24 484229733 ps
T422 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.3897529667 Mar 14 12:22:00 PM PDT 24 Mar 14 12:22:00 PM PDT 24 474313022 ps

Test location /workspace/coverage/default/26.aon_timer_stress_all.3785369058
Short name T3
Test name
Test status
Simulation time 70318078971 ps
CPU time 25.87 seconds
Started Mar 14 12:27:19 PM PDT 24
Finished Mar 14 12:27:45 PM PDT 24
Peak memory 183468 kb
Host smart-4a91def9-e854-48b3-8b92-031dc361a67f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785369058 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_
all.3785369058
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.2370437038
Short name T36
Test name
Test status
Simulation time 36097252871 ps
CPU time 185.77 seconds
Started Mar 14 12:27:26 PM PDT 24
Finished Mar 14 12:30:32 PM PDT 24
Peak memory 198416 kb
Host smart-a4599920-3ff7-4bdc-a7e4-56764a95e705
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370437038 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.2370437038
Directory /workspace/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.2330652232
Short name T33
Test name
Test status
Simulation time 8216199245 ps
CPU time 3.95 seconds
Started Mar 14 12:23:44 PM PDT 24
Finished Mar 14 12:23:48 PM PDT 24
Peak memory 197732 kb
Host smart-ba56fbf1-4c3b-4c15-ba6c-9dad7f23f767
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330652232 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl
_intg_err.2330652232
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.3400376703
Short name T17
Test name
Test status
Simulation time 103742233115 ps
CPU time 727.57 seconds
Started Mar 14 12:27:24 PM PDT 24
Finished Mar 14 12:39:33 PM PDT 24
Peak memory 200868 kb
Host smart-5fb3a749-1c91-47a1-807f-af38115d2660
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400376703 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.3400376703
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.1756598167
Short name T60
Test name
Test status
Simulation time 498233248 ps
CPU time 1.57 seconds
Started Mar 14 12:21:34 PM PDT 24
Finished Mar 14 12:21:36 PM PDT 24
Peak memory 183632 kb
Host smart-bbfec59e-28bf-442e-8235-c3198a978a99
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756598167 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_a
liasing.1756598167
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.2089670451
Short name T23
Test name
Test status
Simulation time 4416885087 ps
CPU time 4.17 seconds
Started Mar 14 12:27:11 PM PDT 24
Finished Mar 14 12:27:16 PM PDT 24
Peak memory 214996 kb
Host smart-eebf663f-2fe4-4328-99f6-48486235fc63
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089670451 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.2089670451
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.1100885953
Short name T55
Test name
Test status
Simulation time 342729499058 ps
CPU time 502.16 seconds
Started Mar 14 12:27:38 PM PDT 24
Finished Mar 14 12:36:01 PM PDT 24
Peak memory 198396 kb
Host smart-9cd63028-7144-4a73-9f7c-391a61a8de8b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100885953 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.1100885953
Directory /workspace/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.3283036995
Short name T90
Test name
Test status
Simulation time 8237972609 ps
CPU time 4.57 seconds
Started Mar 14 12:24:01 PM PDT 24
Finished Mar 14 12:24:06 PM PDT 24
Peak memory 197912 kb
Host smart-b610713e-8b72-45fa-bcd8-d44b78bbe7d1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283036995 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_t
l_intg_err.3283036995
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.610386486
Short name T40
Test name
Test status
Simulation time 361337825496 ps
CPU time 563.85 seconds
Started Mar 14 12:27:45 PM PDT 24
Finished Mar 14 12:37:09 PM PDT 24
Peak memory 198932 kb
Host smart-ff2f5f5d-56e8-4add-b220-b3ca0835efbe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610386486 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.610386486
Directory /workspace/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.2727892078
Short name T32
Test name
Test status
Simulation time 2728200281 ps
CPU time 6.42 seconds
Started Mar 14 12:23:31 PM PDT 24
Finished Mar 14 12:23:38 PM PDT 24
Peak memory 182056 kb
Host smart-9535bbbd-9b51-4cea-8f1a-d1825cb3f26b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727892078 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon
_timer_same_csr_outstanding.2727892078
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.4183232195
Short name T71
Test name
Test status
Simulation time 443239731 ps
CPU time 1.07 seconds
Started Mar 14 12:21:34 PM PDT 24
Finished Mar 14 12:21:36 PM PDT 24
Peak memory 183720 kb
Host smart-0f1be7f0-ed23-4e47-a6fe-26419933315d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183232195 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_a
liasing.4183232195
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.37744154
Short name T73
Test name
Test status
Simulation time 6859728945 ps
CPU time 3.96 seconds
Started Mar 14 12:23:34 PM PDT 24
Finished Mar 14 12:23:38 PM PDT 24
Peak memory 191920 kb
Host smart-85425d6b-4625-4c06-bbd7-0db494d1c659
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37744154 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_bit
_bash.37744154
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.1822438447
Short name T326
Test name
Test status
Simulation time 1321522982 ps
CPU time 0.97 seconds
Started Mar 14 12:23:34 PM PDT 24
Finished Mar 14 12:23:35 PM PDT 24
Peak memory 183512 kb
Host smart-b1c83f3d-ff46-43c0-bc3d-e319ab7203f1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822438447 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_h
w_reset.1822438447
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.780566789
Short name T354
Test name
Test status
Simulation time 594504484 ps
CPU time 0.95 seconds
Started Mar 14 12:23:42 PM PDT 24
Finished Mar 14 12:23:44 PM PDT 24
Peak memory 193768 kb
Host smart-5c05bdb5-7cf4-4e65-b754-4d6c9cdc2228
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780566789 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.780566789
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.53164071
Short name T388
Test name
Test status
Simulation time 502275270 ps
CPU time 1.38 seconds
Started Mar 14 12:21:23 PM PDT 24
Finished Mar 14 12:21:25 PM PDT 24
Peak memory 184148 kb
Host smart-47cf6826-99c7-4c07-afd0-af56481ed4b0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53164071 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.53164071
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.3897529667
Short name T422
Test name
Test status
Simulation time 474313022 ps
CPU time 0.72 seconds
Started Mar 14 12:22:00 PM PDT 24
Finished Mar 14 12:22:00 PM PDT 24
Peak memory 183632 kb
Host smart-530ebaa0-0150-4004-a3bb-9280f53f41af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897529667 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.3897529667
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.1064670282
Short name T381
Test name
Test status
Simulation time 430831950 ps
CPU time 1.22 seconds
Started Mar 14 12:21:05 PM PDT 24
Finished Mar 14 12:21:06 PM PDT 24
Peak memory 183584 kb
Host smart-7af8ece4-5b65-4955-b3e9-39e2be2e9eaa
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064670282 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_t
imer_mem_partial_access.1064670282
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.2634203344
Short name T420
Test name
Test status
Simulation time 457471012 ps
CPU time 0.9 seconds
Started Mar 14 12:22:21 PM PDT 24
Finished Mar 14 12:22:22 PM PDT 24
Peak memory 183604 kb
Host smart-48ba9c5e-ac0a-46bc-b011-eb5455bc1b10
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634203344 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_w
alk.2634203344
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.2571873428
Short name T393
Test name
Test status
Simulation time 1137937184 ps
CPU time 1.36 seconds
Started Mar 14 12:21:57 PM PDT 24
Finished Mar 14 12:21:59 PM PDT 24
Peak memory 193124 kb
Host smart-992ca6cc-0a53-4f55-ae49-a0ec4c3db24d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571873428 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon
_timer_same_csr_outstanding.2571873428
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.2339324587
Short name T315
Test name
Test status
Simulation time 520224853 ps
CPU time 2.61 seconds
Started Mar 14 12:23:56 PM PDT 24
Finished Mar 14 12:23:59 PM PDT 24
Peak memory 198268 kb
Host smart-2e159244-ce07-4ebb-8e3b-b2d51d464d79
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339324587 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.2339324587
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.878623143
Short name T91
Test name
Test status
Simulation time 8171056480 ps
CPU time 7.34 seconds
Started Mar 14 12:24:06 PM PDT 24
Finished Mar 14 12:24:14 PM PDT 24
Peak memory 196564 kb
Host smart-dffad83f-5dc8-492b-b6bd-5a80a555271b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878623143 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_
intg_err.878623143
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.3418968474
Short name T69
Test name
Test status
Simulation time 13843107883 ps
CPU time 10.24 seconds
Started Mar 14 12:23:31 PM PDT 24
Finished Mar 14 12:23:42 PM PDT 24
Peak memory 190820 kb
Host smart-8f4d10e4-c88d-47b5-b236-37fa5ffbf5a5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418968474 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_b
it_bash.3418968474
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.222983405
Short name T70
Test name
Test status
Simulation time 920856575 ps
CPU time 0.7 seconds
Started Mar 14 12:19:09 PM PDT 24
Finished Mar 14 12:19:10 PM PDT 24
Peak memory 183720 kb
Host smart-ce8e5827-0337-40ac-99a6-67d3703cf260
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222983405 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_hw
_reset.222983405
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.1958420788
Short name T317
Test name
Test status
Simulation time 600777485 ps
CPU time 1.26 seconds
Started Mar 14 12:23:47 PM PDT 24
Finished Mar 14 12:23:50 PM PDT 24
Peak memory 196420 kb
Host smart-dac800c6-c245-48fa-94f6-b537fbd49d74
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958420788 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.1958420788
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.2084903205
Short name T332
Test name
Test status
Simulation time 445728010 ps
CPU time 0.67 seconds
Started Mar 14 12:23:34 PM PDT 24
Finished Mar 14 12:23:35 PM PDT 24
Peak memory 192988 kb
Host smart-4aa31290-23a8-4330-b4ef-33afef8cd8bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084903205 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.2084903205
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.450342423
Short name T363
Test name
Test status
Simulation time 504322283 ps
CPU time 1.25 seconds
Started Mar 14 12:23:47 PM PDT 24
Finished Mar 14 12:23:50 PM PDT 24
Peak memory 182284 kb
Host smart-761a628c-e8b7-4e94-83d3-2e7598da2ade
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450342423 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.450342423
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.1484835556
Short name T350
Test name
Test status
Simulation time 369224470 ps
CPU time 1.11 seconds
Started Mar 14 12:19:59 PM PDT 24
Finished Mar 14 12:20:01 PM PDT 24
Peak memory 183572 kb
Host smart-7766d19d-d643-49be-9217-7c567f08165d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484835556 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_t
imer_mem_partial_access.1484835556
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.2645861169
Short name T313
Test name
Test status
Simulation time 501777722 ps
CPU time 1.26 seconds
Started Mar 14 12:20:02 PM PDT 24
Finished Mar 14 12:20:04 PM PDT 24
Peak memory 183612 kb
Host smart-e4103c99-4a95-43ee-8924-381ceda679f7
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645861169 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_w
alk.2645861169
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.1220692325
Short name T398
Test name
Test status
Simulation time 891892073 ps
CPU time 2.23 seconds
Started Mar 14 12:23:48 PM PDT 24
Finished Mar 14 12:23:51 PM PDT 24
Peak memory 198000 kb
Host smart-bad98354-4bad-4ffd-a765-f2eb1b12cd85
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220692325 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.1220692325
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.2339361767
Short name T329
Test name
Test status
Simulation time 4548036006 ps
CPU time 2.69 seconds
Started Mar 14 12:23:33 PM PDT 24
Finished Mar 14 12:23:36 PM PDT 24
Peak memory 197452 kb
Host smart-10a0390d-45f3-40c2-a3aa-fdd2457a6525
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339361767 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl
_intg_err.2339361767
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.525610290
Short name T351
Test name
Test status
Simulation time 482577576 ps
CPU time 1.33 seconds
Started Mar 14 12:24:01 PM PDT 24
Finished Mar 14 12:24:02 PM PDT 24
Peak memory 198336 kb
Host smart-fb92e6c9-5d32-40f5-a39d-ffca9fd9a0ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525610290 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.525610290
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.1747650854
Short name T367
Test name
Test status
Simulation time 530932039 ps
CPU time 0.71 seconds
Started Mar 14 12:24:47 PM PDT 24
Finished Mar 14 12:24:47 PM PDT 24
Peak memory 183588 kb
Host smart-0b912ddc-fb18-4cfe-9185-c57df4384697
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747650854 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.1747650854
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.682423678
Short name T366
Test name
Test status
Simulation time 279101961 ps
CPU time 0.96 seconds
Started Mar 14 12:24:46 PM PDT 24
Finished Mar 14 12:24:47 PM PDT 24
Peak memory 183472 kb
Host smart-ca3505b6-fc18-4cc0-a5b8-2962f1975b3a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682423678 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.682423678
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.2907754643
Short name T77
Test name
Test status
Simulation time 2629520347 ps
CPU time 3.95 seconds
Started Mar 14 12:24:00 PM PDT 24
Finished Mar 14 12:24:04 PM PDT 24
Peak memory 194436 kb
Host smart-552e6088-5abc-4b22-8a76-47775140187e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907754643 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.ao
n_timer_same_csr_outstanding.2907754643
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.1995466052
Short name T362
Test name
Test status
Simulation time 434258620 ps
CPU time 2.72 seconds
Started Mar 14 12:24:57 PM PDT 24
Finished Mar 14 12:25:01 PM PDT 24
Peak memory 198076 kb
Host smart-22071e6e-8a02-4f74-8c02-eeba7a0539a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995466052 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.1995466052
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.3698087128
Short name T401
Test name
Test status
Simulation time 4605839121 ps
CPU time 1.49 seconds
Started Mar 14 12:24:47 PM PDT 24
Finished Mar 14 12:24:49 PM PDT 24
Peak memory 197236 kb
Host smart-20e8d434-58fc-4bf1-bbd6-e4f04850d9b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698087128 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_t
l_intg_err.3698087128
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.4266770917
Short name T364
Test name
Test status
Simulation time 390605833 ps
CPU time 0.96 seconds
Started Mar 14 12:24:02 PM PDT 24
Finished Mar 14 12:24:03 PM PDT 24
Peak memory 195664 kb
Host smart-a9e8e0d8-67af-4f0c-a2b6-5481e96a9fbb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266770917 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.4266770917
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.4202793759
Short name T29
Test name
Test status
Simulation time 445783875 ps
CPU time 1.26 seconds
Started Mar 14 12:24:02 PM PDT 24
Finished Mar 14 12:24:03 PM PDT 24
Peak memory 183764 kb
Host smart-8b07418f-d7d0-448e-98a0-af4430f2f109
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202793759 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.4202793759
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.436487819
Short name T382
Test name
Test status
Simulation time 408697062 ps
CPU time 0.75 seconds
Started Mar 14 12:24:01 PM PDT 24
Finished Mar 14 12:24:02 PM PDT 24
Peak memory 183536 kb
Host smart-ec7235f7-5583-413a-b801-a67780da63ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436487819 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.436487819
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.2654432595
Short name T408
Test name
Test status
Simulation time 2414591624 ps
CPU time 7.28 seconds
Started Mar 14 12:23:49 PM PDT 24
Finished Mar 14 12:23:57 PM PDT 24
Peak memory 183828 kb
Host smart-a284b23a-1aec-4d12-a70b-95054dd8195f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654432595 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.ao
n_timer_same_csr_outstanding.2654432595
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.1841393346
Short name T352
Test name
Test status
Simulation time 811247447 ps
CPU time 1.93 seconds
Started Mar 14 12:24:01 PM PDT 24
Finished Mar 14 12:24:03 PM PDT 24
Peak memory 198332 kb
Host smart-1ed6817d-549d-4fb4-aca5-25fdda945b6e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841393346 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.1841393346
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.2403876764
Short name T93
Test name
Test status
Simulation time 4530470241 ps
CPU time 8.05 seconds
Started Mar 14 12:24:02 PM PDT 24
Finished Mar 14 12:24:10 PM PDT 24
Peak memory 196276 kb
Host smart-70782ef0-7b36-4c97-8e39-433b902ff128
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403876764 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_t
l_intg_err.2403876764
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.1328659963
Short name T318
Test name
Test status
Simulation time 456572074 ps
CPU time 1.34 seconds
Started Mar 14 12:24:04 PM PDT 24
Finished Mar 14 12:24:06 PM PDT 24
Peak memory 194820 kb
Host smart-79905180-eaff-48a0-91bf-f4dc69bb8f75
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328659963 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.1328659963
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.2191526935
Short name T58
Test name
Test status
Simulation time 484400619 ps
CPU time 0.63 seconds
Started Mar 14 12:24:00 PM PDT 24
Finished Mar 14 12:24:01 PM PDT 24
Peak memory 183804 kb
Host smart-5eef82fe-2ce8-4164-aad1-5b1ee09e5e4a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191526935 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.2191526935
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.224324341
Short name T308
Test name
Test status
Simulation time 396637537 ps
CPU time 1.14 seconds
Started Mar 14 12:24:18 PM PDT 24
Finished Mar 14 12:24:19 PM PDT 24
Peak memory 183632 kb
Host smart-6d4d02e1-5ac3-4c1b-ab9b-ad71ccc80294
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224324341 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.224324341
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.3562074081
Short name T371
Test name
Test status
Simulation time 984294756 ps
CPU time 3.25 seconds
Started Mar 14 12:24:20 PM PDT 24
Finished Mar 14 12:24:23 PM PDT 24
Peak memory 183668 kb
Host smart-0907e1db-1b12-4e40-8039-8a097688e49e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562074081 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.ao
n_timer_same_csr_outstanding.3562074081
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.1487204217
Short name T292
Test name
Test status
Simulation time 679998665 ps
CPU time 2.47 seconds
Started Mar 14 12:24:02 PM PDT 24
Finished Mar 14 12:24:05 PM PDT 24
Peak memory 198320 kb
Host smart-e7e1d31f-193c-4f4c-bc55-83046beac272
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487204217 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.1487204217
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.3132023248
Short name T377
Test name
Test status
Simulation time 529856550 ps
CPU time 0.96 seconds
Started Mar 14 12:24:22 PM PDT 24
Finished Mar 14 12:24:23 PM PDT 24
Peak memory 196868 kb
Host smart-6e0a82d2-efe8-4296-9ac9-98e69c2c6c52
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132023248 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.3132023248
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.1817708584
Short name T72
Test name
Test status
Simulation time 442150765 ps
CPU time 1.25 seconds
Started Mar 14 12:24:18 PM PDT 24
Finished Mar 14 12:24:20 PM PDT 24
Peak memory 183848 kb
Host smart-a5c66963-e214-4f63-be68-5ede4eccccda
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817708584 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.1817708584
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.4264644217
Short name T368
Test name
Test status
Simulation time 299175688 ps
CPU time 0.7 seconds
Started Mar 14 12:23:59 PM PDT 24
Finished Mar 14 12:23:59 PM PDT 24
Peak memory 183628 kb
Host smart-71c07bea-b79f-4f98-bfd9-b70e51ac6d17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264644217 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.4264644217
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.3159762829
Short name T345
Test name
Test status
Simulation time 1223186625 ps
CPU time 1.26 seconds
Started Mar 14 12:24:18 PM PDT 24
Finished Mar 14 12:24:19 PM PDT 24
Peak memory 193028 kb
Host smart-e03237ea-093a-45e5-b118-c723234418f9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159762829 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.ao
n_timer_same_csr_outstanding.3159762829
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.4109028519
Short name T322
Test name
Test status
Simulation time 446023050 ps
CPU time 0.94 seconds
Started Mar 14 12:24:00 PM PDT 24
Finished Mar 14 12:24:01 PM PDT 24
Peak memory 197548 kb
Host smart-0db05062-4772-4bf9-acb6-185d88be775d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109028519 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.4109028519
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.430050442
Short name T94
Test name
Test status
Simulation time 8225565055 ps
CPU time 7.61 seconds
Started Mar 14 12:24:00 PM PDT 24
Finished Mar 14 12:24:08 PM PDT 24
Peak memory 197740 kb
Host smart-c86e3235-ad12-4d8e-89bb-d00d05e1c794
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430050442 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl
_intg_err.430050442
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.2015612519
Short name T359
Test name
Test status
Simulation time 333734563 ps
CPU time 0.91 seconds
Started Mar 14 12:24:25 PM PDT 24
Finished Mar 14 12:24:26 PM PDT 24
Peak memory 194820 kb
Host smart-7add4ffd-a743-48e7-907b-8a5ad2073e5c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015612519 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.2015612519
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.17714281
Short name T61
Test name
Test status
Simulation time 340488589 ps
CPU time 0.65 seconds
Started Mar 14 12:24:24 PM PDT 24
Finished Mar 14 12:24:25 PM PDT 24
Peak memory 183736 kb
Host smart-291d165a-cfde-4e0f-aa84-1ae6acdcd7d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17714281 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.17714281
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.2925818589
Short name T348
Test name
Test status
Simulation time 537959210 ps
CPU time 0.74 seconds
Started Mar 14 12:24:25 PM PDT 24
Finished Mar 14 12:24:25 PM PDT 24
Peak memory 183460 kb
Host smart-b9eb7725-75cd-4565-bf8c-aee60fd7dcad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925818589 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.2925818589
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.660427416
Short name T395
Test name
Test status
Simulation time 3003078431 ps
CPU time 2.36 seconds
Started Mar 14 12:24:23 PM PDT 24
Finished Mar 14 12:24:25 PM PDT 24
Peak memory 192040 kb
Host smart-423a8c1c-e63b-4143-a5c8-2c642dc5ff8a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660427416 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon
_timer_same_csr_outstanding.660427416
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.1616495387
Short name T294
Test name
Test status
Simulation time 569860356 ps
CPU time 1.56 seconds
Started Mar 14 12:24:25 PM PDT 24
Finished Mar 14 12:24:27 PM PDT 24
Peak memory 198288 kb
Host smart-893cc65d-4e26-41a4-8136-9c7ece973e9f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616495387 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.1616495387
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.2143541616
Short name T389
Test name
Test status
Simulation time 8491266524 ps
CPU time 13.04 seconds
Started Mar 14 12:24:19 PM PDT 24
Finished Mar 14 12:24:32 PM PDT 24
Peak memory 197868 kb
Host smart-1e7e0846-5d01-4939-9f76-3250299c2489
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143541616 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_t
l_intg_err.2143541616
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.1581549322
Short name T320
Test name
Test status
Simulation time 479426902 ps
CPU time 1.15 seconds
Started Mar 14 12:24:46 PM PDT 24
Finished Mar 14 12:24:48 PM PDT 24
Peak memory 198272 kb
Host smart-99d92f7d-1ecf-459e-b91f-604d3c84b52d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581549322 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.1581549322
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.1295749028
Short name T417
Test name
Test status
Simulation time 542987343 ps
CPU time 0.79 seconds
Started Mar 14 12:24:19 PM PDT 24
Finished Mar 14 12:24:20 PM PDT 24
Peak memory 192992 kb
Host smart-0d8d713e-b466-4318-a3ff-a25c522af539
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295749028 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.1295749028
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.3623745242
Short name T397
Test name
Test status
Simulation time 338714233 ps
CPU time 0.72 seconds
Started Mar 14 12:24:25 PM PDT 24
Finished Mar 14 12:24:26 PM PDT 24
Peak memory 183456 kb
Host smart-aabd0bca-b6fc-45f7-823f-df4c416f874b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623745242 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.3623745242
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.2984358780
Short name T353
Test name
Test status
Simulation time 1351160392 ps
CPU time 1.82 seconds
Started Mar 14 12:24:26 PM PDT 24
Finished Mar 14 12:24:28 PM PDT 24
Peak memory 183364 kb
Host smart-89afa855-0f65-46c3-8a82-db8c3b47ce03
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984358780 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.ao
n_timer_same_csr_outstanding.2984358780
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.3568422553
Short name T392
Test name
Test status
Simulation time 506967784 ps
CPU time 2.49 seconds
Started Mar 14 12:24:25 PM PDT 24
Finished Mar 14 12:24:27 PM PDT 24
Peak memory 198376 kb
Host smart-565ca1a5-b5f6-4bd4-a24a-0482466a7d45
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568422553 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.3568422553
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.1381830031
Short name T355
Test name
Test status
Simulation time 7616117313 ps
CPU time 13 seconds
Started Mar 14 12:24:25 PM PDT 24
Finished Mar 14 12:24:39 PM PDT 24
Peak memory 197776 kb
Host smart-fe30b71d-6b32-4b49-b09d-a316e4a3a9b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381830031 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_t
l_intg_err.1381830031
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.3042192252
Short name T335
Test name
Test status
Simulation time 546635124 ps
CPU time 0.92 seconds
Started Mar 14 12:24:26 PM PDT 24
Finished Mar 14 12:24:27 PM PDT 24
Peak memory 196332 kb
Host smart-47264aea-2176-41ca-8f22-5cc49d81904e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042192252 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.3042192252
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.591113068
Short name T314
Test name
Test status
Simulation time 398009665 ps
CPU time 0.98 seconds
Started Mar 14 12:24:31 PM PDT 24
Finished Mar 14 12:24:32 PM PDT 24
Peak memory 192860 kb
Host smart-44a964a4-e922-4a68-ad79-ca030e5cfe6f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591113068 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.591113068
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.3487961490
Short name T349
Test name
Test status
Simulation time 410278703 ps
CPU time 0.68 seconds
Started Mar 14 12:24:26 PM PDT 24
Finished Mar 14 12:24:27 PM PDT 24
Peak memory 183476 kb
Host smart-90c03277-4f18-4e3f-909b-1eca223d701e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487961490 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.3487961490
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.853438119
Short name T79
Test name
Test status
Simulation time 1259173937 ps
CPU time 4.71 seconds
Started Mar 14 12:24:25 PM PDT 24
Finished Mar 14 12:24:30 PM PDT 24
Peak memory 193120 kb
Host smart-b612d9b4-508c-4c03-ad73-edd7462ee59a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853438119 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon
_timer_same_csr_outstanding.853438119
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.1297590775
Short name T407
Test name
Test status
Simulation time 514710108 ps
CPU time 2.13 seconds
Started Mar 14 12:24:25 PM PDT 24
Finished Mar 14 12:24:27 PM PDT 24
Peak memory 198292 kb
Host smart-45f8fda0-a144-4e3d-82de-3c0d29695d6e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297590775 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.1297590775
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.3499239306
Short name T346
Test name
Test status
Simulation time 4115538740 ps
CPU time 2.55 seconds
Started Mar 14 12:24:25 PM PDT 24
Finished Mar 14 12:24:28 PM PDT 24
Peak memory 197336 kb
Host smart-cbfe7af3-1e75-49c6-80bd-b3ce26a4fd82
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499239306 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_t
l_intg_err.3499239306
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.1313051264
Short name T383
Test name
Test status
Simulation time 741158338 ps
CPU time 1.53 seconds
Started Mar 14 12:24:19 PM PDT 24
Finished Mar 14 12:24:21 PM PDT 24
Peak memory 198448 kb
Host smart-01599e3d-2150-4dc7-83a5-189ae7b62278
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313051264 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.1313051264
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.3236839434
Short name T65
Test name
Test status
Simulation time 488651671 ps
CPU time 0.95 seconds
Started Mar 14 12:24:23 PM PDT 24
Finished Mar 14 12:24:24 PM PDT 24
Peak memory 183672 kb
Host smart-16410418-3e7a-4a9b-997b-ff024012e11e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236839434 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.3236839434
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.1606337776
Short name T413
Test name
Test status
Simulation time 304209063 ps
CPU time 1.08 seconds
Started Mar 14 12:24:25 PM PDT 24
Finished Mar 14 12:24:27 PM PDT 24
Peak memory 183536 kb
Host smart-06fc0a1c-d324-4459-86a0-8be8fe7c03ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606337776 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.1606337776
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.3255922835
Short name T78
Test name
Test status
Simulation time 2300253565 ps
CPU time 2.22 seconds
Started Mar 14 12:24:24 PM PDT 24
Finished Mar 14 12:24:27 PM PDT 24
Peak memory 191932 kb
Host smart-0bc3e99a-bc0d-4eba-a469-1563f6cce4e7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255922835 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.ao
n_timer_same_csr_outstanding.3255922835
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.3706121211
Short name T376
Test name
Test status
Simulation time 491021059 ps
CPU time 1.85 seconds
Started Mar 14 12:24:25 PM PDT 24
Finished Mar 14 12:24:27 PM PDT 24
Peak memory 198236 kb
Host smart-d5690e78-e196-4702-b9d7-b7f5d42b7b88
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706121211 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.3706121211
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.241977674
Short name T34
Test name
Test status
Simulation time 4611798217 ps
CPU time 1.58 seconds
Started Mar 14 12:24:31 PM PDT 24
Finished Mar 14 12:24:32 PM PDT 24
Peak memory 196352 kb
Host smart-cf85f1b6-a492-4c4d-989a-66a9b9b26aa9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241977674 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl
_intg_err.241977674
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.1645060297
Short name T328
Test name
Test status
Simulation time 529605008 ps
CPU time 1.09 seconds
Started Mar 14 12:24:31 PM PDT 24
Finished Mar 14 12:24:32 PM PDT 24
Peak memory 198156 kb
Host smart-02b9d993-1cda-40fe-bb73-f03073a023b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645060297 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.1645060297
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.322343084
Short name T76
Test name
Test status
Simulation time 419266479 ps
CPU time 1.23 seconds
Started Mar 14 12:24:25 PM PDT 24
Finished Mar 14 12:24:27 PM PDT 24
Peak memory 183728 kb
Host smart-f1aff8f7-86f7-467e-b5ce-d8647eacd3ed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322343084 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.322343084
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.1090480730
Short name T414
Test name
Test status
Simulation time 457504266 ps
CPU time 0.74 seconds
Started Mar 14 12:24:25 PM PDT 24
Finished Mar 14 12:24:26 PM PDT 24
Peak memory 183420 kb
Host smart-52ca8541-c845-4972-ad64-3da012128723
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090480730 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.1090480730
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.580175788
Short name T391
Test name
Test status
Simulation time 2205361326 ps
CPU time 2.14 seconds
Started Mar 14 12:24:23 PM PDT 24
Finished Mar 14 12:24:25 PM PDT 24
Peak memory 193876 kb
Host smart-159baed8-4302-4386-a51f-a7fd82d76f70
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580175788 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon
_timer_same_csr_outstanding.580175788
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.3852917208
Short name T309
Test name
Test status
Simulation time 365918280 ps
CPU time 2.33 seconds
Started Mar 14 12:24:23 PM PDT 24
Finished Mar 14 12:24:25 PM PDT 24
Peak memory 198312 kb
Host smart-baec3a28-1827-4ae9-b3d6-4c6da0c7cdf8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852917208 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.3852917208
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.811477333
Short name T92
Test name
Test status
Simulation time 4207929237 ps
CPU time 3.75 seconds
Started Mar 14 12:24:26 PM PDT 24
Finished Mar 14 12:24:30 PM PDT 24
Peak memory 197324 kb
Host smart-d2aff453-4a7c-48b2-b11a-0c8caa0c6a9b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811477333 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl
_intg_err.811477333
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.2631750862
Short name T339
Test name
Test status
Simulation time 507962495 ps
CPU time 1.38 seconds
Started Mar 14 12:24:30 PM PDT 24
Finished Mar 14 12:24:32 PM PDT 24
Peak memory 195512 kb
Host smart-08bf7c60-65c5-456d-a3ae-f3988836cedf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631750862 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.2631750862
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.1453741281
Short name T75
Test name
Test status
Simulation time 320690364 ps
CPU time 1.1 seconds
Started Mar 14 12:24:25 PM PDT 24
Finished Mar 14 12:24:26 PM PDT 24
Peak memory 183696 kb
Host smart-1588971d-fd27-4068-93a0-33af72b8d2af
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453741281 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.1453741281
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.2455388957
Short name T378
Test name
Test status
Simulation time 486544892 ps
CPU time 1.26 seconds
Started Mar 14 12:24:26 PM PDT 24
Finished Mar 14 12:24:28 PM PDT 24
Peak memory 183476 kb
Host smart-b7a93727-94ef-4f56-9cb8-929a2c46c430
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455388957 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.2455388957
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.576860022
Short name T347
Test name
Test status
Simulation time 2589010831 ps
CPU time 2.52 seconds
Started Mar 14 12:24:30 PM PDT 24
Finished Mar 14 12:24:33 PM PDT 24
Peak memory 194224 kb
Host smart-c16d1bd1-c1a7-47ed-bc6b-944ab120174b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576860022 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon
_timer_same_csr_outstanding.576860022
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.1499100245
Short name T303
Test name
Test status
Simulation time 889372040 ps
CPU time 2.2 seconds
Started Mar 14 12:24:26 PM PDT 24
Finished Mar 14 12:24:29 PM PDT 24
Peak memory 198140 kb
Host smart-1b2b2842-33af-410e-8735-ed8d397ac54f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499100245 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.1499100245
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.3772872867
Short name T400
Test name
Test status
Simulation time 8667633107 ps
CPU time 2.81 seconds
Started Mar 14 12:24:31 PM PDT 24
Finished Mar 14 12:24:34 PM PDT 24
Peak memory 197732 kb
Host smart-916d44d4-343a-44e9-bd4e-7f864ecde91c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772872867 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_t
l_intg_err.3772872867
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.2675541883
Short name T59
Test name
Test status
Simulation time 515128433 ps
CPU time 1.36 seconds
Started Mar 14 12:24:31 PM PDT 24
Finished Mar 14 12:24:32 PM PDT 24
Peak memory 182880 kb
Host smart-7ed0388d-e452-43c0-a125-8cba14ba507d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675541883 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_a
liasing.2675541883
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.435236866
Short name T31
Test name
Test status
Simulation time 14141552765 ps
CPU time 21.45 seconds
Started Mar 14 12:19:08 PM PDT 24
Finished Mar 14 12:19:30 PM PDT 24
Peak memory 191928 kb
Host smart-8ff0e8f3-11f5-42d5-9bd8-d54d275a8408
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435236866 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_bi
t_bash.435236866
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.3429638191
Short name T62
Test name
Test status
Simulation time 1221141817 ps
CPU time 1.09 seconds
Started Mar 14 12:19:08 PM PDT 24
Finished Mar 14 12:19:09 PM PDT 24
Peak memory 183592 kb
Host smart-0c9b20e3-fbaf-4f76-96a6-dc0d2fa2812d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429638191 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_h
w_reset.3429638191
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.20482398
Short name T406
Test name
Test status
Simulation time 537791209 ps
CPU time 0.9 seconds
Started Mar 14 12:23:29 PM PDT 24
Finished Mar 14 12:23:30 PM PDT 24
Peak memory 195512 kb
Host smart-e5d8a7de-3931-4354-a9ec-2861770c2a8b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20482398 -assert nopostproc +UVM_TESTNAME=a
on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.20482398
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.3848504009
Short name T67
Test name
Test status
Simulation time 458798788 ps
CPU time 1.28 seconds
Started Mar 14 12:19:34 PM PDT 24
Finished Mar 14 12:19:36 PM PDT 24
Peak memory 183840 kb
Host smart-8decadde-ea1b-4e9c-9ca8-6f68c50d5db3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848504009 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.3848504009
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.3097525783
Short name T372
Test name
Test status
Simulation time 485927587 ps
CPU time 1.41 seconds
Started Mar 14 12:21:06 PM PDT 24
Finished Mar 14 12:21:07 PM PDT 24
Peak memory 183636 kb
Host smart-bd3c0c95-e009-448a-bbec-0ae12d62ae15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097525783 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.3097525783
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.18764785
Short name T380
Test name
Test status
Simulation time 294923030 ps
CPU time 0.74 seconds
Started Mar 14 12:23:32 PM PDT 24
Finished Mar 14 12:23:33 PM PDT 24
Peak memory 183256 kb
Host smart-bf5c838e-f283-4c6c-8a92-618af4ce4dfb
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18764785 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_
timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_tim
er_mem_partial_access.18764785
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.4149925045
Short name T412
Test name
Test status
Simulation time 288368424 ps
CPU time 0.67 seconds
Started Mar 14 12:24:17 PM PDT 24
Finished Mar 14 12:24:18 PM PDT 24
Peak memory 182828 kb
Host smart-a02c80b0-c1e2-4feb-9ee3-e7d12b2ab29d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149925045 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_w
alk.4149925045
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.4091339285
Short name T81
Test name
Test status
Simulation time 1341381060 ps
CPU time 0.78 seconds
Started Mar 14 12:24:28 PM PDT 24
Finished Mar 14 12:24:29 PM PDT 24
Peak memory 193108 kb
Host smart-3222fd79-eb2f-4186-9991-832dd0960327
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091339285 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon
_timer_same_csr_outstanding.4091339285
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.2328138812
Short name T334
Test name
Test status
Simulation time 433991031 ps
CPU time 2.89 seconds
Started Mar 14 12:20:01 PM PDT 24
Finished Mar 14 12:20:04 PM PDT 24
Peak memory 198328 kb
Host smart-454e0684-aab2-4813-9bed-f5582d9d0932
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328138812 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.2328138812
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.3042777708
Short name T330
Test name
Test status
Simulation time 4190356605 ps
CPU time 6.39 seconds
Started Mar 14 12:23:32 PM PDT 24
Finished Mar 14 12:23:38 PM PDT 24
Peak memory 197036 kb
Host smart-df9907e8-57f7-4389-9c88-184f41e526f1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042777708 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl
_intg_err.3042777708
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.1227022470
Short name T344
Test name
Test status
Simulation time 311529383 ps
CPU time 0.66 seconds
Started Mar 14 12:24:25 PM PDT 24
Finished Mar 14 12:24:26 PM PDT 24
Peak memory 183460 kb
Host smart-6b5c8650-c0c7-4c2d-9acb-2d23fb65cfc5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227022470 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.1227022470
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.4153464985
Short name T343
Test name
Test status
Simulation time 385972546 ps
CPU time 1.12 seconds
Started Mar 14 12:24:22 PM PDT 24
Finished Mar 14 12:24:23 PM PDT 24
Peak memory 183480 kb
Host smart-393a7ec4-3947-4763-be2f-c6109343226c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153464985 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.4153464985
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.3517021218
Short name T312
Test name
Test status
Simulation time 533211186 ps
CPU time 0.6 seconds
Started Mar 14 12:24:24 PM PDT 24
Finished Mar 14 12:24:25 PM PDT 24
Peak memory 183532 kb
Host smart-c9a5d228-7ce4-40bd-84bc-9e1797215b3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517021218 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.3517021218
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.3414107456
Short name T390
Test name
Test status
Simulation time 427453296 ps
CPU time 0.72 seconds
Started Mar 14 12:24:30 PM PDT 24
Finished Mar 14 12:24:31 PM PDT 24
Peak memory 183472 kb
Host smart-7ccf31d4-1e78-4d14-acce-c8bf9da67a35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414107456 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.3414107456
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.529505210
Short name T325
Test name
Test status
Simulation time 498667157 ps
CPU time 1.29 seconds
Started Mar 14 12:24:22 PM PDT 24
Finished Mar 14 12:24:24 PM PDT 24
Peak memory 183456 kb
Host smart-e8327f8d-99aa-446f-a158-a1cb70d203be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529505210 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.529505210
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.374054675
Short name T296
Test name
Test status
Simulation time 530715419 ps
CPU time 0.71 seconds
Started Mar 14 12:24:45 PM PDT 24
Finished Mar 14 12:24:51 PM PDT 24
Peak memory 183644 kb
Host smart-9bc6a9ef-8580-4b96-ad7f-04e9040f0d9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374054675 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.374054675
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.1117814841
Short name T385
Test name
Test status
Simulation time 364135822 ps
CPU time 1.05 seconds
Started Mar 14 12:24:44 PM PDT 24
Finished Mar 14 12:24:45 PM PDT 24
Peak memory 183528 kb
Host smart-60fd3474-7cc3-4159-aa7c-4758a8dc5a02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117814841 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.1117814841
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.99747209
Short name T340
Test name
Test status
Simulation time 441512811 ps
CPU time 1.24 seconds
Started Mar 14 12:24:45 PM PDT 24
Finished Mar 14 12:24:47 PM PDT 24
Peak memory 183508 kb
Host smart-4bd1da02-ef8d-4273-afcd-60ad73c9e348
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99747209 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.99747209
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.3079339722
Short name T379
Test name
Test status
Simulation time 391164370 ps
CPU time 0.86 seconds
Started Mar 14 12:24:35 PM PDT 24
Finished Mar 14 12:24:36 PM PDT 24
Peak memory 183624 kb
Host smart-62a0c5ea-bc98-4305-8251-59122fb34f75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079339722 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.3079339722
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.1415783839
Short name T386
Test name
Test status
Simulation time 348900827 ps
CPU time 0.99 seconds
Started Mar 14 12:24:40 PM PDT 24
Finished Mar 14 12:24:42 PM PDT 24
Peak memory 183536 kb
Host smart-f1f83ca0-d3b4-4d13-93d4-cb8807852be6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415783839 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.1415783839
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.1614249781
Short name T327
Test name
Test status
Simulation time 511993669 ps
CPU time 1.2 seconds
Started Mar 14 12:23:22 PM PDT 24
Finished Mar 14 12:23:24 PM PDT 24
Peak memory 191844 kb
Host smart-6fa1c8e6-7b51-4c2c-a145-7f5041ab5a6b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614249781 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_a
liasing.1614249781
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.3878512817
Short name T63
Test name
Test status
Simulation time 4406102291 ps
CPU time 3.99 seconds
Started Mar 14 12:24:48 PM PDT 24
Finished Mar 14 12:24:52 PM PDT 24
Peak memory 195132 kb
Host smart-59605c56-4afb-4f5d-9693-79e65a13a493
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878512817 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_b
it_bash.3878512817
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.2606982289
Short name T68
Test name
Test status
Simulation time 647974646 ps
CPU time 1.05 seconds
Started Mar 14 12:23:24 PM PDT 24
Finished Mar 14 12:23:25 PM PDT 24
Peak memory 183720 kb
Host smart-26884650-111c-4ded-84d7-78500f45a6f3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606982289 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_h
w_reset.2606982289
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.2950678762
Short name T295
Test name
Test status
Simulation time 825554075 ps
CPU time 0.78 seconds
Started Mar 14 12:23:27 PM PDT 24
Finished Mar 14 12:23:28 PM PDT 24
Peak memory 196732 kb
Host smart-5596636d-ef5d-4f5a-9b32-54fdc85436fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950678762 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.2950678762
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.2548509403
Short name T96
Test name
Test status
Simulation time 504507770 ps
CPU time 0.83 seconds
Started Mar 14 12:23:29 PM PDT 24
Finished Mar 14 12:23:29 PM PDT 24
Peak memory 183704 kb
Host smart-3678dea2-2efb-4049-a3c8-bd0eeb9659a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548509403 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.2548509403
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.215822746
Short name T323
Test name
Test status
Simulation time 324699169 ps
CPU time 0.98 seconds
Started Mar 14 12:23:25 PM PDT 24
Finished Mar 14 12:23:26 PM PDT 24
Peak memory 183544 kb
Host smart-eb6d1b3c-bad3-40d9-8df4-8241a34d8eb5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215822746 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.215822746
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.1107750327
Short name T410
Test name
Test status
Simulation time 332337715 ps
CPU time 0.67 seconds
Started Mar 14 12:23:25 PM PDT 24
Finished Mar 14 12:23:26 PM PDT 24
Peak memory 183500 kb
Host smart-aaf4d9b8-8612-4580-8e17-510348a8a613
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107750327 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_t
imer_mem_partial_access.1107750327
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.1910129833
Short name T291
Test name
Test status
Simulation time 511230618 ps
CPU time 0.62 seconds
Started Mar 14 12:23:26 PM PDT 24
Finished Mar 14 12:23:27 PM PDT 24
Peak memory 183620 kb
Host smart-db3dfed2-9515-4885-a81a-51cf94b791c0
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910129833 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_w
alk.1910129833
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.368379253
Short name T419
Test name
Test status
Simulation time 2538123755 ps
CPU time 1.76 seconds
Started Mar 14 12:23:27 PM PDT 24
Finished Mar 14 12:23:28 PM PDT 24
Peak memory 183824 kb
Host smart-b057d381-9d0d-497a-a4b5-e26243e13c1b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368379253 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_
timer_same_csr_outstanding.368379253
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.860748251
Short name T297
Test name
Test status
Simulation time 911917453 ps
CPU time 2.02 seconds
Started Mar 14 12:23:24 PM PDT 24
Finished Mar 14 12:23:27 PM PDT 24
Peak memory 198484 kb
Host smart-e42351ff-6994-492b-a683-d7e57442d1bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860748251 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.860748251
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.3318927964
Short name T405
Test name
Test status
Simulation time 4457788849 ps
CPU time 4.06 seconds
Started Mar 14 12:23:24 PM PDT 24
Finished Mar 14 12:23:29 PM PDT 24
Peak memory 197568 kb
Host smart-aeaf43b9-88bc-4fa5-a291-04872579ec08
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318927964 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl
_intg_err.3318927964
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.2207048925
Short name T290
Test name
Test status
Simulation time 354266577 ps
CPU time 0.85 seconds
Started Mar 14 12:24:51 PM PDT 24
Finished Mar 14 12:24:52 PM PDT 24
Peak memory 183456 kb
Host smart-a3fb0ecb-2133-4d30-8848-be1d3e44e23e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207048925 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.2207048925
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.1795108536
Short name T375
Test name
Test status
Simulation time 457839721 ps
CPU time 0.57 seconds
Started Mar 14 12:24:39 PM PDT 24
Finished Mar 14 12:24:40 PM PDT 24
Peak memory 183632 kb
Host smart-33ec72ff-0840-4a0b-8498-067e1c632290
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795108536 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.1795108536
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.259965022
Short name T369
Test name
Test status
Simulation time 407615952 ps
CPU time 0.63 seconds
Started Mar 14 12:24:36 PM PDT 24
Finished Mar 14 12:24:37 PM PDT 24
Peak memory 183536 kb
Host smart-9cab85f4-86e3-4a45-ad20-e25bcdd4705c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259965022 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.259965022
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.1146756601
Short name T301
Test name
Test status
Simulation time 424143369 ps
CPU time 1.11 seconds
Started Mar 14 12:24:49 PM PDT 24
Finished Mar 14 12:24:51 PM PDT 24
Peak memory 183512 kb
Host smart-67fcb3e4-3c7c-4616-a362-9573ca642e4c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146756601 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.1146756601
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.4033563491
Short name T333
Test name
Test status
Simulation time 396165115 ps
CPU time 0.62 seconds
Started Mar 14 12:24:30 PM PDT 24
Finished Mar 14 12:24:31 PM PDT 24
Peak memory 183532 kb
Host smart-17fb0b48-63d3-47b0-ac42-5e41565c93d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033563491 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.4033563491
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.1193859827
Short name T418
Test name
Test status
Simulation time 580999727 ps
CPU time 0.57 seconds
Started Mar 14 12:24:51 PM PDT 24
Finished Mar 14 12:24:52 PM PDT 24
Peak memory 182964 kb
Host smart-72159be1-9b66-4ec6-ae5b-73f212440ab9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193859827 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.1193859827
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.548837195
Short name T370
Test name
Test status
Simulation time 507761748 ps
CPU time 0.8 seconds
Started Mar 14 12:24:46 PM PDT 24
Finished Mar 14 12:24:47 PM PDT 24
Peak memory 183492 kb
Host smart-9c2e4fe8-60db-4aef-82ee-e90b141f38e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548837195 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.548837195
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.412799536
Short name T300
Test name
Test status
Simulation time 495646709 ps
CPU time 1.34 seconds
Started Mar 14 12:24:46 PM PDT 24
Finished Mar 14 12:24:48 PM PDT 24
Peak memory 183476 kb
Host smart-1eabc0ac-1640-46a8-b725-ddab857d11ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412799536 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.412799536
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.243656275
Short name T324
Test name
Test status
Simulation time 322421670 ps
CPU time 0.95 seconds
Started Mar 14 12:24:51 PM PDT 24
Finished Mar 14 12:24:52 PM PDT 24
Peak memory 182832 kb
Host smart-5f5d9df1-7659-418e-a6fe-670a191cceeb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243656275 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.243656275
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.1993631863
Short name T299
Test name
Test status
Simulation time 527872377 ps
CPU time 0.73 seconds
Started Mar 14 12:24:41 PM PDT 24
Finished Mar 14 12:24:42 PM PDT 24
Peak memory 183456 kb
Host smart-7c57d067-73ab-4ed8-bb99-4aa67ad6067d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993631863 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.1993631863
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.1404658954
Short name T316
Test name
Test status
Simulation time 588031513 ps
CPU time 1.47 seconds
Started Mar 14 12:24:48 PM PDT 24
Finished Mar 14 12:24:49 PM PDT 24
Peak memory 183520 kb
Host smart-5cdbbc6c-6b8c-4ad5-93b7-48ada2abc3e0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404658954 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_a
liasing.1404658954
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.343664248
Short name T64
Test name
Test status
Simulation time 6926672522 ps
CPU time 10.15 seconds
Started Mar 14 12:24:49 PM PDT 24
Finished Mar 14 12:25:00 PM PDT 24
Peak memory 191916 kb
Host smart-e453481a-8abd-4832-93ff-086ae8671f50
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343664248 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_bi
t_bash.343664248
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.2505376508
Short name T394
Test name
Test status
Simulation time 927265776 ps
CPU time 1.42 seconds
Started Mar 14 12:24:31 PM PDT 24
Finished Mar 14 12:24:32 PM PDT 24
Peak memory 183304 kb
Host smart-5e92670b-43ff-4d2f-9a0e-de9998afa88b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505376508 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_h
w_reset.2505376508
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.1098456336
Short name T342
Test name
Test status
Simulation time 340026362 ps
CPU time 0.85 seconds
Started Mar 14 12:23:29 PM PDT 24
Finished Mar 14 12:23:30 PM PDT 24
Peak memory 195776 kb
Host smart-38743d6c-fca5-4385-902c-f6966a1786ff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098456336 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.1098456336
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.4268823975
Short name T66
Test name
Test status
Simulation time 394928773 ps
CPU time 1.13 seconds
Started Mar 14 12:24:31 PM PDT 24
Finished Mar 14 12:24:32 PM PDT 24
Peak memory 183244 kb
Host smart-3dcb26e4-632f-44fc-b602-e422d40ac6be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268823975 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.4268823975
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.1481922006
Short name T311
Test name
Test status
Simulation time 426654595 ps
CPU time 0.63 seconds
Started Mar 14 12:23:39 PM PDT 24
Finished Mar 14 12:23:40 PM PDT 24
Peak memory 183584 kb
Host smart-49304dd2-6413-4d1f-8c98-6287b2c9895f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481922006 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.1481922006
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.3070624593
Short name T288
Test name
Test status
Simulation time 348000342 ps
CPU time 0.61 seconds
Started Mar 14 12:24:47 PM PDT 24
Finished Mar 14 12:24:48 PM PDT 24
Peak memory 183404 kb
Host smart-740e9c93-be7e-401c-b01b-9404213aebde
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070624593 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_t
imer_mem_partial_access.3070624593
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.484074951
Short name T293
Test name
Test status
Simulation time 387952027 ps
CPU time 1.08 seconds
Started Mar 14 12:24:48 PM PDT 24
Finished Mar 14 12:24:49 PM PDT 24
Peak memory 183444 kb
Host smart-41840610-2ed4-4148-88e1-35aef557e6b6
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484074951 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_wa
lk.484074951
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.404177488
Short name T80
Test name
Test status
Simulation time 2084166619 ps
CPU time 1.38 seconds
Started Mar 14 12:24:29 PM PDT 24
Finished Mar 14 12:24:30 PM PDT 24
Peak memory 183736 kb
Host smart-16c95a3a-4e1e-4b75-8755-c1fdfa883f13
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404177488 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_
timer_same_csr_outstanding.404177488
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.1465969062
Short name T307
Test name
Test status
Simulation time 721070098 ps
CPU time 1.51 seconds
Started Mar 14 12:24:48 PM PDT 24
Finished Mar 14 12:24:49 PM PDT 24
Peak memory 198236 kb
Host smart-5dc88b4c-e1ca-4379-85ee-d30880e2e813
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465969062 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.1465969062
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.1400585797
Short name T357
Test name
Test status
Simulation time 4481553941 ps
CPU time 8.06 seconds
Started Mar 14 12:23:25 PM PDT 24
Finished Mar 14 12:23:33 PM PDT 24
Peak memory 197356 kb
Host smart-0be6ad63-1191-45b6-b403-9bee6e87af8e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400585797 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl
_intg_err.1400585797
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.1058366439
Short name T305
Test name
Test status
Simulation time 503574094 ps
CPU time 0.86 seconds
Started Mar 14 12:24:40 PM PDT 24
Finished Mar 14 12:24:41 PM PDT 24
Peak memory 183444 kb
Host smart-70bcd6f0-0391-427b-b34c-757e23e22585
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058366439 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.1058366439
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.1269790401
Short name T356
Test name
Test status
Simulation time 464066177 ps
CPU time 0.94 seconds
Started Mar 14 12:24:36 PM PDT 24
Finished Mar 14 12:24:37 PM PDT 24
Peak memory 183544 kb
Host smart-4b5b2b88-ba2c-41c6-9f13-fc856545325f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269790401 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.1269790401
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.2497986114
Short name T337
Test name
Test status
Simulation time 559539492 ps
CPU time 0.58 seconds
Started Mar 14 12:24:41 PM PDT 24
Finished Mar 14 12:24:41 PM PDT 24
Peak memory 183540 kb
Host smart-5848a935-3638-4634-a8f2-4a850a268a1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497986114 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.2497986114
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.4176541154
Short name T404
Test name
Test status
Simulation time 348267397 ps
CPU time 0.7 seconds
Started Mar 14 12:24:42 PM PDT 24
Finished Mar 14 12:24:43 PM PDT 24
Peak memory 183528 kb
Host smart-538f0eb4-7f21-490c-8342-3b6a10175f2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176541154 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.4176541154
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.964004122
Short name T289
Test name
Test status
Simulation time 333033024 ps
CPU time 0.6 seconds
Started Mar 14 12:24:45 PM PDT 24
Finished Mar 14 12:24:46 PM PDT 24
Peak memory 183644 kb
Host smart-4ddd82e4-4e68-428a-b796-4d9130424bc6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964004122 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.964004122
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.3428954078
Short name T331
Test name
Test status
Simulation time 388617332 ps
CPU time 0.54 seconds
Started Mar 14 12:24:27 PM PDT 24
Finished Mar 14 12:24:28 PM PDT 24
Peak memory 183468 kb
Host smart-c2614418-b4c1-4e9b-9d6d-d7370120df29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428954078 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.3428954078
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.3083171253
Short name T358
Test name
Test status
Simulation time 395274422 ps
CPU time 0.8 seconds
Started Mar 14 12:24:28 PM PDT 24
Finished Mar 14 12:24:29 PM PDT 24
Peak memory 183512 kb
Host smart-3409aea0-641a-42a0-a02c-802941ec35bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083171253 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.3083171253
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.2763592822
Short name T416
Test name
Test status
Simulation time 353766893 ps
CPU time 1.06 seconds
Started Mar 14 12:24:46 PM PDT 24
Finished Mar 14 12:24:47 PM PDT 24
Peak memory 183488 kb
Host smart-78487e00-6426-4ba1-991a-006ffb9f3511
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763592822 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.2763592822
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.218255677
Short name T421
Test name
Test status
Simulation time 484229733 ps
CPU time 0.71 seconds
Started Mar 14 12:24:45 PM PDT 24
Finished Mar 14 12:24:46 PM PDT 24
Peak memory 183556 kb
Host smart-568c1301-9621-4451-911b-b026584d7eda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218255677 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.218255677
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.1803531736
Short name T298
Test name
Test status
Simulation time 485195206 ps
CPU time 0.71 seconds
Started Mar 14 12:24:38 PM PDT 24
Finished Mar 14 12:24:39 PM PDT 24
Peak memory 183528 kb
Host smart-def3f44f-ee31-4e45-9cf2-e1dd228250b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803531736 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.1803531736
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.1945877085
Short name T304
Test name
Test status
Simulation time 563403538 ps
CPU time 1.17 seconds
Started Mar 14 12:23:43 PM PDT 24
Finished Mar 14 12:23:44 PM PDT 24
Peak memory 197732 kb
Host smart-ee7eaefc-36d8-4670-9a68-104be9d99792
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945877085 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.1945877085
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.1785008811
Short name T360
Test name
Test status
Simulation time 379886809 ps
CPU time 1.27 seconds
Started Mar 14 12:24:29 PM PDT 24
Finished Mar 14 12:24:30 PM PDT 24
Peak memory 193016 kb
Host smart-016e5931-12cd-4ad6-b1f8-9a17e42f2a6f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785008811 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.1785008811
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.181055149
Short name T319
Test name
Test status
Simulation time 315415944 ps
CPU time 1.12 seconds
Started Mar 14 12:23:24 PM PDT 24
Finished Mar 14 12:23:26 PM PDT 24
Peak memory 183644 kb
Host smart-5886ae34-c30f-433a-a109-523b70586c47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181055149 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.181055149
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.1432420870
Short name T341
Test name
Test status
Simulation time 1508879071 ps
CPU time 3.93 seconds
Started Mar 14 12:24:28 PM PDT 24
Finished Mar 14 12:24:32 PM PDT 24
Peak memory 183528 kb
Host smart-efbbc7a4-5386-4d98-be25-9a1fa7a5894b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432420870 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon
_timer_same_csr_outstanding.1432420870
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.2412271250
Short name T302
Test name
Test status
Simulation time 573449062 ps
CPU time 2.71 seconds
Started Mar 14 12:24:47 PM PDT 24
Finished Mar 14 12:24:50 PM PDT 24
Peak memory 198284 kb
Host smart-44a04814-bd47-4b7b-8f5b-839c5a763e71
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412271250 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.2412271250
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.2077709315
Short name T89
Test name
Test status
Simulation time 4157967758 ps
CPU time 8.07 seconds
Started Mar 14 12:24:31 PM PDT 24
Finished Mar 14 12:24:39 PM PDT 24
Peak memory 196660 kb
Host smart-375a7ef4-5ce7-48ee-907b-c0082621d314
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077709315 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl
_intg_err.2077709315
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.3348684862
Short name T374
Test name
Test status
Simulation time 401282488 ps
CPU time 0.78 seconds
Started Mar 14 12:23:44 PM PDT 24
Finished Mar 14 12:23:45 PM PDT 24
Peak memory 195568 kb
Host smart-c65c951d-785f-4865-a090-1e09fb60bfe5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348684862 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.3348684862
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.4024383840
Short name T30
Test name
Test status
Simulation time 520300337 ps
CPU time 0.81 seconds
Started Mar 14 12:23:37 PM PDT 24
Finished Mar 14 12:23:38 PM PDT 24
Peak memory 183852 kb
Host smart-a477bfab-1cb6-4089-a6aa-c4c42570d59a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024383840 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.4024383840
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.76331107
Short name T306
Test name
Test status
Simulation time 292549019 ps
CPU time 0.79 seconds
Started Mar 14 12:23:37 PM PDT 24
Finished Mar 14 12:23:38 PM PDT 24
Peak memory 183612 kb
Host smart-a40093d1-d14b-4a99-8967-fc054e499bf4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76331107 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.76331107
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.1235052143
Short name T396
Test name
Test status
Simulation time 1604101801 ps
CPU time 0.95 seconds
Started Mar 14 12:23:36 PM PDT 24
Finished Mar 14 12:23:37 PM PDT 24
Peak memory 193096 kb
Host smart-4301b1ff-1ab0-41ef-bc51-f28ea31c5fe0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235052143 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon
_timer_same_csr_outstanding.1235052143
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.2871847624
Short name T373
Test name
Test status
Simulation time 421673983 ps
CPU time 2.53 seconds
Started Mar 14 12:23:36 PM PDT 24
Finished Mar 14 12:23:39 PM PDT 24
Peak memory 198340 kb
Host smart-2cddcaff-3d96-405a-892a-3f87e6ef347e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871847624 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.2871847624
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.3093747096
Short name T35
Test name
Test status
Simulation time 8297054117 ps
CPU time 13.64 seconds
Started Mar 14 12:23:44 PM PDT 24
Finished Mar 14 12:23:58 PM PDT 24
Peak memory 197584 kb
Host smart-4ecdda43-5e2d-4187-a1d2-270cedc44e5e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093747096 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl
_intg_err.3093747096
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.1353492793
Short name T399
Test name
Test status
Simulation time 438015659 ps
CPU time 1.1 seconds
Started Mar 14 12:24:57 PM PDT 24
Finished Mar 14 12:24:59 PM PDT 24
Peak memory 194204 kb
Host smart-29334211-2aaf-466c-ba8a-4158698eb039
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353492793 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.1353492793
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.1070732417
Short name T95
Test name
Test status
Simulation time 427019729 ps
CPU time 1.42 seconds
Started Mar 14 12:24:57 PM PDT 24
Finished Mar 14 12:24:59 PM PDT 24
Peak memory 182176 kb
Host smart-2559caf5-e182-4fdf-a0ad-019313975593
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070732417 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.1070732417
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.373559386
Short name T403
Test name
Test status
Simulation time 465259869 ps
CPU time 1.32 seconds
Started Mar 14 12:24:47 PM PDT 24
Finished Mar 14 12:24:48 PM PDT 24
Peak memory 183340 kb
Host smart-e0c8281e-c67b-4ea2-aa67-ffc94c6658d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373559386 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.373559386
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.990984793
Short name T74
Test name
Test status
Simulation time 1721535970 ps
CPU time 4.16 seconds
Started Mar 14 12:23:43 PM PDT 24
Finished Mar 14 12:23:48 PM PDT 24
Peak memory 183916 kb
Host smart-28fd50dc-b77b-46dc-bed4-d2fb0cb78756
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990984793 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_
timer_same_csr_outstanding.990984793
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.1569672668
Short name T402
Test name
Test status
Simulation time 1296120267 ps
CPU time 2.22 seconds
Started Mar 14 12:23:36 PM PDT 24
Finished Mar 14 12:23:39 PM PDT 24
Peak memory 198348 kb
Host smart-b6aece62-d1b1-42cf-a009-b92773f8f6e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569672668 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.1569672668
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.2707259580
Short name T361
Test name
Test status
Simulation time 452319381 ps
CPU time 0.82 seconds
Started Mar 14 12:24:58 PM PDT 24
Finished Mar 14 12:24:59 PM PDT 24
Peak memory 195476 kb
Host smart-c0622ce9-4d5f-45a7-aa96-4bf22bd93ec7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707259580 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.2707259580
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.854631210
Short name T28
Test name
Test status
Simulation time 377468306 ps
CPU time 0.75 seconds
Started Mar 14 12:24:58 PM PDT 24
Finished Mar 14 12:24:59 PM PDT 24
Peak memory 183560 kb
Host smart-2abfc41d-97f2-414d-9e48-265dac8a3bd0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854631210 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.854631210
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.4100974510
Short name T384
Test name
Test status
Simulation time 499658161 ps
CPU time 0.6 seconds
Started Mar 14 12:24:57 PM PDT 24
Finished Mar 14 12:24:58 PM PDT 24
Peak memory 182092 kb
Host smart-48245d70-dadd-4797-a50c-12e6129ee5b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100974510 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.4100974510
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.1478461413
Short name T411
Test name
Test status
Simulation time 2498883332 ps
CPU time 1.26 seconds
Started Mar 14 12:25:00 PM PDT 24
Finished Mar 14 12:25:01 PM PDT 24
Peak memory 194028 kb
Host smart-4f4fbfe9-622a-46af-bbb5-27fae1d04f28
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478461413 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon
_timer_same_csr_outstanding.1478461413
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.2875094166
Short name T409
Test name
Test status
Simulation time 457889015 ps
CPU time 1.54 seconds
Started Mar 14 12:25:00 PM PDT 24
Finished Mar 14 12:25:01 PM PDT 24
Peak memory 198324 kb
Host smart-b6cc7b30-dd41-458b-87d7-7687f32a0cf7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875094166 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.2875094166
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.2116473586
Short name T338
Test name
Test status
Simulation time 4300957223 ps
CPU time 2.5 seconds
Started Mar 14 12:24:50 PM PDT 24
Finished Mar 14 12:24:53 PM PDT 24
Peak memory 197388 kb
Host smart-27643239-403d-4831-989c-312c9f895be1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116473586 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl
_intg_err.2116473586
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.3204086911
Short name T415
Test name
Test status
Simulation time 424761774 ps
CPU time 1.11 seconds
Started Mar 14 12:23:44 PM PDT 24
Finished Mar 14 12:23:45 PM PDT 24
Peak memory 196132 kb
Host smart-3d24c8b0-f3c0-4d92-bd4d-46321836ee18
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204086911 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.3204086911
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.1621485087
Short name T321
Test name
Test status
Simulation time 487669424 ps
CPU time 1.07 seconds
Started Mar 14 12:24:57 PM PDT 24
Finished Mar 14 12:24:59 PM PDT 24
Peak memory 183344 kb
Host smart-ef09c773-68c6-4efc-975a-cfa0e41dd522
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621485087 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.1621485087
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.974628224
Short name T336
Test name
Test status
Simulation time 381627006 ps
CPU time 0.65 seconds
Started Mar 14 12:23:36 PM PDT 24
Finished Mar 14 12:23:37 PM PDT 24
Peak memory 183504 kb
Host smart-a53508b6-252f-495f-b01d-fec6ef9020e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974628224 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.974628224
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.2567102024
Short name T387
Test name
Test status
Simulation time 1451882334 ps
CPU time 3.69 seconds
Started Mar 14 12:23:44 PM PDT 24
Finished Mar 14 12:23:48 PM PDT 24
Peak memory 193204 kb
Host smart-cc5b2183-27a3-44b4-934a-780814e2f0bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567102024 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon
_timer_same_csr_outstanding.2567102024
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.2523735141
Short name T310
Test name
Test status
Simulation time 445505486 ps
CPU time 2.63 seconds
Started Mar 14 12:24:57 PM PDT 24
Finished Mar 14 12:25:00 PM PDT 24
Peak memory 197476 kb
Host smart-c2550b87-e249-4058-bffc-517bf69095bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523735141 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.2523735141
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.4231573015
Short name T365
Test name
Test status
Simulation time 8458413254 ps
CPU time 7.81 seconds
Started Mar 14 12:23:37 PM PDT 24
Finished Mar 14 12:23:45 PM PDT 24
Peak memory 197816 kb
Host smart-d8ffacac-3868-479d-8983-5d01976230cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231573015 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl
_intg_err.4231573015
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_jump.2098123716
Short name T156
Test name
Test status
Simulation time 546152017 ps
CPU time 0.79 seconds
Started Mar 14 12:27:03 PM PDT 24
Finished Mar 14 12:27:04 PM PDT 24
Peak memory 183460 kb
Host smart-d26b6c05-082a-4074-8bdf-241d9fea7eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098123716 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.2098123716
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.4142071388
Short name T181
Test name
Test status
Simulation time 19937793933 ps
CPU time 14.87 seconds
Started Mar 14 12:27:06 PM PDT 24
Finished Mar 14 12:27:21 PM PDT 24
Peak memory 183532 kb
Host smart-63825084-cbd7-4e62-a5ce-e4875a6bdc46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142071388 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.4142071388
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.2922078235
Short name T255
Test name
Test status
Simulation time 325198733 ps
CPU time 0.98 seconds
Started Mar 14 12:27:08 PM PDT 24
Finished Mar 14 12:27:09 PM PDT 24
Peak memory 183472 kb
Host smart-f8dda5be-bccd-4128-a1c3-a428686f00cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922078235 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.2922078235
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.2162349457
Short name T87
Test name
Test status
Simulation time 59574559576 ps
CPU time 23.6 seconds
Started Mar 14 12:27:18 PM PDT 24
Finished Mar 14 12:27:42 PM PDT 24
Peak memory 183480 kb
Host smart-e9d7f268-8e5e-49a1-a5ec-f7b7f9fad06f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162349457 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_a
ll.2162349457
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.2080567962
Short name T47
Test name
Test status
Simulation time 184996393773 ps
CPU time 686.49 seconds
Started Mar 14 12:27:16 PM PDT 24
Finished Mar 14 12:38:43 PM PDT 24
Peak memory 201008 kb
Host smart-4d98cfbd-c2ea-402b-b562-3e32feb02999
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080567962 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.2080567962
Directory /workspace/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.aon_timer_jump.2301122440
Short name T224
Test name
Test status
Simulation time 551750680 ps
CPU time 0.66 seconds
Started Mar 14 12:27:42 PM PDT 24
Finished Mar 14 12:27:43 PM PDT 24
Peak memory 183332 kb
Host smart-40100419-b4bd-4eae-9436-c5fe7a2cbed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301122440 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.2301122440
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.2933611468
Short name T113
Test name
Test status
Simulation time 15694948812 ps
CPU time 24.45 seconds
Started Mar 14 12:26:53 PM PDT 24
Finished Mar 14 12:27:18 PM PDT 24
Peak memory 183416 kb
Host smart-c713d06f-db12-4894-a022-3dfe25d0a1ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933611468 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.2933611468
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.2000365073
Short name T16
Test name
Test status
Simulation time 4651699834 ps
CPU time 4.39 seconds
Started Mar 14 12:27:15 PM PDT 24
Finished Mar 14 12:27:20 PM PDT 24
Peak memory 215012 kb
Host smart-ea739425-aa8f-4875-9272-863eb480d03e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000365073 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.2000365073
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.1336625813
Short name T151
Test name
Test status
Simulation time 494783486 ps
CPU time 1.24 seconds
Started Mar 14 12:26:58 PM PDT 24
Finished Mar 14 12:27:00 PM PDT 24
Peak memory 183444 kb
Host smart-b7583c7b-a2f2-491a-be7c-7e803092eac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336625813 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.1336625813
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.1972051611
Short name T43
Test name
Test status
Simulation time 221920323187 ps
CPU time 360.56 seconds
Started Mar 14 12:27:11 PM PDT 24
Finished Mar 14 12:33:12 PM PDT 24
Peak memory 194812 kb
Host smart-dafc49f6-73bf-4da2-a7ef-54b8d1925235
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972051611 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_a
ll.1972051611
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.2473108855
Short name T138
Test name
Test status
Simulation time 197366479333 ps
CPU time 408.8 seconds
Started Mar 14 12:26:56 PM PDT 24
Finished Mar 14 12:33:45 PM PDT 24
Peak memory 198436 kb
Host smart-db866c8b-805a-4357-bcb3-a7c51de01f22
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473108855 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.2473108855
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.aon_timer_jump.2591975787
Short name T109
Test name
Test status
Simulation time 549559452 ps
CPU time 1.38 seconds
Started Mar 14 12:27:40 PM PDT 24
Finished Mar 14 12:27:41 PM PDT 24
Peak memory 183452 kb
Host smart-9e2933f5-a6d3-4aa4-9a29-3e9b4dc5a659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591975787 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.2591975787
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.1957865544
Short name T107
Test name
Test status
Simulation time 57622796475 ps
CPU time 84.37 seconds
Started Mar 14 12:27:16 PM PDT 24
Finished Mar 14 12:28:41 PM PDT 24
Peak memory 183480 kb
Host smart-09c440ee-b8a6-4fa8-9359-941b4b40be58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957865544 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.1957865544
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.3769793068
Short name T135
Test name
Test status
Simulation time 512419301 ps
CPU time 0.71 seconds
Started Mar 14 12:27:17 PM PDT 24
Finished Mar 14 12:27:18 PM PDT 24
Peak memory 183428 kb
Host smart-73522959-ab42-4a20-8e41-839ed32aadb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769793068 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.3769793068
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.3958962762
Short name T192
Test name
Test status
Simulation time 58566195301 ps
CPU time 47.89 seconds
Started Mar 14 12:27:17 PM PDT 24
Finished Mar 14 12:28:05 PM PDT 24
Peak memory 183452 kb
Host smart-9dc05c01-9980-4c53-a371-d15037528b17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958962762 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_
all.3958962762
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.276590569
Short name T177
Test name
Test status
Simulation time 66189239060 ps
CPU time 320.5 seconds
Started Mar 14 12:27:18 PM PDT 24
Finished Mar 14 12:32:39 PM PDT 24
Peak memory 198436 kb
Host smart-247506f7-7ced-4114-8526-2423064e0bb2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276590569 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.276590569
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.aon_timer_jump.1903752819
Short name T130
Test name
Test status
Simulation time 530702732 ps
CPU time 0.68 seconds
Started Mar 14 12:27:37 PM PDT 24
Finished Mar 14 12:27:37 PM PDT 24
Peak memory 183336 kb
Host smart-acf457be-5ce4-4a16-82b2-45f02d712a26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903752819 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.1903752819
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.3355015688
Short name T275
Test name
Test status
Simulation time 56803987600 ps
CPU time 42.36 seconds
Started Mar 14 12:26:58 PM PDT 24
Finished Mar 14 12:27:40 PM PDT 24
Peak memory 183508 kb
Host smart-5c39741a-469a-41e8-97b6-1ee40c730b70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355015688 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.3355015688
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.2630302360
Short name T153
Test name
Test status
Simulation time 558958083 ps
CPU time 0.71 seconds
Started Mar 14 12:26:56 PM PDT 24
Finished Mar 14 12:26:57 PM PDT 24
Peak memory 183448 kb
Host smart-053b5466-b153-4f5b-bc89-68512879771d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630302360 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.2630302360
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.1594256251
Short name T142
Test name
Test status
Simulation time 231789580359 ps
CPU time 60.56 seconds
Started Mar 14 12:27:17 PM PDT 24
Finished Mar 14 12:28:18 PM PDT 24
Peak memory 194936 kb
Host smart-6fce40bf-6a15-4c67-b37f-af21542a4c55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594256251 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_
all.1594256251
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.1523882280
Short name T175
Test name
Test status
Simulation time 52738657174 ps
CPU time 552.54 seconds
Started Mar 14 12:27:21 PM PDT 24
Finished Mar 14 12:36:34 PM PDT 24
Peak memory 206588 kb
Host smart-ae7a2cfc-36fc-4bb4-b6e1-2dc9df51b792
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523882280 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand_reset.1523882280
Directory /workspace/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.aon_timer_jump.2180600177
Short name T53
Test name
Test status
Simulation time 378669115 ps
CPU time 1.16 seconds
Started Mar 14 12:26:55 PM PDT 24
Finished Mar 14 12:26:56 PM PDT 24
Peak memory 183432 kb
Host smart-feb23832-60bd-4030-a4c5-c92cf8668cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180600177 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.2180600177
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.2699747993
Short name T239
Test name
Test status
Simulation time 11988285485 ps
CPU time 20.13 seconds
Started Mar 14 12:27:06 PM PDT 24
Finished Mar 14 12:27:26 PM PDT 24
Peak memory 183488 kb
Host smart-c83e4306-8c64-4f55-8922-a3669221b6fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699747993 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.2699747993
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.2615460001
Short name T196
Test name
Test status
Simulation time 607440113 ps
CPU time 0.9 seconds
Started Mar 14 12:27:09 PM PDT 24
Finished Mar 14 12:27:10 PM PDT 24
Peak memory 183424 kb
Host smart-0d7b8cda-1d4d-4210-86df-8904db9f6f1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615460001 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.2615460001
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.1352437827
Short name T129
Test name
Test status
Simulation time 63837809585 ps
CPU time 101.52 seconds
Started Mar 14 12:27:34 PM PDT 24
Finished Mar 14 12:29:16 PM PDT 24
Peak memory 195388 kb
Host smart-5da41a9b-30b4-4a31-a123-1c3a3d3dfec6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352437827 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_
all.1352437827
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.1750096543
Short name T197
Test name
Test status
Simulation time 80849464447 ps
CPU time 421.91 seconds
Started Mar 14 12:27:17 PM PDT 24
Finished Mar 14 12:34:19 PM PDT 24
Peak memory 198456 kb
Host smart-1e3189dd-5c03-4052-b014-509018b1bb25
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750096543 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.1750096543
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_jump.3962189068
Short name T25
Test name
Test status
Simulation time 363199690 ps
CPU time 1.21 seconds
Started Mar 14 12:27:17 PM PDT 24
Finished Mar 14 12:27:18 PM PDT 24
Peak memory 183424 kb
Host smart-020c1db6-5058-4321-afb2-f60e02b2804a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962189068 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.3962189068
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.4156638019
Short name T104
Test name
Test status
Simulation time 11694760597 ps
CPU time 5.09 seconds
Started Mar 14 12:27:20 PM PDT 24
Finished Mar 14 12:27:26 PM PDT 24
Peak memory 183480 kb
Host smart-37c0afff-8336-46a0-861d-3de4ff66d268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156638019 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.4156638019
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.1143458263
Short name T121
Test name
Test status
Simulation time 543269968 ps
CPU time 0.65 seconds
Started Mar 14 12:27:17 PM PDT 24
Finished Mar 14 12:27:18 PM PDT 24
Peak memory 183412 kb
Host smart-5a8b333c-2ca4-4361-8ac5-29ee6a54bc65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143458263 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.1143458263
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.2304152339
Short name T212
Test name
Test status
Simulation time 47084518261 ps
CPU time 250.91 seconds
Started Mar 14 12:27:01 PM PDT 24
Finished Mar 14 12:31:12 PM PDT 24
Peak memory 198420 kb
Host smart-05f31678-53f4-424c-a574-37ffeedff097
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304152339 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.2304152339
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.aon_timer_jump.3958391900
Short name T2
Test name
Test status
Simulation time 395382326 ps
CPU time 0.69 seconds
Started Mar 14 12:27:30 PM PDT 24
Finished Mar 14 12:27:31 PM PDT 24
Peak memory 183408 kb
Host smart-74b66cb4-1768-4885-a229-93b91e0d884d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958391900 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.3958391900
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.4192250138
Short name T15
Test name
Test status
Simulation time 6007647010 ps
CPU time 10.05 seconds
Started Mar 14 12:27:21 PM PDT 24
Finished Mar 14 12:27:31 PM PDT 24
Peak memory 183404 kb
Host smart-42fce54a-ed32-4b1c-97e7-12af5a7e1688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192250138 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.4192250138
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.2021181057
Short name T247
Test name
Test status
Simulation time 508960351 ps
CPU time 1.38 seconds
Started Mar 14 12:27:24 PM PDT 24
Finished Mar 14 12:27:25 PM PDT 24
Peak memory 183404 kb
Host smart-8c508e3a-34b8-4f73-b1e9-6ddb3d2023b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021181057 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.2021181057
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.1440661775
Short name T215
Test name
Test status
Simulation time 63540359493 ps
CPU time 21.29 seconds
Started Mar 14 12:27:21 PM PDT 24
Finished Mar 14 12:27:47 PM PDT 24
Peak memory 183396 kb
Host smart-a6546f96-75b8-430a-9579-dee2cc1be0ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440661775 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_
all.1440661775
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.907864089
Short name T85
Test name
Test status
Simulation time 122544779882 ps
CPU time 185.14 seconds
Started Mar 14 12:27:17 PM PDT 24
Finished Mar 14 12:30:22 PM PDT 24
Peak memory 198412 kb
Host smart-f186bc1c-9eb0-4434-a724-d12ea6667196
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907864089 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.907864089
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.aon_timer_jump.455213026
Short name T268
Test name
Test status
Simulation time 600819067 ps
CPU time 1 seconds
Started Mar 14 12:27:25 PM PDT 24
Finished Mar 14 12:27:27 PM PDT 24
Peak memory 183548 kb
Host smart-1be3f1c1-7bbb-4ea4-8bab-88b693e2dedc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455213026 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.455213026
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.2860511999
Short name T230
Test name
Test status
Simulation time 24999750453 ps
CPU time 10.01 seconds
Started Mar 14 12:27:21 PM PDT 24
Finished Mar 14 12:27:31 PM PDT 24
Peak memory 183396 kb
Host smart-d8b6958b-d66b-495b-977a-5417796d4b0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860511999 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.2860511999
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.3608234191
Short name T166
Test name
Test status
Simulation time 504442447 ps
CPU time 1.24 seconds
Started Mar 14 12:27:25 PM PDT 24
Finished Mar 14 12:27:27 PM PDT 24
Peak memory 183300 kb
Host smart-398de401-8a50-4e3e-aea2-c2dd70623963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608234191 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.3608234191
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.3318340519
Short name T86
Test name
Test status
Simulation time 82440452155 ps
CPU time 35.57 seconds
Started Mar 14 12:27:21 PM PDT 24
Finished Mar 14 12:27:56 PM PDT 24
Peak memory 183540 kb
Host smart-192f6867-4801-49b7-aa1b-eb505f546987
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318340519 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_
all.3318340519
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_jump.848851043
Short name T190
Test name
Test status
Simulation time 593535533 ps
CPU time 1.05 seconds
Started Mar 14 12:27:13 PM PDT 24
Finished Mar 14 12:27:14 PM PDT 24
Peak memory 183556 kb
Host smart-9c4d29e0-a07a-48a9-a348-2159538e4507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848851043 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.848851043
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.4039562018
Short name T208
Test name
Test status
Simulation time 31431242426 ps
CPU time 44.29 seconds
Started Mar 14 12:27:26 PM PDT 24
Finished Mar 14 12:28:10 PM PDT 24
Peak memory 183460 kb
Host smart-66e199ad-b37f-4ee2-9b8d-8f78f4924aab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039562018 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.4039562018
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.2266393512
Short name T254
Test name
Test status
Simulation time 480553944 ps
CPU time 0.76 seconds
Started Mar 14 12:27:17 PM PDT 24
Finished Mar 14 12:27:18 PM PDT 24
Peak memory 183496 kb
Host smart-ddfe1393-6ea0-41c3-901a-9f27a8d3b1fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266393512 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.2266393512
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.1338210304
Short name T13
Test name
Test status
Simulation time 54879367555 ps
CPU time 24.51 seconds
Started Mar 14 12:27:15 PM PDT 24
Finished Mar 14 12:27:39 PM PDT 24
Peak memory 183496 kb
Host smart-37bab348-0627-4454-a6d3-7b2ae3d31c9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338210304 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_
all.1338210304
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.2648668719
Short name T41
Test name
Test status
Simulation time 50354541933 ps
CPU time 549.76 seconds
Started Mar 14 12:27:20 PM PDT 24
Finished Mar 14 12:36:30 PM PDT 24
Peak memory 206616 kb
Host smart-c23e2aea-53aa-4f9b-9271-f039057a8e1c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648668719 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.2648668719
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.aon_timer_jump.842387196
Short name T114
Test name
Test status
Simulation time 660839076 ps
CPU time 0.59 seconds
Started Mar 14 12:27:13 PM PDT 24
Finished Mar 14 12:27:13 PM PDT 24
Peak memory 183432 kb
Host smart-7ffa4a12-0b92-4efc-9942-1668f2dd22f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842387196 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.842387196
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.3480472739
Short name T88
Test name
Test status
Simulation time 44209698385 ps
CPU time 18.07 seconds
Started Mar 14 12:27:15 PM PDT 24
Finished Mar 14 12:27:33 PM PDT 24
Peak memory 183480 kb
Host smart-ecb9bf2e-c969-418d-8692-6d08aeb56ff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480472739 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.3480472739
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.2225700318
Short name T46
Test name
Test status
Simulation time 612472199 ps
CPU time 1.37 seconds
Started Mar 14 12:27:30 PM PDT 24
Finished Mar 14 12:27:32 PM PDT 24
Peak memory 183516 kb
Host smart-85b3ca33-ea91-471a-9cb2-1f4125cbdaa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225700318 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.2225700318
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.4269854984
Short name T101
Test name
Test status
Simulation time 142097417503 ps
CPU time 50.39 seconds
Started Mar 14 12:27:06 PM PDT 24
Finished Mar 14 12:27:57 PM PDT 24
Peak memory 183528 kb
Host smart-27ac0aaa-f4fb-4d0c-abc1-b7e74910865d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269854984 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_
all.4269854984
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_jump.116298762
Short name T122
Test name
Test status
Simulation time 531961169 ps
CPU time 1.31 seconds
Started Mar 14 12:27:17 PM PDT 24
Finished Mar 14 12:27:19 PM PDT 24
Peak memory 183328 kb
Host smart-3e811544-849f-420f-badd-78e462a10d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116298762 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.116298762
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.204788241
Short name T241
Test name
Test status
Simulation time 11050715717 ps
CPU time 10.44 seconds
Started Mar 14 12:27:25 PM PDT 24
Finished Mar 14 12:27:36 PM PDT 24
Peak memory 183484 kb
Host smart-5fa52246-65e1-4f7b-8325-55a5c780debc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204788241 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.204788241
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.938259542
Short name T134
Test name
Test status
Simulation time 509744696 ps
CPU time 0.71 seconds
Started Mar 14 12:27:24 PM PDT 24
Finished Mar 14 12:27:25 PM PDT 24
Peak memory 183512 kb
Host smart-0b2cbc0a-e1b2-4d31-988a-029c62191229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938259542 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.938259542
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.201317074
Short name T278
Test name
Test status
Simulation time 86292932995 ps
CPU time 104.25 seconds
Started Mar 14 12:27:16 PM PDT 24
Finished Mar 14 12:29:01 PM PDT 24
Peak memory 193688 kb
Host smart-aaa5f517-6b4b-4d08-a9a5-5c4039e44fad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201317074 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_a
ll.201317074
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.1080287418
Short name T217
Test name
Test status
Simulation time 34766387341 ps
CPU time 242.09 seconds
Started Mar 14 12:27:24 PM PDT 24
Finished Mar 14 12:31:26 PM PDT 24
Peak memory 198412 kb
Host smart-067e5e14-c96d-4de5-82ec-8c5361f0977f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080287418 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.1080287418
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.aon_timer_jump.209039773
Short name T127
Test name
Test status
Simulation time 517339623 ps
CPU time 1.3 seconds
Started Mar 14 12:27:22 PM PDT 24
Finished Mar 14 12:27:23 PM PDT 24
Peak memory 183392 kb
Host smart-af7486eb-e99c-4e48-9b55-46355aab8b65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209039773 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.209039773
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.1156916073
Short name T8
Test name
Test status
Simulation time 47985154868 ps
CPU time 16.32 seconds
Started Mar 14 12:27:14 PM PDT 24
Finished Mar 14 12:27:30 PM PDT 24
Peak memory 183484 kb
Host smart-69a1f374-4b65-4425-bc1d-74d9648833ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156916073 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.1156916073
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.2761389350
Short name T144
Test name
Test status
Simulation time 502132380 ps
CPU time 0.7 seconds
Started Mar 14 12:27:25 PM PDT 24
Finished Mar 14 12:27:26 PM PDT 24
Peak memory 183424 kb
Host smart-8124aac0-b4ef-4347-85be-bca328f43b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761389350 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.2761389350
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.2568150057
Short name T26
Test name
Test status
Simulation time 113190298640 ps
CPU time 93.44 seconds
Started Mar 14 12:27:14 PM PDT 24
Finished Mar 14 12:28:47 PM PDT 24
Peak memory 195444 kb
Host smart-b736c952-1400-4717-bdea-9dd601eb993b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568150057 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_
all.2568150057
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_jump.965421403
Short name T165
Test name
Test status
Simulation time 532743464 ps
CPU time 0.99 seconds
Started Mar 14 12:26:54 PM PDT 24
Finished Mar 14 12:26:55 PM PDT 24
Peak memory 183412 kb
Host smart-39331f03-9e50-498a-98d7-f8f89bacf374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965421403 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.965421403
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.2366222157
Short name T10
Test name
Test status
Simulation time 3840627147 ps
CPU time 6.3 seconds
Started Mar 14 12:27:16 PM PDT 24
Finished Mar 14 12:27:22 PM PDT 24
Peak memory 183536 kb
Host smart-c6c310f4-c5e2-46dd-92e0-229bc77af315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366222157 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.2366222157
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.1964883496
Short name T22
Test name
Test status
Simulation time 4609483346 ps
CPU time 1.03 seconds
Started Mar 14 12:27:09 PM PDT 24
Finished Mar 14 12:27:10 PM PDT 24
Peak memory 215036 kb
Host smart-2d91b178-5f8f-4116-b504-c2605f0309f2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964883496 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.1964883496
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.557974494
Short name T137
Test name
Test status
Simulation time 514329598 ps
CPU time 0.93 seconds
Started Mar 14 12:27:18 PM PDT 24
Finished Mar 14 12:27:19 PM PDT 24
Peak memory 183404 kb
Host smart-5e0c69b7-9bee-4097-a3cf-d171295cfc77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557974494 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.557974494
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.4004876558
Short name T98
Test name
Test status
Simulation time 141836513731 ps
CPU time 98.85 seconds
Started Mar 14 12:27:29 PM PDT 24
Finished Mar 14 12:29:08 PM PDT 24
Peak memory 195244 kb
Host smart-594b49a4-6526-48ba-a8e7-f012cb185248
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004876558 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_a
ll.4004876558
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.120664459
Short name T267
Test name
Test status
Simulation time 145391438420 ps
CPU time 307.93 seconds
Started Mar 14 12:27:10 PM PDT 24
Finished Mar 14 12:32:18 PM PDT 24
Peak memory 198468 kb
Host smart-2b75804a-c4fb-4b9a-866d-6f805cf40f1b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120664459 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.120664459
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.aon_timer_jump.3188307419
Short name T145
Test name
Test status
Simulation time 520850724 ps
CPU time 0.55 seconds
Started Mar 14 12:27:07 PM PDT 24
Finished Mar 14 12:27:07 PM PDT 24
Peak memory 183336 kb
Host smart-f3b43ba0-7701-4f04-8d5a-25ef0eef096c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188307419 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.3188307419
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.3471309687
Short name T274
Test name
Test status
Simulation time 12915736986 ps
CPU time 22.07 seconds
Started Mar 14 12:27:36 PM PDT 24
Finished Mar 14 12:27:59 PM PDT 24
Peak memory 183488 kb
Host smart-940e5946-9984-4a51-88c1-d60ed3160ace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471309687 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.3471309687
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.575529362
Short name T262
Test name
Test status
Simulation time 574050946 ps
CPU time 1.24 seconds
Started Mar 14 12:27:13 PM PDT 24
Finished Mar 14 12:27:14 PM PDT 24
Peak memory 183344 kb
Host smart-1a049c45-d332-436f-acd8-02725c45115a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575529362 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.575529362
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.411775290
Short name T280
Test name
Test status
Simulation time 162119980182 ps
CPU time 167.82 seconds
Started Mar 14 12:27:19 PM PDT 24
Finished Mar 14 12:30:07 PM PDT 24
Peak memory 183636 kb
Host smart-650447a7-c6d4-4940-9e13-81ca8eb4811d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411775290 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_a
ll.411775290
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.3434328777
Short name T124
Test name
Test status
Simulation time 46449199366 ps
CPU time 117.97 seconds
Started Mar 14 12:27:08 PM PDT 24
Finished Mar 14 12:29:07 PM PDT 24
Peak memory 198420 kb
Host smart-0746f5c0-241e-48a6-b1fd-ef55bce707d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434328777 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.3434328777
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_jump.2784584994
Short name T184
Test name
Test status
Simulation time 589200051 ps
CPU time 0.77 seconds
Started Mar 14 12:27:35 PM PDT 24
Finished Mar 14 12:27:36 PM PDT 24
Peak memory 183448 kb
Host smart-2b8e1bde-1376-4c86-bd06-3ce9832bb129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784584994 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.2784584994
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.3376507932
Short name T243
Test name
Test status
Simulation time 7495583217 ps
CPU time 3.92 seconds
Started Mar 14 12:27:19 PM PDT 24
Finished Mar 14 12:27:23 PM PDT 24
Peak memory 183456 kb
Host smart-fcffe568-8605-45d3-b9e5-1c99b99be4a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376507932 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.3376507932
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.3284914243
Short name T6
Test name
Test status
Simulation time 520605841 ps
CPU time 1.23 seconds
Started Mar 14 12:27:15 PM PDT 24
Finished Mar 14 12:27:22 PM PDT 24
Peak memory 183388 kb
Host smart-6946b3c2-514f-41bd-9613-c6565b363f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284914243 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.3284914243
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.1978218007
Short name T233
Test name
Test status
Simulation time 101452534166 ps
CPU time 71.71 seconds
Started Mar 14 12:27:15 PM PDT 24
Finished Mar 14 12:28:27 PM PDT 24
Peak memory 194124 kb
Host smart-76c8479c-1148-4e6b-b98a-37f1194433de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978218007 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_
all.1978218007
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_jump.711664483
Short name T221
Test name
Test status
Simulation time 405126505 ps
CPU time 1.12 seconds
Started Mar 14 12:27:20 PM PDT 24
Finished Mar 14 12:27:22 PM PDT 24
Peak memory 183424 kb
Host smart-4a05d522-89ae-4ef0-ad9e-6ad8883522dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711664483 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.711664483
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.1198931650
Short name T283
Test name
Test status
Simulation time 53520375050 ps
CPU time 21.47 seconds
Started Mar 14 12:27:24 PM PDT 24
Finished Mar 14 12:27:46 PM PDT 24
Peak memory 183484 kb
Host smart-c8299dd8-88b3-41f7-87f0-a9f040501129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198931650 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.1198931650
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.414658267
Short name T139
Test name
Test status
Simulation time 650329474 ps
CPU time 0.56 seconds
Started Mar 14 12:27:15 PM PDT 24
Finished Mar 14 12:27:16 PM PDT 24
Peak memory 183396 kb
Host smart-f6c5f83f-13eb-484f-8a0c-38997e352a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414658267 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.414658267
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.67693107
Short name T265
Test name
Test status
Simulation time 180131392722 ps
CPU time 239.92 seconds
Started Mar 14 12:27:56 PM PDT 24
Finished Mar 14 12:31:56 PM PDT 24
Peak memory 183476 kb
Host smart-320a4cc0-2c2a-48f8-ad5e-a9064a5f1efa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67693107 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_al
l.67693107
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.1777812816
Short name T50
Test name
Test status
Simulation time 215994878261 ps
CPU time 988.79 seconds
Started Mar 14 12:27:46 PM PDT 24
Finished Mar 14 12:44:15 PM PDT 24
Peak memory 204268 kb
Host smart-88901f96-30ce-4220-a7e9-ae786f157e08
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777812816 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.1777812816
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.aon_timer_jump.1321813254
Short name T251
Test name
Test status
Simulation time 464959770 ps
CPU time 1.25 seconds
Started Mar 14 12:27:36 PM PDT 24
Finished Mar 14 12:27:38 PM PDT 24
Peak memory 183420 kb
Host smart-8d7a2f17-7094-41e6-82ee-de8a1f6d7f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321813254 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.1321813254
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.3385853626
Short name T11
Test name
Test status
Simulation time 47854229133 ps
CPU time 14.9 seconds
Started Mar 14 12:27:23 PM PDT 24
Finished Mar 14 12:27:38 PM PDT 24
Peak memory 183480 kb
Host smart-af1e4671-1755-4ebf-a4dd-808597abdb1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385853626 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.3385853626
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.1620571610
Short name T187
Test name
Test status
Simulation time 521468840 ps
CPU time 1.33 seconds
Started Mar 14 12:27:23 PM PDT 24
Finished Mar 14 12:27:24 PM PDT 24
Peak memory 183416 kb
Host smart-448ad3cd-aa3d-47fd-868a-5f45e4e6b5c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620571610 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.1620571610
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.3539981341
Short name T136
Test name
Test status
Simulation time 290514088362 ps
CPU time 118.4 seconds
Started Mar 14 12:27:36 PM PDT 24
Finished Mar 14 12:29:35 PM PDT 24
Peak memory 194932 kb
Host smart-f5cc7ad5-16b3-44be-8c36-07580227b8ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539981341 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_
all.3539981341
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.2384419160
Short name T83
Test name
Test status
Simulation time 312485710010 ps
CPU time 250.06 seconds
Started Mar 14 12:27:17 PM PDT 24
Finished Mar 14 12:31:27 PM PDT 24
Peak memory 213976 kb
Host smart-32477a87-389e-4119-afe5-824d4940ff51
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384419160 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.2384419160
Directory /workspace/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.aon_timer_jump.3625137095
Short name T128
Test name
Test status
Simulation time 358925104 ps
CPU time 0.65 seconds
Started Mar 14 12:27:21 PM PDT 24
Finished Mar 14 12:27:22 PM PDT 24
Peak memory 183340 kb
Host smart-77ead639-072b-478f-b589-55b547e78b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625137095 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.3625137095
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.820292082
Short name T183
Test name
Test status
Simulation time 21782325783 ps
CPU time 32.59 seconds
Started Mar 14 12:27:32 PM PDT 24
Finished Mar 14 12:28:05 PM PDT 24
Peak memory 183468 kb
Host smart-a1cc5a03-76ff-404e-99e5-5bc8bda88d20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820292082 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.820292082
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.3480638940
Short name T281
Test name
Test status
Simulation time 544045762 ps
CPU time 0.93 seconds
Started Mar 14 12:27:19 PM PDT 24
Finished Mar 14 12:27:20 PM PDT 24
Peak memory 183552 kb
Host smart-7f9fe8ce-58d9-417c-84e0-ce53c7d09a26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480638940 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.3480638940
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.3494116120
Short name T131
Test name
Test status
Simulation time 132583719667 ps
CPU time 88.26 seconds
Started Mar 14 12:27:21 PM PDT 24
Finished Mar 14 12:28:49 PM PDT 24
Peak memory 193492 kb
Host smart-c5e2b5ca-5193-4473-8d82-9beca29a7e21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494116120 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_
all.3494116120
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.3743478998
Short name T38
Test name
Test status
Simulation time 136023777451 ps
CPU time 338.39 seconds
Started Mar 14 12:27:29 PM PDT 24
Finished Mar 14 12:33:07 PM PDT 24
Peak memory 198408 kb
Host smart-28e47e7f-2038-48fa-a3af-c9a80987d001
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743478998 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand_reset.3743478998
Directory /workspace/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.aon_timer_jump.3242119541
Short name T141
Test name
Test status
Simulation time 414516458 ps
CPU time 0.66 seconds
Started Mar 14 12:27:24 PM PDT 24
Finished Mar 14 12:27:25 PM PDT 24
Peak memory 183332 kb
Host smart-698069ed-ecc5-4847-a2b5-552ba21d14fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242119541 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.3242119541
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.1785033233
Short name T204
Test name
Test status
Simulation time 5378521766 ps
CPU time 4.29 seconds
Started Mar 14 12:27:13 PM PDT 24
Finished Mar 14 12:27:17 PM PDT 24
Peak memory 183480 kb
Host smart-c5f2b42f-51f8-4ce0-8e0f-1ebe72e10bef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785033233 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.1785033233
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.2232724269
Short name T120
Test name
Test status
Simulation time 497927632 ps
CPU time 0.72 seconds
Started Mar 14 12:27:21 PM PDT 24
Finished Mar 14 12:27:22 PM PDT 24
Peak memory 183324 kb
Host smart-b5e52fbf-b40e-4752-bda5-978b98bd6a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232724269 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.2232724269
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.2068554412
Short name T199
Test name
Test status
Simulation time 9503224350 ps
CPU time 13.16 seconds
Started Mar 14 12:27:16 PM PDT 24
Finished Mar 14 12:27:29 PM PDT 24
Peak memory 183492 kb
Host smart-f14cfa3a-acba-4a87-8a0b-4659647b3d7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068554412 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_
all.2068554412
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.1832106293
Short name T272
Test name
Test status
Simulation time 366091475259 ps
CPU time 652.15 seconds
Started Mar 14 12:27:21 PM PDT 24
Finished Mar 14 12:38:13 PM PDT 24
Peak memory 200016 kb
Host smart-a90ab38d-8d97-40ed-9054-f45b088b3939
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832106293 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.1832106293
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.aon_timer_jump.2875664709
Short name T256
Test name
Test status
Simulation time 413771893 ps
CPU time 0.58 seconds
Started Mar 14 12:27:25 PM PDT 24
Finished Mar 14 12:27:26 PM PDT 24
Peak memory 183320 kb
Host smart-d0f3c503-5520-451c-ba71-225937b6f540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875664709 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.2875664709
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.2607322303
Short name T235
Test name
Test status
Simulation time 2101634661 ps
CPU time 3.19 seconds
Started Mar 14 12:27:21 PM PDT 24
Finished Mar 14 12:27:24 PM PDT 24
Peak memory 183332 kb
Host smart-8d24e4da-899a-436d-85b0-26d6ec52afda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607322303 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.2607322303
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.977586643
Short name T9
Test name
Test status
Simulation time 415479544 ps
CPU time 1.13 seconds
Started Mar 14 12:27:37 PM PDT 24
Finished Mar 14 12:27:38 PM PDT 24
Peak memory 183404 kb
Host smart-63d7e418-6dbb-4955-8a42-c32d2c827382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977586643 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.977586643
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.1947759817
Short name T174
Test name
Test status
Simulation time 28826916127 ps
CPU time 291.65 seconds
Started Mar 14 12:27:24 PM PDT 24
Finished Mar 14 12:32:16 PM PDT 24
Peak memory 198368 kb
Host smart-3e750325-7379-468b-981a-33a159891cc3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947759817 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.1947759817
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_jump.468274177
Short name T206
Test name
Test status
Simulation time 538611480 ps
CPU time 0.98 seconds
Started Mar 14 12:27:38 PM PDT 24
Finished Mar 14 12:27:39 PM PDT 24
Peak memory 183404 kb
Host smart-ef52c05a-b573-4308-ba16-09ddcb878171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468274177 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.468274177
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.3524780285
Short name T223
Test name
Test status
Simulation time 49972863339 ps
CPU time 20.6 seconds
Started Mar 14 12:27:44 PM PDT 24
Finished Mar 14 12:28:05 PM PDT 24
Peak memory 183452 kb
Host smart-fa1f071f-d62e-443e-b405-b5b638cd30ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524780285 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.3524780285
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.137100877
Short name T162
Test name
Test status
Simulation time 501636430 ps
CPU time 0.59 seconds
Started Mar 14 12:27:32 PM PDT 24
Finished Mar 14 12:27:33 PM PDT 24
Peak memory 183436 kb
Host smart-880f5f90-35bd-4881-b7a3-a99b33522d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137100877 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.137100877
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.1171638856
Short name T273
Test name
Test status
Simulation time 69487646142 ps
CPU time 26.21 seconds
Started Mar 14 12:27:39 PM PDT 24
Finished Mar 14 12:28:06 PM PDT 24
Peak memory 183484 kb
Host smart-3635cb49-3229-4520-9f17-11e466097411
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171638856 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_
all.1171638856
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.2293379736
Short name T270
Test name
Test status
Simulation time 62145949313 ps
CPU time 324.82 seconds
Started Mar 14 12:27:16 PM PDT 24
Finished Mar 14 12:32:41 PM PDT 24
Peak memory 198420 kb
Host smart-49e6bc54-9d51-4b94-b820-1127365ed4b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293379736 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.2293379736
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_jump.598223890
Short name T210
Test name
Test status
Simulation time 482210402 ps
CPU time 0.67 seconds
Started Mar 14 12:26:56 PM PDT 24
Finished Mar 14 12:26:56 PM PDT 24
Peak memory 183440 kb
Host smart-68a656d2-fcc4-47f8-ae44-5e98c046317e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598223890 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.598223890
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.2110522429
Short name T257
Test name
Test status
Simulation time 7554822812 ps
CPU time 3.25 seconds
Started Mar 14 12:27:24 PM PDT 24
Finished Mar 14 12:27:28 PM PDT 24
Peak memory 183488 kb
Host smart-0fd8d541-fd53-465a-8c28-f4d8e3f59187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110522429 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.2110522429
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.1267055799
Short name T54
Test name
Test status
Simulation time 524555895 ps
CPU time 1.33 seconds
Started Mar 14 12:27:11 PM PDT 24
Finished Mar 14 12:27:12 PM PDT 24
Peak memory 183440 kb
Host smart-136a56c8-3c8c-46da-95a8-0bd6073da5b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267055799 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.1267055799
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.1616906690
Short name T214
Test name
Test status
Simulation time 93651510279 ps
CPU time 138.81 seconds
Started Mar 14 12:27:40 PM PDT 24
Finished Mar 14 12:29:59 PM PDT 24
Peak memory 195156 kb
Host smart-9ff37e14-dc39-406f-8eb3-9176b7667b03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616906690 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_
all.1616906690
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.1593230085
Short name T84
Test name
Test status
Simulation time 401775951442 ps
CPU time 517.87 seconds
Started Mar 14 12:27:50 PM PDT 24
Finished Mar 14 12:36:28 PM PDT 24
Peak memory 198660 kb
Host smart-6fdd60a7-2e42-47b5-b8cb-2ea93c2cc29c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593230085 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.1593230085
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.aon_timer_jump.362290164
Short name T112
Test name
Test status
Simulation time 445311804 ps
CPU time 0.7 seconds
Started Mar 14 12:27:37 PM PDT 24
Finished Mar 14 12:27:38 PM PDT 24
Peak memory 183404 kb
Host smart-88c02126-3e3d-44f9-a32e-427ac4c97d80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362290164 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.362290164
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.2761293338
Short name T157
Test name
Test status
Simulation time 9577561882 ps
CPU time 8.43 seconds
Started Mar 14 12:27:34 PM PDT 24
Finished Mar 14 12:27:43 PM PDT 24
Peak memory 183532 kb
Host smart-b77c6309-4705-4ff4-8a04-341a698a9b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761293338 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.2761293338
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.997270429
Short name T200
Test name
Test status
Simulation time 491661732 ps
CPU time 0.73 seconds
Started Mar 14 12:27:18 PM PDT 24
Finished Mar 14 12:27:19 PM PDT 24
Peak memory 183448 kb
Host smart-c9bd41c4-d055-4edd-8bf0-4ce485a48855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997270429 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.997270429
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.1868031918
Short name T213
Test name
Test status
Simulation time 93980722535 ps
CPU time 134.02 seconds
Started Mar 14 12:27:44 PM PDT 24
Finished Mar 14 12:29:58 PM PDT 24
Peak memory 183588 kb
Host smart-9da9a67d-bd3e-417b-a8e2-ac129a5efe36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868031918 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_
all.1868031918
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.2775157216
Short name T19
Test name
Test status
Simulation time 140171681572 ps
CPU time 599.33 seconds
Started Mar 14 12:27:48 PM PDT 24
Finished Mar 14 12:37:48 PM PDT 24
Peak memory 199332 kb
Host smart-05d358e7-9bda-4cee-9f2d-b8efb39fe503
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775157216 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.2775157216
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.aon_timer_jump.2628710692
Short name T236
Test name
Test status
Simulation time 573513711 ps
CPU time 0.75 seconds
Started Mar 14 12:27:04 PM PDT 24
Finished Mar 14 12:27:05 PM PDT 24
Peak memory 183456 kb
Host smart-4e04a5dc-c54b-4707-80d9-02e8d40ea99c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628710692 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.2628710692
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.3850203077
Short name T182
Test name
Test status
Simulation time 22562111453 ps
CPU time 29.22 seconds
Started Mar 14 12:27:15 PM PDT 24
Finished Mar 14 12:27:45 PM PDT 24
Peak memory 183444 kb
Host smart-5dda5161-e2c9-4cc3-a8e6-ca935705573f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850203077 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.3850203077
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.442585659
Short name T21
Test name
Test status
Simulation time 8479770836 ps
CPU time 13.76 seconds
Started Mar 14 12:27:14 PM PDT 24
Finished Mar 14 12:27:28 PM PDT 24
Peak memory 215104 kb
Host smart-e4329c3a-fedb-43f4-91b6-c72232f58cd1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442585659 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.442585659
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.2654662259
Short name T285
Test name
Test status
Simulation time 521043026 ps
CPU time 0.94 seconds
Started Mar 14 12:27:19 PM PDT 24
Finished Mar 14 12:27:20 PM PDT 24
Peak memory 183420 kb
Host smart-15094df9-d40b-4169-931e-12c0a6f95f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654662259 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.2654662259
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.3048114029
Short name T160
Test name
Test status
Simulation time 116971368947 ps
CPU time 41.06 seconds
Started Mar 14 12:27:17 PM PDT 24
Finished Mar 14 12:27:58 PM PDT 24
Peak memory 183536 kb
Host smart-a7ff1275-ba4e-46cb-908b-bc90a5126e54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048114029 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_a
ll.3048114029
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.4086392755
Short name T37
Test name
Test status
Simulation time 170760556090 ps
CPU time 1010.99 seconds
Started Mar 14 12:26:55 PM PDT 24
Finished Mar 14 12:43:46 PM PDT 24
Peak memory 202196 kb
Host smart-0b9de82e-c877-4a1c-a12b-3517f3244afb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086392755 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.4086392755
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_jump.2312660737
Short name T232
Test name
Test status
Simulation time 524201259 ps
CPU time 0.69 seconds
Started Mar 14 12:27:30 PM PDT 24
Finished Mar 14 12:27:31 PM PDT 24
Peak memory 183392 kb
Host smart-fe3ef9ee-053f-4982-ae4f-ad624cd93615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312660737 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.2312660737
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.459867737
Short name T226
Test name
Test status
Simulation time 24475332725 ps
CPU time 7.36 seconds
Started Mar 14 12:27:22 PM PDT 24
Finished Mar 14 12:27:30 PM PDT 24
Peak memory 183448 kb
Host smart-3a5e2e4b-4d48-4f58-8950-b9a7173bf351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459867737 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.459867737
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.1892477576
Short name T7
Test name
Test status
Simulation time 539809740 ps
CPU time 0.75 seconds
Started Mar 14 12:27:43 PM PDT 24
Finished Mar 14 12:27:44 PM PDT 24
Peak memory 183448 kb
Host smart-98d98d0b-f39d-4dbc-b0c5-3d47682d231e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892477576 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.1892477576
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.2574008012
Short name T111
Test name
Test status
Simulation time 107580124572 ps
CPU time 175.09 seconds
Started Mar 14 12:27:33 PM PDT 24
Finished Mar 14 12:30:28 PM PDT 24
Peak memory 183656 kb
Host smart-920904bb-e457-4c63-9c7b-554d3de6b8af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574008012 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_
all.2574008012
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.3557063936
Short name T269
Test name
Test status
Simulation time 742597901055 ps
CPU time 866.31 seconds
Started Mar 14 12:27:20 PM PDT 24
Finished Mar 14 12:41:47 PM PDT 24
Peak memory 206580 kb
Host smart-f5c4462d-a2f2-4862-92c2-3cab443c08a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557063936 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.3557063936
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.aon_timer_jump.685170585
Short name T103
Test name
Test status
Simulation time 407577708 ps
CPU time 1.13 seconds
Started Mar 14 12:27:18 PM PDT 24
Finished Mar 14 12:27:19 PM PDT 24
Peak memory 183496 kb
Host smart-0b3c379f-10d4-4abf-b705-b9817c52fc8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685170585 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.685170585
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.3530965626
Short name T203
Test name
Test status
Simulation time 23627437456 ps
CPU time 18.41 seconds
Started Mar 14 12:27:24 PM PDT 24
Finished Mar 14 12:27:43 PM PDT 24
Peak memory 183452 kb
Host smart-bb29baf4-393d-429e-bb95-dd2da9c1d88e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530965626 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.3530965626
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.3620252347
Short name T133
Test name
Test status
Simulation time 557120855 ps
CPU time 1.26 seconds
Started Mar 14 12:27:45 PM PDT 24
Finished Mar 14 12:27:47 PM PDT 24
Peak memory 183364 kb
Host smart-8c0a2771-d9b9-47c9-b1f7-237e12ab4577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620252347 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.3620252347
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.1478698320
Short name T1
Test name
Test status
Simulation time 99537909727 ps
CPU time 12.57 seconds
Started Mar 14 12:27:22 PM PDT 24
Finished Mar 14 12:27:34 PM PDT 24
Peak memory 183464 kb
Host smart-ec1b9590-7d94-405d-b13a-01068253909f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478698320 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_
all.1478698320
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/32.aon_timer_jump.1052399366
Short name T152
Test name
Test status
Simulation time 560909025 ps
CPU time 1.49 seconds
Started Mar 14 12:27:50 PM PDT 24
Finished Mar 14 12:27:53 PM PDT 24
Peak memory 183552 kb
Host smart-8999d48a-6b9a-4d96-a7e9-4948ab9cc31b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052399366 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.1052399366
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.3881025076
Short name T248
Test name
Test status
Simulation time 10248121901 ps
CPU time 5.33 seconds
Started Mar 14 12:27:30 PM PDT 24
Finished Mar 14 12:27:35 PM PDT 24
Peak memory 183456 kb
Host smart-81084b21-8e85-4c43-b651-e2a530ae6c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881025076 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.3881025076
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.2004446872
Short name T185
Test name
Test status
Simulation time 425677936 ps
CPU time 0.69 seconds
Started Mar 14 12:27:38 PM PDT 24
Finished Mar 14 12:27:39 PM PDT 24
Peak memory 183440 kb
Host smart-db75d916-0910-45b7-8d1c-f27988ca3184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004446872 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.2004446872
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.3376401754
Short name T242
Test name
Test status
Simulation time 81074484061 ps
CPU time 56.8 seconds
Started Mar 14 12:27:40 PM PDT 24
Finished Mar 14 12:28:37 PM PDT 24
Peak memory 193944 kb
Host smart-c74e6ddc-533d-4755-b18e-8f6d02b2dcbf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376401754 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_
all.3376401754
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.368275976
Short name T161
Test name
Test status
Simulation time 123117510260 ps
CPU time 226.69 seconds
Started Mar 14 12:27:27 PM PDT 24
Finished Mar 14 12:31:13 PM PDT 24
Peak memory 198504 kb
Host smart-66c77bdf-cc01-4119-a164-2382fa942c4d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368275976 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_reset.368275976
Directory /workspace/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.aon_timer_jump.383895209
Short name T149
Test name
Test status
Simulation time 425463566 ps
CPU time 0.7 seconds
Started Mar 14 12:27:25 PM PDT 24
Finished Mar 14 12:27:26 PM PDT 24
Peak memory 183436 kb
Host smart-40919364-33d2-407d-b3fe-8e3d8728dd24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383895209 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.383895209
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.3611395376
Short name T282
Test name
Test status
Simulation time 41200903175 ps
CPU time 42.89 seconds
Started Mar 14 12:27:49 PM PDT 24
Finished Mar 14 12:28:32 PM PDT 24
Peak memory 183460 kb
Host smart-bcb8c59a-7616-4f86-827a-9dc54f2ee640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611395376 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.3611395376
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.2962594614
Short name T125
Test name
Test status
Simulation time 477891743 ps
CPU time 0.76 seconds
Started Mar 14 12:27:29 PM PDT 24
Finished Mar 14 12:27:31 PM PDT 24
Peak memory 183444 kb
Host smart-927b3343-c28f-4efd-bb9c-ab5e8fe2d146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962594614 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.2962594614
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.1652427474
Short name T12
Test name
Test status
Simulation time 172641769120 ps
CPU time 66.77 seconds
Started Mar 14 12:27:49 PM PDT 24
Finished Mar 14 12:28:57 PM PDT 24
Peak memory 193692 kb
Host smart-e07decc5-c238-43c3-803d-d9042b59be97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652427474 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_
all.1652427474
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.1248176706
Short name T57
Test name
Test status
Simulation time 149734566615 ps
CPU time 437.42 seconds
Started Mar 14 12:27:44 PM PDT 24
Finished Mar 14 12:35:02 PM PDT 24
Peak memory 198452 kb
Host smart-6b9c0e9f-d4d7-40f2-8f6a-09b6519e6b36
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248176706 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.1248176706
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.aon_timer_jump.424181292
Short name T202
Test name
Test status
Simulation time 368465969 ps
CPU time 0.66 seconds
Started Mar 14 12:27:21 PM PDT 24
Finished Mar 14 12:27:22 PM PDT 24
Peak memory 183524 kb
Host smart-a4f170d2-a65c-4aa9-bd0f-356402aa324d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424181292 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.424181292
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.2982345797
Short name T158
Test name
Test status
Simulation time 9909710663 ps
CPU time 1.53 seconds
Started Mar 14 12:27:14 PM PDT 24
Finished Mar 14 12:27:16 PM PDT 24
Peak memory 183464 kb
Host smart-adf73a8b-1fe8-4968-a29a-468ab1887ab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982345797 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.2982345797
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.593328401
Short name T222
Test name
Test status
Simulation time 466943098 ps
CPU time 1.21 seconds
Started Mar 14 12:27:15 PM PDT 24
Finished Mar 14 12:27:16 PM PDT 24
Peak memory 183540 kb
Host smart-b0eba381-814f-408b-b8d3-db6ec1bd6874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593328401 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.593328401
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.1327706894
Short name T261
Test name
Test status
Simulation time 305121816616 ps
CPU time 48.76 seconds
Started Mar 14 12:27:17 PM PDT 24
Finished Mar 14 12:28:06 PM PDT 24
Peak memory 183544 kb
Host smart-23700114-0b61-4d75-9660-b49750f28a7b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327706894 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_
all.1327706894
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.967406277
Short name T227
Test name
Test status
Simulation time 174203395852 ps
CPU time 344.42 seconds
Started Mar 14 12:27:26 PM PDT 24
Finished Mar 14 12:33:11 PM PDT 24
Peak memory 198556 kb
Host smart-c2d1e8de-2e33-48f1-8ae5-4f131c6a186f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967406277 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.967406277
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.aon_timer_jump.2043494284
Short name T238
Test name
Test status
Simulation time 550819833 ps
CPU time 1.47 seconds
Started Mar 14 12:27:29 PM PDT 24
Finished Mar 14 12:27:31 PM PDT 24
Peak memory 183484 kb
Host smart-57025b5a-a2b2-4fd6-a4cc-d040dc41fd44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043494284 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.2043494284
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.289910112
Short name T277
Test name
Test status
Simulation time 29896895650 ps
CPU time 41.55 seconds
Started Mar 14 12:27:15 PM PDT 24
Finished Mar 14 12:27:57 PM PDT 24
Peak memory 183444 kb
Host smart-f75d15b8-025a-467e-9a81-f469a2615034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289910112 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.289910112
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.1241428460
Short name T167
Test name
Test status
Simulation time 463107939 ps
CPU time 1.14 seconds
Started Mar 14 12:27:20 PM PDT 24
Finished Mar 14 12:27:21 PM PDT 24
Peak memory 183428 kb
Host smart-d468949d-340d-430f-9225-2173262d53db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241428460 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.1241428460
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.3696954568
Short name T250
Test name
Test status
Simulation time 238024051645 ps
CPU time 39.92 seconds
Started Mar 14 12:27:46 PM PDT 24
Finished Mar 14 12:28:26 PM PDT 24
Peak memory 183680 kb
Host smart-47b6cec8-bd43-484e-9457-085a7767a9f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696954568 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_
all.3696954568
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.4239944063
Short name T179
Test name
Test status
Simulation time 115646073890 ps
CPU time 654.9 seconds
Started Mar 14 12:27:25 PM PDT 24
Finished Mar 14 12:38:20 PM PDT 24
Peak memory 200800 kb
Host smart-98da130c-e5c0-48b6-abae-5cae4987f25f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239944063 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.4239944063
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.aon_timer_jump.3736483597
Short name T284
Test name
Test status
Simulation time 521565660 ps
CPU time 1.34 seconds
Started Mar 14 12:27:31 PM PDT 24
Finished Mar 14 12:27:33 PM PDT 24
Peak memory 183484 kb
Host smart-c8c8447d-6760-4d0d-befe-47f7f83e01fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736483597 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.3736483597
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.1240936290
Short name T193
Test name
Test status
Simulation time 18140042702 ps
CPU time 26.01 seconds
Started Mar 14 12:27:42 PM PDT 24
Finished Mar 14 12:28:09 PM PDT 24
Peak memory 183456 kb
Host smart-24d183c8-8647-485e-aa81-76ac5076f87b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240936290 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.1240936290
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.657604708
Short name T155
Test name
Test status
Simulation time 516633408 ps
CPU time 0.72 seconds
Started Mar 14 12:27:45 PM PDT 24
Finished Mar 14 12:27:47 PM PDT 24
Peak memory 183380 kb
Host smart-79aa7f74-2f32-400d-b06c-13b9ed65e358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657604708 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.657604708
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.1524841270
Short name T143
Test name
Test status
Simulation time 211711370022 ps
CPU time 307.2 seconds
Started Mar 14 12:27:43 PM PDT 24
Finished Mar 14 12:32:50 PM PDT 24
Peak memory 195136 kb
Host smart-81aca365-95e8-4239-a5ff-96325c0f9e8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524841270 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_
all.1524841270
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.1069551916
Short name T180
Test name
Test status
Simulation time 88561740988 ps
CPU time 317.21 seconds
Started Mar 14 12:27:26 PM PDT 24
Finished Mar 14 12:32:48 PM PDT 24
Peak memory 198420 kb
Host smart-143f0eb4-ac9d-4d9a-bc3a-d7bdfa922062
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069551916 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.1069551916
Directory /workspace/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.aon_timer_jump.217990359
Short name T264
Test name
Test status
Simulation time 585814605 ps
CPU time 0.79 seconds
Started Mar 14 12:27:42 PM PDT 24
Finished Mar 14 12:27:43 PM PDT 24
Peak memory 183328 kb
Host smart-1f471e41-8ae5-4756-997a-f211d74d6f33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217990359 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.217990359
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.3183967969
Short name T150
Test name
Test status
Simulation time 12021005725 ps
CPU time 3.62 seconds
Started Mar 14 12:27:23 PM PDT 24
Finished Mar 14 12:27:27 PM PDT 24
Peak memory 183504 kb
Host smart-758d0fff-3359-4339-b8e9-80aaf1460c22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183967969 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.3183967969
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.330666220
Short name T97
Test name
Test status
Simulation time 442697778 ps
CPU time 0.69 seconds
Started Mar 14 12:27:27 PM PDT 24
Finished Mar 14 12:27:28 PM PDT 24
Peak memory 183448 kb
Host smart-d8dfb31a-d2e6-458e-8c7d-f25d1edc1958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330666220 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.330666220
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.4009924173
Short name T123
Test name
Test status
Simulation time 90356820842 ps
CPU time 137.08 seconds
Started Mar 14 12:27:40 PM PDT 24
Finished Mar 14 12:29:57 PM PDT 24
Peak memory 195036 kb
Host smart-8ad4aee3-6c9d-4e7f-be63-ab1f67b46b06
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009924173 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_
all.4009924173
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.853691231
Short name T253
Test name
Test status
Simulation time 91157345336 ps
CPU time 1015.83 seconds
Started Mar 14 12:27:16 PM PDT 24
Finished Mar 14 12:44:12 PM PDT 24
Peak memory 214308 kb
Host smart-3d27b5e3-c98e-4b56-bb18-92da20f7f730
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853691231 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.853691231
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.aon_timer_jump.2287591789
Short name T119
Test name
Test status
Simulation time 352485161 ps
CPU time 1.17 seconds
Started Mar 14 12:27:31 PM PDT 24
Finished Mar 14 12:27:32 PM PDT 24
Peak memory 183424 kb
Host smart-dfb88679-43ed-43f8-b30c-ca43de88d0cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287591789 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.2287591789
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.2060233
Short name T216
Test name
Test status
Simulation time 2783304995 ps
CPU time 1.54 seconds
Started Mar 14 12:27:31 PM PDT 24
Finished Mar 14 12:27:32 PM PDT 24
Peak memory 183552 kb
Host smart-77788fc5-658b-4463-aa2f-ab8c5ba8c2ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060233 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.2060233
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.3567891388
Short name T234
Test name
Test status
Simulation time 531448115 ps
CPU time 0.73 seconds
Started Mar 14 12:27:21 PM PDT 24
Finished Mar 14 12:27:22 PM PDT 24
Peak memory 183404 kb
Host smart-945eb33b-7897-4402-82d9-c9b02b4d2b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567891388 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.3567891388
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.2904736577
Short name T115
Test name
Test status
Simulation time 452739554546 ps
CPU time 176.53 seconds
Started Mar 14 12:27:25 PM PDT 24
Finished Mar 14 12:30:22 PM PDT 24
Peak memory 191744 kb
Host smart-0047908b-72dc-4fb0-bf9d-95c57719199e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904736577 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_
all.2904736577
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_jump.1846402271
Short name T240
Test name
Test status
Simulation time 353145017 ps
CPU time 0.69 seconds
Started Mar 14 12:27:22 PM PDT 24
Finished Mar 14 12:27:23 PM PDT 24
Peak memory 183396 kb
Host smart-fd3a2b7a-a341-4dcd-8009-029eadd381f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846402271 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.1846402271
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.404434068
Short name T147
Test name
Test status
Simulation time 25099791682 ps
CPU time 8.57 seconds
Started Mar 14 12:27:43 PM PDT 24
Finished Mar 14 12:27:52 PM PDT 24
Peak memory 183432 kb
Host smart-c6b22dad-b2b9-4d15-8ba9-edba47aaa318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404434068 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.404434068
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.3867316148
Short name T5
Test name
Test status
Simulation time 589523744 ps
CPU time 1.36 seconds
Started Mar 14 12:27:20 PM PDT 24
Finished Mar 14 12:27:22 PM PDT 24
Peak memory 183520 kb
Host smart-15b71867-301b-4691-ae09-ebf5eaf8d587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867316148 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.3867316148
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.1281506612
Short name T14
Test name
Test status
Simulation time 6180165883 ps
CPU time 5.46 seconds
Started Mar 14 12:27:39 PM PDT 24
Finished Mar 14 12:27:44 PM PDT 24
Peak memory 183580 kb
Host smart-adbe9cf6-6391-47e9-af64-f09c3fc13de7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281506612 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_
all.1281506612
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.1543480453
Short name T82
Test name
Test status
Simulation time 321326315521 ps
CPU time 632.01 seconds
Started Mar 14 12:27:28 PM PDT 24
Finished Mar 14 12:38:01 PM PDT 24
Peak memory 200028 kb
Host smart-5eda08fa-b439-4716-8a5b-79ad8e7e2df4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543480453 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.1543480453
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_jump.2193096510
Short name T168
Test name
Test status
Simulation time 351832285 ps
CPU time 0.66 seconds
Started Mar 14 12:27:24 PM PDT 24
Finished Mar 14 12:27:25 PM PDT 24
Peak memory 183540 kb
Host smart-86962f7d-d674-4f36-a4c7-776f4c83eb3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193096510 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.2193096510
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.1952957783
Short name T148
Test name
Test status
Simulation time 43692897620 ps
CPU time 18.23 seconds
Started Mar 14 12:27:29 PM PDT 24
Finished Mar 14 12:27:47 PM PDT 24
Peak memory 183480 kb
Host smart-724d5f38-91d4-4c8e-affc-b91f45c08c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952957783 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.1952957783
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.4242773782
Short name T24
Test name
Test status
Simulation time 4527899066 ps
CPU time 2.32 seconds
Started Mar 14 12:27:20 PM PDT 24
Finished Mar 14 12:27:23 PM PDT 24
Peak memory 215072 kb
Host smart-8acb40b3-cacd-438b-9778-a7408cb3a6c1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242773782 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.4242773782
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.3277030669
Short name T146
Test name
Test status
Simulation time 439872610 ps
CPU time 0.78 seconds
Started Mar 14 12:27:29 PM PDT 24
Finished Mar 14 12:27:30 PM PDT 24
Peak memory 183420 kb
Host smart-2b299c35-90e8-480b-8f1b-66e3d3d22274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277030669 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.3277030669
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.781215697
Short name T18
Test name
Test status
Simulation time 341219524220 ps
CPU time 125.85 seconds
Started Mar 14 12:27:17 PM PDT 24
Finished Mar 14 12:29:23 PM PDT 24
Peak memory 193600 kb
Host smart-fe49be64-fe8c-48ea-be95-e15cec80e772
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781215697 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_al
l.781215697
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.2865966764
Short name T237
Test name
Test status
Simulation time 42764292065 ps
CPU time 313.38 seconds
Started Mar 14 12:26:56 PM PDT 24
Finished Mar 14 12:32:10 PM PDT 24
Peak memory 198444 kb
Host smart-55208d2f-0fcc-4bf3-b5e6-81b390b3e93c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865966764 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.2865966764
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.aon_timer_jump.3305111991
Short name T4
Test name
Test status
Simulation time 571336073 ps
CPU time 1.36 seconds
Started Mar 14 12:27:41 PM PDT 24
Finished Mar 14 12:27:42 PM PDT 24
Peak memory 183456 kb
Host smart-a1163b0d-b07b-4226-a20e-c3f3a3bbd8f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305111991 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.3305111991
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.384781995
Short name T105
Test name
Test status
Simulation time 26259397794 ps
CPU time 8.62 seconds
Started Mar 14 12:27:13 PM PDT 24
Finished Mar 14 12:27:22 PM PDT 24
Peak memory 183532 kb
Host smart-27028500-ccd5-42eb-b751-5e4d5766fe04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384781995 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.384781995
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.3438984990
Short name T286
Test name
Test status
Simulation time 489810981 ps
CPU time 0.74 seconds
Started Mar 14 12:27:37 PM PDT 24
Finished Mar 14 12:27:38 PM PDT 24
Peak memory 183524 kb
Host smart-38c92172-98e7-4618-a91b-4ddf4f6618a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438984990 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.3438984990
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.3936736153
Short name T198
Test name
Test status
Simulation time 138301983781 ps
CPU time 199.58 seconds
Started Mar 14 12:27:29 PM PDT 24
Finished Mar 14 12:30:48 PM PDT 24
Peak memory 194956 kb
Host smart-86936b73-e68a-43e7-9ead-df99eacede5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936736153 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_
all.3936736153
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.540620075
Short name T201
Test name
Test status
Simulation time 25109903688 ps
CPU time 249.16 seconds
Started Mar 14 12:27:46 PM PDT 24
Finished Mar 14 12:31:55 PM PDT 24
Peak memory 198544 kb
Host smart-b6a8b432-582d-4094-9b58-0e2fe6792bc8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540620075 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.540620075
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.aon_timer_jump.3818807435
Short name T171
Test name
Test status
Simulation time 502487442 ps
CPU time 0.92 seconds
Started Mar 14 12:27:27 PM PDT 24
Finished Mar 14 12:27:28 PM PDT 24
Peak memory 183516 kb
Host smart-e060dc56-cee9-474a-aa74-1ee323de249b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818807435 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.3818807435
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.1856455409
Short name T246
Test name
Test status
Simulation time 4463657575 ps
CPU time 2.14 seconds
Started Mar 14 12:27:30 PM PDT 24
Finished Mar 14 12:27:32 PM PDT 24
Peak memory 183480 kb
Host smart-951bf570-2126-4c89-9c17-8d7ac021cb0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856455409 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.1856455409
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.2846879713
Short name T118
Test name
Test status
Simulation time 455141799 ps
CPU time 1.23 seconds
Started Mar 14 12:27:36 PM PDT 24
Finished Mar 14 12:27:38 PM PDT 24
Peak memory 183468 kb
Host smart-45f53fef-cbfa-4fdc-b936-bd6beae4c418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846879713 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.2846879713
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.392009755
Short name T52
Test name
Test status
Simulation time 139174259346 ps
CPU time 218.37 seconds
Started Mar 14 12:27:26 PM PDT 24
Finished Mar 14 12:31:04 PM PDT 24
Peak memory 183560 kb
Host smart-e3282651-4d87-4c92-9556-6d63560dc4ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392009755 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_a
ll.392009755
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.2962212406
Short name T154
Test name
Test status
Simulation time 44525517641 ps
CPU time 344.18 seconds
Started Mar 14 12:27:49 PM PDT 24
Finished Mar 14 12:33:34 PM PDT 24
Peak memory 198444 kb
Host smart-b923a604-e864-4c3a-a339-f99a1646c056
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962212406 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.2962212406
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.aon_timer_jump.2241890132
Short name T186
Test name
Test status
Simulation time 572586545 ps
CPU time 0.73 seconds
Started Mar 14 12:27:17 PM PDT 24
Finished Mar 14 12:27:18 PM PDT 24
Peak memory 183396 kb
Host smart-e48aa060-2c86-4a5d-9b32-3c5c8bf69521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241890132 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.2241890132
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.2964179390
Short name T209
Test name
Test status
Simulation time 23890519021 ps
CPU time 31.86 seconds
Started Mar 14 12:27:31 PM PDT 24
Finished Mar 14 12:28:03 PM PDT 24
Peak memory 183624 kb
Host smart-e7ecc309-7c47-4959-a7c7-517a645f5c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964179390 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.2964179390
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.3004830615
Short name T49
Test name
Test status
Simulation time 458582836 ps
CPU time 0.71 seconds
Started Mar 14 12:27:29 PM PDT 24
Finished Mar 14 12:27:30 PM PDT 24
Peak memory 183560 kb
Host smart-733e7d90-fa39-435d-8412-f73dc2e550c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004830615 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.3004830615
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.4191865670
Short name T259
Test name
Test status
Simulation time 243862022373 ps
CPU time 395.18 seconds
Started Mar 14 12:27:34 PM PDT 24
Finished Mar 14 12:34:09 PM PDT 24
Peak memory 183668 kb
Host smart-e65a438b-e6b5-4a05-8dfa-0f66bd08b307
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191865670 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_
all.4191865670
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_jump.1060117904
Short name T102
Test name
Test status
Simulation time 439522168 ps
CPU time 1.21 seconds
Started Mar 14 12:27:18 PM PDT 24
Finished Mar 14 12:27:19 PM PDT 24
Peak memory 183452 kb
Host smart-97cc16b5-c81e-474d-88e4-3fa1d2f6e7f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060117904 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.1060117904
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.1198817034
Short name T220
Test name
Test status
Simulation time 26065357718 ps
CPU time 36.54 seconds
Started Mar 14 12:27:18 PM PDT 24
Finished Mar 14 12:27:54 PM PDT 24
Peak memory 183548 kb
Host smart-c28faa62-b0d0-4bb3-a512-edea25cabf28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198817034 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.1198817034
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.3969569238
Short name T258
Test name
Test status
Simulation time 510670895 ps
CPU time 0.74 seconds
Started Mar 14 12:27:29 PM PDT 24
Finished Mar 14 12:27:30 PM PDT 24
Peak memory 183392 kb
Host smart-70a1c0d6-118d-4a77-a53b-4651aefbbbcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969569238 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.3969569238
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.3354140679
Short name T207
Test name
Test status
Simulation time 73547556861 ps
CPU time 7.08 seconds
Started Mar 14 12:27:15 PM PDT 24
Finished Mar 14 12:27:22 PM PDT 24
Peak memory 183516 kb
Host smart-cae441f4-b94b-4eaf-bb95-a224bf71813d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354140679 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_
all.3354140679
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.3836879225
Short name T42
Test name
Test status
Simulation time 142356885468 ps
CPU time 214.53 seconds
Started Mar 14 12:27:41 PM PDT 24
Finished Mar 14 12:31:16 PM PDT 24
Peak memory 198504 kb
Host smart-30a886bf-ed67-4002-850b-78306cbd1aad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836879225 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.3836879225
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.aon_timer_jump.624410179
Short name T218
Test name
Test status
Simulation time 405817642 ps
CPU time 0.87 seconds
Started Mar 14 12:27:29 PM PDT 24
Finished Mar 14 12:27:30 PM PDT 24
Peak memory 183404 kb
Host smart-fa1142bd-942e-44d0-849f-889f65b25758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624410179 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.624410179
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.613358155
Short name T108
Test name
Test status
Simulation time 2871555151 ps
CPU time 3.47 seconds
Started Mar 14 12:27:35 PM PDT 24
Finished Mar 14 12:27:39 PM PDT 24
Peak memory 183488 kb
Host smart-65c609d0-1cf6-4d94-b4b6-624649435f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613358155 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.613358155
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.2077211254
Short name T249
Test name
Test status
Simulation time 609935429 ps
CPU time 0.65 seconds
Started Mar 14 12:27:42 PM PDT 24
Finished Mar 14 12:27:43 PM PDT 24
Peak memory 183404 kb
Host smart-9f67cfee-574f-4f00-9dc0-1a728196e9db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077211254 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.2077211254
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.1029658824
Short name T279
Test name
Test status
Simulation time 65531155352 ps
CPU time 27.7 seconds
Started Mar 14 12:27:18 PM PDT 24
Finished Mar 14 12:27:46 PM PDT 24
Peak memory 183488 kb
Host smart-b92f1ef4-ec98-4258-999a-2372cee57d1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029658824 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_
all.1029658824
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_jump.569260637
Short name T164
Test name
Test status
Simulation time 404588066 ps
CPU time 0.83 seconds
Started Mar 14 12:27:43 PM PDT 24
Finished Mar 14 12:27:44 PM PDT 24
Peak memory 183436 kb
Host smart-1837b43e-4351-41a4-a501-beab93eaa4da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569260637 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.569260637
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.2442476500
Short name T178
Test name
Test status
Simulation time 19327055890 ps
CPU time 16.57 seconds
Started Mar 14 12:27:29 PM PDT 24
Finished Mar 14 12:27:46 PM PDT 24
Peak memory 183580 kb
Host smart-ff5b77be-f426-42a1-9975-b997494fa240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442476500 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.2442476500
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.3280945794
Short name T100
Test name
Test status
Simulation time 491865295 ps
CPU time 0.61 seconds
Started Mar 14 12:27:18 PM PDT 24
Finished Mar 14 12:27:19 PM PDT 24
Peak memory 183388 kb
Host smart-0c677f71-5190-4915-b3f4-52f9363363bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280945794 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.3280945794
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.4004540986
Short name T191
Test name
Test status
Simulation time 204305126090 ps
CPU time 149.12 seconds
Started Mar 14 12:27:35 PM PDT 24
Finished Mar 14 12:30:04 PM PDT 24
Peak memory 195248 kb
Host smart-28c606c5-d5f6-4aa0-ad42-696a8d642b7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004540986 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_
all.4004540986
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.2751596142
Short name T39
Test name
Test status
Simulation time 32213053579 ps
CPU time 64.01 seconds
Started Mar 14 12:27:22 PM PDT 24
Finished Mar 14 12:28:27 PM PDT 24
Peak memory 198420 kb
Host smart-71b139b9-fbae-4777-be48-2790e3e6b798
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751596142 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.2751596142
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.aon_timer_jump.33601541
Short name T271
Test name
Test status
Simulation time 372413501 ps
CPU time 0.85 seconds
Started Mar 14 12:27:34 PM PDT 24
Finished Mar 14 12:27:35 PM PDT 24
Peak memory 183420 kb
Host smart-33ae5f94-c2be-4852-89b2-01a02882c541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33601541 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.33601541
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.2321599012
Short name T263
Test name
Test status
Simulation time 3160877628 ps
CPU time 1.79 seconds
Started Mar 14 12:27:44 PM PDT 24
Finished Mar 14 12:27:46 PM PDT 24
Peak memory 183476 kb
Host smart-f15e4746-b624-440f-8141-f4b978d23b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321599012 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.2321599012
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.2370168823
Short name T117
Test name
Test status
Simulation time 600364353 ps
CPU time 0.74 seconds
Started Mar 14 12:27:29 PM PDT 24
Finished Mar 14 12:27:30 PM PDT 24
Peak memory 183560 kb
Host smart-15f449cd-021f-4bf0-ba6a-4b2e894fca60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370168823 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.2370168823
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.1007313843
Short name T176
Test name
Test status
Simulation time 62427269809 ps
CPU time 22.13 seconds
Started Mar 14 12:27:44 PM PDT 24
Finished Mar 14 12:28:06 PM PDT 24
Peak memory 193976 kb
Host smart-36c1f293-e892-4e69-99e9-be4c4f47add6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007313843 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_
all.1007313843
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.3591799795
Short name T231
Test name
Test status
Simulation time 529539467220 ps
CPU time 403.64 seconds
Started Mar 14 12:27:30 PM PDT 24
Finished Mar 14 12:34:13 PM PDT 24
Peak memory 198556 kb
Host smart-ea3b4f3d-1ecb-4382-953f-b2b13386cc6c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591799795 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.3591799795
Directory /workspace/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.aon_timer_jump.3413298099
Short name T244
Test name
Test status
Simulation time 516511931 ps
CPU time 0.77 seconds
Started Mar 14 12:27:22 PM PDT 24
Finished Mar 14 12:27:23 PM PDT 24
Peak memory 183436 kb
Host smart-27c6f671-6983-4509-a40d-7aa207645d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413298099 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.3413298099
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.830565814
Short name T205
Test name
Test status
Simulation time 46648715488 ps
CPU time 18.35 seconds
Started Mar 14 12:27:39 PM PDT 24
Finished Mar 14 12:27:58 PM PDT 24
Peak memory 183464 kb
Host smart-dbcea988-dbd2-4e52-a549-537b6648f8c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830565814 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.830565814
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.3341524513
Short name T51
Test name
Test status
Simulation time 572368796 ps
CPU time 0.98 seconds
Started Mar 14 12:27:24 PM PDT 24
Finished Mar 14 12:27:25 PM PDT 24
Peak memory 183392 kb
Host smart-0084c553-8218-4c42-b963-2ce96441a890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341524513 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.3341524513
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.4259117250
Short name T44
Test name
Test status
Simulation time 349674514509 ps
CPU time 562.57 seconds
Started Mar 14 12:27:35 PM PDT 24
Finished Mar 14 12:36:58 PM PDT 24
Peak memory 194848 kb
Host smart-3f4e287e-90f6-427d-888e-59062e22da83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259117250 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_
all.4259117250
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.1232506624
Short name T276
Test name
Test status
Simulation time 335093040641 ps
CPU time 199.59 seconds
Started Mar 14 12:27:40 PM PDT 24
Finished Mar 14 12:30:59 PM PDT 24
Peak memory 206768 kb
Host smart-5432273b-4e42-4f4b-b2d6-d364acca4df2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232506624 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.1232506624
Directory /workspace/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_jump.1658451494
Short name T260
Test name
Test status
Simulation time 495333256 ps
CPU time 0.71 seconds
Started Mar 14 12:27:40 PM PDT 24
Finished Mar 14 12:27:41 PM PDT 24
Peak memory 183524 kb
Host smart-e97a1bcd-34c0-44ce-a7fc-8e45172b46cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658451494 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.1658451494
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.1499346316
Short name T132
Test name
Test status
Simulation time 49517236384 ps
CPU time 35.61 seconds
Started Mar 14 12:27:33 PM PDT 24
Finished Mar 14 12:28:14 PM PDT 24
Peak memory 183516 kb
Host smart-9d700926-a18a-49c2-8da0-b9a21e1a4b78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499346316 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.1499346316
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.908921338
Short name T106
Test name
Test status
Simulation time 501229979 ps
CPU time 0.64 seconds
Started Mar 14 12:27:44 PM PDT 24
Finished Mar 14 12:27:45 PM PDT 24
Peak memory 183388 kb
Host smart-c114f8aa-0247-41b1-a935-78fcf9715752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908921338 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.908921338
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.3643279800
Short name T172
Test name
Test status
Simulation time 179938612606 ps
CPU time 256.31 seconds
Started Mar 14 12:27:24 PM PDT 24
Finished Mar 14 12:31:41 PM PDT 24
Peak memory 195100 kb
Host smart-14291e9e-6e1a-415c-8568-5783fcfabf3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643279800 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_
all.3643279800
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.1393533010
Short name T170
Test name
Test status
Simulation time 40579638649 ps
CPU time 326.91 seconds
Started Mar 14 12:27:47 PM PDT 24
Finished Mar 14 12:33:14 PM PDT 24
Peak memory 198516 kb
Host smart-50078aca-12b2-4611-88a2-c68a865be518
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393533010 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.1393533010
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.aon_timer_jump.367042792
Short name T140
Test name
Test status
Simulation time 518531019 ps
CPU time 1.36 seconds
Started Mar 14 12:27:39 PM PDT 24
Finished Mar 14 12:27:41 PM PDT 24
Peak memory 183436 kb
Host smart-8b94e0bf-efc9-45f3-8736-870c543647e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367042792 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.367042792
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.1854465895
Short name T189
Test name
Test status
Simulation time 16678447422 ps
CPU time 7.64 seconds
Started Mar 14 12:27:59 PM PDT 24
Finished Mar 14 12:28:07 PM PDT 24
Peak memory 183536 kb
Host smart-5ba58a76-e531-4160-80ef-b9d02ed88b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854465895 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.1854465895
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.1650709799
Short name T225
Test name
Test status
Simulation time 549335822 ps
CPU time 1.37 seconds
Started Mar 14 12:27:47 PM PDT 24
Finished Mar 14 12:27:49 PM PDT 24
Peak memory 183400 kb
Host smart-943b295f-43bd-4f12-8865-fbd934e86057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650709799 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.1650709799
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.1864642926
Short name T228
Test name
Test status
Simulation time 4281697961 ps
CPU time 6.55 seconds
Started Mar 14 12:27:30 PM PDT 24
Finished Mar 14 12:27:37 PM PDT 24
Peak memory 183460 kb
Host smart-913e8722-b0c8-4b29-86d4-b0ef9cce3f2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864642926 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_
all.1864642926
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_jump.4178976928
Short name T211
Test name
Test status
Simulation time 434123332 ps
CPU time 0.93 seconds
Started Mar 14 12:27:16 PM PDT 24
Finished Mar 14 12:27:17 PM PDT 24
Peak memory 183464 kb
Host smart-ef4f69d8-06c6-46b0-a3f6-ffc736a2789b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178976928 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.4178976928
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.3479063285
Short name T110
Test name
Test status
Simulation time 28735885057 ps
CPU time 39.78 seconds
Started Mar 14 12:27:04 PM PDT 24
Finished Mar 14 12:27:44 PM PDT 24
Peak memory 183540 kb
Host smart-b7134231-1f95-429f-a3c2-3e46855f89da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479063285 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.3479063285
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.403809315
Short name T48
Test name
Test status
Simulation time 462836768 ps
CPU time 1.21 seconds
Started Mar 14 12:27:16 PM PDT 24
Finished Mar 14 12:27:17 PM PDT 24
Peak memory 183476 kb
Host smart-eae424f4-4d38-431f-bfc0-798975d67623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403809315 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.403809315
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.2370873981
Short name T163
Test name
Test status
Simulation time 124908746459 ps
CPU time 189.44 seconds
Started Mar 14 12:27:14 PM PDT 24
Finished Mar 14 12:30:24 PM PDT 24
Peak memory 195312 kb
Host smart-3be720b9-9e7e-4ac0-aec9-14706a3486f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370873981 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_a
ll.2370873981
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.2916208585
Short name T20
Test name
Test status
Simulation time 75104536691 ps
CPU time 403.99 seconds
Started Mar 14 12:27:14 PM PDT 24
Finished Mar 14 12:33:58 PM PDT 24
Peak memory 198504 kb
Host smart-57fc83bd-837d-490e-a5ed-a6c70b62e4b6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916208585 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.2916208585
Directory /workspace/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.aon_timer_jump.752125483
Short name T219
Test name
Test status
Simulation time 595062630 ps
CPU time 1.42 seconds
Started Mar 14 12:27:10 PM PDT 24
Finished Mar 14 12:27:12 PM PDT 24
Peak memory 183436 kb
Host smart-d2e787f1-1279-45c4-983a-d43e308b7a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752125483 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.752125483
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.2874423918
Short name T159
Test name
Test status
Simulation time 54750484093 ps
CPU time 84.08 seconds
Started Mar 14 12:27:15 PM PDT 24
Finished Mar 14 12:28:39 PM PDT 24
Peak memory 183448 kb
Host smart-325cbe79-9385-4313-9439-2aa31bec4fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874423918 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.2874423918
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.2010495262
Short name T287
Test name
Test status
Simulation time 492217697 ps
CPU time 0.73 seconds
Started Mar 14 12:27:38 PM PDT 24
Finished Mar 14 12:27:39 PM PDT 24
Peak memory 183492 kb
Host smart-4a92154e-a827-4595-b5d6-e819b48e2533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010495262 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.2010495262
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.2250879945
Short name T45
Test name
Test status
Simulation time 30693839088 ps
CPU time 47.12 seconds
Started Mar 14 12:27:22 PM PDT 24
Finished Mar 14 12:28:09 PM PDT 24
Peak memory 183548 kb
Host smart-2f370059-e38a-43fb-8e5b-5019a5f61019
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250879945 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_a
ll.2250879945
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.2617718775
Short name T169
Test name
Test status
Simulation time 264394275559 ps
CPU time 755.71 seconds
Started Mar 14 12:27:11 PM PDT 24
Finished Mar 14 12:39:47 PM PDT 24
Peak memory 202312 kb
Host smart-b3d6357c-be06-4c89-b426-103531aaecea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617718775 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.2617718775
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.aon_timer_jump.2871028950
Short name T252
Test name
Test status
Simulation time 520025186 ps
CPU time 0.73 seconds
Started Mar 14 12:27:29 PM PDT 24
Finished Mar 14 12:27:30 PM PDT 24
Peak memory 183424 kb
Host smart-b2d3a600-0a49-4c69-ada1-fa736ad74bfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871028950 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.2871028950
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.4085305515
Short name T188
Test name
Test status
Simulation time 24843977058 ps
CPU time 17.91 seconds
Started Mar 14 12:26:54 PM PDT 24
Finished Mar 14 12:27:12 PM PDT 24
Peak memory 183492 kb
Host smart-780e96bc-582b-4fb2-9800-e3f2b2309dc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085305515 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.4085305515
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.979124815
Short name T56
Test name
Test status
Simulation time 519887978 ps
CPU time 0.75 seconds
Started Mar 14 12:27:29 PM PDT 24
Finished Mar 14 12:27:30 PM PDT 24
Peak memory 183572 kb
Host smart-894d05d7-2278-43c7-8726-73fef442da74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979124815 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.979124815
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.2144767856
Short name T245
Test name
Test status
Simulation time 241132650829 ps
CPU time 401.78 seconds
Started Mar 14 12:27:21 PM PDT 24
Finished Mar 14 12:34:08 PM PDT 24
Peak memory 183548 kb
Host smart-b7c41b35-cba4-4be5-9928-1f28e27f4548
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144767856 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_a
ll.2144767856
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_jump.912999609
Short name T99
Test name
Test status
Simulation time 416600852 ps
CPU time 0.69 seconds
Started Mar 14 12:26:53 PM PDT 24
Finished Mar 14 12:26:54 PM PDT 24
Peak memory 183496 kb
Host smart-76f8ca8c-a2ee-417d-b3e4-20818ba8de53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912999609 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.912999609
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.2069412797
Short name T229
Test name
Test status
Simulation time 18433565399 ps
CPU time 28.2 seconds
Started Mar 14 12:27:08 PM PDT 24
Finished Mar 14 12:27:37 PM PDT 24
Peak memory 183432 kb
Host smart-622cdfa8-b405-4b0d-9a51-11c4da430e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069412797 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.2069412797
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.232157188
Short name T195
Test name
Test status
Simulation time 609037578 ps
CPU time 0.75 seconds
Started Mar 14 12:27:00 PM PDT 24
Finished Mar 14 12:27:00 PM PDT 24
Peak memory 183364 kb
Host smart-f3b3546a-114a-4e83-85d0-44a1d6283a2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232157188 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.232157188
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.4062329685
Short name T116
Test name
Test status
Simulation time 123005293604 ps
CPU time 92.18 seconds
Started Mar 14 12:26:56 PM PDT 24
Finished Mar 14 12:28:28 PM PDT 24
Peak memory 195040 kb
Host smart-5fd3ec85-647a-4118-9f87-fe894306a71a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062329685 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_a
ll.4062329685
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_jump.525769861
Short name T27
Test name
Test status
Simulation time 572567311 ps
CPU time 0.81 seconds
Started Mar 14 12:26:56 PM PDT 24
Finished Mar 14 12:26:56 PM PDT 24
Peak memory 183456 kb
Host smart-3cdda007-6783-4186-a36d-9797d043e2ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525769861 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.525769861
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.533625260
Short name T126
Test name
Test status
Simulation time 17043503017 ps
CPU time 13.91 seconds
Started Mar 14 12:27:33 PM PDT 24
Finished Mar 14 12:27:47 PM PDT 24
Peak memory 183612 kb
Host smart-a4e35396-072f-4345-bb94-5c2ab3828fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533625260 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.533625260
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.2117834261
Short name T194
Test name
Test status
Simulation time 388198458 ps
CPU time 0.67 seconds
Started Mar 14 12:27:39 PM PDT 24
Finished Mar 14 12:27:40 PM PDT 24
Peak memory 183396 kb
Host smart-9b8067d1-bbbb-4fdd-93ac-449bd6aded68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117834261 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.2117834261
Directory /workspace/9.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.2958618419
Short name T173
Test name
Test status
Simulation time 253063707389 ps
CPU time 340.84 seconds
Started Mar 14 12:27:15 PM PDT 24
Finished Mar 14 12:32:56 PM PDT 24
Peak memory 194248 kb
Host smart-a328f7da-6b1f-4249-bc80-7843c302260e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958618419 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_a
ll.2958618419
Directory /workspace/9.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.3522902027
Short name T266
Test name
Test status
Simulation time 89739661280 ps
CPU time 230.08 seconds
Started Mar 14 12:26:55 PM PDT 24
Finished Mar 14 12:30:45 PM PDT 24
Peak memory 198456 kb
Host smart-28d6c32b-a19f-4d99-9020-93fd77af951a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522902027 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.3522902027
Directory /workspace/9.aon_timer_stress_all_with_rand_reset/latest
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