Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
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Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
25.43 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv


Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 173 129 44 25.43


Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
bark_thold_cp 34 32 2 5.88 100 1 1 0
bite_thold_cp 34 32 2 5.88 100 1 1 0
pause_in_sleep_cp 2 1 1 50.00 100 1 1 2
prescale_cp 34 0 34 100.00 100 1 1 0
wdog_regwen_cp 2 0 2 100.00 100 1 1 2
wkup_cause_cp 1 0 1 100.00 100 1 1 0
wkup_thold_cp 66 64 2 3.03 100 1 1 0


Summary for Variable bark_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 32 2 5.88


User Defined Bins for bark_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
bark_max 0 1 1
bark[1] 0 1 1
bark[2] 0 1 1
bark[3] 0 1 1
bark[4] 0 1 1
bark[5] 0 1 1
bark[6] 0 1 1
bark[7] 0 1 1
bark[8] 0 1 1
bark[9] 0 1 1
bark[10] 0 1 1
bark[11] 0 1 1
bark[12] 0 1 1
bark[13] 0 1 1
bark[14] 0 1 1
bark[15] 0 1 1
bark[16] 0 1 1
bark[17] 0 1 1
bark[18] 0 1 1
bark[19] 0 1 1
bark[20] 0 1 1
bark[21] 0 1 1
bark[22] 0 1 1
bark[23] 0 1 1
bark[24] 0 1 1
bark[25] 0 1 1
bark[26] 0 1 1
bark[27] 0 1 1
bark[28] 0 1 1
bark[29] 0 1 1
bark[30] 0 1 1
bark[31] 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
bark[0] 51247 1 T1 12 T2 11 T3 12
bark_0 4918 1 T1 7 T2 7 T3 7


Summary for Variable bite_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 32 2 5.88


User Defined Bins for bite_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
bite_max 0 1 1
bite[1] 0 1 1
bite[2] 0 1 1
bite[3] 0 1 1
bite[4] 0 1 1
bite[5] 0 1 1
bite[6] 0 1 1
bite[7] 0 1 1
bite[8] 0 1 1
bite[9] 0 1 1
bite[10] 0 1 1
bite[11] 0 1 1
bite[12] 0 1 1
bite[13] 0 1 1
bite[14] 0 1 1
bite[15] 0 1 1
bite[16] 0 1 1
bite[17] 0 1 1
bite[18] 0 1 1
bite[19] 0 1 1
bite[20] 0 1 1
bite[21] 0 1 1
bite[22] 0 1 1
bite[23] 0 1 1
bite[24] 0 1 1
bite[25] 0 1 1
bite[26] 0 1 1
bite[27] 0 1 1
bite[28] 0 1 1
bite[29] 0 1 1
bite[30] 0 1 1
bite[31] 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
bite[0] 50714 1 T1 11 T2 10 T3 11
bite_0 5451 1 T1 8 T2 8 T3 8


Summary for Variable pause_in_sleep_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for pause_in_sleep_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 56165 1 T1 19 T2 18 T3 19


Summary for Variable prescale_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 0 34 100.00


User Defined Bins for prescale_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
prescale_max 24 1 T95 24 - - - -
prescale[0] 795 1 T6 29 T10 125 T31 51
prescale[1] 1154 1 T5 19 T6 19 T29 73
prescale[2] 1138 1 T6 102 T11 87 T28 37
prescale[3] 1410 1 T5 19 T10 2 T25 134
prescale[4] 885 1 T11 19 T29 177 T47 60
prescale[5] 915 1 T8 23 T11 51 T31 30
prescale[6] 1061 1 T7 9 T9 2 T11 39
prescale[7] 693 1 T10 2 T29 71 T47 19
prescale[8] 922 1 T10 107 T25 29 T38 19
prescale[9] 1688 1 T9 2 T11 80 T25 2
prescale[10] 1120 1 T6 2 T10 2 T11 19
prescale[11] 649 1 T6 2 T25 45 T29 2
prescale[12] 900 1 T6 2 T25 20 T27 40
prescale[13] 1573 1 T25 67 T38 2 T39 63
prescale[14] 1147 1 T11 46 T25 42 T31 24
prescale[15] 599 1 T4 19 T10 90 T28 18
prescale[16] 856 1 T6 58 T25 127 T38 4
prescale[17] 1470 1 T4 19 T5 19 T6 122
prescale[18] 678 1 T6 2 T10 2 T11 38
prescale[19] 1053 1 T5 32 T6 19 T9 2
prescale[20] 871 1 T3 9 T6 37 T29 2
prescale[21] 647 1 T5 19 T6 40 T9 2
prescale[22] 822 1 T11 34 T27 88 T38 118
prescale[23] 613 1 T6 2 T11 37 T27 2
prescale[24] 460 1 T10 2 T38 65 T51 24
prescale[25] 524 1 T6 33 T10 2 T25 32
prescale[26] 1172 1 T6 9 T11 100 T25 100
prescale[27] 760 1 T4 19 T11 90 T25 194
prescale[28] 1477 1 T1 9 T10 2 T25 93
prescale[29] 599 1 T27 2 T29 40 T39 19
prescale[30] 654 1 T25 53 T27 77 T29 102
prescale[31] 872 1 T6 95 T11 295 T94 9
prescale_0 25988 1 T1 10 T2 18 T3 10


Summary for Variable wdog_regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for wdog_regwen_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 42923 1 T1 19 T2 18 T3 19
auto[1] 13242 1 T4 19 T5 114 T6 194


Summary for Variable wkup_cause_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for wkup_cause_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
wkup_cause_cleared 56165 1 T1 19 T2 18 T3 19


Summary for Variable wkup_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 66 64 2 3.03


User Defined Bins for wkup_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
wkup_max 0 1 1
wkup[1] 0 1 1
wkup[2] 0 1 1
wkup[3] 0 1 1
wkup[4] 0 1 1
wkup[5] 0 1 1
wkup[6] 0 1 1
wkup[7] 0 1 1
wkup[8] 0 1 1
wkup[9] 0 1 1
wkup[10] 0 1 1
wkup[11] 0 1 1
wkup[12] 0 1 1
wkup[13] 0 1 1
wkup[14] 0 1 1
wkup[15] 0 1 1
wkup[16] 0 1 1
wkup[17] 0 1 1
wkup[18] 0 1 1
wkup[19] 0 1 1
wkup[20] 0 1 1
wkup[21] 0 1 1
wkup[22] 0 1 1
wkup[23] 0 1 1
wkup[24] 0 1 1
wkup[25] 0 1 1
wkup[26] 0 1 1
wkup[27] 0 1 1
wkup[28] 0 1 1
wkup[29] 0 1 1
wkup[30] 0 1 1
wkup[31] 0 1 1
wkup[32] 0 1 1
wkup[33] 0 1 1
wkup[34] 0 1 1
wkup[35] 0 1 1
wkup[36] 0 1 1
wkup[37] 0 1 1
wkup[38] 0 1 1
wkup[39] 0 1 1
wkup[40] 0 1 1
wkup[41] 0 1 1
wkup[42] 0 1 1
wkup[43] 0 1 1
wkup[44] 0 1 1
wkup[45] 0 1 1
wkup[46] 0 1 1
wkup[47] 0 1 1
wkup[48] 0 1 1
wkup[49] 0 1 1
wkup[50] 0 1 1
wkup[51] 0 1 1
wkup[52] 0 1 1
wkup[53] 0 1 1
wkup[54] 0 1 1
wkup[55] 0 1 1
wkup[56] 0 1 1
wkup[57] 0 1 1
wkup[58] 0 1 1
wkup[59] 0 1 1
wkup[60] 0 1 1
wkup[61] 0 1 1
wkup[62] 0 1 1
wkup[63] 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
wkup[0] 52288 1 T1 14 T2 13 T3 14
wkup_0 3877 1 T1 5 T2 5 T3 5

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