Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
93.02 99.25 93.67 100.00 98.40 99.51 67.30


Total test records in report: 421
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T37 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.10559808 Mar 17 12:23:28 PM PDT 24 Mar 17 12:23:29 PM PDT 24 940481621 ps
T34 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.1325552350 Mar 17 12:27:41 PM PDT 24 Mar 17 12:27:51 PM PDT 24 8130533094 ps
T55 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.2819724217 Mar 17 12:25:04 PM PDT 24 Mar 17 12:25:07 PM PDT 24 612243268 ps
T283 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.2372032298 Mar 17 12:27:30 PM PDT 24 Mar 17 12:27:31 PM PDT 24 386853413 ps
T284 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.3333940358 Mar 17 12:25:18 PM PDT 24 Mar 17 12:25:19 PM PDT 24 314787171 ps
T35 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.1303051909 Mar 17 12:23:47 PM PDT 24 Mar 17 12:23:50 PM PDT 24 4402027080 ps
T285 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.3499191793 Mar 17 12:26:05 PM PDT 24 Mar 17 12:26:07 PM PDT 24 268998254 ps
T286 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.2245854450 Mar 17 12:23:19 PM PDT 24 Mar 17 12:23:20 PM PDT 24 387886758 ps
T287 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.2452799478 Mar 17 12:26:21 PM PDT 24 Mar 17 12:26:22 PM PDT 24 340871827 ps
T71 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.78151471 Mar 17 12:25:40 PM PDT 24 Mar 17 12:25:42 PM PDT 24 1126157784 ps
T288 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.3502910537 Mar 17 12:25:42 PM PDT 24 Mar 17 12:25:43 PM PDT 24 499622627 ps
T289 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.3966895775 Mar 17 12:25:52 PM PDT 24 Mar 17 12:25:53 PM PDT 24 605546657 ps
T290 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.2570259361 Mar 17 12:24:33 PM PDT 24 Mar 17 12:24:34 PM PDT 24 399955616 ps
T291 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.2473504827 Mar 17 12:24:18 PM PDT 24 Mar 17 12:24:21 PM PDT 24 742485263 ps
T36 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.1593217649 Mar 17 12:27:59 PM PDT 24 Mar 17 12:28:13 PM PDT 24 8060372646 ps
T292 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.805774073 Mar 17 12:25:39 PM PDT 24 Mar 17 12:25:40 PM PDT 24 412518988 ps
T293 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.1615047360 Mar 17 12:28:33 PM PDT 24 Mar 17 12:28:34 PM PDT 24 414150354 ps
T72 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.4037459874 Mar 17 12:24:16 PM PDT 24 Mar 17 12:24:17 PM PDT 24 2547843361 ps
T294 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.2637656899 Mar 17 12:28:11 PM PDT 24 Mar 17 12:28:12 PM PDT 24 360124237 ps
T56 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.1474106232 Mar 17 12:23:19 PM PDT 24 Mar 17 12:23:35 PM PDT 24 5871989574 ps
T295 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.4269567366 Mar 17 12:24:36 PM PDT 24 Mar 17 12:24:36 PM PDT 24 564044198 ps
T296 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.2007362272 Mar 17 12:25:20 PM PDT 24 Mar 17 12:25:23 PM PDT 24 410166219 ps
T297 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.1469681428 Mar 17 12:28:03 PM PDT 24 Mar 17 12:28:04 PM PDT 24 363697231 ps
T73 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.2353946897 Mar 17 12:25:05 PM PDT 24 Mar 17 12:25:07 PM PDT 24 453679123 ps
T298 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.3398293092 Mar 17 12:23:28 PM PDT 24 Mar 17 12:23:31 PM PDT 24 437157492 ps
T299 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.4060695609 Mar 17 12:26:13 PM PDT 24 Mar 17 12:26:14 PM PDT 24 394669816 ps
T300 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.2825331690 Mar 17 12:25:39 PM PDT 24 Mar 17 12:25:40 PM PDT 24 282709750 ps
T74 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.3565990205 Mar 17 12:27:33 PM PDT 24 Mar 17 12:27:35 PM PDT 24 2108221531 ps
T301 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.2794875992 Mar 17 12:26:51 PM PDT 24 Mar 17 12:26:53 PM PDT 24 387098711 ps
T302 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.61064919 Mar 17 12:25:54 PM PDT 24 Mar 17 12:25:56 PM PDT 24 551697495 ps
T303 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.2880619025 Mar 17 12:24:16 PM PDT 24 Mar 17 12:24:18 PM PDT 24 327230732 ps
T75 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.2747946258 Mar 17 12:23:28 PM PDT 24 Mar 17 12:23:30 PM PDT 24 1654235133 ps
T304 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.3622742973 Mar 17 12:28:06 PM PDT 24 Mar 17 12:28:07 PM PDT 24 441623471 ps
T57 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.807061502 Mar 17 12:24:38 PM PDT 24 Mar 17 12:24:39 PM PDT 24 457571546 ps
T305 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.3971541449 Mar 17 12:27:49 PM PDT 24 Mar 17 12:27:50 PM PDT 24 417129350 ps
T306 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.1570255841 Mar 17 12:25:39 PM PDT 24 Mar 17 12:25:41 PM PDT 24 647226378 ps
T58 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.2576845121 Mar 17 12:24:44 PM PDT 24 Mar 17 12:24:45 PM PDT 24 514345938 ps
T76 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.2497092773 Mar 17 12:27:19 PM PDT 24 Mar 17 12:27:20 PM PDT 24 431875337 ps
T307 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.648164508 Mar 17 12:27:13 PM PDT 24 Mar 17 12:27:14 PM PDT 24 362700727 ps
T308 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.3845024305 Mar 17 12:27:41 PM PDT 24 Mar 17 12:27:42 PM PDT 24 313685684 ps
T59 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.1968293440 Mar 17 12:23:28 PM PDT 24 Mar 17 12:23:29 PM PDT 24 529921562 ps
T60 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.1075633243 Mar 17 12:26:22 PM PDT 24 Mar 17 12:26:23 PM PDT 24 314409989 ps
T309 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.4198038378 Mar 17 12:25:39 PM PDT 24 Mar 17 12:25:40 PM PDT 24 407330226 ps
T310 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.2531663091 Mar 17 12:25:02 PM PDT 24 Mar 17 12:25:04 PM PDT 24 578210982 ps
T311 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.613516723 Mar 17 12:27:48 PM PDT 24 Mar 17 12:27:49 PM PDT 24 482665429 ps
T312 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.3164411708 Mar 17 12:28:10 PM PDT 24 Mar 17 12:28:12 PM PDT 24 445547193 ps
T61 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.4114837925 Mar 17 12:24:09 PM PDT 24 Mar 17 12:24:28 PM PDT 24 8426478297 ps
T96 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.3142170761 Mar 17 12:27:07 PM PDT 24 Mar 17 12:27:09 PM PDT 24 9124045155 ps
T313 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.220766764 Mar 17 12:26:23 PM PDT 24 Mar 17 12:26:30 PM PDT 24 4731898114 ps
T314 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.3892088348 Mar 17 12:25:24 PM PDT 24 Mar 17 12:25:25 PM PDT 24 497698809 ps
T77 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.131686693 Mar 17 12:27:48 PM PDT 24 Mar 17 12:27:50 PM PDT 24 1462142461 ps
T315 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.348277878 Mar 17 12:27:34 PM PDT 24 Mar 17 12:27:35 PM PDT 24 277641415 ps
T78 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.3638024046 Mar 17 12:27:59 PM PDT 24 Mar 17 12:28:01 PM PDT 24 989935886 ps
T79 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.1367609203 Mar 17 12:25:56 PM PDT 24 Mar 17 12:25:56 PM PDT 24 457362426 ps
T316 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.468544290 Mar 17 12:24:21 PM PDT 24 Mar 17 12:24:24 PM PDT 24 3990939428 ps
T317 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.1286841891 Mar 17 12:27:41 PM PDT 24 Mar 17 12:27:43 PM PDT 24 612041289 ps
T97 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.2716890181 Mar 17 12:23:17 PM PDT 24 Mar 17 12:23:19 PM PDT 24 4468623678 ps
T318 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.2102060800 Mar 17 12:27:43 PM PDT 24 Mar 17 12:27:56 PM PDT 24 7938850675 ps
T319 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.2068826911 Mar 17 12:23:25 PM PDT 24 Mar 17 12:23:27 PM PDT 24 548099166 ps
T320 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.3760930269 Mar 17 12:24:35 PM PDT 24 Mar 17 12:24:36 PM PDT 24 365852023 ps
T321 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.2027813775 Mar 17 12:26:53 PM PDT 24 Mar 17 12:27:06 PM PDT 24 8269821995 ps
T322 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.3753607323 Mar 17 12:27:20 PM PDT 24 Mar 17 12:27:23 PM PDT 24 4010389831 ps
T323 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.3498205103 Mar 17 12:27:19 PM PDT 24 Mar 17 12:27:24 PM PDT 24 8436158488 ps
T62 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.811641268 Mar 17 12:24:24 PM PDT 24 Mar 17 12:24:25 PM PDT 24 485135986 ps
T324 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.3977040298 Mar 17 12:27:33 PM PDT 24 Mar 17 12:27:33 PM PDT 24 528981471 ps
T325 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.433507944 Mar 17 12:24:30 PM PDT 24 Mar 17 12:24:32 PM PDT 24 772767412 ps
T326 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.452863844 Mar 17 12:27:35 PM PDT 24 Mar 17 12:27:36 PM PDT 24 318188354 ps
T327 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.302491379 Mar 17 12:24:10 PM PDT 24 Mar 17 12:24:11 PM PDT 24 485354446 ps
T328 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.3785140093 Mar 17 12:27:49 PM PDT 24 Mar 17 12:27:50 PM PDT 24 502676874 ps
T329 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.2696486071 Mar 17 12:25:07 PM PDT 24 Mar 17 12:25:09 PM PDT 24 575917732 ps
T330 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.2096287956 Mar 17 12:24:18 PM PDT 24 Mar 17 12:24:20 PM PDT 24 1148757894 ps
T331 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.4234952722 Mar 17 12:27:30 PM PDT 24 Mar 17 12:27:31 PM PDT 24 440991086 ps
T332 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.3294442777 Mar 17 12:24:13 PM PDT 24 Mar 17 12:24:14 PM PDT 24 333658436 ps
T65 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.2360203328 Mar 17 12:25:04 PM PDT 24 Mar 17 12:25:05 PM PDT 24 466417485 ps
T333 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.4265004003 Mar 17 12:27:48 PM PDT 24 Mar 17 12:27:54 PM PDT 24 8735580733 ps
T334 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.1406625670 Mar 17 12:28:15 PM PDT 24 Mar 17 12:28:16 PM PDT 24 479606981 ps
T335 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.882771123 Mar 17 12:27:20 PM PDT 24 Mar 17 12:27:22 PM PDT 24 521309011 ps
T336 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.88760674 Mar 17 12:26:05 PM PDT 24 Mar 17 12:26:09 PM PDT 24 2273219261 ps
T337 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.1260115262 Mar 17 12:27:42 PM PDT 24 Mar 17 12:27:43 PM PDT 24 1371736429 ps
T338 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.3984453219 Mar 17 12:27:30 PM PDT 24 Mar 17 12:27:31 PM PDT 24 476393140 ps
T339 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.4152852758 Mar 17 12:27:23 PM PDT 24 Mar 17 12:27:24 PM PDT 24 351618893 ps
T340 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.2431967658 Mar 17 12:27:00 PM PDT 24 Mar 17 12:27:02 PM PDT 24 1140640649 ps
T341 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.3479480160 Mar 17 12:27:30 PM PDT 24 Mar 17 12:27:30 PM PDT 24 415167752 ps
T342 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.1560524154 Mar 17 12:26:49 PM PDT 24 Mar 17 12:26:52 PM PDT 24 454208143 ps
T343 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.1105897777 Mar 17 12:24:18 PM PDT 24 Mar 17 12:24:28 PM PDT 24 6952814988 ps
T344 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.1146135087 Mar 17 12:28:07 PM PDT 24 Mar 17 12:28:08 PM PDT 24 512107414 ps
T345 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.297258268 Mar 17 12:28:10 PM PDT 24 Mar 17 12:28:12 PM PDT 24 486820141 ps
T66 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.4131776010 Mar 17 12:27:43 PM PDT 24 Mar 17 12:27:44 PM PDT 24 512199398 ps
T346 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.3223816239 Mar 17 12:28:03 PM PDT 24 Mar 17 12:28:04 PM PDT 24 2421438033 ps
T347 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.725333568 Mar 17 12:27:42 PM PDT 24 Mar 17 12:27:42 PM PDT 24 455775711 ps
T348 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.2808879378 Mar 17 12:27:53 PM PDT 24 Mar 17 12:27:55 PM PDT 24 515773632 ps
T349 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.2119595130 Mar 17 12:28:06 PM PDT 24 Mar 17 12:28:08 PM PDT 24 2845010058 ps
T67 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.1694589603 Mar 17 12:25:26 PM PDT 24 Mar 17 12:25:27 PM PDT 24 345985682 ps
T350 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.2762287573 Mar 17 12:26:51 PM PDT 24 Mar 17 12:26:56 PM PDT 24 2829401069 ps
T351 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.1834880532 Mar 17 12:27:34 PM PDT 24 Mar 17 12:27:35 PM PDT 24 442331642 ps
T63 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.2827363966 Mar 17 12:27:33 PM PDT 24 Mar 17 12:27:34 PM PDT 24 330894366 ps
T352 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.3569032367 Mar 17 12:27:32 PM PDT 24 Mar 17 12:27:33 PM PDT 24 357173848 ps
T353 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.3749418079 Mar 17 12:25:52 PM PDT 24 Mar 17 12:25:56 PM PDT 24 8477855115 ps
T68 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.2255723768 Mar 17 12:28:30 PM PDT 24 Mar 17 12:28:42 PM PDT 24 13557390494 ps
T354 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.866865947 Mar 17 12:28:33 PM PDT 24 Mar 17 12:28:34 PM PDT 24 451550679 ps
T355 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.49756388 Mar 17 12:25:53 PM PDT 24 Mar 17 12:25:54 PM PDT 24 427144901 ps
T356 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.955231137 Mar 17 12:24:32 PM PDT 24 Mar 17 12:24:34 PM PDT 24 1147118253 ps
T357 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.345040162 Mar 17 12:27:37 PM PDT 24 Mar 17 12:27:39 PM PDT 24 573848389 ps
T358 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.3618452266 Mar 17 12:26:54 PM PDT 24 Mar 17 12:26:55 PM PDT 24 571567058 ps
T359 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.3952905157 Mar 17 12:24:29 PM PDT 24 Mar 17 12:24:30 PM PDT 24 1759542150 ps
T360 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.513226897 Mar 17 12:26:35 PM PDT 24 Mar 17 12:26:39 PM PDT 24 519852375 ps
T361 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.400562368 Mar 17 12:27:32 PM PDT 24 Mar 17 12:27:45 PM PDT 24 7996465334 ps
T362 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.2313673114 Mar 17 12:27:35 PM PDT 24 Mar 17 12:27:36 PM PDT 24 386428934 ps
T363 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.2791071632 Mar 17 12:25:22 PM PDT 24 Mar 17 12:25:25 PM PDT 24 384015189 ps
T364 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.1045120560 Mar 17 12:24:49 PM PDT 24 Mar 17 12:24:49 PM PDT 24 499730112 ps
T365 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.2278894081 Mar 17 12:24:30 PM PDT 24 Mar 17 12:24:34 PM PDT 24 8491776081 ps
T366 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.4216460570 Mar 17 12:22:53 PM PDT 24 Mar 17 12:22:55 PM PDT 24 375447223 ps
T367 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.1382218213 Mar 17 12:24:14 PM PDT 24 Mar 17 12:24:17 PM PDT 24 8736561811 ps
T368 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.2979908585 Mar 17 12:28:33 PM PDT 24 Mar 17 12:28:34 PM PDT 24 374626356 ps
T369 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.683560922 Mar 17 12:25:23 PM PDT 24 Mar 17 12:25:24 PM PDT 24 355013839 ps
T370 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.3422963936 Mar 17 12:24:53 PM PDT 24 Mar 17 12:24:54 PM PDT 24 1134415758 ps
T371 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.2253354837 Mar 17 12:27:42 PM PDT 24 Mar 17 12:27:42 PM PDT 24 484374955 ps
T372 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.2435877227 Mar 17 12:26:05 PM PDT 24 Mar 17 12:26:09 PM PDT 24 2306052954 ps
T373 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.115558645 Mar 17 12:22:56 PM PDT 24 Mar 17 12:22:57 PM PDT 24 334645539 ps
T374 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.1918864812 Mar 17 12:28:03 PM PDT 24 Mar 17 12:28:04 PM PDT 24 277279934 ps
T375 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.2598396619 Mar 17 12:27:33 PM PDT 24 Mar 17 12:27:34 PM PDT 24 500642271 ps
T376 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.4282641583 Mar 17 12:24:22 PM PDT 24 Mar 17 12:24:25 PM PDT 24 2224769097 ps
T377 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.1647518457 Mar 17 12:23:09 PM PDT 24 Mar 17 12:23:10 PM PDT 24 307909761 ps
T378 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.1020566168 Mar 17 12:27:46 PM PDT 24 Mar 17 12:27:47 PM PDT 24 396012050 ps
T379 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.3297964518 Mar 17 12:25:21 PM PDT 24 Mar 17 12:25:23 PM PDT 24 367435200 ps
T380 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.933302716 Mar 17 12:22:38 PM PDT 24 Mar 17 12:22:45 PM PDT 24 4004577876 ps
T381 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.3100949966 Mar 17 12:25:22 PM PDT 24 Mar 17 12:25:24 PM PDT 24 1073579155 ps
T382 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.939656481 Mar 17 12:28:01 PM PDT 24 Mar 17 12:28:02 PM PDT 24 441953856 ps
T383 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.1232098237 Mar 17 12:27:46 PM PDT 24 Mar 17 12:27:47 PM PDT 24 453356871 ps
T384 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.2698388182 Mar 17 12:24:17 PM PDT 24 Mar 17 12:24:19 PM PDT 24 376648595 ps
T385 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.3525438658 Mar 17 12:25:28 PM PDT 24 Mar 17 12:25:30 PM PDT 24 287369415 ps
T386 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.2836844389 Mar 17 12:24:59 PM PDT 24 Mar 17 12:25:00 PM PDT 24 531057312 ps
T70 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.1425750115 Mar 17 12:27:13 PM PDT 24 Mar 17 12:27:14 PM PDT 24 457213470 ps
T387 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.360817729 Mar 17 12:23:37 PM PDT 24 Mar 17 12:23:38 PM PDT 24 372981142 ps
T388 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.3990380172 Mar 17 12:27:52 PM PDT 24 Mar 17 12:27:53 PM PDT 24 337420678 ps
T389 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.1786775651 Mar 17 12:28:32 PM PDT 24 Mar 17 12:28:34 PM PDT 24 378055057 ps
T390 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.1679737343 Mar 17 12:27:35 PM PDT 24 Mar 17 12:27:37 PM PDT 24 549491990 ps
T391 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.4181664781 Mar 17 12:24:02 PM PDT 24 Mar 17 12:24:04 PM PDT 24 884918052 ps
T392 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.1949791958 Mar 17 12:28:07 PM PDT 24 Mar 17 12:28:09 PM PDT 24 810560789 ps
T393 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.3130570811 Mar 17 12:24:09 PM PDT 24 Mar 17 12:24:10 PM PDT 24 676924760 ps
T394 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.3743999880 Mar 17 12:25:20 PM PDT 24 Mar 17 12:25:21 PM PDT 24 486210052 ps
T395 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.594130372 Mar 17 12:25:49 PM PDT 24 Mar 17 12:25:50 PM PDT 24 689034410 ps
T396 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.4070686247 Mar 17 12:23:51 PM PDT 24 Mar 17 12:23:53 PM PDT 24 436801122 ps
T397 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.469664542 Mar 17 12:25:05 PM PDT 24 Mar 17 12:25:06 PM PDT 24 396506969 ps
T398 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.3866901109 Mar 17 12:27:42 PM PDT 24 Mar 17 12:27:42 PM PDT 24 328063550 ps
T399 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.1128242808 Mar 17 12:24:08 PM PDT 24 Mar 17 12:24:10 PM PDT 24 526401952 ps
T400 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.927684170 Mar 17 12:28:08 PM PDT 24 Mar 17 12:28:12 PM PDT 24 388419827 ps
T401 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.871287692 Mar 17 12:26:51 PM PDT 24 Mar 17 12:26:52 PM PDT 24 391510692 ps
T402 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.1636835998 Mar 17 12:27:59 PM PDT 24 Mar 17 12:28:03 PM PDT 24 522146924 ps
T403 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.966036512 Mar 17 12:27:59 PM PDT 24 Mar 17 12:28:02 PM PDT 24 285735774 ps
T69 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.2382084514 Mar 17 12:28:08 PM PDT 24 Mar 17 12:28:11 PM PDT 24 513237791 ps
T404 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.3137804118 Mar 17 12:24:09 PM PDT 24 Mar 17 12:24:10 PM PDT 24 523358508 ps
T405 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.3357837652 Mar 17 12:28:33 PM PDT 24 Mar 17 12:28:35 PM PDT 24 605318647 ps
T406 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.1962081429 Mar 17 12:25:49 PM PDT 24 Mar 17 12:25:51 PM PDT 24 5042717168 ps
T407 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.4181059195 Mar 17 12:24:14 PM PDT 24 Mar 17 12:24:15 PM PDT 24 429677847 ps
T64 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.2368609907 Mar 17 12:23:57 PM PDT 24 Mar 17 12:23:58 PM PDT 24 377911048 ps
T408 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.1479052093 Mar 17 12:25:15 PM PDT 24 Mar 17 12:25:17 PM PDT 24 1012759608 ps
T409 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.3151639123 Mar 17 12:26:04 PM PDT 24 Mar 17 12:26:07 PM PDT 24 2240340281 ps
T410 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.1715212293 Mar 17 12:23:55 PM PDT 24 Mar 17 12:23:58 PM PDT 24 512518373 ps
T411 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.2267011553 Mar 17 12:28:10 PM PDT 24 Mar 17 12:28:12 PM PDT 24 2296934705 ps
T98 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.2061540428 Mar 17 12:26:22 PM PDT 24 Mar 17 12:26:24 PM PDT 24 9434135158 ps
T412 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.2355463483 Mar 17 12:28:33 PM PDT 24 Mar 17 12:28:36 PM PDT 24 4573372890 ps
T413 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.972316998 Mar 17 12:23:37 PM PDT 24 Mar 17 12:23:38 PM PDT 24 321880889 ps
T414 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.4191621066 Mar 17 12:22:58 PM PDT 24 Mar 17 12:23:26 PM PDT 24 13742319181 ps
T415 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.1464771229 Mar 17 12:26:02 PM PDT 24 Mar 17 12:26:03 PM PDT 24 421148422 ps
T416 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.4082572826 Mar 17 12:27:15 PM PDT 24 Mar 17 12:27:16 PM PDT 24 443329952 ps
T417 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.2694653013 Mar 17 12:27:42 PM PDT 24 Mar 17 12:27:43 PM PDT 24 414865413 ps
T418 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.3944001582 Mar 17 12:25:37 PM PDT 24 Mar 17 12:25:39 PM PDT 24 500499452 ps
T419 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.4245014806 Mar 17 12:27:59 PM PDT 24 Mar 17 12:28:02 PM PDT 24 355210302 ps
T420 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.2857545984 Mar 17 12:26:23 PM PDT 24 Mar 17 12:26:24 PM PDT 24 801879949 ps
T421 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.3693375476 Mar 17 12:28:05 PM PDT 24 Mar 17 12:28:06 PM PDT 24 511092659 ps

Test location /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.2214721282
Short name T6
Test name
Test status
Simulation time 53129363387 ps
CPU time 443.61 seconds
Started Mar 17 12:59:56 PM PDT 24
Finished Mar 17 01:07:20 PM PDT 24
Peak memory 197944 kb
Host smart-0ad13617-8c2d-440d-b611-1c5d3b9c09d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214721282 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.2214721282
Directory /workspace/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.1325552350
Short name T34
Test name
Test status
Simulation time 8130533094 ps
CPU time 10.04 seconds
Started Mar 17 12:27:41 PM PDT 24
Finished Mar 17 12:27:51 PM PDT 24
Peak memory 197836 kb
Host smart-0e1a4e86-9226-44d8-801b-15b5a12372d8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325552350 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_t
l_intg_err.1325552350
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.2567985239
Short name T25
Test name
Test status
Simulation time 539082318456 ps
CPU time 1027.28 seconds
Started Mar 17 12:59:54 PM PDT 24
Finished Mar 17 01:17:02 PM PDT 24
Peak memory 203888 kb
Host smart-b0227680-3f90-4ad1-a650-ebf747c8364c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567985239 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.2567985239
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.1328302583
Short name T38
Test name
Test status
Simulation time 211741415249 ps
CPU time 797.16 seconds
Started Mar 17 12:59:32 PM PDT 24
Finished Mar 17 01:12:50 PM PDT 24
Peak memory 213972 kb
Host smart-a10e9f75-f640-405e-bf8a-14cf3a2d260e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328302583 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.1328302583
Directory /workspace/9.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.4160606383
Short name T4
Test name
Test status
Simulation time 111454350853 ps
CPU time 43.17 seconds
Started Mar 17 12:59:42 PM PDT 24
Finished Mar 17 01:00:25 PM PDT 24
Peak memory 183044 kb
Host smart-47758db7-837a-4d13-bcc6-91b8432acb26
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160606383 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_
all.4160606383
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.3129713951
Short name T13
Test name
Test status
Simulation time 7987769186 ps
CPU time 4.24 seconds
Started Mar 17 12:59:27 PM PDT 24
Finished Mar 17 12:59:31 PM PDT 24
Peak memory 214832 kb
Host smart-7da01248-d9e4-4aac-b030-14abb540be51
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129713951 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.3129713951
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.2564365176
Short name T81
Test name
Test status
Simulation time 157086153152 ps
CPU time 258.6 seconds
Started Mar 17 12:59:47 PM PDT 24
Finished Mar 17 01:04:06 PM PDT 24
Peak memory 197924 kb
Host smart-cf0ffe23-c102-4382-8cbe-5f727b64f4b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564365176 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand_reset.2564365176
Directory /workspace/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.1075633243
Short name T60
Test name
Test status
Simulation time 314409989 ps
CPU time 0.72 seconds
Started Mar 17 12:26:22 PM PDT 24
Finished Mar 17 12:26:23 PM PDT 24
Peak memory 183508 kb
Host smart-6ff5981a-58bd-40d0-b3df-bc667727403c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075633243 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.1075633243
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.2061540428
Short name T98
Test name
Test status
Simulation time 9434135158 ps
CPU time 2.25 seconds
Started Mar 17 12:26:22 PM PDT 24
Finished Mar 17 12:26:24 PM PDT 24
Peak memory 197808 kb
Host smart-b165e645-3579-4f00-bcf1-67d261f67281
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061540428 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl
_intg_err.2061540428
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.2819724217
Short name T55
Test name
Test status
Simulation time 612243268 ps
CPU time 1.99 seconds
Started Mar 17 12:25:04 PM PDT 24
Finished Mar 17 12:25:07 PM PDT 24
Peak memory 194064 kb
Host smart-94a2900a-d772-49a4-922a-b54ddfcebd49
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819724217 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_a
liasing.2819724217
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.3316461189
Short name T95
Test name
Test status
Simulation time 249147593766 ps
CPU time 333.73 seconds
Started Mar 17 12:59:49 PM PDT 24
Finished Mar 17 01:05:23 PM PDT 24
Peak memory 194424 kb
Host smart-ea0f50ab-9031-4c99-9a88-f595b7a2ffa3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316461189 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_
all.3316461189
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.4191621066
Short name T414
Test name
Test status
Simulation time 13742319181 ps
CPU time 27.15 seconds
Started Mar 17 12:22:58 PM PDT 24
Finished Mar 17 12:23:26 PM PDT 24
Peak memory 183836 kb
Host smart-a51c177b-8d12-4d82-b50c-39928bd6c985
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191621066 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_b
it_bash.4191621066
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.2857545984
Short name T420
Test name
Test status
Simulation time 801879949 ps
CPU time 1.22 seconds
Started Mar 17 12:26:23 PM PDT 24
Finished Mar 17 12:26:24 PM PDT 24
Peak memory 183616 kb
Host smart-8e97b972-8eba-4b26-a33d-cecebe0684fc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857545984 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_h
w_reset.2857545984
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.2696486071
Short name T329
Test name
Test status
Simulation time 575917732 ps
CPU time 1.18 seconds
Started Mar 17 12:25:07 PM PDT 24
Finished Mar 17 12:25:09 PM PDT 24
Peak memory 198320 kb
Host smart-1b485d52-ee12-4df2-a7d3-fc42b5c9f93a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696486071 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.2696486071
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.966036512
Short name T403
Test name
Test status
Simulation time 285735774 ps
CPU time 0.93 seconds
Started Mar 17 12:27:59 PM PDT 24
Finished Mar 17 12:28:02 PM PDT 24
Peak memory 182780 kb
Host smart-718c7a2d-2c78-4775-98de-d1872b72b28b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966036512 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.966036512
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.3977040298
Short name T324
Test name
Test status
Simulation time 528981471 ps
CPU time 0.71 seconds
Started Mar 17 12:27:33 PM PDT 24
Finished Mar 17 12:27:33 PM PDT 24
Peak memory 183540 kb
Host smart-9f187fb1-b6aa-4d99-85f9-c6440c93bff0
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977040298 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_t
imer_mem_partial_access.3977040298
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.469664542
Short name T397
Test name
Test status
Simulation time 396506969 ps
CPU time 1.14 seconds
Started Mar 17 12:25:05 PM PDT 24
Finished Mar 17 12:25:06 PM PDT 24
Peak memory 183804 kb
Host smart-37210088-be6b-42a1-8ad2-b42d11df160a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469664542 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_wa
lk.469664542
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.4037459874
Short name T72
Test name
Test status
Simulation time 2547843361 ps
CPU time 1.18 seconds
Started Mar 17 12:24:16 PM PDT 24
Finished Mar 17 12:24:17 PM PDT 24
Peak memory 184164 kb
Host smart-ecf656c7-1cb1-4e08-a98f-042e22c25cbe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037459874 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon
_timer_same_csr_outstanding.4037459874
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.61064919
Short name T302
Test name
Test status
Simulation time 551697495 ps
CPU time 1.23 seconds
Started Mar 17 12:25:54 PM PDT 24
Finished Mar 17 12:25:56 PM PDT 24
Peak memory 198284 kb
Host smart-f01f49da-4ffc-446b-b981-98d680ed4b40
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61064919 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.61064919
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.1968293440
Short name T59
Test name
Test status
Simulation time 529921562 ps
CPU time 0.77 seconds
Started Mar 17 12:23:28 PM PDT 24
Finished Mar 17 12:23:29 PM PDT 24
Peak memory 183824 kb
Host smart-c233e942-2237-4ee9-b586-86eeac51981e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968293440 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_a
liasing.1968293440
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.1474106232
Short name T56
Test name
Test status
Simulation time 5871989574 ps
CPU time 16.35 seconds
Started Mar 17 12:23:19 PM PDT 24
Finished Mar 17 12:23:35 PM PDT 24
Peak memory 192108 kb
Host smart-8ee62d01-ea5a-4051-8e4d-8d27518fc183
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474106232 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_b
it_bash.1474106232
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.3422963936
Short name T370
Test name
Test status
Simulation time 1134415758 ps
CPU time 1.06 seconds
Started Mar 17 12:24:53 PM PDT 24
Finished Mar 17 12:24:54 PM PDT 24
Peak memory 183612 kb
Host smart-edc09d7f-35be-439e-acb4-10cad9482b0c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422963936 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_h
w_reset.3422963936
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.345040162
Short name T357
Test name
Test status
Simulation time 573848389 ps
CPU time 1.1 seconds
Started Mar 17 12:27:37 PM PDT 24
Finished Mar 17 12:27:39 PM PDT 24
Peak memory 195080 kb
Host smart-a7c8fea9-83e4-4c80-835e-aa28e5c0343a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345040162 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.345040162
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.2368609907
Short name T64
Test name
Test status
Simulation time 377911048 ps
CPU time 0.87 seconds
Started Mar 17 12:23:57 PM PDT 24
Finished Mar 17 12:23:58 PM PDT 24
Peak memory 183620 kb
Host smart-bff0fa9b-4ac9-4931-b68d-2db99d974555
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368609907 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.2368609907
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.4070686247
Short name T396
Test name
Test status
Simulation time 436801122 ps
CPU time 1 seconds
Started Mar 17 12:23:51 PM PDT 24
Finished Mar 17 12:23:53 PM PDT 24
Peak memory 183616 kb
Host smart-2ea8f941-0f95-495f-a589-e00c97882afa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070686247 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.4070686247
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.4082572826
Short name T416
Test name
Test status
Simulation time 443329952 ps
CPU time 0.76 seconds
Started Mar 17 12:27:15 PM PDT 24
Finished Mar 17 12:27:16 PM PDT 24
Peak memory 183204 kb
Host smart-3205e98f-64fb-4ad9-91cd-6647189afe5a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082572826 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_t
imer_mem_partial_access.4082572826
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.1045120560
Short name T364
Test name
Test status
Simulation time 499730112 ps
CPU time 0.72 seconds
Started Mar 17 12:24:49 PM PDT 24
Finished Mar 17 12:24:49 PM PDT 24
Peak memory 183668 kb
Host smart-66e9c100-5e3b-4cd7-baa5-588ce972837b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045120560 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_w
alk.1045120560
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.2747946258
Short name T75
Test name
Test status
Simulation time 1654235133 ps
CPU time 1.29 seconds
Started Mar 17 12:23:28 PM PDT 24
Finished Mar 17 12:23:30 PM PDT 24
Peak memory 183824 kb
Host smart-d5a670a5-4315-4bc3-8803-925374a5d435
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747946258 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon
_timer_same_csr_outstanding.2747946258
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.3130570811
Short name T393
Test name
Test status
Simulation time 676924760 ps
CPU time 1.55 seconds
Started Mar 17 12:24:09 PM PDT 24
Finished Mar 17 12:24:10 PM PDT 24
Peak memory 198480 kb
Host smart-9275e527-07b6-4a51-8603-f5c828ec297d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130570811 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.3130570811
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.1382218213
Short name T367
Test name
Test status
Simulation time 8736561811 ps
CPU time 3.22 seconds
Started Mar 17 12:24:14 PM PDT 24
Finished Mar 17 12:24:17 PM PDT 24
Peak memory 197864 kb
Host smart-d728fdd5-aaad-4bcc-8fd9-8a1ca06327ba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382218213 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl
_intg_err.1382218213
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.3743999880
Short name T394
Test name
Test status
Simulation time 486210052 ps
CPU time 0.84 seconds
Started Mar 17 12:25:20 PM PDT 24
Finished Mar 17 12:25:21 PM PDT 24
Peak memory 194940 kb
Host smart-73357a6b-5aac-4cb3-9056-4fdbe7814e0c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743999880 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.3743999880
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.2576845121
Short name T58
Test name
Test status
Simulation time 514345938 ps
CPU time 0.63 seconds
Started Mar 17 12:24:44 PM PDT 24
Finished Mar 17 12:24:45 PM PDT 24
Peak memory 193108 kb
Host smart-d38c90a6-cb61-4f34-87b4-57fc61182715
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576845121 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.2576845121
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.3944001582
Short name T418
Test name
Test status
Simulation time 500499452 ps
CPU time 1.18 seconds
Started Mar 17 12:25:37 PM PDT 24
Finished Mar 17 12:25:39 PM PDT 24
Peak memory 183600 kb
Host smart-a1575d95-279e-4131-bc89-cbc71b3f5274
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944001582 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.3944001582
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.3638024046
Short name T78
Test name
Test status
Simulation time 989935886 ps
CPU time 0.92 seconds
Started Mar 17 12:27:59 PM PDT 24
Finished Mar 17 12:28:01 PM PDT 24
Peak memory 183676 kb
Host smart-cb7302f2-4339-45dc-a0e4-b5c2045a76d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638024046 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.ao
n_timer_same_csr_outstanding.3638024046
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.4181664781
Short name T391
Test name
Test status
Simulation time 884918052 ps
CPU time 2.01 seconds
Started Mar 17 12:24:02 PM PDT 24
Finished Mar 17 12:24:04 PM PDT 24
Peak memory 198512 kb
Host smart-03dd7c1a-408f-4396-9d78-7704abd799c6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181664781 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.4181664781
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.3749418079
Short name T353
Test name
Test status
Simulation time 8477855115 ps
CPU time 3.33 seconds
Started Mar 17 12:25:52 PM PDT 24
Finished Mar 17 12:25:56 PM PDT 24
Peak memory 197844 kb
Host smart-43113582-8f83-4b6e-afcb-b46d1137744b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749418079 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_t
l_intg_err.3749418079
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.3693375476
Short name T421
Test name
Test status
Simulation time 511092659 ps
CPU time 0.84 seconds
Started Mar 17 12:28:05 PM PDT 24
Finished Mar 17 12:28:06 PM PDT 24
Peak memory 196764 kb
Host smart-a47b45d0-b1fa-43a5-a7a0-cfd2479c5a79
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693375476 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.3693375476
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.2808879378
Short name T348
Test name
Test status
Simulation time 515773632 ps
CPU time 0.99 seconds
Started Mar 17 12:27:53 PM PDT 24
Finished Mar 17 12:27:55 PM PDT 24
Peak memory 183592 kb
Host smart-655a9fce-a2e4-457f-b9f4-1f8ad6097091
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808879378 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.2808879378
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.3622742973
Short name T304
Test name
Test status
Simulation time 441623471 ps
CPU time 0.79 seconds
Started Mar 17 12:28:06 PM PDT 24
Finished Mar 17 12:28:07 PM PDT 24
Peak memory 183524 kb
Host smart-912b5c6d-c231-4523-a0a1-d1f7e8df1880
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622742973 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.3622742973
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.3223816239
Short name T346
Test name
Test status
Simulation time 2421438033 ps
CPU time 0.88 seconds
Started Mar 17 12:28:03 PM PDT 24
Finished Mar 17 12:28:04 PM PDT 24
Peak memory 191924 kb
Host smart-e5ffa539-51c0-43e1-a2ee-930d346cfa3a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223816239 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.ao
n_timer_same_csr_outstanding.3223816239
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.2880619025
Short name T303
Test name
Test status
Simulation time 327230732 ps
CPU time 1.4 seconds
Started Mar 17 12:24:16 PM PDT 24
Finished Mar 17 12:24:18 PM PDT 24
Peak memory 196268 kb
Host smart-1a81bd92-7bee-45eb-bd92-ddbe8a929abf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880619025 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.2880619025
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.4265004003
Short name T333
Test name
Test status
Simulation time 8735580733 ps
CPU time 5.03 seconds
Started Mar 17 12:27:48 PM PDT 24
Finished Mar 17 12:27:54 PM PDT 24
Peak memory 197060 kb
Host smart-44a1810e-2d2e-4d03-88ed-41ab39d8914c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265004003 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_t
l_intg_err.4265004003
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.3966895775
Short name T289
Test name
Test status
Simulation time 605546657 ps
CPU time 0.94 seconds
Started Mar 17 12:25:52 PM PDT 24
Finished Mar 17 12:25:53 PM PDT 24
Peak memory 197084 kb
Host smart-5189d101-ed94-4836-b412-6e3e698b68c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966895775 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.3966895775
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.3137804118
Short name T404
Test name
Test status
Simulation time 523358508 ps
CPU time 1.03 seconds
Started Mar 17 12:24:09 PM PDT 24
Finished Mar 17 12:24:10 PM PDT 24
Peak memory 183768 kb
Host smart-f3f5ab8a-b8fb-425c-8dbf-f8ccc50a94d9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137804118 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.3137804118
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.1406625670
Short name T334
Test name
Test status
Simulation time 479606981 ps
CPU time 0.73 seconds
Started Mar 17 12:28:15 PM PDT 24
Finished Mar 17 12:28:16 PM PDT 24
Peak memory 182104 kb
Host smart-3d8a8f1f-e76a-43ec-84a9-af823da21529
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406625670 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.1406625670
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.1479052093
Short name T408
Test name
Test status
Simulation time 1012759608 ps
CPU time 1.29 seconds
Started Mar 17 12:25:15 PM PDT 24
Finished Mar 17 12:25:17 PM PDT 24
Peak memory 183940 kb
Host smart-f56b0142-5ea4-48bf-82e0-48701fec4068
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479052093 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.ao
n_timer_same_csr_outstanding.1479052093
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.2007362272
Short name T296
Test name
Test status
Simulation time 410166219 ps
CPU time 2.76 seconds
Started Mar 17 12:25:20 PM PDT 24
Finished Mar 17 12:25:23 PM PDT 24
Peak memory 198424 kb
Host smart-9f8300b6-e5d7-449d-acf1-ea1b6b1fc60f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007362272 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.2007362272
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.1962081429
Short name T406
Test name
Test status
Simulation time 5042717168 ps
CPU time 1.38 seconds
Started Mar 17 12:25:49 PM PDT 24
Finished Mar 17 12:25:51 PM PDT 24
Peak memory 196484 kb
Host smart-c00d245e-90ba-4f8c-994b-a01cea6c68d7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962081429 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_t
l_intg_err.1962081429
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.882771123
Short name T335
Test name
Test status
Simulation time 521309011 ps
CPU time 0.94 seconds
Started Mar 17 12:27:20 PM PDT 24
Finished Mar 17 12:27:22 PM PDT 24
Peak memory 197456 kb
Host smart-ff6b43e8-7c7a-46c3-8071-ba4875e025c6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882771123 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.882771123
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.1425750115
Short name T70
Test name
Test status
Simulation time 457213470 ps
CPU time 0.81 seconds
Started Mar 17 12:27:13 PM PDT 24
Finished Mar 17 12:27:14 PM PDT 24
Peak memory 183636 kb
Host smart-bff69274-1b6e-4da6-b163-e06680cfa824
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425750115 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.1425750115
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.648164508
Short name T307
Test name
Test status
Simulation time 362700727 ps
CPU time 0.67 seconds
Started Mar 17 12:27:13 PM PDT 24
Finished Mar 17 12:27:14 PM PDT 24
Peak memory 183568 kb
Host smart-a553b6ac-607b-4ca3-b914-b9ca230f255b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648164508 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.648164508
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.2431967658
Short name T340
Test name
Test status
Simulation time 1140640649 ps
CPU time 1.53 seconds
Started Mar 17 12:27:00 PM PDT 24
Finished Mar 17 12:27:02 PM PDT 24
Peak memory 193136 kb
Host smart-b730db8c-c5da-4758-8652-f6c63ca7fdbc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431967658 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.ao
n_timer_same_csr_outstanding.2431967658
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.1636835998
Short name T402
Test name
Test status
Simulation time 522146924 ps
CPU time 2.43 seconds
Started Mar 17 12:27:59 PM PDT 24
Finished Mar 17 12:28:03 PM PDT 24
Peak memory 198456 kb
Host smart-0a9fdcb4-f49c-4158-8267-7661bed11e4a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636835998 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.1636835998
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.3753607323
Short name T322
Test name
Test status
Simulation time 4010389831 ps
CPU time 2.19 seconds
Started Mar 17 12:27:20 PM PDT 24
Finished Mar 17 12:27:23 PM PDT 24
Peak memory 197060 kb
Host smart-e538f227-0f8c-484c-8329-27fb45ced087
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753607323 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_t
l_intg_err.3753607323
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.594130372
Short name T395
Test name
Test status
Simulation time 689034410 ps
CPU time 0.75 seconds
Started Mar 17 12:25:49 PM PDT 24
Finished Mar 17 12:25:50 PM PDT 24
Peak memory 196076 kb
Host smart-7c86907a-8aaa-434c-85c0-39fa8250efcf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594130372 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.594130372
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.2360203328
Short name T65
Test name
Test status
Simulation time 466417485 ps
CPU time 0.77 seconds
Started Mar 17 12:25:04 PM PDT 24
Finished Mar 17 12:25:05 PM PDT 24
Peak memory 193380 kb
Host smart-a5855d23-b13f-4b08-9d89-37b7344c5146
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360203328 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.2360203328
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.1464771229
Short name T415
Test name
Test status
Simulation time 421148422 ps
CPU time 1.2 seconds
Started Mar 17 12:26:02 PM PDT 24
Finished Mar 17 12:26:03 PM PDT 24
Peak memory 183600 kb
Host smart-49b30ef5-cccb-45a5-92dc-5b0b93c28cac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464771229 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.1464771229
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.2096287956
Short name T330
Test name
Test status
Simulation time 1148757894 ps
CPU time 1.49 seconds
Started Mar 17 12:24:18 PM PDT 24
Finished Mar 17 12:24:20 PM PDT 24
Peak memory 193192 kb
Host smart-349b47f7-a073-448b-9f64-25d13ddf3889
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096287956 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao
n_timer_same_csr_outstanding.2096287956
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.2473504827
Short name T291
Test name
Test status
Simulation time 742485263 ps
CPU time 2.09 seconds
Started Mar 17 12:24:18 PM PDT 24
Finished Mar 17 12:24:21 PM PDT 24
Peak memory 198388 kb
Host smart-1fcd596e-85b0-4c8f-9fc4-92806f9c33d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473504827 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.2473504827
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.2355463483
Short name T412
Test name
Test status
Simulation time 4573372890 ps
CPU time 2.25 seconds
Started Mar 17 12:28:33 PM PDT 24
Finished Mar 17 12:28:36 PM PDT 24
Peak memory 197520 kb
Host smart-554605cb-2631-4936-8bbf-80b28bb8bbc9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355463483 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_t
l_intg_err.2355463483
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.297258268
Short name T345
Test name
Test status
Simulation time 486820141 ps
CPU time 1.38 seconds
Started Mar 17 12:28:10 PM PDT 24
Finished Mar 17 12:28:12 PM PDT 24
Peak memory 196868 kb
Host smart-1fc4c84a-d206-45d0-be5a-a44934e60e93
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297258268 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.297258268
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.2382084514
Short name T69
Test name
Test status
Simulation time 513237791 ps
CPU time 1.39 seconds
Started Mar 17 12:28:08 PM PDT 24
Finished Mar 17 12:28:11 PM PDT 24
Peak memory 193016 kb
Host smart-118937f8-a611-44e3-815c-a0c1b4de72a2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382084514 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.2382084514
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.4181059195
Short name T407
Test name
Test status
Simulation time 429677847 ps
CPU time 0.72 seconds
Started Mar 17 12:24:14 PM PDT 24
Finished Mar 17 12:24:15 PM PDT 24
Peak memory 183748 kb
Host smart-186b36b0-d90e-49d4-8d62-5bfae9e250d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181059195 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.4181059195
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.78151471
Short name T71
Test name
Test status
Simulation time 1126157784 ps
CPU time 1.9 seconds
Started Mar 17 12:25:40 PM PDT 24
Finished Mar 17 12:25:42 PM PDT 24
Peak memory 193300 kb
Host smart-66905d6b-8b2a-44cb-9641-aa17b24ebc31
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78151471 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_
timer_same_csr_outstanding.78151471
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.2698388182
Short name T384
Test name
Test status
Simulation time 376648595 ps
CPU time 2.54 seconds
Started Mar 17 12:24:17 PM PDT 24
Finished Mar 17 12:24:19 PM PDT 24
Peak memory 198448 kb
Host smart-e6b180bb-3dc9-4517-96da-e429fa60f346
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698388182 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.2698388182
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.3498205103
Short name T323
Test name
Test status
Simulation time 8436158488 ps
CPU time 4.4 seconds
Started Mar 17 12:27:19 PM PDT 24
Finished Mar 17 12:27:24 PM PDT 24
Peak memory 196792 kb
Host smart-aae03d8f-d33c-483a-9fa7-3cbb05427a60
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498205103 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_t
l_intg_err.3498205103
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.866865947
Short name T354
Test name
Test status
Simulation time 451550679 ps
CPU time 0.95 seconds
Started Mar 17 12:28:33 PM PDT 24
Finished Mar 17 12:28:34 PM PDT 24
Peak memory 193484 kb
Host smart-9ddfc67f-e812-4c58-adc1-daab79303b93
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866865947 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.866865947
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.1367609203
Short name T79
Test name
Test status
Simulation time 457362426 ps
CPU time 0.74 seconds
Started Mar 17 12:25:56 PM PDT 24
Finished Mar 17 12:25:56 PM PDT 24
Peak memory 183824 kb
Host smart-667c4ef5-6960-48a9-bd64-a8f651069fed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367609203 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.1367609203
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.3990380172
Short name T388
Test name
Test status
Simulation time 337420678 ps
CPU time 0.77 seconds
Started Mar 17 12:27:52 PM PDT 24
Finished Mar 17 12:27:53 PM PDT 24
Peak memory 182700 kb
Host smart-0e52c3b8-dd63-40ed-bec8-729a4f528a00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990380172 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.3990380172
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.2267011553
Short name T411
Test name
Test status
Simulation time 2296934705 ps
CPU time 1.11 seconds
Started Mar 17 12:28:10 PM PDT 24
Finished Mar 17 12:28:12 PM PDT 24
Peak memory 183920 kb
Host smart-082ab775-3397-4d35-9891-3298a50e1456
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267011553 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.ao
n_timer_same_csr_outstanding.2267011553
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.927684170
Short name T400
Test name
Test status
Simulation time 388419827 ps
CPU time 2.6 seconds
Started Mar 17 12:28:08 PM PDT 24
Finished Mar 17 12:28:12 PM PDT 24
Peak memory 198384 kb
Host smart-70250616-5a91-40ea-bc2b-7e4749b11495
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927684170 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.927684170
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.3142170761
Short name T96
Test name
Test status
Simulation time 9124045155 ps
CPU time 1.93 seconds
Started Mar 17 12:27:07 PM PDT 24
Finished Mar 17 12:27:09 PM PDT 24
Peak memory 197924 kb
Host smart-56760734-c66c-4c22-a28a-f813ba0ce803
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142170761 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_t
l_intg_err.3142170761
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.3357837652
Short name T405
Test name
Test status
Simulation time 605318647 ps
CPU time 1.5 seconds
Started Mar 17 12:28:33 PM PDT 24
Finished Mar 17 12:28:35 PM PDT 24
Peak memory 193756 kb
Host smart-0f32ee99-f9b3-4d2d-a8fc-427ad9abf33d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357837652 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.3357837652
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.807061502
Short name T57
Test name
Test status
Simulation time 457571546 ps
CPU time 1.22 seconds
Started Mar 17 12:24:38 PM PDT 24
Finished Mar 17 12:24:39 PM PDT 24
Peak memory 183676 kb
Host smart-b3bb136e-0e47-451c-b809-e4ac1a34c042
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807061502 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.807061502
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.3866901109
Short name T398
Test name
Test status
Simulation time 328063550 ps
CPU time 0.62 seconds
Started Mar 17 12:27:42 PM PDT 24
Finished Mar 17 12:27:42 PM PDT 24
Peak memory 182880 kb
Host smart-fd6f199c-49f8-4e81-80fb-216606eb7607
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866901109 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.3866901109
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.3565990205
Short name T74
Test name
Test status
Simulation time 2108221531 ps
CPU time 1.63 seconds
Started Mar 17 12:27:33 PM PDT 24
Finished Mar 17 12:27:35 PM PDT 24
Peak memory 194060 kb
Host smart-fa109776-3983-409e-952d-a02122a9c1f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565990205 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.ao
n_timer_same_csr_outstanding.3565990205
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.1679737343
Short name T390
Test name
Test status
Simulation time 549491990 ps
CPU time 1.8 seconds
Started Mar 17 12:27:35 PM PDT 24
Finished Mar 17 12:27:37 PM PDT 24
Peak memory 198304 kb
Host smart-0dffa717-d8ba-413b-b4f5-fac15b2c1d6f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679737343 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.1679737343
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.2694653013
Short name T417
Test name
Test status
Simulation time 414865413 ps
CPU time 1.22 seconds
Started Mar 17 12:27:42 PM PDT 24
Finished Mar 17 12:27:43 PM PDT 24
Peak memory 194904 kb
Host smart-b0e0a774-c4e9-41df-afc3-f01445df66e6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694653013 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.2694653013
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.2497092773
Short name T76
Test name
Test status
Simulation time 431875337 ps
CPU time 0.65 seconds
Started Mar 17 12:27:19 PM PDT 24
Finished Mar 17 12:27:20 PM PDT 24
Peak memory 182636 kb
Host smart-5a82a71e-c8af-4fb4-aa7e-5113bf9dbac8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497092773 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.2497092773
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.725333568
Short name T347
Test name
Test status
Simulation time 455775711 ps
CPU time 0.67 seconds
Started Mar 17 12:27:42 PM PDT 24
Finished Mar 17 12:27:42 PM PDT 24
Peak memory 182720 kb
Host smart-f9242adb-174e-42dd-beec-0ff504dbe463
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725333568 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.725333568
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.1260115262
Short name T337
Test name
Test status
Simulation time 1371736429 ps
CPU time 1.11 seconds
Started Mar 17 12:27:42 PM PDT 24
Finished Mar 17 12:27:43 PM PDT 24
Peak memory 193076 kb
Host smart-139ef436-2d5d-464b-9c99-87d0a3918223
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260115262 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.ao
n_timer_same_csr_outstanding.1260115262
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.1164002841
Short name T281
Test name
Test status
Simulation time 305311074 ps
CPU time 1.38 seconds
Started Mar 17 12:27:23 PM PDT 24
Finished Mar 17 12:27:25 PM PDT 24
Peak memory 196624 kb
Host smart-957ad739-c719-40df-a218-07bc08fb2fbf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164002841 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.1164002841
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.1593217649
Short name T36
Test name
Test status
Simulation time 8060372646 ps
CPU time 12.31 seconds
Started Mar 17 12:27:59 PM PDT 24
Finished Mar 17 12:28:13 PM PDT 24
Peak memory 197772 kb
Host smart-fbafccb2-1f12-4bb0-8873-b973b2944a93
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593217649 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_t
l_intg_err.1593217649
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.3785140093
Short name T328
Test name
Test status
Simulation time 502676874 ps
CPU time 1.45 seconds
Started Mar 17 12:27:49 PM PDT 24
Finished Mar 17 12:27:50 PM PDT 24
Peak memory 195368 kb
Host smart-fd56844b-296f-4838-80c0-e9866afdb035
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785140093 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.3785140093
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.2253354837
Short name T371
Test name
Test status
Simulation time 484374955 ps
CPU time 0.74 seconds
Started Mar 17 12:27:42 PM PDT 24
Finished Mar 17 12:27:42 PM PDT 24
Peak memory 192676 kb
Host smart-88957c37-c2bc-491a-9cfc-cb97cee25b45
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253354837 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.2253354837
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.3760930269
Short name T320
Test name
Test status
Simulation time 365852023 ps
CPU time 0.85 seconds
Started Mar 17 12:24:35 PM PDT 24
Finished Mar 17 12:24:36 PM PDT 24
Peak memory 183544 kb
Host smart-26a7f328-d14f-4866-8e31-6c8aee8f4c6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760930269 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.3760930269
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.955231137
Short name T356
Test name
Test status
Simulation time 1147118253 ps
CPU time 1.34 seconds
Started Mar 17 12:24:32 PM PDT 24
Finished Mar 17 12:24:34 PM PDT 24
Peak memory 183676 kb
Host smart-5fdd2d3c-11a7-452a-9992-72c98fc3ce65
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955231137 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon
_timer_same_csr_outstanding.955231137
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.1570255841
Short name T306
Test name
Test status
Simulation time 647226378 ps
CPU time 2.36 seconds
Started Mar 17 12:25:39 PM PDT 24
Finished Mar 17 12:25:41 PM PDT 24
Peak memory 198452 kb
Host smart-052d908e-bc5d-4b5f-9efc-6004e496206e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570255841 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.1570255841
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.400562368
Short name T361
Test name
Test status
Simulation time 7996465334 ps
CPU time 11.79 seconds
Started Mar 17 12:27:32 PM PDT 24
Finished Mar 17 12:27:45 PM PDT 24
Peak memory 196588 kb
Host smart-7447c907-8f35-48c6-aacb-98558148109a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400562368 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl
_intg_err.400562368
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.4131776010
Short name T66
Test name
Test status
Simulation time 512199398 ps
CPU time 0.98 seconds
Started Mar 17 12:27:43 PM PDT 24
Finished Mar 17 12:27:44 PM PDT 24
Peak memory 193736 kb
Host smart-6ea38888-ea6a-45d7-990b-1d30e82ac915
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131776010 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_a
liasing.4131776010
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.1105897777
Short name T343
Test name
Test status
Simulation time 6952814988 ps
CPU time 9.8 seconds
Started Mar 17 12:24:18 PM PDT 24
Finished Mar 17 12:24:28 PM PDT 24
Peak memory 192080 kb
Host smart-454ef55f-1ed4-4e67-981f-d9e8db80aaf3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105897777 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_b
it_bash.1105897777
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.10559808
Short name T37
Test name
Test status
Simulation time 940481621 ps
CPU time 0.9 seconds
Started Mar 17 12:23:28 PM PDT 24
Finished Mar 17 12:23:29 PM PDT 24
Peak memory 183892 kb
Host smart-6ebc5e3e-6d07-4197-9723-c18fcc3e974d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10559808 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_hw_
reset.10559808
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.1286841891
Short name T317
Test name
Test status
Simulation time 612041289 ps
CPU time 1.7 seconds
Started Mar 17 12:27:41 PM PDT 24
Finished Mar 17 12:27:43 PM PDT 24
Peak memory 195040 kb
Host smart-cdb493e2-d0f1-4aaf-b4a3-5dc14a166f3d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286841891 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.1286841891
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.811641268
Short name T62
Test name
Test status
Simulation time 485135986 ps
CPU time 0.74 seconds
Started Mar 17 12:24:24 PM PDT 24
Finished Mar 17 12:24:25 PM PDT 24
Peak memory 183648 kb
Host smart-1bb13e7a-bf90-47ad-80d2-437e78c4f76c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811641268 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.811641268
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.2245854450
Short name T286
Test name
Test status
Simulation time 387886758 ps
CPU time 0.9 seconds
Started Mar 17 12:23:19 PM PDT 24
Finished Mar 17 12:23:20 PM PDT 24
Peak memory 183572 kb
Host smart-c6bd2085-d937-4ea9-b1db-f7142d6accee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245854450 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.2245854450
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.115558645
Short name T373
Test name
Test status
Simulation time 334645539 ps
CPU time 1.08 seconds
Started Mar 17 12:22:56 PM PDT 24
Finished Mar 17 12:22:57 PM PDT 24
Peak memory 183560 kb
Host smart-c5eb5225-6922-47cc-a16e-ef824350aaac
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115558645 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_ti
mer_mem_partial_access.115558645
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.1647518457
Short name T377
Test name
Test status
Simulation time 307909761 ps
CPU time 0.64 seconds
Started Mar 17 12:23:09 PM PDT 24
Finished Mar 17 12:23:10 PM PDT 24
Peak memory 183588 kb
Host smart-75be945a-6b2e-4031-abc1-7d8d2d6655cd
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647518457 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_w
alk.1647518457
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.4282641583
Short name T376
Test name
Test status
Simulation time 2224769097 ps
CPU time 2.39 seconds
Started Mar 17 12:24:22 PM PDT 24
Finished Mar 17 12:24:25 PM PDT 24
Peak memory 183916 kb
Host smart-47fb7165-0294-4f49-b60b-420b36f4658c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282641583 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon
_timer_same_csr_outstanding.4282641583
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.3398293092
Short name T298
Test name
Test status
Simulation time 437157492 ps
CPU time 2.3 seconds
Started Mar 17 12:23:28 PM PDT 24
Finished Mar 17 12:23:31 PM PDT 24
Peak memory 198604 kb
Host smart-1f41d9d9-0927-49ff-8cc4-c57be10e5005
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398293092 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.3398293092
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.933302716
Short name T380
Test name
Test status
Simulation time 4004577876 ps
CPU time 7.19 seconds
Started Mar 17 12:22:38 PM PDT 24
Finished Mar 17 12:22:45 PM PDT 24
Peak memory 197764 kb
Host smart-bfbd5a48-a43e-464e-863a-5ba42de4099f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933302716 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_
intg_err.933302716
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.2372032298
Short name T283
Test name
Test status
Simulation time 386853413 ps
CPU time 0.9 seconds
Started Mar 17 12:27:30 PM PDT 24
Finished Mar 17 12:27:31 PM PDT 24
Peak memory 182628 kb
Host smart-ff07f8b8-c2a2-4f57-bca1-4c94012b41a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372032298 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.2372032298
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.2598396619
Short name T375
Test name
Test status
Simulation time 500642271 ps
CPU time 1.29 seconds
Started Mar 17 12:27:33 PM PDT 24
Finished Mar 17 12:27:34 PM PDT 24
Peak memory 183116 kb
Host smart-3f8e7969-93b7-4639-b499-6653298a83c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598396619 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.2598396619
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.1469681428
Short name T297
Test name
Test status
Simulation time 363697231 ps
CPU time 0.84 seconds
Started Mar 17 12:28:03 PM PDT 24
Finished Mar 17 12:28:04 PM PDT 24
Peak memory 183492 kb
Host smart-14864c1a-19ee-4c27-9056-324876c25068
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469681428 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.1469681428
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.2836844389
Short name T386
Test name
Test status
Simulation time 531057312 ps
CPU time 0.76 seconds
Started Mar 17 12:24:59 PM PDT 24
Finished Mar 17 12:25:00 PM PDT 24
Peak memory 183608 kb
Host smart-3b503d42-9e81-47b7-b0b2-162189da01c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836844389 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.2836844389
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.452863844
Short name T326
Test name
Test status
Simulation time 318188354 ps
CPU time 0.63 seconds
Started Mar 17 12:27:35 PM PDT 24
Finished Mar 17 12:27:36 PM PDT 24
Peak memory 183424 kb
Host smart-d9ca0ad4-0718-4b45-a7e0-34be0580717f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452863844 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.452863844
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.348277878
Short name T315
Test name
Test status
Simulation time 277641415 ps
CPU time 0.91 seconds
Started Mar 17 12:27:34 PM PDT 24
Finished Mar 17 12:27:35 PM PDT 24
Peak memory 183420 kb
Host smart-14ec44a5-7b13-4fcf-ba73-90bb681e55bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348277878 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.348277878
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.1918864812
Short name T374
Test name
Test status
Simulation time 277279934 ps
CPU time 0.73 seconds
Started Mar 17 12:28:03 PM PDT 24
Finished Mar 17 12:28:04 PM PDT 24
Peak memory 183488 kb
Host smart-60379a41-bc9f-4694-b5be-8475b4217e59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918864812 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.1918864812
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.3164411708
Short name T312
Test name
Test status
Simulation time 445547193 ps
CPU time 0.68 seconds
Started Mar 17 12:28:10 PM PDT 24
Finished Mar 17 12:28:12 PM PDT 24
Peak memory 183500 kb
Host smart-3f3cc14e-d76c-408d-8917-02ba7a18e010
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164411708 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.3164411708
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.613516723
Short name T311
Test name
Test status
Simulation time 482665429 ps
CPU time 1.23 seconds
Started Mar 17 12:27:48 PM PDT 24
Finished Mar 17 12:27:49 PM PDT 24
Peak memory 183400 kb
Host smart-ba0a430b-fac3-46ae-b1ed-2f1c298adc08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613516723 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.613516723
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.4152852758
Short name T339
Test name
Test status
Simulation time 351618893 ps
CPU time 0.66 seconds
Started Mar 17 12:27:23 PM PDT 24
Finished Mar 17 12:27:24 PM PDT 24
Peak memory 182144 kb
Host smart-f13dd7df-75f5-4dc3-9de4-bdad419b8d73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152852758 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.4152852758
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.4060695609
Short name T299
Test name
Test status
Simulation time 394669816 ps
CPU time 1.21 seconds
Started Mar 17 12:26:13 PM PDT 24
Finished Mar 17 12:26:14 PM PDT 24
Peak memory 192816 kb
Host smart-931d004f-a2d1-4d8f-a2ef-53b485d1767e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060695609 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_a
liasing.4060695609
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.2255723768
Short name T68
Test name
Test status
Simulation time 13557390494 ps
CPU time 12.08 seconds
Started Mar 17 12:28:30 PM PDT 24
Finished Mar 17 12:28:42 PM PDT 24
Peak memory 192132 kb
Host smart-8924d646-cd20-4924-84f6-ca9aaabe82e8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255723768 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_b
it_bash.2255723768
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.1949791958
Short name T392
Test name
Test status
Simulation time 810560789 ps
CPU time 0.84 seconds
Started Mar 17 12:28:07 PM PDT 24
Finished Mar 17 12:28:09 PM PDT 24
Peak memory 183636 kb
Host smart-94f3a77b-5419-4157-b828-dd69d6c2f248
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949791958 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_h
w_reset.1949791958
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.2637656899
Short name T294
Test name
Test status
Simulation time 360124237 ps
CPU time 1.13 seconds
Started Mar 17 12:28:11 PM PDT 24
Finished Mar 17 12:28:12 PM PDT 24
Peak memory 195668 kb
Host smart-79e59f6e-400c-4604-a446-82a765fea2a4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637656899 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.2637656899
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.972316998
Short name T413
Test name
Test status
Simulation time 321880889 ps
CPU time 0.81 seconds
Started Mar 17 12:23:37 PM PDT 24
Finished Mar 17 12:23:38 PM PDT 24
Peak memory 192856 kb
Host smart-8ccf3bf8-304e-47de-b950-a1628e5b4d4f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972316998 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.972316998
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.683560922
Short name T369
Test name
Test status
Simulation time 355013839 ps
CPU time 0.91 seconds
Started Mar 17 12:25:23 PM PDT 24
Finished Mar 17 12:25:24 PM PDT 24
Peak memory 183564 kb
Host smart-ac82b0ae-3704-4f66-9c7b-36df0d3dc32f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683560922 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.683560922
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.1146135087
Short name T344
Test name
Test status
Simulation time 512107414 ps
CPU time 0.67 seconds
Started Mar 17 12:28:07 PM PDT 24
Finished Mar 17 12:28:08 PM PDT 24
Peak memory 183492 kb
Host smart-7facbed5-bf80-45f9-8abc-4a6802cad727
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146135087 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_t
imer_mem_partial_access.1146135087
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.2054157061
Short name T282
Test name
Test status
Simulation time 314211170 ps
CPU time 0.56 seconds
Started Mar 17 12:28:08 PM PDT 24
Finished Mar 17 12:28:10 PM PDT 24
Peak memory 183552 kb
Host smart-1f795d40-ed72-44c5-a0e9-c74be6c0d6a0
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054157061 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_w
alk.2054157061
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.3151639123
Short name T409
Test name
Test status
Simulation time 2240340281 ps
CPU time 3.02 seconds
Started Mar 17 12:26:04 PM PDT 24
Finished Mar 17 12:26:07 PM PDT 24
Peak memory 190956 kb
Host smart-2bfa28d9-71f3-4dcc-9135-b1d9ec89f471
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151639123 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon
_timer_same_csr_outstanding.3151639123
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.1715212293
Short name T410
Test name
Test status
Simulation time 512518373 ps
CPU time 1.85 seconds
Started Mar 17 12:23:55 PM PDT 24
Finished Mar 17 12:23:58 PM PDT 24
Peak memory 198396 kb
Host smart-26c7e2f2-4a9c-4552-9aca-180ba07b8f1c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715212293 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.1715212293
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.2102060800
Short name T318
Test name
Test status
Simulation time 7938850675 ps
CPU time 12.83 seconds
Started Mar 17 12:27:43 PM PDT 24
Finished Mar 17 12:27:56 PM PDT 24
Peak memory 197972 kb
Host smart-b954111b-7722-4129-a4ea-c89a496f752a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102060800 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl
_intg_err.2102060800
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.4245014806
Short name T419
Test name
Test status
Simulation time 355210302 ps
CPU time 0.7 seconds
Started Mar 17 12:27:59 PM PDT 24
Finished Mar 17 12:28:02 PM PDT 24
Peak memory 183548 kb
Host smart-0bf7be1d-587c-4c35-bbad-4d3ec2fed055
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245014806 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.4245014806
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.939656481
Short name T382
Test name
Test status
Simulation time 441953856 ps
CPU time 0.69 seconds
Started Mar 17 12:28:01 PM PDT 24
Finished Mar 17 12:28:02 PM PDT 24
Peak memory 183444 kb
Host smart-2c30c8fa-1968-43d4-9e83-fc81e03da2de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939656481 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.939656481
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.805774073
Short name T292
Test name
Test status
Simulation time 412518988 ps
CPU time 0.75 seconds
Started Mar 17 12:25:39 PM PDT 24
Finished Mar 17 12:25:40 PM PDT 24
Peak memory 183532 kb
Host smart-9d496a02-29c5-4f97-a7a4-4db55697536e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805774073 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.805774073
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.3984453219
Short name T338
Test name
Test status
Simulation time 476393140 ps
CPU time 0.88 seconds
Started Mar 17 12:27:30 PM PDT 24
Finished Mar 17 12:27:31 PM PDT 24
Peak memory 183192 kb
Host smart-86c87c63-d2bc-4bd8-b55b-efa032dbb58f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984453219 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.3984453219
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.1020566168
Short name T378
Test name
Test status
Simulation time 396012050 ps
CPU time 1.17 seconds
Started Mar 17 12:27:46 PM PDT 24
Finished Mar 17 12:27:47 PM PDT 24
Peak memory 182504 kb
Host smart-6d54bd22-55e9-4ff9-be60-45ea930f3658
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020566168 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.1020566168
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.2979908585
Short name T368
Test name
Test status
Simulation time 374626356 ps
CPU time 0.67 seconds
Started Mar 17 12:28:33 PM PDT 24
Finished Mar 17 12:28:34 PM PDT 24
Peak memory 181704 kb
Host smart-440c1cd9-6b35-4d7b-bede-fd8a5c77a0ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979908585 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.2979908585
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.1786775651
Short name T389
Test name
Test status
Simulation time 378055057 ps
CPU time 0.63 seconds
Started Mar 17 12:28:32 PM PDT 24
Finished Mar 17 12:28:34 PM PDT 24
Peak memory 181484 kb
Host smart-e640151f-92fe-4404-90f3-390128025c3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786775651 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.1786775651
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.2570259361
Short name T290
Test name
Test status
Simulation time 399955616 ps
CPU time 1.08 seconds
Started Mar 17 12:24:33 PM PDT 24
Finished Mar 17 12:24:34 PM PDT 24
Peak memory 183932 kb
Host smart-1ed4f998-464d-4fcf-a484-c29421ac0038
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570259361 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.2570259361
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.3569032367
Short name T352
Test name
Test status
Simulation time 357173848 ps
CPU time 0.65 seconds
Started Mar 17 12:27:32 PM PDT 24
Finished Mar 17 12:27:33 PM PDT 24
Peak memory 182276 kb
Host smart-c8ab7edf-2fe0-412e-9022-5b07e39de9bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569032367 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.3569032367
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.3479480160
Short name T341
Test name
Test status
Simulation time 415167752 ps
CPU time 0.72 seconds
Started Mar 17 12:27:30 PM PDT 24
Finished Mar 17 12:27:30 PM PDT 24
Peak memory 183068 kb
Host smart-f4b2a19d-da94-4a92-b92b-2c92dc3dfb9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479480160 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.3479480160
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.3788812224
Short name T32
Test name
Test status
Simulation time 522004014 ps
CPU time 1.6 seconds
Started Mar 17 12:25:20 PM PDT 24
Finished Mar 17 12:25:22 PM PDT 24
Peak memory 183632 kb
Host smart-2e305db7-c3b5-460c-9d7e-b3e64fb29e31
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788812224 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_a
liasing.3788812224
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.4114837925
Short name T61
Test name
Test status
Simulation time 8426478297 ps
CPU time 19.13 seconds
Started Mar 17 12:24:09 PM PDT 24
Finished Mar 17 12:24:28 PM PDT 24
Peak memory 195192 kb
Host smart-f6d3300d-a97b-410e-a91b-fb92dee5fe2e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114837925 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_b
it_bash.4114837925
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.3100949966
Short name T381
Test name
Test status
Simulation time 1073579155 ps
CPU time 1.84 seconds
Started Mar 17 12:25:22 PM PDT 24
Finished Mar 17 12:25:24 PM PDT 24
Peak memory 183748 kb
Host smart-ac55655b-a472-4a71-ba7f-f492f302ac5f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100949966 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_h
w_reset.3100949966
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.4216460570
Short name T366
Test name
Test status
Simulation time 375447223 ps
CPU time 1.24 seconds
Started Mar 17 12:22:53 PM PDT 24
Finished Mar 17 12:22:55 PM PDT 24
Peak memory 195560 kb
Host smart-f41bd4f3-c805-4c0b-9cf3-67e946e5454b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216460570 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.4216460570
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.3502910537
Short name T288
Test name
Test status
Simulation time 499622627 ps
CPU time 0.87 seconds
Started Mar 17 12:25:42 PM PDT 24
Finished Mar 17 12:25:43 PM PDT 24
Peak memory 183924 kb
Host smart-2ea0b688-7515-4c4c-a09b-73422e345884
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502910537 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.3502910537
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.360817729
Short name T387
Test name
Test status
Simulation time 372981142 ps
CPU time 1.14 seconds
Started Mar 17 12:23:37 PM PDT 24
Finished Mar 17 12:23:38 PM PDT 24
Peak memory 183496 kb
Host smart-d4a1c8b0-abc7-4be9-8f7a-acf258f365a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360817729 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.360817729
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.3499191793
Short name T285
Test name
Test status
Simulation time 268998254 ps
CPU time 0.96 seconds
Started Mar 17 12:26:05 PM PDT 24
Finished Mar 17 12:26:07 PM PDT 24
Peak memory 182352 kb
Host smart-93da7393-5c32-412e-9c63-a9bea0cffd24
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499191793 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_t
imer_mem_partial_access.3499191793
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.3333940358
Short name T284
Test name
Test status
Simulation time 314787171 ps
CPU time 0.66 seconds
Started Mar 17 12:25:18 PM PDT 24
Finished Mar 17 12:25:19 PM PDT 24
Peak memory 183660 kb
Host smart-20103492-f590-4118-8846-5407fcb29b11
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333940358 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_w
alk.3333940358
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.131686693
Short name T77
Test name
Test status
Simulation time 1462142461 ps
CPU time 1.24 seconds
Started Mar 17 12:27:48 PM PDT 24
Finished Mar 17 12:27:50 PM PDT 24
Peak memory 193284 kb
Host smart-3626a0be-ce19-4b9f-9f6e-c002f484f95f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131686693 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_
timer_same_csr_outstanding.131686693
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.2794875992
Short name T301
Test name
Test status
Simulation time 387098711 ps
CPU time 1.86 seconds
Started Mar 17 12:26:51 PM PDT 24
Finished Mar 17 12:26:53 PM PDT 24
Peak memory 198448 kb
Host smart-4dabd38b-f4fc-495d-9370-4e68d99f3aed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794875992 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.2794875992
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.220766764
Short name T313
Test name
Test status
Simulation time 4731898114 ps
CPU time 7.59 seconds
Started Mar 17 12:26:23 PM PDT 24
Finished Mar 17 12:26:30 PM PDT 24
Peak memory 197612 kb
Host smart-c3b8479f-ea0f-46f3-90a0-295f8089746e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220766764 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_
intg_err.220766764
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.4269567366
Short name T295
Test name
Test status
Simulation time 564044198 ps
CPU time 0.61 seconds
Started Mar 17 12:24:36 PM PDT 24
Finished Mar 17 12:24:36 PM PDT 24
Peak memory 183596 kb
Host smart-f80b4a75-50b8-450e-ace6-07f166457d3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269567366 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.4269567366
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.2313673114
Short name T362
Test name
Test status
Simulation time 386428934 ps
CPU time 1.1 seconds
Started Mar 17 12:27:35 PM PDT 24
Finished Mar 17 12:27:36 PM PDT 24
Peak memory 183260 kb
Host smart-4393baa2-10c4-4cc5-a4b2-45980ad49d19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313673114 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.2313673114
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.1232098237
Short name T383
Test name
Test status
Simulation time 453356871 ps
CPU time 0.91 seconds
Started Mar 17 12:27:46 PM PDT 24
Finished Mar 17 12:27:47 PM PDT 24
Peak memory 182468 kb
Host smart-c195c2d8-1af8-416b-af6b-133d2f0ee6c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232098237 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.1232098237
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.4198038378
Short name T309
Test name
Test status
Simulation time 407330226 ps
CPU time 0.99 seconds
Started Mar 17 12:25:39 PM PDT 24
Finished Mar 17 12:25:40 PM PDT 24
Peak memory 183532 kb
Host smart-a3388c73-9f5d-44d4-b5a3-85da9ed09966
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198038378 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.4198038378
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.1615047360
Short name T293
Test name
Test status
Simulation time 414150354 ps
CPU time 0.66 seconds
Started Mar 17 12:28:33 PM PDT 24
Finished Mar 17 12:28:34 PM PDT 24
Peak memory 181864 kb
Host smart-9f1e3d1c-8cb1-4599-adf4-cf5256321722
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615047360 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.1615047360
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.2825331690
Short name T300
Test name
Test status
Simulation time 282709750 ps
CPU time 0.99 seconds
Started Mar 17 12:25:39 PM PDT 24
Finished Mar 17 12:25:40 PM PDT 24
Peak memory 183532 kb
Host smart-b94aa4bc-f4cd-4697-927e-f9e9322c2b87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825331690 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.2825331690
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.3845024305
Short name T308
Test name
Test status
Simulation time 313685684 ps
CPU time 0.74 seconds
Started Mar 17 12:27:41 PM PDT 24
Finished Mar 17 12:27:42 PM PDT 24
Peak memory 183464 kb
Host smart-80a6f361-7541-42bb-9a6c-64343bced7e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845024305 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.3845024305
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.4234952722
Short name T331
Test name
Test status
Simulation time 440991086 ps
CPU time 0.86 seconds
Started Mar 17 12:27:30 PM PDT 24
Finished Mar 17 12:27:31 PM PDT 24
Peak memory 182448 kb
Host smart-c5ae0ee4-8514-47ae-b73b-ef89cc5c9503
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234952722 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.4234952722
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.3971541449
Short name T305
Test name
Test status
Simulation time 417129350 ps
CPU time 0.64 seconds
Started Mar 17 12:27:49 PM PDT 24
Finished Mar 17 12:27:50 PM PDT 24
Peak memory 183452 kb
Host smart-d2b5c7a0-5b98-43eb-8927-253f0743247c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971541449 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.3971541449
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.3525438658
Short name T385
Test name
Test status
Simulation time 287369415 ps
CPU time 0.98 seconds
Started Mar 17 12:25:28 PM PDT 24
Finished Mar 17 12:25:30 PM PDT 24
Peak memory 183748 kb
Host smart-0755c1fb-aa42-4685-9943-09fdbc7f1e88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525438658 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.3525438658
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.778497098
Short name T33
Test name
Test status
Simulation time 579148803 ps
CPU time 1.59 seconds
Started Mar 17 12:26:23 PM PDT 24
Finished Mar 17 12:26:25 PM PDT 24
Peak memory 195696 kb
Host smart-230203ca-abd6-4b8a-a38b-084b46025cd4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778497098 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.778497098
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.2827363966
Short name T63
Test name
Test status
Simulation time 330894366 ps
CPU time 1.03 seconds
Started Mar 17 12:27:33 PM PDT 24
Finished Mar 17 12:27:34 PM PDT 24
Peak memory 183184 kb
Host smart-a24cf3c6-1dd1-42ab-93a1-8b1ba05a5ea1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827363966 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.2827363966
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.3297964518
Short name T379
Test name
Test status
Simulation time 367435200 ps
CPU time 0.62 seconds
Started Mar 17 12:25:21 PM PDT 24
Finished Mar 17 12:25:23 PM PDT 24
Peak memory 183584 kb
Host smart-de1bd7ea-34bd-4b04-b579-1fca7d785bfd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297964518 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.3297964518
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.88760674
Short name T336
Test name
Test status
Simulation time 2273219261 ps
CPU time 4.1 seconds
Started Mar 17 12:26:05 PM PDT 24
Finished Mar 17 12:26:09 PM PDT 24
Peak memory 194508 kb
Host smart-c9a78110-73a7-4af8-bc6a-1e90a773baf7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88760674 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_t
imer_same_csr_outstanding.88760674
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.513226897
Short name T360
Test name
Test status
Simulation time 519852375 ps
CPU time 2.77 seconds
Started Mar 17 12:26:35 PM PDT 24
Finished Mar 17 12:26:39 PM PDT 24
Peak memory 197076 kb
Host smart-17495096-29b5-45b2-9ff8-c6040098005f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513226897 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.513226897
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.468544290
Short name T316
Test name
Test status
Simulation time 3990939428 ps
CPU time 2.18 seconds
Started Mar 17 12:24:21 PM PDT 24
Finished Mar 17 12:24:24 PM PDT 24
Peak memory 197284 kb
Host smart-aba23e39-eed9-4730-9e21-498f95a4c03e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468544290 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_
intg_err.468544290
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.2068826911
Short name T319
Test name
Test status
Simulation time 548099166 ps
CPU time 1.52 seconds
Started Mar 17 12:23:25 PM PDT 24
Finished Mar 17 12:23:27 PM PDT 24
Peak memory 195104 kb
Host smart-624bd3f8-86a0-4f63-87e8-3fa8ce2ce827
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068826911 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.2068826911
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.1694589603
Short name T67
Test name
Test status
Simulation time 345985682 ps
CPU time 0.78 seconds
Started Mar 17 12:25:26 PM PDT 24
Finished Mar 17 12:25:27 PM PDT 24
Peak memory 192968 kb
Host smart-870716bb-5af2-4a96-ad99-41e3aacc3d0c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694589603 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.1694589603
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.871287692
Short name T401
Test name
Test status
Simulation time 391510692 ps
CPU time 1.04 seconds
Started Mar 17 12:26:51 PM PDT 24
Finished Mar 17 12:26:52 PM PDT 24
Peak memory 183548 kb
Host smart-eea36d88-d2a6-436f-a0e4-44609f527b48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871287692 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.871287692
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.2435877227
Short name T372
Test name
Test status
Simulation time 2306052954 ps
CPU time 3.29 seconds
Started Mar 17 12:26:05 PM PDT 24
Finished Mar 17 12:26:09 PM PDT 24
Peak memory 182496 kb
Host smart-0accee3d-a504-4e77-991e-b4e0421674a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435877227 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon
_timer_same_csr_outstanding.2435877227
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.433507944
Short name T325
Test name
Test status
Simulation time 772767412 ps
CPU time 2.09 seconds
Started Mar 17 12:24:30 PM PDT 24
Finished Mar 17 12:24:32 PM PDT 24
Peak memory 198468 kb
Host smart-4eb73010-cae0-42a4-9ed8-06e78959c789
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433507944 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.433507944
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.2278894081
Short name T365
Test name
Test status
Simulation time 8491776081 ps
CPU time 4.05 seconds
Started Mar 17 12:24:30 PM PDT 24
Finished Mar 17 12:24:34 PM PDT 24
Peak memory 198060 kb
Host smart-48fb2851-7bfd-48a5-a6d2-5896ea3fad7f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278894081 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl
_intg_err.2278894081
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.1834880532
Short name T351
Test name
Test status
Simulation time 442331642 ps
CPU time 1.24 seconds
Started Mar 17 12:27:34 PM PDT 24
Finished Mar 17 12:27:35 PM PDT 24
Peak memory 195552 kb
Host smart-eab674e8-e02a-4c38-8d60-67840732252f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834880532 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.1834880532
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.3294442777
Short name T332
Test name
Test status
Simulation time 333658436 ps
CPU time 0.72 seconds
Started Mar 17 12:24:13 PM PDT 24
Finished Mar 17 12:24:14 PM PDT 24
Peak memory 192908 kb
Host smart-dbe015eb-a4ca-4498-af50-ab4bff508f1f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294442777 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.3294442777
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.2452799478
Short name T287
Test name
Test status
Simulation time 340871827 ps
CPU time 0.54 seconds
Started Mar 17 12:26:21 PM PDT 24
Finished Mar 17 12:26:22 PM PDT 24
Peak memory 183432 kb
Host smart-6327cfae-5ac8-4647-87a6-a357a716759a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452799478 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.2452799478
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.3952905157
Short name T359
Test name
Test status
Simulation time 1759542150 ps
CPU time 1.32 seconds
Started Mar 17 12:24:29 PM PDT 24
Finished Mar 17 12:24:30 PM PDT 24
Peak memory 184072 kb
Host smart-a4a4f54f-8e66-41ad-9f36-7818cd6c6a1b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952905157 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon
_timer_same_csr_outstanding.3952905157
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.2791071632
Short name T363
Test name
Test status
Simulation time 384015189 ps
CPU time 2.54 seconds
Started Mar 17 12:25:22 PM PDT 24
Finished Mar 17 12:25:25 PM PDT 24
Peak memory 198512 kb
Host smart-8f0c99cf-5561-4ee8-bacd-da2017d88322
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791071632 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.2791071632
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.1303051909
Short name T35
Test name
Test status
Simulation time 4402027080 ps
CPU time 2.63 seconds
Started Mar 17 12:23:47 PM PDT 24
Finished Mar 17 12:23:50 PM PDT 24
Peak memory 197464 kb
Host smart-86189cfb-8221-4d7d-9a14-5a9f145e4ccb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303051909 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl
_intg_err.1303051909
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.1128242808
Short name T399
Test name
Test status
Simulation time 526401952 ps
CPU time 0.87 seconds
Started Mar 17 12:24:08 PM PDT 24
Finished Mar 17 12:24:10 PM PDT 24
Peak memory 196324 kb
Host smart-7e8c8166-37cf-415f-a1f7-a9d07c47fb3f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128242808 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.1128242808
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.2353946897
Short name T73
Test name
Test status
Simulation time 453679123 ps
CPU time 1.34 seconds
Started Mar 17 12:25:05 PM PDT 24
Finished Mar 17 12:25:07 PM PDT 24
Peak memory 183640 kb
Host smart-2950aea4-27be-4fd0-a166-e119292969ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353946897 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.2353946897
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.3892088348
Short name T314
Test name
Test status
Simulation time 497698809 ps
CPU time 0.77 seconds
Started Mar 17 12:25:24 PM PDT 24
Finished Mar 17 12:25:25 PM PDT 24
Peak memory 183636 kb
Host smart-ea5c6d8b-5137-4184-b3cc-386cda60700f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892088348 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.3892088348
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.2762287573
Short name T350
Test name
Test status
Simulation time 2829401069 ps
CPU time 4.88 seconds
Started Mar 17 12:26:51 PM PDT 24
Finished Mar 17 12:26:56 PM PDT 24
Peak memory 194456 kb
Host smart-2f1b951d-94f1-4192-9ddf-4a8c0e600558
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762287573 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon
_timer_same_csr_outstanding.2762287573
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.1560524154
Short name T342
Test name
Test status
Simulation time 454208143 ps
CPU time 2.1 seconds
Started Mar 17 12:26:49 PM PDT 24
Finished Mar 17 12:26:52 PM PDT 24
Peak memory 198500 kb
Host smart-cb07a427-0789-4fa1-8f64-fe12ba8ca178
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560524154 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.1560524154
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.2716890181
Short name T97
Test name
Test status
Simulation time 4468623678 ps
CPU time 2.68 seconds
Started Mar 17 12:23:17 PM PDT 24
Finished Mar 17 12:23:19 PM PDT 24
Peak memory 197372 kb
Host smart-e88b8dd2-6f32-4175-b7ce-345dfe438cea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716890181 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl
_intg_err.2716890181
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.302491379
Short name T327
Test name
Test status
Simulation time 485354446 ps
CPU time 0.82 seconds
Started Mar 17 12:24:10 PM PDT 24
Finished Mar 17 12:24:11 PM PDT 24
Peak memory 196184 kb
Host smart-f583f5d3-5f30-440a-ba0e-5cc9890791dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302491379 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.302491379
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.49756388
Short name T355
Test name
Test status
Simulation time 427144901 ps
CPU time 1.21 seconds
Started Mar 17 12:25:53 PM PDT 24
Finished Mar 17 12:25:54 PM PDT 24
Peak memory 192920 kb
Host smart-ba13deb6-9f8e-416f-9da8-21e0192a873a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49756388 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.49756388
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.3618452266
Short name T358
Test name
Test status
Simulation time 571567058 ps
CPU time 0.63 seconds
Started Mar 17 12:26:54 PM PDT 24
Finished Mar 17 12:26:55 PM PDT 24
Peak memory 183320 kb
Host smart-ba287716-db5a-41eb-8861-abe62fad2504
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618452266 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.3618452266
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.2119595130
Short name T349
Test name
Test status
Simulation time 2845010058 ps
CPU time 1.67 seconds
Started Mar 17 12:28:06 PM PDT 24
Finished Mar 17 12:28:08 PM PDT 24
Peak memory 183728 kb
Host smart-c2b7bf4d-e187-4621-b5ef-b9d39c3ff868
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119595130 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon
_timer_same_csr_outstanding.2119595130
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.2531663091
Short name T310
Test name
Test status
Simulation time 578210982 ps
CPU time 2.36 seconds
Started Mar 17 12:25:02 PM PDT 24
Finished Mar 17 12:25:04 PM PDT 24
Peak memory 198472 kb
Host smart-c2d43772-04f2-43cc-9382-bd4cdad7035a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531663091 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.2531663091
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.2027813775
Short name T321
Test name
Test status
Simulation time 8269821995 ps
CPU time 13.12 seconds
Started Mar 17 12:26:53 PM PDT 24
Finished Mar 17 12:27:06 PM PDT 24
Peak memory 196576 kb
Host smart-cf747db9-a853-47d2-aef6-15b43128d0ef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027813775 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl
_intg_err.2027813775
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_jump.3007221679
Short name T172
Test name
Test status
Simulation time 418687888 ps
CPU time 1.22 seconds
Started Mar 17 12:59:21 PM PDT 24
Finished Mar 17 12:59:22 PM PDT 24
Peak memory 182928 kb
Host smart-b7df9a72-7d41-48c8-9d52-513b3e4f1e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007221679 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.3007221679
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.10239592
Short name T162
Test name
Test status
Simulation time 46067962410 ps
CPU time 37.84 seconds
Started Mar 17 12:59:24 PM PDT 24
Finished Mar 17 01:00:02 PM PDT 24
Peak memory 182948 kb
Host smart-21201016-7623-4e68-a87a-5a49cc194769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10239592 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.10239592
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.3565186333
Short name T178
Test name
Test status
Simulation time 442888269 ps
CPU time 0.68 seconds
Started Mar 17 12:59:26 PM PDT 24
Finished Mar 17 12:59:27 PM PDT 24
Peak memory 182900 kb
Host smart-9b8e1afd-dd13-4ba4-8c9d-7343deb005dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565186333 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.3565186333
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.3374378519
Short name T124
Test name
Test status
Simulation time 414179387629 ps
CPU time 299.95 seconds
Started Mar 17 12:59:26 PM PDT 24
Finished Mar 17 01:04:26 PM PDT 24
Peak memory 191256 kb
Host smart-9f238ddb-56a3-49b0-9a13-da6dc78cd5e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374378519 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_a
ll.3374378519
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.3691649953
Short name T110
Test name
Test status
Simulation time 186002752172 ps
CPU time 366.43 seconds
Started Mar 17 12:59:30 PM PDT 24
Finished Mar 17 01:05:36 PM PDT 24
Peak memory 197996 kb
Host smart-c9d31f64-9c0b-4402-b43a-df4204754750
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691649953 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.3691649953
Directory /workspace/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.aon_timer_jump.765559704
Short name T154
Test name
Test status
Simulation time 441557490 ps
CPU time 1.27 seconds
Started Mar 17 12:59:25 PM PDT 24
Finished Mar 17 12:59:26 PM PDT 24
Peak memory 182972 kb
Host smart-8564aa52-4b99-4d02-93f7-eab6cbca8e38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765559704 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.765559704
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.581246931
Short name T94
Test name
Test status
Simulation time 40096659309 ps
CPU time 57.59 seconds
Started Mar 17 12:59:26 PM PDT 24
Finished Mar 17 01:00:24 PM PDT 24
Peak memory 183060 kb
Host smart-6340f3f2-9f6b-4647-9ab6-f70950b156b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581246931 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.581246931
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.661294413
Short name T12
Test name
Test status
Simulation time 7372074672 ps
CPU time 11.65 seconds
Started Mar 17 12:59:29 PM PDT 24
Finished Mar 17 12:59:41 PM PDT 24
Peak memory 215028 kb
Host smart-93429910-9edd-4518-bcc5-58b135b87caf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661294413 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.661294413
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.2009191465
Short name T212
Test name
Test status
Simulation time 478160349 ps
CPU time 0.78 seconds
Started Mar 17 12:59:22 PM PDT 24
Finished Mar 17 12:59:23 PM PDT 24
Peak memory 182988 kb
Host smart-d5c72b44-1898-423f-b163-990ec67685df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009191465 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.2009191465
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.1076984472
Short name T205
Test name
Test status
Simulation time 326157426140 ps
CPU time 514.74 seconds
Started Mar 17 12:59:31 PM PDT 24
Finished Mar 17 01:08:06 PM PDT 24
Peak memory 194592 kb
Host smart-2fe461dd-def7-4a8b-b48f-2e09747cc80f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076984472 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_a
ll.1076984472
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.156118889
Short name T249
Test name
Test status
Simulation time 12584952092 ps
CPU time 101.41 seconds
Started Mar 17 12:59:23 PM PDT 24
Finished Mar 17 01:01:04 PM PDT 24
Peak memory 197940 kb
Host smart-9dba3ff2-5011-4665-9c9f-3fdd284eaa56
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156118889 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.156118889
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.aon_timer_jump.987146595
Short name T118
Test name
Test status
Simulation time 438964894 ps
CPU time 1.24 seconds
Started Mar 17 12:59:31 PM PDT 24
Finished Mar 17 12:59:32 PM PDT 24
Peak memory 183012 kb
Host smart-1fc381e8-abb2-4155-8457-a3ed684f34f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987146595 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.987146595
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.2870558414
Short name T196
Test name
Test status
Simulation time 21451114346 ps
CPU time 4.1 seconds
Started Mar 17 12:59:31 PM PDT 24
Finished Mar 17 12:59:35 PM PDT 24
Peak memory 183048 kb
Host smart-43c8b548-b00c-45d8-a429-e11b6c977ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870558414 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.2870558414
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.2265767037
Short name T123
Test name
Test status
Simulation time 412141931 ps
CPU time 0.69 seconds
Started Mar 17 12:59:34 PM PDT 24
Finished Mar 17 12:59:35 PM PDT 24
Peak memory 182972 kb
Host smart-ebc82b95-586c-4e91-871a-0299a1c3759e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265767037 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.2265767037
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.1617129369
Short name T156
Test name
Test status
Simulation time 79126381555 ps
CPU time 26.95 seconds
Started Mar 17 12:59:34 PM PDT 24
Finished Mar 17 01:00:01 PM PDT 24
Peak memory 193384 kb
Host smart-196b8427-5150-4cb6-b904-6daef87151c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617129369 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_
all.1617129369
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.2213491785
Short name T88
Test name
Test status
Simulation time 112903395115 ps
CPU time 218.29 seconds
Started Mar 17 12:59:30 PM PDT 24
Finished Mar 17 01:03:08 PM PDT 24
Peak memory 197912 kb
Host smart-0c7e4e82-6f42-44b5-b729-bb2e91eb0b7f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213491785 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.2213491785
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.aon_timer_jump.1448357394
Short name T247
Test name
Test status
Simulation time 650778109 ps
CPU time 0.58 seconds
Started Mar 17 12:59:30 PM PDT 24
Finished Mar 17 12:59:31 PM PDT 24
Peak memory 182976 kb
Host smart-5e3eee91-3341-44b2-b60a-0118665b6fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448357394 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.1448357394
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.3284772868
Short name T279
Test name
Test status
Simulation time 56085714542 ps
CPU time 21.32 seconds
Started Mar 17 12:59:30 PM PDT 24
Finished Mar 17 12:59:52 PM PDT 24
Peak memory 183080 kb
Host smart-577181f3-0e4c-479c-b00e-213089f64663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284772868 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.3284772868
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.3553170753
Short name T241
Test name
Test status
Simulation time 552920032 ps
CPU time 1.31 seconds
Started Mar 17 12:59:29 PM PDT 24
Finished Mar 17 12:59:31 PM PDT 24
Peak memory 182948 kb
Host smart-1802d9d3-5a6c-4794-8a98-bc8b2bc07b92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553170753 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.3553170753
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.964915573
Short name T260
Test name
Test status
Simulation time 44942603760 ps
CPU time 16.93 seconds
Started Mar 17 12:59:52 PM PDT 24
Finished Mar 17 01:00:09 PM PDT 24
Peak memory 183088 kb
Host smart-c2ab5398-f121-4c29-a5ce-a4316b91751b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964915573 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_a
ll.964915573
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.847343206
Short name T91
Test name
Test status
Simulation time 26861324590 ps
CPU time 103.67 seconds
Started Mar 17 12:59:31 PM PDT 24
Finished Mar 17 01:01:15 PM PDT 24
Peak memory 197956 kb
Host smart-95343053-4476-40a8-85c0-7409183cf4a1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847343206 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand_reset.847343206
Directory /workspace/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.aon_timer_jump.72981218
Short name T108
Test name
Test status
Simulation time 546143132 ps
CPU time 1.28 seconds
Started Mar 17 12:59:28 PM PDT 24
Finished Mar 17 12:59:30 PM PDT 24
Peak memory 183012 kb
Host smart-f9d54b7f-616e-4204-bf5b-da235227c2e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72981218 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.72981218
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.57229698
Short name T50
Test name
Test status
Simulation time 29223550551 ps
CPU time 11.48 seconds
Started Mar 17 12:59:31 PM PDT 24
Finished Mar 17 12:59:43 PM PDT 24
Peak memory 183044 kb
Host smart-b9161f39-c1a3-49e4-ac7a-792c07523267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57229698 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.57229698
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.3715942780
Short name T111
Test name
Test status
Simulation time 611404359 ps
CPU time 0.64 seconds
Started Mar 17 12:59:44 PM PDT 24
Finished Mar 17 12:59:45 PM PDT 24
Peak memory 182996 kb
Host smart-8fbd0e10-4fcd-4146-b5ce-cbbaf092795c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715942780 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.3715942780
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.1244375956
Short name T165
Test name
Test status
Simulation time 228403943706 ps
CPU time 91.35 seconds
Started Mar 17 12:59:32 PM PDT 24
Finished Mar 17 01:01:04 PM PDT 24
Peak memory 183056 kb
Host smart-1b3882eb-f942-4f7d-a334-375099a57ba8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244375956 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_
all.1244375956
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.43086685
Short name T207
Test name
Test status
Simulation time 64016815964 ps
CPU time 532.04 seconds
Started Mar 17 12:59:32 PM PDT 24
Finished Mar 17 01:08:25 PM PDT 24
Peak memory 197944 kb
Host smart-af83a75a-a174-44ca-b436-6ddaeb72629c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43086685 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.43086685
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_jump.2293030906
Short name T217
Test name
Test status
Simulation time 422308520 ps
CPU time 0.68 seconds
Started Mar 17 12:59:45 PM PDT 24
Finished Mar 17 12:59:47 PM PDT 24
Peak memory 183000 kb
Host smart-7830e36e-b86e-4141-b9ce-c865eaf4d826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293030906 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.2293030906
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.1296306417
Short name T259
Test name
Test status
Simulation time 26608547836 ps
CPU time 8.04 seconds
Started Mar 17 12:59:32 PM PDT 24
Finished Mar 17 12:59:40 PM PDT 24
Peak memory 183056 kb
Host smart-60e25f4a-aad2-46f1-9423-a331271ac357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296306417 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.1296306417
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.2129000001
Short name T102
Test name
Test status
Simulation time 388034800 ps
CPU time 0.74 seconds
Started Mar 17 12:59:35 PM PDT 24
Finished Mar 17 12:59:36 PM PDT 24
Peak memory 183016 kb
Host smart-997dc5d5-7e2e-4bda-b8e8-b464af67b693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129000001 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.2129000001
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.3573074766
Short name T126
Test name
Test status
Simulation time 105949317595 ps
CPU time 156.39 seconds
Started Mar 17 12:59:39 PM PDT 24
Finished Mar 17 01:02:15 PM PDT 24
Peak memory 183060 kb
Host smart-f82c67ef-106a-4d21-8f25-540f5bb49c46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573074766 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_
all.3573074766
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.730401549
Short name T145
Test name
Test status
Simulation time 52821512844 ps
CPU time 422.49 seconds
Started Mar 17 12:59:49 PM PDT 24
Finished Mar 17 01:06:52 PM PDT 24
Peak memory 197984 kb
Host smart-2664d753-e37c-473f-b21a-dabbc87f0c3d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730401549 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.730401549
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.aon_timer_jump.3758894165
Short name T43
Test name
Test status
Simulation time 359005482 ps
CPU time 1.19 seconds
Started Mar 17 12:59:39 PM PDT 24
Finished Mar 17 12:59:41 PM PDT 24
Peak memory 182952 kb
Host smart-c0b2a4f0-3571-4871-96c0-fb6f156d5268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758894165 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.3758894165
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.4166283648
Short name T131
Test name
Test status
Simulation time 9292507088 ps
CPU time 14.75 seconds
Started Mar 17 12:59:35 PM PDT 24
Finished Mar 17 12:59:50 PM PDT 24
Peak memory 183040 kb
Host smart-45a1f9dd-4f4c-46da-baaa-01e3eeb5b2fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166283648 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.4166283648
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.2557125932
Short name T153
Test name
Test status
Simulation time 465563406 ps
CPU time 0.69 seconds
Started Mar 17 12:59:34 PM PDT 24
Finished Mar 17 12:59:35 PM PDT 24
Peak memory 182964 kb
Host smart-49436277-5bb2-46b5-9033-0178a897a419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557125932 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.2557125932
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.4105693241
Short name T104
Test name
Test status
Simulation time 235639435109 ps
CPU time 185.61 seconds
Started Mar 17 12:59:57 PM PDT 24
Finished Mar 17 01:03:03 PM PDT 24
Peak memory 194556 kb
Host smart-7562356f-0fe7-426a-835a-6754035e638c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105693241 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_
all.4105693241
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.2182542281
Short name T244
Test name
Test status
Simulation time 39304279887 ps
CPU time 301.38 seconds
Started Mar 17 12:59:44 PM PDT 24
Finished Mar 17 01:04:46 PM PDT 24
Peak memory 197932 kb
Host smart-63a15a7a-e17d-40a5-b3f7-0e2d37ca0d4b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182542281 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.2182542281
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.aon_timer_jump.2964468514
Short name T128
Test name
Test status
Simulation time 404157341 ps
CPU time 0.74 seconds
Started Mar 17 12:59:35 PM PDT 24
Finished Mar 17 12:59:36 PM PDT 24
Peak memory 182988 kb
Host smart-5176b4e8-dc4d-4839-980b-ab51271b0699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964468514 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.2964468514
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.1344545121
Short name T1
Test name
Test status
Simulation time 55128198914 ps
CPU time 80.52 seconds
Started Mar 17 12:59:35 PM PDT 24
Finished Mar 17 01:00:56 PM PDT 24
Peak memory 183064 kb
Host smart-6ab0c180-451d-4677-bee2-7d708aae5d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344545121 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.1344545121
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.888391576
Short name T113
Test name
Test status
Simulation time 636140054 ps
CPU time 0.58 seconds
Started Mar 17 01:00:00 PM PDT 24
Finished Mar 17 01:00:01 PM PDT 24
Peak memory 182996 kb
Host smart-2dd13da6-11f4-4818-a12d-2786c2b99dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888391576 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.888391576
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.4151089442
Short name T163
Test name
Test status
Simulation time 89653220991 ps
CPU time 76.6 seconds
Started Mar 17 12:59:53 PM PDT 24
Finished Mar 17 01:01:10 PM PDT 24
Peak memory 183024 kb
Host smart-ba17f2b7-d84d-4f21-b81b-e3f6b57c88df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151089442 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_
all.4151089442
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.1687628857
Short name T144
Test name
Test status
Simulation time 264632298326 ps
CPU time 747.81 seconds
Started Mar 17 12:59:46 PM PDT 24
Finished Mar 17 01:12:15 PM PDT 24
Peak memory 201092 kb
Host smart-4196980b-1137-4467-830b-28e7d783150b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687628857 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.1687628857
Directory /workspace/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.aon_timer_jump.4127001057
Short name T218
Test name
Test status
Simulation time 491727443 ps
CPU time 0.7 seconds
Started Mar 17 12:59:39 PM PDT 24
Finished Mar 17 12:59:41 PM PDT 24
Peak memory 182984 kb
Host smart-428e2cc5-0915-48fb-9161-7bf4a274ec8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127001057 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.4127001057
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.1931800984
Short name T270
Test name
Test status
Simulation time 41676181020 ps
CPU time 16.01 seconds
Started Mar 17 12:59:36 PM PDT 24
Finished Mar 17 12:59:53 PM PDT 24
Peak memory 183024 kb
Host smart-d8532953-8c47-4fa6-9c2b-5ec5f78f1749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931800984 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.1931800984
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.2541573822
Short name T255
Test name
Test status
Simulation time 411463035 ps
CPU time 1.05 seconds
Started Mar 17 12:59:35 PM PDT 24
Finished Mar 17 12:59:37 PM PDT 24
Peak memory 183004 kb
Host smart-3e47096c-f89a-4399-adea-b6bf15155892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541573822 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.2541573822
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.2301958375
Short name T229
Test name
Test status
Simulation time 8326078256 ps
CPU time 7.74 seconds
Started Mar 17 12:59:36 PM PDT 24
Finished Mar 17 12:59:44 PM PDT 24
Peak memory 183192 kb
Host smart-c4daf07c-3205-4562-abae-6427b7f89831
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301958375 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_
all.2301958375
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.2441430137
Short name T80
Test name
Test status
Simulation time 57943648948 ps
CPU time 438.87 seconds
Started Mar 17 12:59:55 PM PDT 24
Finished Mar 17 01:07:14 PM PDT 24
Peak memory 197956 kb
Host smart-9f0d4587-5653-4341-b80c-93592ccf54ff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441430137 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.2441430137
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.aon_timer_jump.3985852514
Short name T22
Test name
Test status
Simulation time 460394139 ps
CPU time 0.69 seconds
Started Mar 17 12:59:46 PM PDT 24
Finished Mar 17 12:59:48 PM PDT 24
Peak memory 182892 kb
Host smart-8709aa23-3db6-4772-a968-a78b7d6628bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985852514 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.3985852514
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.2329803909
Short name T254
Test name
Test status
Simulation time 13686428522 ps
CPU time 5.86 seconds
Started Mar 17 12:59:36 PM PDT 24
Finished Mar 17 12:59:43 PM PDT 24
Peak memory 183024 kb
Host smart-b58142fb-cf57-44eb-9296-2e8eccbe1028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329803909 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.2329803909
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.3619108448
Short name T242
Test name
Test status
Simulation time 473225427 ps
CPU time 0.9 seconds
Started Mar 17 12:59:44 PM PDT 24
Finished Mar 17 12:59:45 PM PDT 24
Peak memory 182956 kb
Host smart-0ba6eaaf-cb83-4bb9-9889-fac67d718ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619108448 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.3619108448
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.315669010
Short name T166
Test name
Test status
Simulation time 128547517105 ps
CPU time 103.38 seconds
Started Mar 17 12:59:43 PM PDT 24
Finished Mar 17 01:01:26 PM PDT 24
Peak memory 193940 kb
Host smart-3a379330-a234-413d-ba4b-24a28042b3d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315669010 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_a
ll.315669010
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.2506790854
Short name T27
Test name
Test status
Simulation time 346093601966 ps
CPU time 683.59 seconds
Started Mar 17 12:59:35 PM PDT 24
Finished Mar 17 01:10:59 PM PDT 24
Peak memory 200360 kb
Host smart-9f0d909c-b94e-4e2a-a77d-624c741ef7bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506790854 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.2506790854
Directory /workspace/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.aon_timer_jump.2717751594
Short name T159
Test name
Test status
Simulation time 458968732 ps
CPU time 0.6 seconds
Started Mar 17 12:59:58 PM PDT 24
Finished Mar 17 01:00:00 PM PDT 24
Peak memory 182916 kb
Host smart-23afbdf6-2349-49dc-a288-0cf7c53b9d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717751594 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.2717751594
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.2439799464
Short name T174
Test name
Test status
Simulation time 47246690115 ps
CPU time 8.05 seconds
Started Mar 17 12:59:57 PM PDT 24
Finished Mar 17 01:00:05 PM PDT 24
Peak memory 183060 kb
Host smart-88532c29-4dc4-4724-bad9-3eb8bdf94209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439799464 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.2439799464
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.2261176976
Short name T190
Test name
Test status
Simulation time 512606703 ps
CPU time 1.34 seconds
Started Mar 17 12:59:36 PM PDT 24
Finished Mar 17 12:59:38 PM PDT 24
Peak memory 183008 kb
Host smart-d53170be-a26f-4ba0-857e-f2fddb82b2c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261176976 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.2261176976
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.1409171655
Short name T235
Test name
Test status
Simulation time 159509542345 ps
CPU time 53.08 seconds
Started Mar 17 12:59:40 PM PDT 24
Finished Mar 17 01:00:33 PM PDT 24
Peak memory 193848 kb
Host smart-72da6510-11fa-4043-9d89-61ce6f8eeaa0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409171655 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_
all.1409171655
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_jump.3112289938
Short name T208
Test name
Test status
Simulation time 585047650 ps
CPU time 1.39 seconds
Started Mar 17 12:59:52 PM PDT 24
Finished Mar 17 12:59:54 PM PDT 24
Peak memory 183000 kb
Host smart-2d4a4913-043c-4c28-a023-2612ebbf0e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112289938 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.3112289938
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.992321072
Short name T3
Test name
Test status
Simulation time 26855059444 ps
CPU time 10.66 seconds
Started Mar 17 12:59:37 PM PDT 24
Finished Mar 17 12:59:48 PM PDT 24
Peak memory 183024 kb
Host smart-3eb39a32-4d0e-4a7d-abb9-c2e5c12f199a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992321072 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.992321072
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.835785969
Short name T245
Test name
Test status
Simulation time 428224766 ps
CPU time 1.19 seconds
Started Mar 17 12:59:49 PM PDT 24
Finished Mar 17 12:59:51 PM PDT 24
Peak memory 182940 kb
Host smart-d48596b7-2dee-463e-9eb4-fb951cfbe665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835785969 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.835785969
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.2489300328
Short name T85
Test name
Test status
Simulation time 31015511425 ps
CPU time 138.47 seconds
Started Mar 17 12:59:50 PM PDT 24
Finished Mar 17 01:02:09 PM PDT 24
Peak memory 197924 kb
Host smart-18a796f6-fbeb-40fc-9cf9-3be22c0d8f22
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489300328 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.2489300328
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_jump.4005492401
Short name T41
Test name
Test status
Simulation time 343156106 ps
CPU time 1.07 seconds
Started Mar 17 12:59:26 PM PDT 24
Finished Mar 17 12:59:27 PM PDT 24
Peak memory 182900 kb
Host smart-99fa34ec-e2f9-4039-bb03-fa1b61cdeafb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005492401 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.4005492401
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.2411860306
Short name T215
Test name
Test status
Simulation time 7896310971 ps
CPU time 13.82 seconds
Started Mar 17 12:59:24 PM PDT 24
Finished Mar 17 12:59:38 PM PDT 24
Peak memory 183000 kb
Host smart-9ae57f17-92a2-4e3b-81e8-f97c4cce2499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411860306 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.2411860306
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.3740859753
Short name T14
Test name
Test status
Simulation time 7874738959 ps
CPU time 7.11 seconds
Started Mar 17 12:59:30 PM PDT 24
Finished Mar 17 12:59:38 PM PDT 24
Peak memory 214920 kb
Host smart-64689979-7c7e-4022-a31b-5c8f069a62c6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740859753 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.3740859753
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.3290921615
Short name T214
Test name
Test status
Simulation time 493354489 ps
CPU time 0.78 seconds
Started Mar 17 12:59:23 PM PDT 24
Finished Mar 17 12:59:24 PM PDT 24
Peak memory 182940 kb
Host smart-2e10de49-0bde-45b7-bfeb-91de6bc7e358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290921615 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.3290921615
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.674738186
Short name T52
Test name
Test status
Simulation time 61880595449 ps
CPU time 49.63 seconds
Started Mar 17 12:59:35 PM PDT 24
Finished Mar 17 01:00:25 PM PDT 24
Peak memory 183068 kb
Host smart-4f45577c-a557-48b7-b34a-7bf9c020395f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674738186 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_al
l.674738186
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.2458485485
Short name T239
Test name
Test status
Simulation time 93841183558 ps
CPU time 208.71 seconds
Started Mar 17 12:59:31 PM PDT 24
Finished Mar 17 01:03:00 PM PDT 24
Peak memory 197928 kb
Host smart-45e325ca-c8d7-491f-a135-c9b7f38c6a59
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458485485 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.2458485485
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.aon_timer_jump.2927843222
Short name T149
Test name
Test status
Simulation time 498967488 ps
CPU time 0.74 seconds
Started Mar 17 12:59:47 PM PDT 24
Finished Mar 17 12:59:48 PM PDT 24
Peak memory 182888 kb
Host smart-6f816329-cc36-40c8-8438-7b9b830543c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927843222 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.2927843222
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.1724707302
Short name T206
Test name
Test status
Simulation time 6121550629 ps
CPU time 5.67 seconds
Started Mar 17 12:59:42 PM PDT 24
Finished Mar 17 12:59:48 PM PDT 24
Peak memory 182948 kb
Host smart-bcccc6c4-563b-48e9-b657-8424311dc734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724707302 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.1724707302
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.1284543110
Short name T99
Test name
Test status
Simulation time 427553224 ps
CPU time 0.69 seconds
Started Mar 17 12:59:58 PM PDT 24
Finished Mar 17 12:59:59 PM PDT 24
Peak memory 182888 kb
Host smart-a4fab06e-ab3d-4321-986d-6741b5bf6549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284543110 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.1284543110
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.133186831
Short name T106
Test name
Test status
Simulation time 329509260529 ps
CPU time 77.11 seconds
Started Mar 17 12:59:53 PM PDT 24
Finished Mar 17 01:01:10 PM PDT 24
Peak memory 183360 kb
Host smart-d2af9a5b-b19d-4252-a479-dabd5e29131d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133186831 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_a
ll.133186831
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.3503357735
Short name T240
Test name
Test status
Simulation time 145200175762 ps
CPU time 537.96 seconds
Started Mar 17 12:59:44 PM PDT 24
Finished Mar 17 01:08:42 PM PDT 24
Peak memory 198116 kb
Host smart-31054599-2b8f-4153-9ac0-5dea705b8b39
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503357735 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.3503357735
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_jump.513021933
Short name T23
Test name
Test status
Simulation time 452565136 ps
CPU time 0.71 seconds
Started Mar 17 12:59:55 PM PDT 24
Finished Mar 17 12:59:55 PM PDT 24
Peak memory 182992 kb
Host smart-89677cca-55d8-455c-939f-67a312be0191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513021933 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.513021933
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.2721928854
Short name T7
Test name
Test status
Simulation time 8426898376 ps
CPU time 3.09 seconds
Started Mar 17 12:59:44 PM PDT 24
Finished Mar 17 12:59:47 PM PDT 24
Peak memory 183032 kb
Host smart-16bdde30-2d29-48de-9d0d-1f29b6441c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721928854 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.2721928854
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.1797803906
Short name T271
Test name
Test status
Simulation time 342713252 ps
CPU time 1.06 seconds
Started Mar 17 01:00:04 PM PDT 24
Finished Mar 17 01:00:05 PM PDT 24
Peak memory 182956 kb
Host smart-9783e3c8-d2b3-4816-b11d-b50385894250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797803906 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.1797803906
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.261597351
Short name T258
Test name
Test status
Simulation time 93851788595 ps
CPU time 73.9 seconds
Started Mar 17 12:59:48 PM PDT 24
Finished Mar 17 01:01:02 PM PDT 24
Peak memory 183040 kb
Host smart-88516697-9dc6-43e4-aee6-84c09a0c88a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261597351 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_a
ll.261597351
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_jump.94422445
Short name T103
Test name
Test status
Simulation time 551585500 ps
CPU time 0.75 seconds
Started Mar 17 12:59:55 PM PDT 24
Finished Mar 17 12:59:56 PM PDT 24
Peak memory 182984 kb
Host smart-2c551e94-271e-4ee0-88a9-4c7c41e706f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94422445 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.94422445
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.2208520890
Short name T141
Test name
Test status
Simulation time 32951158575 ps
CPU time 55.03 seconds
Started Mar 17 12:59:56 PM PDT 24
Finished Mar 17 01:00:51 PM PDT 24
Peak memory 182972 kb
Host smart-659844c9-5938-428e-b67c-1743d345602c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208520890 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.2208520890
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.3099585479
Short name T119
Test name
Test status
Simulation time 511940176 ps
CPU time 0.71 seconds
Started Mar 17 12:59:55 PM PDT 24
Finished Mar 17 12:59:56 PM PDT 24
Peak memory 182988 kb
Host smart-75e0ee9f-dfba-43fb-9018-af08cafe8f73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099585479 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.3099585479
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_jump.3412685730
Short name T210
Test name
Test status
Simulation time 531850158 ps
CPU time 0.85 seconds
Started Mar 17 12:59:58 PM PDT 24
Finished Mar 17 12:59:59 PM PDT 24
Peak memory 182956 kb
Host smart-4723544a-9ad0-4ce1-99bf-6fc73c5325f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412685730 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.3412685730
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.3677840000
Short name T114
Test name
Test status
Simulation time 22037953724 ps
CPU time 9.22 seconds
Started Mar 17 12:59:42 PM PDT 24
Finished Mar 17 12:59:51 PM PDT 24
Peak memory 183056 kb
Host smart-536135c7-89e2-4738-b0a8-7ddf3a47865b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677840000 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.3677840000
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.759396406
Short name T142
Test name
Test status
Simulation time 467273740 ps
CPU time 1.23 seconds
Started Mar 17 01:00:00 PM PDT 24
Finished Mar 17 01:00:01 PM PDT 24
Peak memory 182976 kb
Host smart-deb784d3-d6d5-4af7-98eb-9b38e8ff98db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759396406 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.759396406
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.3771004604
Short name T134
Test name
Test status
Simulation time 74634856499 ps
CPU time 24.45 seconds
Started Mar 17 12:59:54 PM PDT 24
Finished Mar 17 01:00:18 PM PDT 24
Peak memory 183008 kb
Host smart-c37a4d82-528d-441d-9ced-851888121b68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771004604 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_
all.3771004604
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.4114464427
Short name T274
Test name
Test status
Simulation time 98258092220 ps
CPU time 795.63 seconds
Started Mar 17 12:59:54 PM PDT 24
Finished Mar 17 01:13:10 PM PDT 24
Peak memory 201864 kb
Host smart-19734783-511a-4dc8-99a4-f7655c6b4ce7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114464427 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.4114464427
Directory /workspace/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.aon_timer_jump.973105818
Short name T277
Test name
Test status
Simulation time 596772978 ps
CPU time 0.89 seconds
Started Mar 17 12:59:44 PM PDT 24
Finished Mar 17 12:59:45 PM PDT 24
Peak memory 182936 kb
Host smart-032df499-ab3e-411f-a9ec-dcd21360bafe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973105818 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.973105818
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.226880281
Short name T155
Test name
Test status
Simulation time 15150131077 ps
CPU time 21.96 seconds
Started Mar 17 01:00:02 PM PDT 24
Finished Mar 17 01:00:24 PM PDT 24
Peak memory 183052 kb
Host smart-8592e1fc-1395-45de-8f45-8e9cb837b244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226880281 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.226880281
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.217514070
Short name T185
Test name
Test status
Simulation time 573104452 ps
CPU time 0.93 seconds
Started Mar 17 12:59:51 PM PDT 24
Finished Mar 17 12:59:52 PM PDT 24
Peak memory 182940 kb
Host smart-a9a2e704-5bce-4421-9d7f-44d41dc716c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217514070 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.217514070
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.2405272844
Short name T53
Test name
Test status
Simulation time 45747294829 ps
CPU time 63.76 seconds
Started Mar 17 12:59:59 PM PDT 24
Finished Mar 17 01:01:04 PM PDT 24
Peak memory 193560 kb
Host smart-1522f7a3-a712-4451-88cd-430fa8cbdf54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405272844 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_
all.2405272844
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/25.aon_timer_jump.2484974486
Short name T243
Test name
Test status
Simulation time 614002498 ps
CPU time 0.62 seconds
Started Mar 17 12:59:44 PM PDT 24
Finished Mar 17 12:59:45 PM PDT 24
Peak memory 182976 kb
Host smart-96fda476-d973-429a-adbc-f5ee193624e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484974486 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.2484974486
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.1406302644
Short name T265
Test name
Test status
Simulation time 29917298101 ps
CPU time 44.27 seconds
Started Mar 17 12:59:58 PM PDT 24
Finished Mar 17 01:00:43 PM PDT 24
Peak memory 183016 kb
Host smart-dfa13752-5cd1-4569-b716-e671f35aeedf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406302644 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.1406302644
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.3630834017
Short name T157
Test name
Test status
Simulation time 428832935 ps
CPU time 0.71 seconds
Started Mar 17 12:59:44 PM PDT 24
Finished Mar 17 12:59:45 PM PDT 24
Peak memory 182964 kb
Host smart-d5025606-4653-4acb-bb36-6a785ceb0362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630834017 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.3630834017
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.299187556
Short name T28
Test name
Test status
Simulation time 50013722700 ps
CPU time 39.84 seconds
Started Mar 17 01:00:05 PM PDT 24
Finished Mar 17 01:00:45 PM PDT 24
Peak memory 183072 kb
Host smart-5de12864-48d3-4243-aea7-6ae656e3306c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299187556 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_a
ll.299187556
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.3920451064
Short name T83
Test name
Test status
Simulation time 20099739717 ps
CPU time 148.43 seconds
Started Mar 17 12:59:42 PM PDT 24
Finished Mar 17 01:02:11 PM PDT 24
Peak memory 197912 kb
Host smart-9d4d83ae-cd00-45fc-aaa3-01444a83ea30
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920451064 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.3920451064
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.aon_timer_jump.796597900
Short name T175
Test name
Test status
Simulation time 500394401 ps
CPU time 1.28 seconds
Started Mar 17 12:59:44 PM PDT 24
Finished Mar 17 12:59:45 PM PDT 24
Peak memory 183024 kb
Host smart-6620afe0-def4-4e06-b0ea-a210e4ed08ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796597900 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.796597900
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.3065495976
Short name T223
Test name
Test status
Simulation time 17347982398 ps
CPU time 7.01 seconds
Started Mar 17 12:59:47 PM PDT 24
Finished Mar 17 12:59:54 PM PDT 24
Peak memory 183004 kb
Host smart-6a8ecef9-bf1b-4931-a78c-7a0a4c52b2a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065495976 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.3065495976
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.3921057662
Short name T176
Test name
Test status
Simulation time 507809350 ps
CPU time 0.74 seconds
Started Mar 17 12:59:42 PM PDT 24
Finished Mar 17 12:59:43 PM PDT 24
Peak memory 182932 kb
Host smart-e757e3ee-8360-4aa6-9b8a-b129d6bdfbf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921057662 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.3921057662
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.2002397417
Short name T221
Test name
Test status
Simulation time 253879558547 ps
CPU time 327.26 seconds
Started Mar 17 12:59:49 PM PDT 24
Finished Mar 17 01:05:16 PM PDT 24
Peak memory 194288 kb
Host smart-6045f38e-811d-4cb6-83b8-eead1e12982a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002397417 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_
all.2002397417
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.27862272
Short name T193
Test name
Test status
Simulation time 69967979887 ps
CPU time 723.33 seconds
Started Mar 17 01:00:07 PM PDT 24
Finished Mar 17 01:12:10 PM PDT 24
Peak memory 199944 kb
Host smart-3f56fbe8-9152-412a-9793-069825a443ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27862272 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.27862272
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_jump.252753743
Short name T120
Test name
Test status
Simulation time 412646129 ps
CPU time 0.74 seconds
Started Mar 17 12:59:43 PM PDT 24
Finished Mar 17 12:59:44 PM PDT 24
Peak memory 182944 kb
Host smart-042564a7-9552-40cd-bc58-d8605843c8d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252753743 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.252753743
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.628530169
Short name T238
Test name
Test status
Simulation time 18189786245 ps
CPU time 25.23 seconds
Started Mar 17 12:59:44 PM PDT 24
Finished Mar 17 01:00:10 PM PDT 24
Peak memory 182988 kb
Host smart-2c23354c-15c2-4727-ba65-44a6766c61aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628530169 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.628530169
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.1178815213
Short name T227
Test name
Test status
Simulation time 559131294 ps
CPU time 1.37 seconds
Started Mar 17 12:59:49 PM PDT 24
Finished Mar 17 12:59:51 PM PDT 24
Peak memory 182920 kb
Host smart-04af92ab-81a0-42ce-8b07-e019648a146b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178815213 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.1178815213
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.691085479
Short name T216
Test name
Test status
Simulation time 291662334570 ps
CPU time 1614.86 seconds
Started Mar 17 12:59:44 PM PDT 24
Finished Mar 17 01:26:39 PM PDT 24
Peak memory 212128 kb
Host smart-d63e75ce-1277-4cd6-983e-5a8a0ecaa7a6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691085479 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.691085479
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_jump.2718750074
Short name T136
Test name
Test status
Simulation time 404098443 ps
CPU time 0.86 seconds
Started Mar 17 12:59:47 PM PDT 24
Finished Mar 17 12:59:48 PM PDT 24
Peak memory 182948 kb
Host smart-3ca7dde8-f3aa-410a-9366-fcec5ff4ffa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718750074 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.2718750074
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.2148962705
Short name T179
Test name
Test status
Simulation time 40409435305 ps
CPU time 61.48 seconds
Started Mar 17 12:59:44 PM PDT 24
Finished Mar 17 01:00:46 PM PDT 24
Peak memory 183080 kb
Host smart-066a66e0-5e14-42e0-99d8-0efc2b42d248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148962705 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.2148962705
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.3192705630
Short name T226
Test name
Test status
Simulation time 705994930 ps
CPU time 0.67 seconds
Started Mar 17 12:59:55 PM PDT 24
Finished Mar 17 12:59:56 PM PDT 24
Peak memory 182976 kb
Host smart-dbd984e8-c2c0-4a97-8f1e-861856c47cd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192705630 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.3192705630
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.3748841694
Short name T148
Test name
Test status
Simulation time 130589470853 ps
CPU time 45.49 seconds
Started Mar 17 12:59:58 PM PDT 24
Finished Mar 17 01:00:44 PM PDT 24
Peak memory 193800 kb
Host smart-a916f592-e271-4451-ac44-b7d74d6ca646
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748841694 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_
all.3748841694
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.2296931090
Short name T10
Test name
Test status
Simulation time 126494376747 ps
CPU time 230.72 seconds
Started Mar 17 12:59:49 PM PDT 24
Finished Mar 17 01:03:40 PM PDT 24
Peak memory 197920 kb
Host smart-4bf94185-e325-4a77-8a36-a419b23c9d49
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296931090 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.2296931090
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.aon_timer_jump.1510349014
Short name T109
Test name
Test status
Simulation time 557587765 ps
CPU time 1.48 seconds
Started Mar 17 12:59:58 PM PDT 24
Finished Mar 17 01:00:00 PM PDT 24
Peak memory 182960 kb
Host smart-2a0a15c1-7f94-44ae-87f8-63bd2a5e2619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510349014 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.1510349014
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.1549854310
Short name T278
Test name
Test status
Simulation time 11302885011 ps
CPU time 9.48 seconds
Started Mar 17 12:59:56 PM PDT 24
Finished Mar 17 01:00:06 PM PDT 24
Peak memory 183296 kb
Host smart-ae8e2859-94ea-4c8d-b292-f0f69f884462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549854310 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.1549854310
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.2031436293
Short name T112
Test name
Test status
Simulation time 331619744 ps
CPU time 0.82 seconds
Started Mar 17 12:59:51 PM PDT 24
Finished Mar 17 12:59:52 PM PDT 24
Peak memory 182952 kb
Host smart-2fe92248-91b2-43e9-8233-ff71412a4e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031436293 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.2031436293
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.667426457
Short name T138
Test name
Test status
Simulation time 104834225176 ps
CPU time 149.9 seconds
Started Mar 17 01:00:13 PM PDT 24
Finished Mar 17 01:02:43 PM PDT 24
Peak memory 183020 kb
Host smart-ccd5824c-7fd4-4384-8d9f-46df139bcf72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667426457 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_a
ll.667426457
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.3725610241
Short name T29
Test name
Test status
Simulation time 44282708876 ps
CPU time 468.41 seconds
Started Mar 17 12:59:52 PM PDT 24
Finished Mar 17 01:07:41 PM PDT 24
Peak memory 197924 kb
Host smart-252c33e9-0c2c-450e-a829-b6d4d119d336
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725610241 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.3725610241
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.aon_timer_jump.1680031657
Short name T261
Test name
Test status
Simulation time 596883279 ps
CPU time 0.78 seconds
Started Mar 17 12:59:30 PM PDT 24
Finished Mar 17 12:59:31 PM PDT 24
Peak memory 182932 kb
Host smart-f924af88-e1eb-4f57-8f9c-dc5ffb4175ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680031657 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.1680031657
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.877487405
Short name T232
Test name
Test status
Simulation time 49693642655 ps
CPU time 19.6 seconds
Started Mar 17 12:59:38 PM PDT 24
Finished Mar 17 12:59:58 PM PDT 24
Peak memory 183036 kb
Host smart-8b20e839-3232-4ba0-bb32-e20aaa1c3523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877487405 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.877487405
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.2584613649
Short name T15
Test name
Test status
Simulation time 7971686116 ps
CPU time 4.62 seconds
Started Mar 17 12:59:34 PM PDT 24
Finished Mar 17 12:59:39 PM PDT 24
Peak memory 214916 kb
Host smart-4906b564-6610-42ba-9ba9-b35c4638b52e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584613649 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.2584613649
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.3871365519
Short name T115
Test name
Test status
Simulation time 422727714 ps
CPU time 0.71 seconds
Started Mar 17 12:59:31 PM PDT 24
Finished Mar 17 12:59:32 PM PDT 24
Peak memory 183020 kb
Host smart-b52853d4-502a-4115-9360-f20410c497de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871365519 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.3871365519
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.2038131670
Short name T199
Test name
Test status
Simulation time 114886528492 ps
CPU time 88.84 seconds
Started Mar 17 12:59:30 PM PDT 24
Finished Mar 17 01:01:00 PM PDT 24
Peak memory 193344 kb
Host smart-7f13b7b1-aaa5-411b-9502-3a3e2ef8a83e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038131670 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_a
ll.2038131670
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.1512024314
Short name T183
Test name
Test status
Simulation time 76705085091 ps
CPU time 232.36 seconds
Started Mar 17 12:59:29 PM PDT 24
Finished Mar 17 01:03:21 PM PDT 24
Peak memory 197968 kb
Host smart-e1dbdaa6-5a58-45c6-9fc3-cd72d723e695
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512024314 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.1512024314
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_jump.1418134410
Short name T122
Test name
Test status
Simulation time 482284304 ps
CPU time 1 seconds
Started Mar 17 12:59:48 PM PDT 24
Finished Mar 17 12:59:49 PM PDT 24
Peak memory 183016 kb
Host smart-c29adbfd-d925-4919-86d0-c4c7df852d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418134410 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.1418134410
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.3096521428
Short name T158
Test name
Test status
Simulation time 28599125473 ps
CPU time 47.08 seconds
Started Mar 17 12:59:50 PM PDT 24
Finished Mar 17 01:00:38 PM PDT 24
Peak memory 182992 kb
Host smart-3e168899-db3f-4e9b-a3ca-46c1c73a5baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096521428 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.3096521428
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.1308707124
Short name T160
Test name
Test status
Simulation time 380015901 ps
CPU time 0.71 seconds
Started Mar 17 12:59:46 PM PDT 24
Finished Mar 17 12:59:47 PM PDT 24
Peak memory 182976 kb
Host smart-32a97f58-0940-49a4-937f-a69b0ed2b279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308707124 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.1308707124
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.554979121
Short name T263
Test name
Test status
Simulation time 98375480854 ps
CPU time 145.11 seconds
Started Mar 17 01:00:00 PM PDT 24
Finished Mar 17 01:02:25 PM PDT 24
Peak memory 193868 kb
Host smart-f72a3661-5435-40a9-b541-757fb95fca74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554979121 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_a
ll.554979121
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_jump.1895359410
Short name T44
Test name
Test status
Simulation time 369756112 ps
CPU time 0.61 seconds
Started Mar 17 12:59:49 PM PDT 24
Finished Mar 17 12:59:50 PM PDT 24
Peak memory 182988 kb
Host smart-9bdc0b18-5e9c-4c87-8bb2-4a6502d41eec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895359410 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.1895359410
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.2971376045
Short name T146
Test name
Test status
Simulation time 2351407956 ps
CPU time 3.62 seconds
Started Mar 17 12:59:54 PM PDT 24
Finished Mar 17 12:59:58 PM PDT 24
Peak memory 183080 kb
Host smart-27791bdf-fdde-4235-95ae-42f9598b3c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971376045 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.2971376045
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.1115980478
Short name T48
Test name
Test status
Simulation time 602344971 ps
CPU time 1 seconds
Started Mar 17 01:00:04 PM PDT 24
Finished Mar 17 01:00:06 PM PDT 24
Peak memory 182924 kb
Host smart-27baaad0-4cd9-4943-b710-1ae1949591ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115980478 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.1115980478
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.3346587842
Short name T269
Test name
Test status
Simulation time 113545421042 ps
CPU time 46.38 seconds
Started Mar 17 12:59:50 PM PDT 24
Finished Mar 17 01:00:36 PM PDT 24
Peak memory 194512 kb
Host smart-dea68a66-84e6-4368-8660-726c86a68953
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346587842 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_
all.3346587842
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.746474079
Short name T84
Test name
Test status
Simulation time 1147968056574 ps
CPU time 503.29 seconds
Started Mar 17 12:59:54 PM PDT 24
Finished Mar 17 01:08:17 PM PDT 24
Peak memory 214064 kb
Host smart-55fd6316-6f72-47a4-8dca-2cc229020605
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746474079 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.746474079
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.aon_timer_jump.3800347723
Short name T161
Test name
Test status
Simulation time 645987829 ps
CPU time 0.64 seconds
Started Mar 17 01:00:06 PM PDT 24
Finished Mar 17 01:00:07 PM PDT 24
Peak memory 182928 kb
Host smart-37e29266-0148-46d0-a244-306e41f485c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800347723 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.3800347723
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.749641158
Short name T211
Test name
Test status
Simulation time 36033086357 ps
CPU time 57.45 seconds
Started Mar 17 12:59:53 PM PDT 24
Finished Mar 17 01:00:51 PM PDT 24
Peak memory 183072 kb
Host smart-c90cc837-92de-4772-a40f-8c597dea8844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749641158 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.749641158
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.2118503315
Short name T20
Test name
Test status
Simulation time 570939453 ps
CPU time 0.79 seconds
Started Mar 17 12:59:48 PM PDT 24
Finished Mar 17 12:59:48 PM PDT 24
Peak memory 182932 kb
Host smart-0ccfb0ec-8f0a-4205-9581-6c2548d3d6d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118503315 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.2118503315
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.1619399559
Short name T189
Test name
Test status
Simulation time 45610675411 ps
CPU time 17.37 seconds
Started Mar 17 01:00:08 PM PDT 24
Finished Mar 17 01:00:26 PM PDT 24
Peak memory 182952 kb
Host smart-ea6defe1-866b-44f1-a582-2fba72e93779
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619399559 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_
all.1619399559
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_jump.1501666287
Short name T273
Test name
Test status
Simulation time 438515849 ps
CPU time 0.85 seconds
Started Mar 17 12:59:49 PM PDT 24
Finished Mar 17 12:59:50 PM PDT 24
Peak memory 182948 kb
Host smart-f77d8ff7-cfa9-4504-ab9e-1a30295c149d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501666287 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.1501666287
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.32833882
Short name T195
Test name
Test status
Simulation time 27302187044 ps
CPU time 35.26 seconds
Started Mar 17 01:00:04 PM PDT 24
Finished Mar 17 01:00:39 PM PDT 24
Peak memory 182992 kb
Host smart-79031054-07a3-418f-a86e-2642f1616ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32833882 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.32833882
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.371682103
Short name T220
Test name
Test status
Simulation time 440440318 ps
CPU time 1.21 seconds
Started Mar 17 01:00:03 PM PDT 24
Finished Mar 17 01:00:04 PM PDT 24
Peak memory 182936 kb
Host smart-73390cf3-6689-4b4a-96cc-1ac0b6c24491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371682103 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.371682103
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.160497324
Short name T181
Test name
Test status
Simulation time 272907668004 ps
CPU time 196.85 seconds
Started Mar 17 01:00:07 PM PDT 24
Finished Mar 17 01:03:24 PM PDT 24
Peak memory 183048 kb
Host smart-1094efd9-d12d-48bd-8897-5e3e4fce13d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160497324 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_a
ll.160497324
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.1021352484
Short name T86
Test name
Test status
Simulation time 200465524394 ps
CPU time 1079.81 seconds
Started Mar 17 01:00:09 PM PDT 24
Finished Mar 17 01:18:09 PM PDT 24
Peak memory 205132 kb
Host smart-ae543a61-f870-4afe-a8c5-57187fd2c971
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021352484 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.1021352484
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.aon_timer_jump.3271271205
Short name T167
Test name
Test status
Simulation time 386392919 ps
CPU time 1.09 seconds
Started Mar 17 12:59:51 PM PDT 24
Finished Mar 17 12:59:52 PM PDT 24
Peak memory 182892 kb
Host smart-1058a13d-2431-4215-b1a3-fe5df70f41ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271271205 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.3271271205
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.2700138791
Short name T151
Test name
Test status
Simulation time 55008749897 ps
CPU time 77.33 seconds
Started Mar 17 01:00:00 PM PDT 24
Finished Mar 17 01:01:17 PM PDT 24
Peak memory 183040 kb
Host smart-b77c242d-22c4-4158-934f-03706a491a17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700138791 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.2700138791
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.641438519
Short name T219
Test name
Test status
Simulation time 416278749 ps
CPU time 1.06 seconds
Started Mar 17 12:59:51 PM PDT 24
Finished Mar 17 12:59:52 PM PDT 24
Peak memory 182888 kb
Host smart-07b691a2-d0e3-455a-bb04-f4eccc3fb0b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641438519 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.641438519
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.555699555
Short name T152
Test name
Test status
Simulation time 159037100277 ps
CPU time 63.68 seconds
Started Mar 17 12:59:46 PM PDT 24
Finished Mar 17 01:00:50 PM PDT 24
Peak memory 193668 kb
Host smart-68a8a893-e931-475f-aa97-701f481ecf2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555699555 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_a
ll.555699555
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.1397485548
Short name T89
Test name
Test status
Simulation time 102530078590 ps
CPU time 185.44 seconds
Started Mar 17 12:59:59 PM PDT 24
Finished Mar 17 01:03:05 PM PDT 24
Peak memory 197976 kb
Host smart-d8339de3-f482-48b9-8adf-7ca598543c85
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397485548 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.1397485548
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.aon_timer_jump.1208382263
Short name T125
Test name
Test status
Simulation time 363208885 ps
CPU time 0.94 seconds
Started Mar 17 12:59:59 PM PDT 24
Finished Mar 17 01:00:00 PM PDT 24
Peak memory 182980 kb
Host smart-e01a20e4-6453-487c-a127-9b0da4f4a309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208382263 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.1208382263
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.1414860682
Short name T237
Test name
Test status
Simulation time 13701924012 ps
CPU time 2.54 seconds
Started Mar 17 01:00:13 PM PDT 24
Finished Mar 17 01:00:16 PM PDT 24
Peak memory 183064 kb
Host smart-b5eeb543-2e41-4696-9b41-624fffceb19e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414860682 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.1414860682
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.4087565013
Short name T233
Test name
Test status
Simulation time 480679054 ps
CPU time 1.24 seconds
Started Mar 17 12:59:54 PM PDT 24
Finished Mar 17 12:59:56 PM PDT 24
Peak memory 183004 kb
Host smart-8e7d4ed9-117c-480a-95ef-f0da4007a6a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087565013 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.4087565013
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.3305952675
Short name T266
Test name
Test status
Simulation time 43083161654 ps
CPU time 45.71 seconds
Started Mar 17 01:00:00 PM PDT 24
Finished Mar 17 01:00:46 PM PDT 24
Peak memory 183044 kb
Host smart-95bc3d6d-0dc7-401f-81e5-766250d5d39a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305952675 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_
all.3305952675
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.80475105
Short name T246
Test name
Test status
Simulation time 17551896958 ps
CPU time 173.47 seconds
Started Mar 17 12:59:49 PM PDT 24
Finished Mar 17 01:02:42 PM PDT 24
Peak memory 197832 kb
Host smart-07e389fe-a6f6-411c-9650-af4aa9de90c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80475105 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.80475105
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.aon_timer_jump.2872416656
Short name T198
Test name
Test status
Simulation time 468478770 ps
CPU time 0.91 seconds
Started Mar 17 12:59:49 PM PDT 24
Finished Mar 17 12:59:50 PM PDT 24
Peak memory 183008 kb
Host smart-63c89097-b6b0-4774-94c3-eefe8fe40492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872416656 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.2872416656
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.1998449430
Short name T225
Test name
Test status
Simulation time 35829409367 ps
CPU time 11.38 seconds
Started Mar 17 12:59:50 PM PDT 24
Finished Mar 17 01:00:01 PM PDT 24
Peak memory 183076 kb
Host smart-b5f33852-2651-4276-85ef-ea5a45018636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998449430 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.1998449430
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.1089725176
Short name T26
Test name
Test status
Simulation time 490006343 ps
CPU time 0.74 seconds
Started Mar 17 12:59:59 PM PDT 24
Finished Mar 17 01:00:00 PM PDT 24
Peak memory 182972 kb
Host smart-c42678b6-31f9-481c-941f-b19e07bc34d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089725176 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.1089725176
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.3001787962
Short name T130
Test name
Test status
Simulation time 83786624419 ps
CPU time 29.88 seconds
Started Mar 17 12:59:58 PM PDT 24
Finished Mar 17 01:00:28 PM PDT 24
Peak memory 194416 kb
Host smart-6efeb0e3-0245-4280-9457-8f5a1804db06
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001787962 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_
all.3001787962
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.1808247346
Short name T40
Test name
Test status
Simulation time 345385203757 ps
CPU time 882.44 seconds
Started Mar 17 12:59:53 PM PDT 24
Finished Mar 17 01:14:36 PM PDT 24
Peak memory 211336 kb
Host smart-e8476670-107c-43fc-918f-2bcc4619ed3c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808247346 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.1808247346
Directory /workspace/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.aon_timer_jump.470888879
Short name T19
Test name
Test status
Simulation time 400214258 ps
CPU time 1.06 seconds
Started Mar 17 12:59:50 PM PDT 24
Finished Mar 17 12:59:52 PM PDT 24
Peak memory 183020 kb
Host smart-67ad5201-6dd0-4056-abc1-65177f6dbf15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470888879 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.470888879
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.367389644
Short name T275
Test name
Test status
Simulation time 22653162266 ps
CPU time 34.48 seconds
Started Mar 17 01:00:15 PM PDT 24
Finished Mar 17 01:00:50 PM PDT 24
Peak memory 182988 kb
Host smart-7af93df1-8e56-4fef-8885-b7a6c5df3895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367389644 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.367389644
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.920645139
Short name T21
Test name
Test status
Simulation time 499499559 ps
CPU time 0.82 seconds
Started Mar 17 01:00:07 PM PDT 24
Finished Mar 17 01:00:08 PM PDT 24
Peak memory 182992 kb
Host smart-fd960c6e-3782-439e-867e-9cd6ae7aaf9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920645139 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.920645139
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.644992416
Short name T47
Test name
Test status
Simulation time 129821669438 ps
CPU time 210.29 seconds
Started Mar 17 12:59:56 PM PDT 24
Finished Mar 17 01:03:26 PM PDT 24
Peak memory 191220 kb
Host smart-5ef2742f-c629-44d8-9d11-db0e4afaa8c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644992416 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_a
ll.644992416
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.141158408
Short name T188
Test name
Test status
Simulation time 69147629204 ps
CPU time 202 seconds
Started Mar 17 12:59:54 PM PDT 24
Finished Mar 17 01:03:17 PM PDT 24
Peak memory 198008 kb
Host smart-1421102b-1bdd-4322-b00a-e0eab51095a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141158408 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.141158408
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.aon_timer_jump.706317228
Short name T231
Test name
Test status
Simulation time 439646202 ps
CPU time 0.8 seconds
Started Mar 17 12:59:48 PM PDT 24
Finished Mar 17 12:59:49 PM PDT 24
Peak memory 182956 kb
Host smart-596e72d0-fc0b-4094-a12c-f6aa59d461d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706317228 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.706317228
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.2017335284
Short name T192
Test name
Test status
Simulation time 6113507284 ps
CPU time 5.11 seconds
Started Mar 17 01:00:02 PM PDT 24
Finished Mar 17 01:00:07 PM PDT 24
Peak memory 183056 kb
Host smart-e399312d-72f0-46bd-80fd-3b6f262f1b2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017335284 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.2017335284
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.4066474789
Short name T137
Test name
Test status
Simulation time 379133344 ps
CPU time 1.12 seconds
Started Mar 17 01:00:03 PM PDT 24
Finished Mar 17 01:00:04 PM PDT 24
Peak memory 182956 kb
Host smart-e202b582-fde5-4f32-9646-79ffa6e7d212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066474789 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.4066474789
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.6373844
Short name T5
Test name
Test status
Simulation time 103228029287 ps
CPU time 10.02 seconds
Started Mar 17 12:59:54 PM PDT 24
Finished Mar 17 01:00:05 PM PDT 24
Peak memory 193896 kb
Host smart-d7485f26-cace-44e8-9c85-b567aec76392
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6373844 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all.6373844
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.299967503
Short name T222
Test name
Test status
Simulation time 233083684953 ps
CPU time 109.29 seconds
Started Mar 17 12:59:59 PM PDT 24
Finished Mar 17 01:01:48 PM PDT 24
Peak memory 197868 kb
Host smart-372390f4-12b3-4cd4-a5dd-770105272498
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299967503 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand_reset.299967503
Directory /workspace/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.aon_timer_jump.2326695620
Short name T100
Test name
Test status
Simulation time 340150602 ps
CPU time 1.1 seconds
Started Mar 17 12:59:49 PM PDT 24
Finished Mar 17 12:59:50 PM PDT 24
Peak memory 182908 kb
Host smart-26885c75-0baa-47d8-9bab-cff461969abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326695620 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.2326695620
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.3172821021
Short name T45
Test name
Test status
Simulation time 52818744512 ps
CPU time 78.19 seconds
Started Mar 17 12:59:59 PM PDT 24
Finished Mar 17 01:01:17 PM PDT 24
Peak memory 183020 kb
Host smart-d8c50c1b-c45f-4e6e-9d9f-db43c4c93778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172821021 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.3172821021
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.3347567976
Short name T127
Test name
Test status
Simulation time 371073166 ps
CPU time 1.04 seconds
Started Mar 17 12:59:48 PM PDT 24
Finished Mar 17 12:59:49 PM PDT 24
Peak memory 182972 kb
Host smart-009bb7c9-9308-4307-97a5-8b36300d5638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347567976 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.3347567976
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.3590063879
Short name T209
Test name
Test status
Simulation time 185958303399 ps
CPU time 269.23 seconds
Started Mar 17 01:00:13 PM PDT 24
Finished Mar 17 01:04:43 PM PDT 24
Peak memory 192752 kb
Host smart-39b0c848-aa4e-4144-a9d7-90d2ea36ec09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590063879 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_
all.3590063879
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.4197689230
Short name T11
Test name
Test status
Simulation time 219510438129 ps
CPU time 476.44 seconds
Started Mar 17 01:00:03 PM PDT 24
Finished Mar 17 01:08:00 PM PDT 24
Peak memory 197940 kb
Host smart-8404e71b-b99f-4a56-866c-f563803b4d92
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197689230 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.4197689230
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_jump.2551791538
Short name T42
Test name
Test status
Simulation time 375267503 ps
CPU time 1.04 seconds
Started Mar 17 12:59:35 PM PDT 24
Finished Mar 17 12:59:37 PM PDT 24
Peak memory 182932 kb
Host smart-03db53c1-a2a8-4658-b494-aa374a3e26ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551791538 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.2551791538
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.2633128010
Short name T252
Test name
Test status
Simulation time 27688503256 ps
CPU time 10.45 seconds
Started Mar 17 12:59:29 PM PDT 24
Finished Mar 17 12:59:39 PM PDT 24
Peak memory 182992 kb
Host smart-7076d68e-f047-45ec-b702-92f40edb6066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633128010 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.2633128010
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.32902248
Short name T16
Test name
Test status
Simulation time 8906481471 ps
CPU time 4.12 seconds
Started Mar 17 12:59:29 PM PDT 24
Finished Mar 17 12:59:33 PM PDT 24
Peak memory 214892 kb
Host smart-9aa6b8f1-e6cd-4a03-b9f6-7f7e4a15cc70
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32902248 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.32902248
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.818576900
Short name T139
Test name
Test status
Simulation time 436782042 ps
CPU time 0.93 seconds
Started Mar 17 12:59:35 PM PDT 24
Finished Mar 17 12:59:36 PM PDT 24
Peak memory 182864 kb
Host smart-ac0d0f3a-ec9d-4529-9997-e54a2477021f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818576900 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.818576900
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.1996955397
Short name T129
Test name
Test status
Simulation time 35766933967 ps
CPU time 45.01 seconds
Started Mar 17 12:59:34 PM PDT 24
Finished Mar 17 01:00:20 PM PDT 24
Peak memory 193152 kb
Host smart-213021fa-7199-4128-ae3c-bbaee5e68efd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996955397 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_a
ll.1996955397
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.10405239
Short name T87
Test name
Test status
Simulation time 58407531634 ps
CPU time 444.62 seconds
Started Mar 17 12:59:32 PM PDT 24
Finished Mar 17 01:06:57 PM PDT 24
Peak memory 197896 kb
Host smart-6da7a604-d17c-41fb-b217-4a63e23eb1ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10405239 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.10405239
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.aon_timer_jump.1015474438
Short name T191
Test name
Test status
Simulation time 443218067 ps
CPU time 0.88 seconds
Started Mar 17 01:00:06 PM PDT 24
Finished Mar 17 01:00:08 PM PDT 24
Peak memory 182932 kb
Host smart-df0674b2-e792-437d-8712-5e10c2c11184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015474438 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.1015474438
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.3080593130
Short name T204
Test name
Test status
Simulation time 28542854815 ps
CPU time 24.05 seconds
Started Mar 17 12:59:57 PM PDT 24
Finished Mar 17 01:00:21 PM PDT 24
Peak memory 182992 kb
Host smart-6c16197a-c6a2-4ff4-9f3f-831608707d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080593130 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.3080593130
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.1567149906
Short name T257
Test name
Test status
Simulation time 483717995 ps
CPU time 1.18 seconds
Started Mar 17 12:59:52 PM PDT 24
Finished Mar 17 12:59:54 PM PDT 24
Peak memory 182940 kb
Host smart-5f86c5d4-95c1-49bf-919b-dc7bb44b0571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567149906 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.1567149906
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.917141241
Short name T171
Test name
Test status
Simulation time 79275196558 ps
CPU time 120.12 seconds
Started Mar 17 12:59:57 PM PDT 24
Finished Mar 17 01:01:57 PM PDT 24
Peak memory 182952 kb
Host smart-44111429-af38-4479-bba9-b10983ed0774
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917141241 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_a
ll.917141241
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_jump.2755168731
Short name T262
Test name
Test status
Simulation time 642451897 ps
CPU time 0.64 seconds
Started Mar 17 12:59:56 PM PDT 24
Finished Mar 17 12:59:57 PM PDT 24
Peak memory 182988 kb
Host smart-f2e3437a-16f0-4a7b-bdd3-f54835ecb671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755168731 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.2755168731
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.703474494
Short name T132
Test name
Test status
Simulation time 11263731513 ps
CPU time 2.71 seconds
Started Mar 17 12:59:54 PM PDT 24
Finished Mar 17 12:59:57 PM PDT 24
Peak memory 182992 kb
Host smart-2aa1cdb4-06e5-4c46-a838-d9912594d569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703474494 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.703474494
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.2499177957
Short name T180
Test name
Test status
Simulation time 548212125 ps
CPU time 0.9 seconds
Started Mar 17 01:00:09 PM PDT 24
Finished Mar 17 01:00:10 PM PDT 24
Peak memory 182916 kb
Host smart-39d11e54-fd2f-4096-b625-98d591ab34bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499177957 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.2499177957
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.1672489158
Short name T31
Test name
Test status
Simulation time 224273018242 ps
CPU time 289.43 seconds
Started Mar 17 01:00:11 PM PDT 24
Finished Mar 17 01:05:01 PM PDT 24
Peak memory 183024 kb
Host smart-9a3f3be6-7093-40bd-b89e-c0ae9bafe390
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672489158 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_
all.1672489158
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.1605774096
Short name T39
Test name
Test status
Simulation time 106354001852 ps
CPU time 134.6 seconds
Started Mar 17 01:00:02 PM PDT 24
Finished Mar 17 01:02:17 PM PDT 24
Peak memory 197968 kb
Host smart-bb60e5bf-93b9-4ee4-b4b4-ccf601ef662b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605774096 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.1605774096
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.aon_timer_jump.2176418765
Short name T101
Test name
Test status
Simulation time 462135033 ps
CPU time 1.28 seconds
Started Mar 17 01:00:12 PM PDT 24
Finished Mar 17 01:00:14 PM PDT 24
Peak memory 182960 kb
Host smart-7f370773-7c2b-441e-b4df-fc28a151e5dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176418765 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.2176418765
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.347105785
Short name T248
Test name
Test status
Simulation time 52093905303 ps
CPU time 66.66 seconds
Started Mar 17 01:00:10 PM PDT 24
Finished Mar 17 01:01:17 PM PDT 24
Peak memory 183056 kb
Host smart-203ce287-4da0-4521-9694-a9696b0992d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347105785 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.347105785
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.2273703031
Short name T2
Test name
Test status
Simulation time 413462211 ps
CPU time 0.71 seconds
Started Mar 17 12:59:56 PM PDT 24
Finished Mar 17 12:59:57 PM PDT 24
Peak memory 183008 kb
Host smart-d1d8c90e-fe1d-4281-af62-f0d6ea17fb7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273703031 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.2273703031
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.92090343
Short name T116
Test name
Test status
Simulation time 82304207747 ps
CPU time 34.39 seconds
Started Mar 17 12:59:57 PM PDT 24
Finished Mar 17 01:00:31 PM PDT 24
Peak memory 193776 kb
Host smart-5a059289-e060-4186-ab10-9017791b9aa2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92090343 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_al
l.92090343
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.1165543479
Short name T9
Test name
Test status
Simulation time 12503397784 ps
CPU time 83.78 seconds
Started Mar 17 12:59:54 PM PDT 24
Finished Mar 17 01:01:18 PM PDT 24
Peak memory 197964 kb
Host smart-2f4e3812-1ab8-41c1-852e-0b9f8381e1b9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165543479 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.1165543479
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.aon_timer_jump.2557519644
Short name T186
Test name
Test status
Simulation time 574765070 ps
CPU time 0.59 seconds
Started Mar 17 01:00:13 PM PDT 24
Finished Mar 17 01:00:13 PM PDT 24
Peak memory 182956 kb
Host smart-89fa9f59-8837-4288-bfc0-c288141ad021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557519644 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.2557519644
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.1704435176
Short name T49
Test name
Test status
Simulation time 5218932382 ps
CPU time 2.63 seconds
Started Mar 17 01:00:05 PM PDT 24
Finished Mar 17 01:00:08 PM PDT 24
Peak memory 183056 kb
Host smart-9162cd7b-8207-4441-83f2-243b7f1e7bc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704435176 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.1704435176
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.660027788
Short name T117
Test name
Test status
Simulation time 461021954 ps
CPU time 0.9 seconds
Started Mar 17 12:59:55 PM PDT 24
Finished Mar 17 12:59:57 PM PDT 24
Peak memory 183020 kb
Host smart-c8cf09b7-556d-4159-91c0-dbcaa044e162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660027788 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.660027788
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.1379227295
Short name T143
Test name
Test status
Simulation time 266183030429 ps
CPU time 107.01 seconds
Started Mar 17 12:59:52 PM PDT 24
Finished Mar 17 01:01:40 PM PDT 24
Peak memory 182996 kb
Host smart-4e8af40c-83dd-409d-92fa-8a14ae998b15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379227295 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_
all.1379227295
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.2321154092
Short name T17
Test name
Test status
Simulation time 40541566394 ps
CPU time 207.82 seconds
Started Mar 17 01:00:10 PM PDT 24
Finished Mar 17 01:03:38 PM PDT 24
Peak memory 197972 kb
Host smart-5ef3a982-681e-4165-b77a-944c0b19e0dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321154092 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.2321154092
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.aon_timer_jump.1540011409
Short name T201
Test name
Test status
Simulation time 580150757 ps
CPU time 0.79 seconds
Started Mar 17 01:00:12 PM PDT 24
Finished Mar 17 01:00:13 PM PDT 24
Peak memory 183036 kb
Host smart-48906193-547c-404c-ad60-bd76b5e881eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540011409 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.1540011409
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.3400327721
Short name T224
Test name
Test status
Simulation time 29266737740 ps
CPU time 48.75 seconds
Started Mar 17 12:59:57 PM PDT 24
Finished Mar 17 01:00:45 PM PDT 24
Peak memory 182996 kb
Host smart-86abfd08-667d-4364-a7b1-5f9b17228f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400327721 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.3400327721
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.4068714610
Short name T276
Test name
Test status
Simulation time 546182970 ps
CPU time 1.32 seconds
Started Mar 17 01:00:13 PM PDT 24
Finished Mar 17 01:00:15 PM PDT 24
Peak memory 182944 kb
Host smart-043253a6-b4a0-476c-9b08-b9010bd39bed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068714610 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.4068714610
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.1257589821
Short name T168
Test name
Test status
Simulation time 99934438062 ps
CPU time 630.43 seconds
Started Mar 17 12:59:54 PM PDT 24
Finished Mar 17 01:10:25 PM PDT 24
Peak memory 199636 kb
Host smart-2fcc1db3-97f7-4f70-ba57-3bd7fa1b9659
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257589821 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.1257589821
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.aon_timer_jump.1341360314
Short name T250
Test name
Test status
Simulation time 461226724 ps
CPU time 1.22 seconds
Started Mar 17 12:59:55 PM PDT 24
Finished Mar 17 12:59:57 PM PDT 24
Peak memory 182976 kb
Host smart-1802ad15-8b7b-440c-893d-0ce5e3bb7635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341360314 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.1341360314
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.743582869
Short name T184
Test name
Test status
Simulation time 43459186374 ps
CPU time 19.34 seconds
Started Mar 17 01:00:12 PM PDT 24
Finished Mar 17 01:00:32 PM PDT 24
Peak memory 183020 kb
Host smart-dbd34b28-a7ea-42d7-9a2c-701d0a0e6579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743582869 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.743582869
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.1316221593
Short name T169
Test name
Test status
Simulation time 620324301 ps
CPU time 0.76 seconds
Started Mar 17 12:59:56 PM PDT 24
Finished Mar 17 12:59:57 PM PDT 24
Peak memory 183012 kb
Host smart-3fe70604-f644-4e97-9fc8-0cd5ad8beef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316221593 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.1316221593
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.391298633
Short name T8
Test name
Test status
Simulation time 14855077528 ps
CPU time 4.15 seconds
Started Mar 17 12:59:55 PM PDT 24
Finished Mar 17 12:59:59 PM PDT 24
Peak memory 183064 kb
Host smart-3809ecfd-8c31-4b7a-8bda-a8b936d3f685
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391298633 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_a
ll.391298633
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.3074008023
Short name T92
Test name
Test status
Simulation time 106298188482 ps
CPU time 202.23 seconds
Started Mar 17 01:00:11 PM PDT 24
Finished Mar 17 01:03:34 PM PDT 24
Peak memory 197924 kb
Host smart-270039eb-c6f2-4897-95b4-907b34c43e11
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074008023 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.3074008023
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.aon_timer_jump.2767117218
Short name T140
Test name
Test status
Simulation time 416693835 ps
CPU time 0.73 seconds
Started Mar 17 01:00:09 PM PDT 24
Finished Mar 17 01:00:10 PM PDT 24
Peak memory 182940 kb
Host smart-c9b0153d-0824-4dd4-b3d2-71896a382cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767117218 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.2767117218
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.4293675541
Short name T194
Test name
Test status
Simulation time 13331908240 ps
CPU time 19.38 seconds
Started Mar 17 01:00:13 PM PDT 24
Finished Mar 17 01:00:33 PM PDT 24
Peak memory 183040 kb
Host smart-cff4ec73-a90f-4c3e-aa63-bb3438afb212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293675541 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.4293675541
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.4285742335
Short name T264
Test name
Test status
Simulation time 551828241 ps
CPU time 0.66 seconds
Started Mar 17 01:00:03 PM PDT 24
Finished Mar 17 01:00:03 PM PDT 24
Peak memory 182952 kb
Host smart-d7d90540-f433-407d-8e84-14e50d3fc543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285742335 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.4285742335
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.1796108510
Short name T51
Test name
Test status
Simulation time 186474827861 ps
CPU time 275 seconds
Started Mar 17 01:00:01 PM PDT 24
Finished Mar 17 01:04:36 PM PDT 24
Peak memory 193376 kb
Host smart-7eff3436-cea6-46d0-b269-522f069c0098
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796108510 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_
all.1796108510
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_jump.216380662
Short name T213
Test name
Test status
Simulation time 535496067 ps
CPU time 0.77 seconds
Started Mar 17 12:59:59 PM PDT 24
Finished Mar 17 01:00:01 PM PDT 24
Peak memory 182944 kb
Host smart-fafa5c48-2753-4310-bd6e-9be9203697e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216380662 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.216380662
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.2612604922
Short name T253
Test name
Test status
Simulation time 54577240465 ps
CPU time 43.08 seconds
Started Mar 17 01:00:04 PM PDT 24
Finished Mar 17 01:00:47 PM PDT 24
Peak memory 183056 kb
Host smart-828ea275-8d11-4f74-8585-67bceda2884f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612604922 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.2612604922
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.2806261607
Short name T18
Test name
Test status
Simulation time 598275123 ps
CPU time 1.45 seconds
Started Mar 17 01:00:14 PM PDT 24
Finished Mar 17 01:00:16 PM PDT 24
Peak memory 182936 kb
Host smart-de2777bf-f091-43e6-884b-9a5df3ad3b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806261607 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.2806261607
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.3715585594
Short name T150
Test name
Test status
Simulation time 248379062561 ps
CPU time 402.8 seconds
Started Mar 17 12:59:59 PM PDT 24
Finished Mar 17 01:06:43 PM PDT 24
Peak memory 194408 kb
Host smart-ec933644-2d46-48bf-ae3b-4a3499f476af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715585594 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_
all.3715585594
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.795779214
Short name T182
Test name
Test status
Simulation time 128307448505 ps
CPU time 906.62 seconds
Started Mar 17 01:00:11 PM PDT 24
Finished Mar 17 01:15:18 PM PDT 24
Peak memory 200600 kb
Host smart-fd1d1a41-f27f-49fc-8dfa-f4dccc432dae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795779214 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.795779214
Directory /workspace/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_jump.3806102146
Short name T105
Test name
Test status
Simulation time 348389729 ps
CPU time 0.83 seconds
Started Mar 17 12:59:55 PM PDT 24
Finished Mar 17 12:59:56 PM PDT 24
Peak memory 182956 kb
Host smart-b0dd8828-b6ee-40c8-994d-e08d206fe6fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806102146 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.3806102146
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.19894741
Short name T280
Test name
Test status
Simulation time 33173663145 ps
CPU time 48.47 seconds
Started Mar 17 01:00:13 PM PDT 24
Finished Mar 17 01:01:06 PM PDT 24
Peak memory 182988 kb
Host smart-3d0310e0-f8db-4f3e-853e-bfdf59b3ff0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19894741 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.19894741
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.1405666410
Short name T251
Test name
Test status
Simulation time 458392129 ps
CPU time 0.68 seconds
Started Mar 17 12:59:56 PM PDT 24
Finished Mar 17 12:59:57 PM PDT 24
Peak memory 182928 kb
Host smart-3f75d0a7-e465-4ad8-809e-99e9b6eedcaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405666410 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.1405666410
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.998303826
Short name T164
Test name
Test status
Simulation time 203100960682 ps
CPU time 34 seconds
Started Mar 17 12:59:55 PM PDT 24
Finished Mar 17 01:00:29 PM PDT 24
Peak memory 193644 kb
Host smart-7611b63e-e8ea-4766-8517-7200c5d03998
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998303826 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_a
ll.998303826
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.279698778
Short name T82
Test name
Test status
Simulation time 71651910621 ps
CPU time 412.62 seconds
Started Mar 17 01:00:07 PM PDT 24
Finished Mar 17 01:07:00 PM PDT 24
Peak memory 197952 kb
Host smart-31cba30e-ad4b-4386-a0aa-ca32882154a0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279698778 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.279698778
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.aon_timer_jump.2080546232
Short name T200
Test name
Test status
Simulation time 517568905 ps
CPU time 1.32 seconds
Started Mar 17 01:00:10 PM PDT 24
Finished Mar 17 01:00:12 PM PDT 24
Peak memory 182940 kb
Host smart-0b7b65b8-996f-4e45-b453-e37c3cb19bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080546232 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.2080546232
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.2412340902
Short name T230
Test name
Test status
Simulation time 26243100767 ps
CPU time 43.82 seconds
Started Mar 17 01:00:12 PM PDT 24
Finished Mar 17 01:00:57 PM PDT 24
Peak memory 183040 kb
Host smart-f56f0e06-1a46-47c0-bcd1-2f4a27c7b45c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412340902 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.2412340902
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.914801764
Short name T46
Test name
Test status
Simulation time 425718376 ps
CPU time 0.69 seconds
Started Mar 17 01:00:11 PM PDT 24
Finished Mar 17 01:00:13 PM PDT 24
Peak memory 182948 kb
Host smart-942a3eb4-384f-4c16-88c8-dbff056d707d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914801764 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.914801764
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.1423057841
Short name T272
Test name
Test status
Simulation time 171509509936 ps
CPU time 256.74 seconds
Started Mar 17 01:00:12 PM PDT 24
Finished Mar 17 01:04:29 PM PDT 24
Peak memory 195020 kb
Host smart-51edf71a-3921-4a25-a16a-200effa1972c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423057841 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_
all.1423057841
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.1862925468
Short name T93
Test name
Test status
Simulation time 131673653220 ps
CPU time 254.92 seconds
Started Mar 17 01:00:00 PM PDT 24
Finished Mar 17 01:04:16 PM PDT 24
Peak memory 197824 kb
Host smart-451ac9c6-2f93-43b4-b03e-dfe26514c312
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862925468 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.1862925468
Directory /workspace/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.aon_timer_jump.3813328266
Short name T133
Test name
Test status
Simulation time 482462136 ps
CPU time 0.94 seconds
Started Mar 17 12:59:35 PM PDT 24
Finished Mar 17 12:59:36 PM PDT 24
Peak memory 183012 kb
Host smart-c4554c68-4296-4e2f-95e3-182acb248b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813328266 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.3813328266
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.2277867929
Short name T187
Test name
Test status
Simulation time 59515844632 ps
CPU time 30.3 seconds
Started Mar 17 12:59:29 PM PDT 24
Finished Mar 17 01:00:00 PM PDT 24
Peak memory 183044 kb
Host smart-ff56a5cd-04e7-4aae-a550-c0754a98aae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277867929 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.2277867929
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.3360979019
Short name T197
Test name
Test status
Simulation time 457912049 ps
CPU time 0.59 seconds
Started Mar 17 12:59:48 PM PDT 24
Finished Mar 17 12:59:49 PM PDT 24
Peak memory 182892 kb
Host smart-176a7e24-0fea-4fe9-a97f-0610361c5cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360979019 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.3360979019
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.1065601253
Short name T121
Test name
Test status
Simulation time 101984006591 ps
CPU time 34.57 seconds
Started Mar 17 12:59:28 PM PDT 24
Finished Mar 17 01:00:03 PM PDT 24
Peak memory 191244 kb
Host smart-6549ade8-d499-415d-82a5-c8f43b772368
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065601253 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_a
ll.1065601253
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.4206504850
Short name T135
Test name
Test status
Simulation time 18520810626 ps
CPU time 90.53 seconds
Started Mar 17 12:59:57 PM PDT 24
Finished Mar 17 01:01:28 PM PDT 24
Peak memory 198000 kb
Host smart-3c8df170-246b-4490-a391-08effc8d33a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206504850 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.4206504850
Directory /workspace/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.aon_timer_jump.2249454295
Short name T107
Test name
Test status
Simulation time 427194777 ps
CPU time 0.78 seconds
Started Mar 17 12:59:29 PM PDT 24
Finished Mar 17 12:59:30 PM PDT 24
Peak memory 182928 kb
Host smart-941b73fa-7001-49e4-bc8a-9a3d4fdec728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249454295 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.2249454295
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.3319346
Short name T177
Test name
Test status
Simulation time 23237859415 ps
CPU time 37.86 seconds
Started Mar 17 12:59:30 PM PDT 24
Finished Mar 17 01:00:08 PM PDT 24
Peak memory 182952 kb
Host smart-09d51594-c98d-4496-8c27-815e3cc46796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319346 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.3319346
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.2545545691
Short name T256
Test name
Test status
Simulation time 561794147 ps
CPU time 0.7 seconds
Started Mar 17 12:59:28 PM PDT 24
Finished Mar 17 12:59:29 PM PDT 24
Peak memory 183012 kb
Host smart-f4285fe5-afc2-4f6f-8137-a6dea451ea33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545545691 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.2545545691
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.3991709530
Short name T90
Test name
Test status
Simulation time 216472535734 ps
CPU time 414.98 seconds
Started Mar 17 12:59:29 PM PDT 24
Finished Mar 17 01:06:25 PM PDT 24
Peak memory 197896 kb
Host smart-42b8bd12-f93a-4a8e-99b7-91aec06c0059
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991709530 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.3991709530
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.aon_timer_jump.3486072085
Short name T24
Test name
Test status
Simulation time 378192132 ps
CPU time 1.21 seconds
Started Mar 17 12:59:35 PM PDT 24
Finished Mar 17 12:59:36 PM PDT 24
Peak memory 183012 kb
Host smart-ba1bb917-e7c7-4b1f-bab6-071535e05fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486072085 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.3486072085
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.3298813386
Short name T30
Test name
Test status
Simulation time 27503355266 ps
CPU time 23.16 seconds
Started Mar 17 12:59:34 PM PDT 24
Finished Mar 17 12:59:57 PM PDT 24
Peak memory 183024 kb
Host smart-5c53aab0-55be-4abe-a5ad-1a1b1d06fa03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298813386 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.3298813386
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.270555118
Short name T147
Test name
Test status
Simulation time 446252161 ps
CPU time 0.71 seconds
Started Mar 17 12:59:32 PM PDT 24
Finished Mar 17 12:59:32 PM PDT 24
Peak memory 182972 kb
Host smart-1cd73fcd-8b7f-4f3b-a23b-1373826ba2f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270555118 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.270555118
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.748732023
Short name T228
Test name
Test status
Simulation time 216457082846 ps
CPU time 285.44 seconds
Started Mar 17 12:59:52 PM PDT 24
Finished Mar 17 01:04:38 PM PDT 24
Peak memory 183088 kb
Host smart-b30d97e3-53ea-48cd-874a-586ebe0d4da0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748732023 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_al
l.748732023
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.2842450505
Short name T54
Test name
Test status
Simulation time 109976285696 ps
CPU time 1035.02 seconds
Started Mar 17 12:59:31 PM PDT 24
Finished Mar 17 01:16:46 PM PDT 24
Peak memory 204256 kb
Host smart-7f67db75-ef17-41e2-a975-d1f94b3443ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842450505 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.2842450505
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.aon_timer_jump.4140790757
Short name T203
Test name
Test status
Simulation time 537209800 ps
CPU time 1.32 seconds
Started Mar 17 12:59:30 PM PDT 24
Finished Mar 17 12:59:32 PM PDT 24
Peak memory 182936 kb
Host smart-0db16d1f-4151-42e3-9d19-5007e5a89100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140790757 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.4140790757
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.458747323
Short name T170
Test name
Test status
Simulation time 45709626609 ps
CPU time 70.73 seconds
Started Mar 17 12:59:32 PM PDT 24
Finished Mar 17 01:00:43 PM PDT 24
Peak memory 183008 kb
Host smart-caa386f6-96fe-4950-8193-48bef2134f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458747323 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.458747323
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.1780862472
Short name T267
Test name
Test status
Simulation time 411634609 ps
CPU time 1.21 seconds
Started Mar 17 12:59:29 PM PDT 24
Finished Mar 17 12:59:30 PM PDT 24
Peak memory 182952 kb
Host smart-0d509747-ec44-4e67-84e0-09da980977e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780862472 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.1780862472
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.4173676630
Short name T268
Test name
Test status
Simulation time 220691725545 ps
CPU time 82.91 seconds
Started Mar 17 12:59:31 PM PDT 24
Finished Mar 17 01:00:54 PM PDT 24
Peak memory 183172 kb
Host smart-093bf5ad-ad50-4985-b085-0a3f2cf66fad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173676630 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_a
ll.4173676630
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_jump.434251067
Short name T173
Test name
Test status
Simulation time 382919530 ps
CPU time 0.67 seconds
Started Mar 17 12:59:34 PM PDT 24
Finished Mar 17 12:59:35 PM PDT 24
Peak memory 182868 kb
Host smart-d664a133-7b93-4f84-8670-75f2b7bd3f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434251067 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.434251067
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.3410954304
Short name T236
Test name
Test status
Simulation time 2497221836 ps
CPU time 2.59 seconds
Started Mar 17 12:59:36 PM PDT 24
Finished Mar 17 12:59:38 PM PDT 24
Peak memory 183000 kb
Host smart-28a280f2-edd4-420a-bc01-42a016bbb4a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410954304 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.3410954304
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.177333801
Short name T234
Test name
Test status
Simulation time 590972105 ps
CPU time 0.7 seconds
Started Mar 17 12:59:52 PM PDT 24
Finished Mar 17 12:59:53 PM PDT 24
Peak memory 183028 kb
Host smart-eb17c2dc-aaf6-43a1-aab6-8aa9e9f5c20a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177333801 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.177333801
Directory /workspace/9.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.4218292155
Short name T202
Test name
Test status
Simulation time 114439456559 ps
CPU time 11.81 seconds
Started Mar 17 12:59:34 PM PDT 24
Finished Mar 17 12:59:46 PM PDT 24
Peak memory 183040 kb
Host smart-4653ffa0-0a91-4b40-9e13-53ebcb1f726e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218292155 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_a
ll.4218292155
Directory /workspace/9.aon_timer_stress_all/latest
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