Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
92.98 99.25 93.67 100.00 98.40 99.51 67.06


Total test records in report: 419
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T99 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.454126251 Mar 19 12:27:30 PM PDT 24 Mar 19 12:27:37 PM PDT 24 13823648382 ps
T42 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.4129221493 Mar 19 12:27:29 PM PDT 24 Mar 19 12:27:37 PM PDT 24 4252137205 ps
T285 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.4034596912 Mar 19 12:27:37 PM PDT 24 Mar 19 12:27:38 PM PDT 24 884475896 ps
T43 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.2785610511 Mar 19 12:28:40 PM PDT 24 Mar 19 12:28:53 PM PDT 24 8796614676 ps
T81 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.136733798 Mar 19 12:27:41 PM PDT 24 Mar 19 12:27:47 PM PDT 24 2754363616 ps
T286 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.3360387520 Mar 19 12:27:44 PM PDT 24 Mar 19 12:27:45 PM PDT 24 431164911 ps
T287 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.260796674 Mar 19 12:27:49 PM PDT 24 Mar 19 12:27:50 PM PDT 24 374322245 ps
T44 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.748161005 Mar 19 12:27:40 PM PDT 24 Mar 19 12:27:42 PM PDT 24 4754003543 ps
T62 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.1466114689 Mar 19 12:27:47 PM PDT 24 Mar 19 12:27:55 PM PDT 24 8739260451 ps
T82 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.574195709 Mar 19 12:27:31 PM PDT 24 Mar 19 12:27:34 PM PDT 24 2002759283 ps
T288 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.1933210224 Mar 19 12:27:53 PM PDT 24 Mar 19 12:27:54 PM PDT 24 613391768 ps
T289 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.688587285 Mar 19 12:27:41 PM PDT 24 Mar 19 12:27:47 PM PDT 24 491325062 ps
T290 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.3199116150 Mar 19 12:28:00 PM PDT 24 Mar 19 12:28:01 PM PDT 24 570139175 ps
T291 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.3917026798 Mar 19 12:27:41 PM PDT 24 Mar 19 12:27:42 PM PDT 24 514843720 ps
T83 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.1282504820 Mar 19 12:27:42 PM PDT 24 Mar 19 12:27:43 PM PDT 24 2734732822 ps
T84 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.4193325737 Mar 19 12:27:39 PM PDT 24 Mar 19 12:27:40 PM PDT 24 1108892011 ps
T85 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.4161340814 Mar 19 12:27:50 PM PDT 24 Mar 19 12:27:51 PM PDT 24 2620550974 ps
T292 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.1345735576 Mar 19 12:27:44 PM PDT 24 Mar 19 12:27:45 PM PDT 24 531105050 ps
T293 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.3895028531 Mar 19 12:27:43 PM PDT 24 Mar 19 12:27:44 PM PDT 24 531032902 ps
T294 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.662157637 Mar 19 12:27:49 PM PDT 24 Mar 19 12:27:50 PM PDT 24 357537457 ps
T295 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.1711540266 Mar 19 12:28:10 PM PDT 24 Mar 19 12:28:11 PM PDT 24 446329882 ps
T116 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.3592926423 Mar 19 12:27:42 PM PDT 24 Mar 19 12:27:56 PM PDT 24 7958114704 ps
T296 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.399788067 Mar 19 12:27:41 PM PDT 24 Mar 19 12:27:42 PM PDT 24 465132373 ps
T297 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.1765876957 Mar 19 12:27:33 PM PDT 24 Mar 19 12:27:33 PM PDT 24 411913273 ps
T63 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.971224740 Mar 19 12:27:41 PM PDT 24 Mar 19 12:27:42 PM PDT 24 1348498595 ps
T298 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.2521334801 Mar 19 12:27:38 PM PDT 24 Mar 19 12:27:39 PM PDT 24 365641996 ps
T86 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.1506513571 Mar 19 12:27:30 PM PDT 24 Mar 19 12:27:34 PM PDT 24 2421538777 ps
T299 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.689227895 Mar 19 12:27:50 PM PDT 24 Mar 19 12:27:56 PM PDT 24 588234971 ps
T300 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.408957204 Mar 19 12:27:43 PM PDT 24 Mar 19 12:27:44 PM PDT 24 489358511 ps
T301 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.1891101630 Mar 19 12:27:46 PM PDT 24 Mar 19 12:27:48 PM PDT 24 530949129 ps
T302 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.3533313015 Mar 19 12:27:46 PM PDT 24 Mar 19 12:27:47 PM PDT 24 422159464 ps
T303 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.1184762047 Mar 19 12:27:29 PM PDT 24 Mar 19 12:27:37 PM PDT 24 4891554293 ps
T87 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.535202402 Mar 19 12:27:35 PM PDT 24 Mar 19 12:27:36 PM PDT 24 514542725 ps
T88 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.2437210705 Mar 19 12:27:42 PM PDT 24 Mar 19 12:27:44 PM PDT 24 945803600 ps
T304 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.2283734991 Mar 19 12:28:02 PM PDT 24 Mar 19 12:28:03 PM PDT 24 276398712 ps
T305 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.3898916433 Mar 19 12:28:07 PM PDT 24 Mar 19 12:28:08 PM PDT 24 495667835 ps
T306 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.3317132250 Mar 19 12:27:41 PM PDT 24 Mar 19 12:27:48 PM PDT 24 8710561034 ps
T307 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.1231525479 Mar 19 12:27:45 PM PDT 24 Mar 19 12:27:46 PM PDT 24 301983621 ps
T308 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.3228681482 Mar 19 12:27:43 PM PDT 24 Mar 19 12:27:50 PM PDT 24 511154475 ps
T309 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.3043689191 Mar 19 12:27:46 PM PDT 24 Mar 19 12:27:47 PM PDT 24 503049238 ps
T310 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.1584773307 Mar 19 12:27:40 PM PDT 24 Mar 19 12:27:41 PM PDT 24 568778043 ps
T311 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.3887933811 Mar 19 12:27:39 PM PDT 24 Mar 19 12:27:40 PM PDT 24 557458204 ps
T312 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.899260732 Mar 19 12:27:36 PM PDT 24 Mar 19 12:27:37 PM PDT 24 289641905 ps
T64 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.2896001885 Mar 19 12:27:41 PM PDT 24 Mar 19 12:27:42 PM PDT 24 689836644 ps
T313 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.4154142250 Mar 19 12:28:18 PM PDT 24 Mar 19 12:28:19 PM PDT 24 546952871 ps
T314 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.1795327367 Mar 19 12:27:44 PM PDT 24 Mar 19 12:27:46 PM PDT 24 587502909 ps
T315 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.2641969420 Mar 19 12:27:37 PM PDT 24 Mar 19 12:27:38 PM PDT 24 603184685 ps
T89 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.819684799 Mar 19 12:27:53 PM PDT 24 Mar 19 12:27:54 PM PDT 24 1397141606 ps
T316 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.2711427012 Mar 19 12:27:48 PM PDT 24 Mar 19 12:27:49 PM PDT 24 431816035 ps
T317 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.699428592 Mar 19 12:27:40 PM PDT 24 Mar 19 12:27:59 PM PDT 24 8185224193 ps
T318 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.2387019913 Mar 19 12:27:19 PM PDT 24 Mar 19 12:27:21 PM PDT 24 784136079 ps
T319 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.2815182903 Mar 19 12:27:56 PM PDT 24 Mar 19 12:27:59 PM PDT 24 650131370 ps
T320 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.381222186 Mar 19 12:27:52 PM PDT 24 Mar 19 12:28:02 PM PDT 24 6831399126 ps
T321 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.74200779 Mar 19 12:27:41 PM PDT 24 Mar 19 12:27:41 PM PDT 24 501220415 ps
T90 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.1006055255 Mar 19 12:27:44 PM PDT 24 Mar 19 12:27:45 PM PDT 24 1929567607 ps
T322 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.3288947889 Mar 19 12:27:53 PM PDT 24 Mar 19 12:27:53 PM PDT 24 351257600 ps
T323 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.3365071190 Mar 19 12:27:41 PM PDT 24 Mar 19 12:27:43 PM PDT 24 1452101819 ps
T324 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.1269626427 Mar 19 12:27:41 PM PDT 24 Mar 19 12:27:42 PM PDT 24 301343824 ps
T325 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.3537926117 Mar 19 12:27:45 PM PDT 24 Mar 19 12:27:45 PM PDT 24 489792588 ps
T113 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.2054295848 Mar 19 12:27:41 PM PDT 24 Mar 19 12:27:45 PM PDT 24 8456274888 ps
T326 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.2132162604 Mar 19 12:27:41 PM PDT 24 Mar 19 12:27:42 PM PDT 24 497054633 ps
T327 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.185154244 Mar 19 12:27:37 PM PDT 24 Mar 19 12:27:38 PM PDT 24 500924805 ps
T328 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.1757723972 Mar 19 12:27:44 PM PDT 24 Mar 19 12:27:45 PM PDT 24 572770576 ps
T329 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.1823698429 Mar 19 12:27:37 PM PDT 24 Mar 19 12:27:39 PM PDT 24 599282234 ps
T330 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.3624190052 Mar 19 12:27:44 PM PDT 24 Mar 19 12:27:46 PM PDT 24 546677544 ps
T331 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.2116651165 Mar 19 12:28:01 PM PDT 24 Mar 19 12:28:14 PM PDT 24 7309015967 ps
T332 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.3781625144 Mar 19 12:27:43 PM PDT 24 Mar 19 12:27:44 PM PDT 24 415373405 ps
T333 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.4219955256 Mar 19 12:27:34 PM PDT 24 Mar 19 12:27:36 PM PDT 24 427348540 ps
T334 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.509389782 Mar 19 12:27:42 PM PDT 24 Mar 19 12:27:43 PM PDT 24 515666120 ps
T335 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.3435763826 Mar 19 12:27:47 PM PDT 24 Mar 19 12:27:50 PM PDT 24 701375163 ps
T65 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.921104442 Mar 19 12:28:07 PM PDT 24 Mar 19 12:28:08 PM PDT 24 421675371 ps
T336 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.1516608804 Mar 19 12:27:44 PM PDT 24 Mar 19 12:27:44 PM PDT 24 539111390 ps
T337 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.1378369171 Mar 19 12:27:59 PM PDT 24 Mar 19 12:28:01 PM PDT 24 1867560718 ps
T338 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.1178767577 Mar 19 12:27:51 PM PDT 24 Mar 19 12:27:52 PM PDT 24 2215178044 ps
T339 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.2252116204 Mar 19 12:27:41 PM PDT 24 Mar 19 12:27:42 PM PDT 24 307746740 ps
T340 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.827938515 Mar 19 12:27:19 PM PDT 24 Mar 19 12:27:21 PM PDT 24 440688102 ps
T341 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.63688930 Mar 19 12:27:46 PM PDT 24 Mar 19 12:27:47 PM PDT 24 489418457 ps
T342 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.3795602474 Mar 19 12:27:26 PM PDT 24 Mar 19 12:27:27 PM PDT 24 378654250 ps
T343 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.171301000 Mar 19 12:27:49 PM PDT 24 Mar 19 12:27:51 PM PDT 24 507759492 ps
T344 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.262310196 Mar 19 12:27:41 PM PDT 24 Mar 19 12:27:42 PM PDT 24 439947878 ps
T345 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.3240399759 Mar 19 12:28:19 PM PDT 24 Mar 19 12:28:23 PM PDT 24 8510953965 ps
T346 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.62362972 Mar 19 12:27:48 PM PDT 24 Mar 19 12:27:50 PM PDT 24 643134064 ps
T117 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.3556089777 Mar 19 12:27:43 PM PDT 24 Mar 19 12:27:46 PM PDT 24 8389751920 ps
T347 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.3405424347 Mar 19 12:27:40 PM PDT 24 Mar 19 12:27:43 PM PDT 24 626692870 ps
T348 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.815781481 Mar 19 12:27:44 PM PDT 24 Mar 19 12:27:45 PM PDT 24 641479968 ps
T349 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.2037300673 Mar 19 12:27:41 PM PDT 24 Mar 19 12:27:43 PM PDT 24 515821191 ps
T350 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.3277883818 Mar 19 12:27:50 PM PDT 24 Mar 19 12:27:50 PM PDT 24 281826036 ps
T351 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.2050224596 Mar 19 12:27:30 PM PDT 24 Mar 19 12:27:31 PM PDT 24 525663040 ps
T352 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.118502308 Mar 19 12:27:43 PM PDT 24 Mar 19 12:27:44 PM PDT 24 497151455 ps
T353 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.577379160 Mar 19 12:27:45 PM PDT 24 Mar 19 12:27:46 PM PDT 24 271563121 ps
T354 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.2042439027 Mar 19 12:27:40 PM PDT 24 Mar 19 12:27:42 PM PDT 24 432788333 ps
T66 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.3405943052 Mar 19 12:27:46 PM PDT 24 Mar 19 12:27:47 PM PDT 24 496449240 ps
T355 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.2304638486 Mar 19 12:28:00 PM PDT 24 Mar 19 12:28:02 PM PDT 24 523927762 ps
T67 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.2335353465 Mar 19 12:27:26 PM PDT 24 Mar 19 12:27:27 PM PDT 24 595594269 ps
T356 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.2005787119 Mar 19 12:27:49 PM PDT 24 Mar 19 12:27:51 PM PDT 24 1802642728 ps
T68 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.2809889364 Mar 19 12:27:17 PM PDT 24 Mar 19 12:27:21 PM PDT 24 450352543 ps
T357 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.615029571 Mar 19 12:27:30 PM PDT 24 Mar 19 12:27:32 PM PDT 24 752940854 ps
T358 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.3533634217 Mar 19 12:27:44 PM PDT 24 Mar 19 12:27:45 PM PDT 24 466952447 ps
T71 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.1007276950 Mar 19 12:27:29 PM PDT 24 Mar 19 12:27:30 PM PDT 24 472631730 ps
T359 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.2281400595 Mar 19 12:27:47 PM PDT 24 Mar 19 12:27:48 PM PDT 24 283978549 ps
T72 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.3495824639 Mar 19 12:27:45 PM PDT 24 Mar 19 12:27:46 PM PDT 24 386933691 ps
T360 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.148473154 Mar 19 12:28:14 PM PDT 24 Mar 19 12:28:16 PM PDT 24 501067554 ps
T361 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.3556727561 Mar 19 12:27:46 PM PDT 24 Mar 19 12:27:46 PM PDT 24 431860958 ps
T114 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.2046803406 Mar 19 12:27:45 PM PDT 24 Mar 19 12:27:49 PM PDT 24 8605758108 ps
T118 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.962503152 Mar 19 12:27:41 PM PDT 24 Mar 19 12:27:43 PM PDT 24 8844753056 ps
T362 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.3407756622 Mar 19 12:28:26 PM PDT 24 Mar 19 12:28:27 PM PDT 24 284021293 ps
T69 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.3949589593 Mar 19 12:27:32 PM PDT 24 Mar 19 12:27:33 PM PDT 24 397990948 ps
T363 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.2809326873 Mar 19 12:27:47 PM PDT 24 Mar 19 12:27:48 PM PDT 24 458392153 ps
T364 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.735160269 Mar 19 12:27:16 PM PDT 24 Mar 19 12:27:18 PM PDT 24 750473413 ps
T365 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.3478073780 Mar 19 12:27:19 PM PDT 24 Mar 19 12:27:21 PM PDT 24 826405569 ps
T366 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.735761294 Mar 19 12:27:43 PM PDT 24 Mar 19 12:27:45 PM PDT 24 602509834 ps
T367 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.1251989190 Mar 19 12:27:40 PM PDT 24 Mar 19 12:27:40 PM PDT 24 557563916 ps
T368 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.486405938 Mar 19 12:27:39 PM PDT 24 Mar 19 12:27:40 PM PDT 24 465395990 ps
T369 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.490832830 Mar 19 12:27:41 PM PDT 24 Mar 19 12:27:43 PM PDT 24 4809003094 ps
T79 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.83060269 Mar 19 12:27:44 PM PDT 24 Mar 19 12:27:45 PM PDT 24 335422088 ps
T370 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.2222963264 Mar 19 12:27:36 PM PDT 24 Mar 19 12:27:37 PM PDT 24 444566530 ps
T80 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.3199746804 Mar 19 12:27:26 PM PDT 24 Mar 19 12:27:28 PM PDT 24 444805229 ps
T371 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.3466295074 Mar 19 12:28:03 PM PDT 24 Mar 19 12:28:04 PM PDT 24 407612615 ps
T372 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.3811983715 Mar 19 12:27:37 PM PDT 24 Mar 19 12:27:45 PM PDT 24 7939967583 ps
T373 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.1056258403 Mar 19 12:27:47 PM PDT 24 Mar 19 12:27:47 PM PDT 24 464835497 ps
T374 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.4073676830 Mar 19 12:27:51 PM PDT 24 Mar 19 12:27:52 PM PDT 24 504041901 ps
T375 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.2910066377 Mar 19 12:28:42 PM PDT 24 Mar 19 12:28:47 PM PDT 24 2758584796 ps
T376 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.571874642 Mar 19 12:27:42 PM PDT 24 Mar 19 12:27:44 PM PDT 24 2444416171 ps
T377 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.475261302 Mar 19 12:28:35 PM PDT 24 Mar 19 12:28:37 PM PDT 24 474107001 ps
T378 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.67282495 Mar 19 12:27:40 PM PDT 24 Mar 19 12:27:43 PM PDT 24 550965177 ps
T379 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.1626322271 Mar 19 12:27:51 PM PDT 24 Mar 19 12:27:52 PM PDT 24 452114938 ps
T380 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.3940935846 Mar 19 12:27:45 PM PDT 24 Mar 19 12:27:46 PM PDT 24 518141143 ps
T381 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.3368766224 Mar 19 12:27:41 PM PDT 24 Mar 19 12:27:42 PM PDT 24 380758038 ps
T382 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.2238069812 Mar 19 12:28:22 PM PDT 24 Mar 19 12:28:23 PM PDT 24 708492166 ps
T383 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.1251172673 Mar 19 12:28:04 PM PDT 24 Mar 19 12:28:05 PM PDT 24 459471387 ps
T384 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.1257771463 Mar 19 12:27:44 PM PDT 24 Mar 19 12:27:45 PM PDT 24 427762998 ps
T385 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.2370913152 Mar 19 12:27:40 PM PDT 24 Mar 19 12:27:41 PM PDT 24 349400626 ps
T386 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.1474882646 Mar 19 12:27:41 PM PDT 24 Mar 19 12:27:42 PM PDT 24 286319251 ps
T115 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.1511126287 Mar 19 12:28:23 PM PDT 24 Mar 19 12:28:31 PM PDT 24 4231795189 ps
T387 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.1824817921 Mar 19 12:27:27 PM PDT 24 Mar 19 12:27:32 PM PDT 24 1887484310 ps
T388 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.3667638788 Mar 19 12:27:30 PM PDT 24 Mar 19 12:27:32 PM PDT 24 808161833 ps
T389 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.3374053413 Mar 19 12:27:48 PM PDT 24 Mar 19 12:27:51 PM PDT 24 2320897153 ps
T390 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.2357955941 Mar 19 12:27:47 PM PDT 24 Mar 19 12:27:49 PM PDT 24 368245141 ps
T391 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.1855566134 Mar 19 12:27:42 PM PDT 24 Mar 19 12:27:43 PM PDT 24 4186103750 ps
T392 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.2220612954 Mar 19 12:27:41 PM PDT 24 Mar 19 12:27:42 PM PDT 24 506062502 ps
T393 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.3450872829 Mar 19 12:27:43 PM PDT 24 Mar 19 12:27:43 PM PDT 24 386299917 ps
T394 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.2990783679 Mar 19 12:28:12 PM PDT 24 Mar 19 12:28:16 PM PDT 24 7266213605 ps
T395 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.1510929699 Mar 19 12:27:44 PM PDT 24 Mar 19 12:27:46 PM PDT 24 470572139 ps
T396 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.2645694994 Mar 19 12:27:43 PM PDT 24 Mar 19 12:27:44 PM PDT 24 340836396 ps
T397 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.4013365702 Mar 19 12:27:34 PM PDT 24 Mar 19 12:27:36 PM PDT 24 290372153 ps
T398 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.910723297 Mar 19 12:27:52 PM PDT 24 Mar 19 12:27:57 PM PDT 24 8831982169 ps
T399 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.1514594341 Mar 19 12:27:34 PM PDT 24 Mar 19 12:27:35 PM PDT 24 341197327 ps
T400 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.3282382330 Mar 19 12:28:04 PM PDT 24 Mar 19 12:28:05 PM PDT 24 552455636 ps
T73 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.3058538276 Mar 19 12:27:42 PM PDT 24 Mar 19 12:27:52 PM PDT 24 6996468601 ps
T401 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.199514362 Mar 19 12:27:31 PM PDT 24 Mar 19 12:27:33 PM PDT 24 505900412 ps
T402 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.332303133 Mar 19 12:27:41 PM PDT 24 Mar 19 12:27:47 PM PDT 24 4276122610 ps
T403 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.3426577563 Mar 19 12:28:09 PM PDT 24 Mar 19 12:28:09 PM PDT 24 304770044 ps
T404 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.3928879674 Mar 19 12:28:34 PM PDT 24 Mar 19 12:28:36 PM PDT 24 500166257 ps
T405 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.2683402026 Mar 19 12:27:39 PM PDT 24 Mar 19 12:27:39 PM PDT 24 522175709 ps
T406 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.3744413933 Mar 19 12:27:40 PM PDT 24 Mar 19 12:27:41 PM PDT 24 4201809926 ps
T407 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.4063093753 Mar 19 12:27:49 PM PDT 24 Mar 19 12:27:50 PM PDT 24 564477772 ps
T408 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.2737926186 Mar 19 12:27:39 PM PDT 24 Mar 19 12:27:40 PM PDT 24 521021524 ps
T409 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.1186810567 Mar 19 12:27:43 PM PDT 24 Mar 19 12:27:45 PM PDT 24 968751694 ps
T410 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.3875587241 Mar 19 12:27:54 PM PDT 24 Mar 19 12:27:54 PM PDT 24 469006429 ps
T411 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.2667876454 Mar 19 12:27:41 PM PDT 24 Mar 19 12:27:42 PM PDT 24 418323839 ps
T412 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.406943218 Mar 19 12:27:47 PM PDT 24 Mar 19 12:27:48 PM PDT 24 478125951 ps
T413 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.4149926085 Mar 19 12:27:23 PM PDT 24 Mar 19 12:27:26 PM PDT 24 373327617 ps
T414 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.2250127783 Mar 19 12:27:46 PM PDT 24 Mar 19 12:27:50 PM PDT 24 2254064225 ps
T415 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.179682905 Mar 19 12:27:37 PM PDT 24 Mar 19 12:27:38 PM PDT 24 525255296 ps
T416 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.990715899 Mar 19 12:28:13 PM PDT 24 Mar 19 12:28:25 PM PDT 24 2141053041 ps
T417 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.830540968 Mar 19 12:27:42 PM PDT 24 Mar 19 12:27:43 PM PDT 24 358949419 ps
T418 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.3423515516 Mar 19 12:27:44 PM PDT 24 Mar 19 12:27:46 PM PDT 24 320784025 ps
T70 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.1258193840 Mar 19 12:27:58 PM PDT 24 Mar 19 12:27:59 PM PDT 24 391725744 ps
T419 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.3564820612 Mar 19 12:27:42 PM PDT 24 Mar 19 12:27:43 PM PDT 24 275390229 ps

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.875607215
Short name T10
Test name
Test status
Simulation time 40210114075 ps
CPU time 293.93 seconds
Started Mar 19 12:26:44 PM PDT 24
Finished Mar 19 12:31:38 PM PDT 24
Peak memory 197780 kb
Host smart-8b2b0f0f-7ea1-47c7-91cd-0d0544da0d5b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875607215 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.875607215
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.570797495
Short name T2
Test name
Test status
Simulation time 122411349681 ps
CPU time 15.54 seconds
Started Mar 19 12:26:53 PM PDT 24
Finished Mar 19 12:27:08 PM PDT 24
Peak memory 182904 kb
Host smart-4e9aa77d-13fc-46bd-917e-6cf63599563f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570797495 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_a
ll.570797495
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.4129221493
Short name T42
Test name
Test status
Simulation time 4252137205 ps
CPU time 7.54 seconds
Started Mar 19 12:27:29 PM PDT 24
Finished Mar 19 12:27:37 PM PDT 24
Peak memory 197408 kb
Host smart-129019b6-16c3-49c1-982c-a3b524ecefb6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129221493 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl
_intg_err.4129221493
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.459605577
Short name T48
Test name
Test status
Simulation time 79603174897 ps
CPU time 814.04 seconds
Started Mar 19 12:26:26 PM PDT 24
Finished Mar 19 12:40:06 PM PDT 24
Peak memory 200876 kb
Host smart-1ea24afd-c205-4e1b-9285-162c2a451a7b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459605577 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.459605577
Directory /workspace/9.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.1338403148
Short name T76
Test name
Test status
Simulation time 82314838740 ps
CPU time 591.29 seconds
Started Mar 19 12:26:18 PM PDT 24
Finished Mar 19 12:36:09 PM PDT 24
Peak memory 206656 kb
Host smart-9934da93-b86d-491c-b378-254b706196c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338403148 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.1338403148
Directory /workspace/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.1188821012
Short name T24
Test name
Test status
Simulation time 4264106803 ps
CPU time 6.84 seconds
Started Mar 19 12:27:41 PM PDT 24
Finished Mar 19 12:27:48 PM PDT 24
Peak memory 214356 kb
Host smart-02c2517a-86b7-422a-8c51-4650b8ab216b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188821012 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.1188821012
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.900402638
Short name T56
Test name
Test status
Simulation time 218262135028 ps
CPU time 624.52 seconds
Started Mar 19 12:26:25 PM PDT 24
Finished Mar 19 12:36:51 PM PDT 24
Peak memory 197112 kb
Host smart-949cef64-7bcd-44b3-8136-13ac1da919f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900402638 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.900402638
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.2046803406
Short name T114
Test name
Test status
Simulation time 8605758108 ps
CPU time 3.94 seconds
Started Mar 19 12:27:45 PM PDT 24
Finished Mar 19 12:27:49 PM PDT 24
Peak memory 197808 kb
Host smart-91454cca-0b1e-4cff-bd5e-9d1af9c6cdd3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046803406 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_t
l_intg_err.2046803406
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.3546574673
Short name T15
Test name
Test status
Simulation time 45499369325 ps
CPU time 25.08 seconds
Started Mar 19 12:26:49 PM PDT 24
Finished Mar 19 12:27:15 PM PDT 24
Peak memory 193308 kb
Host smart-d1c3f0db-6aaf-4811-96d6-42a7c55c363c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546574673 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_
all.3546574673
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.2809889364
Short name T68
Test name
Test status
Simulation time 450352543 ps
CPU time 1.14 seconds
Started Mar 19 12:27:17 PM PDT 24
Finished Mar 19 12:27:21 PM PDT 24
Peak memory 194204 kb
Host smart-87022151-dce0-4dc2-9972-a75d9e6d7420
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809889364 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_a
liasing.2809889364
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.574195709
Short name T82
Test name
Test status
Simulation time 2002759283 ps
CPU time 2.47 seconds
Started Mar 19 12:27:31 PM PDT 24
Finished Mar 19 12:27:34 PM PDT 24
Peak memory 194448 kb
Host smart-5b7a7e62-179b-4f92-9c65-7b5f862ad0a8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574195709 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_
timer_same_csr_outstanding.574195709
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.4225885604
Short name T18
Test name
Test status
Simulation time 163163475058 ps
CPU time 1163.53 seconds
Started Mar 19 12:26:32 PM PDT 24
Finished Mar 19 12:45:55 PM PDT 24
Peak memory 205880 kb
Host smart-785eff91-b654-4800-8920-5bc931d5a6fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225885604 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.4225885604
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.454126251
Short name T99
Test name
Test status
Simulation time 13823648382 ps
CPU time 6.32 seconds
Started Mar 19 12:27:30 PM PDT 24
Finished Mar 19 12:27:37 PM PDT 24
Peak memory 192116 kb
Host smart-41998616-0c3b-4444-85cd-497f7acca113
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454126251 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_bi
t_bash.454126251
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.93212445
Short name T45
Test name
Test status
Simulation time 870814617 ps
CPU time 0.89 seconds
Started Mar 19 12:27:22 PM PDT 24
Finished Mar 19 12:27:23 PM PDT 24
Peak memory 183680 kb
Host smart-49ccfd1f-a12e-4511-9c4e-26bd3c2bea23
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93212445 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_hw_
reset.93212445
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.2641969420
Short name T315
Test name
Test status
Simulation time 603184685 ps
CPU time 1.26 seconds
Started Mar 19 12:27:37 PM PDT 24
Finished Mar 19 12:27:38 PM PDT 24
Peak memory 198344 kb
Host smart-ae185637-1292-4a9e-932a-842d1d5a4018
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641969420 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.2641969420
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.399788067
Short name T296
Test name
Test status
Simulation time 465132373 ps
CPU time 1.3 seconds
Started Mar 19 12:27:41 PM PDT 24
Finished Mar 19 12:27:42 PM PDT 24
Peak memory 183716 kb
Host smart-b589e2f2-4fbc-4488-baa9-87234cc07521
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399788067 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.399788067
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.899260732
Short name T312
Test name
Test status
Simulation time 289641905 ps
CPU time 0.81 seconds
Started Mar 19 12:27:36 PM PDT 24
Finished Mar 19 12:27:37 PM PDT 24
Peak memory 183508 kb
Host smart-4e0e404d-fff7-461a-bcb2-5ce28f879939
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899260732 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.899260732
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.2521334801
Short name T298
Test name
Test status
Simulation time 365641996 ps
CPU time 0.64 seconds
Started Mar 19 12:27:38 PM PDT 24
Finished Mar 19 12:27:39 PM PDT 24
Peak memory 183520 kb
Host smart-3cb16244-4934-4a1b-8343-1c179c59d57d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521334801 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_t
imer_mem_partial_access.2521334801
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.2683402026
Short name T405
Test name
Test status
Simulation time 522175709 ps
CPU time 0.69 seconds
Started Mar 19 12:27:39 PM PDT 24
Finished Mar 19 12:27:39 PM PDT 24
Peak memory 183588 kb
Host smart-f5a4aaa2-9c84-4fbf-9e0c-d66f34e66c7f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683402026 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_w
alk.2683402026
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.2387019913
Short name T318
Test name
Test status
Simulation time 784136079 ps
CPU time 1.64 seconds
Started Mar 19 12:27:19 PM PDT 24
Finished Mar 19 12:27:21 PM PDT 24
Peak memory 198460 kb
Host smart-68aca8d7-7805-4b9e-920a-783c71e74ea6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387019913 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.2387019913
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.735160269
Short name T364
Test name
Test status
Simulation time 750473413 ps
CPU time 1.3 seconds
Started Mar 19 12:27:16 PM PDT 24
Finished Mar 19 12:27:18 PM PDT 24
Peak memory 194132 kb
Host smart-f2d57886-7426-4ece-b262-0a54d9683427
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735160269 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_al
iasing.735160269
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.381222186
Short name T320
Test name
Test status
Simulation time 6831399126 ps
CPU time 10.42 seconds
Started Mar 19 12:27:52 PM PDT 24
Finished Mar 19 12:28:02 PM PDT 24
Peak memory 195436 kb
Host smart-23878b88-6dc5-4412-a938-b0c9f98f3a44
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381222186 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_bi
t_bash.381222186
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.3478073780
Short name T365
Test name
Test status
Simulation time 826405569 ps
CPU time 1.5 seconds
Started Mar 19 12:27:19 PM PDT 24
Finished Mar 19 12:27:21 PM PDT 24
Peak memory 183620 kb
Host smart-c02935ac-2990-4dea-9f13-0e669b0ddbfa
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478073780 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_h
w_reset.3478073780
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.1757723972
Short name T328
Test name
Test status
Simulation time 572770576 ps
CPU time 1.17 seconds
Started Mar 19 12:27:44 PM PDT 24
Finished Mar 19 12:27:45 PM PDT 24
Peak memory 198252 kb
Host smart-84b3a6ea-0812-4c6f-8184-c99220d974bd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757723972 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.1757723972
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.262310196
Short name T344
Test name
Test status
Simulation time 439947878 ps
CPU time 0.84 seconds
Started Mar 19 12:27:41 PM PDT 24
Finished Mar 19 12:27:42 PM PDT 24
Peak memory 183808 kb
Host smart-97f0b7d1-6cfd-4623-afb4-30bad8ee9c81
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262310196 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.262310196
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.689227895
Short name T299
Test name
Test status
Simulation time 588234971 ps
CPU time 0.57 seconds
Started Mar 19 12:27:50 PM PDT 24
Finished Mar 19 12:27:56 PM PDT 24
Peak memory 183508 kb
Host smart-ef091c65-1700-4fce-b725-6a57848994c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689227895 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.689227895
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.1765876957
Short name T297
Test name
Test status
Simulation time 411913273 ps
CPU time 0.64 seconds
Started Mar 19 12:27:33 PM PDT 24
Finished Mar 19 12:27:33 PM PDT 24
Peak memory 183556 kb
Host smart-36197ef8-e9bf-49a9-b821-d3405d562efb
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765876957 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_t
imer_mem_partial_access.1765876957
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.4149926085
Short name T413
Test name
Test status
Simulation time 373327617 ps
CPU time 0.64 seconds
Started Mar 19 12:27:23 PM PDT 24
Finished Mar 19 12:27:26 PM PDT 24
Peak memory 183596 kb
Host smart-ee1c8501-56a8-4bc4-b53b-dc89c7e4cac2
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149926085 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_w
alk.4149926085
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.1506513571
Short name T86
Test name
Test status
Simulation time 2421538777 ps
CPU time 4.38 seconds
Started Mar 19 12:27:30 PM PDT 24
Finished Mar 19 12:27:34 PM PDT 24
Peak memory 183844 kb
Host smart-457ca315-b8c3-482e-98c7-c4ff9d169da5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506513571 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon
_timer_same_csr_outstanding.1506513571
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.3228681482
Short name T308
Test name
Test status
Simulation time 511154475 ps
CPU time 1.13 seconds
Started Mar 19 12:27:43 PM PDT 24
Finished Mar 19 12:27:50 PM PDT 24
Peak memory 198296 kb
Host smart-8f186eb3-571b-4480-8306-32ef47c513a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228681482 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.3228681482
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.962503152
Short name T118
Test name
Test status
Simulation time 8844753056 ps
CPU time 2.25 seconds
Started Mar 19 12:27:41 PM PDT 24
Finished Mar 19 12:27:43 PM PDT 24
Peak memory 197760 kb
Host smart-95e324cf-b046-4a56-bae9-59eea8e1f0f4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962503152 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_
intg_err.962503152
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.2304638486
Short name T355
Test name
Test status
Simulation time 523927762 ps
CPU time 1.25 seconds
Started Mar 19 12:28:00 PM PDT 24
Finished Mar 19 12:28:02 PM PDT 24
Peak memory 195752 kb
Host smart-eae267df-d10f-494f-95fa-548eba6a96d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304638486 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.2304638486
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.2222963264
Short name T370
Test name
Test status
Simulation time 444566530 ps
CPU time 0.98 seconds
Started Mar 19 12:27:36 PM PDT 24
Finished Mar 19 12:27:37 PM PDT 24
Peak memory 183772 kb
Host smart-6bd2fe9b-4944-43a8-9ca1-8a82143fad5b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222963264 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.2222963264
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.662157637
Short name T294
Test name
Test status
Simulation time 357537457 ps
CPU time 0.84 seconds
Started Mar 19 12:27:49 PM PDT 24
Finished Mar 19 12:27:50 PM PDT 24
Peak memory 183588 kb
Host smart-79c44f4d-17e7-4d99-bed8-4629f14cf849
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662157637 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.662157637
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.1006055255
Short name T90
Test name
Test status
Simulation time 1929567607 ps
CPU time 1.33 seconds
Started Mar 19 12:27:44 PM PDT 24
Finished Mar 19 12:27:45 PM PDT 24
Peak memory 193016 kb
Host smart-04bd6e04-2804-4b65-956c-18578a813ffa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006055255 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.ao
n_timer_same_csr_outstanding.1006055255
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.735761294
Short name T366
Test name
Test status
Simulation time 602509834 ps
CPU time 1.55 seconds
Started Mar 19 12:27:43 PM PDT 24
Finished Mar 19 12:27:45 PM PDT 24
Peak memory 198432 kb
Host smart-22bc69d7-91fe-450c-89ab-671de3d7eb4b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735761294 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.735761294
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.2054295848
Short name T113
Test name
Test status
Simulation time 8456274888 ps
CPU time 4.04 seconds
Started Mar 19 12:27:41 PM PDT 24
Finished Mar 19 12:27:45 PM PDT 24
Peak memory 197704 kb
Host smart-28c749a0-4489-4c78-b5a9-10848249a5ba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054295848 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_t
l_intg_err.2054295848
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.1413970709
Short name T36
Test name
Test status
Simulation time 754275378 ps
CPU time 0.78 seconds
Started Mar 19 12:27:40 PM PDT 24
Finished Mar 19 12:27:41 PM PDT 24
Peak memory 196572 kb
Host smart-f3d9eb32-3c72-4b1e-85af-1119108c280d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413970709 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.1413970709
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.486405938
Short name T368
Test name
Test status
Simulation time 465395990 ps
CPU time 0.7 seconds
Started Mar 19 12:27:39 PM PDT 24
Finished Mar 19 12:27:40 PM PDT 24
Peak memory 193104 kb
Host smart-818046d8-0966-4835-a2d1-8f99423e8f70
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486405938 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.486405938
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.3288947889
Short name T322
Test name
Test status
Simulation time 351257600 ps
CPU time 0.67 seconds
Started Mar 19 12:27:53 PM PDT 24
Finished Mar 19 12:27:53 PM PDT 24
Peak memory 183492 kb
Host smart-5dd32f5f-d78a-4861-825a-698398ee8764
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288947889 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.3288947889
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.3365071190
Short name T323
Test name
Test status
Simulation time 1452101819 ps
CPU time 2.47 seconds
Started Mar 19 12:27:41 PM PDT 24
Finished Mar 19 12:27:43 PM PDT 24
Peak memory 183940 kb
Host smart-e64e8f0f-9d3a-40f6-92a2-7511ca4ffc90
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365071190 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.ao
n_timer_same_csr_outstanding.3365071190
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.1891101630
Short name T301
Test name
Test status
Simulation time 530949129 ps
CPU time 1.32 seconds
Started Mar 19 12:27:46 PM PDT 24
Finished Mar 19 12:27:48 PM PDT 24
Peak memory 198408 kb
Host smart-35f37670-edbb-4bf1-9c21-4f0f485fd931
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891101630 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.1891101630
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.3744413933
Short name T406
Test name
Test status
Simulation time 4201809926 ps
CPU time 1.53 seconds
Started Mar 19 12:27:40 PM PDT 24
Finished Mar 19 12:27:41 PM PDT 24
Peak memory 196484 kb
Host smart-03b0ebc8-7b97-42e5-b084-eb19a9a7c15e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744413933 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_t
l_intg_err.3744413933
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.2050224596
Short name T351
Test name
Test status
Simulation time 525663040 ps
CPU time 0.95 seconds
Started Mar 19 12:27:30 PM PDT 24
Finished Mar 19 12:27:31 PM PDT 24
Peak memory 196360 kb
Host smart-db051858-b6bb-49be-a417-f621c9741c09
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050224596 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.2050224596
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.3360387520
Short name T286
Test name
Test status
Simulation time 431164911 ps
CPU time 1.12 seconds
Started Mar 19 12:27:44 PM PDT 24
Finished Mar 19 12:27:45 PM PDT 24
Peak memory 193000 kb
Host smart-fceb21e4-1b19-4063-a04b-cb28086fb97b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360387520 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.3360387520
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.3450872829
Short name T393
Test name
Test status
Simulation time 386299917 ps
CPU time 0.65 seconds
Started Mar 19 12:27:43 PM PDT 24
Finished Mar 19 12:27:43 PM PDT 24
Peak memory 183528 kb
Host smart-fd5fd000-c236-4925-9062-47bfc3401e7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450872829 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.3450872829
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.990715899
Short name T416
Test name
Test status
Simulation time 2141053041 ps
CPU time 6.18 seconds
Started Mar 19 12:28:13 PM PDT 24
Finished Mar 19 12:28:25 PM PDT 24
Peak memory 194540 kb
Host smart-a4b9549b-f07d-4274-a611-e15ee9c7a4f7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990715899 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon
_timer_same_csr_outstanding.990715899
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.509389782
Short name T334
Test name
Test status
Simulation time 515666120 ps
CPU time 1.36 seconds
Started Mar 19 12:27:42 PM PDT 24
Finished Mar 19 12:27:43 PM PDT 24
Peak memory 198472 kb
Host smart-e44261c4-cefc-4b4e-a79c-6ccd062a8201
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509389782 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.509389782
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.748161005
Short name T44
Test name
Test status
Simulation time 4754003543 ps
CPU time 1.83 seconds
Started Mar 19 12:27:40 PM PDT 24
Finished Mar 19 12:27:42 PM PDT 24
Peak memory 197388 kb
Host smart-c6f13f59-e848-4919-bed9-5f685df38e9d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748161005 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl
_intg_err.748161005
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.1711540266
Short name T295
Test name
Test status
Simulation time 446329882 ps
CPU time 1.36 seconds
Started Mar 19 12:28:10 PM PDT 24
Finished Mar 19 12:28:11 PM PDT 24
Peak memory 195940 kb
Host smart-c7ac9c9c-5b4e-4c75-9747-699e48b2c232
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711540266 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.1711540266
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.921104442
Short name T65
Test name
Test status
Simulation time 421675371 ps
CPU time 0.67 seconds
Started Mar 19 12:28:07 PM PDT 24
Finished Mar 19 12:28:08 PM PDT 24
Peak memory 193044 kb
Host smart-c3baaed0-29d3-49c0-9319-2b31c2a14c75
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921104442 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.921104442
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.3895028531
Short name T293
Test name
Test status
Simulation time 531032902 ps
CPU time 0.66 seconds
Started Mar 19 12:27:43 PM PDT 24
Finished Mar 19 12:27:44 PM PDT 24
Peak memory 183528 kb
Host smart-430372bf-45fd-48db-84b9-3b7fcd888191
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895028531 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.3895028531
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.2437210705
Short name T88
Test name
Test status
Simulation time 945803600 ps
CPU time 1.8 seconds
Started Mar 19 12:27:42 PM PDT 24
Finished Mar 19 12:27:44 PM PDT 24
Peak memory 193096 kb
Host smart-c708c135-8381-4ae3-8f88-94cde285f400
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437210705 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.ao
n_timer_same_csr_outstanding.2437210705
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.67282495
Short name T378
Test name
Test status
Simulation time 550965177 ps
CPU time 2.75 seconds
Started Mar 19 12:27:40 PM PDT 24
Finished Mar 19 12:27:43 PM PDT 24
Peak memory 198396 kb
Host smart-aa0e19a8-ba7a-4bd6-b96b-465c13615e97
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67282495 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.67282495
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.910723297
Short name T398
Test name
Test status
Simulation time 8831982169 ps
CPU time 4.76 seconds
Started Mar 19 12:27:52 PM PDT 24
Finished Mar 19 12:27:57 PM PDT 24
Peak memory 197652 kb
Host smart-7b14df85-afdb-4dd7-ad3f-4c4669e0d390
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910723297 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl
_intg_err.910723297
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.4173428645
Short name T37
Test name
Test status
Simulation time 565839195 ps
CPU time 0.89 seconds
Started Mar 19 12:27:47 PM PDT 24
Finished Mar 19 12:27:48 PM PDT 24
Peak memory 195952 kb
Host smart-4a19b038-37e1-43b6-b990-b3d7df71181a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173428645 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.4173428645
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.1510929699
Short name T395
Test name
Test status
Simulation time 470572139 ps
CPU time 1.18 seconds
Started Mar 19 12:27:44 PM PDT 24
Finished Mar 19 12:27:46 PM PDT 24
Peak memory 183600 kb
Host smart-02109788-9800-4bc8-ac03-debee492310a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510929699 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.1510929699
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.1231525479
Short name T307
Test name
Test status
Simulation time 301983621 ps
CPU time 1.02 seconds
Started Mar 19 12:27:45 PM PDT 24
Finished Mar 19 12:27:46 PM PDT 24
Peak memory 183520 kb
Host smart-f492517d-0bb7-4bd4-8242-7914b06bbf45
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231525479 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.1231525479
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.2005787119
Short name T356
Test name
Test status
Simulation time 1802642728 ps
CPU time 1.36 seconds
Started Mar 19 12:27:49 PM PDT 24
Finished Mar 19 12:27:51 PM PDT 24
Peak memory 193244 kb
Host smart-f629f2b6-91cd-49ff-ac71-d79186676a93
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005787119 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao
n_timer_same_csr_outstanding.2005787119
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.1795327367
Short name T314
Test name
Test status
Simulation time 587502909 ps
CPU time 2.05 seconds
Started Mar 19 12:27:44 PM PDT 24
Finished Mar 19 12:27:46 PM PDT 24
Peak memory 198480 kb
Host smart-4d8e1c8c-6cd9-4157-8e3f-9d30a8c57c00
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795327367 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.1795327367
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.2116651165
Short name T331
Test name
Test status
Simulation time 7309015967 ps
CPU time 13.07 seconds
Started Mar 19 12:28:01 PM PDT 24
Finished Mar 19 12:28:14 PM PDT 24
Peak memory 197872 kb
Host smart-6698d6e3-63ce-4be4-88ca-f9d99bc03f72
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116651165 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_t
l_intg_err.2116651165
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.3282382330
Short name T400
Test name
Test status
Simulation time 552455636 ps
CPU time 0.93 seconds
Started Mar 19 12:28:04 PM PDT 24
Finished Mar 19 12:28:05 PM PDT 24
Peak memory 197724 kb
Host smart-69e4e10d-80e1-41a4-be3f-be1d51cd8ec9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282382330 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.3282382330
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.83060269
Short name T79
Test name
Test status
Simulation time 335422088 ps
CPU time 0.73 seconds
Started Mar 19 12:27:44 PM PDT 24
Finished Mar 19 12:27:45 PM PDT 24
Peak memory 192900 kb
Host smart-769348c1-37bc-400e-ba20-d60d7786cd6d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83060269 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.83060269
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.3875587241
Short name T410
Test name
Test status
Simulation time 469006429 ps
CPU time 0.69 seconds
Started Mar 19 12:27:54 PM PDT 24
Finished Mar 19 12:27:54 PM PDT 24
Peak memory 183520 kb
Host smart-581b7778-b0f6-4a36-82e7-15b8fb276823
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875587241 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.3875587241
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.4161340814
Short name T85
Test name
Test status
Simulation time 2620550974 ps
CPU time 0.99 seconds
Started Mar 19 12:27:50 PM PDT 24
Finished Mar 19 12:27:51 PM PDT 24
Peak memory 191972 kb
Host smart-7d0a8e19-71ec-4689-8615-f9d9cc4ff420
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161340814 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.ao
n_timer_same_csr_outstanding.4161340814
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.2357955941
Short name T390
Test name
Test status
Simulation time 368245141 ps
CPU time 2.37 seconds
Started Mar 19 12:27:47 PM PDT 24
Finished Mar 19 12:27:49 PM PDT 24
Peak memory 198424 kb
Host smart-aedd2580-2e93-4ed6-97a4-75a46b48df42
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357955941 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.2357955941
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.3317132250
Short name T306
Test name
Test status
Simulation time 8710561034 ps
CPU time 7.13 seconds
Started Mar 19 12:27:41 PM PDT 24
Finished Mar 19 12:27:48 PM PDT 24
Peak memory 198128 kb
Host smart-46c6eb69-5c7b-4796-9979-c93110587449
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317132250 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_t
l_intg_err.3317132250
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.2132162604
Short name T326
Test name
Test status
Simulation time 497054633 ps
CPU time 0.77 seconds
Started Mar 19 12:27:41 PM PDT 24
Finished Mar 19 12:27:42 PM PDT 24
Peak memory 195472 kb
Host smart-e7e70812-1ad1-4dad-9523-9660a55d9b26
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132162604 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.2132162604
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.3949589593
Short name T69
Test name
Test status
Simulation time 397990948 ps
CPU time 1.04 seconds
Started Mar 19 12:27:32 PM PDT 24
Finished Mar 19 12:27:33 PM PDT 24
Peak memory 192892 kb
Host smart-09875896-4f06-4e45-8b39-349eb0d8b50a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949589593 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.3949589593
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.1626322271
Short name T379
Test name
Test status
Simulation time 452114938 ps
CPU time 0.72 seconds
Started Mar 19 12:27:51 PM PDT 24
Finished Mar 19 12:27:52 PM PDT 24
Peak memory 183540 kb
Host smart-6d729e92-8f70-4752-a378-6e12a0b73746
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626322271 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.1626322271
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.2250127783
Short name T414
Test name
Test status
Simulation time 2254064225 ps
CPU time 3.98 seconds
Started Mar 19 12:27:46 PM PDT 24
Finished Mar 19 12:27:50 PM PDT 24
Peak memory 183940 kb
Host smart-e91b737e-f4c3-40a7-8c2b-760d908a42e8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250127783 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.ao
n_timer_same_csr_outstanding.2250127783
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.62362972
Short name T346
Test name
Test status
Simulation time 643134064 ps
CPU time 1.33 seconds
Started Mar 19 12:27:48 PM PDT 24
Finished Mar 19 12:27:50 PM PDT 24
Peak memory 198832 kb
Host smart-7e519e91-e204-4b49-9da7-c488914e906b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62362972 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.62362972
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.1855566134
Short name T391
Test name
Test status
Simulation time 4186103750 ps
CPU time 1.14 seconds
Started Mar 19 12:27:42 PM PDT 24
Finished Mar 19 12:27:43 PM PDT 24
Peak memory 196352 kb
Host smart-1935ae56-89d7-41e3-83ed-bf63c9e6c7ff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855566134 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_t
l_intg_err.1855566134
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.406943218
Short name T412
Test name
Test status
Simulation time 478125951 ps
CPU time 1.15 seconds
Started Mar 19 12:27:47 PM PDT 24
Finished Mar 19 12:27:48 PM PDT 24
Peak memory 198224 kb
Host smart-437c6a55-3abc-493e-9dda-2cf6fc7a606f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406943218 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.406943218
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.2645694994
Short name T396
Test name
Test status
Simulation time 340836396 ps
CPU time 0.99 seconds
Started Mar 19 12:27:43 PM PDT 24
Finished Mar 19 12:27:44 PM PDT 24
Peak memory 193076 kb
Host smart-f62609c4-b34b-47bb-aa27-490d42eef7c4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645694994 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.2645694994
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.4073676830
Short name T374
Test name
Test status
Simulation time 504041901 ps
CPU time 1.34 seconds
Started Mar 19 12:27:51 PM PDT 24
Finished Mar 19 12:27:52 PM PDT 24
Peak memory 183520 kb
Host smart-2f4a91e4-a7fa-4ef3-9681-a93672d4767f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073676830 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.4073676830
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.1378369171
Short name T337
Test name
Test status
Simulation time 1867560718 ps
CPU time 1.97 seconds
Started Mar 19 12:27:59 PM PDT 24
Finished Mar 19 12:28:01 PM PDT 24
Peak memory 194444 kb
Host smart-01457b4c-dca3-4e97-ae16-402fc2a26aec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378369171 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.ao
n_timer_same_csr_outstanding.1378369171
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.1823698429
Short name T329
Test name
Test status
Simulation time 599282234 ps
CPU time 2.16 seconds
Started Mar 19 12:27:37 PM PDT 24
Finished Mar 19 12:27:39 PM PDT 24
Peak memory 198480 kb
Host smart-745f1c57-d1d5-473c-b02b-bb115722eb5c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823698429 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.1823698429
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.699428592
Short name T317
Test name
Test status
Simulation time 8185224193 ps
CPU time 13.13 seconds
Started Mar 19 12:27:40 PM PDT 24
Finished Mar 19 12:27:59 PM PDT 24
Peak memory 197820 kb
Host smart-8cc4ab63-a60f-49a5-b188-a96fc95d2047
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699428592 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl
_intg_err.699428592
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.3887933811
Short name T311
Test name
Test status
Simulation time 557458204 ps
CPU time 1.54 seconds
Started Mar 19 12:27:39 PM PDT 24
Finished Mar 19 12:27:40 PM PDT 24
Peak memory 195628 kb
Host smart-33b5ec7a-76da-4a2b-9091-72bb7ce0339f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887933811 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.3887933811
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.408957204
Short name T300
Test name
Test status
Simulation time 489358511 ps
CPU time 0.63 seconds
Started Mar 19 12:27:43 PM PDT 24
Finished Mar 19 12:27:44 PM PDT 24
Peak memory 183740 kb
Host smart-31bbc84d-9d89-4a6c-9e5b-25419d27d5b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408957204 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.408957204
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.3556727561
Short name T361
Test name
Test status
Simulation time 431860958 ps
CPU time 0.69 seconds
Started Mar 19 12:27:46 PM PDT 24
Finished Mar 19 12:27:46 PM PDT 24
Peak memory 183532 kb
Host smart-a4b5459f-34d4-4955-9528-2fb9c1e3a655
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556727561 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.3556727561
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.819684799
Short name T89
Test name
Test status
Simulation time 1397141606 ps
CPU time 0.98 seconds
Started Mar 19 12:27:53 PM PDT 24
Finished Mar 19 12:27:54 PM PDT 24
Peak memory 183580 kb
Host smart-e461d06a-f4f0-45b1-a01f-bc3d384db808
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819684799 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon
_timer_same_csr_outstanding.819684799
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.2815182903
Short name T319
Test name
Test status
Simulation time 650131370 ps
CPU time 2.3 seconds
Started Mar 19 12:27:56 PM PDT 24
Finished Mar 19 12:27:59 PM PDT 24
Peak memory 198484 kb
Host smart-3ad5a19c-c835-49fe-9f40-771e20241c19
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815182903 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.2815182903
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.2667876454
Short name T411
Test name
Test status
Simulation time 418323839 ps
CPU time 0.92 seconds
Started Mar 19 12:27:41 PM PDT 24
Finished Mar 19 12:27:42 PM PDT 24
Peak memory 196512 kb
Host smart-13cadef9-1912-4568-89cf-1e4e814f069f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667876454 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.2667876454
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.4063093753
Short name T407
Test name
Test status
Simulation time 564477772 ps
CPU time 0.7 seconds
Started Mar 19 12:27:49 PM PDT 24
Finished Mar 19 12:27:50 PM PDT 24
Peak memory 192880 kb
Host smart-c50d2936-8a32-4678-8bea-63df2b0a0861
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063093753 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.4063093753
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.3043689191
Short name T309
Test name
Test status
Simulation time 503049238 ps
CPU time 1.24 seconds
Started Mar 19 12:27:46 PM PDT 24
Finished Mar 19 12:27:47 PM PDT 24
Peak memory 183524 kb
Host smart-4c607659-d1bf-4745-bd4b-2a7cf4e64e0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043689191 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.3043689191
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.1178767577
Short name T338
Test name
Test status
Simulation time 2215178044 ps
CPU time 1.56 seconds
Started Mar 19 12:27:51 PM PDT 24
Finished Mar 19 12:27:52 PM PDT 24
Peak memory 194612 kb
Host smart-0dba0eea-dd1f-488a-bd30-412f2b60d6b9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178767577 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao
n_timer_same_csr_outstanding.1178767577
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.2711427012
Short name T316
Test name
Test status
Simulation time 431816035 ps
CPU time 1.13 seconds
Started Mar 19 12:27:48 PM PDT 24
Finished Mar 19 12:27:49 PM PDT 24
Peak memory 196512 kb
Host smart-a7d633f5-e281-4513-8369-8e6a600fd1d9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711427012 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.2711427012
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.332303133
Short name T402
Test name
Test status
Simulation time 4276122610 ps
CPU time 5.74 seconds
Started Mar 19 12:27:41 PM PDT 24
Finished Mar 19 12:27:47 PM PDT 24
Peak memory 197696 kb
Host smart-5860b164-c18f-4e54-bc3a-8dcb208c66a8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332303133 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl
_intg_err.332303133
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.2335353465
Short name T67
Test name
Test status
Simulation time 595594269 ps
CPU time 1.13 seconds
Started Mar 19 12:27:26 PM PDT 24
Finished Mar 19 12:27:27 PM PDT 24
Peak memory 194092 kb
Host smart-a645d6d2-d5e1-4758-b2fc-19dca7f73a56
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335353465 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_a
liasing.2335353465
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.3058538276
Short name T73
Test name
Test status
Simulation time 6996468601 ps
CPU time 9.88 seconds
Started Mar 19 12:27:42 PM PDT 24
Finished Mar 19 12:27:52 PM PDT 24
Peak memory 192136 kb
Host smart-b6b680e7-1c52-4211-92f3-0e3c257785d9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058538276 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_b
it_bash.3058538276
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.4034596912
Short name T285
Test name
Test status
Simulation time 884475896 ps
CPU time 0.92 seconds
Started Mar 19 12:27:37 PM PDT 24
Finished Mar 19 12:27:38 PM PDT 24
Peak memory 183660 kb
Host smart-1203e42f-028f-4555-94f8-e88f4309ae38
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034596912 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_h
w_reset.4034596912
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.74200779
Short name T321
Test name
Test status
Simulation time 501220415 ps
CPU time 0.78 seconds
Started Mar 19 12:27:41 PM PDT 24
Finished Mar 19 12:27:41 PM PDT 24
Peak memory 195792 kb
Host smart-04b94131-99a5-4e31-8d46-07a1e7cddc51
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74200779 -assert nopostproc +UVM_TESTNAME=a
on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.74200779
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.4013365702
Short name T397
Test name
Test status
Simulation time 290372153 ps
CPU time 0.96 seconds
Started Mar 19 12:27:34 PM PDT 24
Finished Mar 19 12:27:36 PM PDT 24
Peak memory 192904 kb
Host smart-84f375a1-c379-4a6f-9326-099505d3b8d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013365702 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.4013365702
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.3277883818
Short name T350
Test name
Test status
Simulation time 281826036 ps
CPU time 0.8 seconds
Started Mar 19 12:27:50 PM PDT 24
Finished Mar 19 12:27:50 PM PDT 24
Peak memory 183532 kb
Host smart-43924c48-ae2b-450c-a533-d58cb1bae651
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277883818 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.3277883818
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.1514594341
Short name T399
Test name
Test status
Simulation time 341197327 ps
CPU time 0.55 seconds
Started Mar 19 12:27:34 PM PDT 24
Finished Mar 19 12:27:35 PM PDT 24
Peak memory 183544 kb
Host smart-7386d781-128d-4201-99e5-664d4b0b0ae2
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514594341 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_t
imer_mem_partial_access.1514594341
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.3795602474
Short name T342
Test name
Test status
Simulation time 378654250 ps
CPU time 0.76 seconds
Started Mar 19 12:27:26 PM PDT 24
Finished Mar 19 12:27:27 PM PDT 24
Peak memory 183628 kb
Host smart-8cd87cfe-39d1-4a1c-b5fe-2b09be452eae
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795602474 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_w
alk.3795602474
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.136733798
Short name T81
Test name
Test status
Simulation time 2754363616 ps
CPU time 6.01 seconds
Started Mar 19 12:27:41 PM PDT 24
Finished Mar 19 12:27:47 PM PDT 24
Peak memory 194368 kb
Host smart-9bce8c24-52a4-4988-8faf-a45c2ac9d74e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136733798 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_
timer_same_csr_outstanding.136733798
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.2037300673
Short name T349
Test name
Test status
Simulation time 515821191 ps
CPU time 2.05 seconds
Started Mar 19 12:27:41 PM PDT 24
Finished Mar 19 12:27:43 PM PDT 24
Peak memory 198428 kb
Host smart-b1d625a4-23fc-417a-ad85-2031324261b8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037300673 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.2037300673
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.3811983715
Short name T372
Test name
Test status
Simulation time 7939967583 ps
CPU time 7.65 seconds
Started Mar 19 12:27:37 PM PDT 24
Finished Mar 19 12:27:45 PM PDT 24
Peak memory 197736 kb
Host smart-34c4cd6f-ccb2-4afb-8650-0a788b13388b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811983715 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl
_intg_err.3811983715
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.1269626427
Short name T324
Test name
Test status
Simulation time 301343824 ps
CPU time 0.6 seconds
Started Mar 19 12:27:41 PM PDT 24
Finished Mar 19 12:27:42 PM PDT 24
Peak memory 183520 kb
Host smart-5277694c-5b0f-4cf9-abff-4676f85f1e2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269626427 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.1269626427
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.2370913152
Short name T385
Test name
Test status
Simulation time 349400626 ps
CPU time 0.63 seconds
Started Mar 19 12:27:40 PM PDT 24
Finished Mar 19 12:27:41 PM PDT 24
Peak memory 183544 kb
Host smart-41c3dd7f-b678-4aab-93ce-96918ae5fc8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370913152 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.2370913152
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.4154142250
Short name T313
Test name
Test status
Simulation time 546952871 ps
CPU time 0.57 seconds
Started Mar 19 12:28:18 PM PDT 24
Finished Mar 19 12:28:19 PM PDT 24
Peak memory 183524 kb
Host smart-5c87753d-8c3a-4a7c-91d0-24ad30c63a58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154142250 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.4154142250
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.3537926117
Short name T325
Test name
Test status
Simulation time 489792588 ps
CPU time 0.69 seconds
Started Mar 19 12:27:45 PM PDT 24
Finished Mar 19 12:27:45 PM PDT 24
Peak memory 183524 kb
Host smart-cdee80c9-f2e9-43a1-b762-ddb05f679ce9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537926117 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.3537926117
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.3564820612
Short name T419
Test name
Test status
Simulation time 275390229 ps
CPU time 0.87 seconds
Started Mar 19 12:27:42 PM PDT 24
Finished Mar 19 12:27:43 PM PDT 24
Peak memory 183544 kb
Host smart-8df9e004-3899-45c9-8744-552221709342
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564820612 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.3564820612
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.3407756622
Short name T362
Test name
Test status
Simulation time 284021293 ps
CPU time 0.66 seconds
Started Mar 19 12:28:26 PM PDT 24
Finished Mar 19 12:28:27 PM PDT 24
Peak memory 183520 kb
Host smart-a69be559-e3ba-4685-9a6d-3d13d9dd80fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407756622 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.3407756622
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.4219955256
Short name T333
Test name
Test status
Simulation time 427348540 ps
CPU time 1.15 seconds
Started Mar 19 12:27:34 PM PDT 24
Finished Mar 19 12:27:36 PM PDT 24
Peak memory 183536 kb
Host smart-3daa7d7e-7e33-4dfb-b965-15a7703cd3cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219955256 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.4219955256
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.2281400595
Short name T359
Test name
Test status
Simulation time 283978549 ps
CPU time 0.63 seconds
Started Mar 19 12:27:47 PM PDT 24
Finished Mar 19 12:27:48 PM PDT 24
Peak memory 183540 kb
Host smart-97ab3f22-7d16-4dd7-8522-34cd6b9c2806
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281400595 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.2281400595
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.63688930
Short name T341
Test name
Test status
Simulation time 489418457 ps
CPU time 0.63 seconds
Started Mar 19 12:27:46 PM PDT 24
Finished Mar 19 12:27:47 PM PDT 24
Peak memory 183524 kb
Host smart-0a6c892b-cfb5-4404-b19f-0a1cfcc90ee0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63688930 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.63688930
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.3898916433
Short name T305
Test name
Test status
Simulation time 495667835 ps
CPU time 1.24 seconds
Started Mar 19 12:28:07 PM PDT 24
Finished Mar 19 12:28:08 PM PDT 24
Peak memory 183528 kb
Host smart-febfb649-0859-452f-8545-db7e0041b7f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898916433 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.3898916433
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.2896001885
Short name T64
Test name
Test status
Simulation time 689836644 ps
CPU time 0.83 seconds
Started Mar 19 12:27:41 PM PDT 24
Finished Mar 19 12:27:42 PM PDT 24
Peak memory 191860 kb
Host smart-a0966061-fb2b-4848-9e82-e0714243d7e0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896001885 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_a
liasing.2896001885
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.1466114689
Short name T62
Test name
Test status
Simulation time 8739260451 ps
CPU time 8.26 seconds
Started Mar 19 12:27:47 PM PDT 24
Finished Mar 19 12:27:55 PM PDT 24
Peak memory 183976 kb
Host smart-567a5d76-d769-4248-a3ca-fcc0f6b787fb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466114689 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_b
it_bash.1466114689
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.1186810567
Short name T409
Test name
Test status
Simulation time 968751694 ps
CPU time 2.09 seconds
Started Mar 19 12:27:43 PM PDT 24
Finished Mar 19 12:27:45 PM PDT 24
Peak memory 183660 kb
Host smart-2da7315c-bb5a-4f60-873d-3879ced33e3c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186810567 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_h
w_reset.1186810567
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.3199116150
Short name T290
Test name
Test status
Simulation time 570139175 ps
CPU time 1.36 seconds
Started Mar 19 12:28:00 PM PDT 24
Finished Mar 19 12:28:01 PM PDT 24
Peak memory 195928 kb
Host smart-9ec43fdc-de9d-4d26-a5f5-93f445f73060
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199116150 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.3199116150
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.1007276950
Short name T71
Test name
Test status
Simulation time 472631730 ps
CPU time 0.86 seconds
Started Mar 19 12:27:29 PM PDT 24
Finished Mar 19 12:27:30 PM PDT 24
Peak memory 183620 kb
Host smart-3b54c0c9-504d-4dcc-8218-00b33784d616
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007276950 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.1007276950
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.2737926186
Short name T408
Test name
Test status
Simulation time 521021524 ps
CPU time 0.77 seconds
Started Mar 19 12:27:39 PM PDT 24
Finished Mar 19 12:27:40 PM PDT 24
Peak memory 183620 kb
Host smart-4b187400-77c9-4ad5-95f4-fcdf02f2802f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737926186 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.2737926186
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.2220612954
Short name T392
Test name
Test status
Simulation time 506062502 ps
CPU time 0.69 seconds
Started Mar 19 12:27:41 PM PDT 24
Finished Mar 19 12:27:42 PM PDT 24
Peak memory 183560 kb
Host smart-8318234b-e5ac-4343-a76c-a5cbf56f6f29
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220612954 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_t
imer_mem_partial_access.2220612954
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.185154244
Short name T327
Test name
Test status
Simulation time 500924805 ps
CPU time 0.86 seconds
Started Mar 19 12:27:37 PM PDT 24
Finished Mar 19 12:27:38 PM PDT 24
Peak memory 183584 kb
Host smart-0c786f2b-25a0-4cc3-9117-fcb040a112dd
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185154244 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_wa
lk.185154244
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.4193325737
Short name T84
Test name
Test status
Simulation time 1108892011 ps
CPU time 0.96 seconds
Started Mar 19 12:27:39 PM PDT 24
Finished Mar 19 12:27:40 PM PDT 24
Peak memory 183672 kb
Host smart-d5d411de-3def-4396-be6e-895da50b3fd9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193325737 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon
_timer_same_csr_outstanding.4193325737
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.3435763826
Short name T335
Test name
Test status
Simulation time 701375163 ps
CPU time 2.3 seconds
Started Mar 19 12:27:47 PM PDT 24
Finished Mar 19 12:27:50 PM PDT 24
Peak memory 198552 kb
Host smart-c6b010bb-1bbd-4f23-b185-093317790ad1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435763826 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.3435763826
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.1511126287
Short name T115
Test name
Test status
Simulation time 4231795189 ps
CPU time 7.87 seconds
Started Mar 19 12:28:23 PM PDT 24
Finished Mar 19 12:28:31 PM PDT 24
Peak memory 197596 kb
Host smart-459a8917-5ba7-4a09-981a-18404b3e1b4a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511126287 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl
_intg_err.1511126287
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.260796674
Short name T287
Test name
Test status
Simulation time 374322245 ps
CPU time 1.09 seconds
Started Mar 19 12:27:49 PM PDT 24
Finished Mar 19 12:27:50 PM PDT 24
Peak memory 183536 kb
Host smart-9bf79f54-eae2-40c2-b08b-aff0a306b742
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260796674 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.260796674
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.1933210224
Short name T288
Test name
Test status
Simulation time 613391768 ps
CPU time 0.58 seconds
Started Mar 19 12:27:53 PM PDT 24
Finished Mar 19 12:27:54 PM PDT 24
Peak memory 183540 kb
Host smart-64b1851a-f415-4dc9-a729-1be61a737327
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933210224 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.1933210224
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.2042439027
Short name T354
Test name
Test status
Simulation time 432788333 ps
CPU time 1.19 seconds
Started Mar 19 12:27:40 PM PDT 24
Finished Mar 19 12:27:42 PM PDT 24
Peak memory 183612 kb
Host smart-904f7786-a09f-4b89-9f21-76a84f00e568
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042439027 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.2042439027
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.3164278726
Short name T284
Test name
Test status
Simulation time 507699831 ps
CPU time 1.28 seconds
Started Mar 19 12:27:40 PM PDT 24
Finished Mar 19 12:27:42 PM PDT 24
Peak memory 183600 kb
Host smart-709c05b4-92d6-4a03-9e5a-6367da9cd565
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164278726 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.3164278726
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.2252116204
Short name T339
Test name
Test status
Simulation time 307746740 ps
CPU time 0.6 seconds
Started Mar 19 12:27:41 PM PDT 24
Finished Mar 19 12:27:42 PM PDT 24
Peak memory 183520 kb
Host smart-b614114b-4a13-46ce-8e5d-080b0fa356f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252116204 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.2252116204
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.1345735576
Short name T292
Test name
Test status
Simulation time 531105050 ps
CPU time 0.79 seconds
Started Mar 19 12:27:44 PM PDT 24
Finished Mar 19 12:27:45 PM PDT 24
Peak memory 183516 kb
Host smart-10ea5fdc-49c0-4f6c-9171-79eb8c8a44c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345735576 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.1345735576
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.3940935846
Short name T380
Test name
Test status
Simulation time 518141143 ps
CPU time 0.71 seconds
Started Mar 19 12:27:45 PM PDT 24
Finished Mar 19 12:27:46 PM PDT 24
Peak memory 183536 kb
Host smart-18e7c733-4c1a-46d6-89c5-9a2d8a23686a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940935846 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.3940935846
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.1257771463
Short name T384
Test name
Test status
Simulation time 427762998 ps
CPU time 0.65 seconds
Started Mar 19 12:27:44 PM PDT 24
Finished Mar 19 12:27:45 PM PDT 24
Peak memory 183612 kb
Host smart-19cca038-637b-4645-99c2-8de6a63d2d5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257771463 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.1257771463
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.118502308
Short name T352
Test name
Test status
Simulation time 497151455 ps
CPU time 0.86 seconds
Started Mar 19 12:27:43 PM PDT 24
Finished Mar 19 12:27:44 PM PDT 24
Peak memory 183540 kb
Host smart-9969f36b-c0f6-4811-9446-c049ed0e42da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118502308 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.118502308
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.2809326873
Short name T363
Test name
Test status
Simulation time 458392153 ps
CPU time 0.88 seconds
Started Mar 19 12:27:47 PM PDT 24
Finished Mar 19 12:27:48 PM PDT 24
Peak memory 183596 kb
Host smart-9dee0e0b-cb2e-47ca-9559-6a774ead3567
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809326873 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.2809326873
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.2329857623
Short name T35
Test name
Test status
Simulation time 556986037 ps
CPU time 1.54 seconds
Started Mar 19 12:27:28 PM PDT 24
Finished Mar 19 12:27:30 PM PDT 24
Peak memory 183688 kb
Host smart-e050f9d3-db5d-48bc-80ea-19e8c0c099a0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329857623 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_a
liasing.2329857623
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.2990783679
Short name T394
Test name
Test status
Simulation time 7266213605 ps
CPU time 4.14 seconds
Started Mar 19 12:28:12 PM PDT 24
Finished Mar 19 12:28:16 PM PDT 24
Peak memory 183896 kb
Host smart-b659f8a1-b44b-4241-9e2f-45291840ca32
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990783679 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_b
it_bash.2990783679
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.971224740
Short name T63
Test name
Test status
Simulation time 1348498595 ps
CPU time 1.08 seconds
Started Mar 19 12:27:41 PM PDT 24
Finished Mar 19 12:27:42 PM PDT 24
Peak memory 183648 kb
Host smart-4460786c-d3e3-4d97-a111-a293f5c70f42
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971224740 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_hw
_reset.971224740
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.2238069812
Short name T382
Test name
Test status
Simulation time 708492166 ps
CPU time 1.1 seconds
Started Mar 19 12:28:22 PM PDT 24
Finished Mar 19 12:28:23 PM PDT 24
Peak memory 198260 kb
Host smart-70fcb5cc-ee03-48dd-8280-c21b14a073b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238069812 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.2238069812
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.3495824639
Short name T72
Test name
Test status
Simulation time 386933691 ps
CPU time 1.2 seconds
Started Mar 19 12:27:45 PM PDT 24
Finished Mar 19 12:27:46 PM PDT 24
Peak memory 183872 kb
Host smart-ef736893-e776-4855-8466-ef3bb236ba42
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495824639 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.3495824639
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.830540968
Short name T417
Test name
Test status
Simulation time 358949419 ps
CPU time 0.98 seconds
Started Mar 19 12:27:42 PM PDT 24
Finished Mar 19 12:27:43 PM PDT 24
Peak memory 183516 kb
Host smart-4f34d4fa-b290-473f-bc75-d19f9a8d22fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830540968 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.830540968
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.3423515516
Short name T418
Test name
Test status
Simulation time 320784025 ps
CPU time 1 seconds
Started Mar 19 12:27:44 PM PDT 24
Finished Mar 19 12:27:46 PM PDT 24
Peak memory 183516 kb
Host smart-0c7a4f60-ff7a-4474-aec1-05d26f6412e9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423515516 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_t
imer_mem_partial_access.3423515516
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.1474882646
Short name T386
Test name
Test status
Simulation time 286319251 ps
CPU time 0.95 seconds
Started Mar 19 12:27:41 PM PDT 24
Finished Mar 19 12:27:42 PM PDT 24
Peak memory 183572 kb
Host smart-f48db6a6-4afe-4458-a433-d7a43874d38a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474882646 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_w
alk.1474882646
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.571874642
Short name T376
Test name
Test status
Simulation time 2444416171 ps
CPU time 1.55 seconds
Started Mar 19 12:27:42 PM PDT 24
Finished Mar 19 12:27:44 PM PDT 24
Peak memory 191928 kb
Host smart-1c99773d-3c9b-4fbb-b241-a2a3ef4fb8de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571874642 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_
timer_same_csr_outstanding.571874642
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.3405424347
Short name T347
Test name
Test status
Simulation time 626692870 ps
CPU time 2.46 seconds
Started Mar 19 12:27:40 PM PDT 24
Finished Mar 19 12:27:43 PM PDT 24
Peak memory 198460 kb
Host smart-a18a1cdd-7cb3-4074-8f87-ddadfe636adb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405424347 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.3405424347
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.3240399759
Short name T345
Test name
Test status
Simulation time 8510953965 ps
CPU time 3.47 seconds
Started Mar 19 12:28:19 PM PDT 24
Finished Mar 19 12:28:23 PM PDT 24
Peak memory 197656 kb
Host smart-c395390c-d7f4-463c-aae7-454d8560c503
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240399759 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl
_intg_err.3240399759
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.3533634217
Short name T358
Test name
Test status
Simulation time 466952447 ps
CPU time 0.62 seconds
Started Mar 19 12:27:44 PM PDT 24
Finished Mar 19 12:27:45 PM PDT 24
Peak memory 183524 kb
Host smart-c5bc5b6d-af46-4be8-af5f-751d86f807a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533634217 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.3533634217
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.3533313015
Short name T302
Test name
Test status
Simulation time 422159464 ps
CPU time 1.18 seconds
Started Mar 19 12:27:46 PM PDT 24
Finished Mar 19 12:27:47 PM PDT 24
Peak memory 183564 kb
Host smart-928f475b-168b-4514-b8e3-59a62075befa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533313015 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.3533313015
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.1251989190
Short name T367
Test name
Test status
Simulation time 557563916 ps
CPU time 0.58 seconds
Started Mar 19 12:27:40 PM PDT 24
Finished Mar 19 12:27:40 PM PDT 24
Peak memory 183528 kb
Host smart-ffc99262-3b75-43a1-ac27-026d8ecc0083
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251989190 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.1251989190
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.3426577563
Short name T403
Test name
Test status
Simulation time 304770044 ps
CPU time 0.64 seconds
Started Mar 19 12:28:09 PM PDT 24
Finished Mar 19 12:28:09 PM PDT 24
Peak memory 183544 kb
Host smart-464a2b50-fa34-4092-b8a8-81fd243d92cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426577563 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.3426577563
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.1251172673
Short name T383
Test name
Test status
Simulation time 459471387 ps
CPU time 0.73 seconds
Started Mar 19 12:28:04 PM PDT 24
Finished Mar 19 12:28:05 PM PDT 24
Peak memory 183548 kb
Host smart-2fe8067d-1f88-4158-80f9-c8a77c74b5f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251172673 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.1251172673
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.688587285
Short name T289
Test name
Test status
Simulation time 491325062 ps
CPU time 0.73 seconds
Started Mar 19 12:27:41 PM PDT 24
Finished Mar 19 12:27:47 PM PDT 24
Peak memory 183544 kb
Host smart-b5dcddfd-88dd-49c7-a286-3b9bdd7996ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688587285 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.688587285
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.1056258403
Short name T373
Test name
Test status
Simulation time 464835497 ps
CPU time 0.81 seconds
Started Mar 19 12:27:47 PM PDT 24
Finished Mar 19 12:27:47 PM PDT 24
Peak memory 183548 kb
Host smart-029fc224-26cd-4f96-b3c1-01da211e3510
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056258403 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.1056258403
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.577379160
Short name T353
Test name
Test status
Simulation time 271563121 ps
CPU time 0.93 seconds
Started Mar 19 12:27:45 PM PDT 24
Finished Mar 19 12:27:46 PM PDT 24
Peak memory 183544 kb
Host smart-32f00f2f-4be6-45f4-a550-99966b106705
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577379160 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.577379160
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.1516608804
Short name T336
Test name
Test status
Simulation time 539111390 ps
CPU time 0.72 seconds
Started Mar 19 12:27:44 PM PDT 24
Finished Mar 19 12:27:44 PM PDT 24
Peak memory 183520 kb
Host smart-bdca4985-7d22-46e1-bb9b-fd7c518a69a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516608804 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.1516608804
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.2283734991
Short name T304
Test name
Test status
Simulation time 276398712 ps
CPU time 1 seconds
Started Mar 19 12:28:02 PM PDT 24
Finished Mar 19 12:28:03 PM PDT 24
Peak memory 183616 kb
Host smart-0ae70eb2-0a15-4f20-9d7d-d30d1df5d9ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283734991 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.2283734991
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.179682905
Short name T415
Test name
Test status
Simulation time 525255296 ps
CPU time 1.04 seconds
Started Mar 19 12:27:37 PM PDT 24
Finished Mar 19 12:27:38 PM PDT 24
Peak memory 195824 kb
Host smart-375bff62-3e59-41f9-b6a0-d0eb35898314
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179682905 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.179682905
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.3199746804
Short name T80
Test name
Test status
Simulation time 444805229 ps
CPU time 1.27 seconds
Started Mar 19 12:27:26 PM PDT 24
Finished Mar 19 12:27:28 PM PDT 24
Peak memory 183772 kb
Host smart-be6b3648-c3f7-49ec-9702-43be9668cb2d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199746804 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.3199746804
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.827938515
Short name T340
Test name
Test status
Simulation time 440688102 ps
CPU time 1.26 seconds
Started Mar 19 12:27:19 PM PDT 24
Finished Mar 19 12:27:21 PM PDT 24
Peak memory 183516 kb
Host smart-756ad890-cb55-43e0-a68b-9fd4cd017c78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827938515 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.827938515
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.1824817921
Short name T387
Test name
Test status
Simulation time 1887484310 ps
CPU time 4.09 seconds
Started Mar 19 12:27:27 PM PDT 24
Finished Mar 19 12:27:32 PM PDT 24
Peak memory 193840 kb
Host smart-d50f1ef9-22b7-488a-9093-9060f413b30b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824817921 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon
_timer_same_csr_outstanding.1824817921
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.171301000
Short name T343
Test name
Test status
Simulation time 507759492 ps
CPU time 2.24 seconds
Started Mar 19 12:27:49 PM PDT 24
Finished Mar 19 12:27:51 PM PDT 24
Peak memory 198516 kb
Host smart-d228bbf9-4714-4e16-9ede-b7d447565e64
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171301000 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.171301000
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.3556089777
Short name T117
Test name
Test status
Simulation time 8389751920 ps
CPU time 3.07 seconds
Started Mar 19 12:27:43 PM PDT 24
Finished Mar 19 12:27:46 PM PDT 24
Peak memory 197868 kb
Host smart-ec291a22-c70a-4c1f-bcca-13a690a58791
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556089777 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl
_intg_err.3556089777
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.1584773307
Short name T310
Test name
Test status
Simulation time 568778043 ps
CPU time 1.1 seconds
Started Mar 19 12:27:40 PM PDT 24
Finished Mar 19 12:27:41 PM PDT 24
Peak memory 196740 kb
Host smart-f5ea7c32-15fc-4cc3-af29-a7051c15d50c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584773307 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.1584773307
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.3405943052
Short name T66
Test name
Test status
Simulation time 496449240 ps
CPU time 1.37 seconds
Started Mar 19 12:27:46 PM PDT 24
Finished Mar 19 12:27:47 PM PDT 24
Peak memory 192956 kb
Host smart-47947c7a-23d0-4936-a686-b5b226f67261
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405943052 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.3405943052
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.475261302
Short name T377
Test name
Test status
Simulation time 474107001 ps
CPU time 1.3 seconds
Started Mar 19 12:28:35 PM PDT 24
Finished Mar 19 12:28:37 PM PDT 24
Peak memory 183520 kb
Host smart-c356d22f-3570-4fb0-81f2-12cef571bba1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475261302 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.475261302
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.3667638788
Short name T388
Test name
Test status
Simulation time 808161833 ps
CPU time 2.47 seconds
Started Mar 19 12:27:30 PM PDT 24
Finished Mar 19 12:27:32 PM PDT 24
Peak memory 183800 kb
Host smart-ff76dbe5-964f-415e-b057-c20010a1b58d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667638788 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon
_timer_same_csr_outstanding.3667638788
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.3928879674
Short name T404
Test name
Test status
Simulation time 500166257 ps
CPU time 2 seconds
Started Mar 19 12:28:34 PM PDT 24
Finished Mar 19 12:28:36 PM PDT 24
Peak memory 198516 kb
Host smart-7be44560-43aa-4944-ad76-94eefabca284
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928879674 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.3928879674
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.490832830
Short name T369
Test name
Test status
Simulation time 4809003094 ps
CPU time 2.02 seconds
Started Mar 19 12:27:41 PM PDT 24
Finished Mar 19 12:27:43 PM PDT 24
Peak memory 197404 kb
Host smart-d99a12ae-0128-4790-8e66-19640a91a22d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490832830 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_
intg_err.490832830
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.3917026798
Short name T291
Test name
Test status
Simulation time 514843720 ps
CPU time 1.35 seconds
Started Mar 19 12:27:41 PM PDT 24
Finished Mar 19 12:27:42 PM PDT 24
Peak memory 196664 kb
Host smart-5677827d-3abe-45aa-90e1-1a1b6bcc0c62
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917026798 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.3917026798
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.148473154
Short name T360
Test name
Test status
Simulation time 501067554 ps
CPU time 0.7 seconds
Started Mar 19 12:28:14 PM PDT 24
Finished Mar 19 12:28:16 PM PDT 24
Peak memory 183652 kb
Host smart-3e5f3602-fe81-4099-9e47-da8d87bc65f9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148473154 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.148473154
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.3781625144
Short name T332
Test name
Test status
Simulation time 415373405 ps
CPU time 1.2 seconds
Started Mar 19 12:27:43 PM PDT 24
Finished Mar 19 12:27:44 PM PDT 24
Peak memory 183444 kb
Host smart-8bf44e1e-6261-40de-a9b8-29d35bd3ab80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781625144 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.3781625144
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.2910066377
Short name T375
Test name
Test status
Simulation time 2758584796 ps
CPU time 4.65 seconds
Started Mar 19 12:28:42 PM PDT 24
Finished Mar 19 12:28:47 PM PDT 24
Peak memory 194640 kb
Host smart-2a55e1d3-2efd-41d3-aa16-75d17e607b1b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910066377 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon
_timer_same_csr_outstanding.2910066377
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.3624190052
Short name T330
Test name
Test status
Simulation time 546677544 ps
CPU time 1.77 seconds
Started Mar 19 12:27:44 PM PDT 24
Finished Mar 19 12:27:46 PM PDT 24
Peak memory 198488 kb
Host smart-b11936ec-dfc4-4dde-97ff-6d20c78ed255
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624190052 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.3624190052
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.2785610511
Short name T43
Test name
Test status
Simulation time 8796614676 ps
CPU time 12.7 seconds
Started Mar 19 12:28:40 PM PDT 24
Finished Mar 19 12:28:53 PM PDT 24
Peak memory 197864 kb
Host smart-a9818fe9-e354-4edd-accf-abf1c80c28d3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785610511 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl
_intg_err.2785610511
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.3466295074
Short name T371
Test name
Test status
Simulation time 407612615 ps
CPU time 0.75 seconds
Started Mar 19 12:28:03 PM PDT 24
Finished Mar 19 12:28:04 PM PDT 24
Peak memory 195684 kb
Host smart-02bff921-018e-467a-a4ac-0a861c64dc29
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466295074 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.3466295074
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.1258193840
Short name T70
Test name
Test status
Simulation time 391725744 ps
CPU time 0.63 seconds
Started Mar 19 12:27:58 PM PDT 24
Finished Mar 19 12:27:59 PM PDT 24
Peak memory 183744 kb
Host smart-7b972bff-99e9-4d8f-993d-9a685b72288c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258193840 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.1258193840
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.3368766224
Short name T381
Test name
Test status
Simulation time 380758038 ps
CPU time 0.72 seconds
Started Mar 19 12:27:41 PM PDT 24
Finished Mar 19 12:27:42 PM PDT 24
Peak memory 183524 kb
Host smart-da133193-320f-423e-a971-ada4ecf5e939
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368766224 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.3368766224
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.1282504820
Short name T83
Test name
Test status
Simulation time 2734732822 ps
CPU time 1.77 seconds
Started Mar 19 12:27:42 PM PDT 24
Finished Mar 19 12:27:43 PM PDT 24
Peak memory 194604 kb
Host smart-5c1b964e-d9ab-45af-9479-e0a9efdef191
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282504820 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon
_timer_same_csr_outstanding.1282504820
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.3754110612
Short name T283
Test name
Test status
Simulation time 460458659 ps
CPU time 2.36 seconds
Started Mar 19 12:27:53 PM PDT 24
Finished Mar 19 12:27:55 PM PDT 24
Peak memory 198472 kb
Host smart-4ac771a9-ed35-4d4f-966e-0ada2cdfce10
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754110612 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.3754110612
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.1184762047
Short name T303
Test name
Test status
Simulation time 4891554293 ps
CPU time 8.4 seconds
Started Mar 19 12:27:29 PM PDT 24
Finished Mar 19 12:27:37 PM PDT 24
Peak memory 197656 kb
Host smart-67055c01-d042-4e0c-bb13-fca24e3cb03a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184762047 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl
_intg_err.1184762047
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.815781481
Short name T348
Test name
Test status
Simulation time 641479968 ps
CPU time 0.84 seconds
Started Mar 19 12:27:44 PM PDT 24
Finished Mar 19 12:27:45 PM PDT 24
Peak memory 196896 kb
Host smart-f8b90892-32bd-40fc-a06a-9fbb3d537a39
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815781481 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.815781481
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.535202402
Short name T87
Test name
Test status
Simulation time 514542725 ps
CPU time 0.78 seconds
Started Mar 19 12:27:35 PM PDT 24
Finished Mar 19 12:27:36 PM PDT 24
Peak memory 183876 kb
Host smart-e396f594-0b49-4643-a472-1de773bed535
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535202402 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.535202402
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.199514362
Short name T401
Test name
Test status
Simulation time 505900412 ps
CPU time 1.24 seconds
Started Mar 19 12:27:31 PM PDT 24
Finished Mar 19 12:27:33 PM PDT 24
Peak memory 183620 kb
Host smart-46b9fc8e-e48b-4d8d-8770-902db6aa688d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199514362 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.199514362
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.3374053413
Short name T389
Test name
Test status
Simulation time 2320897153 ps
CPU time 2.37 seconds
Started Mar 19 12:27:48 PM PDT 24
Finished Mar 19 12:27:51 PM PDT 24
Peak memory 194268 kb
Host smart-830cddff-0df2-47b5-b2bd-de386259da6f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374053413 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon
_timer_same_csr_outstanding.3374053413
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.615029571
Short name T357
Test name
Test status
Simulation time 752940854 ps
CPU time 2.05 seconds
Started Mar 19 12:27:30 PM PDT 24
Finished Mar 19 12:27:32 PM PDT 24
Peak memory 198452 kb
Host smart-de76e1ff-b481-48ca-b15e-af2d332f9ed7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615029571 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.615029571
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.3592926423
Short name T116
Test name
Test status
Simulation time 7958114704 ps
CPU time 13.49 seconds
Started Mar 19 12:27:42 PM PDT 24
Finished Mar 19 12:27:56 PM PDT 24
Peak memory 197888 kb
Host smart-5984e399-0589-47e6-9bb0-80a755e7e304
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592926423 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl
_intg_err.3592926423
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_jump.3475235347
Short name T12
Test name
Test status
Simulation time 359875515 ps
CPU time 0.75 seconds
Started Mar 19 12:27:25 PM PDT 24
Finished Mar 19 12:27:26 PM PDT 24
Peak memory 181840 kb
Host smart-884cefef-28f2-43f8-80d6-4354bf4b4770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475235347 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.3475235347
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.806310946
Short name T202
Test name
Test status
Simulation time 21237305653 ps
CPU time 15.72 seconds
Started Mar 19 12:26:25 PM PDT 24
Finished Mar 19 12:26:44 PM PDT 24
Peak memory 182180 kb
Host smart-e17d5a45-2778-431a-a8f2-335095dd9b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806310946 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.806310946
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.3254083411
Short name T126
Test name
Test status
Simulation time 575579097 ps
CPU time 1.32 seconds
Started Mar 19 12:26:49 PM PDT 24
Finished Mar 19 12:26:51 PM PDT 24
Peak memory 182112 kb
Host smart-c4d22490-5572-40c2-b0c4-8f0ebc6b9039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254083411 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.3254083411
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.1871088703
Short name T40
Test name
Test status
Simulation time 90308619332 ps
CPU time 117.19 seconds
Started Mar 19 12:26:24 PM PDT 24
Finished Mar 19 12:28:23 PM PDT 24
Peak memory 193932 kb
Host smart-eaceee3b-19e4-4710-b619-afa930f7eebd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871088703 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_a
ll.1871088703
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_jump.1697710762
Short name T32
Test name
Test status
Simulation time 474911220 ps
CPU time 0.76 seconds
Started Mar 19 12:27:25 PM PDT 24
Finished Mar 19 12:27:26 PM PDT 24
Peak memory 182056 kb
Host smart-68f03ff6-cc70-4439-95cd-a2f4bd86c01f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697710762 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.1697710762
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.3310907040
Short name T30
Test name
Test status
Simulation time 37884497884 ps
CPU time 57.52 seconds
Started Mar 19 12:27:41 PM PDT 24
Finished Mar 19 12:28:39 PM PDT 24
Peak memory 182928 kb
Host smart-7e3f5b2d-6e0d-48f6-ae61-38d78957df78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310907040 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.3310907040
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.3198891892
Short name T21
Test name
Test status
Simulation time 4146094595 ps
CPU time 2.25 seconds
Started Mar 19 12:26:30 PM PDT 24
Finished Mar 19 12:26:34 PM PDT 24
Peak memory 213116 kb
Host smart-948edab5-4b99-4172-9410-4c0b7caf15f3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198891892 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.3198891892
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.2880105773
Short name T3
Test name
Test status
Simulation time 645925772 ps
CPU time 0.61 seconds
Started Mar 19 12:26:20 PM PDT 24
Finished Mar 19 12:26:21 PM PDT 24
Peak memory 182824 kb
Host smart-89e2ff76-6dfa-4ff4-818a-2437d5627cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880105773 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.2880105773
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.186112213
Short name T233
Test name
Test status
Simulation time 500183852214 ps
CPU time 334.24 seconds
Started Mar 19 12:26:19 PM PDT 24
Finished Mar 19 12:31:53 PM PDT 24
Peak memory 194020 kb
Host smart-f0e622c5-99c8-4fac-9d40-97563624d46e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186112213 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_al
l.186112213
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.3559931171
Short name T251
Test name
Test status
Simulation time 308103833690 ps
CPU time 616.03 seconds
Started Mar 19 12:27:26 PM PDT 24
Finished Mar 19 12:37:42 PM PDT 24
Peak memory 198640 kb
Host smart-bd8edc18-660d-4bdc-b376-314dccaaed90
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559931171 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.3559931171
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.aon_timer_jump.3125975106
Short name T253
Test name
Test status
Simulation time 464483051 ps
CPU time 0.78 seconds
Started Mar 19 12:26:35 PM PDT 24
Finished Mar 19 12:26:36 PM PDT 24
Peak memory 182980 kb
Host smart-37e37d25-8f22-44ba-b787-a774e987960b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125975106 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.3125975106
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.4201901411
Short name T254
Test name
Test status
Simulation time 56830960475 ps
CPU time 84.76 seconds
Started Mar 19 12:26:21 PM PDT 24
Finished Mar 19 12:27:46 PM PDT 24
Peak memory 182900 kb
Host smart-8871284c-c7de-4ecd-83a4-c4c1dabc3883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201901411 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.4201901411
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.1355841612
Short name T255
Test name
Test status
Simulation time 462354626 ps
CPU time 0.77 seconds
Started Mar 19 12:26:25 PM PDT 24
Finished Mar 19 12:26:27 PM PDT 24
Peak memory 182112 kb
Host smart-013a67a1-1ca4-40a9-999f-7f65638907ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355841612 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.1355841612
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.1383825519
Short name T47
Test name
Test status
Simulation time 26624920458 ps
CPU time 299.86 seconds
Started Mar 19 12:26:28 PM PDT 24
Finished Mar 19 12:31:28 PM PDT 24
Peak memory 197784 kb
Host smart-062aa4d6-8406-4f23-9acb-ac29383b659d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383825519 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.1383825519
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.aon_timer_jump.2670107177
Short name T6
Test name
Test status
Simulation time 513679441 ps
CPU time 0.71 seconds
Started Mar 19 12:26:40 PM PDT 24
Finished Mar 19 12:26:41 PM PDT 24
Peak memory 182812 kb
Host smart-2491db2b-30fc-49cb-a72e-7ca97849debf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670107177 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.2670107177
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.1796968537
Short name T166
Test name
Test status
Simulation time 59327456873 ps
CPU time 48.92 seconds
Started Mar 19 12:26:25 PM PDT 24
Finished Mar 19 12:27:14 PM PDT 24
Peak memory 182912 kb
Host smart-99e42828-e06b-4570-8971-ae4d2744a659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796968537 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.1796968537
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.2985555083
Short name T133
Test name
Test status
Simulation time 448795404 ps
CPU time 0.78 seconds
Started Mar 19 12:26:43 PM PDT 24
Finished Mar 19 12:26:44 PM PDT 24
Peak memory 182856 kb
Host smart-d29c84cd-a541-46e4-a378-005f743825dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985555083 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.2985555083
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.2417445743
Short name T258
Test name
Test status
Simulation time 417179768733 ps
CPU time 116.14 seconds
Started Mar 19 12:26:29 PM PDT 24
Finished Mar 19 12:28:26 PM PDT 24
Peak memory 180728 kb
Host smart-7938245f-29d1-452c-b851-36886ab44385
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417445743 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_
all.2417445743
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.2746111692
Short name T217
Test name
Test status
Simulation time 93082885769 ps
CPU time 232.42 seconds
Started Mar 19 12:26:24 PM PDT 24
Finished Mar 19 12:30:18 PM PDT 24
Peak memory 197796 kb
Host smart-291a5777-55cf-4204-bddc-0cbca6b320f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746111692 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand_reset.2746111692
Directory /workspace/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.aon_timer_jump.679227966
Short name T92
Test name
Test status
Simulation time 606418073 ps
CPU time 1.01 seconds
Started Mar 19 12:26:31 PM PDT 24
Finished Mar 19 12:26:33 PM PDT 24
Peak memory 181828 kb
Host smart-7fa94369-8a67-4697-b80e-4cd6d2d87594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679227966 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.679227966
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.1828859790
Short name T11
Test name
Test status
Simulation time 16848350564 ps
CPU time 7.34 seconds
Started Mar 19 12:26:27 PM PDT 24
Finished Mar 19 12:26:35 PM PDT 24
Peak memory 182840 kb
Host smart-10a714db-c695-499e-b30e-fa51b1c70516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828859790 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.1828859790
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.4198930844
Short name T131
Test name
Test status
Simulation time 552728394 ps
CPU time 0.67 seconds
Started Mar 19 12:26:41 PM PDT 24
Finished Mar 19 12:26:41 PM PDT 24
Peak memory 182892 kb
Host smart-dd1e3669-a089-4399-9d0b-74e30582e6fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198930844 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.4198930844
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.3447958390
Short name T154
Test name
Test status
Simulation time 61761358906 ps
CPU time 263.9 seconds
Started Mar 19 12:26:41 PM PDT 24
Finished Mar 19 12:31:05 PM PDT 24
Peak memory 197964 kb
Host smart-17444f53-0907-488e-9a82-929f7fada4ab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447958390 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.3447958390
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_jump.1548776346
Short name T74
Test name
Test status
Simulation time 564574097 ps
CPU time 0.74 seconds
Started Mar 19 12:26:32 PM PDT 24
Finished Mar 19 12:26:33 PM PDT 24
Peak memory 182828 kb
Host smart-68f6f359-f115-4725-af1e-9713baedd664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548776346 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.1548776346
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.3620721681
Short name T155
Test name
Test status
Simulation time 31398160245 ps
CPU time 49.55 seconds
Started Mar 19 12:26:45 PM PDT 24
Finished Mar 19 12:27:35 PM PDT 24
Peak memory 182892 kb
Host smart-dc123da7-6102-42b9-ba0c-0289aa0d6417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620721681 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.3620721681
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.1881631711
Short name T191
Test name
Test status
Simulation time 509715449 ps
CPU time 0.62 seconds
Started Mar 19 12:26:38 PM PDT 24
Finished Mar 19 12:26:40 PM PDT 24
Peak memory 182872 kb
Host smart-fbe72e6a-a733-491a-8131-c98bf11f0a9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881631711 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.1881631711
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.1864910637
Short name T200
Test name
Test status
Simulation time 182974624953 ps
CPU time 261.63 seconds
Started Mar 19 12:26:24 PM PDT 24
Finished Mar 19 12:30:46 PM PDT 24
Peak memory 193344 kb
Host smart-8f376178-78ad-448e-b70a-8ede9897478a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864910637 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_
all.1864910637
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_jump.3054999280
Short name T218
Test name
Test status
Simulation time 588650312 ps
CPU time 1.36 seconds
Started Mar 19 12:26:24 PM PDT 24
Finished Mar 19 12:26:27 PM PDT 24
Peak memory 182808 kb
Host smart-56e71904-ebc3-43dd-abf0-412b4fe62d4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054999280 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.3054999280
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.540213907
Short name T9
Test name
Test status
Simulation time 33906794374 ps
CPU time 9.84 seconds
Started Mar 19 12:26:20 PM PDT 24
Finished Mar 19 12:26:30 PM PDT 24
Peak memory 182160 kb
Host smart-2a7bc4d2-fd19-4891-9724-2431d68d7d86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540213907 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.540213907
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.1584679146
Short name T235
Test name
Test status
Simulation time 508277485 ps
CPU time 0.74 seconds
Started Mar 19 12:26:43 PM PDT 24
Finished Mar 19 12:26:44 PM PDT 24
Peak memory 182836 kb
Host smart-da534b06-c2ba-4019-be90-bd296ba63db1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584679146 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.1584679146
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.3557857632
Short name T103
Test name
Test status
Simulation time 35380617133 ps
CPU time 15.28 seconds
Started Mar 19 12:26:15 PM PDT 24
Finished Mar 19 12:26:31 PM PDT 24
Peak memory 182200 kb
Host smart-c724b929-0030-4bfb-b91f-fedee845e041
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557857632 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_
all.3557857632
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.1364742639
Short name T49
Test name
Test status
Simulation time 96934843159 ps
CPU time 716.9 seconds
Started Mar 19 12:26:28 PM PDT 24
Finished Mar 19 12:38:25 PM PDT 24
Peak memory 209152 kb
Host smart-ea1ff093-d5a5-47b5-a2af-cfdc9b88c097
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364742639 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.1364742639
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.aon_timer_jump.2386297071
Short name T213
Test name
Test status
Simulation time 389044382 ps
CPU time 1.17 seconds
Started Mar 19 12:26:23 PM PDT 24
Finished Mar 19 12:26:24 PM PDT 24
Peak memory 182632 kb
Host smart-63a057ae-c101-4890-afe9-69125c4c1405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386297071 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.2386297071
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.843353010
Short name T139
Test name
Test status
Simulation time 39710677035 ps
CPU time 4.84 seconds
Started Mar 19 12:26:32 PM PDT 24
Finished Mar 19 12:26:39 PM PDT 24
Peak memory 182004 kb
Host smart-d0187576-eb13-4b13-b7a4-fbbbbe49dac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843353010 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.843353010
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.1944335063
Short name T239
Test name
Test status
Simulation time 400819093 ps
CPU time 0.72 seconds
Started Mar 19 12:26:25 PM PDT 24
Finished Mar 19 12:26:26 PM PDT 24
Peak memory 182100 kb
Host smart-a3af1071-3222-4cca-b19c-e2d13d6c10b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944335063 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.1944335063
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.3562459019
Short name T186
Test name
Test status
Simulation time 26653358835 ps
CPU time 10.02 seconds
Started Mar 19 12:26:45 PM PDT 24
Finished Mar 19 12:26:55 PM PDT 24
Peak memory 192972 kb
Host smart-43361e81-620d-4aa0-a4de-0910afe12979
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562459019 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_
all.3562459019
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.1547086402
Short name T46
Test name
Test status
Simulation time 26137100093 ps
CPU time 192.91 seconds
Started Mar 19 12:26:34 PM PDT 24
Finished Mar 19 12:29:47 PM PDT 24
Peak memory 197808 kb
Host smart-d3842c72-81c0-403b-b49b-9eab2dd41a24
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547086402 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.1547086402
Directory /workspace/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.aon_timer_jump.702028544
Short name T279
Test name
Test status
Simulation time 522270184 ps
CPU time 1.31 seconds
Started Mar 19 12:26:44 PM PDT 24
Finished Mar 19 12:26:45 PM PDT 24
Peak memory 182852 kb
Host smart-b976a98e-7f5a-433c-94ca-298149a1f718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702028544 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.702028544
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.3336317487
Short name T93
Test name
Test status
Simulation time 24949640237 ps
CPU time 17.81 seconds
Started Mar 19 12:26:23 PM PDT 24
Finished Mar 19 12:26:41 PM PDT 24
Peak memory 182196 kb
Host smart-47035774-631c-4599-b853-dbefbcaf9c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336317487 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.3336317487
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.2563831618
Short name T246
Test name
Test status
Simulation time 524183526 ps
CPU time 0.83 seconds
Started Mar 19 12:26:22 PM PDT 24
Finished Mar 19 12:26:23 PM PDT 24
Peak memory 182836 kb
Host smart-2b0a020e-d0f0-4aa1-8661-968e01f23122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563831618 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.2563831618
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.326510768
Short name T250
Test name
Test status
Simulation time 204221749493 ps
CPU time 54.47 seconds
Started Mar 19 12:26:33 PM PDT 24
Finished Mar 19 12:27:28 PM PDT 24
Peak memory 182728 kb
Host smart-42e94c01-f91d-43a8-980e-09a03fe24b54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326510768 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_a
ll.326510768
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.2458752138
Short name T39
Test name
Test status
Simulation time 113727229176 ps
CPU time 1198.57 seconds
Started Mar 19 12:26:30 PM PDT 24
Finished Mar 19 12:46:36 PM PDT 24
Peak memory 207632 kb
Host smart-eedb6908-20dd-4331-aff4-1238c386451e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458752138 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.2458752138
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.aon_timer_jump.611777421
Short name T127
Test name
Test status
Simulation time 517093753 ps
CPU time 0.62 seconds
Started Mar 19 12:26:34 PM PDT 24
Finished Mar 19 12:26:35 PM PDT 24
Peak memory 182840 kb
Host smart-ab672788-8416-48b5-9455-3ff2f35982da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611777421 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.611777421
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.57535183
Short name T172
Test name
Test status
Simulation time 51284839656 ps
CPU time 82.43 seconds
Started Mar 19 12:26:43 PM PDT 24
Finished Mar 19 12:28:06 PM PDT 24
Peak memory 182896 kb
Host smart-f2990cde-b99b-4f77-b893-de4d6e650222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57535183 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.57535183
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.1914683564
Short name T60
Test name
Test status
Simulation time 396012863 ps
CPU time 1.09 seconds
Started Mar 19 12:26:31 PM PDT 24
Finished Mar 19 12:26:32 PM PDT 24
Peak memory 182956 kb
Host smart-8f087c45-f431-4a54-8e3c-544f2aac78a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914683564 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.1914683564
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.4075204630
Short name T151
Test name
Test status
Simulation time 256931213432 ps
CPU time 66.01 seconds
Started Mar 19 12:26:40 PM PDT 24
Finished Mar 19 12:27:47 PM PDT 24
Peak memory 182912 kb
Host smart-184fe160-11c6-448e-9d0f-7a5d8f809854
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075204630 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_
all.4075204630
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.3069450587
Short name T140
Test name
Test status
Simulation time 60396883704 ps
CPU time 159.91 seconds
Started Mar 19 12:26:47 PM PDT 24
Finished Mar 19 12:29:28 PM PDT 24
Peak memory 197816 kb
Host smart-90c48dc1-eddd-4183-b2f0-07aed436ea99
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069450587 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.3069450587
Directory /workspace/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.aon_timer_jump.3967668037
Short name T223
Test name
Test status
Simulation time 551260203 ps
CPU time 0.92 seconds
Started Mar 19 12:26:29 PM PDT 24
Finished Mar 19 12:26:30 PM PDT 24
Peak memory 180448 kb
Host smart-75a396ed-95a3-45af-bba7-4333fbc66dbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967668037 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.3967668037
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.2315994877
Short name T157
Test name
Test status
Simulation time 21503936193 ps
CPU time 9.11 seconds
Started Mar 19 12:26:48 PM PDT 24
Finished Mar 19 12:26:58 PM PDT 24
Peak memory 182932 kb
Host smart-a509cf5d-bf72-45ae-a470-7b170b608158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315994877 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.2315994877
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.2181886031
Short name T13
Test name
Test status
Simulation time 346415580 ps
CPU time 1.02 seconds
Started Mar 19 12:26:27 PM PDT 24
Finished Mar 19 12:26:29 PM PDT 24
Peak memory 182936 kb
Host smart-1429e251-f788-4c8d-858a-91b99f91a474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181886031 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.2181886031
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.1426825273
Short name T106
Test name
Test status
Simulation time 165700636091 ps
CPU time 128.36 seconds
Started Mar 19 12:26:34 PM PDT 24
Finished Mar 19 12:28:43 PM PDT 24
Peak memory 182192 kb
Host smart-7a669f06-0cac-43ab-96e2-cd541488c496
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426825273 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_
all.1426825273
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.2207658050
Short name T252
Test name
Test status
Simulation time 89823775764 ps
CPU time 512.24 seconds
Started Mar 19 12:26:49 PM PDT 24
Finished Mar 19 12:35:21 PM PDT 24
Peak memory 198332 kb
Host smart-5ad4b764-42e4-4763-aacc-e71cd70e3503
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207658050 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.2207658050
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.aon_timer_jump.3877624071
Short name T146
Test name
Test status
Simulation time 388954869 ps
CPU time 1.17 seconds
Started Mar 19 12:26:40 PM PDT 24
Finished Mar 19 12:26:41 PM PDT 24
Peak memory 182792 kb
Host smart-e417c17c-7adb-45c9-b3cd-cbf71c77850f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877624071 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.3877624071
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.223328522
Short name T105
Test name
Test status
Simulation time 6675419807 ps
CPU time 6.06 seconds
Started Mar 19 12:26:24 PM PDT 24
Finished Mar 19 12:26:30 PM PDT 24
Peak memory 182836 kb
Host smart-5c9a9288-710c-40c9-b730-9669020336e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223328522 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.223328522
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.1446045118
Short name T160
Test name
Test status
Simulation time 502653687 ps
CPU time 1.24 seconds
Started Mar 19 12:26:46 PM PDT 24
Finished Mar 19 12:26:53 PM PDT 24
Peak memory 181608 kb
Host smart-19478371-f848-4ef3-b298-bf22fe514297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446045118 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.1446045118
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.2959373322
Short name T141
Test name
Test status
Simulation time 48708213916 ps
CPU time 24.69 seconds
Started Mar 19 12:26:45 PM PDT 24
Finished Mar 19 12:27:10 PM PDT 24
Peak memory 183004 kb
Host smart-1c0690c7-583a-4689-927b-c0832ef2f11a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959373322 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_
all.2959373322
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_jump.641098691
Short name T31
Test name
Test status
Simulation time 385766087 ps
CPU time 1.15 seconds
Started Mar 19 12:26:35 PM PDT 24
Finished Mar 19 12:26:36 PM PDT 24
Peak memory 182116 kb
Host smart-e976c286-07dc-4d7f-b4f1-1cbb3f5610d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641098691 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.641098691
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.2242674448
Short name T104
Test name
Test status
Simulation time 4640489237 ps
CPU time 6.61 seconds
Started Mar 19 12:26:18 PM PDT 24
Finished Mar 19 12:26:24 PM PDT 24
Peak memory 182920 kb
Host smart-79521d9a-54d7-4443-80d7-4c6bb6ac6f10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242674448 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.2242674448
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.3665462035
Short name T19
Test name
Test status
Simulation time 8481493248 ps
CPU time 12.1 seconds
Started Mar 19 12:26:40 PM PDT 24
Finished Mar 19 12:26:53 PM PDT 24
Peak memory 214688 kb
Host smart-7092dbfc-b1fa-456e-95d1-02e9fcabcea4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665462035 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.3665462035
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.3764600587
Short name T195
Test name
Test status
Simulation time 504597974 ps
CPU time 0.74 seconds
Started Mar 19 12:26:18 PM PDT 24
Finished Mar 19 12:26:19 PM PDT 24
Peak memory 182824 kb
Host smart-57c98e79-3270-4beb-b555-9361453e1471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764600587 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.3764600587
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.2115226269
Short name T163
Test name
Test status
Simulation time 36925869836 ps
CPU time 48.79 seconds
Started Mar 19 12:26:30 PM PDT 24
Finished Mar 19 12:27:20 PM PDT 24
Peak memory 194496 kb
Host smart-3fb80d9c-b8f3-4b9f-96dd-f3932ec00cb5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115226269 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_a
ll.2115226269
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.251799797
Short name T222
Test name
Test status
Simulation time 50583007761 ps
CPU time 398.81 seconds
Started Mar 19 12:26:38 PM PDT 24
Finished Mar 19 12:33:18 PM PDT 24
Peak memory 197932 kb
Host smart-c29ce1a2-e17c-486c-ba47-e1ae69ef65bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251799797 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.251799797
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.aon_timer_jump.675669041
Short name T147
Test name
Test status
Simulation time 533460989 ps
CPU time 1.32 seconds
Started Mar 19 12:26:19 PM PDT 24
Finished Mar 19 12:26:20 PM PDT 24
Peak memory 182976 kb
Host smart-c7b857ee-ae07-4bfb-a36c-4256324b4467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675669041 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.675669041
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.1109966116
Short name T181
Test name
Test status
Simulation time 21937965847 ps
CPU time 3.33 seconds
Started Mar 19 12:26:48 PM PDT 24
Finished Mar 19 12:26:52 PM PDT 24
Peak memory 182916 kb
Host smart-a34e2258-716a-4d0b-a9dd-c0bc38879f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109966116 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.1109966116
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.3238422146
Short name T5
Test name
Test status
Simulation time 458722729 ps
CPU time 0.87 seconds
Started Mar 19 12:26:36 PM PDT 24
Finished Mar 19 12:26:38 PM PDT 24
Peak memory 182632 kb
Host smart-c66d8b44-ea68-445d-9a8f-dfe8cd329807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238422146 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.3238422146
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.377668715
Short name T102
Test name
Test status
Simulation time 104236165002 ps
CPU time 171.84 seconds
Started Mar 19 12:26:46 PM PDT 24
Finished Mar 19 12:29:38 PM PDT 24
Peak memory 192864 kb
Host smart-be96e627-0b5e-4584-8a9b-a98d84518fa6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377668715 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_a
ll.377668715
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.3905288450
Short name T177
Test name
Test status
Simulation time 18429139625 ps
CPU time 95.29 seconds
Started Mar 19 12:26:45 PM PDT 24
Finished Mar 19 12:28:20 PM PDT 24
Peak memory 197628 kb
Host smart-524353f0-f105-4002-9a72-f5ad46099f13
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905288450 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.3905288450
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_jump.906749629
Short name T260
Test name
Test status
Simulation time 351414693 ps
CPU time 0.7 seconds
Started Mar 19 12:26:47 PM PDT 24
Finished Mar 19 12:26:48 PM PDT 24
Peak memory 182864 kb
Host smart-5ed69cb7-82f7-4fa3-9c61-daea4ba27f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906749629 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.906749629
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.911159657
Short name T169
Test name
Test status
Simulation time 37393190781 ps
CPU time 51.06 seconds
Started Mar 19 12:26:24 PM PDT 24
Finished Mar 19 12:27:15 PM PDT 24
Peak memory 182896 kb
Host smart-8d12c4fc-c9cd-415c-9e81-fd8003c3d10e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911159657 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.911159657
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.3211311331
Short name T150
Test name
Test status
Simulation time 545281130 ps
CPU time 0.9 seconds
Started Mar 19 12:26:45 PM PDT 24
Finished Mar 19 12:26:46 PM PDT 24
Peak memory 182856 kb
Host smart-ad4bf580-5ed6-4843-9565-87aae82e2cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211311331 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.3211311331
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.3421827775
Short name T107
Test name
Test status
Simulation time 106076707000 ps
CPU time 167.99 seconds
Started Mar 19 12:26:33 PM PDT 24
Finished Mar 19 12:29:22 PM PDT 24
Peak memory 193812 kb
Host smart-04b4f592-10a3-49ae-8833-d8e4d2542376
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421827775 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_
all.3421827775
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.1383016104
Short name T100
Test name
Test status
Simulation time 27614537628 ps
CPU time 87.57 seconds
Started Mar 19 12:26:26 PM PDT 24
Finished Mar 19 12:27:53 PM PDT 24
Peak memory 198332 kb
Host smart-f0363c04-2423-4a3a-8575-48147669e042
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383016104 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.1383016104
Directory /workspace/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.aon_timer_jump.1739194463
Short name T52
Test name
Test status
Simulation time 508258757 ps
CPU time 0.71 seconds
Started Mar 19 12:26:48 PM PDT 24
Finished Mar 19 12:26:50 PM PDT 24
Peak memory 182868 kb
Host smart-8cfd47b9-c04d-4542-92a8-d28746f4e763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739194463 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.1739194463
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.1932605727
Short name T280
Test name
Test status
Simulation time 1569406165 ps
CPU time 2.2 seconds
Started Mar 19 12:26:34 PM PDT 24
Finished Mar 19 12:26:37 PM PDT 24
Peak memory 182780 kb
Host smart-cef87fad-f2d1-4b56-91ee-240565141f73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932605727 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.1932605727
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.4093838893
Short name T125
Test name
Test status
Simulation time 581442721 ps
CPU time 0.73 seconds
Started Mar 19 12:26:35 PM PDT 24
Finished Mar 19 12:26:36 PM PDT 24
Peak memory 182840 kb
Host smart-189fc58f-26c1-4a4c-afa5-7a81b1cc7ec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093838893 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.4093838893
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.954819187
Short name T263
Test name
Test status
Simulation time 355586978520 ps
CPU time 553.26 seconds
Started Mar 19 12:26:30 PM PDT 24
Finished Mar 19 12:35:45 PM PDT 24
Peak memory 193448 kb
Host smart-a5b1e073-de35-4251-b6d8-e0e34e67210d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954819187 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_a
ll.954819187
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.3127495818
Short name T25
Test name
Test status
Simulation time 8799645419 ps
CPU time 66.82 seconds
Started Mar 19 12:26:45 PM PDT 24
Finished Mar 19 12:27:52 PM PDT 24
Peak memory 197740 kb
Host smart-fc83ca9e-3b6b-4a11-ba5f-5687cbf4a53f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127495818 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.3127495818
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.aon_timer_jump.3573298261
Short name T14
Test name
Test status
Simulation time 436883178 ps
CPU time 1.21 seconds
Started Mar 19 12:26:35 PM PDT 24
Finished Mar 19 12:26:36 PM PDT 24
Peak memory 182832 kb
Host smart-dc10fa4f-1a4e-4736-b628-9aab70da4bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573298261 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.3573298261
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.318697479
Short name T137
Test name
Test status
Simulation time 33612384670 ps
CPU time 27.66 seconds
Started Mar 19 12:26:34 PM PDT 24
Finished Mar 19 12:27:02 PM PDT 24
Peak memory 182920 kb
Host smart-9eb1b5d8-2503-4471-b306-3fbab78f49e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318697479 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.318697479
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.478692155
Short name T7
Test name
Test status
Simulation time 380134296 ps
CPU time 1.16 seconds
Started Mar 19 12:26:47 PM PDT 24
Finished Mar 19 12:26:49 PM PDT 24
Peak memory 182884 kb
Host smart-ca662d17-1f63-4aa3-81eb-ed71ae84211d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478692155 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.478692155
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.454028603
Short name T144
Test name
Test status
Simulation time 147044344825 ps
CPU time 53.45 seconds
Started Mar 19 12:26:30 PM PDT 24
Finished Mar 19 12:27:25 PM PDT 24
Peak memory 182208 kb
Host smart-8bdfc6ed-8216-4455-9026-eb7f2a13349e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454028603 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_a
ll.454028603
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.1825813147
Short name T41
Test name
Test status
Simulation time 123999038406 ps
CPU time 241.5 seconds
Started Mar 19 12:26:45 PM PDT 24
Finished Mar 19 12:30:47 PM PDT 24
Peak memory 197740 kb
Host smart-33d935c0-f739-4808-b58c-d82ad59d98ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825813147 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.1825813147
Directory /workspace/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.aon_timer_jump.3557379159
Short name T8
Test name
Test status
Simulation time 442555394 ps
CPU time 0.89 seconds
Started Mar 19 12:26:48 PM PDT 24
Finished Mar 19 12:26:50 PM PDT 24
Peak memory 182848 kb
Host smart-c5c348fc-112c-41f1-8992-bbe3df23a2c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557379159 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.3557379159
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.2393600267
Short name T194
Test name
Test status
Simulation time 4385568261 ps
CPU time 2.3 seconds
Started Mar 19 12:26:48 PM PDT 24
Finished Mar 19 12:26:50 PM PDT 24
Peak memory 182172 kb
Host smart-b6993a5f-d2e1-49f2-9bde-ab5928833d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393600267 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.2393600267
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.1216518006
Short name T168
Test name
Test status
Simulation time 666698826 ps
CPU time 0.62 seconds
Started Mar 19 12:26:34 PM PDT 24
Finished Mar 19 12:26:35 PM PDT 24
Peak memory 182744 kb
Host smart-91d0d031-06bb-49b2-942d-6b8d9e07c070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216518006 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.1216518006
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.671495282
Short name T266
Test name
Test status
Simulation time 123135202067 ps
CPU time 22.83 seconds
Started Mar 19 12:26:34 PM PDT 24
Finished Mar 19 12:26:57 PM PDT 24
Peak memory 192476 kb
Host smart-2dbcf728-0be6-4e66-b975-2c34b88f2030
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671495282 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_a
ll.671495282
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.3613134919
Short name T268
Test name
Test status
Simulation time 136165965861 ps
CPU time 158.2 seconds
Started Mar 19 12:26:45 PM PDT 24
Finished Mar 19 12:29:24 PM PDT 24
Peak memory 197948 kb
Host smart-3079278a-ccbd-41d8-8d54-0ba4541c090b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613134919 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand_reset.3613134919
Directory /workspace/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.aon_timer_jump.1141720209
Short name T271
Test name
Test status
Simulation time 587975549 ps
CPU time 0.82 seconds
Started Mar 19 12:26:29 PM PDT 24
Finished Mar 19 12:26:30 PM PDT 24
Peak memory 182728 kb
Host smart-0a0de2e4-5602-450a-a42f-b92ae24a44fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141720209 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.1141720209
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.3535292042
Short name T130
Test name
Test status
Simulation time 994134031 ps
CPU time 1.4 seconds
Started Mar 19 12:26:46 PM PDT 24
Finished Mar 19 12:26:48 PM PDT 24
Peak memory 182852 kb
Host smart-8d287fbd-4d33-436d-a34f-15c61ac1440d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535292042 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.3535292042
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.607382494
Short name T236
Test name
Test status
Simulation time 477807339 ps
CPU time 0.72 seconds
Started Mar 19 12:26:49 PM PDT 24
Finished Mar 19 12:26:50 PM PDT 24
Peak memory 182896 kb
Host smart-094789f1-40f2-4d51-b1eb-f9a599add36d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607382494 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.607382494
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.1630021258
Short name T228
Test name
Test status
Simulation time 136597055442 ps
CPU time 223.24 seconds
Started Mar 19 12:26:29 PM PDT 24
Finished Mar 19 12:30:13 PM PDT 24
Peak memory 193448 kb
Host smart-6ceb6063-e1b1-420f-af9e-10fe09184cf9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630021258 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_
all.1630021258
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.2964538382
Short name T196
Test name
Test status
Simulation time 355476404359 ps
CPU time 951.88 seconds
Started Mar 19 12:26:48 PM PDT 24
Finished Mar 19 12:42:40 PM PDT 24
Peak memory 204028 kb
Host smart-ea39d2a7-60d8-4d39-9a02-21d4fd859c0d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964538382 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.2964538382
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.aon_timer_jump.3951793482
Short name T1
Test name
Test status
Simulation time 360192960 ps
CPU time 0.79 seconds
Started Mar 19 12:26:26 PM PDT 24
Finished Mar 19 12:26:27 PM PDT 24
Peak memory 182840 kb
Host smart-71875baa-0b88-405f-b847-cc869e9e208f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951793482 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.3951793482
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.2174064829
Short name T136
Test name
Test status
Simulation time 57022252011 ps
CPU time 40.48 seconds
Started Mar 19 12:27:25 PM PDT 24
Finished Mar 19 12:28:06 PM PDT 24
Peak memory 182964 kb
Host smart-116e8328-54b3-44fb-abdd-c10d829a888a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174064829 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.2174064829
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.4127256985
Short name T267
Test name
Test status
Simulation time 515964926 ps
CPU time 1.39 seconds
Started Mar 19 12:26:26 PM PDT 24
Finished Mar 19 12:26:30 PM PDT 24
Peak memory 182108 kb
Host smart-5b1a02e3-e8c3-47b4-b347-ee1b9b5999ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127256985 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.4127256985
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.2529649168
Short name T159
Test name
Test status
Simulation time 165108037470 ps
CPU time 62.56 seconds
Started Mar 19 12:26:41 PM PDT 24
Finished Mar 19 12:27:43 PM PDT 24
Peak memory 190932 kb
Host smart-955b27c4-40b2-49a2-a223-9191ff18f66e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529649168 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_
all.2529649168
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/27.aon_timer_jump.3982525801
Short name T134
Test name
Test status
Simulation time 364042909 ps
CPU time 0.67 seconds
Started Mar 19 12:26:54 PM PDT 24
Finished Mar 19 12:26:55 PM PDT 24
Peak memory 182860 kb
Host smart-14ed0c7c-691e-449f-abee-b7626f9cda3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982525801 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.3982525801
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.1791268392
Short name T54
Test name
Test status
Simulation time 2424286690 ps
CPU time 4.22 seconds
Started Mar 19 12:26:45 PM PDT 24
Finished Mar 19 12:26:50 PM PDT 24
Peak memory 182696 kb
Host smart-8df7d44d-5e54-4ea4-ac85-7a23538de0bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791268392 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.1791268392
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.1250636281
Short name T182
Test name
Test status
Simulation time 459852326 ps
CPU time 0.86 seconds
Started Mar 19 12:26:41 PM PDT 24
Finished Mar 19 12:26:42 PM PDT 24
Peak memory 182820 kb
Host smart-3b7450c4-d966-4ce3-92a0-98ccd3efef23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250636281 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.1250636281
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.4200747046
Short name T128
Test name
Test status
Simulation time 56422209196 ps
CPU time 23.52 seconds
Started Mar 19 12:26:31 PM PDT 24
Finished Mar 19 12:26:55 PM PDT 24
Peak memory 182904 kb
Host smart-b4db2109-ca03-42c1-9fd5-b992a628cc25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200747046 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_
all.4200747046
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.2282062747
Short name T214
Test name
Test status
Simulation time 143842478424 ps
CPU time 410.97 seconds
Started Mar 19 12:26:43 PM PDT 24
Finished Mar 19 12:33:34 PM PDT 24
Peak memory 197816 kb
Host smart-600e4e4a-d4ac-45a5-a352-033c5fc57393
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282062747 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.2282062747
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_jump.307499214
Short name T38
Test name
Test status
Simulation time 493965931 ps
CPU time 1.19 seconds
Started Mar 19 12:26:33 PM PDT 24
Finished Mar 19 12:26:35 PM PDT 24
Peak memory 182724 kb
Host smart-bb163f7d-9ca1-4fc4-b331-b5af35938cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307499214 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.307499214
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.1841848172
Short name T192
Test name
Test status
Simulation time 4683682007 ps
CPU time 1.68 seconds
Started Mar 19 12:26:32 PM PDT 24
Finished Mar 19 12:26:35 PM PDT 24
Peak memory 182916 kb
Host smart-865016fa-f060-4493-86d1-cc59350d6729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841848172 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.1841848172
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.3767183490
Short name T229
Test name
Test status
Simulation time 612458948 ps
CPU time 0.81 seconds
Started Mar 19 12:26:50 PM PDT 24
Finished Mar 19 12:26:50 PM PDT 24
Peak memory 182848 kb
Host smart-e2872954-d39b-42fc-9b21-8613701b866d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767183490 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.3767183490
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.2330465433
Short name T22
Test name
Test status
Simulation time 38487520520 ps
CPU time 18.37 seconds
Started Mar 19 12:26:32 PM PDT 24
Finished Mar 19 12:26:50 PM PDT 24
Peak memory 192764 kb
Host smart-b3eaccad-ad90-478a-9379-46a08fe83f9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330465433 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_
all.2330465433
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.3504696645
Short name T50
Test name
Test status
Simulation time 40594929604 ps
CPU time 247.85 seconds
Started Mar 19 12:26:45 PM PDT 24
Finished Mar 19 12:30:53 PM PDT 24
Peak memory 197804 kb
Host smart-e90ae068-c8ee-46b8-bbcc-65864964599a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504696645 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.3504696645
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.aon_timer_jump.3517030824
Short name T96
Test name
Test status
Simulation time 550669332 ps
CPU time 1.44 seconds
Started Mar 19 12:26:34 PM PDT 24
Finished Mar 19 12:26:36 PM PDT 24
Peak memory 182848 kb
Host smart-d6dd8d47-c58b-4c63-8130-c821416e7f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517030824 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.3517030824
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.1986266047
Short name T53
Test name
Test status
Simulation time 37102198521 ps
CPU time 13.73 seconds
Started Mar 19 12:26:56 PM PDT 24
Finished Mar 19 12:27:10 PM PDT 24
Peak memory 182872 kb
Host smart-6590a057-3086-494a-8b72-8e03e9f9ab7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986266047 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.1986266047
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.4221443461
Short name T34
Test name
Test status
Simulation time 486643786 ps
CPU time 0.65 seconds
Started Mar 19 12:26:43 PM PDT 24
Finished Mar 19 12:26:44 PM PDT 24
Peak memory 182852 kb
Host smart-b6bbd334-1ebc-4158-bcac-2104de9dcb57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221443461 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.4221443461
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.2006401511
Short name T33
Test name
Test status
Simulation time 850276491980 ps
CPU time 423.73 seconds
Started Mar 19 12:26:36 PM PDT 24
Finished Mar 19 12:33:41 PM PDT 24
Peak memory 197028 kb
Host smart-63ea2246-8f8c-4dd8-bf45-5ca57b919b9d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006401511 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.2006401511
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.aon_timer_jump.2939399801
Short name T277
Test name
Test status
Simulation time 464692537 ps
CPU time 1.16 seconds
Started Mar 19 12:26:29 PM PDT 24
Finished Mar 19 12:26:30 PM PDT 24
Peak memory 182824 kb
Host smart-365d5c9f-41c9-4c06-8771-39a6fd3965a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939399801 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.2939399801
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.4074371634
Short name T57
Test name
Test status
Simulation time 15168274014 ps
CPU time 21.05 seconds
Started Mar 19 12:26:27 PM PDT 24
Finished Mar 19 12:26:49 PM PDT 24
Peak memory 182896 kb
Host smart-f0cd32de-9a1f-493f-8059-23e33b19a4b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074371634 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.4074371634
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.1558070484
Short name T20
Test name
Test status
Simulation time 3741844251 ps
CPU time 3.46 seconds
Started Mar 19 12:26:22 PM PDT 24
Finished Mar 19 12:26:26 PM PDT 24
Peak memory 214216 kb
Host smart-e599bbdc-7cf0-4b0e-99d9-690ee49c638c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558070484 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.1558070484
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.166758355
Short name T210
Test name
Test status
Simulation time 385010410 ps
CPU time 0.66 seconds
Started Mar 19 12:26:28 PM PDT 24
Finished Mar 19 12:26:29 PM PDT 24
Peak memory 182848 kb
Host smart-4e385982-17f4-47af-8238-eee80e95fc25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166758355 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.166758355
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.4104652535
Short name T241
Test name
Test status
Simulation time 30428261341 ps
CPU time 12.61 seconds
Started Mar 19 12:26:27 PM PDT 24
Finished Mar 19 12:26:41 PM PDT 24
Peak memory 192644 kb
Host smart-55cdf156-f617-4133-b331-d0c3451b7b02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104652535 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_a
ll.4104652535
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/30.aon_timer_jump.3583307457
Short name T209
Test name
Test status
Simulation time 415587770 ps
CPU time 0.66 seconds
Started Mar 19 12:26:44 PM PDT 24
Finished Mar 19 12:26:45 PM PDT 24
Peak memory 182932 kb
Host smart-daabcba1-2abf-40f8-bd2e-7aa7ee15adca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583307457 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.3583307457
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.3743590666
Short name T16
Test name
Test status
Simulation time 36378452549 ps
CPU time 25.17 seconds
Started Mar 19 12:26:33 PM PDT 24
Finished Mar 19 12:26:59 PM PDT 24
Peak memory 182896 kb
Host smart-f757f460-7942-44a5-80a9-3a6bfad842f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743590666 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.3743590666
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.4172486379
Short name T148
Test name
Test status
Simulation time 581345169 ps
CPU time 0.73 seconds
Started Mar 19 12:26:29 PM PDT 24
Finished Mar 19 12:26:35 PM PDT 24
Peak memory 182812 kb
Host smart-51bc6e7c-04a8-42dc-86dd-da0fb69bafbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172486379 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.4172486379
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.4038313203
Short name T215
Test name
Test status
Simulation time 36081200165 ps
CPU time 412.06 seconds
Started Mar 19 12:26:50 PM PDT 24
Finished Mar 19 12:33:42 PM PDT 24
Peak memory 197796 kb
Host smart-a0877bb5-91b6-437a-aaea-ba27e21d48be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038313203 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.4038313203
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.aon_timer_jump.826218084
Short name T129
Test name
Test status
Simulation time 415244208 ps
CPU time 0.69 seconds
Started Mar 19 12:26:47 PM PDT 24
Finished Mar 19 12:26:48 PM PDT 24
Peak memory 182868 kb
Host smart-0bddaedc-f873-49c2-93a9-991918861fe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826218084 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.826218084
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.3445616566
Short name T220
Test name
Test status
Simulation time 51415568777 ps
CPU time 4.93 seconds
Started Mar 19 12:26:39 PM PDT 24
Finished Mar 19 12:26:44 PM PDT 24
Peak memory 182916 kb
Host smart-b87b3c05-3bf2-44d2-a02b-5e1ecba614db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445616566 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.3445616566
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.1601425114
Short name T161
Test name
Test status
Simulation time 391153269 ps
CPU time 1.03 seconds
Started Mar 19 12:26:46 PM PDT 24
Finished Mar 19 12:26:47 PM PDT 24
Peak memory 181684 kb
Host smart-3ec2c6bf-d418-4603-91f5-91cc727f371f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601425114 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.1601425114
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.1789979231
Short name T262
Test name
Test status
Simulation time 167904781176 ps
CPU time 134.78 seconds
Started Mar 19 12:26:42 PM PDT 24
Finished Mar 19 12:29:02 PM PDT 24
Peak memory 192944 kb
Host smart-afb59f41-319c-4617-9fc4-3d45a2ba88c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789979231 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_
all.1789979231
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.2177521217
Short name T261
Test name
Test status
Simulation time 211688913721 ps
CPU time 92.81 seconds
Started Mar 19 12:26:34 PM PDT 24
Finished Mar 19 12:28:07 PM PDT 24
Peak memory 213884 kb
Host smart-de765b55-237b-4929-b14a-33d29544e66d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177521217 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.2177521217
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.aon_timer_jump.2012236218
Short name T244
Test name
Test status
Simulation time 427002741 ps
CPU time 1.22 seconds
Started Mar 19 12:26:34 PM PDT 24
Finished Mar 19 12:26:36 PM PDT 24
Peak memory 182844 kb
Host smart-3e4b6102-9adf-4c9d-9c57-30af7d989201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012236218 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.2012236218
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.3889310239
Short name T164
Test name
Test status
Simulation time 38213442827 ps
CPU time 7.46 seconds
Started Mar 19 12:26:47 PM PDT 24
Finished Mar 19 12:26:55 PM PDT 24
Peak memory 183044 kb
Host smart-ab55d51c-9de9-46d0-923d-26610719c199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889310239 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.3889310239
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.3515621610
Short name T211
Test name
Test status
Simulation time 425515303 ps
CPU time 1.2 seconds
Started Mar 19 12:26:52 PM PDT 24
Finished Mar 19 12:26:54 PM PDT 24
Peak memory 182848 kb
Host smart-a62607cb-6c1b-4395-8e5b-6ea148d9f5de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515621610 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.3515621610
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_jump.2350963045
Short name T206
Test name
Test status
Simulation time 370766228 ps
CPU time 0.81 seconds
Started Mar 19 12:26:50 PM PDT 24
Finished Mar 19 12:26:51 PM PDT 24
Peak memory 182860 kb
Host smart-d869c8a3-4dfc-47ae-9fde-9a2851052dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350963045 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.2350963045
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.1949019113
Short name T240
Test name
Test status
Simulation time 13970976159 ps
CPU time 4.26 seconds
Started Mar 19 12:26:33 PM PDT 24
Finished Mar 19 12:26:38 PM PDT 24
Peak memory 182912 kb
Host smart-e8ef283a-8046-43f7-afcc-66e32ee26a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949019113 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.1949019113
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.2373478630
Short name T28
Test name
Test status
Simulation time 454697244 ps
CPU time 1.26 seconds
Started Mar 19 12:26:50 PM PDT 24
Finished Mar 19 12:26:52 PM PDT 24
Peak memory 182832 kb
Host smart-274019d1-9d18-4531-8432-a510e06b70ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373478630 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.2373478630
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.634656540
Short name T198
Test name
Test status
Simulation time 328878967067 ps
CPU time 510.72 seconds
Started Mar 19 12:26:48 PM PDT 24
Finished Mar 19 12:35:19 PM PDT 24
Peak memory 191128 kb
Host smart-46248ba8-d64f-41e9-b8fd-90080cb64c6a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634656540 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_a
ll.634656540
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_jump.2972252997
Short name T201
Test name
Test status
Simulation time 531247892 ps
CPU time 0.73 seconds
Started Mar 19 12:26:46 PM PDT 24
Finished Mar 19 12:26:47 PM PDT 24
Peak memory 182856 kb
Host smart-abebcb28-4c44-40ed-bc4f-8a0b86c9e01b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972252997 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.2972252997
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.4224140033
Short name T256
Test name
Test status
Simulation time 26906517738 ps
CPU time 40.76 seconds
Started Mar 19 12:26:49 PM PDT 24
Finished Mar 19 12:27:30 PM PDT 24
Peak memory 182916 kb
Host smart-7be1a6b1-42f5-4591-a56f-82ae1f1d79ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224140033 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.4224140033
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.1764767375
Short name T225
Test name
Test status
Simulation time 402412019 ps
CPU time 0.85 seconds
Started Mar 19 12:26:48 PM PDT 24
Finished Mar 19 12:26:49 PM PDT 24
Peak memory 182860 kb
Host smart-68b5ccb3-2c90-41c4-9c49-ed73a31857b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764767375 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.1764767375
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.2879487763
Short name T138
Test name
Test status
Simulation time 208133982077 ps
CPU time 64.65 seconds
Started Mar 19 12:26:46 PM PDT 24
Finished Mar 19 12:27:51 PM PDT 24
Peak memory 194852 kb
Host smart-d4d7b935-d63b-44d4-8eb5-d5d896a5f958
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879487763 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_
all.2879487763
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.2030243954
Short name T98
Test name
Test status
Simulation time 246863009938 ps
CPU time 858.94 seconds
Started Mar 19 12:26:43 PM PDT 24
Finished Mar 19 12:41:02 PM PDT 24
Peak memory 201836 kb
Host smart-f6e6948e-7da7-461a-b65a-13bbb3bb050c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030243954 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.2030243954
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.aon_timer_jump.467822345
Short name T224
Test name
Test status
Simulation time 578780815 ps
CPU time 0.71 seconds
Started Mar 19 12:26:50 PM PDT 24
Finished Mar 19 12:26:52 PM PDT 24
Peak memory 182892 kb
Host smart-62802a0c-5a8f-4f48-9359-1bec35616b54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467822345 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.467822345
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.2703565850
Short name T230
Test name
Test status
Simulation time 61579351827 ps
CPU time 96.87 seconds
Started Mar 19 12:26:40 PM PDT 24
Finished Mar 19 12:28:17 PM PDT 24
Peak memory 182972 kb
Host smart-8a537b95-4849-409c-ab84-252589bd3e8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703565850 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.2703565850
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.1523077531
Short name T190
Test name
Test status
Simulation time 496887947 ps
CPU time 0.7 seconds
Started Mar 19 12:26:32 PM PDT 24
Finished Mar 19 12:26:33 PM PDT 24
Peak memory 182620 kb
Host smart-919d23e4-6e51-49ec-b2a8-a253bbb4c28c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523077531 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.1523077531
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.2719407754
Short name T219
Test name
Test status
Simulation time 83531578370 ps
CPU time 129.14 seconds
Started Mar 19 12:26:53 PM PDT 24
Finished Mar 19 12:29:02 PM PDT 24
Peak memory 193816 kb
Host smart-47134ed3-d91f-4605-a3e1-3b3c9e90a5a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719407754 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_
all.2719407754
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.4034345007
Short name T212
Test name
Test status
Simulation time 35626212494 ps
CPU time 100.35 seconds
Started Mar 19 12:26:50 PM PDT 24
Finished Mar 19 12:28:31 PM PDT 24
Peak memory 197716 kb
Host smart-36b5553e-5c61-45e2-a120-98ee133c7f48
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034345007 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.4034345007
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.aon_timer_jump.2067020569
Short name T51
Test name
Test status
Simulation time 469175402 ps
CPU time 1.04 seconds
Started Mar 19 12:26:41 PM PDT 24
Finished Mar 19 12:26:42 PM PDT 24
Peak memory 182944 kb
Host smart-32c3f721-4119-4d32-87ba-7a3c05c23fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067020569 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.2067020569
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.1378289749
Short name T278
Test name
Test status
Simulation time 45805691853 ps
CPU time 72.93 seconds
Started Mar 19 12:26:39 PM PDT 24
Finished Mar 19 12:27:52 PM PDT 24
Peak memory 182788 kb
Host smart-55ba1e25-2c26-40d6-a73c-0e1ebea86f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378289749 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.1378289749
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.3520378566
Short name T185
Test name
Test status
Simulation time 344767329 ps
CPU time 0.99 seconds
Started Mar 19 12:26:44 PM PDT 24
Finished Mar 19 12:26:51 PM PDT 24
Peak memory 182656 kb
Host smart-868ba8a1-2d48-4ad4-a643-39519211950a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520378566 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.3520378566
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.1983664005
Short name T77
Test name
Test status
Simulation time 492765383880 ps
CPU time 784.69 seconds
Started Mar 19 12:26:25 PM PDT 24
Finished Mar 19 12:39:30 PM PDT 24
Peak memory 182200 kb
Host smart-35be1ded-292d-478f-a137-18799b48b0e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983664005 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_
all.1983664005
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.2494690450
Short name T156
Test name
Test status
Simulation time 534761080325 ps
CPU time 310.56 seconds
Started Mar 19 12:26:37 PM PDT 24
Finished Mar 19 12:31:48 PM PDT 24
Peak memory 205368 kb
Host smart-21d6c41b-1d79-4e99-ad04-edb0295aa2cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494690450 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.2494690450
Directory /workspace/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.aon_timer_jump.1558248638
Short name T245
Test name
Test status
Simulation time 361542966 ps
CPU time 1.05 seconds
Started Mar 19 12:26:47 PM PDT 24
Finished Mar 19 12:26:49 PM PDT 24
Peak memory 182864 kb
Host smart-4028eb69-ba92-4151-8ca6-64763166ddf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558248638 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.1558248638
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.433440638
Short name T275
Test name
Test status
Simulation time 47165786022 ps
CPU time 65.19 seconds
Started Mar 19 12:26:27 PM PDT 24
Finished Mar 19 12:27:33 PM PDT 24
Peak memory 182908 kb
Host smart-21f614c3-2d4c-4bea-a67e-79d2438965b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433440638 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.433440638
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.1802116782
Short name T265
Test name
Test status
Simulation time 481805712 ps
CPU time 0.73 seconds
Started Mar 19 12:26:36 PM PDT 24
Finished Mar 19 12:26:38 PM PDT 24
Peak memory 182852 kb
Host smart-03cdaff3-6480-4c22-809d-b88416775840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802116782 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.1802116782
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.1453185578
Short name T274
Test name
Test status
Simulation time 233270131289 ps
CPU time 53.4 seconds
Started Mar 19 12:26:29 PM PDT 24
Finished Mar 19 12:27:22 PM PDT 24
Peak memory 194532 kb
Host smart-587876d7-1ba6-4bb6-923a-e96f97164fef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453185578 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_
all.1453185578
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_jump.1260875056
Short name T4
Test name
Test status
Simulation time 465866495 ps
CPU time 0.59 seconds
Started Mar 19 12:26:56 PM PDT 24
Finished Mar 19 12:26:57 PM PDT 24
Peak memory 182872 kb
Host smart-0d3266df-418b-473c-95fc-41d48704e2e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260875056 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.1260875056
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.60032104
Short name T281
Test name
Test status
Simulation time 51555684667 ps
CPU time 38.55 seconds
Started Mar 19 12:27:01 PM PDT 24
Finished Mar 19 12:27:42 PM PDT 24
Peak memory 182920 kb
Host smart-e176319d-cb1f-4158-85c2-439b21b8421c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60032104 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.60032104
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.4205832849
Short name T227
Test name
Test status
Simulation time 365727097 ps
CPU time 0.65 seconds
Started Mar 19 12:26:45 PM PDT 24
Finished Mar 19 12:26:46 PM PDT 24
Peak memory 182832 kb
Host smart-c42173a6-286b-4ace-afb2-ec7459d0c76d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205832849 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.4205832849
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.3454610698
Short name T110
Test name
Test status
Simulation time 108202090570 ps
CPU time 42.52 seconds
Started Mar 19 12:26:48 PM PDT 24
Finished Mar 19 12:27:30 PM PDT 24
Peak memory 182924 kb
Host smart-d734932a-d702-43ef-ad55-d5b34e8295c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454610698 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_
all.3454610698
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_jump.1227816206
Short name T205
Test name
Test status
Simulation time 430451351 ps
CPU time 0.99 seconds
Started Mar 19 12:26:45 PM PDT 24
Finished Mar 19 12:26:47 PM PDT 24
Peak memory 182840 kb
Host smart-04c74afc-e7af-4711-9f9a-2ea1d4917a84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227816206 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.1227816206
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.4168606494
Short name T270
Test name
Test status
Simulation time 11748993411 ps
CPU time 15.83 seconds
Started Mar 19 12:27:06 PM PDT 24
Finished Mar 19 12:27:22 PM PDT 24
Peak memory 182896 kb
Host smart-8e8619e3-dd24-441f-ba81-5dc86097a5d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168606494 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.4168606494
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.3231759583
Short name T180
Test name
Test status
Simulation time 446446075 ps
CPU time 0.59 seconds
Started Mar 19 12:26:50 PM PDT 24
Finished Mar 19 12:26:51 PM PDT 24
Peak memory 182868 kb
Host smart-766cd6fd-c5c6-41cc-939f-c79b1ff44973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231759583 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.3231759583
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.1249652491
Short name T232
Test name
Test status
Simulation time 133027809067 ps
CPU time 185.07 seconds
Started Mar 19 12:26:46 PM PDT 24
Finished Mar 19 12:29:51 PM PDT 24
Peak memory 193524 kb
Host smart-c7c1a74e-9811-4602-8217-26d1c10a3f0b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249652491 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_
all.1249652491
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_jump.3968172711
Short name T175
Test name
Test status
Simulation time 565929215 ps
CPU time 0.74 seconds
Started Mar 19 12:26:34 PM PDT 24
Finished Mar 19 12:26:35 PM PDT 24
Peak memory 182840 kb
Host smart-f4ff62fa-24c1-4ae5-ac8c-5e728810cd03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968172711 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.3968172711
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.1599234459
Short name T199
Test name
Test status
Simulation time 41075426713 ps
CPU time 61.12 seconds
Started Mar 19 12:26:35 PM PDT 24
Finished Mar 19 12:27:36 PM PDT 24
Peak memory 182920 kb
Host smart-39a10646-db3d-4713-aa0c-b1dddf3b6512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599234459 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.1599234459
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.2681785950
Short name T23
Test name
Test status
Simulation time 3889846859 ps
CPU time 6.21 seconds
Started Mar 19 12:26:34 PM PDT 24
Finished Mar 19 12:26:40 PM PDT 24
Peak memory 214072 kb
Host smart-0e569ec3-466d-4078-8af7-d2cf5dc95b7f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681785950 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.2681785950
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.3989949856
Short name T152
Test name
Test status
Simulation time 365382519 ps
CPU time 1.07 seconds
Started Mar 19 12:26:17 PM PDT 24
Finished Mar 19 12:26:18 PM PDT 24
Peak memory 182836 kb
Host smart-910e7dca-9c0a-463b-888b-0f6baa39ee61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989949856 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.3989949856
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.2646399595
Short name T108
Test name
Test status
Simulation time 98755309183 ps
CPU time 39.94 seconds
Started Mar 19 12:26:29 PM PDT 24
Finished Mar 19 12:27:09 PM PDT 24
Peak memory 193796 kb
Host smart-4bd46ae6-755f-417a-a133-307fe3f5968b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646399595 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_a
ll.2646399595
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_jump.4278677183
Short name T162
Test name
Test status
Simulation time 467276956 ps
CPU time 1.28 seconds
Started Mar 19 12:26:47 PM PDT 24
Finished Mar 19 12:26:49 PM PDT 24
Peak memory 182860 kb
Host smart-0f26fa57-396c-435c-9f34-84fdebb27b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278677183 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.4278677183
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.2289275139
Short name T173
Test name
Test status
Simulation time 5595571584 ps
CPU time 4.56 seconds
Started Mar 19 12:26:53 PM PDT 24
Finished Mar 19 12:26:58 PM PDT 24
Peak memory 182900 kb
Host smart-752046dd-9711-4c1c-ad69-6e76812fdc23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289275139 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.2289275139
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.650358773
Short name T187
Test name
Test status
Simulation time 347226720 ps
CPU time 0.7 seconds
Started Mar 19 12:26:49 PM PDT 24
Finished Mar 19 12:26:50 PM PDT 24
Peak memory 182832 kb
Host smart-68bb38b4-5ce7-4bd3-89f0-1e04caefc1ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650358773 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.650358773
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.4198286070
Short name T174
Test name
Test status
Simulation time 100342704609 ps
CPU time 43.27 seconds
Started Mar 19 12:26:49 PM PDT 24
Finished Mar 19 12:27:32 PM PDT 24
Peak memory 193056 kb
Host smart-661c69ac-9e55-4921-8b46-9ca57827423a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198286070 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_
all.4198286070
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.2137326250
Short name T17
Test name
Test status
Simulation time 10800373148 ps
CPU time 41.28 seconds
Started Mar 19 12:26:50 PM PDT 24
Finished Mar 19 12:27:32 PM PDT 24
Peak memory 197840 kb
Host smart-2c91300a-512a-464a-bc58-557f4577ba1f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137326250 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.2137326250
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.aon_timer_jump.2968058432
Short name T226
Test name
Test status
Simulation time 488678729 ps
CPU time 1.3 seconds
Started Mar 19 12:26:48 PM PDT 24
Finished Mar 19 12:26:50 PM PDT 24
Peak memory 182860 kb
Host smart-0655c941-d6f3-4448-8d97-8c56eefa019b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968058432 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.2968058432
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.2717361324
Short name T193
Test name
Test status
Simulation time 21974814603 ps
CPU time 34.62 seconds
Started Mar 19 12:26:33 PM PDT 24
Finished Mar 19 12:27:08 PM PDT 24
Peak memory 182232 kb
Host smart-ae045faf-44af-4197-a20d-59b8b0d44a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717361324 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.2717361324
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.1046724244
Short name T189
Test name
Test status
Simulation time 480815783 ps
CPU time 1.29 seconds
Started Mar 19 12:26:57 PM PDT 24
Finished Mar 19 12:27:00 PM PDT 24
Peak memory 182940 kb
Host smart-7d01c957-9198-4382-9cb4-6b2777d118d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046724244 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.1046724244
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.1121286808
Short name T27
Test name
Test status
Simulation time 83115796700 ps
CPU time 10.01 seconds
Started Mar 19 12:26:31 PM PDT 24
Finished Mar 19 12:26:42 PM PDT 24
Peak memory 182928 kb
Host smart-73dd8395-05b2-4234-860a-7a3444ae6cdb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121286808 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_
all.1121286808
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.3693670681
Short name T78
Test name
Test status
Simulation time 46103328162 ps
CPU time 488.86 seconds
Started Mar 19 12:26:42 PM PDT 24
Finished Mar 19 12:34:51 PM PDT 24
Peak memory 197860 kb
Host smart-87d7b225-8846-48e0-b793-e91abf8b41d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693670681 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.3693670681
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.aon_timer_jump.2602221845
Short name T203
Test name
Test status
Simulation time 457815601 ps
CPU time 0.82 seconds
Started Mar 19 12:26:37 PM PDT 24
Finished Mar 19 12:26:38 PM PDT 24
Peak memory 182852 kb
Host smart-43c5265f-7dc7-4965-bc74-2ce1f585c527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602221845 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.2602221845
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.288820004
Short name T257
Test name
Test status
Simulation time 39781011999 ps
CPU time 10.73 seconds
Started Mar 19 12:26:47 PM PDT 24
Finished Mar 19 12:26:58 PM PDT 24
Peak memory 182944 kb
Host smart-2fe46a70-4c5c-4b71-b641-e0ba0419ce30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288820004 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.288820004
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.951418275
Short name T242
Test name
Test status
Simulation time 459512354 ps
CPU time 0.87 seconds
Started Mar 19 12:26:49 PM PDT 24
Finished Mar 19 12:26:50 PM PDT 24
Peak memory 182892 kb
Host smart-fbf12a05-692d-4a27-85da-a9d46b89a6dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951418275 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.951418275
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.4268216442
Short name T109
Test name
Test status
Simulation time 53769555672 ps
CPU time 22.35 seconds
Started Mar 19 12:26:40 PM PDT 24
Finished Mar 19 12:27:02 PM PDT 24
Peak memory 193632 kb
Host smart-e2bd1a18-c562-4292-8a90-74acd74220c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268216442 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_
all.4268216442
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.863775417
Short name T75
Test name
Test status
Simulation time 35821841066 ps
CPU time 359 seconds
Started Mar 19 12:26:56 PM PDT 24
Finished Mar 19 12:32:55 PM PDT 24
Peak memory 197832 kb
Host smart-a47b489c-4bc0-463e-917a-1f1ec1f377e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863775417 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.863775417
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.aon_timer_jump.3186896055
Short name T216
Test name
Test status
Simulation time 512244665 ps
CPU time 0.67 seconds
Started Mar 19 12:26:44 PM PDT 24
Finished Mar 19 12:26:45 PM PDT 24
Peak memory 182644 kb
Host smart-3d801945-c7f7-42df-9d66-9e0661bfc902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186896055 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.3186896055
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.1432377796
Short name T176
Test name
Test status
Simulation time 4086264593 ps
CPU time 2.45 seconds
Started Mar 19 12:26:28 PM PDT 24
Finished Mar 19 12:26:31 PM PDT 24
Peak memory 182692 kb
Host smart-f40c9200-c64e-4e23-8cd9-6addfca4a4a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432377796 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.1432377796
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.1916969711
Short name T178
Test name
Test status
Simulation time 346926148 ps
CPU time 1.05 seconds
Started Mar 19 12:26:34 PM PDT 24
Finished Mar 19 12:26:36 PM PDT 24
Peak memory 182836 kb
Host smart-656fa8f5-0f9e-42fd-8a05-40f7f0d45ff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916969711 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.1916969711
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.3337633857
Short name T132
Test name
Test status
Simulation time 77752896226 ps
CPU time 114.09 seconds
Started Mar 19 12:26:50 PM PDT 24
Finished Mar 19 12:28:45 PM PDT 24
Peak memory 182920 kb
Host smart-7703ff0b-74c9-424b-9a89-c022dcd7fd24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337633857 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_
all.3337633857
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.1715857829
Short name T204
Test name
Test status
Simulation time 61362714313 ps
CPU time 171.89 seconds
Started Mar 19 12:26:29 PM PDT 24
Finished Mar 19 12:29:21 PM PDT 24
Peak memory 197808 kb
Host smart-758a6822-88d3-49f1-98ef-a83e5a924a7b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715857829 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.1715857829
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.aon_timer_jump.1441524404
Short name T197
Test name
Test status
Simulation time 428222851 ps
CPU time 0.92 seconds
Started Mar 19 12:26:41 PM PDT 24
Finished Mar 19 12:26:42 PM PDT 24
Peak memory 182644 kb
Host smart-0c17dac5-c3f1-4bd0-bc5b-8179c353e2b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441524404 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.1441524404
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.4137684675
Short name T142
Test name
Test status
Simulation time 40441845168 ps
CPU time 30.87 seconds
Started Mar 19 12:26:43 PM PDT 24
Finished Mar 19 12:27:14 PM PDT 24
Peak memory 182896 kb
Host smart-de9495ae-2b07-4ed6-9065-3d09f4c0a6f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137684675 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.4137684675
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.3788102686
Short name T120
Test name
Test status
Simulation time 535159943 ps
CPU time 0.63 seconds
Started Mar 19 12:26:59 PM PDT 24
Finished Mar 19 12:27:00 PM PDT 24
Peak memory 182844 kb
Host smart-9eeabe69-18f5-4564-8663-632107ce3813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788102686 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.3788102686
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.3613756701
Short name T29
Test name
Test status
Simulation time 491289153644 ps
CPU time 157.69 seconds
Started Mar 19 12:26:48 PM PDT 24
Finished Mar 19 12:29:26 PM PDT 24
Peak memory 183072 kb
Host smart-b7e5082e-3161-4fca-a1ef-21452f5fd30d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613756701 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_
all.3613756701
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.3253582093
Short name T208
Test name
Test status
Simulation time 200612781136 ps
CPU time 358.74 seconds
Started Mar 19 12:26:53 PM PDT 24
Finished Mar 19 12:32:52 PM PDT 24
Peak memory 197916 kb
Host smart-834fb4c5-417b-4f3c-8d3a-b3976045ed82
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253582093 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.3253582093
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.aon_timer_jump.2398374134
Short name T91
Test name
Test status
Simulation time 557764570 ps
CPU time 0.71 seconds
Started Mar 19 12:26:48 PM PDT 24
Finished Mar 19 12:26:49 PM PDT 24
Peak memory 182888 kb
Host smart-f1b69163-e532-457f-b325-637d6b15f546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398374134 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.2398374134
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.2773520277
Short name T143
Test name
Test status
Simulation time 25385245256 ps
CPU time 10.55 seconds
Started Mar 19 12:26:54 PM PDT 24
Finished Mar 19 12:27:05 PM PDT 24
Peak memory 182924 kb
Host smart-084dd9f4-25b7-476f-9883-377fecc07c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773520277 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.2773520277
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.1201081311
Short name T165
Test name
Test status
Simulation time 436929462 ps
CPU time 0.85 seconds
Started Mar 19 12:26:47 PM PDT 24
Finished Mar 19 12:26:49 PM PDT 24
Peak memory 182856 kb
Host smart-c70128ae-186c-4edb-8e95-76b1d9cb1fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201081311 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.1201081311
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.899849072
Short name T170
Test name
Test status
Simulation time 4451279204 ps
CPU time 3.24 seconds
Started Mar 19 12:27:02 PM PDT 24
Finished Mar 19 12:27:07 PM PDT 24
Peak memory 182964 kb
Host smart-161727d4-bd70-4085-b336-5263b51f39ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899849072 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_a
ll.899849072
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.261909950
Short name T55
Test name
Test status
Simulation time 47791328450 ps
CPU time 177.78 seconds
Started Mar 19 12:26:56 PM PDT 24
Finished Mar 19 12:29:54 PM PDT 24
Peak memory 197860 kb
Host smart-1d4f5fff-0862-4fc7-abaf-7e56e5b08bc4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261909950 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.261909950
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.aon_timer_jump.2325343308
Short name T121
Test name
Test status
Simulation time 556388006 ps
CPU time 1.37 seconds
Started Mar 19 12:26:31 PM PDT 24
Finished Mar 19 12:26:33 PM PDT 24
Peak memory 182852 kb
Host smart-973886ba-201d-4d45-81ed-e25a0a475c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325343308 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.2325343308
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.395999230
Short name T111
Test name
Test status
Simulation time 24603292582 ps
CPU time 8.04 seconds
Started Mar 19 12:27:13 PM PDT 24
Finished Mar 19 12:27:23 PM PDT 24
Peak memory 182924 kb
Host smart-dc174e7b-0c66-4f5a-b51a-6cd64ff26298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395999230 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.395999230
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.107799330
Short name T183
Test name
Test status
Simulation time 375206308 ps
CPU time 0.66 seconds
Started Mar 19 12:26:54 PM PDT 24
Finished Mar 19 12:26:55 PM PDT 24
Peak memory 182864 kb
Host smart-bc75c3e4-19fa-412e-8455-71cc686320e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107799330 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.107799330
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.3267845608
Short name T207
Test name
Test status
Simulation time 31906524614 ps
CPU time 11.91 seconds
Started Mar 19 12:26:51 PM PDT 24
Finished Mar 19 12:27:03 PM PDT 24
Peak memory 194436 kb
Host smart-9a07a6ca-448e-4423-a1f6-948954eeae66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267845608 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_
all.3267845608
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.1043359004
Short name T101
Test name
Test status
Simulation time 90783436387 ps
CPU time 333.12 seconds
Started Mar 19 12:26:46 PM PDT 24
Finished Mar 19 12:32:19 PM PDT 24
Peak memory 197812 kb
Host smart-ed1a4346-350a-405a-a0ad-416d38086751
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043359004 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.1043359004
Directory /workspace/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.aon_timer_jump.3759068998
Short name T247
Test name
Test status
Simulation time 416213691 ps
CPU time 1.09 seconds
Started Mar 19 12:26:40 PM PDT 24
Finished Mar 19 12:26:41 PM PDT 24
Peak memory 182856 kb
Host smart-6dfc4f03-c26a-4332-bff2-e0a9fa04d5dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759068998 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.3759068998
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.3300956486
Short name T276
Test name
Test status
Simulation time 23904420063 ps
CPU time 9.2 seconds
Started Mar 19 12:27:21 PM PDT 24
Finished Mar 19 12:27:32 PM PDT 24
Peak memory 182960 kb
Host smart-cf9fa922-592a-451d-acaf-3a83a28780a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300956486 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.3300956486
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.3529398073
Short name T171
Test name
Test status
Simulation time 441067162 ps
CPU time 0.69 seconds
Started Mar 19 12:26:50 PM PDT 24
Finished Mar 19 12:26:52 PM PDT 24
Peak memory 182892 kb
Host smart-bbd2dcf1-6a11-4997-affe-e2bcaf394799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529398073 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.3529398073
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.2583278664
Short name T153
Test name
Test status
Simulation time 164679941775 ps
CPU time 279.85 seconds
Started Mar 19 12:26:50 PM PDT 24
Finished Mar 19 12:31:30 PM PDT 24
Peak memory 194352 kb
Host smart-7e7830cc-2315-4d0a-83ae-c9b4a1dee06a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583278664 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_
all.2583278664
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.159082570
Short name T97
Test name
Test status
Simulation time 182452900509 ps
CPU time 809.62 seconds
Started Mar 19 12:26:50 PM PDT 24
Finished Mar 19 12:40:21 PM PDT 24
Peak memory 210468 kb
Host smart-650cb1e1-570b-435e-8be2-b07b93dd138d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159082570 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.159082570
Directory /workspace/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_jump.1606340950
Short name T119
Test name
Test status
Simulation time 596363748 ps
CPU time 0.67 seconds
Started Mar 19 12:26:53 PM PDT 24
Finished Mar 19 12:26:54 PM PDT 24
Peak memory 182904 kb
Host smart-ff667b9a-6c33-444e-abe3-0dbdffa2d4a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606340950 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.1606340950
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.531156978
Short name T135
Test name
Test status
Simulation time 28693764115 ps
CPU time 43.61 seconds
Started Mar 19 12:26:48 PM PDT 24
Finished Mar 19 12:27:33 PM PDT 24
Peak memory 182892 kb
Host smart-d02034b2-6647-4d55-8a73-d18e24919fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531156978 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.531156978
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.3748281399
Short name T259
Test name
Test status
Simulation time 506067588 ps
CPU time 1.22 seconds
Started Mar 19 12:27:22 PM PDT 24
Finished Mar 19 12:27:24 PM PDT 24
Peak memory 182872 kb
Host smart-c0368c57-a72a-4872-a3fa-af4ab387819e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748281399 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.3748281399
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.2902537039
Short name T237
Test name
Test status
Simulation time 61240814819 ps
CPU time 26.59 seconds
Started Mar 19 12:26:47 PM PDT 24
Finished Mar 19 12:27:19 PM PDT 24
Peak memory 192396 kb
Host smart-7d3283a7-bc4b-4d0d-84d7-d44a5d3cd809
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902537039 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_
all.2902537039
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.4054645536
Short name T231
Test name
Test status
Simulation time 248070088116 ps
CPU time 613.79 seconds
Started Mar 19 12:27:10 PM PDT 24
Finished Mar 19 12:37:26 PM PDT 24
Peak memory 199024 kb
Host smart-da6eec54-22d3-4ba5-8bb7-b1c0cf84a85f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054645536 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.4054645536
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.aon_timer_jump.104136292
Short name T248
Test name
Test status
Simulation time 701172580 ps
CPU time 0.63 seconds
Started Mar 19 12:26:49 PM PDT 24
Finished Mar 19 12:26:50 PM PDT 24
Peak memory 182844 kb
Host smart-613e68a1-8f13-47f8-ae07-22e520d29711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104136292 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.104136292
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.3263239117
Short name T112
Test name
Test status
Simulation time 39462803745 ps
CPU time 53.21 seconds
Started Mar 19 12:26:53 PM PDT 24
Finished Mar 19 12:27:46 PM PDT 24
Peak memory 182924 kb
Host smart-8ca7b2f2-6b4c-487d-8a96-7317b8af47ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263239117 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.3263239117
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.405658358
Short name T124
Test name
Test status
Simulation time 580320590 ps
CPU time 0.64 seconds
Started Mar 19 12:27:00 PM PDT 24
Finished Mar 19 12:27:01 PM PDT 24
Peak memory 182868 kb
Host smart-1cb63a57-3bc5-4445-812d-6b569dc2677b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405658358 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.405658358
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.1233498727
Short name T149
Test name
Test status
Simulation time 515286885221 ps
CPU time 168.53 seconds
Started Mar 19 12:27:17 PM PDT 24
Finished Mar 19 12:30:06 PM PDT 24
Peak memory 182944 kb
Host smart-9876a899-2030-47f5-9b55-484ffb38cb86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233498727 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_
all.1233498727
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.1125975381
Short name T158
Test name
Test status
Simulation time 327591248157 ps
CPU time 389.01 seconds
Started Mar 19 12:26:48 PM PDT 24
Finished Mar 19 12:33:18 PM PDT 24
Peak memory 206044 kb
Host smart-21699098-0f67-40c5-9151-95881352cae9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125975381 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.1125975381
Directory /workspace/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.aon_timer_jump.1261617862
Short name T184
Test name
Test status
Simulation time 502747864 ps
CPU time 1.42 seconds
Started Mar 19 12:26:32 PM PDT 24
Finished Mar 19 12:26:33 PM PDT 24
Peak memory 182840 kb
Host smart-07f395a7-a452-483d-8e28-bf13a4ca87fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261617862 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.1261617862
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.500409710
Short name T234
Test name
Test status
Simulation time 51291010665 ps
CPU time 18.73 seconds
Started Mar 19 12:26:27 PM PDT 24
Finished Mar 19 12:26:47 PM PDT 24
Peak memory 182708 kb
Host smart-a5bc4964-6c1a-4fa1-9b6a-d1cd88a0da91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500409710 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.500409710
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.1906163648
Short name T282
Test name
Test status
Simulation time 553590373 ps
CPU time 1.04 seconds
Started Mar 19 12:26:31 PM PDT 24
Finished Mar 19 12:26:32 PM PDT 24
Peak memory 182196 kb
Host smart-23c74381-4af1-4b51-8ca7-e7cbc533b458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906163648 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.1906163648
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.1698908582
Short name T272
Test name
Test status
Simulation time 40189014364 ps
CPU time 14.91 seconds
Started Mar 19 12:26:35 PM PDT 24
Finished Mar 19 12:26:50 PM PDT 24
Peak memory 183068 kb
Host smart-3b3636f5-ccdd-4237-98fd-828cc00db438
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698908582 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_a
ll.1698908582
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.413338481
Short name T188
Test name
Test status
Simulation time 74266305214 ps
CPU time 225.49 seconds
Started Mar 19 12:26:44 PM PDT 24
Finished Mar 19 12:30:30 PM PDT 24
Peak memory 197868 kb
Host smart-b4304f2a-6181-4427-ac81-1ab9c7e5b510
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413338481 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.413338481
Directory /workspace/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.aon_timer_jump.2206204351
Short name T264
Test name
Test status
Simulation time 429282790 ps
CPU time 1.25 seconds
Started Mar 19 12:26:27 PM PDT 24
Finished Mar 19 12:26:29 PM PDT 24
Peak memory 182832 kb
Host smart-573bac2b-57d2-4734-98cf-a89721a6ed41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206204351 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.2206204351
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.1776919124
Short name T243
Test name
Test status
Simulation time 60597853282 ps
CPU time 45.56 seconds
Started Mar 19 12:26:28 PM PDT 24
Finished Mar 19 12:27:14 PM PDT 24
Peak memory 182860 kb
Host smart-f25c9d68-bccb-49cd-b3e7-2d722a8c871b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776919124 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.1776919124
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.2906675987
Short name T273
Test name
Test status
Simulation time 467737104 ps
CPU time 1.29 seconds
Started Mar 19 12:26:21 PM PDT 24
Finished Mar 19 12:26:22 PM PDT 24
Peak memory 182828 kb
Host smart-516d852e-00c3-4730-855c-8da660438fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906675987 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.2906675987
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.4258714472
Short name T167
Test name
Test status
Simulation time 121406586491 ps
CPU time 195.84 seconds
Started Mar 19 12:26:46 PM PDT 24
Finished Mar 19 12:30:03 PM PDT 24
Peak memory 191128 kb
Host smart-177d538c-ef94-4af0-96e6-db71995f21b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258714472 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_a
ll.4258714472
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.1166494691
Short name T61
Test name
Test status
Simulation time 306674893997 ps
CPU time 178.92 seconds
Started Mar 19 12:26:50 PM PDT 24
Finished Mar 19 12:29:49 PM PDT 24
Peak memory 197888 kb
Host smart-8c5334b3-1e85-4904-8755-0c48c0f73ff3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166494691 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.1166494691
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.aon_timer_jump.218603025
Short name T221
Test name
Test status
Simulation time 523065177 ps
CPU time 0.88 seconds
Started Mar 19 12:26:56 PM PDT 24
Finished Mar 19 12:26:57 PM PDT 24
Peak memory 182804 kb
Host smart-5ea6cde1-2505-49a3-8c43-d0c463d16d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218603025 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.218603025
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.3867733957
Short name T95
Test name
Test status
Simulation time 22979629326 ps
CPU time 10.32 seconds
Started Mar 19 12:26:27 PM PDT 24
Finished Mar 19 12:26:38 PM PDT 24
Peak memory 182932 kb
Host smart-e52eef18-c85c-445d-afe4-928f299cacda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867733957 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.3867733957
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.1394002562
Short name T123
Test name
Test status
Simulation time 365015841 ps
CPU time 0.65 seconds
Started Mar 19 12:26:32 PM PDT 24
Finished Mar 19 12:26:34 PM PDT 24
Peak memory 182880 kb
Host smart-59b4fedf-eb85-4518-bbde-1ee7f0549a53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394002562 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.1394002562
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.753660535
Short name T179
Test name
Test status
Simulation time 140783287043 ps
CPU time 11.89 seconds
Started Mar 19 12:26:32 PM PDT 24
Finished Mar 19 12:26:46 PM PDT 24
Peak memory 193984 kb
Host smart-875ab97f-f27d-4255-b659-598747026b36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753660535 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_al
l.753660535
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.506624601
Short name T145
Test name
Test status
Simulation time 258601499627 ps
CPU time 663.03 seconds
Started Mar 19 12:26:44 PM PDT 24
Finished Mar 19 12:37:47 PM PDT 24
Peak memory 200136 kb
Host smart-6794f8ea-d91c-4fcf-a694-a129b41a0b36
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506624601 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.506624601
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.aon_timer_jump.2422785196
Short name T269
Test name
Test status
Simulation time 375843888 ps
CPU time 0.82 seconds
Started Mar 19 12:26:15 PM PDT 24
Finished Mar 19 12:26:15 PM PDT 24
Peak memory 182788 kb
Host smart-265f1057-0d20-4cdd-97f2-8b0c6f4ba7cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422785196 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.2422785196
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.2568857600
Short name T58
Test name
Test status
Simulation time 16820530697 ps
CPU time 12.55 seconds
Started Mar 19 12:26:22 PM PDT 24
Finished Mar 19 12:26:35 PM PDT 24
Peak memory 183044 kb
Host smart-d447256f-232a-4802-afcc-d00455df3565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568857600 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.2568857600
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.3427800671
Short name T122
Test name
Test status
Simulation time 413861797 ps
CPU time 0.88 seconds
Started Mar 19 12:26:45 PM PDT 24
Finished Mar 19 12:26:46 PM PDT 24
Peak memory 182852 kb
Host smart-e1e44e2f-d53b-41e3-a7cf-de7da4a25641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427800671 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.3427800671
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.581988312
Short name T26
Test name
Test status
Simulation time 108231728987 ps
CPU time 300.36 seconds
Started Mar 19 12:26:40 PM PDT 24
Finished Mar 19 12:31:41 PM PDT 24
Peak memory 197876 kb
Host smart-550c9cd3-712f-4429-8bed-e3a8b9022f2f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581988312 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.581988312
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.aon_timer_jump.2290335673
Short name T94
Test name
Test status
Simulation time 523507581 ps
CPU time 1 seconds
Started Mar 19 12:26:41 PM PDT 24
Finished Mar 19 12:26:43 PM PDT 24
Peak memory 182856 kb
Host smart-0c524de4-8c1b-40e1-bb6b-241a299d09d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290335673 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.2290335673
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.3629331540
Short name T59
Test name
Test status
Simulation time 7996732668 ps
CPU time 3.7 seconds
Started Mar 19 12:26:39 PM PDT 24
Finished Mar 19 12:26:43 PM PDT 24
Peak memory 182924 kb
Host smart-936cf2b7-e879-4878-943b-fa0b5740b89d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629331540 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.3629331540
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.3710067200
Short name T238
Test name
Test status
Simulation time 606177539 ps
CPU time 0.68 seconds
Started Mar 19 12:26:18 PM PDT 24
Finished Mar 19 12:26:19 PM PDT 24
Peak memory 182096 kb
Host smart-f0f2f567-90ed-459f-99ca-278014d203dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710067200 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.3710067200
Directory /workspace/9.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.3198695365
Short name T249
Test name
Test status
Simulation time 241568309465 ps
CPU time 372.19 seconds
Started Mar 19 12:26:32 PM PDT 24
Finished Mar 19 12:32:44 PM PDT 24
Peak memory 193516 kb
Host smart-54f09798-6a13-480a-9a19-52f5987119df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198695365 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_a
ll.3198695365
Directory /workspace/9.aon_timer_stress_all/latest
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