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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
92.98 99.25 93.67 100.00 98.40 99.51 67.06


Total test records in report: 419
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T28 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.2180986450 Mar 21 12:24:17 PM PDT 24 Mar 21 12:24:19 PM PDT 24 380743653 ps
T55 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.1139973358 Mar 21 12:24:04 PM PDT 24 Mar 21 12:24:05 PM PDT 24 387640745 ps
T29 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.1119526313 Mar 21 12:24:28 PM PDT 24 Mar 21 12:24:35 PM PDT 24 4618142552 ps
T68 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.1969374220 Mar 21 12:24:09 PM PDT 24 Mar 21 12:24:14 PM PDT 24 1871379084 ps
T56 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.2194146866 Mar 21 12:24:00 PM PDT 24 Mar 21 12:24:02 PM PDT 24 1122217350 ps
T57 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.1816807590 Mar 21 12:24:01 PM PDT 24 Mar 21 12:24:06 PM PDT 24 6511156966 ps
T278 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.3216259724 Mar 21 12:24:00 PM PDT 24 Mar 21 12:24:02 PM PDT 24 597633676 ps
T279 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.2405222233 Mar 21 12:24:22 PM PDT 24 Mar 21 12:24:25 PM PDT 24 301880473 ps
T280 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.2891663621 Mar 21 12:24:13 PM PDT 24 Mar 21 12:24:14 PM PDT 24 525989231 ps
T104 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.2644142430 Mar 21 12:24:05 PM PDT 24 Mar 21 12:24:10 PM PDT 24 7243701213 ps
T281 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.2119429216 Mar 21 12:24:27 PM PDT 24 Mar 21 12:24:29 PM PDT 24 477630146 ps
T282 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.1574820818 Mar 21 12:24:17 PM PDT 24 Mar 21 12:24:18 PM PDT 24 483620108 ps
T283 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.2888622531 Mar 21 12:24:19 PM PDT 24 Mar 21 12:24:19 PM PDT 24 448596948 ps
T284 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.518265628 Mar 21 12:24:33 PM PDT 24 Mar 21 12:24:34 PM PDT 24 479595990 ps
T285 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.3492746059 Mar 21 12:24:18 PM PDT 24 Mar 21 12:24:18 PM PDT 24 576073036 ps
T100 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.723767676 Mar 21 12:24:10 PM PDT 24 Mar 21 12:24:22 PM PDT 24 4163011322 ps
T286 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.2038927571 Mar 21 12:24:32 PM PDT 24 Mar 21 12:24:33 PM PDT 24 453733571 ps
T58 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.1476978326 Mar 21 12:24:00 PM PDT 24 Mar 21 12:24:03 PM PDT 24 504373304 ps
T287 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.59514590 Mar 21 12:24:17 PM PDT 24 Mar 21 12:24:30 PM PDT 24 9225062984 ps
T102 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.2463083087 Mar 21 12:24:03 PM PDT 24 Mar 21 12:24:10 PM PDT 24 7594042772 ps
T288 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.3217470305 Mar 21 12:24:20 PM PDT 24 Mar 21 12:24:21 PM PDT 24 405460664 ps
T101 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.4038157625 Mar 21 12:24:09 PM PDT 24 Mar 21 12:24:12 PM PDT 24 8989555008 ps
T289 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.3174576410 Mar 21 12:24:47 PM PDT 24 Mar 21 12:24:48 PM PDT 24 426011013 ps
T290 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.3321000336 Mar 21 12:24:27 PM PDT 24 Mar 21 12:24:27 PM PDT 24 390858850 ps
T291 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.2517098287 Mar 21 12:24:01 PM PDT 24 Mar 21 12:24:04 PM PDT 24 2677335097 ps
T292 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.1196006413 Mar 21 12:24:20 PM PDT 24 Mar 21 12:24:21 PM PDT 24 452997705 ps
T69 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.2851311035 Mar 21 12:24:10 PM PDT 24 Mar 21 12:24:13 PM PDT 24 1330760183 ps
T293 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.635627332 Mar 21 12:24:16 PM PDT 24 Mar 21 12:24:17 PM PDT 24 485534665 ps
T70 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.567391407 Mar 21 12:24:30 PM PDT 24 Mar 21 12:24:32 PM PDT 24 1480515598 ps
T59 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.665177716 Mar 21 12:24:02 PM PDT 24 Mar 21 12:24:04 PM PDT 24 475960303 ps
T294 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.660519212 Mar 21 12:24:05 PM PDT 24 Mar 21 12:24:08 PM PDT 24 4201240874 ps
T295 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.3284203755 Mar 21 12:24:37 PM PDT 24 Mar 21 12:24:38 PM PDT 24 323451882 ps
T296 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.2108096382 Mar 21 12:24:19 PM PDT 24 Mar 21 12:24:21 PM PDT 24 8423279367 ps
T60 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.1508260259 Mar 21 12:24:17 PM PDT 24 Mar 21 12:24:25 PM PDT 24 13947788527 ps
T297 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.856917940 Mar 21 12:24:15 PM PDT 24 Mar 21 12:24:16 PM PDT 24 579180823 ps
T298 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.276479597 Mar 21 12:24:17 PM PDT 24 Mar 21 12:24:20 PM PDT 24 896979816 ps
T71 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.3941954248 Mar 21 12:24:01 PM PDT 24 Mar 21 12:24:04 PM PDT 24 2500606891 ps
T299 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.4143585714 Mar 21 12:24:01 PM PDT 24 Mar 21 12:24:03 PM PDT 24 320257429 ps
T300 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.2018358943 Mar 21 12:24:33 PM PDT 24 Mar 21 12:24:34 PM PDT 24 396355803 ps
T301 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.301361015 Mar 21 12:24:01 PM PDT 24 Mar 21 12:24:03 PM PDT 24 412505074 ps
T302 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.2760294288 Mar 21 12:24:16 PM PDT 24 Mar 21 12:24:17 PM PDT 24 558564154 ps
T303 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.634096829 Mar 21 12:24:19 PM PDT 24 Mar 21 12:24:20 PM PDT 24 512972577 ps
T304 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.4152420237 Mar 21 12:24:15 PM PDT 24 Mar 21 12:24:17 PM PDT 24 903182895 ps
T305 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.108564808 Mar 21 12:24:34 PM PDT 24 Mar 21 12:24:35 PM PDT 24 318720915 ps
T306 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.702125998 Mar 21 12:24:17 PM PDT 24 Mar 21 12:24:18 PM PDT 24 491568128 ps
T103 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.113675497 Mar 21 12:24:21 PM PDT 24 Mar 21 12:24:29 PM PDT 24 8295523226 ps
T61 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.3483851944 Mar 21 12:24:17 PM PDT 24 Mar 21 12:24:20 PM PDT 24 458685376 ps
T72 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.1448628476 Mar 21 12:24:18 PM PDT 24 Mar 21 12:24:25 PM PDT 24 2416597168 ps
T307 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.4032348599 Mar 21 12:24:16 PM PDT 24 Mar 21 12:24:17 PM PDT 24 493609475 ps
T308 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.1596468127 Mar 21 12:24:28 PM PDT 24 Mar 21 12:24:29 PM PDT 24 546205851 ps
T309 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.2935533982 Mar 21 12:24:20 PM PDT 24 Mar 21 12:24:21 PM PDT 24 314128611 ps
T310 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.2893193469 Mar 21 12:24:03 PM PDT 24 Mar 21 12:24:05 PM PDT 24 279183867 ps
T311 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.260337398 Mar 21 12:24:32 PM PDT 24 Mar 21 12:24:32 PM PDT 24 398205065 ps
T312 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.3388282257 Mar 21 12:24:37 PM PDT 24 Mar 21 12:24:38 PM PDT 24 348529399 ps
T73 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.3495067977 Mar 21 12:24:20 PM PDT 24 Mar 21 12:24:21 PM PDT 24 474941034 ps
T313 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.3439407966 Mar 21 12:24:12 PM PDT 24 Mar 21 12:24:13 PM PDT 24 537335281 ps
T314 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.3383709819 Mar 21 12:24:17 PM PDT 24 Mar 21 12:24:19 PM PDT 24 309484856 ps
T62 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.1843754047 Mar 21 12:24:19 PM PDT 24 Mar 21 12:24:20 PM PDT 24 397813345 ps
T315 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.630702630 Mar 21 12:24:02 PM PDT 24 Mar 21 12:24:03 PM PDT 24 272707883 ps
T74 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.480528572 Mar 21 12:24:30 PM PDT 24 Mar 21 12:24:32 PM PDT 24 1610916944 ps
T316 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.3118854008 Mar 21 12:24:15 PM PDT 24 Mar 21 12:24:16 PM PDT 24 378341112 ps
T317 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.2439242126 Mar 21 12:24:33 PM PDT 24 Mar 21 12:24:34 PM PDT 24 268323556 ps
T318 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.3621245861 Mar 21 12:24:26 PM PDT 24 Mar 21 12:24:27 PM PDT 24 286950197 ps
T319 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.3603239476 Mar 21 12:24:11 PM PDT 24 Mar 21 12:24:14 PM PDT 24 1502035392 ps
T320 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.39206130 Mar 21 12:24:03 PM PDT 24 Mar 21 12:24:05 PM PDT 24 598816446 ps
T321 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.2904061682 Mar 21 12:24:11 PM PDT 24 Mar 21 12:24:16 PM PDT 24 8281279995 ps
T322 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.375651868 Mar 21 12:24:15 PM PDT 24 Mar 21 12:24:16 PM PDT 24 359096774 ps
T323 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.3860953656 Mar 21 12:24:21 PM PDT 24 Mar 21 12:24:22 PM PDT 24 337840806 ps
T324 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.2183486585 Mar 21 12:24:18 PM PDT 24 Mar 21 12:24:20 PM PDT 24 2187861787 ps
T325 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.90054243 Mar 21 12:24:09 PM PDT 24 Mar 21 12:24:10 PM PDT 24 765932245 ps
T326 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.1834612691 Mar 21 12:24:10 PM PDT 24 Mar 21 12:24:11 PM PDT 24 452947048 ps
T327 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.641010425 Mar 21 12:24:32 PM PDT 24 Mar 21 12:24:33 PM PDT 24 285021520 ps
T328 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.3155232333 Mar 21 12:24:38 PM PDT 24 Mar 21 12:24:39 PM PDT 24 275727119 ps
T329 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.1691986970 Mar 21 12:23:57 PM PDT 24 Mar 21 12:23:58 PM PDT 24 301052357 ps
T330 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.2306884233 Mar 21 12:24:43 PM PDT 24 Mar 21 12:24:45 PM PDT 24 1621930828 ps
T65 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.3482032131 Mar 21 12:24:03 PM PDT 24 Mar 21 12:24:04 PM PDT 24 434785839 ps
T331 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.2530676318 Mar 21 12:24:31 PM PDT 24 Mar 21 12:24:32 PM PDT 24 325387627 ps
T332 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.367714728 Mar 21 12:24:10 PM PDT 24 Mar 21 12:24:11 PM PDT 24 359927086 ps
T333 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.3624104257 Mar 21 12:24:35 PM PDT 24 Mar 21 12:24:36 PM PDT 24 553003414 ps
T334 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.1812592945 Mar 21 12:24:35 PM PDT 24 Mar 21 12:24:36 PM PDT 24 374440811 ps
T335 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.3425505150 Mar 21 12:24:24 PM PDT 24 Mar 21 12:24:25 PM PDT 24 292370163 ps
T64 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.3321336801 Mar 21 12:24:09 PM PDT 24 Mar 21 12:24:10 PM PDT 24 499054849 ps
T336 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.1098462015 Mar 21 12:24:10 PM PDT 24 Mar 21 12:24:11 PM PDT 24 351206734 ps
T337 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.2801534698 Mar 21 12:24:34 PM PDT 24 Mar 21 12:24:41 PM PDT 24 2420338962 ps
T63 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.2028574044 Mar 21 12:24:14 PM PDT 24 Mar 21 12:24:16 PM PDT 24 624067764 ps
T338 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.3788424671 Mar 21 12:24:19 PM PDT 24 Mar 21 12:24:25 PM PDT 24 332992378 ps
T339 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.1586927439 Mar 21 12:24:26 PM PDT 24 Mar 21 12:24:28 PM PDT 24 425297221 ps
T340 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.2097376279 Mar 21 12:24:01 PM PDT 24 Mar 21 12:24:03 PM PDT 24 310083606 ps
T341 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.2127064301 Mar 21 12:24:26 PM PDT 24 Mar 21 12:24:28 PM PDT 24 493108046 ps
T342 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.1039759262 Mar 21 12:24:00 PM PDT 24 Mar 21 12:24:03 PM PDT 24 506560292 ps
T343 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.3294404331 Mar 21 12:24:38 PM PDT 24 Mar 21 12:24:39 PM PDT 24 364185817 ps
T344 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.2096130317 Mar 21 12:24:10 PM PDT 24 Mar 21 12:24:13 PM PDT 24 2680141975 ps
T345 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.290584291 Mar 21 12:24:02 PM PDT 24 Mar 21 12:24:04 PM PDT 24 566487206 ps
T346 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.1833431187 Mar 21 12:24:12 PM PDT 24 Mar 21 12:24:14 PM PDT 24 522590743 ps
T347 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.7455462 Mar 21 12:23:56 PM PDT 24 Mar 21 12:23:57 PM PDT 24 441054928 ps
T348 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.3647406586 Mar 21 12:24:29 PM PDT 24 Mar 21 12:24:31 PM PDT 24 2863793437 ps
T349 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.3417293191 Mar 21 12:24:15 PM PDT 24 Mar 21 12:24:18 PM PDT 24 488137143 ps
T350 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.2086651448 Mar 21 12:24:19 PM PDT 24 Mar 21 12:24:22 PM PDT 24 1468442074 ps
T351 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.4066371704 Mar 21 12:23:54 PM PDT 24 Mar 21 12:23:55 PM PDT 24 565009797 ps
T352 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.3239641786 Mar 21 12:24:10 PM PDT 24 Mar 21 12:24:14 PM PDT 24 8823854836 ps
T353 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.4072377605 Mar 21 12:24:08 PM PDT 24 Mar 21 12:24:09 PM PDT 24 424862518 ps
T354 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.2503145295 Mar 21 12:24:16 PM PDT 24 Mar 21 12:24:19 PM PDT 24 4045182800 ps
T355 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.3429590467 Mar 21 12:24:03 PM PDT 24 Mar 21 12:24:05 PM PDT 24 506698326 ps
T356 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.2859947151 Mar 21 12:24:28 PM PDT 24 Mar 21 12:24:33 PM PDT 24 450486232 ps
T357 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.1052099278 Mar 21 12:24:21 PM PDT 24 Mar 21 12:24:22 PM PDT 24 443993765 ps
T358 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.1163886677 Mar 21 12:24:11 PM PDT 24 Mar 21 12:24:13 PM PDT 24 468361452 ps
T359 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.4012627021 Mar 21 12:24:13 PM PDT 24 Mar 21 12:24:14 PM PDT 24 430421032 ps
T360 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.4148130875 Mar 21 12:24:36 PM PDT 24 Mar 21 12:24:38 PM PDT 24 450362561 ps
T361 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.1442620411 Mar 21 12:24:38 PM PDT 24 Mar 21 12:24:38 PM PDT 24 363392370 ps
T362 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.2630257673 Mar 21 12:24:19 PM PDT 24 Mar 21 12:24:26 PM PDT 24 4245229613 ps
T363 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.718146646 Mar 21 12:24:22 PM PDT 24 Mar 21 12:24:23 PM PDT 24 483548753 ps
T364 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.1902720417 Mar 21 12:24:04 PM PDT 24 Mar 21 12:24:05 PM PDT 24 350865659 ps
T365 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.1504704400 Mar 21 12:24:32 PM PDT 24 Mar 21 12:24:35 PM PDT 24 4426768200 ps
T66 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.3534414707 Mar 21 12:24:02 PM PDT 24 Mar 21 12:24:08 PM PDT 24 9131321717 ps
T366 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.1298398112 Mar 21 12:24:39 PM PDT 24 Mar 21 12:24:40 PM PDT 24 509586779 ps
T367 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.81944992 Mar 21 12:24:12 PM PDT 24 Mar 21 12:24:14 PM PDT 24 948511783 ps
T368 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.1515093490 Mar 21 12:24:02 PM PDT 24 Mar 21 12:24:06 PM PDT 24 1025789680 ps
T369 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.2382057914 Mar 21 12:24:08 PM PDT 24 Mar 21 12:24:09 PM PDT 24 404608088 ps
T67 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.2273827201 Mar 21 12:24:15 PM PDT 24 Mar 21 12:24:16 PM PDT 24 346982651 ps
T370 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.132527386 Mar 21 12:24:19 PM PDT 24 Mar 21 12:24:21 PM PDT 24 907472206 ps
T371 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.3058286518 Mar 21 12:24:01 PM PDT 24 Mar 21 12:24:04 PM PDT 24 532961708 ps
T372 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.3731756645 Mar 21 12:24:26 PM PDT 24 Mar 21 12:24:28 PM PDT 24 512331297 ps
T373 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.3018526739 Mar 21 12:24:08 PM PDT 24 Mar 21 12:24:10 PM PDT 24 614200515 ps
T374 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.2837409910 Mar 21 12:24:21 PM PDT 24 Mar 21 12:24:23 PM PDT 24 611369361 ps
T375 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.1795052717 Mar 21 12:24:17 PM PDT 24 Mar 21 12:24:18 PM PDT 24 418582216 ps
T376 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.2923878851 Mar 21 12:24:16 PM PDT 24 Mar 21 12:24:18 PM PDT 24 457525041 ps
T377 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.2806015691 Mar 21 12:24:17 PM PDT 24 Mar 21 12:24:18 PM PDT 24 521647511 ps
T378 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.2224278871 Mar 21 12:24:24 PM PDT 24 Mar 21 12:24:25 PM PDT 24 286011661 ps
T379 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.825252726 Mar 21 12:24:09 PM PDT 24 Mar 21 12:24:11 PM PDT 24 475416888 ps
T380 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.775817093 Mar 21 12:24:32 PM PDT 24 Mar 21 12:24:33 PM PDT 24 488422539 ps
T381 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.1458765872 Mar 21 12:24:19 PM PDT 24 Mar 21 12:24:21 PM PDT 24 1764998157 ps
T382 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.2364956426 Mar 21 12:24:15 PM PDT 24 Mar 21 12:24:17 PM PDT 24 1619119154 ps
T383 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.1000594123 Mar 21 12:24:01 PM PDT 24 Mar 21 12:24:04 PM PDT 24 437869600 ps
T384 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.3362830407 Mar 21 12:24:10 PM PDT 24 Mar 21 12:24:12 PM PDT 24 836180135 ps
T385 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.4152422495 Mar 21 12:24:16 PM PDT 24 Mar 21 12:24:17 PM PDT 24 405060962 ps
T386 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.513575487 Mar 21 12:24:11 PM PDT 24 Mar 21 12:24:12 PM PDT 24 1173150652 ps
T387 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.2390971077 Mar 21 12:24:10 PM PDT 24 Mar 21 12:24:12 PM PDT 24 545924572 ps
T388 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.4282013818 Mar 21 12:24:25 PM PDT 24 Mar 21 12:24:26 PM PDT 24 407730518 ps
T389 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.2161397048 Mar 21 12:24:03 PM PDT 24 Mar 21 12:24:04 PM PDT 24 378354524 ps
T390 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.3637271456 Mar 21 12:24:21 PM PDT 24 Mar 21 12:24:22 PM PDT 24 310335770 ps
T391 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.82762782 Mar 21 12:24:31 PM PDT 24 Mar 21 12:24:32 PM PDT 24 438959300 ps
T392 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.313544164 Mar 21 12:24:19 PM PDT 24 Mar 21 12:24:21 PM PDT 24 2368271273 ps
T393 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.2853319252 Mar 21 12:24:01 PM PDT 24 Mar 21 12:24:02 PM PDT 24 434426946 ps
T394 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.2741558337 Mar 21 12:24:12 PM PDT 24 Mar 21 12:24:13 PM PDT 24 384798289 ps
T395 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.4291262453 Mar 21 12:24:35 PM PDT 24 Mar 21 12:24:36 PM PDT 24 349506049 ps
T396 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.3400095373 Mar 21 12:24:33 PM PDT 24 Mar 21 12:24:34 PM PDT 24 318170243 ps
T397 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.3187152477 Mar 21 12:24:09 PM PDT 24 Mar 21 12:24:10 PM PDT 24 679910708 ps
T398 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.1414824190 Mar 21 12:24:20 PM PDT 24 Mar 21 12:24:22 PM PDT 24 492707130 ps
T399 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.1139193819 Mar 21 12:24:18 PM PDT 24 Mar 21 12:24:19 PM PDT 24 504203418 ps
T400 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.1808660118 Mar 21 12:24:12 PM PDT 24 Mar 21 12:24:24 PM PDT 24 8101951848 ps
T401 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.1780290778 Mar 21 12:24:20 PM PDT 24 Mar 21 12:24:21 PM PDT 24 470837562 ps
T402 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.1852760911 Mar 21 12:24:00 PM PDT 24 Mar 21 12:24:02 PM PDT 24 576709569 ps
T403 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.3864047936 Mar 21 12:24:17 PM PDT 24 Mar 21 12:24:19 PM PDT 24 2289679204 ps
T404 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.3727860302 Mar 21 12:23:55 PM PDT 24 Mar 21 12:23:58 PM PDT 24 597178201 ps
T405 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.77449739 Mar 21 12:23:59 PM PDT 24 Mar 21 12:24:00 PM PDT 24 471437132 ps
T406 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.3247943098 Mar 21 12:24:11 PM PDT 24 Mar 21 12:24:13 PM PDT 24 498503561 ps
T407 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.147253701 Mar 21 12:24:00 PM PDT 24 Mar 21 12:24:08 PM PDT 24 8207736058 ps
T408 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.2453271545 Mar 21 12:24:12 PM PDT 24 Mar 21 12:24:15 PM PDT 24 601791637 ps
T409 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.3220552852 Mar 21 12:24:12 PM PDT 24 Mar 21 12:24:20 PM PDT 24 4384863712 ps
T410 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.3852234818 Mar 21 12:24:19 PM PDT 24 Mar 21 12:24:21 PM PDT 24 8759001205 ps
T411 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.1786621135 Mar 21 12:24:07 PM PDT 24 Mar 21 12:24:14 PM PDT 24 8513366921 ps
T412 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.2872256503 Mar 21 12:24:42 PM PDT 24 Mar 21 12:24:43 PM PDT 24 317885533 ps
T413 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.899724568 Mar 21 12:24:35 PM PDT 24 Mar 21 12:24:36 PM PDT 24 458670245 ps
T414 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.474088044 Mar 21 12:24:33 PM PDT 24 Mar 21 12:24:34 PM PDT 24 504921475 ps
T415 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.1295179176 Mar 21 12:24:00 PM PDT 24 Mar 21 12:24:02 PM PDT 24 1457371106 ps
T416 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.427847968 Mar 21 12:24:12 PM PDT 24 Mar 21 12:24:14 PM PDT 24 360096728 ps
T417 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.2126791390 Mar 21 12:24:11 PM PDT 24 Mar 21 12:24:13 PM PDT 24 556833007 ps
T418 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.1710527055 Mar 21 12:24:03 PM PDT 24 Mar 21 12:24:04 PM PDT 24 396431251 ps
T419 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.1946088433 Mar 21 12:24:15 PM PDT 24 Mar 21 12:24:17 PM PDT 24 704491582 ps

Test location /workspace/coverage/default/15.aon_timer_stress_all.3544235387
Short name T7
Test name
Test status
Simulation time 129401279639 ps
CPU time 51.38 seconds
Started Mar 21 12:38:03 PM PDT 24
Finished Mar 21 12:38:55 PM PDT 24
Peak memory 193660 kb
Host smart-30befcbc-efb6-43a0-8548-4e008418379c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544235387 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_
all.3544235387
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.2671295092
Short name T16
Test name
Test status
Simulation time 458881980501 ps
CPU time 971.49 seconds
Started Mar 21 12:38:03 PM PDT 24
Finished Mar 21 12:54:14 PM PDT 24
Peak memory 203268 kb
Host smart-424f83d2-fbcf-4bde-be3d-b9ec50b7f78c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671295092 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.2671295092
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.2074651195
Short name T24
Test name
Test status
Simulation time 8155626787 ps
CPU time 4.18 seconds
Started Mar 21 12:24:19 PM PDT 24
Finished Mar 21 12:24:23 PM PDT 24
Peak memory 196428 kb
Host smart-debc793b-04a6-462a-b9d4-6063d090f8e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074651195 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_t
l_intg_err.2074651195
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.2932784678
Short name T15
Test name
Test status
Simulation time 120009261729 ps
CPU time 481.98 seconds
Started Mar 21 12:38:00 PM PDT 24
Finished Mar 21 12:46:02 PM PDT 24
Peak memory 206020 kb
Host smart-3615c917-ceb6-4e92-beee-f2dde5ae990b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932784678 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand_reset.2932784678
Directory /workspace/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.2180986450
Short name T28
Test name
Test status
Simulation time 380743653 ps
CPU time 1.13 seconds
Started Mar 21 12:24:17 PM PDT 24
Finished Mar 21 12:24:19 PM PDT 24
Peak memory 183644 kb
Host smart-78a6ae40-33d3-4b6a-aab5-8a6d2ff16528
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180986450 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.2180986450
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.2628470897
Short name T19
Test name
Test status
Simulation time 4629931750 ps
CPU time 2.44 seconds
Started Mar 21 12:37:56 PM PDT 24
Finished Mar 21 12:38:00 PM PDT 24
Peak memory 214736 kb
Host smart-be8629b9-318c-4aef-bf52-c12c1ece7700
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628470897 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.2628470897
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.512104551
Short name T149
Test name
Test status
Simulation time 130938025861 ps
CPU time 280.36 seconds
Started Mar 21 12:38:33 PM PDT 24
Finished Mar 21 12:43:13 PM PDT 24
Peak memory 197916 kb
Host smart-500d460e-a6db-4347-b17c-528bc246bd18
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512104551 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.512104551
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.2859084204
Short name T39
Test name
Test status
Simulation time 390467177145 ps
CPU time 149.25 seconds
Started Mar 21 12:38:21 PM PDT 24
Finished Mar 21 12:40:50 PM PDT 24
Peak memory 194840 kb
Host smart-40f11bad-f3c2-41d5-8b37-c77abe30ded2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859084204 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_
all.2859084204
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.3171487280
Short name T82
Test name
Test status
Simulation time 114649397394 ps
CPU time 373.54 seconds
Started Mar 21 12:38:08 PM PDT 24
Finished Mar 21 12:44:22 PM PDT 24
Peak memory 197888 kb
Host smart-42036b84-ffad-490f-b9c4-db649766d9b2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171487280 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.3171487280
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.113675497
Short name T103
Test name
Test status
Simulation time 8295523226 ps
CPU time 7.61 seconds
Started Mar 21 12:24:21 PM PDT 24
Finished Mar 21 12:24:29 PM PDT 24
Peak memory 197696 kb
Host smart-a306212e-5eb7-48c7-acb3-a41773eb4677
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113675497 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl
_intg_err.113675497
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.3727860302
Short name T404
Test name
Test status
Simulation time 597178201 ps
CPU time 1.68 seconds
Started Mar 21 12:23:55 PM PDT 24
Finished Mar 21 12:23:58 PM PDT 24
Peak memory 183480 kb
Host smart-4c7334be-48a7-4cb8-ae4b-202fbe87edbc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727860302 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_a
liasing.3727860302
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.3534414707
Short name T66
Test name
Test status
Simulation time 9131321717 ps
CPU time 4.89 seconds
Started Mar 21 12:24:02 PM PDT 24
Finished Mar 21 12:24:08 PM PDT 24
Peak memory 193268 kb
Host smart-51d532ec-d33f-4b4e-8829-2b52740d5d2a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534414707 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_b
it_bash.3534414707
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.2194146866
Short name T56
Test name
Test status
Simulation time 1122217350 ps
CPU time 2.1 seconds
Started Mar 21 12:24:00 PM PDT 24
Finished Mar 21 12:24:02 PM PDT 24
Peak memory 183524 kb
Host smart-a445f5a8-b233-4554-aff8-cd0841a7e4bf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194146866 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_h
w_reset.2194146866
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.4066371704
Short name T351
Test name
Test status
Simulation time 565009797 ps
CPU time 1.06 seconds
Started Mar 21 12:23:54 PM PDT 24
Finished Mar 21 12:23:55 PM PDT 24
Peak memory 195376 kb
Host smart-26359cc3-21fd-4ddb-b911-540627acfaed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066371704 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.4066371704
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.3482032131
Short name T65
Test name
Test status
Simulation time 434785839 ps
CPU time 1.15 seconds
Started Mar 21 12:24:03 PM PDT 24
Finished Mar 21 12:24:04 PM PDT 24
Peak memory 183468 kb
Host smart-6087133a-d274-4159-8953-30cc2f7c941f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482032131 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.3482032131
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.301361015
Short name T301
Test name
Test status
Simulation time 412505074 ps
CPU time 1.21 seconds
Started Mar 21 12:24:01 PM PDT 24
Finished Mar 21 12:24:03 PM PDT 24
Peak memory 182088 kb
Host smart-418e7edc-fb20-4d07-9c5f-975577ed2f5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301361015 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.301361015
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.2097376279
Short name T340
Test name
Test status
Simulation time 310083606 ps
CPU time 0.97 seconds
Started Mar 21 12:24:01 PM PDT 24
Finished Mar 21 12:24:03 PM PDT 24
Peak memory 183472 kb
Host smart-754240d6-1908-4314-a9ef-39196c5dba1e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097376279 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_t
imer_mem_partial_access.2097376279
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.7455462
Short name T347
Test name
Test status
Simulation time 441054928 ps
CPU time 1.09 seconds
Started Mar 21 12:23:56 PM PDT 24
Finished Mar 21 12:23:57 PM PDT 24
Peak memory 183432 kb
Host smart-d504fef3-1eb8-4527-b36c-194930f670b5
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7455462 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_walk.7455462
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.1515093490
Short name T368
Test name
Test status
Simulation time 1025789680 ps
CPU time 3.14 seconds
Started Mar 21 12:24:02 PM PDT 24
Finished Mar 21 12:24:06 PM PDT 24
Peak memory 192244 kb
Host smart-3175a7d6-b63c-453a-b20c-c7a2fbe68f6f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515093490 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon
_timer_same_csr_outstanding.1515093490
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.1039759262
Short name T342
Test name
Test status
Simulation time 506560292 ps
CPU time 2.25 seconds
Started Mar 21 12:24:00 PM PDT 24
Finished Mar 21 12:24:03 PM PDT 24
Peak memory 198368 kb
Host smart-48eac903-3d77-4720-9e72-decb63ec3400
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039759262 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.1039759262
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.147253701
Short name T407
Test name
Test status
Simulation time 8207736058 ps
CPU time 7.31 seconds
Started Mar 21 12:24:00 PM PDT 24
Finished Mar 21 12:24:08 PM PDT 24
Peak memory 197064 kb
Host smart-7122668b-f917-4b1b-949f-53cf8f25aab3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147253701 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_
intg_err.147253701
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.290584291
Short name T345
Test name
Test status
Simulation time 566487206 ps
CPU time 1.37 seconds
Started Mar 21 12:24:02 PM PDT 24
Finished Mar 21 12:24:04 PM PDT 24
Peak memory 194072 kb
Host smart-3cfc7e08-6a75-4d1b-a88c-15a1c2e21d77
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290584291 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_al
iasing.290584291
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.1508260259
Short name T60
Test name
Test status
Simulation time 13947788527 ps
CPU time 7.01 seconds
Started Mar 21 12:24:17 PM PDT 24
Finished Mar 21 12:24:25 PM PDT 24
Peak memory 192136 kb
Host smart-fb911cdb-241a-4168-a6eb-c43d884215fa
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508260259 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_b
it_bash.1508260259
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.39206130
Short name T320
Test name
Test status
Simulation time 598816446 ps
CPU time 1.36 seconds
Started Mar 21 12:24:03 PM PDT 24
Finished Mar 21 12:24:05 PM PDT 24
Peak memory 183572 kb
Host smart-c5a5e6b6-f1e1-46d8-836d-df11bcff3330
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39206130 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_hw_
reset.39206130
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.1902720417
Short name T364
Test name
Test status
Simulation time 350865659 ps
CPU time 0.83 seconds
Started Mar 21 12:24:04 PM PDT 24
Finished Mar 21 12:24:05 PM PDT 24
Peak memory 194612 kb
Host smart-3e26bf9e-493b-49cf-9079-bed57feb237a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902720417 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.1902720417
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.2273827201
Short name T67
Test name
Test status
Simulation time 346982651 ps
CPU time 0.72 seconds
Started Mar 21 12:24:15 PM PDT 24
Finished Mar 21 12:24:16 PM PDT 24
Peak memory 192948 kb
Host smart-8badeb37-2df0-4de4-b75a-99399d28c368
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273827201 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.2273827201
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.1098462015
Short name T336
Test name
Test status
Simulation time 351206734 ps
CPU time 0.67 seconds
Started Mar 21 12:24:10 PM PDT 24
Finished Mar 21 12:24:11 PM PDT 24
Peak memory 183484 kb
Host smart-2b292cd9-3065-4a11-b8ab-b7e6538d6005
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098462015 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.1098462015
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.77449739
Short name T405
Test name
Test status
Simulation time 471437132 ps
CPU time 1.27 seconds
Started Mar 21 12:23:59 PM PDT 24
Finished Mar 21 12:24:00 PM PDT 24
Peak memory 183408 kb
Host smart-5904fa30-ae6e-43a5-afeb-7177532679e3
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77449739 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_
timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_tim
er_mem_partial_access.77449739
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.3118854008
Short name T316
Test name
Test status
Simulation time 378341112 ps
CPU time 0.55 seconds
Started Mar 21 12:24:15 PM PDT 24
Finished Mar 21 12:24:16 PM PDT 24
Peak memory 183564 kb
Host smart-f0476e5d-dff5-46ed-be53-beb8db4e1138
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118854008 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_w
alk.3118854008
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.2096130317
Short name T344
Test name
Test status
Simulation time 2680141975 ps
CPU time 2.78 seconds
Started Mar 21 12:24:10 PM PDT 24
Finished Mar 21 12:24:13 PM PDT 24
Peak memory 194256 kb
Host smart-9ececffa-1106-48bc-a07c-bd05a5e33b1e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096130317 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon
_timer_same_csr_outstanding.2096130317
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.2041850008
Short name T275
Test name
Test status
Simulation time 586027830 ps
CPU time 2.62 seconds
Started Mar 21 12:24:01 PM PDT 24
Finished Mar 21 12:24:05 PM PDT 24
Peak memory 197612 kb
Host smart-1f9d0cd4-c4b9-435d-a894-5bc0116bfe27
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041850008 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.2041850008
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.723767676
Short name T100
Test name
Test status
Simulation time 4163011322 ps
CPU time 7.32 seconds
Started Mar 21 12:24:10 PM PDT 24
Finished Mar 21 12:24:22 PM PDT 24
Peak memory 197092 kb
Host smart-d61b4beb-af6d-42c3-a622-5381755229eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723767676 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_
intg_err.723767676
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.825252726
Short name T379
Test name
Test status
Simulation time 475416888 ps
CPU time 1.29 seconds
Started Mar 21 12:24:09 PM PDT 24
Finished Mar 21 12:24:11 PM PDT 24
Peak memory 195492 kb
Host smart-22fea3d8-8bd3-4e6f-a35e-3fe47a1ea7f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825252726 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.825252726
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.2390971077
Short name T387
Test name
Test status
Simulation time 545924572 ps
CPU time 1.45 seconds
Started Mar 21 12:24:10 PM PDT 24
Finished Mar 21 12:24:12 PM PDT 24
Peak memory 192848 kb
Host smart-99dcfebc-820b-44a8-90d5-f8bc58076d0b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390971077 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.2390971077
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.3788424671
Short name T338
Test name
Test status
Simulation time 332992378 ps
CPU time 1.07 seconds
Started Mar 21 12:24:19 PM PDT 24
Finished Mar 21 12:24:25 PM PDT 24
Peak memory 182828 kb
Host smart-a3228af1-e39d-4b0b-8880-e9a20d9611b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788424671 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.3788424671
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.513575487
Short name T386
Test name
Test status
Simulation time 1173150652 ps
CPU time 1.04 seconds
Started Mar 21 12:24:11 PM PDT 24
Finished Mar 21 12:24:12 PM PDT 24
Peak memory 183828 kb
Host smart-9bc85f9d-d08a-4aff-8c16-b49cf79566dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513575487 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon
_timer_same_csr_outstanding.513575487
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.2405222233
Short name T279
Test name
Test status
Simulation time 301880473 ps
CPU time 2.52 seconds
Started Mar 21 12:24:22 PM PDT 24
Finished Mar 21 12:24:25 PM PDT 24
Peak memory 198400 kb
Host smart-0f9c7af0-3402-4930-a9bb-a52521dd9f40
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405222233 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.2405222233
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.4152422495
Short name T385
Test name
Test status
Simulation time 405060962 ps
CPU time 1.23 seconds
Started Mar 21 12:24:16 PM PDT 24
Finished Mar 21 12:24:17 PM PDT 24
Peak memory 195864 kb
Host smart-5071937d-d2e3-4e19-8c21-2aa14087ebd5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152422495 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.4152422495
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.4072377605
Short name T353
Test name
Test status
Simulation time 424862518 ps
CPU time 0.67 seconds
Started Mar 21 12:24:08 PM PDT 24
Finished Mar 21 12:24:09 PM PDT 24
Peak memory 183472 kb
Host smart-19803b1b-8d81-4c51-90ed-ae5f0fb94830
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072377605 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.4072377605
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.1448628476
Short name T72
Test name
Test status
Simulation time 2416597168 ps
CPU time 6.6 seconds
Started Mar 21 12:24:18 PM PDT 24
Finished Mar 21 12:24:25 PM PDT 24
Peak memory 194764 kb
Host smart-7aa64f78-544b-44bd-bcbb-33b3ea6f8914
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448628476 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.ao
n_timer_same_csr_outstanding.1448628476
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.2126791390
Short name T417
Test name
Test status
Simulation time 556833007 ps
CPU time 1.89 seconds
Started Mar 21 12:24:11 PM PDT 24
Finished Mar 21 12:24:13 PM PDT 24
Peak memory 198372 kb
Host smart-8985178f-797a-4b0b-9a98-33373c0d7541
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126791390 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.2126791390
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.4038157625
Short name T101
Test name
Test status
Simulation time 8989555008 ps
CPU time 2.18 seconds
Started Mar 21 12:24:09 PM PDT 24
Finished Mar 21 12:24:12 PM PDT 24
Peak memory 197604 kb
Host smart-e30751ec-6c41-4217-9065-3450d96c70d8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038157625 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_t
l_intg_err.4038157625
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.634096829
Short name T303
Test name
Test status
Simulation time 512972577 ps
CPU time 1 seconds
Started Mar 21 12:24:19 PM PDT 24
Finished Mar 21 12:24:20 PM PDT 24
Peak memory 196264 kb
Host smart-c9db8c42-ca8d-45b0-96f5-3fba2215bf1b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634096829 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.634096829
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.2806015691
Short name T377
Test name
Test status
Simulation time 521647511 ps
CPU time 0.7 seconds
Started Mar 21 12:24:17 PM PDT 24
Finished Mar 21 12:24:18 PM PDT 24
Peak memory 192712 kb
Host smart-28ead866-4278-45f6-8893-3e5c2554cc33
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806015691 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.2806015691
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.1052099278
Short name T357
Test name
Test status
Simulation time 443993765 ps
CPU time 0.85 seconds
Started Mar 21 12:24:21 PM PDT 24
Finished Mar 21 12:24:22 PM PDT 24
Peak memory 183480 kb
Host smart-ccb1f2a4-84a8-4bc5-af04-6d00133c4b72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052099278 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.1052099278
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.1458765872
Short name T381
Test name
Test status
Simulation time 1764998157 ps
CPU time 1.74 seconds
Started Mar 21 12:24:19 PM PDT 24
Finished Mar 21 12:24:21 PM PDT 24
Peak memory 193328 kb
Host smart-c00e756a-00f8-4fe3-865f-d91c2cef7dc1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458765872 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.ao
n_timer_same_csr_outstanding.1458765872
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.81944992
Short name T367
Test name
Test status
Simulation time 948511783 ps
CPU time 1.82 seconds
Started Mar 21 12:24:12 PM PDT 24
Finished Mar 21 12:24:14 PM PDT 24
Peak memory 198412 kb
Host smart-febfaa42-1fee-4c82-a167-6799c6d049d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81944992 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.81944992
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.1808660118
Short name T400
Test name
Test status
Simulation time 8101951848 ps
CPU time 11.76 seconds
Started Mar 21 12:24:12 PM PDT 24
Finished Mar 21 12:24:24 PM PDT 24
Peak memory 197732 kb
Host smart-a8e0ee56-1f9a-4f81-8070-bf955609a98d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808660118 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_t
l_intg_err.1808660118
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.1196006413
Short name T292
Test name
Test status
Simulation time 452997705 ps
CPU time 0.87 seconds
Started Mar 21 12:24:20 PM PDT 24
Finished Mar 21 12:24:21 PM PDT 24
Peak memory 195544 kb
Host smart-109eedc5-e511-4154-aede-55907df54679
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196006413 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.1196006413
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.1574820818
Short name T282
Test name
Test status
Simulation time 483620108 ps
CPU time 0.76 seconds
Started Mar 21 12:24:17 PM PDT 24
Finished Mar 21 12:24:18 PM PDT 24
Peak memory 183784 kb
Host smart-41d8f8c1-5f10-470c-9afa-5e81085c0eff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574820818 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.1574820818
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.3247943098
Short name T406
Test name
Test status
Simulation time 498503561 ps
CPU time 1.44 seconds
Started Mar 21 12:24:11 PM PDT 24
Finished Mar 21 12:24:13 PM PDT 24
Peak memory 182740 kb
Host smart-14f1a3b6-14ae-470e-84a7-63a12b19cda4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247943098 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.3247943098
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.313544164
Short name T392
Test name
Test status
Simulation time 2368271273 ps
CPU time 1.86 seconds
Started Mar 21 12:24:19 PM PDT 24
Finished Mar 21 12:24:21 PM PDT 24
Peak memory 193748 kb
Host smart-5805c286-89a3-4035-aa0e-6e3937f5d0b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313544164 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon
_timer_same_csr_outstanding.313544164
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.2453271545
Short name T408
Test name
Test status
Simulation time 601791637 ps
CPU time 2.52 seconds
Started Mar 21 12:24:12 PM PDT 24
Finished Mar 21 12:24:15 PM PDT 24
Peak memory 198392 kb
Host smart-6362c685-81ee-48d0-b58f-1408fcecb26e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453271545 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.2453271545
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.3220552852
Short name T409
Test name
Test status
Simulation time 4384863712 ps
CPU time 7.93 seconds
Started Mar 21 12:24:12 PM PDT 24
Finished Mar 21 12:24:20 PM PDT 24
Peak memory 196628 kb
Host smart-89d58ced-81af-4351-bbd1-90226add7ee0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220552852 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_t
l_intg_err.3220552852
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.3731756645
Short name T372
Test name
Test status
Simulation time 512331297 ps
CPU time 1.43 seconds
Started Mar 21 12:24:26 PM PDT 24
Finished Mar 21 12:24:28 PM PDT 24
Peak memory 198628 kb
Host smart-a08daf6c-a639-4a8d-a131-6ff25e297c3e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731756645 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.3731756645
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.3495067977
Short name T73
Test name
Test status
Simulation time 474941034 ps
CPU time 0.91 seconds
Started Mar 21 12:24:20 PM PDT 24
Finished Mar 21 12:24:21 PM PDT 24
Peak memory 183564 kb
Host smart-27615eb5-9737-44d7-a843-892e6e4c3046
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495067977 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.3495067977
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.3383709819
Short name T314
Test name
Test status
Simulation time 309484856 ps
CPU time 0.69 seconds
Started Mar 21 12:24:17 PM PDT 24
Finished Mar 21 12:24:19 PM PDT 24
Peak memory 182412 kb
Host smart-838bfadc-e8e3-45a3-8029-6ac667243157
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383709819 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.3383709819
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.2086651448
Short name T350
Test name
Test status
Simulation time 1468442074 ps
CPU time 2.5 seconds
Started Mar 21 12:24:19 PM PDT 24
Finished Mar 21 12:24:22 PM PDT 24
Peak memory 191816 kb
Host smart-5b7c3274-0d19-40bd-a85a-7b9218e60b1a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086651448 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao
n_timer_same_csr_outstanding.2086651448
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.427847968
Short name T416
Test name
Test status
Simulation time 360096728 ps
CPU time 1.91 seconds
Started Mar 21 12:24:12 PM PDT 24
Finished Mar 21 12:24:14 PM PDT 24
Peak memory 197368 kb
Host smart-b7c1eb38-11e2-417c-ac44-33c6fbcc3d26
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427847968 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.427847968
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.3852234818
Short name T410
Test name
Test status
Simulation time 8759001205 ps
CPU time 1.82 seconds
Started Mar 21 12:24:19 PM PDT 24
Finished Mar 21 12:24:21 PM PDT 24
Peak memory 197596 kb
Host smart-4ff3af89-1ce7-4945-b4ef-42885f71eaf5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852234818 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_t
l_intg_err.3852234818
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.1596468127
Short name T308
Test name
Test status
Simulation time 546205851 ps
CPU time 1.05 seconds
Started Mar 21 12:24:28 PM PDT 24
Finished Mar 21 12:24:29 PM PDT 24
Peak memory 196844 kb
Host smart-4f4e870f-682c-4805-b736-8170b87c32a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596468127 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.1596468127
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.4012627021
Short name T359
Test name
Test status
Simulation time 430421032 ps
CPU time 0.8 seconds
Started Mar 21 12:24:13 PM PDT 24
Finished Mar 21 12:24:14 PM PDT 24
Peak memory 192180 kb
Host smart-f3e79f10-a989-47c3-b3cc-c7c748421a34
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012627021 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.4012627021
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.4032348599
Short name T307
Test name
Test status
Simulation time 493609475 ps
CPU time 0.64 seconds
Started Mar 21 12:24:16 PM PDT 24
Finished Mar 21 12:24:17 PM PDT 24
Peak memory 183376 kb
Host smart-2025694c-9108-4b09-a6ca-43f172e369ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032348599 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.4032348599
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.2306884233
Short name T330
Test name
Test status
Simulation time 1621930828 ps
CPU time 1.51 seconds
Started Mar 21 12:24:43 PM PDT 24
Finished Mar 21 12:24:45 PM PDT 24
Peak memory 193168 kb
Host smart-c57a2af0-9c93-4a80-9e75-87b6ed55fd38
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306884233 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.ao
n_timer_same_csr_outstanding.2306884233
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.3860953656
Short name T323
Test name
Test status
Simulation time 337840806 ps
CPU time 1.87 seconds
Started Mar 21 12:24:21 PM PDT 24
Finished Mar 21 12:24:22 PM PDT 24
Peak memory 198228 kb
Host smart-aae241dd-8f7e-4ffd-9e5b-63e695a6fbd1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860953656 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.3860953656
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.2630257673
Short name T362
Test name
Test status
Simulation time 4245229613 ps
CPU time 6.58 seconds
Started Mar 21 12:24:19 PM PDT 24
Finished Mar 21 12:24:26 PM PDT 24
Peak memory 197256 kb
Host smart-44d21d13-b824-4b7d-a4b6-de27ab70f5af
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630257673 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_t
l_intg_err.2630257673
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.224306389
Short name T26
Test name
Test status
Simulation time 488866130 ps
CPU time 1.27 seconds
Started Mar 21 12:24:40 PM PDT 24
Finished Mar 21 12:24:41 PM PDT 24
Peak memory 196736 kb
Host smart-7cf4de26-3ef8-4331-8699-687ec3b9affd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224306389 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.224306389
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.3637271456
Short name T390
Test name
Test status
Simulation time 310335770 ps
CPU time 1.07 seconds
Started Mar 21 12:24:21 PM PDT 24
Finished Mar 21 12:24:22 PM PDT 24
Peak memory 183496 kb
Host smart-e887e94f-5da7-4048-b02b-968c9d81250d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637271456 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.3637271456
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.1586927439
Short name T339
Test name
Test status
Simulation time 425297221 ps
CPU time 1.09 seconds
Started Mar 21 12:24:26 PM PDT 24
Finished Mar 21 12:24:28 PM PDT 24
Peak memory 183500 kb
Host smart-4a30d84f-63d3-4b16-b7a6-a37fb6e4f95f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586927439 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.1586927439
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.3647406586
Short name T348
Test name
Test status
Simulation time 2863793437 ps
CPU time 1.36 seconds
Started Mar 21 12:24:29 PM PDT 24
Finished Mar 21 12:24:31 PM PDT 24
Peak memory 194276 kb
Host smart-ee7e44d0-005d-4747-b013-4ea38695b834
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647406586 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.ao
n_timer_same_csr_outstanding.3647406586
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.132527386
Short name T370
Test name
Test status
Simulation time 907472206 ps
CPU time 1.88 seconds
Started Mar 21 12:24:19 PM PDT 24
Finished Mar 21 12:24:21 PM PDT 24
Peak memory 198452 kb
Host smart-4fa25065-d892-47e2-9de5-5e999d2b34ca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132527386 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.132527386
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.1119526313
Short name T29
Test name
Test status
Simulation time 4618142552 ps
CPU time 7.44 seconds
Started Mar 21 12:24:28 PM PDT 24
Finished Mar 21 12:24:35 PM PDT 24
Peak memory 197308 kb
Host smart-621d134b-84b5-47d5-9d78-9956e6b17eba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119526313 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_t
l_intg_err.1119526313
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.2530676318
Short name T331
Test name
Test status
Simulation time 325387627 ps
CPU time 0.98 seconds
Started Mar 21 12:24:31 PM PDT 24
Finished Mar 21 12:24:32 PM PDT 24
Peak memory 194684 kb
Host smart-95196024-47d3-4e77-9270-6d2e2259fa91
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530676318 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.2530676318
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.3400095373
Short name T396
Test name
Test status
Simulation time 318170243 ps
CPU time 1.07 seconds
Started Mar 21 12:24:33 PM PDT 24
Finished Mar 21 12:24:34 PM PDT 24
Peak memory 192912 kb
Host smart-381e8640-4840-42bb-bdc4-131b81fb872d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400095373 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.3400095373
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.2038927571
Short name T286
Test name
Test status
Simulation time 453733571 ps
CPU time 1.31 seconds
Started Mar 21 12:24:32 PM PDT 24
Finished Mar 21 12:24:33 PM PDT 24
Peak memory 183720 kb
Host smart-3a20a4ac-d675-40a9-b5fd-6dba4b35ec69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038927571 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.2038927571
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.480528572
Short name T74
Test name
Test status
Simulation time 1610916944 ps
CPU time 2.4 seconds
Started Mar 21 12:24:30 PM PDT 24
Finished Mar 21 12:24:32 PM PDT 24
Peak memory 183664 kb
Host smart-b99e9a98-3b8a-4e3f-9016-5addfc18d866
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480528572 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon
_timer_same_csr_outstanding.480528572
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.2127064301
Short name T341
Test name
Test status
Simulation time 493108046 ps
CPU time 1.87 seconds
Started Mar 21 12:24:26 PM PDT 24
Finished Mar 21 12:24:28 PM PDT 24
Peak memory 198376 kb
Host smart-33560bc4-1aed-495b-807a-207c45d31fbb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127064301 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.2127064301
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.1504704400
Short name T365
Test name
Test status
Simulation time 4426768200 ps
CPU time 2.51 seconds
Started Mar 21 12:24:32 PM PDT 24
Finished Mar 21 12:24:35 PM PDT 24
Peak memory 197348 kb
Host smart-a3d0e005-03ea-4b9c-b823-a6236b7dcf04
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504704400 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_t
l_intg_err.1504704400
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.1780290778
Short name T401
Test name
Test status
Simulation time 470837562 ps
CPU time 1.39 seconds
Started Mar 21 12:24:20 PM PDT 24
Finished Mar 21 12:24:21 PM PDT 24
Peak memory 195032 kb
Host smart-eac1e64f-3d29-458d-8f3a-e7fd8149a39e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780290778 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.1780290778
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.3621245861
Short name T318
Test name
Test status
Simulation time 286950197 ps
CPU time 1.05 seconds
Started Mar 21 12:24:26 PM PDT 24
Finished Mar 21 12:24:27 PM PDT 24
Peak memory 192844 kb
Host smart-7da6c4c3-a433-4620-aa3b-4395a5882782
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621245861 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.3621245861
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.4282013818
Short name T388
Test name
Test status
Simulation time 407730518 ps
CPU time 0.88 seconds
Started Mar 21 12:24:25 PM PDT 24
Finished Mar 21 12:24:26 PM PDT 24
Peak memory 183476 kb
Host smart-3648611b-8a1f-4f86-8168-01ae127dab9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282013818 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.4282013818
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.567391407
Short name T70
Test name
Test status
Simulation time 1480515598 ps
CPU time 1.89 seconds
Started Mar 21 12:24:30 PM PDT 24
Finished Mar 21 12:24:32 PM PDT 24
Peak memory 183628 kb
Host smart-a9f9cd0c-52dc-4161-92a4-9491724a655c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567391407 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon
_timer_same_csr_outstanding.567391407
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.1319299803
Short name T277
Test name
Test status
Simulation time 370913316 ps
CPU time 1.07 seconds
Started Mar 21 12:24:29 PM PDT 24
Finished Mar 21 12:24:30 PM PDT 24
Peak memory 197896 kb
Host smart-8d3a61cf-2790-483d-a33a-0c74fd12cc8c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319299803 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.1319299803
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.1451843821
Short name T25
Test name
Test status
Simulation time 7934182076 ps
CPU time 12.43 seconds
Started Mar 21 12:24:26 PM PDT 24
Finished Mar 21 12:24:38 PM PDT 24
Peak memory 197824 kb
Host smart-6e1e8e57-f2de-40ec-a990-0e3333367ef4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451843821 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_t
l_intg_err.1451843821
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.3174576410
Short name T289
Test name
Test status
Simulation time 426011013 ps
CPU time 0.91 seconds
Started Mar 21 12:24:47 PM PDT 24
Finished Mar 21 12:24:48 PM PDT 24
Peak memory 197196 kb
Host smart-32eaef59-26fa-47b2-8a2e-eebc9f981c7a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174576410 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.3174576410
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.3388282257
Short name T312
Test name
Test status
Simulation time 348529399 ps
CPU time 0.86 seconds
Started Mar 21 12:24:37 PM PDT 24
Finished Mar 21 12:24:38 PM PDT 24
Peak memory 191916 kb
Host smart-47b9b8ca-bd5b-4e67-9233-77101d95c8c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388282257 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.3388282257
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.718146646
Short name T363
Test name
Test status
Simulation time 483548753 ps
CPU time 1.26 seconds
Started Mar 21 12:24:22 PM PDT 24
Finished Mar 21 12:24:23 PM PDT 24
Peak memory 183500 kb
Host smart-84c0c182-fe61-4812-babf-7fff1a0a8934
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718146646 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.718146646
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.2801534698
Short name T337
Test name
Test status
Simulation time 2420338962 ps
CPU time 6.53 seconds
Started Mar 21 12:24:34 PM PDT 24
Finished Mar 21 12:24:41 PM PDT 24
Peak memory 194156 kb
Host smart-c40f0e68-6606-46a5-b052-38300cebee4d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801534698 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao
n_timer_same_csr_outstanding.2801534698
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.2837409910
Short name T374
Test name
Test status
Simulation time 611369361 ps
CPU time 1.67 seconds
Started Mar 21 12:24:21 PM PDT 24
Finished Mar 21 12:24:23 PM PDT 24
Peak memory 198412 kb
Host smart-2daaaf79-8890-4c28-adaa-c2ae01d042bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837409910 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.2837409910
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.1139973358
Short name T55
Test name
Test status
Simulation time 387640745 ps
CPU time 1.33 seconds
Started Mar 21 12:24:04 PM PDT 24
Finished Mar 21 12:24:05 PM PDT 24
Peak memory 183496 kb
Host smart-e0d58813-bd59-4e20-b181-9c6decd1f59c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139973358 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_a
liasing.1139973358
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.1816807590
Short name T57
Test name
Test status
Simulation time 6511156966 ps
CPU time 3.93 seconds
Started Mar 21 12:24:01 PM PDT 24
Finished Mar 21 12:24:06 PM PDT 24
Peak memory 191284 kb
Host smart-1d4235c5-91c2-4bdd-8c90-e0caaf065536
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816807590 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_b
it_bash.1816807590
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.3362830407
Short name T384
Test name
Test status
Simulation time 836180135 ps
CPU time 0.86 seconds
Started Mar 21 12:24:10 PM PDT 24
Finished Mar 21 12:24:12 PM PDT 24
Peak memory 183620 kb
Host smart-e48bd368-7a27-4f14-986f-06ce6423df94
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362830407 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_h
w_reset.3362830407
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.702125998
Short name T306
Test name
Test status
Simulation time 491568128 ps
CPU time 0.81 seconds
Started Mar 21 12:24:17 PM PDT 24
Finished Mar 21 12:24:18 PM PDT 24
Peak memory 196672 kb
Host smart-25dc003b-2f73-434f-9ee0-f9e5ad05a696
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702125998 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.702125998
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.1476978326
Short name T58
Test name
Test status
Simulation time 504373304 ps
CPU time 1.34 seconds
Started Mar 21 12:24:00 PM PDT 24
Finished Mar 21 12:24:03 PM PDT 24
Peak memory 182800 kb
Host smart-0a33324b-9a6a-4c02-a165-db275faaf1aa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476978326 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.1476978326
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.3429590467
Short name T355
Test name
Test status
Simulation time 506698326 ps
CPU time 0.85 seconds
Started Mar 21 12:24:03 PM PDT 24
Finished Mar 21 12:24:05 PM PDT 24
Peak memory 182248 kb
Host smart-3a2f4ba1-2bc5-4969-b669-7ec13a9de686
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429590467 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.3429590467
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.375651868
Short name T322
Test name
Test status
Simulation time 359096774 ps
CPU time 1.05 seconds
Started Mar 21 12:24:15 PM PDT 24
Finished Mar 21 12:24:16 PM PDT 24
Peak memory 183504 kb
Host smart-f6adcddc-2f7c-4d42-8de0-c9c629d89982
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375651868 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_ti
mer_mem_partial_access.375651868
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.1691986970
Short name T329
Test name
Test status
Simulation time 301052357 ps
CPU time 0.66 seconds
Started Mar 21 12:23:57 PM PDT 24
Finished Mar 21 12:23:58 PM PDT 24
Peak memory 183480 kb
Host smart-f6d3ed76-a465-41b3-96bd-f878327121ff
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691986970 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_w
alk.1691986970
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.2364956426
Short name T382
Test name
Test status
Simulation time 1619119154 ps
CPU time 1.9 seconds
Started Mar 21 12:24:15 PM PDT 24
Finished Mar 21 12:24:17 PM PDT 24
Peak memory 193088 kb
Host smart-12cb6e5f-6c81-4aed-b02b-727ab4d8aa67
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364956426 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon
_timer_same_csr_outstanding.2364956426
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.3058286518
Short name T371
Test name
Test status
Simulation time 532961708 ps
CPU time 2.17 seconds
Started Mar 21 12:24:01 PM PDT 24
Finished Mar 21 12:24:04 PM PDT 24
Peak memory 197120 kb
Host smart-142fe856-b68e-4880-9a11-0b820d50347b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058286518 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.3058286518
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.1786621135
Short name T411
Test name
Test status
Simulation time 8513366921 ps
CPU time 6.89 seconds
Started Mar 21 12:24:07 PM PDT 24
Finished Mar 21 12:24:14 PM PDT 24
Peak memory 197800 kb
Host smart-2a858e2a-180b-4840-b68d-a53a3d9b3d4c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786621135 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl
_intg_err.1786621135
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.3284203755
Short name T295
Test name
Test status
Simulation time 323451882 ps
CPU time 0.98 seconds
Started Mar 21 12:24:37 PM PDT 24
Finished Mar 21 12:24:38 PM PDT 24
Peak memory 183468 kb
Host smart-754d4d82-7284-4732-a6f5-70b0a3de2bb1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284203755 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.3284203755
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.641010425
Short name T327
Test name
Test status
Simulation time 285021520 ps
CPU time 0.93 seconds
Started Mar 21 12:24:32 PM PDT 24
Finished Mar 21 12:24:33 PM PDT 24
Peak memory 183468 kb
Host smart-63d43067-fa50-4592-b7d2-eb8a6ff26900
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641010425 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.641010425
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.518265628
Short name T284
Test name
Test status
Simulation time 479595990 ps
CPU time 0.75 seconds
Started Mar 21 12:24:33 PM PDT 24
Finished Mar 21 12:24:34 PM PDT 24
Peak memory 183464 kb
Host smart-8fd66e5c-24b3-4355-9d22-8102999dc011
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518265628 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.518265628
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.2439242126
Short name T317
Test name
Test status
Simulation time 268323556 ps
CPU time 1 seconds
Started Mar 21 12:24:33 PM PDT 24
Finished Mar 21 12:24:34 PM PDT 24
Peak memory 183496 kb
Host smart-b199ff22-d896-4028-83ec-2906ca7db1ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439242126 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.2439242126
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.108564808
Short name T305
Test name
Test status
Simulation time 318720915 ps
CPU time 0.73 seconds
Started Mar 21 12:24:34 PM PDT 24
Finished Mar 21 12:24:35 PM PDT 24
Peak memory 183464 kb
Host smart-10633dd1-c324-43fb-bdcc-13ebfcff7be2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108564808 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.108564808
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.3217470305
Short name T288
Test name
Test status
Simulation time 405460664 ps
CPU time 0.63 seconds
Started Mar 21 12:24:20 PM PDT 24
Finished Mar 21 12:24:21 PM PDT 24
Peak memory 183480 kb
Host smart-f2d4d968-d2f7-4065-bdfb-f9ea7bbb6238
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217470305 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.3217470305
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.260337398
Short name T311
Test name
Test status
Simulation time 398205065 ps
CPU time 0.67 seconds
Started Mar 21 12:24:32 PM PDT 24
Finished Mar 21 12:24:32 PM PDT 24
Peak memory 183488 kb
Host smart-8cedb16e-1adf-4f47-81f5-1299a0755eed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260337398 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.260337398
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.1442620411
Short name T361
Test name
Test status
Simulation time 363392370 ps
CPU time 0.67 seconds
Started Mar 21 12:24:38 PM PDT 24
Finished Mar 21 12:24:38 PM PDT 24
Peak memory 183488 kb
Host smart-e8686070-8202-4611-9776-b6e8ad43e7d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442620411 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.1442620411
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.1823606672
Short name T276
Test name
Test status
Simulation time 486366870 ps
CPU time 0.74 seconds
Started Mar 21 12:24:22 PM PDT 24
Finished Mar 21 12:24:23 PM PDT 24
Peak memory 183496 kb
Host smart-0da71829-5189-4d28-9a1c-0960857caa6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823606672 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.1823606672
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.2119429216
Short name T281
Test name
Test status
Simulation time 477630146 ps
CPU time 1.24 seconds
Started Mar 21 12:24:27 PM PDT 24
Finished Mar 21 12:24:29 PM PDT 24
Peak memory 183488 kb
Host smart-a2fa8c71-3bb5-43c5-b886-0b194b496e01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119429216 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.2119429216
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.3216259724
Short name T278
Test name
Test status
Simulation time 597633676 ps
CPU time 1.49 seconds
Started Mar 21 12:24:00 PM PDT 24
Finished Mar 21 12:24:02 PM PDT 24
Peak memory 193184 kb
Host smart-8d5bc96c-25ea-4e45-ae90-55c60d1c4e17
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216259724 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_a
liasing.3216259724
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.2028574044
Short name T63
Test name
Test status
Simulation time 624067764 ps
CPU time 1.91 seconds
Started Mar 21 12:24:14 PM PDT 24
Finished Mar 21 12:24:16 PM PDT 24
Peak memory 195284 kb
Host smart-ed66560b-0d9e-40f9-a6b0-3504c53f4c97
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028574044 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_b
it_bash.2028574044
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.856917940
Short name T297
Test name
Test status
Simulation time 579180823 ps
CPU time 0.99 seconds
Started Mar 21 12:24:15 PM PDT 24
Finished Mar 21 12:24:16 PM PDT 24
Peak memory 183556 kb
Host smart-be32b9b8-f639-419b-96c8-c0207f830bfb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856917940 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_hw
_reset.856917940
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.3417293191
Short name T349
Test name
Test status
Simulation time 488137143 ps
CPU time 1.52 seconds
Started Mar 21 12:24:15 PM PDT 24
Finished Mar 21 12:24:18 PM PDT 24
Peak memory 196032 kb
Host smart-f234e7e7-2472-430d-9507-01867d22b3af
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417293191 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.3417293191
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.3321336801
Short name T64
Test name
Test status
Simulation time 499054849 ps
CPU time 1.09 seconds
Started Mar 21 12:24:09 PM PDT 24
Finished Mar 21 12:24:10 PM PDT 24
Peak memory 192788 kb
Host smart-23e4d40f-5019-4fe2-8966-bcc81aef2271
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321336801 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.3321336801
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.635627332
Short name T293
Test name
Test status
Simulation time 485534665 ps
CPU time 1.17 seconds
Started Mar 21 12:24:16 PM PDT 24
Finished Mar 21 12:24:17 PM PDT 24
Peak memory 183476 kb
Host smart-732a7759-2335-4f45-8474-d05fc0d7df8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635627332 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.635627332
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.2853319252
Short name T393
Test name
Test status
Simulation time 434426946 ps
CPU time 0.88 seconds
Started Mar 21 12:24:01 PM PDT 24
Finished Mar 21 12:24:02 PM PDT 24
Peak memory 182712 kb
Host smart-3f7e672b-1be8-40b4-b312-b9dc0a74f512
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853319252 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_t
imer_mem_partial_access.2853319252
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.2893193469
Short name T310
Test name
Test status
Simulation time 279183867 ps
CPU time 0.98 seconds
Started Mar 21 12:24:03 PM PDT 24
Finished Mar 21 12:24:05 PM PDT 24
Peak memory 182388 kb
Host smart-4ff6649f-999a-45e3-bfd7-50b9be95f7bd
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893193469 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_w
alk.2893193469
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.3941954248
Short name T71
Test name
Test status
Simulation time 2500606891 ps
CPU time 2.62 seconds
Started Mar 21 12:24:01 PM PDT 24
Finished Mar 21 12:24:04 PM PDT 24
Peak memory 194000 kb
Host smart-e3736239-88b2-4ad4-ad58-0d7f043855e7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941954248 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon
_timer_same_csr_outstanding.3941954248
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.1852760911
Short name T402
Test name
Test status
Simulation time 576709569 ps
CPU time 2.25 seconds
Started Mar 21 12:24:00 PM PDT 24
Finished Mar 21 12:24:02 PM PDT 24
Peak memory 198088 kb
Host smart-255eb802-e5b8-45ee-b659-6318205cd6da
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852760911 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.1852760911
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.660519212
Short name T294
Test name
Test status
Simulation time 4201240874 ps
CPU time 2.43 seconds
Started Mar 21 12:24:05 PM PDT 24
Finished Mar 21 12:24:08 PM PDT 24
Peak memory 196232 kb
Host smart-00480976-d82a-4a76-a9cd-a598bec920c3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660519212 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_
intg_err.660519212
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.775817093
Short name T380
Test name
Test status
Simulation time 488422539 ps
CPU time 0.58 seconds
Started Mar 21 12:24:32 PM PDT 24
Finished Mar 21 12:24:33 PM PDT 24
Peak memory 183464 kb
Host smart-1bd19acd-6ccc-4830-81ba-80d78438d1a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775817093 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.775817093
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.3294404331
Short name T343
Test name
Test status
Simulation time 364185817 ps
CPU time 0.72 seconds
Started Mar 21 12:24:38 PM PDT 24
Finished Mar 21 12:24:39 PM PDT 24
Peak memory 183488 kb
Host smart-cdbdc9b3-6998-43f2-a68f-bb2e0b67cfb0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294404331 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.3294404331
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.82762782
Short name T391
Test name
Test status
Simulation time 438959300 ps
CPU time 0.65 seconds
Started Mar 21 12:24:31 PM PDT 24
Finished Mar 21 12:24:32 PM PDT 24
Peak memory 183628 kb
Host smart-e0fd5115-f23c-455f-8a28-93ca4e976954
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82762782 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.82762782
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.1298398112
Short name T366
Test name
Test status
Simulation time 509586779 ps
CPU time 0.69 seconds
Started Mar 21 12:24:39 PM PDT 24
Finished Mar 21 12:24:40 PM PDT 24
Peak memory 183492 kb
Host smart-6a68796f-ba60-4254-8c73-8661c27460c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298398112 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.1298398112
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.1414824190
Short name T398
Test name
Test status
Simulation time 492707130 ps
CPU time 1.19 seconds
Started Mar 21 12:24:20 PM PDT 24
Finished Mar 21 12:24:22 PM PDT 24
Peak memory 183420 kb
Host smart-1464053c-1e7b-406f-a09e-fd11c5bbc86e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414824190 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.1414824190
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.899724568
Short name T413
Test name
Test status
Simulation time 458670245 ps
CPU time 0.75 seconds
Started Mar 21 12:24:35 PM PDT 24
Finished Mar 21 12:24:36 PM PDT 24
Peak memory 183484 kb
Host smart-229dbb3c-9c3a-4d0c-bfb7-03c9223eb06f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899724568 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.899724568
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.3425505150
Short name T335
Test name
Test status
Simulation time 292370163 ps
CPU time 0.9 seconds
Started Mar 21 12:24:24 PM PDT 24
Finished Mar 21 12:24:25 PM PDT 24
Peak memory 183496 kb
Host smart-013e76be-a108-40a4-84f1-e314f5ec4ad0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425505150 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.3425505150
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.2935533982
Short name T309
Test name
Test status
Simulation time 314128611 ps
CPU time 0.66 seconds
Started Mar 21 12:24:20 PM PDT 24
Finished Mar 21 12:24:21 PM PDT 24
Peak memory 183704 kb
Host smart-5aa41477-c046-458f-b2ac-b37bb7fa171a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935533982 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.2935533982
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.2224278871
Short name T378
Test name
Test status
Simulation time 286011661 ps
CPU time 0.74 seconds
Started Mar 21 12:24:24 PM PDT 24
Finished Mar 21 12:24:25 PM PDT 24
Peak memory 183440 kb
Host smart-f0afab9e-4818-499f-aca0-cc20444f1b64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224278871 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.2224278871
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.2888622531
Short name T283
Test name
Test status
Simulation time 448596948 ps
CPU time 0.67 seconds
Started Mar 21 12:24:19 PM PDT 24
Finished Mar 21 12:24:19 PM PDT 24
Peak memory 183456 kb
Host smart-431e699e-9a3a-4639-a16d-6ca88bd1b640
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888622531 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.2888622531
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.1946088433
Short name T419
Test name
Test status
Simulation time 704491582 ps
CPU time 1.1 seconds
Started Mar 21 12:24:15 PM PDT 24
Finished Mar 21 12:24:17 PM PDT 24
Peak memory 182584 kb
Host smart-518f1e39-fd41-43c4-bd83-74abaa52ba1c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946088433 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_a
liasing.1946088433
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.2644142430
Short name T104
Test name
Test status
Simulation time 7243701213 ps
CPU time 4.68 seconds
Started Mar 21 12:24:05 PM PDT 24
Finished Mar 21 12:24:10 PM PDT 24
Peak memory 195048 kb
Host smart-8421d373-ca11-4a85-9ff5-436e1fceab65
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644142430 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_b
it_bash.2644142430
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.4152420237
Short name T304
Test name
Test status
Simulation time 903182895 ps
CPU time 0.92 seconds
Started Mar 21 12:24:15 PM PDT 24
Finished Mar 21 12:24:17 PM PDT 24
Peak memory 183644 kb
Host smart-0d72d7c6-4962-473c-b8b0-e9c0aa5da316
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152420237 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_h
w_reset.4152420237
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.2760294288
Short name T302
Test name
Test status
Simulation time 558564154 ps
CPU time 1.17 seconds
Started Mar 21 12:24:16 PM PDT 24
Finished Mar 21 12:24:17 PM PDT 24
Peak memory 197532 kb
Host smart-704ea6a5-e695-49fd-badf-6c5d89aeb1c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760294288 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.2760294288
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.1834612691
Short name T326
Test name
Test status
Simulation time 452947048 ps
CPU time 0.78 seconds
Started Mar 21 12:24:10 PM PDT 24
Finished Mar 21 12:24:11 PM PDT 24
Peak memory 183716 kb
Host smart-365817fa-6e36-433f-8196-9a6793fe18ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834612691 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.1834612691
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.4143585714
Short name T299
Test name
Test status
Simulation time 320257429 ps
CPU time 1.24 seconds
Started Mar 21 12:24:01 PM PDT 24
Finished Mar 21 12:24:03 PM PDT 24
Peak memory 182336 kb
Host smart-0ace8d4a-28d2-4b17-9773-ee58d3144cf4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143585714 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.4143585714
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.630702630
Short name T315
Test name
Test status
Simulation time 272707883 ps
CPU time 0.69 seconds
Started Mar 21 12:24:02 PM PDT 24
Finished Mar 21 12:24:03 PM PDT 24
Peak memory 183480 kb
Host smart-6a234aaf-d0d5-420b-815c-43fe3e23be42
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630702630 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_ti
mer_mem_partial_access.630702630
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.3439407966
Short name T313
Test name
Test status
Simulation time 537335281 ps
CPU time 0.68 seconds
Started Mar 21 12:24:12 PM PDT 24
Finished Mar 21 12:24:13 PM PDT 24
Peak memory 183564 kb
Host smart-f62d21da-9041-4b7a-9a47-1640c0d34958
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439407966 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_w
alk.3439407966
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.3864047936
Short name T403
Test name
Test status
Simulation time 2289679204 ps
CPU time 1.52 seconds
Started Mar 21 12:24:17 PM PDT 24
Finished Mar 21 12:24:19 PM PDT 24
Peak memory 183552 kb
Host smart-8ca36172-408f-4b7e-a1f9-9873ca077ef9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864047936 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon
_timer_same_csr_outstanding.3864047936
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.2517098287
Short name T291
Test name
Test status
Simulation time 2677335097 ps
CPU time 2.41 seconds
Started Mar 21 12:24:01 PM PDT 24
Finished Mar 21 12:24:04 PM PDT 24
Peak memory 197648 kb
Host smart-37a27fc6-2a50-48ee-94a1-cb33d8ec0642
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517098287 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.2517098287
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.3239641786
Short name T352
Test name
Test status
Simulation time 8823854836 ps
CPU time 3.63 seconds
Started Mar 21 12:24:10 PM PDT 24
Finished Mar 21 12:24:14 PM PDT 24
Peak memory 197780 kb
Host smart-53560d27-521a-4707-8508-e00430f08615
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239641786 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl
_intg_err.3239641786
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.3624104257
Short name T333
Test name
Test status
Simulation time 553003414 ps
CPU time 0.61 seconds
Started Mar 21 12:24:35 PM PDT 24
Finished Mar 21 12:24:36 PM PDT 24
Peak memory 183472 kb
Host smart-3b4c86be-e1bd-4cbd-b3c1-dcc2ffe2c0cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624104257 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.3624104257
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.4291262453
Short name T395
Test name
Test status
Simulation time 349506049 ps
CPU time 0.66 seconds
Started Mar 21 12:24:35 PM PDT 24
Finished Mar 21 12:24:36 PM PDT 24
Peak memory 183472 kb
Host smart-8442ab43-1f70-4a68-a7e5-80a54d876486
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291262453 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.4291262453
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.4148130875
Short name T360
Test name
Test status
Simulation time 450362561 ps
CPU time 1.16 seconds
Started Mar 21 12:24:36 PM PDT 24
Finished Mar 21 12:24:38 PM PDT 24
Peak memory 183480 kb
Host smart-4cc307a2-cb48-4c26-bba3-54f792bc1cea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148130875 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.4148130875
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.3321000336
Short name T290
Test name
Test status
Simulation time 390858850 ps
CPU time 0.67 seconds
Started Mar 21 12:24:27 PM PDT 24
Finished Mar 21 12:24:27 PM PDT 24
Peak memory 183432 kb
Host smart-18584979-f445-4d9a-aca6-12666d4832fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321000336 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.3321000336
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.1812592945
Short name T334
Test name
Test status
Simulation time 374440811 ps
CPU time 1.07 seconds
Started Mar 21 12:24:35 PM PDT 24
Finished Mar 21 12:24:36 PM PDT 24
Peak memory 183472 kb
Host smart-bf2cacd2-2e3b-47f8-9281-fab0f779890b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812592945 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.1812592945
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.2872256503
Short name T412
Test name
Test status
Simulation time 317885533 ps
CPU time 0.65 seconds
Started Mar 21 12:24:42 PM PDT 24
Finished Mar 21 12:24:43 PM PDT 24
Peak memory 183452 kb
Host smart-a76cec31-afbf-473d-b35c-f1c7b78e1549
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872256503 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.2872256503
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.3155232333
Short name T328
Test name
Test status
Simulation time 275727119 ps
CPU time 0.96 seconds
Started Mar 21 12:24:38 PM PDT 24
Finished Mar 21 12:24:39 PM PDT 24
Peak memory 183644 kb
Host smart-8feb23c4-4aba-464c-9ef2-4d92f661b638
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155232333 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.3155232333
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.474088044
Short name T414
Test name
Test status
Simulation time 504921475 ps
CPU time 0.69 seconds
Started Mar 21 12:24:33 PM PDT 24
Finished Mar 21 12:24:34 PM PDT 24
Peak memory 183484 kb
Host smart-d4e70e7d-b423-475f-9ff1-7729ebf910aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474088044 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.474088044
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.2018358943
Short name T300
Test name
Test status
Simulation time 396355803 ps
CPU time 0.67 seconds
Started Mar 21 12:24:33 PM PDT 24
Finished Mar 21 12:24:34 PM PDT 24
Peak memory 183492 kb
Host smart-341b352d-d8ad-47a2-8363-e71c5f10e5f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018358943 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.2018358943
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.2859947151
Short name T356
Test name
Test status
Simulation time 450486232 ps
CPU time 0.61 seconds
Started Mar 21 12:24:28 PM PDT 24
Finished Mar 21 12:24:33 PM PDT 24
Peak memory 183500 kb
Host smart-ffd0eccb-2306-4302-be45-7452b24f3fec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859947151 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.2859947151
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.2382057914
Short name T369
Test name
Test status
Simulation time 404608088 ps
CPU time 0.84 seconds
Started Mar 21 12:24:08 PM PDT 24
Finished Mar 21 12:24:09 PM PDT 24
Peak memory 195300 kb
Host smart-ce71b302-b348-44f3-bec3-5e0c2a91058d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382057914 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.2382057914
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.665177716
Short name T59
Test name
Test status
Simulation time 475960303 ps
CPU time 0.81 seconds
Started Mar 21 12:24:02 PM PDT 24
Finished Mar 21 12:24:04 PM PDT 24
Peak memory 192184 kb
Host smart-2f6cf8d8-d31a-46fb-9370-e16bce95f8ec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665177716 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.665177716
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.2161397048
Short name T389
Test name
Test status
Simulation time 378354524 ps
CPU time 0.78 seconds
Started Mar 21 12:24:03 PM PDT 24
Finished Mar 21 12:24:04 PM PDT 24
Peak memory 182724 kb
Host smart-07776f59-3dc8-4f7e-b212-1146aec474f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161397048 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.2161397048
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.1295179176
Short name T415
Test name
Test status
Simulation time 1457371106 ps
CPU time 1.5 seconds
Started Mar 21 12:24:00 PM PDT 24
Finished Mar 21 12:24:02 PM PDT 24
Peak memory 193208 kb
Host smart-f6d5f88d-f7ac-4d13-b0ef-1a29277398b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295179176 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon
_timer_same_csr_outstanding.1295179176
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.1000594123
Short name T383
Test name
Test status
Simulation time 437869600 ps
CPU time 2.47 seconds
Started Mar 21 12:24:01 PM PDT 24
Finished Mar 21 12:24:04 PM PDT 24
Peak memory 197304 kb
Host smart-f0f3245e-97ca-48a9-87d4-e8a4aa55caa9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000594123 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.1000594123
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.2108096382
Short name T296
Test name
Test status
Simulation time 8423279367 ps
CPU time 2.25 seconds
Started Mar 21 12:24:19 PM PDT 24
Finished Mar 21 12:24:21 PM PDT 24
Peak memory 197904 kb
Host smart-384a7ee9-4f41-44c3-8a80-4a5bc75431c2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108096382 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl
_intg_err.2108096382
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.90054243
Short name T325
Test name
Test status
Simulation time 765932245 ps
CPU time 0.89 seconds
Started Mar 21 12:24:09 PM PDT 24
Finished Mar 21 12:24:10 PM PDT 24
Peak memory 197536 kb
Host smart-4cb180be-265a-4ae2-8307-891d1854cf3c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90054243 -assert nopostproc +UVM_TESTNAME=a
on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.90054243
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.3492746059
Short name T285
Test name
Test status
Simulation time 576073036 ps
CPU time 0.64 seconds
Started Mar 21 12:24:18 PM PDT 24
Finished Mar 21 12:24:18 PM PDT 24
Peak memory 183792 kb
Host smart-06c78a43-1be4-48ce-8581-67674af4cc61
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492746059 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.3492746059
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.1710527055
Short name T418
Test name
Test status
Simulation time 396431251 ps
CPU time 0.69 seconds
Started Mar 21 12:24:03 PM PDT 24
Finished Mar 21 12:24:04 PM PDT 24
Peak memory 183488 kb
Host smart-9460d707-3151-4105-bf87-c5321a148275
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710527055 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.1710527055
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.2183486585
Short name T324
Test name
Test status
Simulation time 2187861787 ps
CPU time 2 seconds
Started Mar 21 12:24:18 PM PDT 24
Finished Mar 21 12:24:20 PM PDT 24
Peak memory 194320 kb
Host smart-e88e48e0-0e38-4a17-8ae1-ccc5b7411238
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183486585 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon
_timer_same_csr_outstanding.2183486585
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.3018526739
Short name T373
Test name
Test status
Simulation time 614200515 ps
CPU time 1.42 seconds
Started Mar 21 12:24:08 PM PDT 24
Finished Mar 21 12:24:10 PM PDT 24
Peak memory 198220 kb
Host smart-a9763930-1caa-4c98-a92c-10d58d4e4457
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018526739 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.3018526739
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.2463083087
Short name T102
Test name
Test status
Simulation time 7594042772 ps
CPU time 7.3 seconds
Started Mar 21 12:24:03 PM PDT 24
Finished Mar 21 12:24:10 PM PDT 24
Peak memory 197124 kb
Host smart-9091d11f-e6ba-4b43-9fcc-4b313248852d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463083087 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl
_intg_err.2463083087
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.2891663621
Short name T280
Test name
Test status
Simulation time 525989231 ps
CPU time 0.83 seconds
Started Mar 21 12:24:13 PM PDT 24
Finished Mar 21 12:24:14 PM PDT 24
Peak memory 195580 kb
Host smart-f82339a4-424e-4eb7-bb0e-8fa1090660a2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891663621 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.2891663621
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.1163886677
Short name T358
Test name
Test status
Simulation time 468361452 ps
CPU time 1.23 seconds
Started Mar 21 12:24:11 PM PDT 24
Finished Mar 21 12:24:13 PM PDT 24
Peak memory 182288 kb
Host smart-fc075f24-50ae-4dab-a882-eaa0c6e7d303
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163886677 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.1163886677
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.367714728
Short name T332
Test name
Test status
Simulation time 359927086 ps
CPU time 0.62 seconds
Started Mar 21 12:24:10 PM PDT 24
Finished Mar 21 12:24:11 PM PDT 24
Peak memory 183480 kb
Host smart-76c6699a-aa0e-4980-98c1-db2adb964dd5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367714728 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.367714728
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.1969374220
Short name T68
Test name
Test status
Simulation time 1871379084 ps
CPU time 4.47 seconds
Started Mar 21 12:24:09 PM PDT 24
Finished Mar 21 12:24:14 PM PDT 24
Peak memory 183624 kb
Host smart-3f00bb0a-8d62-4a1d-a681-0339c7e0c8e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969374220 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon
_timer_same_csr_outstanding.1969374220
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.276479597
Short name T298
Test name
Test status
Simulation time 896979816 ps
CPU time 2.45 seconds
Started Mar 21 12:24:17 PM PDT 24
Finished Mar 21 12:24:20 PM PDT 24
Peak memory 198400 kb
Host smart-80a7ee3e-7228-45ba-a44d-9023a718f6f5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276479597 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.276479597
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.2904061682
Short name T321
Test name
Test status
Simulation time 8281279995 ps
CPU time 4.62 seconds
Started Mar 21 12:24:11 PM PDT 24
Finished Mar 21 12:24:16 PM PDT 24
Peak memory 196960 kb
Host smart-25000b0a-9f0f-4e48-ac56-1b94c97d94ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904061682 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl
_intg_err.2904061682
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.1139193819
Short name T399
Test name
Test status
Simulation time 504203418 ps
CPU time 0.71 seconds
Started Mar 21 12:24:18 PM PDT 24
Finished Mar 21 12:24:19 PM PDT 24
Peak memory 195312 kb
Host smart-56140539-1bc1-422b-b8a4-a7c05bed64d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139193819 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.1139193819
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.1843754047
Short name T62
Test name
Test status
Simulation time 397813345 ps
CPU time 0.81 seconds
Started Mar 21 12:24:19 PM PDT 24
Finished Mar 21 12:24:20 PM PDT 24
Peak memory 191900 kb
Host smart-18e63617-a0d9-4ea2-b498-df9005fc5e55
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843754047 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.1843754047
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.1795052717
Short name T375
Test name
Test status
Simulation time 418582216 ps
CPU time 0.57 seconds
Started Mar 21 12:24:17 PM PDT 24
Finished Mar 21 12:24:18 PM PDT 24
Peak memory 183444 kb
Host smart-e962a23a-3b4b-4148-a582-29e52c2c043c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795052717 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.1795052717
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.3603239476
Short name T319
Test name
Test status
Simulation time 1502035392 ps
CPU time 2.51 seconds
Started Mar 21 12:24:11 PM PDT 24
Finished Mar 21 12:24:14 PM PDT 24
Peak memory 193184 kb
Host smart-057f801d-6e48-4396-89d9-ac28d2b806b2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603239476 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon
_timer_same_csr_outstanding.3603239476
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.2923878851
Short name T376
Test name
Test status
Simulation time 457525041 ps
CPU time 1.3 seconds
Started Mar 21 12:24:16 PM PDT 24
Finished Mar 21 12:24:18 PM PDT 24
Peak memory 198332 kb
Host smart-5f9e193b-3f04-458d-be81-592b83c1686c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923878851 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.2923878851
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.59514590
Short name T287
Test name
Test status
Simulation time 9225062984 ps
CPU time 13.29 seconds
Started Mar 21 12:24:17 PM PDT 24
Finished Mar 21 12:24:30 PM PDT 24
Peak memory 198032 kb
Host smart-1ed2e62c-ecf7-4e6a-b870-8cdfb671f4d3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59514590 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_i
ntg_err.59514590
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.3187152477
Short name T397
Test name
Test status
Simulation time 679910708 ps
CPU time 0.74 seconds
Started Mar 21 12:24:09 PM PDT 24
Finished Mar 21 12:24:10 PM PDT 24
Peak memory 195332 kb
Host smart-be561627-d2a3-417e-95db-15b66086253f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187152477 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.3187152477
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.3483851944
Short name T61
Test name
Test status
Simulation time 458685376 ps
CPU time 1.31 seconds
Started Mar 21 12:24:17 PM PDT 24
Finished Mar 21 12:24:20 PM PDT 24
Peak memory 191744 kb
Host smart-fd631328-b13a-406b-b8d7-e18b7fd8296d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483851944 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.3483851944
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.2741558337
Short name T394
Test name
Test status
Simulation time 384798289 ps
CPU time 0.82 seconds
Started Mar 21 12:24:12 PM PDT 24
Finished Mar 21 12:24:13 PM PDT 24
Peak memory 183484 kb
Host smart-0c32e6f6-63a0-42b1-a877-6be8375159a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741558337 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.2741558337
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.2851311035
Short name T69
Test name
Test status
Simulation time 1330760183 ps
CPU time 1.53 seconds
Started Mar 21 12:24:10 PM PDT 24
Finished Mar 21 12:24:13 PM PDT 24
Peak memory 192308 kb
Host smart-07d76ab4-ca77-44d0-a4b4-a23381f3a2cf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851311035 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon
_timer_same_csr_outstanding.2851311035
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.1833431187
Short name T346
Test name
Test status
Simulation time 522590743 ps
CPU time 2 seconds
Started Mar 21 12:24:12 PM PDT 24
Finished Mar 21 12:24:14 PM PDT 24
Peak memory 198340 kb
Host smart-870e8ef3-63d3-454c-a051-b6e4b8a44793
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833431187 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.1833431187
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.2503145295
Short name T354
Test name
Test status
Simulation time 4045182800 ps
CPU time 2.21 seconds
Started Mar 21 12:24:16 PM PDT 24
Finished Mar 21 12:24:19 PM PDT 24
Peak memory 196060 kb
Host smart-0d32c38d-6d3e-457e-b771-0371c744a32e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503145295 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl
_intg_err.2503145295
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_jump.2105563029
Short name T232
Test name
Test status
Simulation time 435838855 ps
CPU time 0.69 seconds
Started Mar 21 12:37:56 PM PDT 24
Finished Mar 21 12:37:59 PM PDT 24
Peak memory 182880 kb
Host smart-7a501bbb-0292-4770-ab58-8816dc198864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105563029 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.2105563029
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.3734398378
Short name T96
Test name
Test status
Simulation time 20833613922 ps
CPU time 30.39 seconds
Started Mar 21 12:38:00 PM PDT 24
Finished Mar 21 12:38:31 PM PDT 24
Peak memory 182956 kb
Host smart-da9ce04c-7e83-4695-a33a-6e30975e7a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734398378 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.3734398378
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.3933787257
Short name T182
Test name
Test status
Simulation time 489613153 ps
CPU time 1.28 seconds
Started Mar 21 12:37:49 PM PDT 24
Finished Mar 21 12:37:51 PM PDT 24
Peak memory 182992 kb
Host smart-25be5b91-48c0-4d63-8e4d-5f1b79189eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933787257 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.3933787257
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.1548713102
Short name T40
Test name
Test status
Simulation time 123382395329 ps
CPU time 81.63 seconds
Started Mar 21 12:37:53 PM PDT 24
Finished Mar 21 12:39:15 PM PDT 24
Peak memory 182956 kb
Host smart-a368d7f1-7964-42e6-8259-31aed6ccb965
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548713102 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_a
ll.1548713102
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.3561140109
Short name T215
Test name
Test status
Simulation time 110610408598 ps
CPU time 453.61 seconds
Started Mar 21 12:37:55 PM PDT 24
Finished Mar 21 12:45:29 PM PDT 24
Peak memory 197912 kb
Host smart-b314e3b7-e3ef-4707-96b9-686dd6a66631
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561140109 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.3561140109
Directory /workspace/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.aon_timer_jump.3372566255
Short name T229
Test name
Test status
Simulation time 493891408 ps
CPU time 0.71 seconds
Started Mar 21 12:37:54 PM PDT 24
Finished Mar 21 12:37:55 PM PDT 24
Peak memory 182896 kb
Host smart-2afbbabb-5e65-4a9c-96b5-651ce35031c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372566255 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.3372566255
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.2965978600
Short name T236
Test name
Test status
Simulation time 59327239795 ps
CPU time 39.38 seconds
Started Mar 21 12:38:03 PM PDT 24
Finished Mar 21 12:38:43 PM PDT 24
Peak memory 183024 kb
Host smart-045a8a7f-1d91-4e43-a9ce-7c01a922fd88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965978600 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.2965978600
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.2628866932
Short name T21
Test name
Test status
Simulation time 4469458486 ps
CPU time 1.83 seconds
Started Mar 21 12:37:57 PM PDT 24
Finished Mar 21 12:38:00 PM PDT 24
Peak memory 214680 kb
Host smart-4729dde6-2bf8-4a88-8d4b-9302b29a475b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628866932 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.2628866932
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.4131411237
Short name T252
Test name
Test status
Simulation time 442492514 ps
CPU time 0.86 seconds
Started Mar 21 12:38:02 PM PDT 24
Finished Mar 21 12:38:03 PM PDT 24
Peak memory 183048 kb
Host smart-704dd54b-d2af-4f3c-8c6e-0b196daaaa8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131411237 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.4131411237
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.1903587969
Short name T98
Test name
Test status
Simulation time 149146121781 ps
CPU time 64.05 seconds
Started Mar 21 12:38:18 PM PDT 24
Finished Mar 21 12:39:23 PM PDT 24
Peak memory 183160 kb
Host smart-3505bbf3-5341-4440-82c7-3da68cc38124
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903587969 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_a
ll.1903587969
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/10.aon_timer_jump.865460223
Short name T49
Test name
Test status
Simulation time 452530166 ps
CPU time 1.34 seconds
Started Mar 21 12:38:01 PM PDT 24
Finished Mar 21 12:38:02 PM PDT 24
Peak memory 182856 kb
Host smart-8d40b354-0917-494c-9830-919d481cfb56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865460223 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.865460223
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.2776980710
Short name T97
Test name
Test status
Simulation time 23103827560 ps
CPU time 9.88 seconds
Started Mar 21 12:38:05 PM PDT 24
Finished Mar 21 12:38:15 PM PDT 24
Peak memory 182956 kb
Host smart-48f77b7c-0893-4ca1-a43a-dfbb0f6d93c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776980710 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.2776980710
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.139603470
Short name T259
Test name
Test status
Simulation time 539806821 ps
CPU time 1.35 seconds
Started Mar 21 12:37:59 PM PDT 24
Finished Mar 21 12:38:01 PM PDT 24
Peak memory 182876 kb
Host smart-5438ffe4-0491-49c2-b25f-7312f2a88cc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139603470 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.139603470
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.2282047282
Short name T42
Test name
Test status
Simulation time 133355987764 ps
CPU time 114.46 seconds
Started Mar 21 12:38:03 PM PDT 24
Finished Mar 21 12:39:58 PM PDT 24
Peak memory 194660 kb
Host smart-6e31ba04-d1fe-401c-91cb-446d63876468
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282047282 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_
all.2282047282
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.2128619508
Short name T88
Test name
Test status
Simulation time 80911347935 ps
CPU time 191.52 seconds
Started Mar 21 12:37:50 PM PDT 24
Finished Mar 21 12:41:01 PM PDT 24
Peak memory 213916 kb
Host smart-c1024022-8ea4-41d8-99e1-1ce6278b85c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128619508 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.2128619508
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.aon_timer_jump.981193628
Short name T168
Test name
Test status
Simulation time 602985590 ps
CPU time 0.62 seconds
Started Mar 21 12:38:11 PM PDT 24
Finished Mar 21 12:38:12 PM PDT 24
Peak memory 182896 kb
Host smart-f8bad5c2-6947-4750-aa72-81a6b73e56ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981193628 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.981193628
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.2244843277
Short name T220
Test name
Test status
Simulation time 45041972269 ps
CPU time 50.76 seconds
Started Mar 21 12:38:01 PM PDT 24
Finished Mar 21 12:38:51 PM PDT 24
Peak memory 182904 kb
Host smart-054b0f81-825c-421f-8f16-450fbe3c29e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244843277 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.2244843277
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.1105239165
Short name T231
Test name
Test status
Simulation time 440007860 ps
CPU time 0.8 seconds
Started Mar 21 12:38:15 PM PDT 24
Finished Mar 21 12:38:16 PM PDT 24
Peak memory 182976 kb
Host smart-1e89da20-97a0-46ba-b17a-293f46bdca27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105239165 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.1105239165
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.2538382149
Short name T211
Test name
Test status
Simulation time 126404305904 ps
CPU time 41.15 seconds
Started Mar 21 12:38:04 PM PDT 24
Finished Mar 21 12:38:45 PM PDT 24
Peak memory 194556 kb
Host smart-2d70ef1f-fdf0-49cc-a303-64d9d491b7f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538382149 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_
all.2538382149
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.1212428038
Short name T263
Test name
Test status
Simulation time 86238611478 ps
CPU time 578.18 seconds
Started Mar 21 12:38:23 PM PDT 24
Finished Mar 21 12:48:01 PM PDT 24
Peak memory 206468 kb
Host smart-33f1c762-0133-43cd-b12d-46555183e88b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212428038 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand_reset.1212428038
Directory /workspace/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.aon_timer_jump.204082702
Short name T115
Test name
Test status
Simulation time 587226675 ps
CPU time 0.98 seconds
Started Mar 21 12:38:05 PM PDT 24
Finished Mar 21 12:38:06 PM PDT 24
Peak memory 182900 kb
Host smart-2890fdc5-2022-4c33-80af-365ec2b980fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204082702 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.204082702
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.1208892312
Short name T99
Test name
Test status
Simulation time 51547229879 ps
CPU time 19.09 seconds
Started Mar 21 12:38:03 PM PDT 24
Finished Mar 21 12:38:22 PM PDT 24
Peak memory 182920 kb
Host smart-14c105e5-116e-460c-a3e3-ecde1e629a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208892312 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.1208892312
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.1656569227
Short name T151
Test name
Test status
Simulation time 527437398 ps
CPU time 1.34 seconds
Started Mar 21 12:38:08 PM PDT 24
Finished Mar 21 12:38:09 PM PDT 24
Peak memory 182916 kb
Host smart-9a568273-dedf-4b79-8552-01617491e4f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656569227 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.1656569227
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.821207167
Short name T253
Test name
Test status
Simulation time 81589786106 ps
CPU time 33.32 seconds
Started Mar 21 12:38:23 PM PDT 24
Finished Mar 21 12:38:57 PM PDT 24
Peak memory 194716 kb
Host smart-e3ed39ec-930f-4083-a4f3-2219cc67b4f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821207167 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_a
ll.821207167
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.1755443941
Short name T93
Test name
Test status
Simulation time 40080926761 ps
CPU time 156.87 seconds
Started Mar 21 12:38:14 PM PDT 24
Finished Mar 21 12:40:51 PM PDT 24
Peak memory 197880 kb
Host smart-d5817b9a-9b1f-456d-bf99-f3989bcd5e43
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755443941 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.1755443941
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_jump.261383718
Short name T172
Test name
Test status
Simulation time 531104206 ps
CPU time 1.4 seconds
Started Mar 21 12:38:10 PM PDT 24
Finished Mar 21 12:38:12 PM PDT 24
Peak memory 182856 kb
Host smart-cb84131a-b209-4133-b835-6f00771ef93c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261383718 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.261383718
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.3776890304
Short name T237
Test name
Test status
Simulation time 38532617369 ps
CPU time 14.13 seconds
Started Mar 21 12:38:03 PM PDT 24
Finished Mar 21 12:38:17 PM PDT 24
Peak memory 182956 kb
Host smart-2695c87c-2511-4f52-a441-f1462a04c033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776890304 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.3776890304
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.3626376742
Short name T131
Test name
Test status
Simulation time 411194469 ps
CPU time 1.15 seconds
Started Mar 21 12:38:04 PM PDT 24
Finished Mar 21 12:38:06 PM PDT 24
Peak memory 182892 kb
Host smart-22385dbc-5495-4362-8b63-d7edff377462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626376742 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.3626376742
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.3810784136
Short name T199
Test name
Test status
Simulation time 221168963287 ps
CPU time 164.37 seconds
Started Mar 21 12:37:59 PM PDT 24
Finished Mar 21 12:40:43 PM PDT 24
Peak memory 182964 kb
Host smart-9155cb96-efba-4d40-a9b3-d186d4d48944
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810784136 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_
all.3810784136
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.595419785
Short name T257
Test name
Test status
Simulation time 20472995583 ps
CPU time 213.6 seconds
Started Mar 21 12:38:16 PM PDT 24
Finished Mar 21 12:41:50 PM PDT 24
Peak memory 197876 kb
Host smart-d28cfdef-4aac-4e00-80f4-17ef08a5378c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595419785 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.595419785
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.aon_timer_jump.2573829503
Short name T136
Test name
Test status
Simulation time 516198916 ps
CPU time 1.31 seconds
Started Mar 21 12:38:11 PM PDT 24
Finished Mar 21 12:38:12 PM PDT 24
Peak memory 182844 kb
Host smart-0b5421cf-b291-47f0-b119-bf0062d2760d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573829503 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.2573829503
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.1941455304
Short name T230
Test name
Test status
Simulation time 34611157142 ps
CPU time 26.75 seconds
Started Mar 21 12:38:22 PM PDT 24
Finished Mar 21 12:38:50 PM PDT 24
Peak memory 182924 kb
Host smart-d9c754ac-4821-4fe5-897e-b0b2cc5be51f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941455304 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.1941455304
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.3336709175
Short name T202
Test name
Test status
Simulation time 521018114 ps
CPU time 1.32 seconds
Started Mar 21 12:38:11 PM PDT 24
Finished Mar 21 12:38:12 PM PDT 24
Peak memory 182888 kb
Host smart-a8bcddec-2c7e-4920-a6e4-f1343b061c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336709175 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.3336709175
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.1354657235
Short name T27
Test name
Test status
Simulation time 4278270475 ps
CPU time 1.9 seconds
Started Mar 21 12:38:01 PM PDT 24
Finished Mar 21 12:38:03 PM PDT 24
Peak memory 193772 kb
Host smart-89e3a42b-978a-48b0-82d6-9f478573e846
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354657235 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_
all.1354657235
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.864833217
Short name T87
Test name
Test status
Simulation time 313425410888 ps
CPU time 662.87 seconds
Started Mar 21 12:38:01 PM PDT 24
Finished Mar 21 12:49:04 PM PDT 24
Peak memory 200320 kb
Host smart-70aaffca-1abf-448f-be2f-f4d93afe7576
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864833217 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.864833217
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.aon_timer_jump.1850118294
Short name T204
Test name
Test status
Simulation time 427618004 ps
CPU time 0.87 seconds
Started Mar 21 12:38:21 PM PDT 24
Finished Mar 21 12:38:22 PM PDT 24
Peak memory 182844 kb
Host smart-2a5c24d2-24f0-4d12-a7e9-0c76b6fd6870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850118294 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.1850118294
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.1238581656
Short name T235
Test name
Test status
Simulation time 8914368125 ps
CPU time 4.34 seconds
Started Mar 21 12:38:00 PM PDT 24
Finished Mar 21 12:38:05 PM PDT 24
Peak memory 182920 kb
Host smart-113f1c89-aeaa-4766-b967-ebf81530d2aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238581656 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.1238581656
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.2206282451
Short name T187
Test name
Test status
Simulation time 490150987 ps
CPU time 0.73 seconds
Started Mar 21 12:38:02 PM PDT 24
Finished Mar 21 12:38:02 PM PDT 24
Peak memory 182980 kb
Host smart-07ff670f-5f64-4865-8533-2e80216cc767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206282451 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.2206282451
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.3666131258
Short name T30
Test name
Test status
Simulation time 259974991967 ps
CPU time 556.6 seconds
Started Mar 21 12:38:35 PM PDT 24
Finished Mar 21 12:47:52 PM PDT 24
Peak memory 198248 kb
Host smart-2d07b968-2b3e-4c51-8a54-874ef9561d30
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666131258 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.3666131258
Directory /workspace/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.aon_timer_jump.1802471245
Short name T273
Test name
Test status
Simulation time 523724440 ps
CPU time 0.9 seconds
Started Mar 21 12:38:06 PM PDT 24
Finished Mar 21 12:38:07 PM PDT 24
Peak memory 182924 kb
Host smart-a255068a-653d-4700-a8f1-780a7c6b166a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802471245 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.1802471245
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.3877720517
Short name T105
Test name
Test status
Simulation time 32245172326 ps
CPU time 26.76 seconds
Started Mar 21 12:38:08 PM PDT 24
Finished Mar 21 12:38:35 PM PDT 24
Peak memory 182964 kb
Host smart-fbf8d773-1e32-4e00-8e13-d965e82239bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877720517 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.3877720517
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.2267243543
Short name T270
Test name
Test status
Simulation time 524725257 ps
CPU time 0.88 seconds
Started Mar 21 12:38:09 PM PDT 24
Finished Mar 21 12:38:09 PM PDT 24
Peak memory 182908 kb
Host smart-a44c69ce-b7c5-4c2f-8c6b-01b839c55f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267243543 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.2267243543
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.2725166859
Short name T122
Test name
Test status
Simulation time 77712483952 ps
CPU time 7.2 seconds
Started Mar 21 12:38:20 PM PDT 24
Finished Mar 21 12:38:28 PM PDT 24
Peak memory 182912 kb
Host smart-6dab6ccd-5559-4dc4-8769-39fb5a37199e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725166859 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_
all.2725166859
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.138117961
Short name T207
Test name
Test status
Simulation time 38770402507 ps
CPU time 307.14 seconds
Started Mar 21 12:38:06 PM PDT 24
Finished Mar 21 12:43:13 PM PDT 24
Peak memory 197772 kb
Host smart-85120057-3bd5-41d0-b37f-9fdcf455987b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138117961 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.138117961
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.aon_timer_jump.218180686
Short name T265
Test name
Test status
Simulation time 557099888 ps
CPU time 0.99 seconds
Started Mar 21 12:38:01 PM PDT 24
Finished Mar 21 12:38:02 PM PDT 24
Peak memory 182848 kb
Host smart-527f6271-feed-4edf-92ef-ebb1849560b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218180686 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.218180686
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.2184189390
Short name T267
Test name
Test status
Simulation time 2399219046 ps
CPU time 1.5 seconds
Started Mar 21 12:38:06 PM PDT 24
Finished Mar 21 12:38:08 PM PDT 24
Peak memory 182980 kb
Host smart-2288d3d2-af81-47e7-aa82-7518e07ccba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184189390 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.2184189390
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.420594719
Short name T228
Test name
Test status
Simulation time 606883257 ps
CPU time 0.69 seconds
Started Mar 21 12:38:02 PM PDT 24
Finished Mar 21 12:38:03 PM PDT 24
Peak memory 182976 kb
Host smart-12381fc7-0b07-457b-aa7c-2b6269e38da6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420594719 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.420594719
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.1176880765
Short name T233
Test name
Test status
Simulation time 25783791197 ps
CPU time 6.02 seconds
Started Mar 21 12:38:05 PM PDT 24
Finished Mar 21 12:38:11 PM PDT 24
Peak memory 194724 kb
Host smart-9397004d-360a-4d81-9382-71616d10722e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176880765 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_
all.1176880765
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.2956140782
Short name T268
Test name
Test status
Simulation time 63094777840 ps
CPU time 143.96 seconds
Started Mar 21 12:38:00 PM PDT 24
Finished Mar 21 12:40:24 PM PDT 24
Peak memory 197872 kb
Host smart-dd483c4b-5bdb-4dc5-a781-9314d8c4e594
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956140782 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.2956140782
Directory /workspace/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.aon_timer_jump.2767312382
Short name T193
Test name
Test status
Simulation time 343061556 ps
CPU time 1.1 seconds
Started Mar 21 12:38:06 PM PDT 24
Finished Mar 21 12:38:07 PM PDT 24
Peak memory 182924 kb
Host smart-1d1d4f73-98ef-4e58-886e-5ee9fcb39867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767312382 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.2767312382
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.3914467397
Short name T141
Test name
Test status
Simulation time 13306950011 ps
CPU time 4.51 seconds
Started Mar 21 12:38:02 PM PDT 24
Finished Mar 21 12:38:06 PM PDT 24
Peak memory 182908 kb
Host smart-657d6b77-5557-4de5-b2d5-db5c97c36fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914467397 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.3914467397
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.1418289598
Short name T4
Test name
Test status
Simulation time 354541418 ps
CPU time 0.67 seconds
Started Mar 21 12:38:13 PM PDT 24
Finished Mar 21 12:38:14 PM PDT 24
Peak memory 182844 kb
Host smart-433a6fc1-5773-452e-9c82-9bb161cb2d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418289598 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.1418289598
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.719419317
Short name T17
Test name
Test status
Simulation time 56927551252 ps
CPU time 325.59 seconds
Started Mar 21 12:38:25 PM PDT 24
Finished Mar 21 12:43:51 PM PDT 24
Peak memory 197828 kb
Host smart-2a0b0b29-f914-4436-94ab-4f905726f988
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719419317 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.719419317
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.aon_timer_jump.4277334598
Short name T118
Test name
Test status
Simulation time 448779780 ps
CPU time 0.57 seconds
Started Mar 21 12:38:13 PM PDT 24
Finished Mar 21 12:38:14 PM PDT 24
Peak memory 182880 kb
Host smart-c53440e2-a581-4ef9-8c03-c2e7c29c8a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277334598 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.4277334598
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.2695386826
Short name T190
Test name
Test status
Simulation time 18829502778 ps
CPU time 14.6 seconds
Started Mar 21 12:38:20 PM PDT 24
Finished Mar 21 12:38:34 PM PDT 24
Peak memory 182932 kb
Host smart-dc34eaf6-a030-439a-8132-8307d433817e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695386826 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.2695386826
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.1836005028
Short name T256
Test name
Test status
Simulation time 560445202 ps
CPU time 0.72 seconds
Started Mar 21 12:38:07 PM PDT 24
Finished Mar 21 12:38:08 PM PDT 24
Peak memory 182856 kb
Host smart-d25f936f-c33c-4dac-854e-e5a2e12f9a4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836005028 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.1836005028
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.2346503839
Short name T183
Test name
Test status
Simulation time 143107975864 ps
CPU time 232.71 seconds
Started Mar 21 12:38:09 PM PDT 24
Finished Mar 21 12:42:02 PM PDT 24
Peak memory 193892 kb
Host smart-aa4d1bc2-997b-47a0-bcf1-04f3dc05f90b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346503839 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_
all.2346503839
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_jump.2484799334
Short name T130
Test name
Test status
Simulation time 434961848 ps
CPU time 1.15 seconds
Started Mar 21 12:37:51 PM PDT 24
Finished Mar 21 12:37:52 PM PDT 24
Peak memory 182968 kb
Host smart-0626c92f-24dc-4b24-9d38-d8c54c853553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484799334 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.2484799334
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.2622410969
Short name T9
Test name
Test status
Simulation time 8539274898 ps
CPU time 1.31 seconds
Started Mar 21 12:37:48 PM PDT 24
Finished Mar 21 12:37:50 PM PDT 24
Peak memory 182892 kb
Host smart-cc223598-d6f0-41a3-89b2-49dac5d6a61b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622410969 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.2622410969
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.903194790
Short name T18
Test name
Test status
Simulation time 3884248130 ps
CPU time 2.33 seconds
Started Mar 21 12:37:59 PM PDT 24
Finished Mar 21 12:38:01 PM PDT 24
Peak memory 214384 kb
Host smart-22264f23-98b3-4858-be57-3eef9f0261e0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903194790 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.903194790
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.3551811300
Short name T150
Test name
Test status
Simulation time 509592949 ps
CPU time 0.75 seconds
Started Mar 21 12:37:48 PM PDT 24
Finished Mar 21 12:37:49 PM PDT 24
Peak memory 182900 kb
Host smart-9665c246-2e08-4e46-9f13-1db7de2ffc5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551811300 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.3551811300
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.3978189528
Short name T161
Test name
Test status
Simulation time 5253914941 ps
CPU time 1.2 seconds
Started Mar 21 12:38:07 PM PDT 24
Finished Mar 21 12:38:09 PM PDT 24
Peak memory 182940 kb
Host smart-a851ddc2-146c-4a7c-9e30-cb32354cc7a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978189528 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_a
ll.3978189528
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.833217711
Short name T209
Test name
Test status
Simulation time 319443756595 ps
CPU time 844.27 seconds
Started Mar 21 12:37:58 PM PDT 24
Finished Mar 21 12:52:03 PM PDT 24
Peak memory 201900 kb
Host smart-aaee83e3-6eb1-4c17-9683-d52ce7dd99b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833217711 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.833217711
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.aon_timer_jump.3516735182
Short name T189
Test name
Test status
Simulation time 543384874 ps
CPU time 1.37 seconds
Started Mar 21 12:38:12 PM PDT 24
Finished Mar 21 12:38:14 PM PDT 24
Peak memory 182896 kb
Host smart-c2203374-979a-4622-af5f-b7995e4153b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516735182 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.3516735182
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.3534974986
Short name T1
Test name
Test status
Simulation time 22722061213 ps
CPU time 3.31 seconds
Started Mar 21 12:38:20 PM PDT 24
Finished Mar 21 12:38:23 PM PDT 24
Peak memory 182940 kb
Host smart-0a450f57-8025-4bb4-8d82-343a965e75f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534974986 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.3534974986
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.2097730076
Short name T54
Test name
Test status
Simulation time 553177191 ps
CPU time 1.34 seconds
Started Mar 21 12:38:04 PM PDT 24
Finished Mar 21 12:38:05 PM PDT 24
Peak memory 182836 kb
Host smart-437d207e-5be0-44f7-8344-5b09852b6d42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097730076 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.2097730076
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.4158305323
Short name T272
Test name
Test status
Simulation time 87749256840 ps
CPU time 32.3 seconds
Started Mar 21 12:38:18 PM PDT 24
Finished Mar 21 12:38:52 PM PDT 24
Peak memory 192656 kb
Host smart-fd9e391f-66c5-488a-ae52-b2efe9febe2a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158305323 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_
all.4158305323
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.2653158912
Short name T137
Test name
Test status
Simulation time 10280207471 ps
CPU time 80.91 seconds
Started Mar 21 12:38:10 PM PDT 24
Finished Mar 21 12:39:31 PM PDT 24
Peak memory 197820 kb
Host smart-8a141cde-6f8d-4b0c-9bd4-f413d3973fc4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653158912 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.2653158912
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_jump.3622054457
Short name T48
Test name
Test status
Simulation time 412891763 ps
CPU time 0.91 seconds
Started Mar 21 12:38:07 PM PDT 24
Finished Mar 21 12:38:08 PM PDT 24
Peak memory 182788 kb
Host smart-5236c2d0-b92b-4152-ae25-263a3770ccad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622054457 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.3622054457
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.2921767467
Short name T50
Test name
Test status
Simulation time 17231004659 ps
CPU time 7.61 seconds
Started Mar 21 12:38:13 PM PDT 24
Finished Mar 21 12:38:21 PM PDT 24
Peak memory 182852 kb
Host smart-18feaff6-f6fb-4471-9f3b-579c98bfaa2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921767467 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.2921767467
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.3000889376
Short name T258
Test name
Test status
Simulation time 567973750 ps
CPU time 1.44 seconds
Started Mar 21 12:38:10 PM PDT 24
Finished Mar 21 12:38:12 PM PDT 24
Peak memory 182788 kb
Host smart-e9077b40-8223-4599-8575-126f9ab08fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000889376 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.3000889376
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.535413279
Short name T274
Test name
Test status
Simulation time 364728380326 ps
CPU time 524.18 seconds
Started Mar 21 12:38:08 PM PDT 24
Finished Mar 21 12:46:52 PM PDT 24
Peak memory 192548 kb
Host smart-f1ef2a54-264c-46f3-b6e7-715b0f394c98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535413279 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_a
ll.535413279
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.498839829
Short name T91
Test name
Test status
Simulation time 16083913529 ps
CPU time 59.27 seconds
Started Mar 21 12:38:17 PM PDT 24
Finished Mar 21 12:39:18 PM PDT 24
Peak memory 197880 kb
Host smart-3b9c6382-b140-4856-b037-9dc2cfc0ed33
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498839829 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.498839829
Directory /workspace/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.aon_timer_jump.670482826
Short name T247
Test name
Test status
Simulation time 359980333 ps
CPU time 0.67 seconds
Started Mar 21 12:38:13 PM PDT 24
Finished Mar 21 12:38:14 PM PDT 24
Peak memory 182888 kb
Host smart-e39ed65a-874f-4b5e-865d-962cc68c8ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670482826 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.670482826
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.3979439683
Short name T22
Test name
Test status
Simulation time 8742776838 ps
CPU time 3.05 seconds
Started Mar 21 12:38:12 PM PDT 24
Finished Mar 21 12:38:15 PM PDT 24
Peak memory 182956 kb
Host smart-97fd73c9-f20c-4ccc-aaed-a494d070475b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979439683 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.3979439683
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.3088370465
Short name T198
Test name
Test status
Simulation time 528565877 ps
CPU time 0.7 seconds
Started Mar 21 12:38:11 PM PDT 24
Finished Mar 21 12:38:12 PM PDT 24
Peak memory 182884 kb
Host smart-fcb96cc8-d22a-4467-b656-7c7e8bcfa52f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088370465 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.3088370465
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.2334962319
Short name T12
Test name
Test status
Simulation time 320851312665 ps
CPU time 113.93 seconds
Started Mar 21 12:38:18 PM PDT 24
Finished Mar 21 12:40:13 PM PDT 24
Peak memory 193088 kb
Host smart-2f44e911-24b6-4d81-8320-93dec843e969
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334962319 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_
all.2334962319
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.1508078023
Short name T45
Test name
Test status
Simulation time 18360200121 ps
CPU time 146.52 seconds
Started Mar 21 12:38:16 PM PDT 24
Finished Mar 21 12:40:43 PM PDT 24
Peak memory 197708 kb
Host smart-238b0fbe-b3f5-42a7-98ab-b5aa43dcc128
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508078023 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.1508078023
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.aon_timer_jump.3754581640
Short name T212
Test name
Test status
Simulation time 344489602 ps
CPU time 0.83 seconds
Started Mar 21 12:38:18 PM PDT 24
Finished Mar 21 12:38:20 PM PDT 24
Peak memory 182728 kb
Host smart-9d7e70b3-2084-4b34-a107-052e977ec3c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754581640 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.3754581640
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.4161089603
Short name T249
Test name
Test status
Simulation time 20597733708 ps
CPU time 6.48 seconds
Started Mar 21 12:37:59 PM PDT 24
Finished Mar 21 12:38:06 PM PDT 24
Peak memory 182948 kb
Host smart-3f96f534-68e5-4f19-9c17-1a3c8cdac112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161089603 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.4161089603
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.2798767658
Short name T158
Test name
Test status
Simulation time 615673863 ps
CPU time 0.67 seconds
Started Mar 21 12:38:10 PM PDT 24
Finished Mar 21 12:38:11 PM PDT 24
Peak memory 182888 kb
Host smart-47c1c487-c3fb-4b4c-8903-90ac98ee9bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798767658 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.2798767658
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.2094948953
Short name T14
Test name
Test status
Simulation time 132806594374 ps
CPU time 75.25 seconds
Started Mar 21 12:38:12 PM PDT 24
Finished Mar 21 12:39:28 PM PDT 24
Peak memory 182960 kb
Host smart-0b5b838d-07c5-4ce3-aaa1-fa04b1043cbd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094948953 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_
all.2094948953
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_jump.847817930
Short name T117
Test name
Test status
Simulation time 625154105 ps
CPU time 1.1 seconds
Started Mar 21 12:38:14 PM PDT 24
Finished Mar 21 12:38:16 PM PDT 24
Peak memory 182888 kb
Host smart-d51c404e-40aa-45ce-8e6f-dc303a64b0a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847817930 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.847817930
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.225702000
Short name T173
Test name
Test status
Simulation time 33386421689 ps
CPU time 49.01 seconds
Started Mar 21 12:38:20 PM PDT 24
Finished Mar 21 12:39:09 PM PDT 24
Peak memory 182952 kb
Host smart-573b0898-ca36-40ad-9fac-da073fbd04f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225702000 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.225702000
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.4022607898
Short name T245
Test name
Test status
Simulation time 532891559 ps
CPU time 0.71 seconds
Started Mar 21 12:38:18 PM PDT 24
Finished Mar 21 12:38:20 PM PDT 24
Peak memory 182728 kb
Host smart-6afbf4c8-bbc9-4c1d-8323-8f61a9d3e3e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022607898 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.4022607898
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.2368565833
Short name T244
Test name
Test status
Simulation time 75353104538 ps
CPU time 115.11 seconds
Started Mar 21 12:38:13 PM PDT 24
Finished Mar 21 12:40:08 PM PDT 24
Peak memory 182916 kb
Host smart-06411218-e66e-4ad9-9bb8-3d20952b39bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368565833 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_
all.2368565833
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/25.aon_timer_jump.1953242488
Short name T179
Test name
Test status
Simulation time 426757978 ps
CPU time 0.84 seconds
Started Mar 21 12:38:16 PM PDT 24
Finished Mar 21 12:38:17 PM PDT 24
Peak memory 182852 kb
Host smart-9de47bca-10a6-43a7-a7de-0f74c6cdd555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953242488 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.1953242488
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.2994651518
Short name T208
Test name
Test status
Simulation time 33721091399 ps
CPU time 27.17 seconds
Started Mar 21 12:38:18 PM PDT 24
Finished Mar 21 12:38:46 PM PDT 24
Peak memory 182904 kb
Host smart-bc721606-c04f-44b5-81e6-996d3b2ea805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994651518 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.2994651518
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.2946506761
Short name T261
Test name
Test status
Simulation time 527329677 ps
CPU time 1.37 seconds
Started Mar 21 12:38:05 PM PDT 24
Finished Mar 21 12:38:12 PM PDT 24
Peak memory 182844 kb
Host smart-7339b8df-3450-43ec-8c9d-6b6d2f3a3238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946506761 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.2946506761
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.494865643
Short name T166
Test name
Test status
Simulation time 194964838541 ps
CPU time 339.98 seconds
Started Mar 21 12:38:18 PM PDT 24
Finished Mar 21 12:43:59 PM PDT 24
Peak memory 182916 kb
Host smart-c0f216c6-d793-468c-bf67-04d2df65896d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494865643 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_a
ll.494865643
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.579968582
Short name T144
Test name
Test status
Simulation time 24197735808 ps
CPU time 190.92 seconds
Started Mar 21 12:37:58 PM PDT 24
Finished Mar 21 12:41:09 PM PDT 24
Peak memory 197804 kb
Host smart-1524613e-04a6-4202-aabe-eed401a1c5de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579968582 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.579968582
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.aon_timer_jump.68949606
Short name T194
Test name
Test status
Simulation time 495500096 ps
CPU time 0.88 seconds
Started Mar 21 12:38:05 PM PDT 24
Finished Mar 21 12:38:06 PM PDT 24
Peak memory 182888 kb
Host smart-3603bb08-34b9-4891-8f94-23729e99fac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68949606 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.68949606
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.2295499406
Short name T195
Test name
Test status
Simulation time 54635810476 ps
CPU time 37.04 seconds
Started Mar 21 12:38:07 PM PDT 24
Finished Mar 21 12:38:44 PM PDT 24
Peak memory 182928 kb
Host smart-8f879b97-3efa-4e56-9caf-0077dab55522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295499406 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.2295499406
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.2387743248
Short name T234
Test name
Test status
Simulation time 589179173 ps
CPU time 0.7 seconds
Started Mar 21 12:38:11 PM PDT 24
Finished Mar 21 12:38:12 PM PDT 24
Peak memory 182884 kb
Host smart-14627a74-fcb4-477c-9c8f-2802a2463e33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387743248 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.2387743248
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.2575655202
Short name T95
Test name
Test status
Simulation time 317661271138 ps
CPU time 393.52 seconds
Started Mar 21 12:38:06 PM PDT 24
Finished Mar 21 12:44:39 PM PDT 24
Peak memory 197808 kb
Host smart-2bfc02fd-2e66-4b33-b3ff-e2f1b1f10742
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575655202 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.2575655202
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_jump.4285098935
Short name T184
Test name
Test status
Simulation time 603077145 ps
CPU time 0.78 seconds
Started Mar 21 12:38:02 PM PDT 24
Finished Mar 21 12:38:03 PM PDT 24
Peak memory 182868 kb
Host smart-93ba2d8f-f534-430e-a97c-ab14abfdb811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285098935 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.4285098935
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.1760249414
Short name T269
Test name
Test status
Simulation time 41773135470 ps
CPU time 59.39 seconds
Started Mar 21 12:38:24 PM PDT 24
Finished Mar 21 12:39:23 PM PDT 24
Peak memory 182896 kb
Host smart-be68b09b-510b-40b2-b5ee-ea97cc4f26c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760249414 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.1760249414
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.2596837307
Short name T177
Test name
Test status
Simulation time 494223031 ps
CPU time 0.88 seconds
Started Mar 21 12:38:05 PM PDT 24
Finished Mar 21 12:38:06 PM PDT 24
Peak memory 182872 kb
Host smart-322d025d-c8f5-4422-a464-c916c22ca527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596837307 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.2596837307
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.1936482868
Short name T201
Test name
Test status
Simulation time 139190831680 ps
CPU time 13.78 seconds
Started Mar 21 12:38:24 PM PDT 24
Finished Mar 21 12:38:38 PM PDT 24
Peak memory 192444 kb
Host smart-c533b817-94ab-4997-aa3d-fef83716a8dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936482868 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_
all.1936482868
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_jump.1451558632
Short name T255
Test name
Test status
Simulation time 362387086 ps
CPU time 0.71 seconds
Started Mar 21 12:37:59 PM PDT 24
Finished Mar 21 12:38:00 PM PDT 24
Peak memory 182868 kb
Host smart-5b10ed3c-bcc7-4df3-b18b-f5fb73fb8b10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451558632 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.1451558632
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.4083007459
Short name T41
Test name
Test status
Simulation time 13296881436 ps
CPU time 21.23 seconds
Started Mar 21 12:38:03 PM PDT 24
Finished Mar 21 12:38:24 PM PDT 24
Peak memory 182908 kb
Host smart-ff9db79c-f6e7-4acc-b003-763516c719b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083007459 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.4083007459
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.2989181547
Short name T218
Test name
Test status
Simulation time 432587022 ps
CPU time 1.2 seconds
Started Mar 21 12:37:58 PM PDT 24
Finished Mar 21 12:37:59 PM PDT 24
Peak memory 182908 kb
Host smart-c1a5f389-ac67-4803-94c3-5d7c01c22702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989181547 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.2989181547
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.3839518524
Short name T13
Test name
Test status
Simulation time 447094955696 ps
CPU time 172.97 seconds
Started Mar 21 12:38:26 PM PDT 24
Finished Mar 21 12:41:20 PM PDT 24
Peak memory 193796 kb
Host smart-31d70dd3-4823-4dc7-a8e4-73c7ec26176b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839518524 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_
all.3839518524
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/29.aon_timer_jump.3020871861
Short name T192
Test name
Test status
Simulation time 558639954 ps
CPU time 1.38 seconds
Started Mar 21 12:38:13 PM PDT 24
Finished Mar 21 12:38:15 PM PDT 24
Peak memory 182880 kb
Host smart-26b7c99e-116f-465b-910d-7579755367a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020871861 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.3020871861
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.1583979478
Short name T23
Test name
Test status
Simulation time 59651325457 ps
CPU time 91.33 seconds
Started Mar 21 12:38:17 PM PDT 24
Finished Mar 21 12:39:50 PM PDT 24
Peak memory 182940 kb
Host smart-f6c8584a-a979-4cd0-bcca-6bf9caedf427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583979478 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.1583979478
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.1378083525
Short name T224
Test name
Test status
Simulation time 532727740 ps
CPU time 0.69 seconds
Started Mar 21 12:38:09 PM PDT 24
Finished Mar 21 12:38:10 PM PDT 24
Peak memory 182836 kb
Host smart-0cf20e6b-9091-4589-9eda-7f3767480ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378083525 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.1378083525
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.1391172283
Short name T124
Test name
Test status
Simulation time 85397994492 ps
CPU time 34.98 seconds
Started Mar 21 12:38:12 PM PDT 24
Finished Mar 21 12:38:47 PM PDT 24
Peak memory 194312 kb
Host smart-7d44e301-390f-4179-b6ce-e05aeb2187e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391172283 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_
all.1391172283
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.1571914125
Short name T260
Test name
Test status
Simulation time 26104151513 ps
CPU time 204.18 seconds
Started Mar 21 12:38:02 PM PDT 24
Finished Mar 21 12:41:26 PM PDT 24
Peak memory 197824 kb
Host smart-7db81a13-339d-4b13-95ed-8c53117668f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571914125 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.1571914125
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.aon_timer_jump.3537981944
Short name T142
Test name
Test status
Simulation time 538839573 ps
CPU time 1.4 seconds
Started Mar 21 12:37:57 PM PDT 24
Finished Mar 21 12:38:04 PM PDT 24
Peak memory 182904 kb
Host smart-12d17c52-53e8-4a58-93d3-426000340ae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537981944 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.3537981944
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.2746682210
Short name T146
Test name
Test status
Simulation time 38024400462 ps
CPU time 14.13 seconds
Started Mar 21 12:37:48 PM PDT 24
Finished Mar 21 12:38:02 PM PDT 24
Peak memory 182952 kb
Host smart-9e0df780-b558-4971-9f83-8de792f1da2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746682210 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.2746682210
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.2148343978
Short name T11
Test name
Test status
Simulation time 4134945586 ps
CPU time 2.44 seconds
Started Mar 21 12:38:10 PM PDT 24
Finished Mar 21 12:38:13 PM PDT 24
Peak memory 214396 kb
Host smart-cdbae347-0b31-4e92-830a-507dd4a4ab0f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148343978 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.2148343978
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.3219484342
Short name T43
Test name
Test status
Simulation time 525040561 ps
CPU time 0.65 seconds
Started Mar 21 12:37:57 PM PDT 24
Finished Mar 21 12:37:59 PM PDT 24
Peak memory 182896 kb
Host smart-272f96da-2c60-453f-85f5-f1a7ca9b3ed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219484342 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.3219484342
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.3976792201
Short name T241
Test name
Test status
Simulation time 280213015219 ps
CPU time 164 seconds
Started Mar 21 12:37:56 PM PDT 24
Finished Mar 21 12:40:42 PM PDT 24
Peak memory 193728 kb
Host smart-e4c52498-df39-4558-bd57-e1f6aa5d3987
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976792201 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_a
ll.3976792201
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.4131275740
Short name T35
Test name
Test status
Simulation time 45518486270 ps
CPU time 510.55 seconds
Started Mar 21 12:37:58 PM PDT 24
Finished Mar 21 12:46:29 PM PDT 24
Peak memory 197908 kb
Host smart-643768e0-f895-4ba3-8fc0-c608d576a0e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131275740 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.4131275740
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_jump.3080745649
Short name T169
Test name
Test status
Simulation time 602235877 ps
CPU time 0.59 seconds
Started Mar 21 12:37:54 PM PDT 24
Finished Mar 21 12:37:54 PM PDT 24
Peak memory 182844 kb
Host smart-7555dd00-2850-414e-b5c1-f915dae8bb6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080745649 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.3080745649
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.3101666418
Short name T6
Test name
Test status
Simulation time 10675881807 ps
CPU time 16.66 seconds
Started Mar 21 12:38:01 PM PDT 24
Finished Mar 21 12:38:18 PM PDT 24
Peak memory 182936 kb
Host smart-d1f210bb-6459-4d27-9b47-413d58cf58a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101666418 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.3101666418
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.789520259
Short name T210
Test name
Test status
Simulation time 474861105 ps
CPU time 0.68 seconds
Started Mar 21 12:38:03 PM PDT 24
Finished Mar 21 12:38:04 PM PDT 24
Peak memory 182872 kb
Host smart-ea7fdbfc-3aa7-466f-ae8c-0c1e600da797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789520259 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.789520259
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.674505692
Short name T10
Test name
Test status
Simulation time 86105955060 ps
CPU time 74.11 seconds
Started Mar 21 12:38:10 PM PDT 24
Finished Mar 21 12:39:25 PM PDT 24
Peak memory 193092 kb
Host smart-53d8d657-7748-420c-947c-dda9ed6c2c93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674505692 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_a
ll.674505692
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.2819062420
Short name T86
Test name
Test status
Simulation time 80524284438 ps
CPU time 778.48 seconds
Started Mar 21 12:38:09 PM PDT 24
Finished Mar 21 12:51:08 PM PDT 24
Peak memory 201396 kb
Host smart-8eeb5139-f878-423e-969c-3ac1f698e835
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819062420 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.2819062420
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.aon_timer_jump.469578416
Short name T157
Test name
Test status
Simulation time 430043988 ps
CPU time 0.71 seconds
Started Mar 21 12:38:05 PM PDT 24
Finished Mar 21 12:38:06 PM PDT 24
Peak memory 182844 kb
Host smart-c65dcb2a-fc72-4163-9376-b881e2bd86af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469578416 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.469578416
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.3814443775
Short name T138
Test name
Test status
Simulation time 29504477992 ps
CPU time 11.53 seconds
Started Mar 21 12:38:12 PM PDT 24
Finished Mar 21 12:38:24 PM PDT 24
Peak memory 182956 kb
Host smart-d9022c4d-dcf8-4b11-976d-f47290aec626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814443775 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.3814443775
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.1139658906
Short name T135
Test name
Test status
Simulation time 377207573 ps
CPU time 0.78 seconds
Started Mar 21 12:38:15 PM PDT 24
Finished Mar 21 12:38:15 PM PDT 24
Peak memory 182788 kb
Host smart-5a7e7ec1-c40e-4090-a455-1d242e465915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139658906 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.1139658906
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.3919735764
Short name T221
Test name
Test status
Simulation time 50998032991 ps
CPU time 17.6 seconds
Started Mar 21 12:38:11 PM PDT 24
Finished Mar 21 12:38:28 PM PDT 24
Peak memory 182960 kb
Host smart-8a331966-ffc3-4250-85b1-7eb40747bddd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919735764 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_
all.3919735764
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.634437669
Short name T31
Test name
Test status
Simulation time 500368306871 ps
CPU time 1419.81 seconds
Started Mar 21 12:38:19 PM PDT 24
Finished Mar 21 01:01:59 PM PDT 24
Peak memory 209992 kb
Host smart-5e8f4aa2-b84b-4178-a1a0-b13835fd4b67
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634437669 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.634437669
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.aon_timer_jump.1531657171
Short name T148
Test name
Test status
Simulation time 515392540 ps
CPU time 1.36 seconds
Started Mar 21 12:38:32 PM PDT 24
Finished Mar 21 12:38:34 PM PDT 24
Peak memory 182868 kb
Host smart-855e8edd-abfc-4398-843a-72a26b43a6e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531657171 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.1531657171
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.2188653183
Short name T214
Test name
Test status
Simulation time 16980126587 ps
CPU time 8.37 seconds
Started Mar 21 12:38:22 PM PDT 24
Finished Mar 21 12:38:31 PM PDT 24
Peak memory 182912 kb
Host smart-c0e3e87f-ce56-43c2-aeca-3be87c1b8433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188653183 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.2188653183
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.3344670359
Short name T110
Test name
Test status
Simulation time 504535919 ps
CPU time 1.03 seconds
Started Mar 21 12:38:18 PM PDT 24
Finished Mar 21 12:38:20 PM PDT 24
Peak memory 182892 kb
Host smart-7515b04f-27cd-426e-b2be-d047ce3f386c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344670359 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.3344670359
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.2823765911
Short name T145
Test name
Test status
Simulation time 120976032673 ps
CPU time 125.85 seconds
Started Mar 21 12:38:10 PM PDT 24
Finished Mar 21 12:40:16 PM PDT 24
Peak memory 193868 kb
Host smart-06698eb0-ce5e-4b18-b7db-0c1f8675e0e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823765911 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_
all.2823765911
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.9523148
Short name T34
Test name
Test status
Simulation time 42818360672 ps
CPU time 199.18 seconds
Started Mar 21 12:38:06 PM PDT 24
Finished Mar 21 12:41:25 PM PDT 24
Peak memory 197908 kb
Host smart-caa27a2b-227b-453c-a1a8-b05322706e89
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9523148 -assert nopos
tproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_reset.9523148
Directory /workspace/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.aon_timer_jump.2688970482
Short name T129
Test name
Test status
Simulation time 396810939 ps
CPU time 0.78 seconds
Started Mar 21 12:38:09 PM PDT 24
Finished Mar 21 12:38:10 PM PDT 24
Peak memory 182904 kb
Host smart-df189349-5552-4fdd-bc47-665fc8a7fb10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688970482 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.2688970482
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.881421559
Short name T134
Test name
Test status
Simulation time 8571902782 ps
CPU time 11.33 seconds
Started Mar 21 12:38:07 PM PDT 24
Finished Mar 21 12:38:19 PM PDT 24
Peak memory 182920 kb
Host smart-f020a2ef-2a85-444f-9c68-4fd21135aaa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881421559 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.881421559
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.1253719577
Short name T3
Test name
Test status
Simulation time 457391335 ps
CPU time 0.57 seconds
Started Mar 21 12:38:28 PM PDT 24
Finished Mar 21 12:38:29 PM PDT 24
Peak memory 182956 kb
Host smart-ff5cba3c-5413-4937-bded-4674d6bc5ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253719577 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.1253719577
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.2842239301
Short name T126
Test name
Test status
Simulation time 316264170325 ps
CPU time 122.26 seconds
Started Mar 21 12:38:25 PM PDT 24
Finished Mar 21 12:40:28 PM PDT 24
Peak memory 191168 kb
Host smart-13a7028e-32f0-4026-9598-223cc157d97b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842239301 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_
all.2842239301
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_jump.1218488793
Short name T46
Test name
Test status
Simulation time 547871841 ps
CPU time 0.77 seconds
Started Mar 21 12:38:20 PM PDT 24
Finished Mar 21 12:38:21 PM PDT 24
Peak memory 182900 kb
Host smart-68f1fcaa-f490-4be7-a581-c38fb84dabf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218488793 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.1218488793
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.470683200
Short name T38
Test name
Test status
Simulation time 31934691675 ps
CPU time 44.92 seconds
Started Mar 21 12:38:33 PM PDT 24
Finished Mar 21 12:39:18 PM PDT 24
Peak memory 182904 kb
Host smart-fe95474d-8dea-4741-a0d1-3e1fd901dfe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470683200 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.470683200
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.671962202
Short name T242
Test name
Test status
Simulation time 569864373 ps
CPU time 0.79 seconds
Started Mar 21 12:38:25 PM PDT 24
Finished Mar 21 12:38:26 PM PDT 24
Peak memory 182808 kb
Host smart-7bf1a7d8-f0da-4515-81c5-c4503f99295e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671962202 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.671962202
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.1300207411
Short name T47
Test name
Test status
Simulation time 380675033086 ps
CPU time 57.82 seconds
Started Mar 21 12:38:19 PM PDT 24
Finished Mar 21 12:39:17 PM PDT 24
Peak memory 183188 kb
Host smart-fb9d372a-42fc-4497-8db6-3d07d83e6d87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300207411 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_
all.1300207411
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.2803609455
Short name T92
Test name
Test status
Simulation time 20784604969 ps
CPU time 129.3 seconds
Started Mar 21 12:38:20 PM PDT 24
Finished Mar 21 12:40:30 PM PDT 24
Peak memory 197756 kb
Host smart-1f38e03a-233e-482b-855a-7eb1defb978f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803609455 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.2803609455
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.aon_timer_jump.2881674597
Short name T140
Test name
Test status
Simulation time 464952537 ps
CPU time 0.73 seconds
Started Mar 21 12:38:37 PM PDT 24
Finished Mar 21 12:38:39 PM PDT 24
Peak memory 182900 kb
Host smart-89f627e8-aef7-4479-a7f0-329670758cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881674597 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.2881674597
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.4197362282
Short name T133
Test name
Test status
Simulation time 37045109078 ps
CPU time 49.46 seconds
Started Mar 21 12:38:30 PM PDT 24
Finished Mar 21 12:39:19 PM PDT 24
Peak memory 182928 kb
Host smart-01ff680f-a09c-478f-8836-477c071bb43e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197362282 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.4197362282
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.3157051736
Short name T2
Test name
Test status
Simulation time 396112651 ps
CPU time 0.71 seconds
Started Mar 21 12:38:11 PM PDT 24
Finished Mar 21 12:38:11 PM PDT 24
Peak memory 182896 kb
Host smart-a4319682-43d6-4384-b1b5-ca0c2e1defee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157051736 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.3157051736
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.2823628431
Short name T175
Test name
Test status
Simulation time 171076106898 ps
CPU time 288.89 seconds
Started Mar 21 12:38:09 PM PDT 24
Finished Mar 21 12:42:58 PM PDT 24
Peak memory 193992 kb
Host smart-60642266-c235-428a-ba20-44a4083e8c73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823628431 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_
all.2823628431
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_jump.1382891223
Short name T200
Test name
Test status
Simulation time 494329429 ps
CPU time 0.7 seconds
Started Mar 21 12:38:48 PM PDT 24
Finished Mar 21 12:38:50 PM PDT 24
Peak memory 182868 kb
Host smart-faf05378-4b54-4e35-87de-342e68b55e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382891223 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.1382891223
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.2613231072
Short name T147
Test name
Test status
Simulation time 2774680587 ps
CPU time 1.48 seconds
Started Mar 21 12:38:12 PM PDT 24
Finished Mar 21 12:38:13 PM PDT 24
Peak memory 182876 kb
Host smart-3bb5c225-09e8-4d40-9adf-0032522b6854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613231072 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.2613231072
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.748180829
Short name T106
Test name
Test status
Simulation time 676743067 ps
CPU time 0.65 seconds
Started Mar 21 12:38:28 PM PDT 24
Finished Mar 21 12:38:29 PM PDT 24
Peak memory 182888 kb
Host smart-73eac710-c334-4238-ba3c-0155262ff5b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748180829 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.748180829
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.1047953005
Short name T79
Test name
Test status
Simulation time 57594882323 ps
CPU time 51.82 seconds
Started Mar 21 12:38:05 PM PDT 24
Finished Mar 21 12:38:57 PM PDT 24
Peak memory 183232 kb
Host smart-c806af52-38f5-454f-b665-e4bc42d565cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047953005 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_
all.1047953005
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.2498038024
Short name T248
Test name
Test status
Simulation time 16678692374 ps
CPU time 175.85 seconds
Started Mar 21 12:38:09 PM PDT 24
Finished Mar 21 12:41:05 PM PDT 24
Peak memory 197796 kb
Host smart-5299533c-957b-487d-9aae-89595d4585c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498038024 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.2498038024
Directory /workspace/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.aon_timer_jump.1531921174
Short name T243
Test name
Test status
Simulation time 555965279 ps
CPU time 1.3 seconds
Started Mar 21 12:38:26 PM PDT 24
Finished Mar 21 12:38:28 PM PDT 24
Peak memory 182976 kb
Host smart-9129081b-40fc-44b2-99af-e06315aea0e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531921174 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.1531921174
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.200892738
Short name T171
Test name
Test status
Simulation time 29062689566 ps
CPU time 10.63 seconds
Started Mar 21 12:38:26 PM PDT 24
Finished Mar 21 12:38:37 PM PDT 24
Peak memory 182960 kb
Host smart-b02c9935-aabf-441c-a366-a55f081079b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200892738 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.200892738
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.3617701940
Short name T160
Test name
Test status
Simulation time 333658250 ps
CPU time 1.06 seconds
Started Mar 21 12:38:32 PM PDT 24
Finished Mar 21 12:38:34 PM PDT 24
Peak memory 182872 kb
Host smart-4fc369d2-50a0-46ed-8a4a-5ffe47164927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617701940 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.3617701940
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.3884057713
Short name T77
Test name
Test status
Simulation time 64151991780 ps
CPU time 96.26 seconds
Started Mar 21 12:38:17 PM PDT 24
Finished Mar 21 12:39:55 PM PDT 24
Peak memory 191180 kb
Host smart-379f79a6-129f-427a-85e8-685bbc85bf0f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884057713 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_
all.3884057713
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_jump.521283390
Short name T163
Test name
Test status
Simulation time 455237386 ps
CPU time 1.18 seconds
Started Mar 21 12:38:05 PM PDT 24
Finished Mar 21 12:38:06 PM PDT 24
Peak memory 182864 kb
Host smart-696190a3-6983-4b42-9f1d-f0a95641fb2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521283390 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.521283390
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.2242422184
Short name T162
Test name
Test status
Simulation time 29043851723 ps
CPU time 42.45 seconds
Started Mar 21 12:38:12 PM PDT 24
Finished Mar 21 12:38:55 PM PDT 24
Peak memory 182928 kb
Host smart-303b29a9-11fc-441c-a720-cf44516b8aba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242422184 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.2242422184
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.4250936232
Short name T107
Test name
Test status
Simulation time 548081723 ps
CPU time 1.42 seconds
Started Mar 21 12:38:40 PM PDT 24
Finished Mar 21 12:38:42 PM PDT 24
Peak memory 182416 kb
Host smart-7a1ea5f9-a094-4290-b21d-89738198317c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250936232 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.4250936232
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.2594422911
Short name T266
Test name
Test status
Simulation time 114124398058 ps
CPU time 92.31 seconds
Started Mar 21 12:38:10 PM PDT 24
Finished Mar 21 12:39:42 PM PDT 24
Peak memory 194732 kb
Host smart-1cd6339a-6d88-4429-9d1a-fba2c64cbabd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594422911 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_
all.2594422911
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.2913334570
Short name T83
Test name
Test status
Simulation time 298384809735 ps
CPU time 692.65 seconds
Started Mar 21 12:38:35 PM PDT 24
Finished Mar 21 12:50:08 PM PDT 24
Peak memory 200148 kb
Host smart-eb00c8c7-eba6-4574-911e-71e65d996583
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913334570 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand_reset.2913334570
Directory /workspace/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.aon_timer_jump.156938576
Short name T78
Test name
Test status
Simulation time 559577952 ps
CPU time 0.82 seconds
Started Mar 21 12:38:07 PM PDT 24
Finished Mar 21 12:38:08 PM PDT 24
Peak memory 183052 kb
Host smart-23ce7adc-7ff8-41b3-851f-02f6c288942d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156938576 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.156938576
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.3341062941
Short name T222
Test name
Test status
Simulation time 2333215783 ps
CPU time 1.23 seconds
Started Mar 21 12:38:46 PM PDT 24
Finished Mar 21 12:38:47 PM PDT 24
Peak memory 182952 kb
Host smart-db959c22-e5ee-410b-a0de-47e9ee9ec186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341062941 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.3341062941
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.2617171686
Short name T178
Test name
Test status
Simulation time 424558922 ps
CPU time 0.61 seconds
Started Mar 21 12:38:36 PM PDT 24
Finished Mar 21 12:38:37 PM PDT 24
Peak memory 182948 kb
Host smart-326701fe-3ff5-432d-b0fd-612a5692532d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617171686 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.2617171686
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.1613651405
Short name T127
Test name
Test status
Simulation time 5472454593 ps
CPU time 4.21 seconds
Started Mar 21 12:38:33 PM PDT 24
Finished Mar 21 12:38:37 PM PDT 24
Peak memory 193904 kb
Host smart-a914945e-0f53-4b33-96bc-652eb9f3cc47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613651405 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_
all.1613651405
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.4011762534
Short name T159
Test name
Test status
Simulation time 56575469979 ps
CPU time 627.85 seconds
Started Mar 21 12:38:12 PM PDT 24
Finished Mar 21 12:48:40 PM PDT 24
Peak memory 197888 kb
Host smart-85bbf041-45a1-40ec-8861-571bc0d4bed9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011762534 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.4011762534
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_jump.4118313220
Short name T120
Test name
Test status
Simulation time 578210171 ps
CPU time 0.78 seconds
Started Mar 21 12:38:09 PM PDT 24
Finished Mar 21 12:38:10 PM PDT 24
Peak memory 182852 kb
Host smart-c349b044-53bb-4596-9865-2b3b4f3dec59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118313220 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.4118313220
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.4276412140
Short name T238
Test name
Test status
Simulation time 34268015794 ps
CPU time 14.14 seconds
Started Mar 21 12:38:07 PM PDT 24
Finished Mar 21 12:38:21 PM PDT 24
Peak memory 182920 kb
Host smart-507d3067-134b-4977-84de-2b8d882ee694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276412140 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.4276412140
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.2992502025
Short name T20
Test name
Test status
Simulation time 8001845259 ps
CPU time 6.48 seconds
Started Mar 21 12:38:03 PM PDT 24
Finished Mar 21 12:38:09 PM PDT 24
Peak memory 214808 kb
Host smart-7176fd98-4942-437d-9ab3-8e1b8d447d24
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992502025 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.2992502025
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.276890503
Short name T254
Test name
Test status
Simulation time 471969257 ps
CPU time 0.7 seconds
Started Mar 21 12:38:02 PM PDT 24
Finished Mar 21 12:38:03 PM PDT 24
Peak memory 182868 kb
Host smart-d0c07681-95a5-46c5-a27f-5a07a95395bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276890503 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.276890503
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.1830068036
Short name T170
Test name
Test status
Simulation time 236230357141 ps
CPU time 171.28 seconds
Started Mar 21 12:38:05 PM PDT 24
Finished Mar 21 12:40:57 PM PDT 24
Peak memory 182944 kb
Host smart-240ddd72-b094-4229-ab51-7e4a63839f5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830068036 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_a
ll.1830068036
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_jump.622781332
Short name T226
Test name
Test status
Simulation time 514005939 ps
CPU time 0.7 seconds
Started Mar 21 12:38:18 PM PDT 24
Finished Mar 21 12:38:20 PM PDT 24
Peak memory 182880 kb
Host smart-6c1bd215-c8f3-42b4-b426-5fb42ab12d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622781332 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.622781332
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.3888354971
Short name T205
Test name
Test status
Simulation time 18043235179 ps
CPU time 9.99 seconds
Started Mar 21 12:38:07 PM PDT 24
Finished Mar 21 12:38:17 PM PDT 24
Peak memory 182936 kb
Host smart-14d55c7e-30ae-482c-8d86-7b1eb446a204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888354971 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.3888354971
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.862521280
Short name T217
Test name
Test status
Simulation time 447742736 ps
CPU time 0.73 seconds
Started Mar 21 12:38:40 PM PDT 24
Finished Mar 21 12:38:41 PM PDT 24
Peak memory 182376 kb
Host smart-3e094412-7938-4d32-a02d-4222095a82e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862521280 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.862521280
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.2655070242
Short name T80
Test name
Test status
Simulation time 59344877254 ps
CPU time 24.91 seconds
Started Mar 21 12:38:27 PM PDT 24
Finished Mar 21 12:38:52 PM PDT 24
Peak memory 182964 kb
Host smart-cdeb122a-daf8-414e-bc75-1323b434150a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655070242 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_
all.2655070242
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.841186388
Short name T84
Test name
Test status
Simulation time 314026520074 ps
CPU time 494.08 seconds
Started Mar 21 12:38:27 PM PDT 24
Finished Mar 21 12:46:42 PM PDT 24
Peak memory 206040 kb
Host smart-8bba5660-5cd4-4969-af23-36de18acc9ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841186388 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.841186388
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.aon_timer_jump.1172529348
Short name T167
Test name
Test status
Simulation time 574172760 ps
CPU time 0.63 seconds
Started Mar 21 12:38:10 PM PDT 24
Finished Mar 21 12:38:11 PM PDT 24
Peak memory 182860 kb
Host smart-95b4308c-5c35-4438-bc55-3d9079d6871d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172529348 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.1172529348
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.3755518152
Short name T119
Test name
Test status
Simulation time 47308485969 ps
CPU time 30.6 seconds
Started Mar 21 12:38:14 PM PDT 24
Finished Mar 21 12:38:45 PM PDT 24
Peak memory 182924 kb
Host smart-96eb8443-98af-4483-b1d4-e7c6d79959a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755518152 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.3755518152
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.2482034314
Short name T112
Test name
Test status
Simulation time 496942687 ps
CPU time 1.09 seconds
Started Mar 21 12:38:22 PM PDT 24
Finished Mar 21 12:38:24 PM PDT 24
Peak memory 182880 kb
Host smart-84a87999-7051-47f2-8f5d-017e0d9981a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482034314 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.2482034314
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.3551431270
Short name T164
Test name
Test status
Simulation time 127540086287 ps
CPU time 103.58 seconds
Started Mar 21 12:38:15 PM PDT 24
Finished Mar 21 12:39:58 PM PDT 24
Peak memory 182952 kb
Host smart-11707ccb-ca8a-48e0-a2ab-ed0f5a36e8bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551431270 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_
all.3551431270
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.564737083
Short name T90
Test name
Test status
Simulation time 57972922745 ps
CPU time 99.76 seconds
Started Mar 21 12:38:40 PM PDT 24
Finished Mar 21 12:40:20 PM PDT 24
Peak memory 197864 kb
Host smart-8eb1b521-2378-41c1-9880-f07bf323bf90
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564737083 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.564737083
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.aon_timer_jump.704460010
Short name T81
Test name
Test status
Simulation time 424313916 ps
CPU time 0.7 seconds
Started Mar 21 12:38:14 PM PDT 24
Finished Mar 21 12:38:15 PM PDT 24
Peak memory 182892 kb
Host smart-15fbb592-ced0-4db2-b20f-a879c266470e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704460010 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.704460010
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.238425422
Short name T111
Test name
Test status
Simulation time 35687595355 ps
CPU time 8.08 seconds
Started Mar 21 12:38:20 PM PDT 24
Finished Mar 21 12:38:28 PM PDT 24
Peak memory 182928 kb
Host smart-e9d6b394-dcd0-43d3-88fe-67a25d27f4ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238425422 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.238425422
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.339740598
Short name T123
Test name
Test status
Simulation time 409799136 ps
CPU time 0.7 seconds
Started Mar 21 12:38:21 PM PDT 24
Finished Mar 21 12:38:22 PM PDT 24
Peak memory 182864 kb
Host smart-bb6bc62d-c7db-429a-9732-8582560a3296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339740598 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.339740598
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.2611415995
Short name T85
Test name
Test status
Simulation time 285802789136 ps
CPU time 252.4 seconds
Started Mar 21 12:38:30 PM PDT 24
Finished Mar 21 12:42:42 PM PDT 24
Peak memory 197860 kb
Host smart-29a45776-25d5-42fe-b236-555886867d00
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611415995 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.2611415995
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.aon_timer_jump.267323222
Short name T206
Test name
Test status
Simulation time 542477270 ps
CPU time 0.8 seconds
Started Mar 21 12:38:25 PM PDT 24
Finished Mar 21 12:38:26 PM PDT 24
Peak memory 182812 kb
Host smart-cbaab7f4-7363-4b74-8cd3-3911fbc80880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267323222 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.267323222
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.3244204284
Short name T125
Test name
Test status
Simulation time 55056780658 ps
CPU time 19.59 seconds
Started Mar 21 12:38:23 PM PDT 24
Finished Mar 21 12:38:43 PM PDT 24
Peak memory 182944 kb
Host smart-dae00bf4-cf39-46b5-b630-7f67e8a3ba2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244204284 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.3244204284
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.2139824194
Short name T53
Test name
Test status
Simulation time 704297909 ps
CPU time 0.61 seconds
Started Mar 21 12:38:32 PM PDT 24
Finished Mar 21 12:38:33 PM PDT 24
Peak memory 182868 kb
Host smart-1d2b393e-8060-467c-b349-b0552c811f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139824194 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.2139824194
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.2352695264
Short name T37
Test name
Test status
Simulation time 141892485434 ps
CPU time 212.15 seconds
Started Mar 21 12:38:08 PM PDT 24
Finished Mar 21 12:41:40 PM PDT 24
Peak memory 182940 kb
Host smart-5514a706-b7a8-42c1-af54-10e5aad411c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352695264 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_
all.2352695264
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_jump.1118055985
Short name T180
Test name
Test status
Simulation time 546948965 ps
CPU time 1.38 seconds
Started Mar 21 12:38:21 PM PDT 24
Finished Mar 21 12:38:23 PM PDT 24
Peak memory 182972 kb
Host smart-77e4185e-5d4f-4c59-96a2-a13e8f80c54e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118055985 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.1118055985
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.3449238139
Short name T176
Test name
Test status
Simulation time 24990627152 ps
CPU time 40.26 seconds
Started Mar 21 12:38:32 PM PDT 24
Finished Mar 21 12:39:13 PM PDT 24
Peak memory 182928 kb
Host smart-8b91ee45-cf49-4a54-a429-03499914fa2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449238139 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.3449238139
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.1907818859
Short name T216
Test name
Test status
Simulation time 426473358 ps
CPU time 1.27 seconds
Started Mar 21 12:38:32 PM PDT 24
Finished Mar 21 12:38:34 PM PDT 24
Peak memory 182864 kb
Host smart-0ce033ba-422d-4b3d-be1f-040497f82e44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907818859 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.1907818859
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.694743964
Short name T121
Test name
Test status
Simulation time 23774687049 ps
CPU time 33.47 seconds
Started Mar 21 12:38:34 PM PDT 24
Finished Mar 21 12:39:08 PM PDT 24
Peak memory 182908 kb
Host smart-72479d8c-2c9f-436c-86b7-ad77bef713c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694743964 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_a
ll.694743964
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.3053097340
Short name T128
Test name
Test status
Simulation time 384913038049 ps
CPU time 866.74 seconds
Started Mar 21 12:38:18 PM PDT 24
Finished Mar 21 12:52:46 PM PDT 24
Peak memory 201708 kb
Host smart-3b771327-6725-418a-97a6-f0d70592ed67
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053097340 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.3053097340
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.aon_timer_jump.3078334088
Short name T264
Test name
Test status
Simulation time 608460942 ps
CPU time 0.8 seconds
Started Mar 21 12:38:25 PM PDT 24
Finished Mar 21 12:38:26 PM PDT 24
Peak memory 182872 kb
Host smart-28e0540b-71ec-4b44-b392-ab1019438b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078334088 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.3078334088
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.27487628
Short name T52
Test name
Test status
Simulation time 39241709950 ps
CPU time 15.12 seconds
Started Mar 21 12:38:29 PM PDT 24
Finished Mar 21 12:38:44 PM PDT 24
Peak memory 182956 kb
Host smart-5cab6c47-31c7-4347-8024-50db69f5c2ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27487628 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.27487628
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.1936383333
Short name T223
Test name
Test status
Simulation time 503219332 ps
CPU time 0.59 seconds
Started Mar 21 12:38:28 PM PDT 24
Finished Mar 21 12:38:29 PM PDT 24
Peak memory 182888 kb
Host smart-b00fff04-a629-4fb2-bdc1-5a43d87ba6a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936383333 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.1936383333
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.2011876811
Short name T76
Test name
Test status
Simulation time 58261070749 ps
CPU time 24.24 seconds
Started Mar 21 12:38:20 PM PDT 24
Finished Mar 21 12:38:44 PM PDT 24
Peak memory 192344 kb
Host smart-240fc586-7f7b-4bae-8e94-03eec6622216
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011876811 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_
all.2011876811
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.1230127428
Short name T36
Test name
Test status
Simulation time 91489952095 ps
CPU time 256.71 seconds
Started Mar 21 12:38:28 PM PDT 24
Finished Mar 21 12:42:45 PM PDT 24
Peak memory 197884 kb
Host smart-e229aae5-6114-4249-a633-e4cfd5cabda7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230127428 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.1230127428
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.aon_timer_jump.2018271488
Short name T116
Test name
Test status
Simulation time 596131858 ps
CPU time 1.46 seconds
Started Mar 21 12:38:33 PM PDT 24
Finished Mar 21 12:38:35 PM PDT 24
Peak memory 182908 kb
Host smart-c992e1ab-0c4c-4eeb-89a0-8d0eb156293d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018271488 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.2018271488
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.1732035581
Short name T155
Test name
Test status
Simulation time 10989564325 ps
CPU time 4.89 seconds
Started Mar 21 12:38:39 PM PDT 24
Finished Mar 21 12:38:44 PM PDT 24
Peak memory 182876 kb
Host smart-27203e13-4144-4b94-b015-0ad6965328fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732035581 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.1732035581
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.54377742
Short name T8
Test name
Test status
Simulation time 430951846 ps
CPU time 0.9 seconds
Started Mar 21 12:38:12 PM PDT 24
Finished Mar 21 12:38:13 PM PDT 24
Peak memory 182916 kb
Host smart-992da588-2088-4d7e-adbc-20415959a87c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54377742 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.54377742
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.2410223050
Short name T139
Test name
Test status
Simulation time 241507283634 ps
CPU time 93.37 seconds
Started Mar 21 12:38:42 PM PDT 24
Finished Mar 21 12:40:16 PM PDT 24
Peak memory 192396 kb
Host smart-c7cf675c-dea9-410c-9668-0a9d21ca924a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410223050 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_
all.2410223050
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.2635618639
Short name T227
Test name
Test status
Simulation time 131500020515 ps
CPU time 317.37 seconds
Started Mar 21 12:38:32 PM PDT 24
Finished Mar 21 12:43:50 PM PDT 24
Peak memory 197900 kb
Host smart-5b67d24c-52b7-44d2-91e5-f32f663c1603
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635618639 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.2635618639
Directory /workspace/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.aon_timer_jump.394660345
Short name T186
Test name
Test status
Simulation time 382136914 ps
CPU time 0.69 seconds
Started Mar 21 12:38:27 PM PDT 24
Finished Mar 21 12:38:28 PM PDT 24
Peak memory 182860 kb
Host smart-6ace140a-9e78-4b92-adc6-4ecf39ba45b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394660345 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.394660345
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.866585762
Short name T156
Test name
Test status
Simulation time 38400877698 ps
CPU time 28.32 seconds
Started Mar 21 12:38:37 PM PDT 24
Finished Mar 21 12:39:06 PM PDT 24
Peak memory 182920 kb
Host smart-ccd39115-ec3f-40f0-ab9a-26b71b78d4e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866585762 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.866585762
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.1717420207
Short name T197
Test name
Test status
Simulation time 400911846 ps
CPU time 0.7 seconds
Started Mar 21 12:38:32 PM PDT 24
Finished Mar 21 12:38:33 PM PDT 24
Peak memory 182908 kb
Host smart-563284ee-3240-4101-a343-d16a28c4973b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717420207 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.1717420207
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.677548791
Short name T251
Test name
Test status
Simulation time 53477119172 ps
CPU time 71.33 seconds
Started Mar 21 12:38:29 PM PDT 24
Finished Mar 21 12:39:41 PM PDT 24
Peak memory 182968 kb
Host smart-c2398810-aca5-4e2a-ba07-63740b59d0b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677548791 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_a
ll.677548791
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_jump.74237249
Short name T271
Test name
Test status
Simulation time 549610842 ps
CPU time 1.35 seconds
Started Mar 21 12:38:44 PM PDT 24
Finished Mar 21 12:38:45 PM PDT 24
Peak memory 183032 kb
Host smart-dc08429d-ae35-4584-89f5-f917b36d61fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74237249 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.74237249
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.2197880783
Short name T213
Test name
Test status
Simulation time 34687442534 ps
CPU time 48.78 seconds
Started Mar 21 12:38:54 PM PDT 24
Finished Mar 21 12:39:44 PM PDT 24
Peak memory 182944 kb
Host smart-36617bd2-b353-4977-9fbd-707be276fcf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197880783 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.2197880783
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.167297606
Short name T250
Test name
Test status
Simulation time 363334754 ps
CPU time 1.24 seconds
Started Mar 21 12:38:46 PM PDT 24
Finished Mar 21 12:38:47 PM PDT 24
Peak memory 182816 kb
Host smart-67f6c28f-7b12-4031-a8e9-1171f22559b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167297606 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.167297606
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.4021972005
Short name T219
Test name
Test status
Simulation time 124694287547 ps
CPU time 48.74 seconds
Started Mar 21 12:38:44 PM PDT 24
Finished Mar 21 12:39:33 PM PDT 24
Peak memory 182952 kb
Host smart-acebfd62-09db-4a63-9e7f-a54b7847439d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021972005 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_
all.4021972005
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.1340058218
Short name T32
Test name
Test status
Simulation time 184269307532 ps
CPU time 262.06 seconds
Started Mar 21 12:38:33 PM PDT 24
Finished Mar 21 12:42:56 PM PDT 24
Peak memory 206108 kb
Host smart-1e5f5ad7-e8ec-4000-9662-fda43bb1ca2d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340058218 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.1340058218
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.aon_timer_jump.1690055208
Short name T239
Test name
Test status
Simulation time 603575103 ps
CPU time 0.79 seconds
Started Mar 21 12:38:51 PM PDT 24
Finished Mar 21 12:38:51 PM PDT 24
Peak memory 182888 kb
Host smart-d18ad64f-6c13-4de1-9290-8c69b5f395aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690055208 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.1690055208
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.4200261012
Short name T5
Test name
Test status
Simulation time 24768290248 ps
CPU time 21.06 seconds
Started Mar 21 12:38:36 PM PDT 24
Finished Mar 21 12:38:57 PM PDT 24
Peak memory 183264 kb
Host smart-1221c2ef-1a9c-4f9a-9226-ba396771abb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200261012 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.4200261012
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.797948546
Short name T143
Test name
Test status
Simulation time 409894526 ps
CPU time 0.66 seconds
Started Mar 21 12:38:34 PM PDT 24
Finished Mar 21 12:38:36 PM PDT 24
Peak memory 182800 kb
Host smart-e828f332-ba87-4e9f-8666-50db16c307e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797948546 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.797948546
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.2620719429
Short name T51
Test name
Test status
Simulation time 181820991468 ps
CPU time 222.62 seconds
Started Mar 21 12:38:40 PM PDT 24
Finished Mar 21 12:42:23 PM PDT 24
Peak memory 194820 kb
Host smart-1c7b6cc3-eb85-4005-ab4c-58eae1ee778f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620719429 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_
all.2620719429
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.3355095177
Short name T33
Test name
Test status
Simulation time 269529784151 ps
CPU time 485.09 seconds
Started Mar 21 12:38:42 PM PDT 24
Finished Mar 21 12:46:48 PM PDT 24
Peak memory 197884 kb
Host smart-b6b4c856-94f6-4839-aef5-0180f54a0063
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355095177 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.3355095177
Directory /workspace/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.aon_timer_jump.2390873077
Short name T174
Test name
Test status
Simulation time 473187275 ps
CPU time 0.72 seconds
Started Mar 21 12:38:00 PM PDT 24
Finished Mar 21 12:38:01 PM PDT 24
Peak memory 182892 kb
Host smart-312d0dae-89ce-4548-8042-727afab077a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390873077 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.2390873077
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.1989195906
Short name T188
Test name
Test status
Simulation time 36034480209 ps
CPU time 14.05 seconds
Started Mar 21 12:38:16 PM PDT 24
Finished Mar 21 12:38:30 PM PDT 24
Peak memory 182912 kb
Host smart-97ca2833-95d7-4e3d-943c-ec68df702f62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989195906 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.1989195906
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.734803833
Short name T154
Test name
Test status
Simulation time 494918136 ps
CPU time 0.74 seconds
Started Mar 21 12:38:19 PM PDT 24
Finished Mar 21 12:38:20 PM PDT 24
Peak memory 182972 kb
Host smart-74a87001-130d-433c-aed0-7c4a5c294761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734803833 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.734803833
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.2629804075
Short name T75
Test name
Test status
Simulation time 22605157954 ps
CPU time 33.86 seconds
Started Mar 21 12:38:00 PM PDT 24
Finished Mar 21 12:38:34 PM PDT 24
Peak memory 182960 kb
Host smart-32e188af-ea5b-4a8e-99d4-c41c1ad75ecd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629804075 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_a
ll.2629804075
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.1596721594
Short name T89
Test name
Test status
Simulation time 217630620161 ps
CPU time 127.57 seconds
Started Mar 21 12:38:02 PM PDT 24
Finished Mar 21 12:40:09 PM PDT 24
Peak memory 197864 kb
Host smart-cbee48cb-1684-4589-aa1a-918b83efa5a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596721594 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.1596721594
Directory /workspace/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.aon_timer_jump.686893734
Short name T108
Test name
Test status
Simulation time 596678167 ps
CPU time 0.74 seconds
Started Mar 21 12:37:47 PM PDT 24
Finished Mar 21 12:37:48 PM PDT 24
Peak memory 182852 kb
Host smart-c946f4a5-06f1-4495-a48d-8a3d41b85403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686893734 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.686893734
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.2261658963
Short name T153
Test name
Test status
Simulation time 33125424403 ps
CPU time 11.72 seconds
Started Mar 21 12:38:13 PM PDT 24
Finished Mar 21 12:38:24 PM PDT 24
Peak memory 182928 kb
Host smart-38db936c-911c-4d83-b45c-927c3b9e2fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261658963 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.2261658963
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.3313158784
Short name T225
Test name
Test status
Simulation time 457134381 ps
CPU time 0.72 seconds
Started Mar 21 12:38:01 PM PDT 24
Finished Mar 21 12:38:02 PM PDT 24
Peak memory 182892 kb
Host smart-b99c1bc7-840c-4c69-b196-0ffdee67b235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313158784 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.3313158784
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.4033045672
Short name T203
Test name
Test status
Simulation time 91005138567 ps
CPU time 128.24 seconds
Started Mar 21 12:38:13 PM PDT 24
Finished Mar 21 12:40:22 PM PDT 24
Peak memory 183304 kb
Host smart-7b2814e7-ebb5-4faf-9968-4317640d385f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033045672 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_a
ll.4033045672
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.1633819723
Short name T94
Test name
Test status
Simulation time 28686878989 ps
CPU time 205.23 seconds
Started Mar 21 12:37:55 PM PDT 24
Finished Mar 21 12:41:20 PM PDT 24
Peak memory 197860 kb
Host smart-c172c04b-c8e3-47b9-85e6-4e51da3a96ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633819723 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.1633819723
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.aon_timer_jump.2431264262
Short name T185
Test name
Test status
Simulation time 463171358 ps
CPU time 1.26 seconds
Started Mar 21 12:38:14 PM PDT 24
Finished Mar 21 12:38:15 PM PDT 24
Peak memory 182916 kb
Host smart-dd280365-e29b-400d-8596-6bcfcb04ba10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431264262 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.2431264262
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.2767889777
Short name T240
Test name
Test status
Simulation time 13755911952 ps
CPU time 18.36 seconds
Started Mar 21 12:38:04 PM PDT 24
Finished Mar 21 12:38:23 PM PDT 24
Peak memory 182904 kb
Host smart-ba8fbf81-95ad-4e94-9f32-60b5c48400ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767889777 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.2767889777
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.1832772409
Short name T44
Test name
Test status
Simulation time 534694719 ps
CPU time 0.75 seconds
Started Mar 21 12:38:12 PM PDT 24
Finished Mar 21 12:38:12 PM PDT 24
Peak memory 182856 kb
Host smart-6690859f-044f-468b-8cc8-ccceb7a1b1b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832772409 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.1832772409
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.2754250889
Short name T165
Test name
Test status
Simulation time 274474853231 ps
CPU time 403.54 seconds
Started Mar 21 12:37:59 PM PDT 24
Finished Mar 21 12:44:43 PM PDT 24
Peak memory 182932 kb
Host smart-143190e3-d9ac-429e-926a-3313f78233fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754250889 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_a
ll.2754250889
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.3459965925
Short name T152
Test name
Test status
Simulation time 111639326096 ps
CPU time 295.43 seconds
Started Mar 21 12:37:50 PM PDT 24
Finished Mar 21 12:42:46 PM PDT 24
Peak memory 197828 kb
Host smart-29259233-a9c2-469c-af85-98ff00b35051
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459965925 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.3459965925
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.aon_timer_jump.3087564513
Short name T246
Test name
Test status
Simulation time 549908068 ps
CPU time 0.73 seconds
Started Mar 21 12:38:08 PM PDT 24
Finished Mar 21 12:38:09 PM PDT 24
Peak memory 182836 kb
Host smart-41e2087d-2e86-47a4-89df-6bd31c80a0b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087564513 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.3087564513
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.3056658280
Short name T113
Test name
Test status
Simulation time 41204052901 ps
CPU time 15.97 seconds
Started Mar 21 12:38:09 PM PDT 24
Finished Mar 21 12:38:25 PM PDT 24
Peak memory 182908 kb
Host smart-625eae60-468f-409e-9e8e-10f105020c43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056658280 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.3056658280
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.4274330971
Short name T196
Test name
Test status
Simulation time 379601235 ps
CPU time 0.74 seconds
Started Mar 21 12:38:01 PM PDT 24
Finished Mar 21 12:38:02 PM PDT 24
Peak memory 182856 kb
Host smart-dd3b3470-1887-4278-b7a3-54f16bc21d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274330971 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.4274330971
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.701691599
Short name T132
Test name
Test status
Simulation time 241668820774 ps
CPU time 178.44 seconds
Started Mar 21 12:38:03 PM PDT 24
Finished Mar 21 12:41:02 PM PDT 24
Peak memory 183004 kb
Host smart-1463c149-cd5b-47e3-b363-2e2ff388f473
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701691599 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_al
l.701691599
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.1712416937
Short name T181
Test name
Test status
Simulation time 32967051488 ps
CPU time 353.56 seconds
Started Mar 21 12:37:59 PM PDT 24
Finished Mar 21 12:43:53 PM PDT 24
Peak memory 197824 kb
Host smart-b23a4b0f-0916-4dbb-8dee-cb595524c2e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712416937 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.1712416937
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.aon_timer_jump.3667718741
Short name T109
Test name
Test status
Simulation time 638175448 ps
CPU time 0.62 seconds
Started Mar 21 12:38:04 PM PDT 24
Finished Mar 21 12:38:05 PM PDT 24
Peak memory 182840 kb
Host smart-26ad2700-2511-4f10-bea9-021f3ddbbc3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667718741 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.3667718741
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.514732719
Short name T114
Test name
Test status
Simulation time 55333003999 ps
CPU time 77.95 seconds
Started Mar 21 12:38:07 PM PDT 24
Finished Mar 21 12:39:25 PM PDT 24
Peak memory 182916 kb
Host smart-f5b61b25-d357-4110-b2ef-cd5a0f7f9694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514732719 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.514732719
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.3828974650
Short name T191
Test name
Test status
Simulation time 572296077 ps
CPU time 1.31 seconds
Started Mar 21 12:38:08 PM PDT 24
Finished Mar 21 12:38:10 PM PDT 24
Peak memory 182888 kb
Host smart-819bd288-9487-4337-be5e-0f78da5591c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828974650 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.3828974650
Directory /workspace/9.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.1458203945
Short name T262
Test name
Test status
Simulation time 72669539555 ps
CPU time 61.18 seconds
Started Mar 21 12:38:10 PM PDT 24
Finished Mar 21 12:39:12 PM PDT 24
Peak memory 193892 kb
Host smart-21980807-b56c-4d93-b53a-80f2c675fd8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458203945 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_a
ll.1458203945
Directory /workspace/9.aon_timer_stress_all/latest
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