Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
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Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
24.86 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv


Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 173 130 43 24.86


Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
bark_thold_cp 34 32 2 5.88 100 1 1 0
bite_thold_cp 34 32 2 5.88 100 1 1 0
pause_in_sleep_cp 2 1 1 50.00 100 1 1 2
prescale_cp 34 1 33 97.06 100 1 1 0
wdog_regwen_cp 2 0 2 100.00 100 1 1 2
wkup_cause_cp 1 0 1 100.00 100 1 1 0
wkup_thold_cp 66 64 2 3.03 100 1 1 0


Summary for Variable bark_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 32 2 5.88


User Defined Bins for bark_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
bark_max 0 1 1
bark[1] 0 1 1
bark[2] 0 1 1
bark[3] 0 1 1
bark[4] 0 1 1
bark[5] 0 1 1
bark[6] 0 1 1
bark[7] 0 1 1
bark[8] 0 1 1
bark[9] 0 1 1
bark[10] 0 1 1
bark[11] 0 1 1
bark[12] 0 1 1
bark[13] 0 1 1
bark[14] 0 1 1
bark[15] 0 1 1
bark[16] 0 1 1
bark[17] 0 1 1
bark[18] 0 1 1
bark[19] 0 1 1
bark[20] 0 1 1
bark[21] 0 1 1
bark[22] 0 1 1
bark[23] 0 1 1
bark[24] 0 1 1
bark[25] 0 1 1
bark[26] 0 1 1
bark[27] 0 1 1
bark[28] 0 1 1
bark[29] 0 1 1
bark[30] 0 1 1
bark[31] 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
bark[0] 48630 1 T1 12 T2 12 T3 11
bark_0 4656 1 T1 7 T2 7 T3 7


Summary for Variable bite_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 32 2 5.88


User Defined Bins for bite_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
bite_max 0 1 1
bite[1] 0 1 1
bite[2] 0 1 1
bite[3] 0 1 1
bite[4] 0 1 1
bite[5] 0 1 1
bite[6] 0 1 1
bite[7] 0 1 1
bite[8] 0 1 1
bite[9] 0 1 1
bite[10] 0 1 1
bite[11] 0 1 1
bite[12] 0 1 1
bite[13] 0 1 1
bite[14] 0 1 1
bite[15] 0 1 1
bite[16] 0 1 1
bite[17] 0 1 1
bite[18] 0 1 1
bite[19] 0 1 1
bite[20] 0 1 1
bite[21] 0 1 1
bite[22] 0 1 1
bite[23] 0 1 1
bite[24] 0 1 1
bite[25] 0 1 1
bite[26] 0 1 1
bite[27] 0 1 1
bite[28] 0 1 1
bite[29] 0 1 1
bite[30] 0 1 1
bite[31] 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
bite[0] 48129 1 T1 11 T2 11 T3 10
bite_0 5157 1 T1 8 T2 8 T3 8


Summary for Variable pause_in_sleep_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for pause_in_sleep_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 53286 1 T1 19 T2 19 T3 18


Summary for Variable prescale_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for prescale_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
prescale_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
prescale[0] 1008 1 T8 9 T30 19 T35 40
prescale[1] 1459 1 T6 48 T8 19 T41 42
prescale[2] 566 1 T19 19 T93 9 T76 39
prescale[3] 1320 1 T8 19 T15 111 T30 44
prescale[4] 897 1 T6 19 T39 84 T79 9
prescale[5] 752 1 T4 41 T6 61 T8 2
prescale[6] 919 1 T6 19 T41 19 T35 199
prescale[7] 663 1 T8 2 T37 91 T94 53
prescale[8] 1273 1 T4 2 T8 118 T14 23
prescale[9] 595 1 T6 4 T8 19 T16 2
prescale[10] 703 1 T8 37 T15 27 T95 9
prescale[11] 903 1 T19 19 T20 32 T96 32
prescale[12] 872 1 T15 40 T35 63 T97 9
prescale[13] 361 1 T6 54 T41 9 T35 19
prescale[14] 879 1 T15 19 T41 49 T35 2
prescale[15] 957 1 T14 19 T19 23 T36 131
prescale[16] 425 1 T6 2 T20 19 T37 37
prescale[17] 694 1 T8 2 T35 9 T97 19
prescale[18] 728 1 T6 2 T35 123 T98 28
prescale[19] 860 1 T6 19 T15 19 T35 21
prescale[20] 1121 1 T20 19 T35 19 T97 47
prescale[21] 911 1 T16 278 T99 9 T38 79
prescale[22] 547 1 T14 9 T19 19 T35 63
prescale[23] 923 1 T15 19 T16 2 T38 47
prescale[24] 948 1 T4 2 T20 28 T41 53
prescale[25] 639 1 T36 2 T86 2 T87 102
prescale[26] 998 1 T2 9 T5 9 T6 2
prescale[27] 489 1 T1 9 T6 2 T30 78
prescale[28] 1042 1 T15 2 T35 49 T36 65
prescale[29] 1217 1 T4 107 T37 2 T38 32
prescale[30] 813 1 T6 2 T8 97 T96 40
prescale[31] 1373 1 T8 2 T97 37 T38 103
prescale_0 25431 1 T1 10 T2 10 T3 18


Summary for Variable wdog_regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for wdog_regwen_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 40624 1 T1 9 T2 19 T3 9
auto[1] 12662 1 T1 10 T3 9 T4 83


Summary for Variable wkup_cause_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for wkup_cause_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
wkup_cause_cleared 53286 1 T1 19 T2 19 T3 18


Summary for Variable wkup_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 66 64 2 3.03


User Defined Bins for wkup_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
wkup_max 0 1 1
wkup[1] 0 1 1
wkup[2] 0 1 1
wkup[3] 0 1 1
wkup[4] 0 1 1
wkup[5] 0 1 1
wkup[6] 0 1 1
wkup[7] 0 1 1
wkup[8] 0 1 1
wkup[9] 0 1 1
wkup[10] 0 1 1
wkup[11] 0 1 1
wkup[12] 0 1 1
wkup[13] 0 1 1
wkup[14] 0 1 1
wkup[15] 0 1 1
wkup[16] 0 1 1
wkup[17] 0 1 1
wkup[18] 0 1 1
wkup[19] 0 1 1
wkup[20] 0 1 1
wkup[21] 0 1 1
wkup[22] 0 1 1
wkup[23] 0 1 1
wkup[24] 0 1 1
wkup[25] 0 1 1
wkup[26] 0 1 1
wkup[27] 0 1 1
wkup[28] 0 1 1
wkup[29] 0 1 1
wkup[30] 0 1 1
wkup[31] 0 1 1
wkup[32] 0 1 1
wkup[33] 0 1 1
wkup[34] 0 1 1
wkup[35] 0 1 1
wkup[36] 0 1 1
wkup[37] 0 1 1
wkup[38] 0 1 1
wkup[39] 0 1 1
wkup[40] 0 1 1
wkup[41] 0 1 1
wkup[42] 0 1 1
wkup[43] 0 1 1
wkup[44] 0 1 1
wkup[45] 0 1 1
wkup[46] 0 1 1
wkup[47] 0 1 1
wkup[48] 0 1 1
wkup[49] 0 1 1
wkup[50] 0 1 1
wkup[51] 0 1 1
wkup[52] 0 1 1
wkup[53] 0 1 1
wkup[54] 0 1 1
wkup[55] 0 1 1
wkup[56] 0 1 1
wkup[57] 0 1 1
wkup[58] 0 1 1
wkup[59] 0 1 1
wkup[60] 0 1 1
wkup[61] 0 1 1
wkup[62] 0 1 1
wkup[63] 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
wkup[0] 49647 1 T1 14 T2 14 T3 13
wkup_0 3639 1 T1 5 T2 5 T3 5

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