Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
92.98 99.25 93.67 100.00 98.40 99.51 67.06


Total test records in report: 420
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T281 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.2122528955 Mar 24 12:48:37 PM PDT 24 Mar 24 12:48:38 PM PDT 24 389785236 ps
T50 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.2509052018 Mar 24 12:48:41 PM PDT 24 Mar 24 12:48:45 PM PDT 24 7809684788 ps
T282 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.1591014450 Mar 24 12:48:40 PM PDT 24 Mar 24 12:48:40 PM PDT 24 539715939 ps
T283 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.1743550636 Mar 24 12:48:39 PM PDT 24 Mar 24 12:48:40 PM PDT 24 417193666 ps
T31 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.719456269 Mar 24 12:48:39 PM PDT 24 Mar 24 12:48:40 PM PDT 24 1173463657 ps
T32 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.689729120 Mar 24 12:48:50 PM PDT 24 Mar 24 12:48:54 PM PDT 24 8575548902 ps
T51 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.1519547250 Mar 24 12:48:43 PM PDT 24 Mar 24 12:48:44 PM PDT 24 497997251 ps
T284 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.3225534916 Mar 24 12:48:58 PM PDT 24 Mar 24 12:49:00 PM PDT 24 439139800 ps
T285 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.3846148079 Mar 24 12:49:06 PM PDT 24 Mar 24 12:49:07 PM PDT 24 428379951 ps
T286 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.316426950 Mar 24 12:48:44 PM PDT 24 Mar 24 12:48:46 PM PDT 24 738939281 ps
T52 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.3416868649 Mar 24 12:49:01 PM PDT 24 Mar 24 12:49:02 PM PDT 24 499288704 ps
T287 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.3870891962 Mar 24 12:49:08 PM PDT 24 Mar 24 12:49:09 PM PDT 24 354403001 ps
T33 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.1821014649 Mar 24 12:48:43 PM PDT 24 Mar 24 12:48:47 PM PDT 24 4868639558 ps
T288 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.1662603724 Mar 24 12:48:37 PM PDT 24 Mar 24 12:48:38 PM PDT 24 495656056 ps
T289 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.3617694964 Mar 24 12:48:53 PM PDT 24 Mar 24 12:48:55 PM PDT 24 558048401 ps
T290 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.4287305608 Mar 24 12:48:37 PM PDT 24 Mar 24 12:48:38 PM PDT 24 841101339 ps
T291 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.425380475 Mar 24 12:48:43 PM PDT 24 Mar 24 12:48:44 PM PDT 24 276100548 ps
T292 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.3879991468 Mar 24 12:48:43 PM PDT 24 Mar 24 12:48:44 PM PDT 24 454388635 ps
T53 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.3858060549 Mar 24 12:48:46 PM PDT 24 Mar 24 12:48:47 PM PDT 24 515561813 ps
T293 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.3701053852 Mar 24 12:48:48 PM PDT 24 Mar 24 12:48:50 PM PDT 24 427582499 ps
T294 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.2887996077 Mar 24 12:49:01 PM PDT 24 Mar 24 12:49:02 PM PDT 24 386958556 ps
T295 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.1237001893 Mar 24 12:49:01 PM PDT 24 Mar 24 12:49:03 PM PDT 24 371401876 ps
T296 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.251192425 Mar 24 12:48:50 PM PDT 24 Mar 24 12:48:50 PM PDT 24 336745897 ps
T64 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.2351019901 Mar 24 12:48:55 PM PDT 24 Mar 24 12:48:57 PM PDT 24 1041744728 ps
T297 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.3841446991 Mar 24 12:49:07 PM PDT 24 Mar 24 12:49:08 PM PDT 24 288476012 ps
T298 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.2338348546 Mar 24 12:49:02 PM PDT 24 Mar 24 12:49:03 PM PDT 24 488558346 ps
T299 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.1044355419 Mar 24 12:48:50 PM PDT 24 Mar 24 12:48:51 PM PDT 24 390814153 ps
T300 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.2124389186 Mar 24 12:48:47 PM PDT 24 Mar 24 12:48:48 PM PDT 24 826959758 ps
T301 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.3806962688 Mar 24 12:48:42 PM PDT 24 Mar 24 12:48:43 PM PDT 24 506066676 ps
T302 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.1444216492 Mar 24 12:48:57 PM PDT 24 Mar 24 12:48:59 PM PDT 24 437507710 ps
T303 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.1528283264 Mar 24 12:48:47 PM PDT 24 Mar 24 12:48:47 PM PDT 24 365213513 ps
T304 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.2434532532 Mar 24 12:48:37 PM PDT 24 Mar 24 12:48:38 PM PDT 24 475398135 ps
T305 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.3934737379 Mar 24 12:49:01 PM PDT 24 Mar 24 12:49:03 PM PDT 24 461344021 ps
T306 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.3645530350 Mar 24 12:48:50 PM PDT 24 Mar 24 12:48:51 PM PDT 24 507693036 ps
T307 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.3803647718 Mar 24 12:48:49 PM PDT 24 Mar 24 12:48:50 PM PDT 24 897987241 ps
T308 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.3530286577 Mar 24 12:48:59 PM PDT 24 Mar 24 12:49:00 PM PDT 24 421543994 ps
T309 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.3081535036 Mar 24 12:49:01 PM PDT 24 Mar 24 12:49:02 PM PDT 24 491545733 ps
T65 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.4240863267 Mar 24 12:48:40 PM PDT 24 Mar 24 12:48:45 PM PDT 24 1894246911 ps
T54 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.3910641894 Mar 24 12:48:54 PM PDT 24 Mar 24 12:48:55 PM PDT 24 518155613 ps
T310 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.3136704142 Mar 24 12:48:59 PM PDT 24 Mar 24 12:49:00 PM PDT 24 357512319 ps
T66 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.936026906 Mar 24 12:48:43 PM PDT 24 Mar 24 12:48:46 PM PDT 24 2903433818 ps
T311 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.1178005359 Mar 24 12:49:02 PM PDT 24 Mar 24 12:49:03 PM PDT 24 518750643 ps
T312 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.682062354 Mar 24 12:48:38 PM PDT 24 Mar 24 12:48:39 PM PDT 24 596783362 ps
T313 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.3506693233 Mar 24 12:48:55 PM PDT 24 Mar 24 12:48:57 PM PDT 24 446102428 ps
T67 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.3669967274 Mar 24 12:49:01 PM PDT 24 Mar 24 12:49:03 PM PDT 24 1376132110 ps
T314 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.1054261120 Mar 24 12:49:10 PM PDT 24 Mar 24 12:49:12 PM PDT 24 423824055 ps
T315 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.27207826 Mar 24 12:48:44 PM PDT 24 Mar 24 12:48:46 PM PDT 24 529788680 ps
T68 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.1539535273 Mar 24 12:48:49 PM PDT 24 Mar 24 12:48:51 PM PDT 24 2603358289 ps
T316 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.2711764107 Mar 24 12:48:40 PM PDT 24 Mar 24 12:48:43 PM PDT 24 1304735699 ps
T55 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.1393289277 Mar 24 12:48:41 PM PDT 24 Mar 24 12:48:44 PM PDT 24 9708204996 ps
T34 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.2168206506 Mar 24 12:48:47 PM PDT 24 Mar 24 12:48:55 PM PDT 24 4341078775 ps
T317 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.2082610358 Mar 24 12:49:00 PM PDT 24 Mar 24 12:49:01 PM PDT 24 443526249 ps
T318 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.270683886 Mar 24 12:49:10 PM PDT 24 Mar 24 12:49:11 PM PDT 24 482042271 ps
T319 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.3617821548 Mar 24 12:49:01 PM PDT 24 Mar 24 12:49:02 PM PDT 24 458607666 ps
T320 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.4226411560 Mar 24 12:48:37 PM PDT 24 Mar 24 12:48:38 PM PDT 24 513444038 ps
T321 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.2333520876 Mar 24 12:49:08 PM PDT 24 Mar 24 12:49:08 PM PDT 24 340995765 ps
T69 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.1487547938 Mar 24 12:49:01 PM PDT 24 Mar 24 12:49:01 PM PDT 24 321332592 ps
T322 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.3546224206 Mar 24 12:49:03 PM PDT 24 Mar 24 12:49:04 PM PDT 24 405473183 ps
T323 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.1279743624 Mar 24 12:48:57 PM PDT 24 Mar 24 12:49:00 PM PDT 24 453676325 ps
T70 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.2844780317 Mar 24 12:49:01 PM PDT 24 Mar 24 12:49:03 PM PDT 24 817376266 ps
T324 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.1013902564 Mar 24 12:48:50 PM PDT 24 Mar 24 12:48:51 PM PDT 24 278531975 ps
T325 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.342536736 Mar 24 12:49:05 PM PDT 24 Mar 24 12:49:05 PM PDT 24 514260391 ps
T326 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.2360959427 Mar 24 12:48:49 PM PDT 24 Mar 24 12:48:50 PM PDT 24 329427502 ps
T327 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.1154927592 Mar 24 12:49:08 PM PDT 24 Mar 24 12:49:09 PM PDT 24 439487054 ps
T328 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.1254998003 Mar 24 12:48:49 PM PDT 24 Mar 24 12:48:50 PM PDT 24 351962075 ps
T329 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.1642976040 Mar 24 12:48:42 PM PDT 24 Mar 24 12:48:43 PM PDT 24 505859473 ps
T330 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.3892780414 Mar 24 12:49:02 PM PDT 24 Mar 24 12:49:03 PM PDT 24 422683339 ps
T331 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.3634746938 Mar 24 12:48:41 PM PDT 24 Mar 24 12:48:42 PM PDT 24 1210859272 ps
T102 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.1895628868 Mar 24 12:48:49 PM PDT 24 Mar 24 12:48:52 PM PDT 24 4146386022 ps
T332 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.1168838960 Mar 24 12:48:50 PM PDT 24 Mar 24 12:48:51 PM PDT 24 429495864 ps
T333 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.581461493 Mar 24 12:49:03 PM PDT 24 Mar 24 12:49:16 PM PDT 24 7719624692 ps
T71 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.793801090 Mar 24 12:48:39 PM PDT 24 Mar 24 12:48:41 PM PDT 24 1039743761 ps
T56 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.3035290452 Mar 24 12:48:38 PM PDT 24 Mar 24 12:49:02 PM PDT 24 10171612711 ps
T334 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.482707570 Mar 24 12:49:09 PM PDT 24 Mar 24 12:49:11 PM PDT 24 1941062199 ps
T335 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.29136525 Mar 24 12:49:03 PM PDT 24 Mar 24 12:49:04 PM PDT 24 550819837 ps
T336 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.468187750 Mar 24 12:48:56 PM PDT 24 Mar 24 12:48:58 PM PDT 24 541339451 ps
T337 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.3728515420 Mar 24 12:48:43 PM PDT 24 Mar 24 12:48:45 PM PDT 24 669829499 ps
T57 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.802478950 Mar 24 12:49:03 PM PDT 24 Mar 24 12:49:04 PM PDT 24 406776239 ps
T338 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.1961240816 Mar 24 12:48:57 PM PDT 24 Mar 24 12:48:59 PM PDT 24 656858889 ps
T339 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.2915075464 Mar 24 12:48:53 PM PDT 24 Mar 24 12:48:54 PM PDT 24 537120697 ps
T340 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.869307722 Mar 24 12:49:12 PM PDT 24 Mar 24 12:49:13 PM PDT 24 334091753 ps
T341 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.281976458 Mar 24 12:49:02 PM PDT 24 Mar 24 12:49:03 PM PDT 24 443793606 ps
T342 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.245187912 Mar 24 12:48:55 PM PDT 24 Mar 24 12:48:58 PM PDT 24 566739887 ps
T343 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.488232925 Mar 24 12:48:39 PM PDT 24 Mar 24 12:48:40 PM PDT 24 602754479 ps
T344 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.3571884411 Mar 24 12:48:48 PM PDT 24 Mar 24 12:48:53 PM PDT 24 1334844664 ps
T345 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.3817579209 Mar 24 12:49:09 PM PDT 24 Mar 24 12:49:11 PM PDT 24 438046659 ps
T346 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.397123645 Mar 24 12:48:41 PM PDT 24 Mar 24 12:48:42 PM PDT 24 497505529 ps
T58 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.700819376 Mar 24 12:48:38 PM PDT 24 Mar 24 12:48:46 PM PDT 24 13479975629 ps
T347 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.4005456479 Mar 24 12:49:07 PM PDT 24 Mar 24 12:49:08 PM PDT 24 391954529 ps
T348 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.246214513 Mar 24 12:48:50 PM PDT 24 Mar 24 12:48:51 PM PDT 24 520997973 ps
T103 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.1754054215 Mar 24 12:49:01 PM PDT 24 Mar 24 12:49:05 PM PDT 24 8036981962 ps
T349 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.1387456722 Mar 24 12:49:09 PM PDT 24 Mar 24 12:49:10 PM PDT 24 355518168 ps
T350 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.3351483248 Mar 24 12:48:55 PM PDT 24 Mar 24 12:49:01 PM PDT 24 2154124028 ps
T351 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.490890508 Mar 24 12:48:49 PM PDT 24 Mar 24 12:48:53 PM PDT 24 8439904587 ps
T352 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.4248218118 Mar 24 12:49:07 PM PDT 24 Mar 24 12:49:08 PM PDT 24 346988655 ps
T353 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.369127592 Mar 24 12:48:57 PM PDT 24 Mar 24 12:49:00 PM PDT 24 362630749 ps
T100 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.4266104461 Mar 24 12:48:55 PM PDT 24 Mar 24 12:48:59 PM PDT 24 4198761627 ps
T354 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.3020710486 Mar 24 12:48:54 PM PDT 24 Mar 24 12:48:54 PM PDT 24 479072182 ps
T355 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.214571141 Mar 24 12:49:02 PM PDT 24 Mar 24 12:49:05 PM PDT 24 720429546 ps
T356 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.4168459744 Mar 24 12:49:06 PM PDT 24 Mar 24 12:49:07 PM PDT 24 354739821 ps
T357 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.3166432059 Mar 24 12:48:51 PM PDT 24 Mar 24 12:48:53 PM PDT 24 352006568 ps
T60 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.1841211338 Mar 24 12:48:38 PM PDT 24 Mar 24 12:48:39 PM PDT 24 317699196 ps
T358 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.3169871621 Mar 24 12:48:48 PM PDT 24 Mar 24 12:48:49 PM PDT 24 357853297 ps
T359 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.1601376412 Mar 24 12:48:37 PM PDT 24 Mar 24 12:48:38 PM PDT 24 431968608 ps
T101 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.4222501098 Mar 24 12:48:40 PM PDT 24 Mar 24 12:48:44 PM PDT 24 8567367044 ps
T360 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.525726892 Mar 24 12:49:01 PM PDT 24 Mar 24 12:49:12 PM PDT 24 8774951284 ps
T361 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.1366142154 Mar 24 12:48:49 PM PDT 24 Mar 24 12:48:50 PM PDT 24 549835348 ps
T362 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.844815029 Mar 24 12:48:39 PM PDT 24 Mar 24 12:48:40 PM PDT 24 512639062 ps
T363 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.1490437578 Mar 24 12:48:39 PM PDT 24 Mar 24 12:48:43 PM PDT 24 8291566634 ps
T364 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.400268701 Mar 24 12:49:07 PM PDT 24 Mar 24 12:49:08 PM PDT 24 485739812 ps
T365 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.2599878010 Mar 24 12:48:53 PM PDT 24 Mar 24 12:49:01 PM PDT 24 4720920500 ps
T366 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.2799460933 Mar 24 12:49:04 PM PDT 24 Mar 24 12:49:05 PM PDT 24 328330587 ps
T367 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.564683744 Mar 24 12:48:40 PM PDT 24 Mar 24 12:48:44 PM PDT 24 9045884890 ps
T368 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.674522439 Mar 24 12:49:02 PM PDT 24 Mar 24 12:49:03 PM PDT 24 525616068 ps
T369 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.424100932 Mar 24 12:48:50 PM PDT 24 Mar 24 12:48:51 PM PDT 24 386599952 ps
T370 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.797675867 Mar 24 12:48:42 PM PDT 24 Mar 24 12:48:44 PM PDT 24 1287924963 ps
T371 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.2561272261 Mar 24 12:48:52 PM PDT 24 Mar 24 12:48:53 PM PDT 24 498884670 ps
T372 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.2837581527 Mar 24 12:48:56 PM PDT 24 Mar 24 12:49:05 PM PDT 24 2461357072 ps
T373 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.3097164302 Mar 24 12:49:12 PM PDT 24 Mar 24 12:49:13 PM PDT 24 349302909 ps
T374 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.2343565439 Mar 24 12:48:39 PM PDT 24 Mar 24 12:48:41 PM PDT 24 726455527 ps
T375 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.3258610290 Mar 24 12:48:44 PM PDT 24 Mar 24 12:48:45 PM PDT 24 442919638 ps
T376 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.453378807 Mar 24 12:49:06 PM PDT 24 Mar 24 12:49:06 PM PDT 24 500412699 ps
T377 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.412648060 Mar 24 12:49:04 PM PDT 24 Mar 24 12:49:05 PM PDT 24 374777414 ps
T378 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.2556396563 Mar 24 12:49:10 PM PDT 24 Mar 24 12:49:12 PM PDT 24 440000232 ps
T379 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.3440638353 Mar 24 12:48:50 PM PDT 24 Mar 24 12:48:53 PM PDT 24 1410365771 ps
T380 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.2044631255 Mar 24 12:49:09 PM PDT 24 Mar 24 12:49:10 PM PDT 24 354116314 ps
T381 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.3567820997 Mar 24 12:48:46 PM PDT 24 Mar 24 12:48:47 PM PDT 24 527403147 ps
T382 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.365533177 Mar 24 12:48:45 PM PDT 24 Mar 24 12:48:46 PM PDT 24 846401632 ps
T383 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.3251270011 Mar 24 12:48:56 PM PDT 24 Mar 24 12:48:58 PM PDT 24 385376436 ps
T384 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.776042879 Mar 24 12:49:04 PM PDT 24 Mar 24 12:49:05 PM PDT 24 329319529 ps
T385 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.426567521 Mar 24 12:49:08 PM PDT 24 Mar 24 12:49:09 PM PDT 24 456336704 ps
T386 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.3639268394 Mar 24 12:48:57 PM PDT 24 Mar 24 12:49:00 PM PDT 24 4193198056 ps
T387 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.3688823620 Mar 24 12:48:37 PM PDT 24 Mar 24 12:48:39 PM PDT 24 936625073 ps
T388 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.3310275130 Mar 24 12:48:54 PM PDT 24 Mar 24 12:48:56 PM PDT 24 333676970 ps
T59 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.1161019442 Mar 24 12:48:49 PM PDT 24 Mar 24 12:48:49 PM PDT 24 557908247 ps
T389 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.2700606396 Mar 24 12:48:56 PM PDT 24 Mar 24 12:48:59 PM PDT 24 4607294429 ps
T390 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.1097834547 Mar 24 12:48:53 PM PDT 24 Mar 24 12:48:54 PM PDT 24 528272267 ps
T391 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.403111463 Mar 24 12:48:47 PM PDT 24 Mar 24 12:48:55 PM PDT 24 4493663446 ps
T392 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.329623625 Mar 24 12:49:00 PM PDT 24 Mar 24 12:49:03 PM PDT 24 8299038928 ps
T393 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.2044896641 Mar 24 12:48:54 PM PDT 24 Mar 24 12:48:58 PM PDT 24 1238979352 ps
T394 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.355913687 Mar 24 12:48:49 PM PDT 24 Mar 24 12:48:50 PM PDT 24 1617185975 ps
T395 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.1417869885 Mar 24 12:49:09 PM PDT 24 Mar 24 12:49:11 PM PDT 24 352795733 ps
T396 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.3071154918 Mar 24 12:48:39 PM PDT 24 Mar 24 12:48:41 PM PDT 24 410399856 ps
T397 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.1867472381 Mar 24 12:49:05 PM PDT 24 Mar 24 12:49:06 PM PDT 24 362126489 ps
T398 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.28743402 Mar 24 12:49:05 PM PDT 24 Mar 24 12:49:06 PM PDT 24 406109111 ps
T399 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.1016615960 Mar 24 12:48:44 PM PDT 24 Mar 24 12:48:45 PM PDT 24 450075434 ps
T400 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.3845796748 Mar 24 12:49:01 PM PDT 24 Mar 24 12:49:02 PM PDT 24 660863835 ps
T401 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.3402064659 Mar 24 12:48:38 PM PDT 24 Mar 24 12:48:39 PM PDT 24 375729983 ps
T61 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.3577196583 Mar 24 12:48:45 PM PDT 24 Mar 24 12:48:57 PM PDT 24 7205856754 ps
T402 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.1309945031 Mar 24 12:49:07 PM PDT 24 Mar 24 12:49:09 PM PDT 24 447618872 ps
T403 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.627648511 Mar 24 12:48:54 PM PDT 24 Mar 24 12:48:57 PM PDT 24 8223942802 ps
T404 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.4039327410 Mar 24 12:48:57 PM PDT 24 Mar 24 12:48:59 PM PDT 24 589583242 ps
T405 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.1473132054 Mar 24 12:49:02 PM PDT 24 Mar 24 12:49:03 PM PDT 24 664148398 ps
T62 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.2432679182 Mar 24 12:48:37 PM PDT 24 Mar 24 12:48:38 PM PDT 24 1250480092 ps
T406 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.694225311 Mar 24 12:49:10 PM PDT 24 Mar 24 12:49:12 PM PDT 24 396666792 ps
T407 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.2517375274 Mar 24 12:49:01 PM PDT 24 Mar 24 12:49:08 PM PDT 24 3740741720 ps
T408 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.2750168458 Mar 24 12:48:37 PM PDT 24 Mar 24 12:48:38 PM PDT 24 514690843 ps
T409 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.1177007831 Mar 24 12:48:36 PM PDT 24 Mar 24 12:48:37 PM PDT 24 537872542 ps
T410 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.1827551993 Mar 24 12:49:03 PM PDT 24 Mar 24 12:49:03 PM PDT 24 504179024 ps
T411 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.3569517552 Mar 24 12:48:56 PM PDT 24 Mar 24 12:48:58 PM PDT 24 1788673014 ps
T412 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.2488223793 Mar 24 12:48:50 PM PDT 24 Mar 24 12:48:57 PM PDT 24 4430860945 ps
T413 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.1043995729 Mar 24 12:48:51 PM PDT 24 Mar 24 12:48:55 PM PDT 24 1163481031 ps
T414 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.1152338103 Mar 24 12:48:47 PM PDT 24 Mar 24 12:48:50 PM PDT 24 560490514 ps
T415 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.4204248472 Mar 24 12:49:04 PM PDT 24 Mar 24 12:49:05 PM PDT 24 369312262 ps
T416 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.3073629016 Mar 24 12:49:12 PM PDT 24 Mar 24 12:49:13 PM PDT 24 398399153 ps
T417 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.4132491189 Mar 24 12:48:53 PM PDT 24 Mar 24 12:48:54 PM PDT 24 369198507 ps
T418 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.3006686181 Mar 24 12:48:43 PM PDT 24 Mar 24 12:48:44 PM PDT 24 385345515 ps
T419 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.2379723577 Mar 24 12:48:46 PM PDT 24 Mar 24 12:48:47 PM PDT 24 456835301 ps
T63 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.4000394835 Mar 24 12:48:41 PM PDT 24 Mar 24 12:48:42 PM PDT 24 403862799 ps
T420 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.1556133524 Mar 24 12:49:01 PM PDT 24 Mar 24 12:49:02 PM PDT 24 460918736 ps

Test location /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.887362793
Short name T4
Test name
Test status
Simulation time 43272541466 ps
CPU time 144.24 seconds
Started Mar 24 12:49:53 PM PDT 24
Finished Mar 24 12:52:17 PM PDT 24
Peak memory 197984 kb
Host smart-93d973a5-80cf-458a-81c7-d32a0ecd494a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887362793 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.887362793
Directory /workspace/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.689729120
Short name T32
Test name
Test status
Simulation time 8575548902 ps
CPU time 3.82 seconds
Started Mar 24 12:48:50 PM PDT 24
Finished Mar 24 12:48:54 PM PDT 24
Peak memory 197832 kb
Host smart-2d1ec010-1e7c-4f14-ab0a-18dd0117ff06
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689729120 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl
_intg_err.689729120
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.1973702198
Short name T35
Test name
Test status
Simulation time 38191744824 ps
CPU time 199.85 seconds
Started Mar 24 12:49:40 PM PDT 24
Finished Mar 24 12:53:00 PM PDT 24
Peak memory 197996 kb
Host smart-33d88f02-ffa8-4b6d-add4-07751cc6994b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973702198 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.1973702198
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.703193172
Short name T81
Test name
Test status
Simulation time 156359441645 ps
CPU time 239.49 seconds
Started Mar 24 12:50:12 PM PDT 24
Finished Mar 24 12:54:12 PM PDT 24
Peak memory 214364 kb
Host smart-c8815c77-335f-416d-8ac2-2261565b2e29
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703193172 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.703193172
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.1815548955
Short name T20
Test name
Test status
Simulation time 87848396892 ps
CPU time 143.5 seconds
Started Mar 24 12:50:14 PM PDT 24
Finished Mar 24 12:52:37 PM PDT 24
Peak memory 195036 kb
Host smart-1ad0afdb-2652-4925-bcab-d106a3a58bce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815548955 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_
all.1815548955
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.2509052018
Short name T50
Test name
Test status
Simulation time 7809684788 ps
CPU time 4.15 seconds
Started Mar 24 12:48:41 PM PDT 24
Finished Mar 24 12:48:45 PM PDT 24
Peak memory 192328 kb
Host smart-7df51063-2d4f-4b76-9e50-da9a1572d07d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509052018 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_b
it_bash.2509052018
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.868343048
Short name T17
Test name
Test status
Simulation time 4247876477 ps
CPU time 7.82 seconds
Started Mar 24 12:49:35 PM PDT 24
Finished Mar 24 12:49:43 PM PDT 24
Peak memory 214624 kb
Host smart-f8efc52e-2f49-4f69-8348-1a317ec63537
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868343048 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.868343048
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.347823306
Short name T2
Test name
Test status
Simulation time 51763075461 ps
CPU time 16.92 seconds
Started Mar 24 12:50:11 PM PDT 24
Finished Mar 24 12:50:28 PM PDT 24
Peak memory 183032 kb
Host smart-0839e163-15be-44f3-a096-231b8d853022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347823306 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.347823306
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.3697375378
Short name T140
Test name
Test status
Simulation time 73978281669 ps
CPU time 241.15 seconds
Started Mar 24 12:49:47 PM PDT 24
Finished Mar 24 12:53:48 PM PDT 24
Peak memory 197992 kb
Host smart-29e89a02-4776-4722-9592-c1420a33e11d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697375378 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.3697375378
Directory /workspace/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.793801090
Short name T71
Test name
Test status
Simulation time 1039743761 ps
CPU time 2.76 seconds
Started Mar 24 12:48:39 PM PDT 24
Finished Mar 24 12:48:41 PM PDT 24
Peak memory 193336 kb
Host smart-51247b91-d06b-4a02-aa22-4f4cc0621d88
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793801090 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_
timer_same_csr_outstanding.793801090
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.4222501098
Short name T101
Test name
Test status
Simulation time 8567367044 ps
CPU time 4.07 seconds
Started Mar 24 12:48:40 PM PDT 24
Finished Mar 24 12:48:44 PM PDT 24
Peak memory 197924 kb
Host smart-bdf218c9-f8bb-4d7b-91a1-9536c35b1f9e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222501098 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl
_intg_err.4222501098
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.3571314127
Short name T87
Test name
Test status
Simulation time 56323397673 ps
CPU time 421.32 seconds
Started Mar 24 12:49:45 PM PDT 24
Finished Mar 24 12:56:46 PM PDT 24
Peak memory 198004 kb
Host smart-e89acfd3-5f02-4cb7-a0cd-ad9c5fc06d24
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571314127 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.3571314127
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.4287305608
Short name T290
Test name
Test status
Simulation time 841101339 ps
CPU time 0.89 seconds
Started Mar 24 12:48:37 PM PDT 24
Finished Mar 24 12:48:38 PM PDT 24
Peak memory 183868 kb
Host smart-1a550deb-051e-471f-85eb-d72f62960d3c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287305608 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_a
liasing.4287305608
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.700819376
Short name T58
Test name
Test status
Simulation time 13479975629 ps
CPU time 7.73 seconds
Started Mar 24 12:48:38 PM PDT 24
Finished Mar 24 12:48:46 PM PDT 24
Peak memory 196016 kb
Host smart-4510a211-97f8-491f-9f7c-b84f6604e067
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700819376 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_bi
t_bash.700819376
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.2432679182
Short name T62
Test name
Test status
Simulation time 1250480092 ps
CPU time 1.03 seconds
Started Mar 24 12:48:37 PM PDT 24
Finished Mar 24 12:48:38 PM PDT 24
Peak memory 193180 kb
Host smart-63b3e4a3-64d0-4426-aec7-60bfd06a679d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432679182 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_h
w_reset.2432679182
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.1601376412
Short name T359
Test name
Test status
Simulation time 431968608 ps
CPU time 1 seconds
Started Mar 24 12:48:37 PM PDT 24
Finished Mar 24 12:48:38 PM PDT 24
Peak memory 196272 kb
Host smart-808360fe-7a2c-4271-b95d-84a7068e9f50
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601376412 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.1601376412
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.1177007831
Short name T409
Test name
Test status
Simulation time 537872542 ps
CPU time 1.04 seconds
Started Mar 24 12:48:36 PM PDT 24
Finished Mar 24 12:48:37 PM PDT 24
Peak memory 193348 kb
Host smart-0bbe5cbd-e4e7-474b-9321-4df1d072493e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177007831 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.1177007831
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.1591014450
Short name T282
Test name
Test status
Simulation time 539715939 ps
CPU time 0.74 seconds
Started Mar 24 12:48:40 PM PDT 24
Finished Mar 24 12:48:40 PM PDT 24
Peak memory 183716 kb
Host smart-190d095d-749b-4d1c-ba58-697d05ea4266
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591014450 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.1591014450
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.2122528955
Short name T281
Test name
Test status
Simulation time 389785236 ps
CPU time 0.72 seconds
Started Mar 24 12:48:37 PM PDT 24
Finished Mar 24 12:48:38 PM PDT 24
Peak memory 183700 kb
Host smart-2c9e71ce-1d3b-4c37-8acc-557d3391c13d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122528955 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_t
imer_mem_partial_access.2122528955
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.2434532532
Short name T304
Test name
Test status
Simulation time 475398135 ps
CPU time 0.74 seconds
Started Mar 24 12:48:37 PM PDT 24
Finished Mar 24 12:48:38 PM PDT 24
Peak memory 183784 kb
Host smart-43dfcc9c-315b-4ee2-8198-068fecc30af1
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434532532 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_w
alk.2434532532
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.2711764107
Short name T316
Test name
Test status
Simulation time 1304735699 ps
CPU time 2.65 seconds
Started Mar 24 12:48:40 PM PDT 24
Finished Mar 24 12:48:43 PM PDT 24
Peak memory 198596 kb
Host smart-eab5e351-019d-4e0e-aee8-ec0596ea59b8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711764107 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.2711764107
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.682062354
Short name T312
Test name
Test status
Simulation time 596783362 ps
CPU time 1.02 seconds
Started Mar 24 12:48:38 PM PDT 24
Finished Mar 24 12:48:39 PM PDT 24
Peak memory 193112 kb
Host smart-bb7a8a4d-0fa6-4e34-8308-79a25acc9621
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682062354 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_al
iasing.682062354
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.3035290452
Short name T56
Test name
Test status
Simulation time 10171612711 ps
CPU time 23.47 seconds
Started Mar 24 12:48:38 PM PDT 24
Finished Mar 24 12:49:02 PM PDT 24
Peak memory 194448 kb
Host smart-c7f1e8eb-440a-4b32-8101-c36a48bd0f77
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035290452 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_b
it_bash.3035290452
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.3688823620
Short name T387
Test name
Test status
Simulation time 936625073 ps
CPU time 1.89 seconds
Started Mar 24 12:48:37 PM PDT 24
Finished Mar 24 12:48:39 PM PDT 24
Peak memory 183860 kb
Host smart-c21a614e-2c1b-4d25-9c23-eedc6eb4a585
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688823620 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_h
w_reset.3688823620
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.488232925
Short name T343
Test name
Test status
Simulation time 602754479 ps
CPU time 0.95 seconds
Started Mar 24 12:48:39 PM PDT 24
Finished Mar 24 12:48:40 PM PDT 24
Peak memory 196224 kb
Host smart-b125bf8d-a410-4aeb-8981-20b9d82fd066
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488232925 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.488232925
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.2750168458
Short name T408
Test name
Test status
Simulation time 514690843 ps
CPU time 0.9 seconds
Started Mar 24 12:48:37 PM PDT 24
Finished Mar 24 12:48:38 PM PDT 24
Peak memory 183984 kb
Host smart-d192b528-a014-4ecc-8c6a-fdbea90229da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750168458 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.2750168458
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.4226411560
Short name T320
Test name
Test status
Simulation time 513444038 ps
CPU time 0.77 seconds
Started Mar 24 12:48:37 PM PDT 24
Finished Mar 24 12:48:38 PM PDT 24
Peak memory 183552 kb
Host smart-8a4e6ce1-4ecb-48e1-a6e8-e168747e57cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226411560 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.4226411560
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.2736684774
Short name T280
Test name
Test status
Simulation time 301081943 ps
CPU time 0.92 seconds
Started Mar 24 12:48:37 PM PDT 24
Finished Mar 24 12:48:38 PM PDT 24
Peak memory 183716 kb
Host smart-9fcace3f-5bb4-4977-a799-720575ad3242
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736684774 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_t
imer_mem_partial_access.2736684774
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.1743550636
Short name T283
Test name
Test status
Simulation time 417193666 ps
CPU time 1.03 seconds
Started Mar 24 12:48:39 PM PDT 24
Finished Mar 24 12:48:40 PM PDT 24
Peak memory 183728 kb
Host smart-f2f790e2-6b15-460b-a9d9-94b6d4c76e6b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743550636 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_w
alk.1743550636
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.4240863267
Short name T65
Test name
Test status
Simulation time 1894246911 ps
CPU time 5.49 seconds
Started Mar 24 12:48:40 PM PDT 24
Finished Mar 24 12:48:45 PM PDT 24
Peak memory 194428 kb
Host smart-accc6d7a-88e6-42a0-84dc-a5121d891996
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240863267 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon
_timer_same_csr_outstanding.4240863267
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.2343565439
Short name T374
Test name
Test status
Simulation time 726455527 ps
CPU time 2.17 seconds
Started Mar 24 12:48:39 PM PDT 24
Finished Mar 24 12:48:41 PM PDT 24
Peak memory 198604 kb
Host smart-360b6edb-5096-4bd4-bdbc-62535a02a8b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343565439 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.2343565439
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.1490437578
Short name T363
Test name
Test status
Simulation time 8291566634 ps
CPU time 3.96 seconds
Started Mar 24 12:48:39 PM PDT 24
Finished Mar 24 12:48:43 PM PDT 24
Peak memory 198044 kb
Host smart-e21f640f-223f-4d86-ad76-93f1d85cfbb7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490437578 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl
_intg_err.1490437578
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.3617694964
Short name T289
Test name
Test status
Simulation time 558048401 ps
CPU time 1.14 seconds
Started Mar 24 12:48:53 PM PDT 24
Finished Mar 24 12:48:55 PM PDT 24
Peak memory 196416 kb
Host smart-9371d175-2ca2-4231-a078-bb5ee2735be1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617694964 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.3617694964
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.3310275130
Short name T388
Test name
Test status
Simulation time 333676970 ps
CPU time 1.04 seconds
Started Mar 24 12:48:54 PM PDT 24
Finished Mar 24 12:48:56 PM PDT 24
Peak memory 193284 kb
Host smart-04e15f89-bd28-45dc-83d3-2369d12dde84
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310275130 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.3310275130
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.4132491189
Short name T417
Test name
Test status
Simulation time 369198507 ps
CPU time 0.69 seconds
Started Mar 24 12:48:53 PM PDT 24
Finished Mar 24 12:48:54 PM PDT 24
Peak memory 183684 kb
Host smart-0c8114d4-0718-4203-8b77-e969b4f331f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132491189 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.4132491189
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.2837581527
Short name T372
Test name
Test status
Simulation time 2461357072 ps
CPU time 8.32 seconds
Started Mar 24 12:48:56 PM PDT 24
Finished Mar 24 12:49:05 PM PDT 24
Peak memory 194432 kb
Host smart-797bf907-4ac6-4f1b-befe-cbfee63298b9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837581527 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.ao
n_timer_same_csr_outstanding.2837581527
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.2360959427
Short name T326
Test name
Test status
Simulation time 329427502 ps
CPU time 1.06 seconds
Started Mar 24 12:48:49 PM PDT 24
Finished Mar 24 12:48:50 PM PDT 24
Peak memory 197616 kb
Host smart-bb360a6c-6b6a-42f9-ae4f-a9d6731989a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360959427 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.2360959427
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.468187750
Short name T336
Test name
Test status
Simulation time 541339451 ps
CPU time 1.43 seconds
Started Mar 24 12:48:56 PM PDT 24
Finished Mar 24 12:48:58 PM PDT 24
Peak memory 195816 kb
Host smart-0b406829-45d6-4f41-b3e6-aa445e219c09
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468187750 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.468187750
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.1487547938
Short name T69
Test name
Test status
Simulation time 321332592 ps
CPU time 0.66 seconds
Started Mar 24 12:49:01 PM PDT 24
Finished Mar 24 12:49:01 PM PDT 24
Peak memory 191976 kb
Host smart-ebb4c0a3-c15b-497d-93c2-ea8318fcc07f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487547938 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.1487547938
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.3020710486
Short name T354
Test name
Test status
Simulation time 479072182 ps
CPU time 0.64 seconds
Started Mar 24 12:48:54 PM PDT 24
Finished Mar 24 12:48:54 PM PDT 24
Peak memory 183720 kb
Host smart-f64886d7-7ae5-4037-ad12-3c2612c14235
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020710486 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.3020710486
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.2044896641
Short name T393
Test name
Test status
Simulation time 1238979352 ps
CPU time 2.83 seconds
Started Mar 24 12:48:54 PM PDT 24
Finished Mar 24 12:48:58 PM PDT 24
Peak memory 193340 kb
Host smart-b8d5432c-bc95-447b-ab68-3c0523901517
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044896641 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.ao
n_timer_same_csr_outstanding.2044896641
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.1961240816
Short name T338
Test name
Test status
Simulation time 656858889 ps
CPU time 1.35 seconds
Started Mar 24 12:48:57 PM PDT 24
Finished Mar 24 12:48:59 PM PDT 24
Peak memory 198612 kb
Host smart-055cf8b1-488b-41a2-80c1-64517eb5f143
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961240816 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.1961240816
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.2700606396
Short name T389
Test name
Test status
Simulation time 4607294429 ps
CPU time 1.91 seconds
Started Mar 24 12:48:56 PM PDT 24
Finished Mar 24 12:48:59 PM PDT 24
Peak memory 196496 kb
Host smart-10c5612f-a06d-467a-93aa-6b0143bb8ab2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700606396 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_t
l_intg_err.2700606396
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.3530286577
Short name T308
Test name
Test status
Simulation time 421543994 ps
CPU time 0.98 seconds
Started Mar 24 12:48:59 PM PDT 24
Finished Mar 24 12:49:00 PM PDT 24
Peak memory 198428 kb
Host smart-247e9009-c81f-4b14-8c18-4c8b15eaa7cb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530286577 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.3530286577
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.674522439
Short name T368
Test name
Test status
Simulation time 525616068 ps
CPU time 0.77 seconds
Started Mar 24 12:49:02 PM PDT 24
Finished Mar 24 12:49:03 PM PDT 24
Peak memory 183544 kb
Host smart-90303cfc-0ea7-4498-8a24-686bb1a2e361
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674522439 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.674522439
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.3506693233
Short name T313
Test name
Test status
Simulation time 446102428 ps
CPU time 0.73 seconds
Started Mar 24 12:48:55 PM PDT 24
Finished Mar 24 12:48:57 PM PDT 24
Peak memory 183632 kb
Host smart-73d67a2f-4840-4bea-8e49-e536935bb9f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506693233 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.3506693233
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.3569517552
Short name T411
Test name
Test status
Simulation time 1788673014 ps
CPU time 1.64 seconds
Started Mar 24 12:48:56 PM PDT 24
Finished Mar 24 12:48:58 PM PDT 24
Peak memory 184000 kb
Host smart-f1164e37-a0b4-4d9d-867e-b2ebe7829070
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569517552 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.ao
n_timer_same_csr_outstanding.3569517552
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.1279743624
Short name T323
Test name
Test status
Simulation time 453676325 ps
CPU time 1.72 seconds
Started Mar 24 12:48:57 PM PDT 24
Finished Mar 24 12:49:00 PM PDT 24
Peak memory 198456 kb
Host smart-7cb384b1-253e-43cd-96f6-368944cf9e99
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279743624 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.1279743624
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.3639268394
Short name T386
Test name
Test status
Simulation time 4193198056 ps
CPU time 2.44 seconds
Started Mar 24 12:48:57 PM PDT 24
Finished Mar 24 12:49:00 PM PDT 24
Peak memory 197548 kb
Host smart-849be8c0-d4f2-4e23-83fb-c8c0693cd98a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639268394 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_t
l_intg_err.3639268394
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.4039327410
Short name T404
Test name
Test status
Simulation time 589583242 ps
CPU time 1.05 seconds
Started Mar 24 12:48:57 PM PDT 24
Finished Mar 24 12:48:59 PM PDT 24
Peak memory 198392 kb
Host smart-d3b82273-2ee2-451f-8720-8c8a30279c33
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039327410 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.4039327410
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.3416868649
Short name T52
Test name
Test status
Simulation time 499288704 ps
CPU time 0.76 seconds
Started Mar 24 12:49:01 PM PDT 24
Finished Mar 24 12:49:02 PM PDT 24
Peak memory 183896 kb
Host smart-a04676c8-dad4-4f65-8268-34ab30a772cb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416868649 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.3416868649
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.3136704142
Short name T310
Test name
Test status
Simulation time 357512319 ps
CPU time 1.08 seconds
Started Mar 24 12:48:59 PM PDT 24
Finished Mar 24 12:49:00 PM PDT 24
Peak memory 183652 kb
Host smart-7e30c957-db4d-4432-bb7a-5e64fa218fec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136704142 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.3136704142
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.3351483248
Short name T350
Test name
Test status
Simulation time 2154124028 ps
CPU time 4.86 seconds
Started Mar 24 12:48:55 PM PDT 24
Finished Mar 24 12:49:01 PM PDT 24
Peak memory 194544 kb
Host smart-f773ac87-d6cd-4f08-8fe6-f32de687ed90
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351483248 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.ao
n_timer_same_csr_outstanding.3351483248
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.245187912
Short name T342
Test name
Test status
Simulation time 566739887 ps
CPU time 2.38 seconds
Started Mar 24 12:48:55 PM PDT 24
Finished Mar 24 12:48:58 PM PDT 24
Peak memory 198640 kb
Host smart-d4aa23bc-cda4-49f1-b1a6-eb9a933390c3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245187912 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.245187912
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.1754054215
Short name T103
Test name
Test status
Simulation time 8036981962 ps
CPU time 3.08 seconds
Started Mar 24 12:49:01 PM PDT 24
Finished Mar 24 12:49:05 PM PDT 24
Peak memory 197892 kb
Host smart-59d239b2-a161-43a3-b0a6-b9fb0bf3c812
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754054215 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_t
l_intg_err.1754054215
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.2887996077
Short name T294
Test name
Test status
Simulation time 386958556 ps
CPU time 0.96 seconds
Started Mar 24 12:49:01 PM PDT 24
Finished Mar 24 12:49:02 PM PDT 24
Peak memory 195344 kb
Host smart-1c8259ee-fa58-443b-94f9-221a1d6984d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887996077 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.2887996077
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.3910641894
Short name T54
Test name
Test status
Simulation time 518155613 ps
CPU time 0.81 seconds
Started Mar 24 12:48:54 PM PDT 24
Finished Mar 24 12:48:55 PM PDT 24
Peak memory 193092 kb
Host smart-ff6ec245-3bb6-42ca-9165-6afec89a1bff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910641894 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.3910641894
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.1444216492
Short name T302
Test name
Test status
Simulation time 437507710 ps
CPU time 0.93 seconds
Started Mar 24 12:48:57 PM PDT 24
Finished Mar 24 12:48:59 PM PDT 24
Peak memory 183696 kb
Host smart-fcca93a0-8127-44cb-9416-2b6568d4204d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444216492 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.1444216492
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.2351019901
Short name T64
Test name
Test status
Simulation time 1041744728 ps
CPU time 0.81 seconds
Started Mar 24 12:48:55 PM PDT 24
Finished Mar 24 12:48:57 PM PDT 24
Peak memory 193376 kb
Host smart-58d7dc06-7e25-471a-8dd4-ace79cfc4cb5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351019901 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao
n_timer_same_csr_outstanding.2351019901
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.3225534916
Short name T284
Test name
Test status
Simulation time 439139800 ps
CPU time 1.86 seconds
Started Mar 24 12:48:58 PM PDT 24
Finished Mar 24 12:49:00 PM PDT 24
Peak memory 198540 kb
Host smart-4c85149e-ad67-44bc-8cdf-0e2cb9c3d33f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225534916 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.3225534916
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.627648511
Short name T403
Test name
Test status
Simulation time 8223942802 ps
CPU time 2.87 seconds
Started Mar 24 12:48:54 PM PDT 24
Finished Mar 24 12:48:57 PM PDT 24
Peak memory 198004 kb
Host smart-05658bb4-12c3-4e50-8d47-70b73da0ac91
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627648511 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl
_intg_err.627648511
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.2082610358
Short name T317
Test name
Test status
Simulation time 443526249 ps
CPU time 1.27 seconds
Started Mar 24 12:49:00 PM PDT 24
Finished Mar 24 12:49:01 PM PDT 24
Peak memory 195996 kb
Host smart-f206244a-037f-4abb-a84b-1dd9b1b75ff1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082610358 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.2082610358
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.3251270011
Short name T383
Test name
Test status
Simulation time 385376436 ps
CPU time 0.86 seconds
Started Mar 24 12:48:56 PM PDT 24
Finished Mar 24 12:48:58 PM PDT 24
Peak memory 183932 kb
Host smart-dbf21fe1-c535-453b-9ff9-950f0e9c60e8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251270011 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.3251270011
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.2338348546
Short name T298
Test name
Test status
Simulation time 488558346 ps
CPU time 0.73 seconds
Started Mar 24 12:49:02 PM PDT 24
Finished Mar 24 12:49:03 PM PDT 24
Peak memory 183560 kb
Host smart-f7cd3cc4-35af-45c5-92ec-c2e38944858c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338348546 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.2338348546
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.482707570
Short name T334
Test name
Test status
Simulation time 1941062199 ps
CPU time 1.87 seconds
Started Mar 24 12:49:09 PM PDT 24
Finished Mar 24 12:49:11 PM PDT 24
Peak memory 194392 kb
Host smart-e1b3ca94-e0f9-406d-9b15-b196155d43bf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482707570 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon
_timer_same_csr_outstanding.482707570
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.369127592
Short name T353
Test name
Test status
Simulation time 362630749 ps
CPU time 2.03 seconds
Started Mar 24 12:48:57 PM PDT 24
Finished Mar 24 12:49:00 PM PDT 24
Peak memory 198596 kb
Host smart-29e135e0-d405-4685-8a3b-143f7062acf5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369127592 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.369127592
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.4266104461
Short name T100
Test name
Test status
Simulation time 4198761627 ps
CPU time 2.76 seconds
Started Mar 24 12:48:55 PM PDT 24
Finished Mar 24 12:48:59 PM PDT 24
Peak memory 197292 kb
Host smart-4dd53baf-24dd-46fe-b07a-dd1311674e6d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266104461 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_t
l_intg_err.4266104461
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.1237001893
Short name T295
Test name
Test status
Simulation time 371401876 ps
CPU time 1.08 seconds
Started Mar 24 12:49:01 PM PDT 24
Finished Mar 24 12:49:03 PM PDT 24
Peak memory 195368 kb
Host smart-c35b666d-35b0-4e1e-b998-b06459507c71
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237001893 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.1237001893
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.802478950
Short name T57
Test name
Test status
Simulation time 406776239 ps
CPU time 0.65 seconds
Started Mar 24 12:49:03 PM PDT 24
Finished Mar 24 12:49:04 PM PDT 24
Peak memory 193260 kb
Host smart-ab0b8870-82e8-4962-b15d-fb34a83d6631
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802478950 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.802478950
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.776042879
Short name T384
Test name
Test status
Simulation time 329319529 ps
CPU time 1.04 seconds
Started Mar 24 12:49:04 PM PDT 24
Finished Mar 24 12:49:05 PM PDT 24
Peak memory 183692 kb
Host smart-d0db17cf-bab7-44fb-bf89-7c1bad164765
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776042879 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.776042879
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.3669967274
Short name T67
Test name
Test status
Simulation time 1376132110 ps
CPU time 2.27 seconds
Started Mar 24 12:49:01 PM PDT 24
Finished Mar 24 12:49:03 PM PDT 24
Peak memory 183768 kb
Host smart-f436ad30-b1f9-45d4-b3cd-b659f15b0200
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669967274 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.ao
n_timer_same_csr_outstanding.3669967274
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.281976458
Short name T341
Test name
Test status
Simulation time 443793606 ps
CPU time 1.14 seconds
Started Mar 24 12:49:02 PM PDT 24
Finished Mar 24 12:49:03 PM PDT 24
Peak memory 198420 kb
Host smart-9d983dfe-fe08-4344-930a-b7be666a9892
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281976458 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.281976458
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.2517375274
Short name T407
Test name
Test status
Simulation time 3740741720 ps
CPU time 6.58 seconds
Started Mar 24 12:49:01 PM PDT 24
Finished Mar 24 12:49:08 PM PDT 24
Peak memory 196212 kb
Host smart-ae84867d-eee2-4bde-91f5-c10c8dd6d12e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517375274 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_t
l_intg_err.2517375274
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.29136525
Short name T335
Test name
Test status
Simulation time 550819837 ps
CPU time 1.35 seconds
Started Mar 24 12:49:03 PM PDT 24
Finished Mar 24 12:49:04 PM PDT 24
Peak memory 195960 kb
Host smart-3e63ebd2-b099-451f-b9a6-04f9d098a114
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29136525 -assert nopostproc +UVM_TESTNAME=a
on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.29136525
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.4204248472
Short name T415
Test name
Test status
Simulation time 369312262 ps
CPU time 0.65 seconds
Started Mar 24 12:49:04 PM PDT 24
Finished Mar 24 12:49:05 PM PDT 24
Peak memory 183752 kb
Host smart-489c7f38-c4ff-4790-80b4-18da2c92c25d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204248472 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.4204248472
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.3617821548
Short name T319
Test name
Test status
Simulation time 458607666 ps
CPU time 0.7 seconds
Started Mar 24 12:49:01 PM PDT 24
Finished Mar 24 12:49:02 PM PDT 24
Peak memory 183628 kb
Host smart-ed5877b0-3115-4569-936d-cd63c44cf10c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617821548 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.3617821548
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.2844780317
Short name T70
Test name
Test status
Simulation time 817376266 ps
CPU time 1.15 seconds
Started Mar 24 12:49:01 PM PDT 24
Finished Mar 24 12:49:03 PM PDT 24
Peak memory 183784 kb
Host smart-074b412f-00a7-4cfe-a562-e48ef2e64ec7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844780317 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.ao
n_timer_same_csr_outstanding.2844780317
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.3845796748
Short name T400
Test name
Test status
Simulation time 660863835 ps
CPU time 1.53 seconds
Started Mar 24 12:49:01 PM PDT 24
Finished Mar 24 12:49:02 PM PDT 24
Peak memory 198448 kb
Host smart-06237593-4a94-4866-bcad-07c55143a130
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845796748 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.3845796748
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.581461493
Short name T333
Test name
Test status
Simulation time 7719624692 ps
CPU time 13.1 seconds
Started Mar 24 12:49:03 PM PDT 24
Finished Mar 24 12:49:16 PM PDT 24
Peak memory 198096 kb
Host smart-f81de8fe-dfe8-4dec-9314-6550e3112abe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581461493 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl
_intg_err.581461493
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.3892780414
Short name T330
Test name
Test status
Simulation time 422683339 ps
CPU time 0.85 seconds
Started Mar 24 12:49:02 PM PDT 24
Finished Mar 24 12:49:03 PM PDT 24
Peak memory 196416 kb
Host smart-1d9f1726-ad7d-44b2-acbc-92528cd1a9c4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892780414 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.3892780414
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.3817579209
Short name T345
Test name
Test status
Simulation time 438046659 ps
CPU time 0.89 seconds
Started Mar 24 12:49:09 PM PDT 24
Finished Mar 24 12:49:11 PM PDT 24
Peak memory 193064 kb
Host smart-1bc8825f-f508-48d7-a9c5-a07bb9b41a90
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817579209 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.3817579209
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.1387456722
Short name T349
Test name
Test status
Simulation time 355518168 ps
CPU time 0.71 seconds
Started Mar 24 12:49:09 PM PDT 24
Finished Mar 24 12:49:10 PM PDT 24
Peak memory 183704 kb
Host smart-5c9f52fb-ab23-4afa-a325-0a4f2a239ef6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387456722 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.1387456722
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.1536508194
Short name T26
Test name
Test status
Simulation time 1280535097 ps
CPU time 4.21 seconds
Started Mar 24 12:49:03 PM PDT 24
Finished Mar 24 12:49:08 PM PDT 24
Peak memory 193268 kb
Host smart-3ad58234-a0f1-445b-ba23-ffc4c83a810a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536508194 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.ao
n_timer_same_csr_outstanding.1536508194
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.214571141
Short name T355
Test name
Test status
Simulation time 720429546 ps
CPU time 2.37 seconds
Started Mar 24 12:49:02 PM PDT 24
Finished Mar 24 12:49:05 PM PDT 24
Peak memory 198608 kb
Host smart-1abf36a9-dfb7-4e7a-baec-3bae0e8de809
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214571141 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.214571141
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.525726892
Short name T360
Test name
Test status
Simulation time 8774951284 ps
CPU time 11.42 seconds
Started Mar 24 12:49:01 PM PDT 24
Finished Mar 24 12:49:12 PM PDT 24
Peak memory 198008 kb
Host smart-bf51527a-e5f2-43f1-8830-e3aefe8a2156
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525726892 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl
_intg_err.525726892
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.1473132054
Short name T405
Test name
Test status
Simulation time 664148398 ps
CPU time 0.88 seconds
Started Mar 24 12:49:02 PM PDT 24
Finished Mar 24 12:49:03 PM PDT 24
Peak memory 196860 kb
Host smart-d2a4e5cb-171e-4160-97ee-29e457ad5cfb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473132054 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.1473132054
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.1556133524
Short name T420
Test name
Test status
Simulation time 460918736 ps
CPU time 0.74 seconds
Started Mar 24 12:49:01 PM PDT 24
Finished Mar 24 12:49:02 PM PDT 24
Peak memory 183816 kb
Host smart-55ea62af-e2ee-42ee-8692-efa37393535d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556133524 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.1556133524
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.342536736
Short name T325
Test name
Test status
Simulation time 514260391 ps
CPU time 0.68 seconds
Started Mar 24 12:49:05 PM PDT 24
Finished Mar 24 12:49:05 PM PDT 24
Peak memory 183692 kb
Host smart-e9d5fa6c-8ea7-4aae-a7fa-eef9cddb53ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342536736 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.342536736
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.1631164631
Short name T27
Test name
Test status
Simulation time 1250381078 ps
CPU time 1.06 seconds
Started Mar 24 12:49:04 PM PDT 24
Finished Mar 24 12:49:05 PM PDT 24
Peak memory 193132 kb
Host smart-8450df00-7a56-4ccd-af5e-05352fc95828
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631164631 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao
n_timer_same_csr_outstanding.1631164631
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.3934737379
Short name T305
Test name
Test status
Simulation time 461344021 ps
CPU time 1.56 seconds
Started Mar 24 12:49:01 PM PDT 24
Finished Mar 24 12:49:03 PM PDT 24
Peak memory 198588 kb
Host smart-24df5421-15bc-48ca-ac3f-4f0ca5b6dab7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934737379 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.3934737379
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.329623625
Short name T392
Test name
Test status
Simulation time 8299038928 ps
CPU time 3.46 seconds
Started Mar 24 12:49:00 PM PDT 24
Finished Mar 24 12:49:03 PM PDT 24
Peak memory 197976 kb
Host smart-111f8a2a-9f0c-408f-9aca-6f01852fba73
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329623625 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl
_intg_err.329623625
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.316426950
Short name T286
Test name
Test status
Simulation time 738939281 ps
CPU time 1.32 seconds
Started Mar 24 12:48:44 PM PDT 24
Finished Mar 24 12:48:46 PM PDT 24
Peak memory 192032 kb
Host smart-e4ba17c9-a465-40a4-8e86-ac0d921526b6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316426950 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_al
iasing.316426950
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.719456269
Short name T31
Test name
Test status
Simulation time 1173463657 ps
CPU time 0.82 seconds
Started Mar 24 12:48:39 PM PDT 24
Finished Mar 24 12:48:40 PM PDT 24
Peak memory 183672 kb
Host smart-a3c39087-fe7e-43e9-8868-966c8b36782e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719456269 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_hw
_reset.719456269
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.3006686181
Short name T418
Test name
Test status
Simulation time 385345515 ps
CPU time 1.18 seconds
Started Mar 24 12:48:43 PM PDT 24
Finished Mar 24 12:48:44 PM PDT 24
Peak memory 196436 kb
Host smart-b84a06e5-855b-4aae-9a2a-8cc317bb4fb3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006686181 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.3006686181
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.1841211338
Short name T60
Test name
Test status
Simulation time 317699196 ps
CPU time 1.05 seconds
Started Mar 24 12:48:38 PM PDT 24
Finished Mar 24 12:48:39 PM PDT 24
Peak memory 193356 kb
Host smart-9331fd38-1b46-48bc-9858-61a814db2c00
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841211338 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.1841211338
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.844815029
Short name T362
Test name
Test status
Simulation time 512639062 ps
CPU time 1.24 seconds
Started Mar 24 12:48:39 PM PDT 24
Finished Mar 24 12:48:40 PM PDT 24
Peak memory 183684 kb
Host smart-27d42712-692c-4d26-8fef-abddbcdf9b56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844815029 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.844815029
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.1662603724
Short name T288
Test name
Test status
Simulation time 495656056 ps
CPU time 0.69 seconds
Started Mar 24 12:48:37 PM PDT 24
Finished Mar 24 12:48:38 PM PDT 24
Peak memory 183708 kb
Host smart-05bd475a-cdee-4c56-8c8f-44c57660a242
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662603724 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_t
imer_mem_partial_access.1662603724
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.3402064659
Short name T401
Test name
Test status
Simulation time 375729983 ps
CPU time 0.8 seconds
Started Mar 24 12:48:38 PM PDT 24
Finished Mar 24 12:48:39 PM PDT 24
Peak memory 183772 kb
Host smart-72e08730-8c7d-4f58-b026-6fd10ef20f8c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402064659 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_w
alk.3402064659
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.936026906
Short name T66
Test name
Test status
Simulation time 2903433818 ps
CPU time 2.95 seconds
Started Mar 24 12:48:43 PM PDT 24
Finished Mar 24 12:48:46 PM PDT 24
Peak memory 194612 kb
Host smart-267b5b23-3bf6-4be9-847e-86646f444ed8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936026906 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_
timer_same_csr_outstanding.936026906
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.3071154918
Short name T396
Test name
Test status
Simulation time 410399856 ps
CPU time 1.58 seconds
Started Mar 24 12:48:39 PM PDT 24
Finished Mar 24 12:48:41 PM PDT 24
Peak memory 198460 kb
Host smart-33874364-fa6a-45b8-b7f8-6ed3af142395
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071154918 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.3071154918
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.564683744
Short name T367
Test name
Test status
Simulation time 9045884890 ps
CPU time 3.87 seconds
Started Mar 24 12:48:40 PM PDT 24
Finished Mar 24 12:48:44 PM PDT 24
Peak memory 198056 kb
Host smart-68f16748-c9c9-458c-a64b-74873e5cbd9e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564683744 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_
intg_err.564683744
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.3870891962
Short name T287
Test name
Test status
Simulation time 354403001 ps
CPU time 1.09 seconds
Started Mar 24 12:49:08 PM PDT 24
Finished Mar 24 12:49:09 PM PDT 24
Peak memory 183560 kb
Host smart-63a12567-f521-495c-a0c6-091142309229
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870891962 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.3870891962
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.1417869885
Short name T395
Test name
Test status
Simulation time 352795733 ps
CPU time 1.02 seconds
Started Mar 24 12:49:09 PM PDT 24
Finished Mar 24 12:49:11 PM PDT 24
Peak memory 183700 kb
Host smart-adeeb86a-d7b5-43f0-8398-5db0766e137f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417869885 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.1417869885
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.1867472381
Short name T397
Test name
Test status
Simulation time 362126489 ps
CPU time 0.78 seconds
Started Mar 24 12:49:05 PM PDT 24
Finished Mar 24 12:49:06 PM PDT 24
Peak memory 183696 kb
Host smart-59e7cdb3-b22a-4429-b624-29071cd1d8b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867472381 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.1867472381
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.3081535036
Short name T309
Test name
Test status
Simulation time 491545733 ps
CPU time 0.63 seconds
Started Mar 24 12:49:01 PM PDT 24
Finished Mar 24 12:49:02 PM PDT 24
Peak memory 183912 kb
Host smart-b1a8a802-235a-4a00-bcbe-9b1f10389760
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081535036 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.3081535036
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.2799460933
Short name T366
Test name
Test status
Simulation time 328330587 ps
CPU time 0.69 seconds
Started Mar 24 12:49:04 PM PDT 24
Finished Mar 24 12:49:05 PM PDT 24
Peak memory 183692 kb
Host smart-626cbbfe-abee-4cf7-91ac-bc5f91db778f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799460933 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.2799460933
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.1178005359
Short name T311
Test name
Test status
Simulation time 518750643 ps
CPU time 0.69 seconds
Started Mar 24 12:49:02 PM PDT 24
Finished Mar 24 12:49:03 PM PDT 24
Peak memory 183628 kb
Host smart-0c9a9b22-3ded-46e1-ae6b-4eb4e793d167
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178005359 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.1178005359
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.1827551993
Short name T410
Test name
Test status
Simulation time 504179024 ps
CPU time 0.66 seconds
Started Mar 24 12:49:03 PM PDT 24
Finished Mar 24 12:49:03 PM PDT 24
Peak memory 183644 kb
Host smart-b255ccf2-82d7-4854-9b46-1ac8eb9611c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827551993 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.1827551993
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.3546224206
Short name T322
Test name
Test status
Simulation time 405473183 ps
CPU time 0.69 seconds
Started Mar 24 12:49:03 PM PDT 24
Finished Mar 24 12:49:04 PM PDT 24
Peak memory 183556 kb
Host smart-aeb82fb5-2470-4902-90e4-4f373e90e9bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546224206 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.3546224206
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.2044631255
Short name T380
Test name
Test status
Simulation time 354116314 ps
CPU time 1.06 seconds
Started Mar 24 12:49:09 PM PDT 24
Finished Mar 24 12:49:10 PM PDT 24
Peak memory 183704 kb
Host smart-b10f3d74-f9b5-46bb-b0a2-79f395e7de09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044631255 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.2044631255
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.412648060
Short name T377
Test name
Test status
Simulation time 374777414 ps
CPU time 0.78 seconds
Started Mar 24 12:49:04 PM PDT 24
Finished Mar 24 12:49:05 PM PDT 24
Peak memory 183728 kb
Host smart-7e942b23-62c1-43ed-a7cb-2e6211fc6371
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412648060 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.412648060
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.4000394835
Short name T63
Test name
Test status
Simulation time 403862799 ps
CPU time 0.75 seconds
Started Mar 24 12:48:41 PM PDT 24
Finished Mar 24 12:48:42 PM PDT 24
Peak memory 183720 kb
Host smart-9477e6f5-7287-4084-9283-a285e85b4042
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000394835 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_a
liasing.4000394835
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.3577196583
Short name T61
Test name
Test status
Simulation time 7205856754 ps
CPU time 11.4 seconds
Started Mar 24 12:48:45 PM PDT 24
Finished Mar 24 12:48:57 PM PDT 24
Peak memory 192264 kb
Host smart-6e6d4e45-f978-48df-bf98-ade088861bf2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577196583 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_b
it_bash.3577196583
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.3634746938
Short name T331
Test name
Test status
Simulation time 1210859272 ps
CPU time 1.48 seconds
Started Mar 24 12:48:41 PM PDT 24
Finished Mar 24 12:48:42 PM PDT 24
Peak memory 183840 kb
Host smart-0000cb9d-cccd-4ffc-a6ee-3ab52e75d0d3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634746938 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_h
w_reset.3634746938
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.3567820997
Short name T381
Test name
Test status
Simulation time 527403147 ps
CPU time 1.28 seconds
Started Mar 24 12:48:46 PM PDT 24
Finished Mar 24 12:48:47 PM PDT 24
Peak memory 196076 kb
Host smart-caae7c32-7517-4457-89e3-e136d425da2d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567820997 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.3567820997
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.1519547250
Short name T51
Test name
Test status
Simulation time 497997251 ps
CPU time 1.37 seconds
Started Mar 24 12:48:43 PM PDT 24
Finished Mar 24 12:48:44 PM PDT 24
Peak memory 183788 kb
Host smart-297ca727-8617-414a-83e8-0788db2a8bd5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519547250 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.1519547250
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.3258610290
Short name T375
Test name
Test status
Simulation time 442919638 ps
CPU time 1.18 seconds
Started Mar 24 12:48:44 PM PDT 24
Finished Mar 24 12:48:45 PM PDT 24
Peak memory 183684 kb
Host smart-c7773cfc-1fb6-40fe-b4fd-ed1a9bacce11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258610290 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.3258610290
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.1528283264
Short name T303
Test name
Test status
Simulation time 365213513 ps
CPU time 0.65 seconds
Started Mar 24 12:48:47 PM PDT 24
Finished Mar 24 12:48:47 PM PDT 24
Peak memory 183696 kb
Host smart-7d3a9af7-1307-49be-817d-0b39f6a06fcc
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528283264 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_t
imer_mem_partial_access.1528283264
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.3806962688
Short name T301
Test name
Test status
Simulation time 506066676 ps
CPU time 0.62 seconds
Started Mar 24 12:48:42 PM PDT 24
Finished Mar 24 12:48:43 PM PDT 24
Peak memory 183756 kb
Host smart-c5b54e88-6ad9-4014-86de-77e8a866da6c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806962688 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_w
alk.3806962688
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.797675867
Short name T370
Test name
Test status
Simulation time 1287924963 ps
CPU time 1.59 seconds
Started Mar 24 12:48:42 PM PDT 24
Finished Mar 24 12:48:44 PM PDT 24
Peak memory 183896 kb
Host smart-7c973bd6-accd-414d-b1d7-8f55104fecc5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797675867 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_
timer_same_csr_outstanding.797675867
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.3728515420
Short name T337
Test name
Test status
Simulation time 669829499 ps
CPU time 1.29 seconds
Started Mar 24 12:48:43 PM PDT 24
Finished Mar 24 12:48:45 PM PDT 24
Peak memory 198432 kb
Host smart-cc54b1cb-43ea-4f1a-92f7-792c81f8b552
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728515420 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.3728515420
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.2168206506
Short name T34
Test name
Test status
Simulation time 4341078775 ps
CPU time 7.62 seconds
Started Mar 24 12:48:47 PM PDT 24
Finished Mar 24 12:48:55 PM PDT 24
Peak memory 197356 kb
Host smart-31a8e58a-ce10-4ac2-9646-6876af13f85c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168206506 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl
_intg_err.2168206506
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.1154927592
Short name T327
Test name
Test status
Simulation time 439487054 ps
CPU time 1.24 seconds
Started Mar 24 12:49:08 PM PDT 24
Finished Mar 24 12:49:09 PM PDT 24
Peak memory 183556 kb
Host smart-424df504-95b1-4c98-bef7-d9f9783d32a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154927592 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.1154927592
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.3097164302
Short name T373
Test name
Test status
Simulation time 349302909 ps
CPU time 0.62 seconds
Started Mar 24 12:49:12 PM PDT 24
Finished Mar 24 12:49:13 PM PDT 24
Peak memory 183492 kb
Host smart-df65c55c-6d49-44c7-9bba-1b43cb731c59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097164302 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.3097164302
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.3073629016
Short name T416
Test name
Test status
Simulation time 398399153 ps
CPU time 0.79 seconds
Started Mar 24 12:49:12 PM PDT 24
Finished Mar 24 12:49:13 PM PDT 24
Peak memory 183592 kb
Host smart-b57c5156-df6b-4d51-8a49-9f4e36ccc67c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073629016 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.3073629016
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.1309945031
Short name T402
Test name
Test status
Simulation time 447618872 ps
CPU time 1.2 seconds
Started Mar 24 12:49:07 PM PDT 24
Finished Mar 24 12:49:09 PM PDT 24
Peak memory 183696 kb
Host smart-e8fc4eaa-22c8-4e07-9c52-7489299861f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309945031 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.1309945031
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.3841446991
Short name T297
Test name
Test status
Simulation time 288476012 ps
CPU time 0.99 seconds
Started Mar 24 12:49:07 PM PDT 24
Finished Mar 24 12:49:08 PM PDT 24
Peak memory 183700 kb
Host smart-cfe1e597-6be2-46e5-bcc3-8fb8e8a8741b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841446991 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.3841446991
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.4168459744
Short name T356
Test name
Test status
Simulation time 354739821 ps
CPU time 0.65 seconds
Started Mar 24 12:49:06 PM PDT 24
Finished Mar 24 12:49:07 PM PDT 24
Peak memory 183704 kb
Host smart-800b404f-d08b-4a3c-b10e-96b1f20f8f03
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168459744 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.4168459744
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.400268701
Short name T364
Test name
Test status
Simulation time 485739812 ps
CPU time 0.71 seconds
Started Mar 24 12:49:07 PM PDT 24
Finished Mar 24 12:49:08 PM PDT 24
Peak memory 183712 kb
Host smart-5afe83f7-63d3-4457-a714-d4fe59da6444
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400268701 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.400268701
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.270683886
Short name T318
Test name
Test status
Simulation time 482042271 ps
CPU time 0.79 seconds
Started Mar 24 12:49:10 PM PDT 24
Finished Mar 24 12:49:11 PM PDT 24
Peak memory 183704 kb
Host smart-0b61ed2d-3bec-4c1a-9411-67a8278ccabd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270683886 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.270683886
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.3846148079
Short name T285
Test name
Test status
Simulation time 428379951 ps
CPU time 1.2 seconds
Started Mar 24 12:49:06 PM PDT 24
Finished Mar 24 12:49:07 PM PDT 24
Peak memory 183644 kb
Host smart-9e43e713-97f5-4bd9-a727-419fe275e1c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846148079 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.3846148079
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.4248218118
Short name T352
Test name
Test status
Simulation time 346988655 ps
CPU time 0.82 seconds
Started Mar 24 12:49:07 PM PDT 24
Finished Mar 24 12:49:08 PM PDT 24
Peak memory 183544 kb
Host smart-7857cad7-d041-4ccc-83f5-bd47feef6ba7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248218118 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.4248218118
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.3858060549
Short name T53
Test name
Test status
Simulation time 515561813 ps
CPU time 1.45 seconds
Started Mar 24 12:48:46 PM PDT 24
Finished Mar 24 12:48:47 PM PDT 24
Peak memory 183756 kb
Host smart-e94dc686-2d60-457b-88e3-3cf3ae0e17f9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858060549 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_a
liasing.3858060549
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.1393289277
Short name T55
Test name
Test status
Simulation time 9708204996 ps
CPU time 3.11 seconds
Started Mar 24 12:48:41 PM PDT 24
Finished Mar 24 12:48:44 PM PDT 24
Peak memory 192336 kb
Host smart-47f64217-b521-468f-905e-8b9f54619faf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393289277 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_b
it_bash.1393289277
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.2124389186
Short name T300
Test name
Test status
Simulation time 826959758 ps
CPU time 0.67 seconds
Started Mar 24 12:48:47 PM PDT 24
Finished Mar 24 12:48:48 PM PDT 24
Peak memory 183712 kb
Host smart-f2e1ff7b-d3af-4b70-a335-570411e93b0f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124389186 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_h
w_reset.2124389186
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.397123645
Short name T346
Test name
Test status
Simulation time 497505529 ps
CPU time 0.88 seconds
Started Mar 24 12:48:41 PM PDT 24
Finished Mar 24 12:48:42 PM PDT 24
Peak memory 196456 kb
Host smart-eeefafbf-887a-44ee-ba76-5789f28e897a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397123645 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.397123645
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.3879991468
Short name T292
Test name
Test status
Simulation time 454388635 ps
CPU time 0.79 seconds
Started Mar 24 12:48:43 PM PDT 24
Finished Mar 24 12:48:44 PM PDT 24
Peak memory 192172 kb
Host smart-1ed4b715-fcb4-42e8-862a-f773a42447a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879991468 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.3879991468
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.2379723577
Short name T419
Test name
Test status
Simulation time 456835301 ps
CPU time 1.15 seconds
Started Mar 24 12:48:46 PM PDT 24
Finished Mar 24 12:48:47 PM PDT 24
Peak memory 183684 kb
Host smart-d9867dbd-adf6-4e8c-963f-70fd7b028f9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379723577 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.2379723577
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.425380475
Short name T291
Test name
Test status
Simulation time 276100548 ps
CPU time 0.97 seconds
Started Mar 24 12:48:43 PM PDT 24
Finished Mar 24 12:48:44 PM PDT 24
Peak memory 183676 kb
Host smart-06610a3d-4bb6-414b-ab69-58400fc3e785
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425380475 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_ti
mer_mem_partial_access.425380475
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.1016615960
Short name T399
Test name
Test status
Simulation time 450075434 ps
CPU time 1.11 seconds
Started Mar 24 12:48:44 PM PDT 24
Finished Mar 24 12:48:45 PM PDT 24
Peak memory 183744 kb
Host smart-8e3980f1-e3e8-4d1a-b575-9b2f3b606bbe
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016615960 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_w
alk.1016615960
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.365533177
Short name T382
Test name
Test status
Simulation time 846401632 ps
CPU time 1.62 seconds
Started Mar 24 12:48:45 PM PDT 24
Finished Mar 24 12:48:46 PM PDT 24
Peak memory 193348 kb
Host smart-e857ae53-a513-45bf-ac31-0c72dbef39e6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365533177 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_
timer_same_csr_outstanding.365533177
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.1152338103
Short name T414
Test name
Test status
Simulation time 560490514 ps
CPU time 2.68 seconds
Started Mar 24 12:48:47 PM PDT 24
Finished Mar 24 12:48:50 PM PDT 24
Peak memory 198612 kb
Host smart-fabca24d-f3ae-4012-8acc-4f79df40ad98
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152338103 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.1152338103
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.1821014649
Short name T33
Test name
Test status
Simulation time 4868639558 ps
CPU time 4.23 seconds
Started Mar 24 12:48:43 PM PDT 24
Finished Mar 24 12:48:47 PM PDT 24
Peak memory 196432 kb
Host smart-a16ba5d6-904c-4e41-82a0-f213fbc1adae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821014649 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl
_intg_err.1821014649
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.869307722
Short name T340
Test name
Test status
Simulation time 334091753 ps
CPU time 0.81 seconds
Started Mar 24 12:49:12 PM PDT 24
Finished Mar 24 12:49:13 PM PDT 24
Peak memory 183468 kb
Host smart-af65965c-470e-47dd-9f77-20b6abd7b9de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869307722 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.869307722
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.2333520876
Short name T321
Test name
Test status
Simulation time 340995765 ps
CPU time 0.85 seconds
Started Mar 24 12:49:08 PM PDT 24
Finished Mar 24 12:49:08 PM PDT 24
Peak memory 183692 kb
Host smart-91554fd6-bfe1-4ae2-a774-df843f402248
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333520876 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.2333520876
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.694225311
Short name T406
Test name
Test status
Simulation time 396666792 ps
CPU time 1.19 seconds
Started Mar 24 12:49:10 PM PDT 24
Finished Mar 24 12:49:12 PM PDT 24
Peak memory 183720 kb
Host smart-5de10b4f-b3a0-4375-bc69-a961bddb67e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694225311 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.694225311
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.28743402
Short name T398
Test name
Test status
Simulation time 406109111 ps
CPU time 0.73 seconds
Started Mar 24 12:49:05 PM PDT 24
Finished Mar 24 12:49:06 PM PDT 24
Peak memory 183716 kb
Host smart-a030250b-9525-468b-8957-a5303120a47c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28743402 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.28743402
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.426567521
Short name T385
Test name
Test status
Simulation time 456336704 ps
CPU time 1.23 seconds
Started Mar 24 12:49:08 PM PDT 24
Finished Mar 24 12:49:09 PM PDT 24
Peak memory 183692 kb
Host smart-18113b1a-1741-44f8-b66e-0550c8d4b655
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426567521 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.426567521
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.1054261120
Short name T314
Test name
Test status
Simulation time 423824055 ps
CPU time 0.79 seconds
Started Mar 24 12:49:10 PM PDT 24
Finished Mar 24 12:49:12 PM PDT 24
Peak memory 183700 kb
Host smart-3e201f90-0126-4802-93f4-fa60c95dca45
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054261120 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.1054261120
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.4005456479
Short name T347
Test name
Test status
Simulation time 391954529 ps
CPU time 1.12 seconds
Started Mar 24 12:49:07 PM PDT 24
Finished Mar 24 12:49:08 PM PDT 24
Peak memory 183704 kb
Host smart-13b10a5e-b717-4818-9cfa-0d987d43a249
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005456479 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.4005456479
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.2556396563
Short name T378
Test name
Test status
Simulation time 440000232 ps
CPU time 1.16 seconds
Started Mar 24 12:49:10 PM PDT 24
Finished Mar 24 12:49:12 PM PDT 24
Peak memory 183704 kb
Host smart-bef7793b-76ed-417b-9cf1-7284a5268cfa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556396563 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.2556396563
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.453378807
Short name T376
Test name
Test status
Simulation time 500412699 ps
CPU time 0.7 seconds
Started Mar 24 12:49:06 PM PDT 24
Finished Mar 24 12:49:06 PM PDT 24
Peak memory 183608 kb
Host smart-ffbd392d-69dc-4e84-84d2-cd0123619878
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453378807 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.453378807
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.1019058491
Short name T279
Test name
Test status
Simulation time 433697246 ps
CPU time 0.65 seconds
Started Mar 24 12:49:12 PM PDT 24
Finished Mar 24 12:49:13 PM PDT 24
Peak memory 183704 kb
Host smart-c595c95d-9720-4342-8deb-29e783f02bbd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019058491 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.1019058491
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.3645530350
Short name T306
Test name
Test status
Simulation time 507693036 ps
CPU time 1.1 seconds
Started Mar 24 12:48:50 PM PDT 24
Finished Mar 24 12:48:51 PM PDT 24
Peak memory 198404 kb
Host smart-b031b216-a231-4500-9eea-068373d15ab9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645530350 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.3645530350
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.1161019442
Short name T59
Test name
Test status
Simulation time 557908247 ps
CPU time 0.79 seconds
Started Mar 24 12:48:49 PM PDT 24
Finished Mar 24 12:48:49 PM PDT 24
Peak memory 193116 kb
Host smart-602bb2d1-e4a3-4d30-b74c-9034331f7752
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161019442 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.1161019442
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.1642976040
Short name T329
Test name
Test status
Simulation time 505859473 ps
CPU time 0.7 seconds
Started Mar 24 12:48:42 PM PDT 24
Finished Mar 24 12:48:43 PM PDT 24
Peak memory 183716 kb
Host smart-c0be65f8-b340-4976-9c4e-916a53aeb2e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642976040 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.1642976040
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.1539535273
Short name T68
Test name
Test status
Simulation time 2603358289 ps
CPU time 2.16 seconds
Started Mar 24 12:48:49 PM PDT 24
Finished Mar 24 12:48:51 PM PDT 24
Peak memory 183896 kb
Host smart-72c7f2b7-53ff-4040-aeb7-cdd59ff6776b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539535273 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon
_timer_same_csr_outstanding.1539535273
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.27207826
Short name T315
Test name
Test status
Simulation time 529788680 ps
CPU time 2.6 seconds
Started Mar 24 12:48:44 PM PDT 24
Finished Mar 24 12:48:46 PM PDT 24
Peak memory 198588 kb
Host smart-6b9003f4-3876-47e8-bad8-4057f93882a0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27207826 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.27207826
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.403111463
Short name T391
Test name
Test status
Simulation time 4493663446 ps
CPU time 7.27 seconds
Started Mar 24 12:48:47 PM PDT 24
Finished Mar 24 12:48:55 PM PDT 24
Peak memory 197324 kb
Host smart-8ecc83b0-57f9-48cf-b9b5-b725ff4aec52
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403111463 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_
intg_err.403111463
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.246214513
Short name T348
Test name
Test status
Simulation time 520997973 ps
CPU time 0.87 seconds
Started Mar 24 12:48:50 PM PDT 24
Finished Mar 24 12:48:51 PM PDT 24
Peak memory 197172 kb
Host smart-0ea3c90e-5bf0-4c5a-b85c-6a44130eca31
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246214513 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.246214513
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.1168838960
Short name T332
Test name
Test status
Simulation time 429495864 ps
CPU time 0.94 seconds
Started Mar 24 12:48:50 PM PDT 24
Finished Mar 24 12:48:51 PM PDT 24
Peak memory 184040 kb
Host smart-3c14429a-9aa0-41cc-afb0-e4021816e03b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168838960 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.1168838960
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.1254998003
Short name T328
Test name
Test status
Simulation time 351962075 ps
CPU time 1.02 seconds
Started Mar 24 12:48:49 PM PDT 24
Finished Mar 24 12:48:50 PM PDT 24
Peak memory 183672 kb
Host smart-a30c57bb-5172-4a52-8c54-22f6060a9e3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254998003 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.1254998003
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.3440638353
Short name T379
Test name
Test status
Simulation time 1410365771 ps
CPU time 2.79 seconds
Started Mar 24 12:48:50 PM PDT 24
Finished Mar 24 12:48:53 PM PDT 24
Peak memory 193272 kb
Host smart-7565fc32-b76d-40b4-a74a-724aaf400faf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440638353 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon
_timer_same_csr_outstanding.3440638353
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.3166432059
Short name T357
Test name
Test status
Simulation time 352006568 ps
CPU time 1.46 seconds
Started Mar 24 12:48:51 PM PDT 24
Finished Mar 24 12:48:53 PM PDT 24
Peak memory 198044 kb
Host smart-c0dca85a-bc6f-42bf-9094-b249c019b81f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166432059 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.3166432059
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.490890508
Short name T351
Test name
Test status
Simulation time 8439904587 ps
CPU time 3.98 seconds
Started Mar 24 12:48:49 PM PDT 24
Finished Mar 24 12:48:53 PM PDT 24
Peak memory 197816 kb
Host smart-b3f18ec3-cd5f-4431-9936-770ef7919d93
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490890508 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_
intg_err.490890508
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.1044355419
Short name T299
Test name
Test status
Simulation time 390814153 ps
CPU time 0.79 seconds
Started Mar 24 12:48:50 PM PDT 24
Finished Mar 24 12:48:51 PM PDT 24
Peak memory 196388 kb
Host smart-51f410ab-3e11-4efc-b2f2-acfa8015d3c6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044355419 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.1044355419
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.1366142154
Short name T361
Test name
Test status
Simulation time 549835348 ps
CPU time 0.81 seconds
Started Mar 24 12:48:49 PM PDT 24
Finished Mar 24 12:48:50 PM PDT 24
Peak memory 183628 kb
Host smart-8960ee43-1d43-4177-883d-c952c6d97976
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366142154 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.1366142154
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.251192425
Short name T296
Test name
Test status
Simulation time 336745897 ps
CPU time 0.65 seconds
Started Mar 24 12:48:50 PM PDT 24
Finished Mar 24 12:48:50 PM PDT 24
Peak memory 183600 kb
Host smart-bc2b1598-b900-4024-93f6-b4b98a29d7ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251192425 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.251192425
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.355913687
Short name T394
Test name
Test status
Simulation time 1617185975 ps
CPU time 1.03 seconds
Started Mar 24 12:48:49 PM PDT 24
Finished Mar 24 12:48:50 PM PDT 24
Peak memory 193508 kb
Host smart-20352f88-c64e-4599-a0e7-b72cf7ad2119
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355913687 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_
timer_same_csr_outstanding.355913687
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.3803647718
Short name T307
Test name
Test status
Simulation time 897987241 ps
CPU time 1.38 seconds
Started Mar 24 12:48:49 PM PDT 24
Finished Mar 24 12:48:50 PM PDT 24
Peak memory 198640 kb
Host smart-b78cdb25-ab0f-49f9-b939-14b45a6dd6eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803647718 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.3803647718
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.1895628868
Short name T102
Test name
Test status
Simulation time 4146386022 ps
CPU time 2.43 seconds
Started Mar 24 12:48:49 PM PDT 24
Finished Mar 24 12:48:52 PM PDT 24
Peak memory 197608 kb
Host smart-8bbeb0be-aa70-46fa-9f7c-396f31b9d2ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895628868 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl
_intg_err.1895628868
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.1097834547
Short name T390
Test name
Test status
Simulation time 528272267 ps
CPU time 0.71 seconds
Started Mar 24 12:48:53 PM PDT 24
Finished Mar 24 12:48:54 PM PDT 24
Peak memory 194812 kb
Host smart-bbb25c1a-6f3f-4f17-b839-b7aae39b810c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097834547 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.1097834547
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.424100932
Short name T369
Test name
Test status
Simulation time 386599952 ps
CPU time 0.62 seconds
Started Mar 24 12:48:50 PM PDT 24
Finished Mar 24 12:48:51 PM PDT 24
Peak memory 193052 kb
Host smart-d6e682d6-4119-44fc-ab94-ed031aa20155
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424100932 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.424100932
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.2561272261
Short name T371
Test name
Test status
Simulation time 498884670 ps
CPU time 0.65 seconds
Started Mar 24 12:48:52 PM PDT 24
Finished Mar 24 12:48:53 PM PDT 24
Peak memory 183684 kb
Host smart-05e34987-635c-4317-af2e-ec2dbc81b75a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561272261 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.2561272261
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.1043995729
Short name T413
Test name
Test status
Simulation time 1163481031 ps
CPU time 3.37 seconds
Started Mar 24 12:48:51 PM PDT 24
Finished Mar 24 12:48:55 PM PDT 24
Peak memory 183780 kb
Host smart-dbc2f6ab-3a3f-4c23-9c9c-d1f5b17a67a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043995729 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon
_timer_same_csr_outstanding.1043995729
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.3701053852
Short name T293
Test name
Test status
Simulation time 427582499 ps
CPU time 1.7 seconds
Started Mar 24 12:48:48 PM PDT 24
Finished Mar 24 12:48:50 PM PDT 24
Peak memory 198592 kb
Host smart-478b4c97-ca96-446f-b2c6-f4dc8a555cf3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701053852 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.3701053852
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.2488223793
Short name T412
Test name
Test status
Simulation time 4430860945 ps
CPU time 7.19 seconds
Started Mar 24 12:48:50 PM PDT 24
Finished Mar 24 12:48:57 PM PDT 24
Peak memory 196572 kb
Host smart-415fb246-b83b-48e2-8273-978150617fa3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488223793 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl
_intg_err.2488223793
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.3569319252
Short name T28
Test name
Test status
Simulation time 483362774 ps
CPU time 0.81 seconds
Started Mar 24 12:48:48 PM PDT 24
Finished Mar 24 12:48:49 PM PDT 24
Peak memory 196996 kb
Host smart-be1d5d7e-bf15-4f1d-bc4e-7852f2713c85
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569319252 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.3569319252
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.3169871621
Short name T358
Test name
Test status
Simulation time 357853297 ps
CPU time 0.81 seconds
Started Mar 24 12:48:48 PM PDT 24
Finished Mar 24 12:48:49 PM PDT 24
Peak memory 183892 kb
Host smart-9911eca4-6d03-4354-8c9e-def87040a8a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169871621 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.3169871621
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.1013902564
Short name T324
Test name
Test status
Simulation time 278531975 ps
CPU time 0.71 seconds
Started Mar 24 12:48:50 PM PDT 24
Finished Mar 24 12:48:51 PM PDT 24
Peak memory 183712 kb
Host smart-ebf1b6ae-aa78-4e95-9e22-c1d97dc0b323
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013902564 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.1013902564
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.3571884411
Short name T344
Test name
Test status
Simulation time 1334844664 ps
CPU time 4.04 seconds
Started Mar 24 12:48:48 PM PDT 24
Finished Mar 24 12:48:53 PM PDT 24
Peak memory 193284 kb
Host smart-b876699c-a9f7-4ba5-9571-fbeac1b06f89
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571884411 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon
_timer_same_csr_outstanding.3571884411
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.2915075464
Short name T339
Test name
Test status
Simulation time 537120697 ps
CPU time 1.74 seconds
Started Mar 24 12:48:53 PM PDT 24
Finished Mar 24 12:48:54 PM PDT 24
Peak memory 198400 kb
Host smart-6056654c-7d85-401e-9808-6d7024106179
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915075464 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.2915075464
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.2599878010
Short name T365
Test name
Test status
Simulation time 4720920500 ps
CPU time 7.32 seconds
Started Mar 24 12:48:53 PM PDT 24
Finished Mar 24 12:49:01 PM PDT 24
Peak memory 197624 kb
Host smart-c83b0856-5f8e-4a19-af70-7bebffbb2936
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599878010 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl
_intg_err.2599878010
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_jump.1330568910
Short name T278
Test name
Test status
Simulation time 578263811 ps
CPU time 1.44 seconds
Started Mar 24 12:49:39 PM PDT 24
Finished Mar 24 12:49:41 PM PDT 24
Peak memory 183076 kb
Host smart-67376cac-a38a-4829-b956-6bdfe8e89c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330568910 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.1330568910
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.2221574138
Short name T155
Test name
Test status
Simulation time 29219026287 ps
CPU time 43.56 seconds
Started Mar 24 12:49:36 PM PDT 24
Finished Mar 24 12:50:20 PM PDT 24
Peak memory 183148 kb
Host smart-87e0238b-063d-479d-931f-249f9e4a5797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221574138 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.2221574138
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.186293110
Short name T203
Test name
Test status
Simulation time 408218035 ps
CPU time 0.85 seconds
Started Mar 24 12:49:38 PM PDT 24
Finished Mar 24 12:49:44 PM PDT 24
Peak memory 183044 kb
Host smart-7ba77c3f-6eb1-442d-b341-9cd9d057d5d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186293110 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.186293110
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.46117801
Short name T276
Test name
Test status
Simulation time 257328651174 ps
CPU time 167.44 seconds
Started Mar 24 12:49:40 PM PDT 24
Finished Mar 24 12:52:28 PM PDT 24
Peak memory 183284 kb
Host smart-958821fd-790b-4287-9bf7-1ce6c928610f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46117801 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all
.46117801
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.2400779833
Short name T259
Test name
Test status
Simulation time 31996461096 ps
CPU time 323.01 seconds
Started Mar 24 12:49:39 PM PDT 24
Finished Mar 24 12:55:02 PM PDT 24
Peak memory 198068 kb
Host smart-9b641f40-3628-4045-97eb-5123dcb4aac6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400779833 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.2400779833
Directory /workspace/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.aon_timer_jump.2106019509
Short name T170
Test name
Test status
Simulation time 538285141 ps
CPU time 1.36 seconds
Started Mar 24 12:49:37 PM PDT 24
Finished Mar 24 12:49:38 PM PDT 24
Peak memory 183316 kb
Host smart-3bd937ae-9817-40c8-be2d-0469a5ab6743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106019509 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.2106019509
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.136871074
Short name T121
Test name
Test status
Simulation time 25753589982 ps
CPU time 17.31 seconds
Started Mar 24 12:49:36 PM PDT 24
Finished Mar 24 12:49:54 PM PDT 24
Peak memory 183128 kb
Host smart-a4610d4f-63b9-48d3-abc0-300167c29131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136871074 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.136871074
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.3837607442
Short name T22
Test name
Test status
Simulation time 4086591812 ps
CPU time 2.2 seconds
Started Mar 24 12:49:41 PM PDT 24
Finished Mar 24 12:49:43 PM PDT 24
Peak memory 214688 kb
Host smart-a18de5ba-cb90-4808-95e9-2229aaaded68
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837607442 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.3837607442
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.2279432322
Short name T107
Test name
Test status
Simulation time 469043847 ps
CPU time 0.72 seconds
Started Mar 24 12:49:39 PM PDT 24
Finished Mar 24 12:49:40 PM PDT 24
Peak memory 183064 kb
Host smart-bc51c6a5-e7d8-4888-85ae-4df903df4c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279432322 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.2279432322
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.1204005937
Short name T47
Test name
Test status
Simulation time 167572214093 ps
CPU time 120.71 seconds
Started Mar 24 12:49:38 PM PDT 24
Finished Mar 24 12:51:40 PM PDT 24
Peak memory 194412 kb
Host smart-3ac9d5f8-8417-4788-ac45-13091ba12cd3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204005937 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_a
ll.1204005937
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.2342498090
Short name T168
Test name
Test status
Simulation time 55687726442 ps
CPU time 614.28 seconds
Started Mar 24 12:49:35 PM PDT 24
Finished Mar 24 12:59:49 PM PDT 24
Peak memory 197904 kb
Host smart-0a17c683-9c7c-4410-a5c1-f21390ab7357
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342498090 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.2342498090
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.aon_timer_jump.1747462929
Short name T212
Test name
Test status
Simulation time 428370972 ps
CPU time 0.68 seconds
Started Mar 24 12:49:41 PM PDT 24
Finished Mar 24 12:49:42 PM PDT 24
Peak memory 183056 kb
Host smart-713ff60b-3ec8-46ee-9532-4e8224cb0a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747462929 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.1747462929
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.3288378189
Short name T99
Test name
Test status
Simulation time 41641334731 ps
CPU time 20.41 seconds
Started Mar 24 12:49:40 PM PDT 24
Finished Mar 24 12:50:01 PM PDT 24
Peak memory 183108 kb
Host smart-e4c27524-124e-4f91-9f65-092b900df6ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288378189 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.3288378189
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.3473885831
Short name T150
Test name
Test status
Simulation time 531546749 ps
CPU time 0.75 seconds
Started Mar 24 12:49:40 PM PDT 24
Finished Mar 24 12:49:41 PM PDT 24
Peak memory 183052 kb
Host smart-b1aa3a22-e651-4ba0-b69c-026ff65f05d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473885831 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.3473885831
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_jump.2445559775
Short name T136
Test name
Test status
Simulation time 617267317 ps
CPU time 0.99 seconds
Started Mar 24 12:49:45 PM PDT 24
Finished Mar 24 12:49:46 PM PDT 24
Peak memory 183072 kb
Host smart-82b838f8-c1b3-4881-8658-f5d377505a1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445559775 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.2445559775
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.2266437404
Short name T240
Test name
Test status
Simulation time 61714274247 ps
CPU time 18.71 seconds
Started Mar 24 12:49:43 PM PDT 24
Finished Mar 24 12:50:02 PM PDT 24
Peak memory 183108 kb
Host smart-b06f8279-258e-49d7-ab4e-bd6c7a0a2070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266437404 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.2266437404
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.4146970558
Short name T10
Test name
Test status
Simulation time 463294637 ps
CPU time 1.05 seconds
Started Mar 24 12:49:45 PM PDT 24
Finished Mar 24 12:49:46 PM PDT 24
Peak memory 183080 kb
Host smart-7eec84f2-daca-4985-b4d7-d2df310726d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146970558 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.4146970558
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.4283418562
Short name T267
Test name
Test status
Simulation time 210639528761 ps
CPU time 320.96 seconds
Started Mar 24 12:49:42 PM PDT 24
Finished Mar 24 12:55:03 PM PDT 24
Peak memory 194920 kb
Host smart-5659fc21-6c46-4dad-bc73-bf485f9593fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283418562 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_
all.4283418562
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.1767276248
Short name T86
Test name
Test status
Simulation time 81546254181 ps
CPU time 154.91 seconds
Started Mar 24 12:49:42 PM PDT 24
Finished Mar 24 12:52:17 PM PDT 24
Peak memory 198040 kb
Host smart-3959305e-085c-487f-b055-d82bdebe2f76
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767276248 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand_reset.1767276248
Directory /workspace/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.aon_timer_jump.2922815230
Short name T183
Test name
Test status
Simulation time 509812097 ps
CPU time 0.74 seconds
Started Mar 24 12:49:43 PM PDT 24
Finished Mar 24 12:49:44 PM PDT 24
Peak memory 183020 kb
Host smart-5489043b-6f3c-48ed-8fdc-40c29b190d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922815230 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.2922815230
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.4165242337
Short name T231
Test name
Test status
Simulation time 16177887934 ps
CPU time 5.78 seconds
Started Mar 24 12:49:48 PM PDT 24
Finished Mar 24 12:49:53 PM PDT 24
Peak memory 183136 kb
Host smart-42401981-6c4e-46b0-84df-4e06ed35da31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165242337 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.4165242337
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.494599426
Short name T108
Test name
Test status
Simulation time 450456091 ps
CPU time 0.9 seconds
Started Mar 24 12:49:44 PM PDT 24
Finished Mar 24 12:49:45 PM PDT 24
Peak memory 182948 kb
Host smart-c7132b28-96c2-4753-927e-7843aea04c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494599426 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.494599426
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.650441845
Short name T206
Test name
Test status
Simulation time 310398341728 ps
CPU time 113.3 seconds
Started Mar 24 12:49:43 PM PDT 24
Finished Mar 24 12:51:36 PM PDT 24
Peak memory 194520 kb
Host smart-d0001b7c-eace-4fc5-999a-3cb6142601e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650441845 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_a
ll.650441845
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/13.aon_timer_jump.2326226046
Short name T272
Test name
Test status
Simulation time 385833269 ps
CPU time 0.69 seconds
Started Mar 24 12:49:42 PM PDT 24
Finished Mar 24 12:49:43 PM PDT 24
Peak memory 183024 kb
Host smart-7cfa2de8-436b-49e6-87f0-99d8481bd34e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326226046 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.2326226046
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.4183427617
Short name T237
Test name
Test status
Simulation time 19814388804 ps
CPU time 31.55 seconds
Started Mar 24 12:49:40 PM PDT 24
Finished Mar 24 12:50:12 PM PDT 24
Peak memory 183032 kb
Host smart-14d886b5-cced-4456-a3e9-df393b2ab078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183427617 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.4183427617
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.901506814
Short name T106
Test name
Test status
Simulation time 360795404 ps
CPU time 0.67 seconds
Started Mar 24 12:49:41 PM PDT 24
Finished Mar 24 12:49:41 PM PDT 24
Peak memory 183036 kb
Host smart-cff90eb6-2b3b-413c-bac2-179511ede544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901506814 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.901506814
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.102031332
Short name T263
Test name
Test status
Simulation time 258700383421 ps
CPU time 379.76 seconds
Started Mar 24 12:49:43 PM PDT 24
Finished Mar 24 12:56:02 PM PDT 24
Peak memory 194868 kb
Host smart-96f0dd2a-09b2-46a2-aef5-4b2f8fecbd43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102031332 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_a
ll.102031332
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.3972732287
Short name T92
Test name
Test status
Simulation time 246362286153 ps
CPU time 477.52 seconds
Started Mar 24 12:49:41 PM PDT 24
Finished Mar 24 12:57:39 PM PDT 24
Peak memory 197972 kb
Host smart-64e44950-6734-4563-af58-488653d3400b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972732287 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.3972732287
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.aon_timer_jump.3674629931
Short name T113
Test name
Test status
Simulation time 435825605 ps
CPU time 0.66 seconds
Started Mar 24 12:49:45 PM PDT 24
Finished Mar 24 12:49:46 PM PDT 24
Peak memory 183052 kb
Host smart-a2ada34b-dc00-4707-b857-92b3d4adeea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674629931 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.3674629931
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.3224700620
Short name T79
Test name
Test status
Simulation time 9697821674 ps
CPU time 3.74 seconds
Started Mar 24 12:49:40 PM PDT 24
Finished Mar 24 12:49:44 PM PDT 24
Peak memory 183144 kb
Host smart-e8866adf-a2f1-43b4-bd71-a1ef66098e83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224700620 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.3224700620
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.4109920798
Short name T3
Test name
Test status
Simulation time 482809753 ps
CPU time 1.24 seconds
Started Mar 24 12:49:45 PM PDT 24
Finished Mar 24 12:49:47 PM PDT 24
Peak memory 183076 kb
Host smart-6ecad516-fb06-4983-aeba-683f11e5081a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109920798 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.4109920798
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.1313329125
Short name T159
Test name
Test status
Simulation time 51623428171 ps
CPU time 21.31 seconds
Started Mar 24 12:49:47 PM PDT 24
Finished Mar 24 12:50:09 PM PDT 24
Peak memory 183100 kb
Host smart-c5d7837b-6ddb-4a1d-b568-c22ee58a6e21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313329125 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_
all.1313329125
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_jump.4011214407
Short name T199
Test name
Test status
Simulation time 586853616 ps
CPU time 0.72 seconds
Started Mar 24 12:49:49 PM PDT 24
Finished Mar 24 12:49:50 PM PDT 24
Peak memory 183292 kb
Host smart-d281c80c-bfd9-4fdf-a40e-7f6f26cfdeac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011214407 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.4011214407
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.2863712716
Short name T187
Test name
Test status
Simulation time 3264996278 ps
CPU time 5.51 seconds
Started Mar 24 12:49:57 PM PDT 24
Finished Mar 24 12:50:03 PM PDT 24
Peak memory 183140 kb
Host smart-43f1b6cb-4b1f-48ec-ac20-a8fdf53ab074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863712716 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.2863712716
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.1856543958
Short name T105
Test name
Test status
Simulation time 570501759 ps
CPU time 0.77 seconds
Started Mar 24 12:50:01 PM PDT 24
Finished Mar 24 12:50:02 PM PDT 24
Peak memory 183020 kb
Host smart-c317d62e-1c5a-4332-8d1d-830c57627d11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856543958 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.1856543958
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.527230184
Short name T208
Test name
Test status
Simulation time 48786563203 ps
CPU time 33.1 seconds
Started Mar 24 12:49:48 PM PDT 24
Finished Mar 24 12:50:26 PM PDT 24
Peak memory 182976 kb
Host smart-1e0d2e07-bfc1-45b2-be17-231ceafbc5d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527230184 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_a
ll.527230184
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_jump.3315084540
Short name T49
Test name
Test status
Simulation time 375048774 ps
CPU time 1.15 seconds
Started Mar 24 12:49:49 PM PDT 24
Finished Mar 24 12:49:51 PM PDT 24
Peak memory 182992 kb
Host smart-87377fdb-83e3-40c2-abe2-d5e9775f1235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315084540 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.3315084540
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.4162491736
Short name T93
Test name
Test status
Simulation time 4772139054 ps
CPU time 2.48 seconds
Started Mar 24 12:49:52 PM PDT 24
Finished Mar 24 12:49:55 PM PDT 24
Peak memory 183072 kb
Host smart-a114f219-0c50-41e7-a9f5-8934ba1828c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162491736 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.4162491736
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.2604602690
Short name T25
Test name
Test status
Simulation time 387024118 ps
CPU time 1.1 seconds
Started Mar 24 12:49:56 PM PDT 24
Finished Mar 24 12:49:57 PM PDT 24
Peak memory 182876 kb
Host smart-e732f000-19a0-40b1-90d7-f0770e5fe452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604602690 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.2604602690
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.260494909
Short name T19
Test name
Test status
Simulation time 155936580273 ps
CPU time 53.48 seconds
Started Mar 24 12:49:49 PM PDT 24
Finished Mar 24 12:50:43 PM PDT 24
Peak memory 193512 kb
Host smart-1d0f15f2-78c1-4a13-b329-2f55951acf62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260494909 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_a
ll.260494909
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/17.aon_timer_jump.3241321847
Short name T13
Test name
Test status
Simulation time 376094164 ps
CPU time 0.8 seconds
Started Mar 24 12:49:47 PM PDT 24
Finished Mar 24 12:49:48 PM PDT 24
Peak memory 183052 kb
Host smart-2b5a5ead-42d4-4d8f-93d3-d0374db7b580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241321847 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.3241321847
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.131231141
Short name T253
Test name
Test status
Simulation time 16614852398 ps
CPU time 3.71 seconds
Started Mar 24 12:49:49 PM PDT 24
Finished Mar 24 12:49:53 PM PDT 24
Peak memory 183044 kb
Host smart-12a747a6-db50-4ae4-af18-21a48446b144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131231141 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.131231141
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.3119406459
Short name T244
Test name
Test status
Simulation time 415265368 ps
CPU time 1.27 seconds
Started Mar 24 12:49:50 PM PDT 24
Finished Mar 24 12:49:51 PM PDT 24
Peak memory 183068 kb
Host smart-1d278808-262b-4639-83d3-351dc533f470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119406459 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.3119406459
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.1122649929
Short name T239
Test name
Test status
Simulation time 287713519769 ps
CPU time 108.65 seconds
Started Mar 24 12:49:49 PM PDT 24
Finished Mar 24 12:51:38 PM PDT 24
Peak memory 183152 kb
Host smart-961c88ec-a044-4dee-8c34-63b0c5837499
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122649929 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_
all.1122649929
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_jump.3002236326
Short name T158
Test name
Test status
Simulation time 394139037 ps
CPU time 1.08 seconds
Started Mar 24 12:49:47 PM PDT 24
Finished Mar 24 12:49:48 PM PDT 24
Peak memory 183020 kb
Host smart-1dc75541-f1dd-49ae-bcb0-11d2c1e87277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002236326 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.3002236326
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.3574370364
Short name T245
Test name
Test status
Simulation time 23937740862 ps
CPU time 18.06 seconds
Started Mar 24 12:49:45 PM PDT 24
Finished Mar 24 12:50:04 PM PDT 24
Peak memory 183144 kb
Host smart-d3d3fb50-3050-4b9e-943e-060398dbfc4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574370364 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.3574370364
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.1084019209
Short name T256
Test name
Test status
Simulation time 490892002 ps
CPU time 1.28 seconds
Started Mar 24 12:49:58 PM PDT 24
Finished Mar 24 12:50:00 PM PDT 24
Peak memory 183064 kb
Host smart-4ef5f017-c407-4da1-b051-a4ddc45e1b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084019209 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.1084019209
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.3773263813
Short name T218
Test name
Test status
Simulation time 241212969309 ps
CPU time 81.79 seconds
Started Mar 24 12:49:47 PM PDT 24
Finished Mar 24 12:51:09 PM PDT 24
Peak memory 183140 kb
Host smart-461afcb6-3eb9-416f-a860-deab5433b87e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773263813 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_
all.3773263813
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_jump.3892804398
Short name T234
Test name
Test status
Simulation time 378882438 ps
CPU time 0.9 seconds
Started Mar 24 12:49:58 PM PDT 24
Finished Mar 24 12:49:59 PM PDT 24
Peak memory 183072 kb
Host smart-1e356714-d7b0-48b5-9b5e-037b2822b130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892804398 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.3892804398
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.1730333096
Short name T185
Test name
Test status
Simulation time 4122629171 ps
CPU time 2.35 seconds
Started Mar 24 12:49:49 PM PDT 24
Finished Mar 24 12:49:52 PM PDT 24
Peak memory 183144 kb
Host smart-b9629ad8-036d-49f1-9749-4238dcbede0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730333096 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.1730333096
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.948069020
Short name T172
Test name
Test status
Simulation time 655922228 ps
CPU time 0.67 seconds
Started Mar 24 12:49:53 PM PDT 24
Finished Mar 24 12:49:54 PM PDT 24
Peak memory 183056 kb
Host smart-eddb767e-7ae8-4007-be5f-d3f5f9286627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948069020 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.948069020
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.473429256
Short name T275
Test name
Test status
Simulation time 222276911113 ps
CPU time 175.88 seconds
Started Mar 24 12:49:55 PM PDT 24
Finished Mar 24 12:52:51 PM PDT 24
Peak memory 192796 kb
Host smart-526c6867-876c-4f89-a538-7d7503b0c3ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473429256 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_a
ll.473429256
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_jump.889439834
Short name T116
Test name
Test status
Simulation time 360294052 ps
CPU time 0.67 seconds
Started Mar 24 12:49:39 PM PDT 24
Finished Mar 24 12:49:40 PM PDT 24
Peak memory 183016 kb
Host smart-2ab7ac4b-929c-4253-9407-7704544974f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889439834 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.889439834
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.1104599383
Short name T270
Test name
Test status
Simulation time 13615588830 ps
CPU time 5.93 seconds
Started Mar 24 12:49:37 PM PDT 24
Finished Mar 24 12:49:43 PM PDT 24
Peak memory 183028 kb
Host smart-e4a93bc0-a11e-4c34-9344-18a4dbf222a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104599383 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.1104599383
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.1331403838
Short name T18
Test name
Test status
Simulation time 4016580750 ps
CPU time 3.61 seconds
Started Mar 24 12:49:41 PM PDT 24
Finished Mar 24 12:49:44 PM PDT 24
Peak memory 214580 kb
Host smart-eebfa77b-57be-4e0e-8214-c5b0a8dd1be4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331403838 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.1331403838
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.3736860158
Short name T264
Test name
Test status
Simulation time 337929993 ps
CPU time 0.94 seconds
Started Mar 24 12:49:37 PM PDT 24
Finished Mar 24 12:49:38 PM PDT 24
Peak memory 183032 kb
Host smart-f4dc53ec-95b6-47cc-83db-a1172d9c17df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736860158 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.3736860158
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.3832760983
Short name T174
Test name
Test status
Simulation time 140928037201 ps
CPU time 229.01 seconds
Started Mar 24 12:49:35 PM PDT 24
Finished Mar 24 12:53:24 PM PDT 24
Peak memory 183288 kb
Host smart-64283677-daf1-43ea-930a-ab40baf6ba11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832760983 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_a
ll.3832760983
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.423250395
Short name T42
Test name
Test status
Simulation time 33661283718 ps
CPU time 265.66 seconds
Started Mar 24 12:49:40 PM PDT 24
Finished Mar 24 12:54:06 PM PDT 24
Peak memory 198048 kb
Host smart-f3002523-4501-4293-adf7-899d51c42219
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423250395 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.423250395
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.aon_timer_jump.1014123805
Short name T146
Test name
Test status
Simulation time 538506849 ps
CPU time 0.75 seconds
Started Mar 24 12:49:57 PM PDT 24
Finished Mar 24 12:49:58 PM PDT 24
Peak memory 183056 kb
Host smart-bab249c1-22ed-4f75-a0c1-daa9045b1f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014123805 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.1014123805
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.524681907
Short name T241
Test name
Test status
Simulation time 33078617385 ps
CPU time 48.75 seconds
Started Mar 24 12:49:59 PM PDT 24
Finished Mar 24 12:50:48 PM PDT 24
Peak memory 183036 kb
Host smart-a9c03caa-9a85-4417-8fec-ad6500f5961d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524681907 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.524681907
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.753074002
Short name T109
Test name
Test status
Simulation time 328649076 ps
CPU time 0.89 seconds
Started Mar 24 12:50:03 PM PDT 24
Finished Mar 24 12:50:04 PM PDT 24
Peak memory 183056 kb
Host smart-13568126-f881-4711-93b6-e8c1df1346a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753074002 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.753074002
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.1861122993
Short name T198
Test name
Test status
Simulation time 51882733511 ps
CPU time 38.94 seconds
Started Mar 24 12:50:00 PM PDT 24
Finished Mar 24 12:50:39 PM PDT 24
Peak memory 183356 kb
Host smart-ce5cb6e2-ada2-46ba-8006-8391e15363d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861122993 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_
all.1861122993
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.4162660800
Short name T15
Test name
Test status
Simulation time 51931949980 ps
CPU time 425.61 seconds
Started Mar 24 12:49:48 PM PDT 24
Finished Mar 24 12:56:54 PM PDT 24
Peak memory 198060 kb
Host smart-9db1c550-67b5-4cdb-8928-b57ea8fa8def
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162660800 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.4162660800
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_jump.2233423330
Short name T144
Test name
Test status
Simulation time 369236172 ps
CPU time 0.69 seconds
Started Mar 24 12:49:54 PM PDT 24
Finished Mar 24 12:49:55 PM PDT 24
Peak memory 183024 kb
Host smart-4b05215e-9d46-4141-99f7-9b5c3cbece60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233423330 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.2233423330
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.50497792
Short name T182
Test name
Test status
Simulation time 54842848024 ps
CPU time 21.15 seconds
Started Mar 24 12:50:00 PM PDT 24
Finished Mar 24 12:50:21 PM PDT 24
Peak memory 183056 kb
Host smart-7a079063-94fa-475b-8b70-b723c87432c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50497792 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.50497792
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.689661472
Short name T112
Test name
Test status
Simulation time 498720926 ps
CPU time 0.72 seconds
Started Mar 24 12:49:54 PM PDT 24
Finished Mar 24 12:49:55 PM PDT 24
Peak memory 183056 kb
Host smart-fdea03b1-9cbe-4e9e-ba7f-5f1e9b889a61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689661472 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.689661472
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.148587173
Short name T152
Test name
Test status
Simulation time 74796496560 ps
CPU time 18.47 seconds
Started Mar 24 12:49:59 PM PDT 24
Finished Mar 24 12:50:18 PM PDT 24
Peak memory 193848 kb
Host smart-38a2b959-2912-4054-ae62-e4cc4aa6b107
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148587173 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_a
ll.148587173
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.3903904780
Short name T176
Test name
Test status
Simulation time 44172267003 ps
CPU time 468.56 seconds
Started Mar 24 12:50:00 PM PDT 24
Finished Mar 24 12:57:49 PM PDT 24
Peak memory 197932 kb
Host smart-f97650d9-af32-412d-8dfe-1dedcbc0bb6c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903904780 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.3903904780
Directory /workspace/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.aon_timer_jump.2802466305
Short name T43
Test name
Test status
Simulation time 557408993 ps
CPU time 1.45 seconds
Started Mar 24 12:49:54 PM PDT 24
Finished Mar 24 12:49:55 PM PDT 24
Peak memory 183084 kb
Host smart-6285e30f-5394-4971-be58-aa7020ec60fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802466305 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.2802466305
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.3003858668
Short name T213
Test name
Test status
Simulation time 36074688114 ps
CPU time 27.67 seconds
Started Mar 24 12:49:56 PM PDT 24
Finished Mar 24 12:50:24 PM PDT 24
Peak memory 183120 kb
Host smart-458e8333-4f1f-423c-8a65-a2c00ffef927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003858668 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.3003858668
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.1243845524
Short name T9
Test name
Test status
Simulation time 388007149 ps
CPU time 1.18 seconds
Started Mar 24 12:49:50 PM PDT 24
Finished Mar 24 12:49:51 PM PDT 24
Peak memory 182972 kb
Host smart-eb26aefb-b958-413e-afc9-abedcdfbb136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243845524 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.1243845524
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.3869762808
Short name T207
Test name
Test status
Simulation time 158262703194 ps
CPU time 129.06 seconds
Started Mar 24 12:50:02 PM PDT 24
Finished Mar 24 12:52:11 PM PDT 24
Peak memory 183064 kb
Host smart-3117eb52-d7a7-406b-b5a1-c57271c9558c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869762808 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_
all.3869762808
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.4228489137
Short name T268
Test name
Test status
Simulation time 67371595175 ps
CPU time 543.04 seconds
Started Mar 24 12:49:54 PM PDT 24
Finished Mar 24 12:58:57 PM PDT 24
Peak memory 197988 kb
Host smart-2f548210-df9d-48e5-847d-a4b1efb2bb21
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228489137 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.4228489137
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.aon_timer_jump.3685200670
Short name T137
Test name
Test status
Simulation time 520509648 ps
CPU time 0.94 seconds
Started Mar 24 12:49:54 PM PDT 24
Finished Mar 24 12:49:55 PM PDT 24
Peak memory 183040 kb
Host smart-222222cb-fdcc-4bc4-a946-a54489c71a87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685200670 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.3685200670
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.954529846
Short name T238
Test name
Test status
Simulation time 26083556710 ps
CPU time 39.65 seconds
Started Mar 24 12:50:02 PM PDT 24
Finished Mar 24 12:50:42 PM PDT 24
Peak memory 183132 kb
Host smart-d6e04adc-3d6f-4e06-81f3-f281b8d52d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954529846 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.954529846
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.4225590362
Short name T135
Test name
Test status
Simulation time 361284178 ps
CPU time 0.82 seconds
Started Mar 24 12:49:54 PM PDT 24
Finished Mar 24 12:49:55 PM PDT 24
Peak memory 183064 kb
Host smart-429ef5ed-6dc9-4b23-8bac-0cab08cfb5d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225590362 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.4225590362
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.502000343
Short name T214
Test name
Test status
Simulation time 154089528850 ps
CPU time 59.37 seconds
Started Mar 24 12:50:00 PM PDT 24
Finished Mar 24 12:51:00 PM PDT 24
Peak memory 183120 kb
Host smart-ec020b69-eeba-4e06-92b6-43dec5bf370b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502000343 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_a
ll.502000343
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.1320197310
Short name T36
Test name
Test status
Simulation time 50167540308 ps
CPU time 515.59 seconds
Started Mar 24 12:49:55 PM PDT 24
Finished Mar 24 12:58:30 PM PDT 24
Peak memory 198040 kb
Host smart-e9f85651-b03f-4fd6-addd-29d0973b0ca4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320197310 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.1320197310
Directory /workspace/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.aon_timer_jump.908023878
Short name T128
Test name
Test status
Simulation time 549464123 ps
CPU time 0.84 seconds
Started Mar 24 12:49:59 PM PDT 24
Finished Mar 24 12:50:00 PM PDT 24
Peak memory 182988 kb
Host smart-48b89162-f891-4dee-8ff4-0d8e6dc6778c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908023878 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.908023878
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.3553531557
Short name T74
Test name
Test status
Simulation time 22544940878 ps
CPU time 9.1 seconds
Started Mar 24 12:50:05 PM PDT 24
Finished Mar 24 12:50:15 PM PDT 24
Peak memory 183140 kb
Host smart-384667b5-f469-4b62-aae0-51c891187915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553531557 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.3553531557
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.2278081031
Short name T104
Test name
Test status
Simulation time 442663265 ps
CPU time 0.9 seconds
Started Mar 24 12:49:53 PM PDT 24
Finished Mar 24 12:49:54 PM PDT 24
Peak memory 183080 kb
Host smart-ab0617b0-063a-4fe3-9782-cc1fb62cbe8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278081031 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.2278081031
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.2208032000
Short name T166
Test name
Test status
Simulation time 352336641124 ps
CPU time 566.54 seconds
Started Mar 24 12:50:03 PM PDT 24
Finished Mar 24 12:59:30 PM PDT 24
Peak memory 194508 kb
Host smart-8c4e5536-b2f7-44ad-b50b-4e271bc27dfe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208032000 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_
all.2208032000
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.1727772724
Short name T228
Test name
Test status
Simulation time 41226396052 ps
CPU time 321.66 seconds
Started Mar 24 12:50:12 PM PDT 24
Finished Mar 24 12:55:34 PM PDT 24
Peak memory 198060 kb
Host smart-041e7ace-8f14-4824-9076-60358444c1cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727772724 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand_reset.1727772724
Directory /workspace/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.aon_timer_jump.1455964921
Short name T145
Test name
Test status
Simulation time 581296594 ps
CPU time 0.75 seconds
Started Mar 24 12:50:22 PM PDT 24
Finished Mar 24 12:50:23 PM PDT 24
Peak memory 183076 kb
Host smart-5b7a0e1e-fee3-49b7-8cb1-92fce290476d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455964921 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.1455964921
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.536763829
Short name T178
Test name
Test status
Simulation time 59436522597 ps
CPU time 18.33 seconds
Started Mar 24 12:50:14 PM PDT 24
Finished Mar 24 12:50:32 PM PDT 24
Peak memory 183108 kb
Host smart-2896b543-87f4-44c0-b878-fa628ddc5a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536763829 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.536763829
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.1729922418
Short name T205
Test name
Test status
Simulation time 439355084 ps
CPU time 0.71 seconds
Started Mar 24 12:49:58 PM PDT 24
Finished Mar 24 12:49:59 PM PDT 24
Peak memory 183068 kb
Host smart-109d3138-1b57-4197-99c2-06136c50835e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729922418 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.1729922418
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.35682958
Short name T30
Test name
Test status
Simulation time 152868771006 ps
CPU time 70.86 seconds
Started Mar 24 12:50:22 PM PDT 24
Finished Mar 24 12:51:33 PM PDT 24
Peak memory 183236 kb
Host smart-8781e681-6b0c-470e-8ed9-05bc03063b12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35682958 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_al
l.35682958
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.457046498
Short name T165
Test name
Test status
Simulation time 37902742344 ps
CPU time 394.33 seconds
Started Mar 24 12:50:02 PM PDT 24
Finished Mar 24 12:56:37 PM PDT 24
Peak memory 198000 kb
Host smart-4a4187c1-5c50-40c8-bd16-34fc5fcaf1e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457046498 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.457046498
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.aon_timer_jump.870124702
Short name T24
Test name
Test status
Simulation time 565074916 ps
CPU time 1.43 seconds
Started Mar 24 12:50:01 PM PDT 24
Finished Mar 24 12:50:02 PM PDT 24
Peak memory 183004 kb
Host smart-52327427-37a2-42be-8205-b0db210e7bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870124702 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.870124702
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.3812319397
Short name T173
Test name
Test status
Simulation time 40033542369 ps
CPU time 60.01 seconds
Started Mar 24 12:50:13 PM PDT 24
Finished Mar 24 12:51:13 PM PDT 24
Peak memory 183112 kb
Host smart-bad926fb-1cb2-40d3-9157-f23f15ecd631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812319397 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.3812319397
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.399870076
Short name T72
Test name
Test status
Simulation time 366302422 ps
CPU time 0.77 seconds
Started Mar 24 12:50:07 PM PDT 24
Finished Mar 24 12:50:08 PM PDT 24
Peak memory 183036 kb
Host smart-8b5d3d77-cc01-42dd-b665-0168d5485522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399870076 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.399870076
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.833976358
Short name T96
Test name
Test status
Simulation time 178929493325 ps
CPU time 269.59 seconds
Started Mar 24 12:50:20 PM PDT 24
Finished Mar 24 12:54:50 PM PDT 24
Peak memory 183140 kb
Host smart-aeee0b7b-9ad0-4abe-b0ef-6b17af557342
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833976358 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_a
ll.833976358
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.236736586
Short name T84
Test name
Test status
Simulation time 158677993681 ps
CPU time 846.1 seconds
Started Mar 24 12:49:58 PM PDT 24
Finished Mar 24 01:04:04 PM PDT 24
Peak memory 202412 kb
Host smart-743d4922-e240-462d-b8cd-499af46fdcfc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236736586 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.236736586
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_jump.2277483422
Short name T261
Test name
Test status
Simulation time 468733167 ps
CPU time 1.29 seconds
Started Mar 24 12:50:06 PM PDT 24
Finished Mar 24 12:50:07 PM PDT 24
Peak memory 183060 kb
Host smart-9508bf7d-d23f-4460-b684-dfad2dd0bc03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277483422 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.2277483422
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.3911230518
Short name T122
Test name
Test status
Simulation time 41088871048 ps
CPU time 60.92 seconds
Started Mar 24 12:49:59 PM PDT 24
Finished Mar 24 12:51:01 PM PDT 24
Peak memory 183140 kb
Host smart-e5851265-6298-4617-9cf3-650163f3844d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911230518 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.3911230518
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.3060039623
Short name T255
Test name
Test status
Simulation time 518736164 ps
CPU time 1.03 seconds
Started Mar 24 12:50:05 PM PDT 24
Finished Mar 24 12:50:06 PM PDT 24
Peak memory 182936 kb
Host smart-f7f93916-f04c-4d89-8bd6-323029673314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060039623 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.3060039623
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.1315364972
Short name T224
Test name
Test status
Simulation time 273922365158 ps
CPU time 450.7 seconds
Started Mar 24 12:49:58 PM PDT 24
Finished Mar 24 12:57:29 PM PDT 24
Peak memory 194584 kb
Host smart-153cb954-ab5b-4452-9217-3b4c1883fe3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315364972 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_
all.1315364972
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_jump.3052227213
Short name T119
Test name
Test status
Simulation time 468358034 ps
CPU time 0.76 seconds
Started Mar 24 12:50:00 PM PDT 24
Finished Mar 24 12:50:00 PM PDT 24
Peak memory 183020 kb
Host smart-62293984-1dce-40b4-82de-4ed1cc0423d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052227213 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.3052227213
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.2746857395
Short name T175
Test name
Test status
Simulation time 8403413014 ps
CPU time 12 seconds
Started Mar 24 12:50:21 PM PDT 24
Finished Mar 24 12:50:34 PM PDT 24
Peak memory 182992 kb
Host smart-e7f8a413-3571-43db-9edb-003288cc72a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746857395 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.2746857395
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.3852277228
Short name T115
Test name
Test status
Simulation time 391953997 ps
CPU time 0.68 seconds
Started Mar 24 12:49:56 PM PDT 24
Finished Mar 24 12:49:57 PM PDT 24
Peak memory 183032 kb
Host smart-33f30398-97d6-4499-891d-edc351c641d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852277228 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.3852277228
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.2620769546
Short name T147
Test name
Test status
Simulation time 216812229178 ps
CPU time 85.56 seconds
Started Mar 24 12:50:14 PM PDT 24
Finished Mar 24 12:51:40 PM PDT 24
Peak memory 183116 kb
Host smart-72b0f5cd-5f86-46de-9fd9-943c7300ae36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620769546 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_
all.2620769546
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.14487400
Short name T44
Test name
Test status
Simulation time 81319827948 ps
CPU time 232.89 seconds
Started Mar 24 12:50:01 PM PDT 24
Finished Mar 24 12:53:54 PM PDT 24
Peak memory 198052 kb
Host smart-9b5fe3d4-e06f-496e-9915-21badba6a4bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14487400 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.14487400
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.aon_timer_jump.3995495879
Short name T181
Test name
Test status
Simulation time 555609519 ps
CPU time 1.45 seconds
Started Mar 24 12:50:04 PM PDT 24
Finished Mar 24 12:50:05 PM PDT 24
Peak memory 182932 kb
Host smart-50f0b7ba-ca31-424b-a297-ec87f56f3d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995495879 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.3995495879
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.3859306863
Short name T163
Test name
Test status
Simulation time 17307688724 ps
CPU time 4.6 seconds
Started Mar 24 12:49:59 PM PDT 24
Finished Mar 24 12:50:03 PM PDT 24
Peak memory 183072 kb
Host smart-7c98ced8-bed7-4113-a168-29681b904a75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859306863 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.3859306863
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.1702907175
Short name T221
Test name
Test status
Simulation time 429903946 ps
CPU time 1.1 seconds
Started Mar 24 12:50:15 PM PDT 24
Finished Mar 24 12:50:16 PM PDT 24
Peak memory 183068 kb
Host smart-bd20be7d-09ef-4463-a4b6-dd0f5de08e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702907175 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.1702907175
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.1404191025
Short name T157
Test name
Test status
Simulation time 267379730587 ps
CPU time 393.53 seconds
Started Mar 24 12:50:04 PM PDT 24
Finished Mar 24 12:56:37 PM PDT 24
Peak memory 193832 kb
Host smart-323e447b-b83f-4dc1-844b-9e1f4bcaeeb3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404191025 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_
all.1404191025
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.3271683809
Short name T190
Test name
Test status
Simulation time 9458946436 ps
CPU time 104.6 seconds
Started Mar 24 12:50:19 PM PDT 24
Finished Mar 24 12:52:04 PM PDT 24
Peak memory 197900 kb
Host smart-8822dfa9-60cc-491e-b1ae-0450edd03ffd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271683809 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.3271683809
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.aon_timer_jump.1266565803
Short name T233
Test name
Test status
Simulation time 583727073 ps
CPU time 0.96 seconds
Started Mar 24 12:49:37 PM PDT 24
Finished Mar 24 12:49:38 PM PDT 24
Peak memory 183076 kb
Host smart-d56e8e91-cfe8-4c7a-856d-0f542e10535a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266565803 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.1266565803
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.850403663
Short name T95
Test name
Test status
Simulation time 21105000923 ps
CPU time 9.25 seconds
Started Mar 24 12:49:35 PM PDT 24
Finished Mar 24 12:49:44 PM PDT 24
Peak memory 183152 kb
Host smart-fdce95ba-941e-4176-98a8-b2d16e9c1582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850403663 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.850403663
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.663049439
Short name T21
Test name
Test status
Simulation time 7717546800 ps
CPU time 3.94 seconds
Started Mar 24 12:49:35 PM PDT 24
Finished Mar 24 12:49:39 PM PDT 24
Peak memory 215052 kb
Host smart-c0876820-e022-4415-8d08-a0ffcc83b67e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663049439 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.663049439
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.1464310534
Short name T211
Test name
Test status
Simulation time 474467026 ps
CPU time 0.68 seconds
Started Mar 24 12:49:40 PM PDT 24
Finished Mar 24 12:49:41 PM PDT 24
Peak memory 183072 kb
Host smart-9259fd20-950c-402c-a76d-0084004c6749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464310534 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.1464310534
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.679541229
Short name T41
Test name
Test status
Simulation time 151172349524 ps
CPU time 71.22 seconds
Started Mar 24 12:49:36 PM PDT 24
Finished Mar 24 12:50:47 PM PDT 24
Peak memory 194024 kb
Host smart-95be9954-9b67-4434-a12b-757acbb315f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679541229 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_al
l.679541229
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.3646389619
Short name T6
Test name
Test status
Simulation time 30847616099 ps
CPU time 227.86 seconds
Started Mar 24 12:49:40 PM PDT 24
Finished Mar 24 12:53:28 PM PDT 24
Peak memory 198012 kb
Host smart-18481b81-4a4a-4b6b-b693-bd17d487a691
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646389619 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.3646389619
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_jump.3151768435
Short name T139
Test name
Test status
Simulation time 597085895 ps
CPU time 1.43 seconds
Started Mar 24 12:50:00 PM PDT 24
Finished Mar 24 12:50:01 PM PDT 24
Peak memory 183056 kb
Host smart-6592ecd5-cb9f-4298-a2a5-2e6ee68f7869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151768435 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.3151768435
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.2187651846
Short name T248
Test name
Test status
Simulation time 19064504569 ps
CPU time 26 seconds
Started Mar 24 12:50:02 PM PDT 24
Finished Mar 24 12:50:29 PM PDT 24
Peak memory 183112 kb
Host smart-d017cf3c-0cf6-409f-b35c-c2e7c395ccb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187651846 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.2187651846
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.1012870978
Short name T156
Test name
Test status
Simulation time 490835288 ps
CPU time 1.34 seconds
Started Mar 24 12:50:00 PM PDT 24
Finished Mar 24 12:50:01 PM PDT 24
Peak memory 183080 kb
Host smart-0b5faa21-0419-4885-b39e-c3c5ddcc843d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012870978 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.1012870978
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.906204801
Short name T242
Test name
Test status
Simulation time 119041675913 ps
CPU time 194.79 seconds
Started Mar 24 12:50:06 PM PDT 24
Finished Mar 24 12:53:21 PM PDT 24
Peak memory 183100 kb
Host smart-cd5a4edf-305b-4612-ba8a-bbcc9e12d72e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906204801 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_a
ll.906204801
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.923625246
Short name T89
Test name
Test status
Simulation time 36769677023 ps
CPU time 140.57 seconds
Started Mar 24 12:49:58 PM PDT 24
Finished Mar 24 12:52:19 PM PDT 24
Peak memory 198056 kb
Host smart-babd6f4d-8102-45a4-8699-af93795ff272
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923625246 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.923625246
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.aon_timer_jump.1636172097
Short name T194
Test name
Test status
Simulation time 592960746 ps
CPU time 1.48 seconds
Started Mar 24 12:50:00 PM PDT 24
Finished Mar 24 12:50:02 PM PDT 24
Peak memory 183024 kb
Host smart-30f0c839-af18-438f-b440-e7c7cd43da06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636172097 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.1636172097
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.3733193158
Short name T132
Test name
Test status
Simulation time 18993983082 ps
CPU time 27.06 seconds
Started Mar 24 12:50:12 PM PDT 24
Finished Mar 24 12:50:39 PM PDT 24
Peak memory 183072 kb
Host smart-f8345b35-7612-469c-86c5-6cf883634c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733193158 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.3733193158
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.981547363
Short name T78
Test name
Test status
Simulation time 451475098 ps
CPU time 0.75 seconds
Started Mar 24 12:50:14 PM PDT 24
Finished Mar 24 12:50:14 PM PDT 24
Peak memory 183052 kb
Host smart-37d6fabf-316a-43b2-bfba-39cd4ae45d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981547363 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.981547363
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.1172845099
Short name T204
Test name
Test status
Simulation time 47160901638 ps
CPU time 260.68 seconds
Started Mar 24 12:50:02 PM PDT 24
Finished Mar 24 12:54:24 PM PDT 24
Peak memory 198040 kb
Host smart-3dac5b5a-8b3e-4ea5-9544-a3e8ce55dabe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172845099 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.1172845099
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.aon_timer_jump.516257019
Short name T209
Test name
Test status
Simulation time 475058619 ps
CPU time 0.73 seconds
Started Mar 24 12:50:00 PM PDT 24
Finished Mar 24 12:50:01 PM PDT 24
Peak memory 183084 kb
Host smart-a3497085-dd54-49ef-991c-8eadc1f40fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516257019 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.516257019
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.3456852612
Short name T277
Test name
Test status
Simulation time 29091243825 ps
CPU time 11.61 seconds
Started Mar 24 12:50:21 PM PDT 24
Finished Mar 24 12:50:33 PM PDT 24
Peak memory 183136 kb
Host smart-7aa59195-ab72-4d0c-b290-533beffad2d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456852612 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.3456852612
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.3593191691
Short name T201
Test name
Test status
Simulation time 615599797 ps
CPU time 0.75 seconds
Started Mar 24 12:50:00 PM PDT 24
Finished Mar 24 12:50:01 PM PDT 24
Peak memory 183032 kb
Host smart-e20c3b2f-da7e-4fdf-ae56-e37fd1a8db67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593191691 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.3593191691
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.799615815
Short name T161
Test name
Test status
Simulation time 110774858079 ps
CPU time 146.64 seconds
Started Mar 24 12:50:24 PM PDT 24
Finished Mar 24 12:52:51 PM PDT 24
Peak memory 193312 kb
Host smart-c4f5552c-bea9-4a38-92bc-cde2fe31a0bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799615815 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_a
ll.799615815
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_jump.3067525900
Short name T111
Test name
Test status
Simulation time 558735093 ps
CPU time 1.31 seconds
Started Mar 24 12:50:12 PM PDT 24
Finished Mar 24 12:50:14 PM PDT 24
Peak memory 183052 kb
Host smart-c52281a8-ea30-46f0-b998-16e6392958c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067525900 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.3067525900
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.1239897883
Short name T148
Test name
Test status
Simulation time 22410669107 ps
CPU time 19.1 seconds
Started Mar 24 12:50:19 PM PDT 24
Finished Mar 24 12:50:39 PM PDT 24
Peak memory 183100 kb
Host smart-1c0ed80b-f4a3-49fb-b35b-9fce13e6ab5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239897883 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.1239897883
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.3484276715
Short name T126
Test name
Test status
Simulation time 426569050 ps
CPU time 0.89 seconds
Started Mar 24 12:50:19 PM PDT 24
Finished Mar 24 12:50:20 PM PDT 24
Peak memory 182940 kb
Host smart-abefe08f-d791-4509-8c95-831cc251419d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484276715 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.3484276715
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.3375615161
Short name T153
Test name
Test status
Simulation time 126842921687 ps
CPU time 34 seconds
Started Mar 24 12:50:05 PM PDT 24
Finished Mar 24 12:50:39 PM PDT 24
Peak memory 193468 kb
Host smart-fdee0b95-6243-4904-bab8-e3fabe5034ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375615161 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_
all.3375615161
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.3120119421
Short name T222
Test name
Test status
Simulation time 38071722241 ps
CPU time 331.68 seconds
Started Mar 24 12:50:19 PM PDT 24
Finished Mar 24 12:55:51 PM PDT 24
Peak memory 198040 kb
Host smart-12236dd7-a383-437a-846a-702266878b67
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120119421 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.3120119421
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.aon_timer_jump.2050438215
Short name T7
Test name
Test status
Simulation time 456517435 ps
CPU time 0.74 seconds
Started Mar 24 12:50:04 PM PDT 24
Finished Mar 24 12:50:05 PM PDT 24
Peak memory 182996 kb
Host smart-93f2d281-d907-449f-b1b1-653b2513f55b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050438215 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.2050438215
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.2886389368
Short name T1
Test name
Test status
Simulation time 52902132123 ps
CPU time 72.97 seconds
Started Mar 24 12:50:25 PM PDT 24
Finished Mar 24 12:51:38 PM PDT 24
Peak memory 183108 kb
Host smart-ff44cb69-c322-486e-b971-4c3806689b73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886389368 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.2886389368
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.2130973555
Short name T210
Test name
Test status
Simulation time 525850121 ps
CPU time 0.81 seconds
Started Mar 24 12:50:24 PM PDT 24
Finished Mar 24 12:50:25 PM PDT 24
Peak memory 182940 kb
Host smart-87e1ef8c-c515-4b3e-b522-7b67a6ce8d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130973555 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.2130973555
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.2579972552
Short name T252
Test name
Test status
Simulation time 296610998126 ps
CPU time 113.92 seconds
Started Mar 24 12:50:15 PM PDT 24
Finished Mar 24 12:52:09 PM PDT 24
Peak memory 183124 kb
Host smart-6800721d-f1ca-4795-9651-ea5c581fc6c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579972552 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_
all.2579972552
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.4094704127
Short name T76
Test name
Test status
Simulation time 14120912631 ps
CPU time 98.46 seconds
Started Mar 24 12:50:07 PM PDT 24
Finished Mar 24 12:51:46 PM PDT 24
Peak memory 197996 kb
Host smart-1f68bae9-db2c-408e-b7e0-56939d32efbd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094704127 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.4094704127
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.aon_timer_jump.1577010907
Short name T236
Test name
Test status
Simulation time 365498098 ps
CPU time 0.69 seconds
Started Mar 24 12:50:20 PM PDT 24
Finished Mar 24 12:50:21 PM PDT 24
Peak memory 182984 kb
Host smart-5ae4b34f-583e-423b-818f-6a11e2696644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577010907 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.1577010907
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.2022105124
Short name T232
Test name
Test status
Simulation time 23708621407 ps
CPU time 2.85 seconds
Started Mar 24 12:50:24 PM PDT 24
Finished Mar 24 12:50:27 PM PDT 24
Peak memory 183072 kb
Host smart-e8f08a9a-4a3e-4cfa-822e-c3d6ac98a8a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022105124 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.2022105124
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.100805141
Short name T129
Test name
Test status
Simulation time 592990107 ps
CPU time 0.68 seconds
Started Mar 24 12:50:10 PM PDT 24
Finished Mar 24 12:50:12 PM PDT 24
Peak memory 183072 kb
Host smart-6867657c-2481-48fd-b8ba-c6487d99f904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100805141 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.100805141
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.1560148092
Short name T143
Test name
Test status
Simulation time 342840042184 ps
CPU time 55.21 seconds
Started Mar 24 12:50:09 PM PDT 24
Finished Mar 24 12:51:05 PM PDT 24
Peak memory 183060 kb
Host smart-baea6658-5ada-41f4-86fc-4d75a87f69f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560148092 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_
all.1560148092
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_jump.1326881311
Short name T220
Test name
Test status
Simulation time 425953951 ps
CPU time 1.26 seconds
Started Mar 24 12:50:02 PM PDT 24
Finished Mar 24 12:50:03 PM PDT 24
Peak memory 183056 kb
Host smart-a635c5a4-d20b-46b1-b3f8-d3a12fa5dd8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326881311 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.1326881311
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.1315206992
Short name T196
Test name
Test status
Simulation time 23404697095 ps
CPU time 38.17 seconds
Started Mar 24 12:50:04 PM PDT 24
Finished Mar 24 12:50:42 PM PDT 24
Peak memory 183072 kb
Host smart-c25f516b-9be1-4b23-9a00-8982eea56678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315206992 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.1315206992
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.3569873551
Short name T188
Test name
Test status
Simulation time 641765155 ps
CPU time 0.62 seconds
Started Mar 24 12:50:06 PM PDT 24
Finished Mar 24 12:50:07 PM PDT 24
Peak memory 183084 kb
Host smart-fb24be51-9205-46fd-bd8e-3876fbcaf6ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569873551 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.3569873551
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.2441919037
Short name T162
Test name
Test status
Simulation time 132177100935 ps
CPU time 98.28 seconds
Started Mar 24 12:50:06 PM PDT 24
Finished Mar 24 12:51:45 PM PDT 24
Peak memory 192852 kb
Host smart-f65884bd-c1fd-4410-b73b-51bbcdd113b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441919037 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_
all.2441919037
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.1418605962
Short name T273
Test name
Test status
Simulation time 44683380109 ps
CPU time 111.04 seconds
Started Mar 24 12:50:05 PM PDT 24
Finished Mar 24 12:51:57 PM PDT 24
Peak memory 197984 kb
Host smart-278b7ff0-8290-4f52-b362-64a3f178224f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418605962 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.1418605962
Directory /workspace/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.aon_timer_jump.862682267
Short name T40
Test name
Test status
Simulation time 361952244 ps
CPU time 0.75 seconds
Started Mar 24 12:50:10 PM PDT 24
Finished Mar 24 12:50:11 PM PDT 24
Peak memory 183020 kb
Host smart-4866b2c6-c03d-4989-aa3b-d21e8bc34e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862682267 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.862682267
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.816669800
Short name T202
Test name
Test status
Simulation time 4246247446 ps
CPU time 6.87 seconds
Started Mar 24 12:50:04 PM PDT 24
Finished Mar 24 12:50:11 PM PDT 24
Peak memory 183116 kb
Host smart-fe9eee3f-a457-4bdf-8542-b02c30b327d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816669800 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.816669800
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.1618003078
Short name T200
Test name
Test status
Simulation time 506117686 ps
CPU time 0.75 seconds
Started Mar 24 12:50:15 PM PDT 24
Finished Mar 24 12:50:16 PM PDT 24
Peak memory 183072 kb
Host smart-9e4a1d7c-eee5-4706-807c-bdd5a27bd658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618003078 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.1618003078
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.2424651792
Short name T258
Test name
Test status
Simulation time 57812729488 ps
CPU time 18.96 seconds
Started Mar 24 12:50:18 PM PDT 24
Finished Mar 24 12:50:37 PM PDT 24
Peak memory 193616 kb
Host smart-c2a2de82-2ec7-4f96-853e-819b90eaf172
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424651792 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_
all.2424651792
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.2174908404
Short name T85
Test name
Test status
Simulation time 237492191675 ps
CPU time 811.7 seconds
Started Mar 24 12:50:22 PM PDT 24
Finished Mar 24 01:03:54 PM PDT 24
Peak memory 201100 kb
Host smart-13ed89c6-612a-4fb2-8b36-3a0d3c94ecca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174908404 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.2174908404
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.aon_timer_jump.3365848419
Short name T142
Test name
Test status
Simulation time 449384761 ps
CPU time 0.86 seconds
Started Mar 24 12:50:18 PM PDT 24
Finished Mar 24 12:50:19 PM PDT 24
Peak memory 183076 kb
Host smart-29038d47-8d6e-41a3-9b88-da29287553b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365848419 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.3365848419
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.3691540924
Short name T80
Test name
Test status
Simulation time 23462982228 ps
CPU time 8.55 seconds
Started Mar 24 12:50:21 PM PDT 24
Finished Mar 24 12:50:29 PM PDT 24
Peak memory 183068 kb
Host smart-e9641aef-900a-4b06-bbc9-ca1c11b5d4b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691540924 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.3691540924
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.2648219854
Short name T77
Test name
Test status
Simulation time 487059077 ps
CPU time 0.92 seconds
Started Mar 24 12:50:25 PM PDT 24
Finished Mar 24 12:50:26 PM PDT 24
Peak memory 183056 kb
Host smart-bc68a700-972e-4314-b81a-5803640d74df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648219854 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.2648219854
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.1180397125
Short name T274
Test name
Test status
Simulation time 39263546950 ps
CPU time 59.81 seconds
Started Mar 24 12:50:04 PM PDT 24
Finished Mar 24 12:51:04 PM PDT 24
Peak memory 183148 kb
Host smart-e49ec13e-f8dc-44a1-8b31-9aef79731914
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180397125 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_
all.1180397125
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_jump.1534560637
Short name T262
Test name
Test status
Simulation time 426139560 ps
CPU time 1.08 seconds
Started Mar 24 12:50:04 PM PDT 24
Finished Mar 24 12:50:06 PM PDT 24
Peak memory 183120 kb
Host smart-f1e39ad8-3963-4e75-b186-71c652b4bca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534560637 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.1534560637
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.122836850
Short name T184
Test name
Test status
Simulation time 17918253268 ps
CPU time 25.79 seconds
Started Mar 24 12:50:25 PM PDT 24
Finished Mar 24 12:50:50 PM PDT 24
Peak memory 183092 kb
Host smart-91645a83-6eb1-44c3-8c3c-276cd698d0b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122836850 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.122836850
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.3335672855
Short name T130
Test name
Test status
Simulation time 359771563 ps
CPU time 0.91 seconds
Started Mar 24 12:50:07 PM PDT 24
Finished Mar 24 12:50:08 PM PDT 24
Peak memory 183036 kb
Host smart-9f2e94fe-1be0-4880-a4f2-6ce46a55996a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335672855 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.3335672855
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.2313156011
Short name T216
Test name
Test status
Simulation time 80452207901 ps
CPU time 22.01 seconds
Started Mar 24 12:50:04 PM PDT 24
Finished Mar 24 12:50:26 PM PDT 24
Peak memory 183136 kb
Host smart-e3c1cf82-e058-4a70-82b2-8b26ae66b682
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313156011 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_
all.2313156011
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.318666954
Short name T246
Test name
Test status
Simulation time 187711746746 ps
CPU time 981.37 seconds
Started Mar 24 12:50:19 PM PDT 24
Finished Mar 24 01:06:40 PM PDT 24
Peak memory 204116 kb
Host smart-c6c91252-805c-4603-b0ab-4de691ceb780
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318666954 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.318666954
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_jump.2199064723
Short name T271
Test name
Test status
Simulation time 435435665 ps
CPU time 0.74 seconds
Started Mar 24 12:49:39 PM PDT 24
Finished Mar 24 12:49:40 PM PDT 24
Peak memory 183060 kb
Host smart-5230ba4a-b932-4a22-8d65-7bd5bbae0abc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199064723 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.2199064723
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.1957272325
Short name T225
Test name
Test status
Simulation time 27501202836 ps
CPU time 11.79 seconds
Started Mar 24 12:49:39 PM PDT 24
Finished Mar 24 12:49:52 PM PDT 24
Peak memory 183132 kb
Host smart-921daab9-53ff-4922-9b33-b383aa983e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957272325 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.1957272325
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.2444051502
Short name T11
Test name
Test status
Simulation time 4156131709 ps
CPU time 1.93 seconds
Started Mar 24 12:49:38 PM PDT 24
Finished Mar 24 12:49:41 PM PDT 24
Peak memory 214644 kb
Host smart-d8abfe20-e280-4e41-ab21-2ece0691ecd3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444051502 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.2444051502
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.3184704874
Short name T110
Test name
Test status
Simulation time 479538649 ps
CPU time 1.32 seconds
Started Mar 24 12:49:40 PM PDT 24
Finished Mar 24 12:49:41 PM PDT 24
Peak memory 183000 kb
Host smart-396cdc52-0f5f-4fb5-a316-ad87500463df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184704874 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.3184704874
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.1267536214
Short name T186
Test name
Test status
Simulation time 370301845639 ps
CPU time 1033.41 seconds
Started Mar 24 12:49:38 PM PDT 24
Finished Mar 24 01:06:52 PM PDT 24
Peak memory 204980 kb
Host smart-d942a50c-83b3-4cdd-93c4-dfdc2d609782
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267536214 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.1267536214
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.aon_timer_jump.541811822
Short name T123
Test name
Test status
Simulation time 356923271 ps
CPU time 0.75 seconds
Started Mar 24 12:50:05 PM PDT 24
Finished Mar 24 12:50:06 PM PDT 24
Peak memory 183068 kb
Host smart-a8f6b110-c792-4c96-b08e-0e4d775254ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541811822 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.541811822
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.3757445152
Short name T219
Test name
Test status
Simulation time 18574020343 ps
CPU time 2.49 seconds
Started Mar 24 12:50:19 PM PDT 24
Finished Mar 24 12:50:22 PM PDT 24
Peak memory 183136 kb
Host smart-1c252992-1c44-4907-b090-b833a8351579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757445152 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.3757445152
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.4161273301
Short name T226
Test name
Test status
Simulation time 396007841 ps
CPU time 0.63 seconds
Started Mar 24 12:50:21 PM PDT 24
Finished Mar 24 12:50:23 PM PDT 24
Peak memory 183048 kb
Host smart-8ee1251f-9dd0-4731-8fee-1637b71d0554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161273301 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.4161273301
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.1316308158
Short name T98
Test name
Test status
Simulation time 215547071530 ps
CPU time 349.17 seconds
Started Mar 24 12:50:25 PM PDT 24
Finished Mar 24 12:56:14 PM PDT 24
Peak memory 192828 kb
Host smart-2dff680b-6698-4ff1-a257-2e4eb0958860
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316308158 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_
all.1316308158
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.1410689414
Short name T8
Test name
Test status
Simulation time 16628250344 ps
CPU time 161.27 seconds
Started Mar 24 12:50:02 PM PDT 24
Finished Mar 24 12:52:44 PM PDT 24
Peak memory 198024 kb
Host smart-ca1de007-b176-48b2-8c1a-ea89673e9310
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410689414 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.1410689414
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.aon_timer_jump.1345282469
Short name T29
Test name
Test status
Simulation time 346762880 ps
CPU time 1.02 seconds
Started Mar 24 12:50:18 PM PDT 24
Finished Mar 24 12:50:19 PM PDT 24
Peak memory 182948 kb
Host smart-63eaf50f-9d1b-4475-9583-0fa22ad4e002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345282469 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.1345282469
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.3071003066
Short name T193
Test name
Test status
Simulation time 31411874807 ps
CPU time 13.63 seconds
Started Mar 24 12:50:03 PM PDT 24
Finished Mar 24 12:50:17 PM PDT 24
Peak memory 183120 kb
Host smart-92f94f4a-96f4-443b-96b3-0d254306ec4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071003066 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.3071003066
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.2916390510
Short name T179
Test name
Test status
Simulation time 350500731 ps
CPU time 1.12 seconds
Started Mar 24 12:50:04 PM PDT 24
Finished Mar 24 12:50:05 PM PDT 24
Peak memory 183028 kb
Host smart-c4638865-dd48-4762-9aec-2221b390d464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916390510 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.2916390510
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.3099998321
Short name T125
Test name
Test status
Simulation time 5868501477 ps
CPU time 9.93 seconds
Started Mar 24 12:50:18 PM PDT 24
Finished Mar 24 12:50:28 PM PDT 24
Peak memory 195016 kb
Host smart-ec251156-ecba-4020-8e77-cc9101e5826d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099998321 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_
all.3099998321
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.335466583
Short name T38
Test name
Test status
Simulation time 101140931039 ps
CPU time 526.14 seconds
Started Mar 24 12:50:05 PM PDT 24
Finished Mar 24 12:58:51 PM PDT 24
Peak memory 198748 kb
Host smart-f228e71a-7ed3-4306-aff6-17ae8b53ac07
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335466583 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.335466583
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.aon_timer_jump.1733137966
Short name T118
Test name
Test status
Simulation time 611560886 ps
CPU time 1.47 seconds
Started Mar 24 12:50:19 PM PDT 24
Finished Mar 24 12:50:21 PM PDT 24
Peak memory 182996 kb
Host smart-6bafe2b6-fd86-461b-8608-5069fa0020aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733137966 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.1733137966
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.2711427493
Short name T124
Test name
Test status
Simulation time 52969217802 ps
CPU time 43.87 seconds
Started Mar 24 12:50:25 PM PDT 24
Finished Mar 24 12:51:09 PM PDT 24
Peak memory 183116 kb
Host smart-cda4c56f-a92c-4e1c-a739-8b04b420b55b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711427493 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.2711427493
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.1888801214
Short name T269
Test name
Test status
Simulation time 561653210 ps
CPU time 0.75 seconds
Started Mar 24 12:50:17 PM PDT 24
Finished Mar 24 12:50:18 PM PDT 24
Peak memory 183056 kb
Host smart-6a1a4332-3cfa-44bf-a734-c74d83828f95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888801214 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.1888801214
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.2815239559
Short name T247
Test name
Test status
Simulation time 213127046885 ps
CPU time 351.27 seconds
Started Mar 24 12:50:06 PM PDT 24
Finished Mar 24 12:55:57 PM PDT 24
Peak memory 191348 kb
Host smart-b615b287-75de-4ca3-9ed4-8065fea67d0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815239559 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_
all.2815239559
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.1817635310
Short name T16
Test name
Test status
Simulation time 35267835058 ps
CPU time 143.84 seconds
Started Mar 24 12:50:04 PM PDT 24
Finished Mar 24 12:52:28 PM PDT 24
Peak memory 198032 kb
Host smart-3f7e2d1d-512c-4fcf-82a7-0c74b2f20064
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817635310 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.1817635310
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.aon_timer_jump.1466289460
Short name T138
Test name
Test status
Simulation time 510880686 ps
CPU time 0.77 seconds
Started Mar 24 12:50:05 PM PDT 24
Finished Mar 24 12:50:06 PM PDT 24
Peak memory 183084 kb
Host smart-e61782ad-6e3c-4142-9d1e-c2bfed59217f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466289460 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.1466289460
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.2256695360
Short name T223
Test name
Test status
Simulation time 20913546912 ps
CPU time 16.07 seconds
Started Mar 24 12:50:07 PM PDT 24
Finished Mar 24 12:50:23 PM PDT 24
Peak memory 183128 kb
Host smart-df0c6e24-84ea-4fd5-b205-f85fe0270ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256695360 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.2256695360
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.2729690878
Short name T154
Test name
Test status
Simulation time 546139045 ps
CPU time 0.9 seconds
Started Mar 24 12:50:26 PM PDT 24
Finished Mar 24 12:50:27 PM PDT 24
Peak memory 183072 kb
Host smart-13781c7e-4302-4e80-b4f2-d92b742e8170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729690878 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.2729690878
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.4003733083
Short name T94
Test name
Test status
Simulation time 65154163852 ps
CPU time 110.91 seconds
Started Mar 24 12:50:06 PM PDT 24
Finished Mar 24 12:51:57 PM PDT 24
Peak memory 194276 kb
Host smart-b8670ac7-07d5-48ef-99f8-59f1e5a68d03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003733083 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_
all.4003733083
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.653937569
Short name T189
Test name
Test status
Simulation time 39973536240 ps
CPU time 172.4 seconds
Started Mar 24 12:50:10 PM PDT 24
Finished Mar 24 12:53:03 PM PDT 24
Peak memory 198072 kb
Host smart-3e5b7b98-d994-4a96-a43f-a01806071f04
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653937569 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.653937569
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.aon_timer_jump.3692978682
Short name T160
Test name
Test status
Simulation time 574998852 ps
CPU time 0.7 seconds
Started Mar 24 12:50:26 PM PDT 24
Finished Mar 24 12:50:27 PM PDT 24
Peak memory 183056 kb
Host smart-d216b614-1342-42e9-935d-7e6ce3c20ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692978682 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.3692978682
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.3175174665
Short name T141
Test name
Test status
Simulation time 30847990315 ps
CPU time 13.3 seconds
Started Mar 24 12:50:16 PM PDT 24
Finished Mar 24 12:50:29 PM PDT 24
Peak memory 183112 kb
Host smart-d2b1477e-4549-4e72-9629-30d799db664d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175174665 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.3175174665
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.1522360188
Short name T48
Test name
Test status
Simulation time 351641381 ps
CPU time 0.69 seconds
Started Mar 24 12:50:05 PM PDT 24
Finished Mar 24 12:50:06 PM PDT 24
Peak memory 183068 kb
Host smart-636443ae-8940-415a-b013-4eecef2fa4ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522360188 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.1522360188
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.3976221795
Short name T97
Test name
Test status
Simulation time 197192865125 ps
CPU time 66.62 seconds
Started Mar 24 12:50:06 PM PDT 24
Finished Mar 24 12:51:13 PM PDT 24
Peak memory 193360 kb
Host smart-7a347041-cbe0-4e1a-b1da-25f4bee7a218
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976221795 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_
all.3976221795
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.4219223897
Short name T83
Test name
Test status
Simulation time 140360132401 ps
CPU time 340.93 seconds
Started Mar 24 12:50:05 PM PDT 24
Finished Mar 24 12:55:46 PM PDT 24
Peak memory 197964 kb
Host smart-298c8c38-439a-4b3a-a941-14ede361c2a1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219223897 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.4219223897
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.aon_timer_jump.2275563240
Short name T169
Test name
Test status
Simulation time 537243417 ps
CPU time 1.22 seconds
Started Mar 24 12:50:21 PM PDT 24
Finished Mar 24 12:50:23 PM PDT 24
Peak memory 183076 kb
Host smart-1bf3a845-3951-4f0c-977c-e288fbbf093b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275563240 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.2275563240
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.3630160538
Short name T164
Test name
Test status
Simulation time 38199652283 ps
CPU time 13.63 seconds
Started Mar 24 12:50:19 PM PDT 24
Finished Mar 24 12:50:33 PM PDT 24
Peak memory 183056 kb
Host smart-ca87bf97-cc0c-4d35-9b96-54d4051472a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630160538 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.3630160538
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.3910517318
Short name T192
Test name
Test status
Simulation time 428130168 ps
CPU time 1.27 seconds
Started Mar 24 12:50:24 PM PDT 24
Finished Mar 24 12:50:25 PM PDT 24
Peak memory 183072 kb
Host smart-edc9b2f3-d480-4930-b7f5-e9d3ba9a86ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910517318 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.3910517318
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.2494410150
Short name T133
Test name
Test status
Simulation time 67059490110 ps
CPU time 94.86 seconds
Started Mar 24 12:50:15 PM PDT 24
Finished Mar 24 12:51:51 PM PDT 24
Peak memory 183152 kb
Host smart-75958e96-7323-4d89-ac78-6e36343688d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494410150 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_
all.2494410150
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.1589279524
Short name T149
Test name
Test status
Simulation time 231002790902 ps
CPU time 694.74 seconds
Started Mar 24 12:50:11 PM PDT 24
Finished Mar 24 01:01:46 PM PDT 24
Peak memory 200256 kb
Host smart-adad3c65-94c4-416f-b8f8-9f22e98bc588
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589279524 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.1589279524
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.aon_timer_jump.3821628775
Short name T257
Test name
Test status
Simulation time 615192738 ps
CPU time 0.68 seconds
Started Mar 24 12:50:25 PM PDT 24
Finished Mar 24 12:50:26 PM PDT 24
Peak memory 183008 kb
Host smart-a84ddc58-1b41-48e1-8e1b-e161cd3f4335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821628775 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.3821628775
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.438257540
Short name T227
Test name
Test status
Simulation time 35376723150 ps
CPU time 51.2 seconds
Started Mar 24 12:50:25 PM PDT 24
Finished Mar 24 12:51:16 PM PDT 24
Peak memory 183112 kb
Host smart-c6616a0a-88e8-4fb7-9032-36220df70a87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438257540 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.438257540
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.3520107330
Short name T217
Test name
Test status
Simulation time 444118945 ps
CPU time 0.69 seconds
Started Mar 24 12:50:12 PM PDT 24
Finished Mar 24 12:50:13 PM PDT 24
Peak memory 183056 kb
Host smart-193dab49-aa9d-4166-9b55-3b46859d8e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520107330 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.3520107330
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.3023170617
Short name T215
Test name
Test status
Simulation time 191015967773 ps
CPU time 67.57 seconds
Started Mar 24 12:50:24 PM PDT 24
Finished Mar 24 12:51:31 PM PDT 24
Peak memory 193792 kb
Host smart-6ccc9fd8-1641-44b0-8da7-a0d0a0c88dae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023170617 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_
all.3023170617
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.3934409291
Short name T90
Test name
Test status
Simulation time 1857132432585 ps
CPU time 742.98 seconds
Started Mar 24 12:50:23 PM PDT 24
Finished Mar 24 01:02:46 PM PDT 24
Peak memory 200544 kb
Host smart-99f8bc10-ad7b-48d9-9b67-0ab0156add1d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934409291 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.3934409291
Directory /workspace/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.aon_timer_jump.2017324920
Short name T167
Test name
Test status
Simulation time 542239102 ps
CPU time 0.91 seconds
Started Mar 24 12:50:23 PM PDT 24
Finished Mar 24 12:50:24 PM PDT 24
Peak memory 182928 kb
Host smart-8d80c629-41d3-4906-82b7-fe15586c82a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017324920 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.2017324920
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.959515102
Short name T197
Test name
Test status
Simulation time 502523076 ps
CPU time 1.42 seconds
Started Mar 24 12:50:25 PM PDT 24
Finished Mar 24 12:50:26 PM PDT 24
Peak memory 183052 kb
Host smart-399e0b35-8625-4035-b1fe-9c61afba58ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959515102 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.959515102
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.3404830638
Short name T88
Test name
Test status
Simulation time 272509466697 ps
CPU time 546.8 seconds
Started Mar 24 12:50:22 PM PDT 24
Finished Mar 24 12:59:29 PM PDT 24
Peak memory 198204 kb
Host smart-42b323e4-cd29-4c37-a92e-77dcbb7146b2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404830638 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.3404830638
Directory /workspace/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_jump.2548608520
Short name T114
Test name
Test status
Simulation time 443793344 ps
CPU time 0.77 seconds
Started Mar 24 12:50:14 PM PDT 24
Finished Mar 24 12:50:15 PM PDT 24
Peak memory 183068 kb
Host smart-3a5a275d-8723-4496-97c9-d0e995e61355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548608520 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.2548608520
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.1508629806
Short name T5
Test name
Test status
Simulation time 50658289619 ps
CPU time 37.06 seconds
Started Mar 24 12:50:26 PM PDT 24
Finished Mar 24 12:51:03 PM PDT 24
Peak memory 183140 kb
Host smart-c1b243c9-7fa2-4f9b-95dc-8c823ba1b461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508629806 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.1508629806
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.3521155706
Short name T46
Test name
Test status
Simulation time 505871737 ps
CPU time 0.98 seconds
Started Mar 24 12:50:15 PM PDT 24
Finished Mar 24 12:50:16 PM PDT 24
Peak memory 182988 kb
Host smart-ec24ba20-6f10-466b-94e4-80565d577d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521155706 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.3521155706
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.3819534943
Short name T195
Test name
Test status
Simulation time 137583649529 ps
CPU time 26.84 seconds
Started Mar 24 12:50:11 PM PDT 24
Finished Mar 24 12:50:38 PM PDT 24
Peak memory 183124 kb
Host smart-6219cde1-0c80-4e62-a3f5-fe776b4ec4db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819534943 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_
all.3819534943
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.85918130
Short name T177
Test name
Test status
Simulation time 77869477917 ps
CPU time 321.13 seconds
Started Mar 24 12:50:23 PM PDT 24
Finished Mar 24 12:55:44 PM PDT 24
Peak memory 198012 kb
Host smart-cd799c15-b999-415e-a70e-687fa6ba77d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85918130 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.85918130
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.aon_timer_jump.1634107569
Short name T117
Test name
Test status
Simulation time 357727588 ps
CPU time 0.83 seconds
Started Mar 24 12:50:24 PM PDT 24
Finished Mar 24 12:50:25 PM PDT 24
Peak memory 182996 kb
Host smart-4f609e08-b559-42f5-847c-61e4d28faf5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634107569 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.1634107569
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.859789345
Short name T235
Test name
Test status
Simulation time 3159390703 ps
CPU time 2.92 seconds
Started Mar 24 12:50:12 PM PDT 24
Finished Mar 24 12:50:15 PM PDT 24
Peak memory 183132 kb
Host smart-5f3345e4-6a1a-4928-86d8-8ef4b2bbac99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859789345 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.859789345
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.2191216375
Short name T23
Test name
Test status
Simulation time 405789625 ps
CPU time 1.11 seconds
Started Mar 24 12:50:27 PM PDT 24
Finished Mar 24 12:50:29 PM PDT 24
Peak memory 182880 kb
Host smart-cf3bee67-a498-4934-8845-a1d6110325d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191216375 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.2191216375
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.951407934
Short name T14
Test name
Test status
Simulation time 78704041575 ps
CPU time 107.05 seconds
Started Mar 24 12:50:11 PM PDT 24
Finished Mar 24 12:51:58 PM PDT 24
Peak memory 183084 kb
Host smart-b8a0ad41-8505-4167-b8e8-61651cbadd4c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951407934 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_a
ll.951407934
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.1424592887
Short name T37
Test name
Test status
Simulation time 159123927147 ps
CPU time 458.89 seconds
Started Mar 24 12:50:12 PM PDT 24
Finished Mar 24 12:57:51 PM PDT 24
Peak memory 198040 kb
Host smart-43a4242b-a79f-4af5-8f5d-379bafc8efa9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424592887 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.1424592887
Directory /workspace/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.aon_timer_jump.3817389067
Short name T134
Test name
Test status
Simulation time 381928586 ps
CPU time 0.81 seconds
Started Mar 24 12:49:36 PM PDT 24
Finished Mar 24 12:49:37 PM PDT 24
Peak memory 183016 kb
Host smart-6fbe3f9b-5361-48d9-b12c-7117ce1732f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817389067 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.3817389067
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.3919613427
Short name T266
Test name
Test status
Simulation time 17856488596 ps
CPU time 6.22 seconds
Started Mar 24 12:49:38 PM PDT 24
Finished Mar 24 12:49:44 PM PDT 24
Peak memory 183080 kb
Host smart-fc32ce42-20f9-4b18-a4d3-685d65d3e2c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919613427 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.3919613427
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.1014728979
Short name T73
Test name
Test status
Simulation time 646642155 ps
CPU time 0.62 seconds
Started Mar 24 12:49:39 PM PDT 24
Finished Mar 24 12:49:39 PM PDT 24
Peak memory 183044 kb
Host smart-311d0a58-3e1f-4e73-81ec-27c21d5b919c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014728979 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.1014728979
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.4083122326
Short name T229
Test name
Test status
Simulation time 308740095687 ps
CPU time 486.12 seconds
Started Mar 24 12:49:38 PM PDT 24
Finished Mar 24 12:57:44 PM PDT 24
Peak memory 183136 kb
Host smart-249c0257-2636-413a-8711-fc0c4a0f28b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083122326 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_a
ll.4083122326
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.2417916746
Short name T250
Test name
Test status
Simulation time 239275522077 ps
CPU time 622.32 seconds
Started Mar 24 12:49:39 PM PDT 24
Finished Mar 24 01:00:02 PM PDT 24
Peak memory 200224 kb
Host smart-6a390d3f-427b-48a5-ab85-ab5510db7380
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417916746 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.2417916746
Directory /workspace/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.aon_timer_jump.2919693734
Short name T171
Test name
Test status
Simulation time 522335942 ps
CPU time 0.94 seconds
Started Mar 24 12:49:39 PM PDT 24
Finished Mar 24 12:49:40 PM PDT 24
Peak memory 182992 kb
Host smart-6e112c76-b525-45bd-bee8-775548c833d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919693734 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.2919693734
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.4209981316
Short name T191
Test name
Test status
Simulation time 21834471406 ps
CPU time 8.01 seconds
Started Mar 24 12:49:39 PM PDT 24
Finished Mar 24 12:49:47 PM PDT 24
Peak memory 183116 kb
Host smart-5f9d6bb6-07a8-4946-bab3-5e66e77fe4e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209981316 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.4209981316
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.587688753
Short name T254
Test name
Test status
Simulation time 535157630 ps
CPU time 0.94 seconds
Started Mar 24 12:49:40 PM PDT 24
Finished Mar 24 12:49:41 PM PDT 24
Peak memory 183048 kb
Host smart-a2d881f2-77a6-4931-8e24-92f66425ee2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587688753 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.587688753
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.3003679348
Short name T45
Test name
Test status
Simulation time 544143046766 ps
CPU time 200.99 seconds
Started Mar 24 12:49:37 PM PDT 24
Finished Mar 24 12:52:58 PM PDT 24
Peak memory 194504 kb
Host smart-2ecd11df-1ebf-44e8-9431-b7e31fe1af9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003679348 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_a
ll.3003679348
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.1831992921
Short name T39
Test name
Test status
Simulation time 57703148383 ps
CPU time 392.53 seconds
Started Mar 24 12:49:40 PM PDT 24
Finished Mar 24 12:56:12 PM PDT 24
Peak memory 197920 kb
Host smart-af7a8bd2-a3e0-425d-b225-2f74c0b2de03
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831992921 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.1831992921
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.aon_timer_jump.3484469415
Short name T249
Test name
Test status
Simulation time 457029963 ps
CPU time 1.26 seconds
Started Mar 24 12:49:37 PM PDT 24
Finished Mar 24 12:49:38 PM PDT 24
Peak memory 183080 kb
Host smart-6823d011-bb25-47ac-8b8c-c5e4aaeb5a4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484469415 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.3484469415
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.243908595
Short name T265
Test name
Test status
Simulation time 32465231964 ps
CPU time 13.56 seconds
Started Mar 24 12:49:40 PM PDT 24
Finished Mar 24 12:49:54 PM PDT 24
Peak memory 183112 kb
Host smart-319c42fc-b3a4-4f4b-bf4e-95785b394ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243908595 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.243908595
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.1515561249
Short name T12
Test name
Test status
Simulation time 507946980 ps
CPU time 1.37 seconds
Started Mar 24 12:49:40 PM PDT 24
Finished Mar 24 12:49:42 PM PDT 24
Peak memory 182964 kb
Host smart-f4b4d632-18aa-40c1-af01-33dee4e8e64c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515561249 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.1515561249
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.3155114162
Short name T75
Test name
Test status
Simulation time 96448214204 ps
CPU time 33.79 seconds
Started Mar 24 12:49:42 PM PDT 24
Finished Mar 24 12:50:16 PM PDT 24
Peak memory 193376 kb
Host smart-4116bee9-35a7-4fcb-bdf1-d9cb23423c08
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155114162 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_a
ll.3155114162
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.3541159776
Short name T230
Test name
Test status
Simulation time 69436349455 ps
CPU time 790.07 seconds
Started Mar 24 12:49:35 PM PDT 24
Finished Mar 24 01:02:46 PM PDT 24
Peak memory 200768 kb
Host smart-8f26370a-40b6-4b3c-8230-0d81636c41cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541159776 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.3541159776
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.aon_timer_jump.363672628
Short name T180
Test name
Test status
Simulation time 362096522 ps
CPU time 0.66 seconds
Started Mar 24 12:49:41 PM PDT 24
Finished Mar 24 12:49:41 PM PDT 24
Peak memory 182992 kb
Host smart-951eeaf0-8684-4dab-a546-4d5cd36e7975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363672628 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.363672628
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.521736342
Short name T127
Test name
Test status
Simulation time 41133630985 ps
CPU time 14.84 seconds
Started Mar 24 12:49:45 PM PDT 24
Finished Mar 24 12:49:59 PM PDT 24
Peak memory 183048 kb
Host smart-6d9a8578-b1b9-4a80-9990-3e89a427b194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521736342 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.521736342
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.3883896235
Short name T243
Test name
Test status
Simulation time 400653101 ps
CPU time 0.61 seconds
Started Mar 24 12:49:40 PM PDT 24
Finished Mar 24 12:49:41 PM PDT 24
Peak memory 182972 kb
Host smart-c0355885-cc76-489d-ab6b-0f000d88c5e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883896235 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.3883896235
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.709354988
Short name T251
Test name
Test status
Simulation time 24595094617 ps
CPU time 36.78 seconds
Started Mar 24 12:49:44 PM PDT 24
Finished Mar 24 12:50:21 PM PDT 24
Peak memory 193712 kb
Host smart-aea6a116-d019-4d6d-8db3-b8af1cd92627
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709354988 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_al
l.709354988
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.14106841
Short name T82
Test name
Test status
Simulation time 50768310032 ps
CPU time 503.04 seconds
Started Mar 24 12:49:42 PM PDT 24
Finished Mar 24 12:58:05 PM PDT 24
Peak memory 197968 kb
Host smart-1251ec87-2263-4f58-a964-f2457fc05ca5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14106841 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.14106841
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.aon_timer_jump.799336854
Short name T260
Test name
Test status
Simulation time 603140866 ps
CPU time 0.96 seconds
Started Mar 24 12:49:41 PM PDT 24
Finished Mar 24 12:49:42 PM PDT 24
Peak memory 183084 kb
Host smart-31ddf18b-85bb-4d55-a1e4-5c54a0807220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799336854 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.799336854
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.1736907407
Short name T131
Test name
Test status
Simulation time 36647405103 ps
CPU time 54.02 seconds
Started Mar 24 12:49:48 PM PDT 24
Finished Mar 24 12:50:42 PM PDT 24
Peak memory 183136 kb
Host smart-a4500765-5cf5-41e2-a3fa-aa1a55049eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736907407 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.1736907407
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.725926853
Short name T120
Test name
Test status
Simulation time 519487735 ps
CPU time 1.39 seconds
Started Mar 24 12:49:41 PM PDT 24
Finished Mar 24 12:49:43 PM PDT 24
Peak memory 182992 kb
Host smart-6e5d78c9-9d57-4cde-936f-9de7ab8476eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725926853 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.725926853
Directory /workspace/9.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.132551035
Short name T151
Test name
Test status
Simulation time 50728975162 ps
CPU time 49.07 seconds
Started Mar 24 12:49:45 PM PDT 24
Finished Mar 24 12:50:35 PM PDT 24
Peak memory 193472 kb
Host smart-80ac027b-92a0-498a-8bbf-daafaae30573
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132551035 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_al
l.132551035
Directory /workspace/9.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.2069862845
Short name T91
Test name
Test status
Simulation time 532694785188 ps
CPU time 449.2 seconds
Started Mar 24 12:49:42 PM PDT 24
Finished Mar 24 12:57:11 PM PDT 24
Peak memory 198016 kb
Host smart-bc12beb6-d333-465f-9c79-8ddf20bc8dd1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069862845 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.2069862845
Directory /workspace/9.aon_timer_stress_all_with_rand_reset/latest
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