Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
92.98 99.25 93.67 100.00 98.40 99.51 67.06


Total test records in report: 423
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T28 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.2275814077 Mar 26 01:49:32 PM PDT 24 Mar 26 01:49:33 PM PDT 24 574328663 ps
T29 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.3372644895 Mar 26 01:49:33 PM PDT 24 Mar 26 01:49:34 PM PDT 24 307339473 ps
T283 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.3143816370 Mar 26 01:48:55 PM PDT 24 Mar 26 01:48:56 PM PDT 24 400699356 ps
T30 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.2791662667 Mar 26 01:50:01 PM PDT 24 Mar 26 01:50:08 PM PDT 24 4204188900 ps
T284 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.2473177054 Mar 26 01:49:14 PM PDT 24 Mar 26 01:49:16 PM PDT 24 504776731 ps
T32 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.3283486390 Mar 26 01:49:03 PM PDT 24 Mar 26 01:49:06 PM PDT 24 1010340153 ps
T78 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.1850239213 Mar 26 01:49:52 PM PDT 24 Mar 26 01:49:53 PM PDT 24 495735033 ps
T79 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.536987471 Mar 26 01:49:43 PM PDT 24 Mar 26 01:49:44 PM PDT 24 2884518306 ps
T285 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.1218211687 Mar 26 01:50:18 PM PDT 24 Mar 26 01:50:19 PM PDT 24 329806007 ps
T106 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.2397314158 Mar 26 01:49:06 PM PDT 24 Mar 26 01:49:07 PM PDT 24 526831871 ps
T286 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.2062437232 Mar 26 01:49:06 PM PDT 24 Mar 26 01:49:07 PM PDT 24 1134543097 ps
T80 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.284019434 Mar 26 01:49:15 PM PDT 24 Mar 26 01:49:17 PM PDT 24 1365714053 ps
T287 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.2900642539 Mar 26 01:50:07 PM PDT 24 Mar 26 01:50:08 PM PDT 24 394163716 ps
T288 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.2712159957 Mar 26 01:50:13 PM PDT 24 Mar 26 01:50:14 PM PDT 24 397296101 ps
T33 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.967705074 Mar 26 01:49:33 PM PDT 24 Mar 26 01:49:36 PM PDT 24 9101549986 ps
T289 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.2908219690 Mar 26 01:49:34 PM PDT 24 Mar 26 01:49:35 PM PDT 24 445890789 ps
T290 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.2231170953 Mar 26 01:50:13 PM PDT 24 Mar 26 01:50:14 PM PDT 24 477263714 ps
T64 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.1790807133 Mar 26 01:49:27 PM PDT 24 Mar 26 01:49:28 PM PDT 24 457101620 ps
T291 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.3868067829 Mar 26 01:49:41 PM PDT 24 Mar 26 01:49:43 PM PDT 24 475956958 ps
T81 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.3348085391 Mar 26 01:49:04 PM PDT 24 Mar 26 01:49:05 PM PDT 24 1375182451 ps
T292 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.933030926 Mar 26 01:49:04 PM PDT 24 Mar 26 01:49:05 PM PDT 24 523524561 ps
T293 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.1891143220 Mar 26 01:50:14 PM PDT 24 Mar 26 01:50:15 PM PDT 24 309629519 ps
T34 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.2205934941 Mar 26 01:50:03 PM PDT 24 Mar 26 01:50:10 PM PDT 24 4639450553 ps
T294 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.56778627 Mar 26 01:50:13 PM PDT 24 Mar 26 01:50:14 PM PDT 24 340539020 ps
T295 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.1036513413 Mar 26 01:50:17 PM PDT 24 Mar 26 01:50:17 PM PDT 24 344675193 ps
T82 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.1463629436 Mar 26 01:49:08 PM PDT 24 Mar 26 01:49:09 PM PDT 24 320172637 ps
T296 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.2187330364 Mar 26 01:49:03 PM PDT 24 Mar 26 01:49:06 PM PDT 24 560334279 ps
T297 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.2313300596 Mar 26 01:50:13 PM PDT 24 Mar 26 01:50:15 PM PDT 24 384589563 ps
T298 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.3823885505 Mar 26 01:49:07 PM PDT 24 Mar 26 01:49:07 PM PDT 24 693844139 ps
T299 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.2364499302 Mar 26 01:50:01 PM PDT 24 Mar 26 01:50:02 PM PDT 24 342060847 ps
T300 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.4122611954 Mar 26 01:50:18 PM PDT 24 Mar 26 01:50:19 PM PDT 24 433727198 ps
T301 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.2449748281 Mar 26 01:49:34 PM PDT 24 Mar 26 01:49:36 PM PDT 24 445521589 ps
T302 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.3058441814 Mar 26 01:50:01 PM PDT 24 Mar 26 01:50:04 PM PDT 24 800868707 ps
T303 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.2465341197 Mar 26 01:50:22 PM PDT 24 Mar 26 01:50:23 PM PDT 24 388624793 ps
T304 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.334645591 Mar 26 01:49:59 PM PDT 24 Mar 26 01:50:01 PM PDT 24 553088505 ps
T83 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.2849641089 Mar 26 01:49:44 PM PDT 24 Mar 26 01:49:45 PM PDT 24 1433428218 ps
T305 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.411629275 Mar 26 01:49:52 PM PDT 24 Mar 26 01:49:54 PM PDT 24 502146759 ps
T306 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.695523225 Mar 26 01:49:58 PM PDT 24 Mar 26 01:50:00 PM PDT 24 459445192 ps
T65 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.2904748532 Mar 26 01:49:34 PM PDT 24 Mar 26 01:49:35 PM PDT 24 413111425 ps
T307 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.1625199154 Mar 26 01:49:13 PM PDT 24 Mar 26 01:49:14 PM PDT 24 439369730 ps
T308 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.809046562 Mar 26 01:49:13 PM PDT 24 Mar 26 01:49:14 PM PDT 24 518295485 ps
T309 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.1408253960 Mar 26 01:49:34 PM PDT 24 Mar 26 01:49:36 PM PDT 24 501835751 ps
T103 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.2553008302 Mar 26 01:50:00 PM PDT 24 Mar 26 01:50:04 PM PDT 24 4500015950 ps
T310 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.3823266519 Mar 26 01:50:05 PM PDT 24 Mar 26 01:50:08 PM PDT 24 1168627334 ps
T66 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.4149393639 Mar 26 01:49:32 PM PDT 24 Mar 26 01:49:33 PM PDT 24 362162983 ps
T311 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.2540423175 Mar 26 01:49:44 PM PDT 24 Mar 26 01:49:45 PM PDT 24 509235972 ps
T84 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.543346178 Mar 26 01:49:42 PM PDT 24 Mar 26 01:49:43 PM PDT 24 410216124 ps
T85 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.523143538 Mar 26 01:49:32 PM PDT 24 Mar 26 01:49:33 PM PDT 24 1701500078 ps
T312 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.4268090796 Mar 26 01:49:42 PM PDT 24 Mar 26 01:49:43 PM PDT 24 443007433 ps
T313 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.1756455720 Mar 26 01:50:13 PM PDT 24 Mar 26 01:50:14 PM PDT 24 444445134 ps
T314 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.425497097 Mar 26 01:50:01 PM PDT 24 Mar 26 01:50:02 PM PDT 24 385312551 ps
T315 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.2066085485 Mar 26 01:50:18 PM PDT 24 Mar 26 01:50:18 PM PDT 24 390274417 ps
T316 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.1114310216 Mar 26 01:49:52 PM PDT 24 Mar 26 01:49:54 PM PDT 24 570056908 ps
T317 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.3011157339 Mar 26 01:50:12 PM PDT 24 Mar 26 01:50:13 PM PDT 24 415618859 ps
T318 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.185511927 Mar 26 01:49:12 PM PDT 24 Mar 26 01:49:13 PM PDT 24 484926340 ps
T319 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.2622284120 Mar 26 01:49:51 PM PDT 24 Mar 26 01:49:54 PM PDT 24 535566380 ps
T320 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.958584230 Mar 26 01:50:13 PM PDT 24 Mar 26 01:50:14 PM PDT 24 382201940 ps
T67 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.4216939316 Mar 26 01:49:13 PM PDT 24 Mar 26 01:49:15 PM PDT 24 509807123 ps
T321 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.427895513 Mar 26 01:50:11 PM PDT 24 Mar 26 01:50:13 PM PDT 24 4121022216 ps
T322 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.4078861313 Mar 26 01:50:07 PM PDT 24 Mar 26 01:50:07 PM PDT 24 358165213 ps
T323 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.4066114864 Mar 26 01:49:32 PM PDT 24 Mar 26 01:49:35 PM PDT 24 4308409756 ps
T324 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.2493558601 Mar 26 01:48:52 PM PDT 24 Mar 26 01:48:53 PM PDT 24 327429844 ps
T325 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.992432125 Mar 26 01:49:52 PM PDT 24 Mar 26 01:49:53 PM PDT 24 335854461 ps
T326 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.2268147128 Mar 26 01:50:17 PM PDT 24 Mar 26 01:50:17 PM PDT 24 396420440 ps
T327 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.4246929217 Mar 26 01:50:01 PM PDT 24 Mar 26 01:50:03 PM PDT 24 520628240 ps
T328 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.1690853482 Mar 26 01:48:53 PM PDT 24 Mar 26 01:48:57 PM PDT 24 8387409644 ps
T329 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.3431884762 Mar 26 01:49:02 PM PDT 24 Mar 26 01:49:04 PM PDT 24 467205618 ps
T330 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.1462078168 Mar 26 01:49:31 PM PDT 24 Mar 26 01:49:32 PM PDT 24 397417914 ps
T331 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.2094629182 Mar 26 01:48:54 PM PDT 24 Mar 26 01:48:55 PM PDT 24 590473990 ps
T332 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.2556512337 Mar 26 01:49:25 PM PDT 24 Mar 26 01:49:26 PM PDT 24 504472564 ps
T333 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.2538723031 Mar 26 01:49:04 PM PDT 24 Mar 26 01:49:19 PM PDT 24 8577067232 ps
T104 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.3109340239 Mar 26 01:48:53 PM PDT 24 Mar 26 01:48:57 PM PDT 24 7734076193 ps
T68 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.2152335810 Mar 26 01:49:14 PM PDT 24 Mar 26 01:49:18 PM PDT 24 8540476355 ps
T334 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.1497099255 Mar 26 01:49:51 PM PDT 24 Mar 26 01:49:53 PM PDT 24 1116071889 ps
T335 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.2830353214 Mar 26 01:49:26 PM PDT 24 Mar 26 01:49:27 PM PDT 24 429851457 ps
T336 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.318367618 Mar 26 01:49:52 PM PDT 24 Mar 26 01:49:53 PM PDT 24 335615332 ps
T337 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.3132348918 Mar 26 01:49:34 PM PDT 24 Mar 26 01:49:37 PM PDT 24 568993596 ps
T338 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.4188235571 Mar 26 01:49:41 PM PDT 24 Mar 26 01:49:43 PM PDT 24 372112292 ps
T339 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.1392250177 Mar 26 01:49:45 PM PDT 24 Mar 26 01:49:56 PM PDT 24 7922532332 ps
T340 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.2483781868 Mar 26 01:49:42 PM PDT 24 Mar 26 01:49:43 PM PDT 24 499087946 ps
T341 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.3532777581 Mar 26 01:48:55 PM PDT 24 Mar 26 01:48:55 PM PDT 24 453975312 ps
T342 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.87361945 Mar 26 01:50:01 PM PDT 24 Mar 26 01:50:02 PM PDT 24 311063793 ps
T343 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.2309437312 Mar 26 01:50:15 PM PDT 24 Mar 26 01:50:16 PM PDT 24 447640366 ps
T69 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.2278529190 Mar 26 01:49:42 PM PDT 24 Mar 26 01:49:43 PM PDT 24 479199942 ps
T344 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.281296844 Mar 26 01:50:14 PM PDT 24 Mar 26 01:50:15 PM PDT 24 310638922 ps
T345 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.771072387 Mar 26 01:49:52 PM PDT 24 Mar 26 01:49:53 PM PDT 24 362436625 ps
T346 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.1124175876 Mar 26 01:49:33 PM PDT 24 Mar 26 01:49:34 PM PDT 24 448978154 ps
T347 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.1011230762 Mar 26 01:49:34 PM PDT 24 Mar 26 01:49:38 PM PDT 24 2216247017 ps
T348 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.1839738129 Mar 26 01:49:54 PM PDT 24 Mar 26 01:50:01 PM PDT 24 2527789579 ps
T349 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.3568837043 Mar 26 01:50:01 PM PDT 24 Mar 26 01:50:03 PM PDT 24 3086337900 ps
T350 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.897879254 Mar 26 01:49:54 PM PDT 24 Mar 26 01:49:59 PM PDT 24 8208166067 ps
T351 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.1921936358 Mar 26 01:50:01 PM PDT 24 Mar 26 01:50:02 PM PDT 24 308694673 ps
T352 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.3990196292 Mar 26 01:48:52 PM PDT 24 Mar 26 01:48:54 PM PDT 24 482986568 ps
T353 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.14635400 Mar 26 01:49:03 PM PDT 24 Mar 26 01:49:04 PM PDT 24 349126612 ps
T354 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.1985808676 Mar 26 01:49:03 PM PDT 24 Mar 26 01:49:04 PM PDT 24 345120849 ps
T355 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.2119371421 Mar 26 01:50:02 PM PDT 24 Mar 26 01:50:03 PM PDT 24 1048928614 ps
T356 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.2836752280 Mar 26 01:49:24 PM PDT 24 Mar 26 01:49:26 PM PDT 24 1235056715 ps
T357 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.1541950857 Mar 26 01:48:55 PM PDT 24 Mar 26 01:48:55 PM PDT 24 436299483 ps
T358 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.423166552 Mar 26 01:49:33 PM PDT 24 Mar 26 01:49:36 PM PDT 24 908239531 ps
T359 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.1339231505 Mar 26 01:49:26 PM PDT 24 Mar 26 01:49:26 PM PDT 24 427266822 ps
T70 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.3629868507 Mar 26 01:49:03 PM PDT 24 Mar 26 01:49:05 PM PDT 24 360347104 ps
T360 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.2838252235 Mar 26 01:49:04 PM PDT 24 Mar 26 01:49:04 PM PDT 24 447789780 ps
T361 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.4185938798 Mar 26 01:50:11 PM PDT 24 Mar 26 01:50:12 PM PDT 24 545412565 ps
T362 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.2392892247 Mar 26 01:50:23 PM PDT 24 Mar 26 01:50:24 PM PDT 24 289824710 ps
T363 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.2142634916 Mar 26 01:49:59 PM PDT 24 Mar 26 01:50:01 PM PDT 24 593323919 ps
T364 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.1729182150 Mar 26 01:49:25 PM PDT 24 Mar 26 01:49:27 PM PDT 24 615986593 ps
T365 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.3925136885 Mar 26 01:50:02 PM PDT 24 Mar 26 01:50:05 PM PDT 24 1511882981 ps
T366 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.991552897 Mar 26 01:50:23 PM PDT 24 Mar 26 01:50:24 PM PDT 24 474371020 ps
T367 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.377210686 Mar 26 01:49:52 PM PDT 24 Mar 26 01:49:53 PM PDT 24 384215337 ps
T368 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.1788653716 Mar 26 01:49:51 PM PDT 24 Mar 26 01:49:53 PM PDT 24 316037983 ps
T369 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.1691552054 Mar 26 01:50:11 PM PDT 24 Mar 26 01:50:12 PM PDT 24 376901526 ps
T71 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.3718007396 Mar 26 01:49:08 PM PDT 24 Mar 26 01:49:09 PM PDT 24 748695100 ps
T370 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.825743263 Mar 26 01:49:35 PM PDT 24 Mar 26 01:49:37 PM PDT 24 543136006 ps
T371 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.385723430 Mar 26 01:49:52 PM PDT 24 Mar 26 01:50:06 PM PDT 24 8554998078 ps
T76 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.477278166 Mar 26 01:49:54 PM PDT 24 Mar 26 01:49:56 PM PDT 24 474999740 ps
T372 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.1207897904 Mar 26 01:49:41 PM PDT 24 Mar 26 01:49:46 PM PDT 24 8698615518 ps
T373 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.308192334 Mar 26 01:49:32 PM PDT 24 Mar 26 01:49:34 PM PDT 24 399696520 ps
T374 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.2380753575 Mar 26 01:50:10 PM PDT 24 Mar 26 01:50:13 PM PDT 24 1153277263 ps
T375 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.3021802036 Mar 26 01:48:54 PM PDT 24 Mar 26 01:48:55 PM PDT 24 344699459 ps
T376 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.1327461669 Mar 26 01:50:15 PM PDT 24 Mar 26 01:50:16 PM PDT 24 297736484 ps
T73 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.3275987362 Mar 26 01:48:55 PM PDT 24 Mar 26 01:49:08 PM PDT 24 5082468249 ps
T377 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.1010469717 Mar 26 01:49:15 PM PDT 24 Mar 26 01:49:16 PM PDT 24 477002851 ps
T378 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.2199912419 Mar 26 01:49:41 PM PDT 24 Mar 26 01:49:43 PM PDT 24 4866591785 ps
T379 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.434032940 Mar 26 01:50:01 PM PDT 24 Mar 26 01:50:02 PM PDT 24 485977733 ps
T380 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.2611381013 Mar 26 01:49:32 PM PDT 24 Mar 26 01:49:35 PM PDT 24 707587006 ps
T74 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.3850752683 Mar 26 01:49:31 PM PDT 24 Mar 26 01:49:34 PM PDT 24 764213718 ps
T381 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.1977332270 Mar 26 01:49:04 PM PDT 24 Mar 26 01:49:20 PM PDT 24 7316696253 ps
T382 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.2713965386 Mar 26 01:49:15 PM PDT 24 Mar 26 01:49:16 PM PDT 24 819751715 ps
T383 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.1875335440 Mar 26 01:49:25 PM PDT 24 Mar 26 01:49:26 PM PDT 24 440956257 ps
T384 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.1308419403 Mar 26 01:49:14 PM PDT 24 Mar 26 01:49:15 PM PDT 24 418426966 ps
T77 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.3076632776 Mar 26 01:49:06 PM PDT 24 Mar 26 01:49:08 PM PDT 24 889794555 ps
T385 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.3642747708 Mar 26 01:48:54 PM PDT 24 Mar 26 01:48:55 PM PDT 24 821932902 ps
T386 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.1232869865 Mar 26 01:50:14 PM PDT 24 Mar 26 01:50:15 PM PDT 24 310026150 ps
T387 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.1073712581 Mar 26 01:48:53 PM PDT 24 Mar 26 01:48:57 PM PDT 24 2385247974 ps
T388 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.625967294 Mar 26 01:49:52 PM PDT 24 Mar 26 01:49:54 PM PDT 24 1194796969 ps
T389 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.1297829600 Mar 26 01:49:08 PM PDT 24 Mar 26 01:49:09 PM PDT 24 599646018 ps
T390 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.602697071 Mar 26 01:49:11 PM PDT 24 Mar 26 01:49:12 PM PDT 24 518588563 ps
T105 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.542732548 Mar 26 01:49:13 PM PDT 24 Mar 26 01:49:21 PM PDT 24 4341258232 ps
T391 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.2222316119 Mar 26 01:48:54 PM PDT 24 Mar 26 01:48:55 PM PDT 24 429663091 ps
T392 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.3750209746 Mar 26 01:50:17 PM PDT 24 Mar 26 01:50:18 PM PDT 24 497969675 ps
T393 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.4206127420 Mar 26 01:49:52 PM PDT 24 Mar 26 01:49:54 PM PDT 24 630099248 ps
T394 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.2346343222 Mar 26 01:49:26 PM PDT 24 Mar 26 01:49:41 PM PDT 24 8221603973 ps
T395 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.4219412291 Mar 26 01:49:14 PM PDT 24 Mar 26 01:49:15 PM PDT 24 390296739 ps
T396 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.3636233181 Mar 26 01:49:50 PM PDT 24 Mar 26 01:49:52 PM PDT 24 574113493 ps
T397 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.3478350003 Mar 26 01:49:34 PM PDT 24 Mar 26 01:49:42 PM PDT 24 2532087889 ps
T398 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.1980419702 Mar 26 01:49:41 PM PDT 24 Mar 26 01:49:42 PM PDT 24 1408352174 ps
T399 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.3333568975 Mar 26 01:49:11 PM PDT 24 Mar 26 01:49:16 PM PDT 24 8004555043 ps
T400 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.2010385922 Mar 26 01:50:06 PM PDT 24 Mar 26 01:50:07 PM PDT 24 373443621 ps
T401 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.1995445031 Mar 26 01:49:33 PM PDT 24 Mar 26 01:49:34 PM PDT 24 491007614 ps
T402 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.3502682605 Mar 26 01:50:07 PM PDT 24 Mar 26 01:50:08 PM PDT 24 381912059 ps
T403 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.3794606861 Mar 26 01:49:25 PM PDT 24 Mar 26 01:49:27 PM PDT 24 1430976893 ps
T404 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.1473981195 Mar 26 01:49:31 PM PDT 24 Mar 26 01:49:32 PM PDT 24 416176812 ps
T405 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.1564753719 Mar 26 01:49:44 PM PDT 24 Mar 26 01:49:45 PM PDT 24 345216361 ps
T406 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.3186644204 Mar 26 01:49:49 PM PDT 24 Mar 26 01:49:54 PM PDT 24 4130393471 ps
T407 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.1716691913 Mar 26 01:49:34 PM PDT 24 Mar 26 01:49:44 PM PDT 24 7972393515 ps
T408 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.2169366962 Mar 26 01:49:32 PM PDT 24 Mar 26 01:49:36 PM PDT 24 8949571101 ps
T409 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.4245852973 Mar 26 01:50:14 PM PDT 24 Mar 26 01:50:15 PM PDT 24 497991393 ps
T410 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.3933712915 Mar 26 01:49:59 PM PDT 24 Mar 26 01:50:01 PM PDT 24 374248395 ps
T411 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.1153615996 Mar 26 01:49:51 PM PDT 24 Mar 26 01:49:52 PM PDT 24 345794173 ps
T412 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.1475483251 Mar 26 01:50:06 PM PDT 24 Mar 26 01:50:07 PM PDT 24 440776673 ps
T413 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.554397144 Mar 26 01:49:51 PM PDT 24 Mar 26 01:49:55 PM PDT 24 2315043861 ps
T414 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.67966345 Mar 26 01:50:02 PM PDT 24 Mar 26 01:50:03 PM PDT 24 323801916 ps
T415 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.3079485562 Mar 26 01:49:26 PM PDT 24 Mar 26 01:49:27 PM PDT 24 1331709688 ps
T72 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.2740788132 Mar 26 01:49:13 PM PDT 24 Mar 26 01:49:14 PM PDT 24 576020155 ps
T75 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.4139300117 Mar 26 01:48:54 PM PDT 24 Mar 26 01:48:55 PM PDT 24 473265436 ps
T416 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.2187204306 Mar 26 01:49:54 PM PDT 24 Mar 26 01:49:56 PM PDT 24 270035053 ps
T417 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.4108701787 Mar 26 01:48:53 PM PDT 24 Mar 26 01:48:54 PM PDT 24 508151778 ps
T418 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.686861844 Mar 26 01:49:42 PM PDT 24 Mar 26 01:49:44 PM PDT 24 361791480 ps
T419 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.3760014474 Mar 26 01:49:42 PM PDT 24 Mar 26 01:49:43 PM PDT 24 474509426 ps
T420 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.3806385534 Mar 26 01:50:06 PM PDT 24 Mar 26 01:50:07 PM PDT 24 440816024 ps
T421 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.3979970697 Mar 26 01:50:15 PM PDT 24 Mar 26 01:50:16 PM PDT 24 387396974 ps
T422 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.49583972 Mar 26 01:49:14 PM PDT 24 Mar 26 01:49:15 PM PDT 24 589842712 ps
T423 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.3700940173 Mar 26 01:50:13 PM PDT 24 Mar 26 01:50:14 PM PDT 24 466254091 ps

Test location /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.3588231074
Short name T4
Test name
Test status
Simulation time 300992415727 ps
CPU time 603.75 seconds
Started Mar 26 02:45:06 PM PDT 24
Finished Mar 26 02:55:09 PM PDT 24
Peak memory 199504 kb
Host smart-d3e68312-99c3-4812-9b7a-eaf3f36abd25
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588231074 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.3588231074
Directory /workspace/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.2791662667
Short name T30
Test name
Test status
Simulation time 4204188900 ps
CPU time 7.13 seconds
Started Mar 26 01:50:01 PM PDT 24
Finished Mar 26 01:50:08 PM PDT 24
Peak memory 197572 kb
Host smart-ad4f5e1c-3278-4aed-b4a2-ffe23afcfcee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791662667 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_t
l_intg_err.2791662667
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.4143872263
Short name T19
Test name
Test status
Simulation time 92405509770 ps
CPU time 271.11 seconds
Started Mar 26 02:44:50 PM PDT 24
Finished Mar 26 02:49:22 PM PDT 24
Peak memory 198444 kb
Host smart-8cdb7a81-bfcf-4716-be43-e099ca8d332f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143872263 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.4143872263
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.1048715602
Short name T11
Test name
Test status
Simulation time 161266167452 ps
CPU time 126.8 seconds
Started Mar 26 02:45:03 PM PDT 24
Finished Mar 26 02:47:10 PM PDT 24
Peak memory 183456 kb
Host smart-591ac9c0-d99b-46a8-aa46-f32a32510956
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048715602 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_
all.1048715602
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.2904748532
Short name T65
Test name
Test status
Simulation time 413111425 ps
CPU time 0.82 seconds
Started Mar 26 01:49:34 PM PDT 24
Finished Mar 26 01:49:35 PM PDT 24
Peak memory 183504 kb
Host smart-36a1ea55-4150-4948-a1d5-aa7f7ebe28fe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904748532 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.2904748532
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.3311209408
Short name T14
Test name
Test status
Simulation time 8193644522 ps
CPU time 10.57 seconds
Started Mar 26 02:44:08 PM PDT 24
Finished Mar 26 02:44:19 PM PDT 24
Peak memory 215508 kb
Host smart-4d899c88-84d8-4c72-b47c-e526c219e4c6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311209408 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.3311209408
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.2172996082
Short name T89
Test name
Test status
Simulation time 163951113869 ps
CPU time 442.32 seconds
Started Mar 26 02:44:27 PM PDT 24
Finished Mar 26 02:51:50 PM PDT 24
Peak memory 198484 kb
Host smart-b5e1923e-3d9e-45bb-8b1a-fedd973641fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172996082 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.2172996082
Directory /workspace/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.2346343222
Short name T394
Test name
Test status
Simulation time 8221603973 ps
CPU time 14.39 seconds
Started Mar 26 01:49:26 PM PDT 24
Finished Mar 26 01:49:41 PM PDT 24
Peak memory 197840 kb
Host smart-ed3077b1-e58f-4e43-a06d-27a2f5b1911e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346343222 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl
_intg_err.2346343222
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.4096916379
Short name T8
Test name
Test status
Simulation time 423011132806 ps
CPU time 50.36 seconds
Started Mar 26 02:44:18 PM PDT 24
Finished Mar 26 02:45:08 PM PDT 24
Peak memory 183472 kb
Host smart-be4364f7-63d9-4dab-83ac-b5ff43181afd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096916379 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_a
ll.4096916379
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.4139300117
Short name T75
Test name
Test status
Simulation time 473265436 ps
CPU time 1.07 seconds
Started Mar 26 01:48:54 PM PDT 24
Finished Mar 26 01:48:55 PM PDT 24
Peak memory 193948 kb
Host smart-c689b035-a359-485d-b206-7fedf08e683f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139300117 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_a
liasing.4139300117
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.3275987362
Short name T73
Test name
Test status
Simulation time 5082468249 ps
CPU time 13.58 seconds
Started Mar 26 01:48:55 PM PDT 24
Finished Mar 26 01:49:08 PM PDT 24
Peak memory 184016 kb
Host smart-2a879bd6-efe4-4924-9309-a4caa74d5832
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275987362 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_b
it_bash.3275987362
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.3642747708
Short name T385
Test name
Test status
Simulation time 821932902 ps
CPU time 0.79 seconds
Started Mar 26 01:48:54 PM PDT 24
Finished Mar 26 01:48:55 PM PDT 24
Peak memory 183612 kb
Host smart-ef94dc08-9209-41f4-a3a7-ff7cdd8f9892
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642747708 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_h
w_reset.3642747708
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.2094629182
Short name T331
Test name
Test status
Simulation time 590473990 ps
CPU time 0.9 seconds
Started Mar 26 01:48:54 PM PDT 24
Finished Mar 26 01:48:55 PM PDT 24
Peak memory 198124 kb
Host smart-12222329-f00c-4331-b190-6a5918b1584d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094629182 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.2094629182
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.2493558601
Short name T324
Test name
Test status
Simulation time 327429844 ps
CPU time 0.62 seconds
Started Mar 26 01:48:52 PM PDT 24
Finished Mar 26 01:48:53 PM PDT 24
Peak memory 193060 kb
Host smart-38c17ea3-eadb-4b80-b174-f3c678277554
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493558601 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.2493558601
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.4108701787
Short name T417
Test name
Test status
Simulation time 508151778 ps
CPU time 0.72 seconds
Started Mar 26 01:48:53 PM PDT 24
Finished Mar 26 01:48:54 PM PDT 24
Peak memory 183708 kb
Host smart-242696a4-043d-4ef2-8e9c-25d9aa864f8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108701787 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.4108701787
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.3532777581
Short name T341
Test name
Test status
Simulation time 453975312 ps
CPU time 0.69 seconds
Started Mar 26 01:48:55 PM PDT 24
Finished Mar 26 01:48:55 PM PDT 24
Peak memory 183596 kb
Host smart-97631160-4a97-45aa-88e0-e853f16250ee
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532777581 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_t
imer_mem_partial_access.3532777581
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.1541950857
Short name T357
Test name
Test status
Simulation time 436299483 ps
CPU time 0.54 seconds
Started Mar 26 01:48:55 PM PDT 24
Finished Mar 26 01:48:55 PM PDT 24
Peak memory 183640 kb
Host smart-99592787-ae1c-497b-8ccd-754077dee8d2
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541950857 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_w
alk.1541950857
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.1073712581
Short name T387
Test name
Test status
Simulation time 2385247974 ps
CPU time 4.1 seconds
Started Mar 26 01:48:53 PM PDT 24
Finished Mar 26 01:48:57 PM PDT 24
Peak memory 194548 kb
Host smart-350f199e-b142-4514-9113-14febe3cd9d5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073712581 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon
_timer_same_csr_outstanding.1073712581
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.3021802036
Short name T375
Test name
Test status
Simulation time 344699459 ps
CPU time 1.12 seconds
Started Mar 26 01:48:54 PM PDT 24
Finished Mar 26 01:48:55 PM PDT 24
Peak memory 198324 kb
Host smart-f87eaac6-0d91-4885-bc2a-f3351976b436
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021802036 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.3021802036
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.1690853482
Short name T328
Test name
Test status
Simulation time 8387409644 ps
CPU time 4.31 seconds
Started Mar 26 01:48:53 PM PDT 24
Finished Mar 26 01:48:57 PM PDT 24
Peak memory 198172 kb
Host smart-f2c350ef-cd84-4015-a68d-39e849ccd378
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690853482 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl
_intg_err.1690853482
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.3629868507
Short name T70
Test name
Test status
Simulation time 360347104 ps
CPU time 1.21 seconds
Started Mar 26 01:49:03 PM PDT 24
Finished Mar 26 01:49:05 PM PDT 24
Peak memory 193284 kb
Host smart-ba288cfb-25fa-48b0-ada8-9748ad364fa9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629868507 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_a
liasing.3629868507
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.3718007396
Short name T71
Test name
Test status
Simulation time 748695100 ps
CPU time 1.74 seconds
Started Mar 26 01:49:08 PM PDT 24
Finished Mar 26 01:49:09 PM PDT 24
Peak memory 192104 kb
Host smart-0a6ca4e2-9cd4-4283-9fed-d619d6287a80
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718007396 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_b
it_bash.3718007396
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.3076632776
Short name T77
Test name
Test status
Simulation time 889794555 ps
CPU time 1.91 seconds
Started Mar 26 01:49:06 PM PDT 24
Finished Mar 26 01:49:08 PM PDT 24
Peak memory 193268 kb
Host smart-ed781655-65c1-4ae7-aa3a-f034de7dd729
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076632776 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_h
w_reset.3076632776
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.1297829600
Short name T389
Test name
Test status
Simulation time 599646018 ps
CPU time 1.31 seconds
Started Mar 26 01:49:08 PM PDT 24
Finished Mar 26 01:49:09 PM PDT 24
Peak memory 195616 kb
Host smart-358d3a67-1a53-4994-af8f-8bc8194c2a09
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297829600 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.1297829600
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.1463629436
Short name T82
Test name
Test status
Simulation time 320172637 ps
CPU time 1.18 seconds
Started Mar 26 01:49:08 PM PDT 24
Finished Mar 26 01:49:09 PM PDT 24
Peak memory 183756 kb
Host smart-f2bdcb18-ba9b-4d45-8d12-acb9e64a867f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463629436 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.1463629436
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.2222316119
Short name T391
Test name
Test status
Simulation time 429663091 ps
CPU time 1.17 seconds
Started Mar 26 01:48:54 PM PDT 24
Finished Mar 26 01:48:55 PM PDT 24
Peak memory 183672 kb
Host smart-e42d6616-3cf2-4104-b378-4e26ab154972
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222316119 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.2222316119
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.3431884762
Short name T329
Test name
Test status
Simulation time 467205618 ps
CPU time 1.18 seconds
Started Mar 26 01:49:02 PM PDT 24
Finished Mar 26 01:49:04 PM PDT 24
Peak memory 183632 kb
Host smart-0981d96d-9c67-4d2b-94cb-5f8d93f34b89
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431884762 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_t
imer_mem_partial_access.3431884762
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.3143816370
Short name T283
Test name
Test status
Simulation time 400699356 ps
CPU time 0.82 seconds
Started Mar 26 01:48:55 PM PDT 24
Finished Mar 26 01:48:56 PM PDT 24
Peak memory 183628 kb
Host smart-e21d9d12-86f9-4ecd-b068-21983bd7e15c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143816370 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_w
alk.3143816370
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.3283486390
Short name T32
Test name
Test status
Simulation time 1010340153 ps
CPU time 2.23 seconds
Started Mar 26 01:49:03 PM PDT 24
Finished Mar 26 01:49:06 PM PDT 24
Peak memory 193272 kb
Host smart-7080166f-3e2d-4e84-8c15-3419be21c928
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283486390 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon
_timer_same_csr_outstanding.3283486390
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.3990196292
Short name T352
Test name
Test status
Simulation time 482986568 ps
CPU time 2.1 seconds
Started Mar 26 01:48:52 PM PDT 24
Finished Mar 26 01:48:54 PM PDT 24
Peak memory 198912 kb
Host smart-77bd3be7-1bd6-480f-82bb-918f843052f0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990196292 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.3990196292
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.3109340239
Short name T104
Test name
Test status
Simulation time 7734076193 ps
CPU time 3.76 seconds
Started Mar 26 01:48:53 PM PDT 24
Finished Mar 26 01:48:57 PM PDT 24
Peak memory 197988 kb
Host smart-32e9e0de-d711-4cb0-8486-10b391e7f1d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109340239 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl
_intg_err.3109340239
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.1564753719
Short name T405
Test name
Test status
Simulation time 345216361 ps
CPU time 0.94 seconds
Started Mar 26 01:49:44 PM PDT 24
Finished Mar 26 01:49:45 PM PDT 24
Peak memory 195852 kb
Host smart-177878ef-d47f-4e44-9683-805f24dbbf1e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564753719 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.1564753719
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.543346178
Short name T84
Test name
Test status
Simulation time 410216124 ps
CPU time 0.63 seconds
Started Mar 26 01:49:42 PM PDT 24
Finished Mar 26 01:49:43 PM PDT 24
Peak memory 193044 kb
Host smart-4136f838-6295-4ace-be3a-d17e8bbafbf1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543346178 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.543346178
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.4268090796
Short name T312
Test name
Test status
Simulation time 443007433 ps
CPU time 0.72 seconds
Started Mar 26 01:49:42 PM PDT 24
Finished Mar 26 01:49:43 PM PDT 24
Peak memory 183628 kb
Host smart-8b626fff-5527-46f2-856c-d783d10fec65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268090796 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.4268090796
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.1980419702
Short name T398
Test name
Test status
Simulation time 1408352174 ps
CPU time 1.08 seconds
Started Mar 26 01:49:41 PM PDT 24
Finished Mar 26 01:49:42 PM PDT 24
Peak memory 183732 kb
Host smart-c66cd8db-cd19-4289-ab5c-40e04e45f055
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980419702 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.ao
n_timer_same_csr_outstanding.1980419702
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.3868067829
Short name T291
Test name
Test status
Simulation time 475956958 ps
CPU time 1.3 seconds
Started Mar 26 01:49:41 PM PDT 24
Finished Mar 26 01:49:43 PM PDT 24
Peak memory 198544 kb
Host smart-f9b463ce-0ab0-409c-aee8-0b90bc27ec70
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868067829 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.3868067829
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.2199912419
Short name T378
Test name
Test status
Simulation time 4866591785 ps
CPU time 1.55 seconds
Started Mar 26 01:49:41 PM PDT 24
Finished Mar 26 01:49:43 PM PDT 24
Peak memory 197424 kb
Host smart-69efc729-e3f2-45f6-9b5c-cf0ffc1e03c2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199912419 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_t
l_intg_err.2199912419
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.2483781868
Short name T340
Test name
Test status
Simulation time 499087946 ps
CPU time 1.05 seconds
Started Mar 26 01:49:42 PM PDT 24
Finished Mar 26 01:49:43 PM PDT 24
Peak memory 198220 kb
Host smart-159ff47f-30f8-447e-91e7-eb21a2b8b8c4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483781868 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.2483781868
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.2278529190
Short name T69
Test name
Test status
Simulation time 479199942 ps
CPU time 0.92 seconds
Started Mar 26 01:49:42 PM PDT 24
Finished Mar 26 01:49:43 PM PDT 24
Peak memory 193068 kb
Host smart-99dc17a8-d27a-4c39-ac83-7e2138fcf056
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278529190 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.2278529190
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.2540423175
Short name T311
Test name
Test status
Simulation time 509235972 ps
CPU time 1.14 seconds
Started Mar 26 01:49:44 PM PDT 24
Finished Mar 26 01:49:45 PM PDT 24
Peak memory 183608 kb
Host smart-6c34d198-9e5a-4227-9180-8b32c46fe021
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540423175 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.2540423175
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.2849641089
Short name T83
Test name
Test status
Simulation time 1433428218 ps
CPU time 1.26 seconds
Started Mar 26 01:49:44 PM PDT 24
Finished Mar 26 01:49:45 PM PDT 24
Peak memory 183844 kb
Host smart-242bd0be-ec0c-4035-b1c5-8ad6691e9a21
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849641089 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.ao
n_timer_same_csr_outstanding.2849641089
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.686861844
Short name T418
Test name
Test status
Simulation time 361791480 ps
CPU time 1.37 seconds
Started Mar 26 01:49:42 PM PDT 24
Finished Mar 26 01:49:44 PM PDT 24
Peak memory 196840 kb
Host smart-e77a51e0-30d8-4d19-825a-297737d0f1a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686861844 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.686861844
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.1207897904
Short name T372
Test name
Test status
Simulation time 8698615518 ps
CPU time 4.95 seconds
Started Mar 26 01:49:41 PM PDT 24
Finished Mar 26 01:49:46 PM PDT 24
Peak memory 197936 kb
Host smart-1011786d-0b8a-4bb2-aeec-8aae42e801ad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207897904 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_t
l_intg_err.1207897904
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.1114310216
Short name T316
Test name
Test status
Simulation time 570056908 ps
CPU time 1.08 seconds
Started Mar 26 01:49:52 PM PDT 24
Finished Mar 26 01:49:54 PM PDT 24
Peak memory 196988 kb
Host smart-a5aa6d60-635e-4c48-8918-3dfb1dc7e548
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114310216 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.1114310216
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.771072387
Short name T345
Test name
Test status
Simulation time 362436625 ps
CPU time 0.82 seconds
Started Mar 26 01:49:52 PM PDT 24
Finished Mar 26 01:49:53 PM PDT 24
Peak memory 183748 kb
Host smart-7bfdf09d-48ed-4b03-a77c-19d4fa510495
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771072387 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.771072387
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.318367618
Short name T336
Test name
Test status
Simulation time 335615332 ps
CPU time 0.58 seconds
Started Mar 26 01:49:52 PM PDT 24
Finished Mar 26 01:49:53 PM PDT 24
Peak memory 183684 kb
Host smart-2a2ac58c-50e3-48cb-969a-843d2a2cae53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318367618 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.318367618
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.1497099255
Short name T334
Test name
Test status
Simulation time 1116071889 ps
CPU time 0.92 seconds
Started Mar 26 01:49:51 PM PDT 24
Finished Mar 26 01:49:53 PM PDT 24
Peak memory 183772 kb
Host smart-723fb01d-2f3b-49c6-a198-3eff5b31c969
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497099255 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.ao
n_timer_same_csr_outstanding.1497099255
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.4188235571
Short name T338
Test name
Test status
Simulation time 372112292 ps
CPU time 2.66 seconds
Started Mar 26 01:49:41 PM PDT 24
Finished Mar 26 01:49:43 PM PDT 24
Peak memory 198656 kb
Host smart-9a1241d3-72b3-41e5-8f0e-a22edd329d26
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188235571 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.4188235571
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.1392250177
Short name T339
Test name
Test status
Simulation time 7922532332 ps
CPU time 11.57 seconds
Started Mar 26 01:49:45 PM PDT 24
Finished Mar 26 01:49:56 PM PDT 24
Peak memory 197952 kb
Host smart-f48c7c9f-b610-49cc-978c-a3e83e2b65a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392250177 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_t
l_intg_err.1392250177
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.377210686
Short name T367
Test name
Test status
Simulation time 384215337 ps
CPU time 0.93 seconds
Started Mar 26 01:49:52 PM PDT 24
Finished Mar 26 01:49:53 PM PDT 24
Peak memory 196168 kb
Host smart-c6b64b8c-7a69-46d6-8bda-cd7d622625e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377210686 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.377210686
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.1850239213
Short name T78
Test name
Test status
Simulation time 495735033 ps
CPU time 0.8 seconds
Started Mar 26 01:49:52 PM PDT 24
Finished Mar 26 01:49:53 PM PDT 24
Peak memory 183824 kb
Host smart-db4b54d0-88a4-41a1-a523-6c48f590d959
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850239213 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.1850239213
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.1153615996
Short name T411
Test name
Test status
Simulation time 345794173 ps
CPU time 1.07 seconds
Started Mar 26 01:49:51 PM PDT 24
Finished Mar 26 01:49:52 PM PDT 24
Peak memory 183972 kb
Host smart-29f98dd0-5e3a-4dcc-86fa-7165c970b8cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153615996 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.1153615996
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.1839738129
Short name T348
Test name
Test status
Simulation time 2527789579 ps
CPU time 6.19 seconds
Started Mar 26 01:49:54 PM PDT 24
Finished Mar 26 01:50:01 PM PDT 24
Peak memory 194540 kb
Host smart-7e89c91c-b9cf-4973-89d6-5c5fc86b3017
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839738129 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.ao
n_timer_same_csr_outstanding.1839738129
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.2622284120
Short name T319
Test name
Test status
Simulation time 535566380 ps
CPU time 2.09 seconds
Started Mar 26 01:49:51 PM PDT 24
Finished Mar 26 01:49:54 PM PDT 24
Peak memory 198580 kb
Host smart-f0ddabc1-c284-4ac4-bc9e-7a10f32e0afd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622284120 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.2622284120
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.385723430
Short name T371
Test name
Test status
Simulation time 8554998078 ps
CPU time 13.65 seconds
Started Mar 26 01:49:52 PM PDT 24
Finished Mar 26 01:50:06 PM PDT 24
Peak memory 197980 kb
Host smart-db1cea80-5be3-4e90-bd1e-12a233f68a17
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385723430 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl
_intg_err.385723430
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.411629275
Short name T305
Test name
Test status
Simulation time 502146759 ps
CPU time 1.4 seconds
Started Mar 26 01:49:52 PM PDT 24
Finished Mar 26 01:49:54 PM PDT 24
Peak memory 197008 kb
Host smart-30d1fdf6-ba79-49e6-9949-4566b147b61b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411629275 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.411629275
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.477278166
Short name T76
Test name
Test status
Simulation time 474999740 ps
CPU time 1.17 seconds
Started Mar 26 01:49:54 PM PDT 24
Finished Mar 26 01:49:56 PM PDT 24
Peak memory 183820 kb
Host smart-7e5d28d3-fc6b-4d8b-afff-f0e8408c4554
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477278166 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.477278166
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.2187204306
Short name T416
Test name
Test status
Simulation time 270035053 ps
CPU time 0.95 seconds
Started Mar 26 01:49:54 PM PDT 24
Finished Mar 26 01:49:56 PM PDT 24
Peak memory 183740 kb
Host smart-64d6cb3d-b3be-4d57-813a-6ef0f72df604
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187204306 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.2187204306
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.625967294
Short name T388
Test name
Test status
Simulation time 1194796969 ps
CPU time 1.47 seconds
Started Mar 26 01:49:52 PM PDT 24
Finished Mar 26 01:49:54 PM PDT 24
Peak memory 183688 kb
Host smart-49f9b9b7-45d9-47a8-9827-90acdea3e885
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625967294 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon
_timer_same_csr_outstanding.625967294
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.4206127420
Short name T393
Test name
Test status
Simulation time 630099248 ps
CPU time 1.55 seconds
Started Mar 26 01:49:52 PM PDT 24
Finished Mar 26 01:49:54 PM PDT 24
Peak memory 198612 kb
Host smart-f7924134-ec30-4328-b6b0-4b9f8a8128c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206127420 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.4206127420
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.897879254
Short name T350
Test name
Test status
Simulation time 8208166067 ps
CPU time 4.49 seconds
Started Mar 26 01:49:54 PM PDT 24
Finished Mar 26 01:49:59 PM PDT 24
Peak memory 198084 kb
Host smart-8e83fcb5-6cf6-4eaa-baab-d2e6525c80b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897879254 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl
_intg_err.897879254
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.334645591
Short name T304
Test name
Test status
Simulation time 553088505 ps
CPU time 1.17 seconds
Started Mar 26 01:49:59 PM PDT 24
Finished Mar 26 01:50:01 PM PDT 24
Peak memory 195704 kb
Host smart-317aeb4d-4f7e-4488-9800-cf0f1d9fb9a9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334645591 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.334645591
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.992432125
Short name T325
Test name
Test status
Simulation time 335854461 ps
CPU time 0.97 seconds
Started Mar 26 01:49:52 PM PDT 24
Finished Mar 26 01:49:53 PM PDT 24
Peak memory 183932 kb
Host smart-3fb0627d-0ab7-43d3-80db-678e59319cce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992432125 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.992432125
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.1788653716
Short name T368
Test name
Test status
Simulation time 316037983 ps
CPU time 1.04 seconds
Started Mar 26 01:49:51 PM PDT 24
Finished Mar 26 01:49:53 PM PDT 24
Peak memory 183712 kb
Host smart-efef0177-1c0a-4dc7-8b8d-359da404bba1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788653716 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.1788653716
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.554397144
Short name T413
Test name
Test status
Simulation time 2315043861 ps
CPU time 3.29 seconds
Started Mar 26 01:49:51 PM PDT 24
Finished Mar 26 01:49:55 PM PDT 24
Peak memory 183884 kb
Host smart-6934d74f-4387-4018-bc05-caa1bd388b9e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554397144 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon
_timer_same_csr_outstanding.554397144
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.3636233181
Short name T396
Test name
Test status
Simulation time 574113493 ps
CPU time 1.81 seconds
Started Mar 26 01:49:50 PM PDT 24
Finished Mar 26 01:49:52 PM PDT 24
Peak memory 198572 kb
Host smart-53deead6-d3d3-4763-bc30-e8825812b743
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636233181 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.3636233181
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.3186644204
Short name T406
Test name
Test status
Simulation time 4130393471 ps
CPU time 3.6 seconds
Started Mar 26 01:49:49 PM PDT 24
Finished Mar 26 01:49:54 PM PDT 24
Peak memory 197640 kb
Host smart-c74fffad-2e8f-40ab-aab8-672e248163bd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186644204 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_t
l_intg_err.3186644204
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.2142634916
Short name T363
Test name
Test status
Simulation time 593323919 ps
CPU time 0.86 seconds
Started Mar 26 01:49:59 PM PDT 24
Finished Mar 26 01:50:01 PM PDT 24
Peak memory 196044 kb
Host smart-0fb57792-5d37-4f31-b165-6eff7a12d306
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142634916 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.2142634916
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.67966345
Short name T414
Test name
Test status
Simulation time 323801916 ps
CPU time 1.13 seconds
Started Mar 26 01:50:02 PM PDT 24
Finished Mar 26 01:50:03 PM PDT 24
Peak memory 183736 kb
Host smart-905c4979-e8a0-41cc-b5f6-4d9b18bfce83
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67966345 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.67966345
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.425497097
Short name T314
Test name
Test status
Simulation time 385312551 ps
CPU time 1.05 seconds
Started Mar 26 01:50:01 PM PDT 24
Finished Mar 26 01:50:02 PM PDT 24
Peak memory 183528 kb
Host smart-2edd4fe1-d074-42c0-a897-1eec42c45355
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425497097 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.425497097
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.2119371421
Short name T355
Test name
Test status
Simulation time 1048928614 ps
CPU time 0.95 seconds
Started Mar 26 01:50:02 PM PDT 24
Finished Mar 26 01:50:03 PM PDT 24
Peak memory 183680 kb
Host smart-1ce651c0-84b9-49ec-8862-658b7130f69c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119371421 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.ao
n_timer_same_csr_outstanding.2119371421
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.4246929217
Short name T327
Test name
Test status
Simulation time 520628240 ps
CPU time 1.83 seconds
Started Mar 26 01:50:01 PM PDT 24
Finished Mar 26 01:50:03 PM PDT 24
Peak memory 198516 kb
Host smart-e581bb47-e3b7-4f59-a744-d4e5fafe38e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246929217 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.4246929217
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.2205934941
Short name T34
Test name
Test status
Simulation time 4639450553 ps
CPU time 7.41 seconds
Started Mar 26 01:50:03 PM PDT 24
Finished Mar 26 01:50:10 PM PDT 24
Peak memory 197204 kb
Host smart-0d06527e-f1c5-4f58-b0fe-96f598df2322
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205934941 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_t
l_intg_err.2205934941
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.2364499302
Short name T299
Test name
Test status
Simulation time 342060847 ps
CPU time 1.17 seconds
Started Mar 26 01:50:01 PM PDT 24
Finished Mar 26 01:50:02 PM PDT 24
Peak memory 195928 kb
Host smart-68bf0814-1e1f-4235-96d7-ecff186e30d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364499302 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.2364499302
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.87361945
Short name T342
Test name
Test status
Simulation time 311063793 ps
CPU time 1.01 seconds
Started Mar 26 01:50:01 PM PDT 24
Finished Mar 26 01:50:02 PM PDT 24
Peak memory 183688 kb
Host smart-418edc8e-1171-4f8e-9837-14a58f6d982e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87361945 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.87361945
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.1921936358
Short name T351
Test name
Test status
Simulation time 308694673 ps
CPU time 0.95 seconds
Started Mar 26 01:50:01 PM PDT 24
Finished Mar 26 01:50:02 PM PDT 24
Peak memory 183636 kb
Host smart-ec97ce8c-4140-40d3-b2fb-a9bc120e1a8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921936358 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.1921936358
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.3568837043
Short name T349
Test name
Test status
Simulation time 3086337900 ps
CPU time 1.77 seconds
Started Mar 26 01:50:01 PM PDT 24
Finished Mar 26 01:50:03 PM PDT 24
Peak memory 194888 kb
Host smart-eab649c8-79c9-4c43-a898-285fc1c01b06
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568837043 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.ao
n_timer_same_csr_outstanding.3568837043
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.3058441814
Short name T302
Test name
Test status
Simulation time 800868707 ps
CPU time 2.46 seconds
Started Mar 26 01:50:01 PM PDT 24
Finished Mar 26 01:50:04 PM PDT 24
Peak memory 198536 kb
Host smart-983344e0-ddd3-419e-a2b1-c5d1cf2e428d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058441814 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.3058441814
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.4185938798
Short name T361
Test name
Test status
Simulation time 545412565 ps
CPU time 0.85 seconds
Started Mar 26 01:50:11 PM PDT 24
Finished Mar 26 01:50:12 PM PDT 24
Peak memory 195928 kb
Host smart-549de9a3-f936-4e71-9a1d-100c1df09c38
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185938798 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.4185938798
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.3933712915
Short name T410
Test name
Test status
Simulation time 374248395 ps
CPU time 0.67 seconds
Started Mar 26 01:49:59 PM PDT 24
Finished Mar 26 01:50:01 PM PDT 24
Peak memory 193104 kb
Host smart-76af1ff7-3ee0-4bb3-930a-c8085e967374
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933712915 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.3933712915
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.695523225
Short name T306
Test name
Test status
Simulation time 459445192 ps
CPU time 0.98 seconds
Started Mar 26 01:49:58 PM PDT 24
Finished Mar 26 01:50:00 PM PDT 24
Peak memory 183708 kb
Host smart-d59a283c-e5ea-4f36-ac95-40c94720c835
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695523225 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.695523225
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.3925136885
Short name T365
Test name
Test status
Simulation time 1511882981 ps
CPU time 2.61 seconds
Started Mar 26 01:50:02 PM PDT 24
Finished Mar 26 01:50:05 PM PDT 24
Peak memory 193124 kb
Host smart-bcc88aee-d8f7-49b4-8e65-23bd4e822f35
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925136885 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.ao
n_timer_same_csr_outstanding.3925136885
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.434032940
Short name T379
Test name
Test status
Simulation time 485977733 ps
CPU time 1.31 seconds
Started Mar 26 01:50:01 PM PDT 24
Finished Mar 26 01:50:02 PM PDT 24
Peak memory 198584 kb
Host smart-ce45cb47-3076-4e10-a40b-5cedc42660e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434032940 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.434032940
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.2553008302
Short name T103
Test name
Test status
Simulation time 4500015950 ps
CPU time 2.88 seconds
Started Mar 26 01:50:00 PM PDT 24
Finished Mar 26 01:50:04 PM PDT 24
Peak memory 197600 kb
Host smart-649dd465-de22-4171-9cd8-9a809f7089e3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553008302 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_t
l_intg_err.2553008302
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.2010385922
Short name T400
Test name
Test status
Simulation time 373443621 ps
CPU time 0.88 seconds
Started Mar 26 01:50:06 PM PDT 24
Finished Mar 26 01:50:07 PM PDT 24
Peak memory 195472 kb
Host smart-b7955170-9fae-455f-ac66-38b3cf173263
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010385922 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.2010385922
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.3502682605
Short name T402
Test name
Test status
Simulation time 381912059 ps
CPU time 0.62 seconds
Started Mar 26 01:50:07 PM PDT 24
Finished Mar 26 01:50:08 PM PDT 24
Peak memory 193108 kb
Host smart-fa892682-fbd6-4814-aa76-86675ae39140
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502682605 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.3502682605
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.2900642539
Short name T287
Test name
Test status
Simulation time 394163716 ps
CPU time 0.86 seconds
Started Mar 26 01:50:07 PM PDT 24
Finished Mar 26 01:50:08 PM PDT 24
Peak memory 183684 kb
Host smart-cf063118-a6b9-4e9e-b341-a1dccab144ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900642539 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.2900642539
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.2380753575
Short name T374
Test name
Test status
Simulation time 1153277263 ps
CPU time 2.45 seconds
Started Mar 26 01:50:10 PM PDT 24
Finished Mar 26 01:50:13 PM PDT 24
Peak memory 193444 kb
Host smart-66e0855f-92cc-4013-9372-b72430dc5feb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380753575 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao
n_timer_same_csr_outstanding.2380753575
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.3823266519
Short name T310
Test name
Test status
Simulation time 1168627334 ps
CPU time 2.72 seconds
Started Mar 26 01:50:05 PM PDT 24
Finished Mar 26 01:50:08 PM PDT 24
Peak memory 198628 kb
Host smart-4dc14d91-fe27-49cb-99dc-045871daaecf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823266519 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.3823266519
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.427895513
Short name T321
Test name
Test status
Simulation time 4121022216 ps
CPU time 2.59 seconds
Started Mar 26 01:50:11 PM PDT 24
Finished Mar 26 01:50:13 PM PDT 24
Peak memory 197296 kb
Host smart-0ed617ac-16f9-4d2a-b257-de6ce20c10ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427895513 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl
_intg_err.427895513
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.3823885505
Short name T298
Test name
Test status
Simulation time 693844139 ps
CPU time 0.76 seconds
Started Mar 26 01:49:07 PM PDT 24
Finished Mar 26 01:49:07 PM PDT 24
Peak memory 183716 kb
Host smart-e6872976-0b51-4750-b188-5d6f309c8a5a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823885505 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_a
liasing.3823885505
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.1977332270
Short name T381
Test name
Test status
Simulation time 7316696253 ps
CPU time 15.67 seconds
Started Mar 26 01:49:04 PM PDT 24
Finished Mar 26 01:49:20 PM PDT 24
Peak memory 192264 kb
Host smart-3f3587ae-efbb-44dd-a6f3-078709bd09dd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977332270 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_b
it_bash.1977332270
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.2062437232
Short name T286
Test name
Test status
Simulation time 1134543097 ps
CPU time 0.9 seconds
Started Mar 26 01:49:06 PM PDT 24
Finished Mar 26 01:49:07 PM PDT 24
Peak memory 183776 kb
Host smart-76644a42-62fe-41ae-9af8-a59a0a3b1ed7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062437232 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_h
w_reset.2062437232
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.2397314158
Short name T106
Test name
Test status
Simulation time 526831871 ps
CPU time 1.54 seconds
Started Mar 26 01:49:06 PM PDT 24
Finished Mar 26 01:49:07 PM PDT 24
Peak memory 196328 kb
Host smart-1f0bc8b7-0192-4cfc-8ebd-4b0ff0d560fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397314158 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.2397314158
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.14635400
Short name T353
Test name
Test status
Simulation time 349126612 ps
CPU time 0.81 seconds
Started Mar 26 01:49:03 PM PDT 24
Finished Mar 26 01:49:04 PM PDT 24
Peak memory 183940 kb
Host smart-3abe568f-9efa-46c2-9acb-01a330d48be1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14635400 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.14635400
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.2838252235
Short name T360
Test name
Test status
Simulation time 447789780 ps
CPU time 0.72 seconds
Started Mar 26 01:49:04 PM PDT 24
Finished Mar 26 01:49:04 PM PDT 24
Peak memory 183632 kb
Host smart-a38865b6-3d08-4e04-9744-7b86ecf96539
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838252235 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.2838252235
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.933030926
Short name T292
Test name
Test status
Simulation time 523524561 ps
CPU time 0.58 seconds
Started Mar 26 01:49:04 PM PDT 24
Finished Mar 26 01:49:05 PM PDT 24
Peak memory 183592 kb
Host smart-e5c1a704-6fb6-4709-903e-ca8c2dd08041
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933030926 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_ti
mer_mem_partial_access.933030926
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.1985808676
Short name T354
Test name
Test status
Simulation time 345120849 ps
CPU time 0.63 seconds
Started Mar 26 01:49:03 PM PDT 24
Finished Mar 26 01:49:04 PM PDT 24
Peak memory 183668 kb
Host smart-8a5f9652-712d-4481-b43e-a291cddb1529
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985808676 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_w
alk.1985808676
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.3348085391
Short name T81
Test name
Test status
Simulation time 1375182451 ps
CPU time 1.19 seconds
Started Mar 26 01:49:04 PM PDT 24
Finished Mar 26 01:49:05 PM PDT 24
Peak memory 193304 kb
Host smart-276d9bd9-e937-4fc5-9b51-41c84d8f36c1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348085391 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon
_timer_same_csr_outstanding.3348085391
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.2187330364
Short name T296
Test name
Test status
Simulation time 560334279 ps
CPU time 2.14 seconds
Started Mar 26 01:49:03 PM PDT 24
Finished Mar 26 01:49:06 PM PDT 24
Peak memory 198524 kb
Host smart-7b311f15-150e-45a3-9e82-0bb5a2ab5378
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187330364 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.2187330364
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.2538723031
Short name T333
Test name
Test status
Simulation time 8577067232 ps
CPU time 14.61 seconds
Started Mar 26 01:49:04 PM PDT 24
Finished Mar 26 01:49:19 PM PDT 24
Peak memory 197904 kb
Host smart-164c78b9-4442-4aec-b2f6-0e2670a88481
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538723031 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl
_intg_err.2538723031
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.3806385534
Short name T420
Test name
Test status
Simulation time 440816024 ps
CPU time 0.68 seconds
Started Mar 26 01:50:06 PM PDT 24
Finished Mar 26 01:50:07 PM PDT 24
Peak memory 183652 kb
Host smart-baa36e7d-a823-4d91-af18-d8b7fd2970de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806385534 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.3806385534
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.1691552054
Short name T369
Test name
Test status
Simulation time 376901526 ps
CPU time 0.62 seconds
Started Mar 26 01:50:11 PM PDT 24
Finished Mar 26 01:50:12 PM PDT 24
Peak memory 183652 kb
Host smart-d8948c3c-6e4e-48cb-ab92-55417a9a96d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691552054 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.1691552054
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.4078861313
Short name T322
Test name
Test status
Simulation time 358165213 ps
CPU time 0.78 seconds
Started Mar 26 01:50:07 PM PDT 24
Finished Mar 26 01:50:07 PM PDT 24
Peak memory 183708 kb
Host smart-ef986772-5aad-4663-93eb-62596b776ec6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078861313 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.4078861313
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.1475483251
Short name T412
Test name
Test status
Simulation time 440776673 ps
CPU time 1.14 seconds
Started Mar 26 01:50:06 PM PDT 24
Finished Mar 26 01:50:07 PM PDT 24
Peak memory 183628 kb
Host smart-c665c9df-19fc-4787-afbd-403a592e8a87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475483251 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.1475483251
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.2231170953
Short name T290
Test name
Test status
Simulation time 477263714 ps
CPU time 0.71 seconds
Started Mar 26 01:50:13 PM PDT 24
Finished Mar 26 01:50:14 PM PDT 24
Peak memory 183680 kb
Host smart-34ed148d-39ee-4166-b0bc-9e37c4071683
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231170953 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.2231170953
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.4122611954
Short name T300
Test name
Test status
Simulation time 433727198 ps
CPU time 1.16 seconds
Started Mar 26 01:50:18 PM PDT 24
Finished Mar 26 01:50:19 PM PDT 24
Peak memory 183664 kb
Host smart-7307a420-8083-44e9-850a-b8bc5b4f5854
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122611954 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.4122611954
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.281296844
Short name T344
Test name
Test status
Simulation time 310638922 ps
CPU time 0.58 seconds
Started Mar 26 01:50:14 PM PDT 24
Finished Mar 26 01:50:15 PM PDT 24
Peak memory 183668 kb
Host smart-88f319c3-0f33-44b2-9184-593fe42aeda8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281296844 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.281296844
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.1891143220
Short name T293
Test name
Test status
Simulation time 309629519 ps
CPU time 0.97 seconds
Started Mar 26 01:50:14 PM PDT 24
Finished Mar 26 01:50:15 PM PDT 24
Peak memory 183696 kb
Host smart-04f791b5-27ab-4d0d-90d2-25e6a2bdd8c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891143220 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.1891143220
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.2268147128
Short name T326
Test name
Test status
Simulation time 396420440 ps
CPU time 0.68 seconds
Started Mar 26 01:50:17 PM PDT 24
Finished Mar 26 01:50:17 PM PDT 24
Peak memory 183656 kb
Host smart-b7fd8016-862a-4357-a26d-7ffeafa802a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268147128 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.2268147128
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.4245852973
Short name T409
Test name
Test status
Simulation time 497991393 ps
CPU time 0.63 seconds
Started Mar 26 01:50:14 PM PDT 24
Finished Mar 26 01:50:15 PM PDT 24
Peak memory 183676 kb
Host smart-c52ba00b-0eeb-4f80-b0b9-9297fc04ea1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245852973 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.4245852973
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.4216939316
Short name T67
Test name
Test status
Simulation time 509807123 ps
CPU time 1.47 seconds
Started Mar 26 01:49:13 PM PDT 24
Finished Mar 26 01:49:15 PM PDT 24
Peak memory 194216 kb
Host smart-3260472d-449a-47e3-9e3c-2e620e16d0ee
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216939316 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_a
liasing.4216939316
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.2152335810
Short name T68
Test name
Test status
Simulation time 8540476355 ps
CPU time 3.38 seconds
Started Mar 26 01:49:14 PM PDT 24
Finished Mar 26 01:49:18 PM PDT 24
Peak memory 195748 kb
Host smart-16c4e8f9-bd65-4f19-8b1f-eb42e62ff198
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152335810 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_b
it_bash.2152335810
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.2713965386
Short name T382
Test name
Test status
Simulation time 819751715 ps
CPU time 1.2 seconds
Started Mar 26 01:49:15 PM PDT 24
Finished Mar 26 01:49:16 PM PDT 24
Peak memory 183776 kb
Host smart-ba7cec8b-b5fe-4c1f-a4c6-9555f3f8eed4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713965386 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_h
w_reset.2713965386
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.1010469717
Short name T377
Test name
Test status
Simulation time 477002851 ps
CPU time 0.83 seconds
Started Mar 26 01:49:15 PM PDT 24
Finished Mar 26 01:49:16 PM PDT 24
Peak memory 194800 kb
Host smart-b0ccb1f0-12d4-4932-9227-4d0712549bc8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010469717 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.1010469717
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.2740788132
Short name T72
Test name
Test status
Simulation time 576020155 ps
CPU time 0.62 seconds
Started Mar 26 01:49:13 PM PDT 24
Finished Mar 26 01:49:14 PM PDT 24
Peak memory 193172 kb
Host smart-aad675e7-2a4f-4f50-ae11-f83995c5ba7f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740788132 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.2740788132
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.49583972
Short name T422
Test name
Test status
Simulation time 589842712 ps
CPU time 0.59 seconds
Started Mar 26 01:49:14 PM PDT 24
Finished Mar 26 01:49:15 PM PDT 24
Peak memory 183648 kb
Host smart-8db1b6cd-57f8-4a2a-8d8d-251817f73927
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49583972 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.49583972
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.185511927
Short name T318
Test name
Test status
Simulation time 484926340 ps
CPU time 1.28 seconds
Started Mar 26 01:49:12 PM PDT 24
Finished Mar 26 01:49:13 PM PDT 24
Peak memory 183604 kb
Host smart-b35bbf86-884d-4734-93cd-3e758d9ecb6c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185511927 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_ti
mer_mem_partial_access.185511927
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.2473177054
Short name T284
Test name
Test status
Simulation time 504776731 ps
CPU time 0.9 seconds
Started Mar 26 01:49:14 PM PDT 24
Finished Mar 26 01:49:16 PM PDT 24
Peak memory 183672 kb
Host smart-334ad539-29e7-407f-9e9e-34b6a58ab8ab
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473177054 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_w
alk.2473177054
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.284019434
Short name T80
Test name
Test status
Simulation time 1365714053 ps
CPU time 1.15 seconds
Started Mar 26 01:49:15 PM PDT 24
Finished Mar 26 01:49:17 PM PDT 24
Peak memory 193328 kb
Host smart-c8481da3-8af7-42f2-809d-ff7a777e64c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284019434 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_
timer_same_csr_outstanding.284019434
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.1308419403
Short name T384
Test name
Test status
Simulation time 418426966 ps
CPU time 1.08 seconds
Started Mar 26 01:49:14 PM PDT 24
Finished Mar 26 01:49:15 PM PDT 24
Peak memory 197912 kb
Host smart-d870f0e7-eda8-4918-a276-715985062463
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308419403 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.1308419403
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.542732548
Short name T105
Test name
Test status
Simulation time 4341258232 ps
CPU time 8.17 seconds
Started Mar 26 01:49:13 PM PDT 24
Finished Mar 26 01:49:21 PM PDT 24
Peak memory 197708 kb
Host smart-73a509b7-112c-41ec-a9e8-e3cf39d0eef7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542732548 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_
intg_err.542732548
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.3700940173
Short name T423
Test name
Test status
Simulation time 466254091 ps
CPU time 0.7 seconds
Started Mar 26 01:50:13 PM PDT 24
Finished Mar 26 01:50:14 PM PDT 24
Peak memory 183680 kb
Host smart-7aec464c-3ab0-4f00-89cb-da18c743dcb7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700940173 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.3700940173
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.3011157339
Short name T317
Test name
Test status
Simulation time 415618859 ps
CPU time 1.12 seconds
Started Mar 26 01:50:12 PM PDT 24
Finished Mar 26 01:50:13 PM PDT 24
Peak memory 183684 kb
Host smart-e0d3ab96-2fad-43e1-86d2-59bd0d99fc4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011157339 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.3011157339
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.2712159957
Short name T288
Test name
Test status
Simulation time 397296101 ps
CPU time 0.61 seconds
Started Mar 26 01:50:13 PM PDT 24
Finished Mar 26 01:50:14 PM PDT 24
Peak memory 183664 kb
Host smart-e42ca4e8-661a-46d2-a64e-bcc6b52a012e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712159957 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.2712159957
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.3750209746
Short name T392
Test name
Test status
Simulation time 497969675 ps
CPU time 1.3 seconds
Started Mar 26 01:50:17 PM PDT 24
Finished Mar 26 01:50:18 PM PDT 24
Peak memory 183644 kb
Host smart-23eb6b94-29a1-4ef0-a565-bb1cc73691f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750209746 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.3750209746
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.1756455720
Short name T313
Test name
Test status
Simulation time 444445134 ps
CPU time 0.73 seconds
Started Mar 26 01:50:13 PM PDT 24
Finished Mar 26 01:50:14 PM PDT 24
Peak memory 183652 kb
Host smart-668b9cd2-7b49-490b-97b2-a4d32a69c883
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756455720 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.1756455720
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.2309437312
Short name T343
Test name
Test status
Simulation time 447640366 ps
CPU time 1.23 seconds
Started Mar 26 01:50:15 PM PDT 24
Finished Mar 26 01:50:16 PM PDT 24
Peak memory 183660 kb
Host smart-6f6148d8-63dd-4562-a938-ec0005d8049b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309437312 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.2309437312
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.56778627
Short name T294
Test name
Test status
Simulation time 340539020 ps
CPU time 0.61 seconds
Started Mar 26 01:50:13 PM PDT 24
Finished Mar 26 01:50:14 PM PDT 24
Peak memory 183624 kb
Host smart-d737dc8c-05a3-4fc4-bb13-7247695a8175
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56778627 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.56778627
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.2066085485
Short name T315
Test name
Test status
Simulation time 390274417 ps
CPU time 0.57 seconds
Started Mar 26 01:50:18 PM PDT 24
Finished Mar 26 01:50:18 PM PDT 24
Peak memory 183660 kb
Host smart-b851913c-af6f-444f-90d9-6628dac52bb0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066085485 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.2066085485
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.1036513413
Short name T295
Test name
Test status
Simulation time 344675193 ps
CPU time 0.78 seconds
Started Mar 26 01:50:17 PM PDT 24
Finished Mar 26 01:50:17 PM PDT 24
Peak memory 183644 kb
Host smart-026cea22-6657-4600-92b7-1da1a28cdede
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036513413 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.1036513413
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.2313300596
Short name T297
Test name
Test status
Simulation time 384589563 ps
CPU time 0.83 seconds
Started Mar 26 01:50:13 PM PDT 24
Finished Mar 26 01:50:15 PM PDT 24
Peak memory 183712 kb
Host smart-e833b5ca-8167-48c5-a436-a8d892497ae1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313300596 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.2313300596
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.2830353214
Short name T335
Test name
Test status
Simulation time 429851457 ps
CPU time 0.78 seconds
Started Mar 26 01:49:26 PM PDT 24
Finished Mar 26 01:49:27 PM PDT 24
Peak memory 183896 kb
Host smart-9e222d19-1559-4fc8-aff9-08699f2adc9e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830353214 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_a
liasing.2830353214
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.3850752683
Short name T74
Test name
Test status
Simulation time 764213718 ps
CPU time 2.62 seconds
Started Mar 26 01:49:31 PM PDT 24
Finished Mar 26 01:49:34 PM PDT 24
Peak memory 184028 kb
Host smart-04f5a873-a674-4918-9ba7-1332f2ba5b91
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850752683 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_b
it_bash.3850752683
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.3079485562
Short name T415
Test name
Test status
Simulation time 1331709688 ps
CPU time 0.91 seconds
Started Mar 26 01:49:26 PM PDT 24
Finished Mar 26 01:49:27 PM PDT 24
Peak memory 183756 kb
Host smart-6ea027df-f3aa-45bd-b4bf-b13afd4017e7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079485562 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_h
w_reset.3079485562
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.1875335440
Short name T383
Test name
Test status
Simulation time 440956257 ps
CPU time 1.29 seconds
Started Mar 26 01:49:25 PM PDT 24
Finished Mar 26 01:49:26 PM PDT 24
Peak memory 195700 kb
Host smart-10f302e0-fda5-4553-962f-8761863fb1ec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875335440 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.1875335440
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.1790807133
Short name T64
Test name
Test status
Simulation time 457101620 ps
CPU time 0.76 seconds
Started Mar 26 01:49:27 PM PDT 24
Finished Mar 26 01:49:28 PM PDT 24
Peak memory 193156 kb
Host smart-85a7ab18-0d4e-4512-b1fb-f62f2c60f14b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790807133 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.1790807133
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.602697071
Short name T390
Test name
Test status
Simulation time 518588563 ps
CPU time 0.68 seconds
Started Mar 26 01:49:11 PM PDT 24
Finished Mar 26 01:49:12 PM PDT 24
Peak memory 183660 kb
Host smart-678dd6a7-1eaf-4162-87b1-b919e9a8eeff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602697071 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.602697071
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.1625199154
Short name T307
Test name
Test status
Simulation time 439369730 ps
CPU time 0.62 seconds
Started Mar 26 01:49:13 PM PDT 24
Finished Mar 26 01:49:14 PM PDT 24
Peak memory 183476 kb
Host smart-42c92102-bca3-44df-bb1c-283f655be141
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625199154 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_t
imer_mem_partial_access.1625199154
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.809046562
Short name T308
Test name
Test status
Simulation time 518295485 ps
CPU time 0.93 seconds
Started Mar 26 01:49:13 PM PDT 24
Finished Mar 26 01:49:14 PM PDT 24
Peak memory 183560 kb
Host smart-7ac0aa72-9ca4-46fe-b7c1-fec961c53121
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809046562 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_wa
lk.809046562
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.3794606861
Short name T403
Test name
Test status
Simulation time 1430976893 ps
CPU time 1.48 seconds
Started Mar 26 01:49:25 PM PDT 24
Finished Mar 26 01:49:27 PM PDT 24
Peak memory 193428 kb
Host smart-70344709-b862-46a0-8336-27c7ccbb8807
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794606861 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon
_timer_same_csr_outstanding.3794606861
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.4219412291
Short name T395
Test name
Test status
Simulation time 390296739 ps
CPU time 1.09 seconds
Started Mar 26 01:49:14 PM PDT 24
Finished Mar 26 01:49:15 PM PDT 24
Peak memory 198320 kb
Host smart-5a24a3f8-27fb-4495-aea1-796f411f55d5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219412291 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.4219412291
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.3333568975
Short name T399
Test name
Test status
Simulation time 8004555043 ps
CPU time 4.22 seconds
Started Mar 26 01:49:11 PM PDT 24
Finished Mar 26 01:49:16 PM PDT 24
Peak memory 198048 kb
Host smart-2fb40d9b-2aa4-461e-a04c-3fe44bdb3066
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333568975 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl
_intg_err.3333568975
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.1327461669
Short name T376
Test name
Test status
Simulation time 297736484 ps
CPU time 0.66 seconds
Started Mar 26 01:50:15 PM PDT 24
Finished Mar 26 01:50:16 PM PDT 24
Peak memory 183708 kb
Host smart-4a837cd4-9d29-4d30-b56f-6a29d552c427
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327461669 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.1327461669
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.958584230
Short name T320
Test name
Test status
Simulation time 382201940 ps
CPU time 0.62 seconds
Started Mar 26 01:50:13 PM PDT 24
Finished Mar 26 01:50:14 PM PDT 24
Peak memory 183724 kb
Host smart-51a32e11-aa16-4738-b4a8-28e1a1872453
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958584230 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.958584230
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.2094606458
Short name T282
Test name
Test status
Simulation time 336481017 ps
CPU time 0.8 seconds
Started Mar 26 01:50:14 PM PDT 24
Finished Mar 26 01:50:15 PM PDT 24
Peak memory 183636 kb
Host smart-04d3ac94-370c-4aa9-b152-0818e7f26cc4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094606458 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.2094606458
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.1218211687
Short name T285
Test name
Test status
Simulation time 329806007 ps
CPU time 0.78 seconds
Started Mar 26 01:50:18 PM PDT 24
Finished Mar 26 01:50:19 PM PDT 24
Peak memory 183660 kb
Host smart-f5751128-92ff-4e66-b6e4-a18c068489a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218211687 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.1218211687
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.1232869865
Short name T386
Test name
Test status
Simulation time 310026150 ps
CPU time 1.04 seconds
Started Mar 26 01:50:14 PM PDT 24
Finished Mar 26 01:50:15 PM PDT 24
Peak memory 183636 kb
Host smart-e879df99-fa07-4e9a-b00c-39efdbb48a91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232869865 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.1232869865
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.3979970697
Short name T421
Test name
Test status
Simulation time 387396974 ps
CPU time 0.64 seconds
Started Mar 26 01:50:15 PM PDT 24
Finished Mar 26 01:50:16 PM PDT 24
Peak memory 183676 kb
Host smart-733581f3-92d0-47a6-930c-6089b9c229ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979970697 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.3979970697
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.991552897
Short name T366
Test name
Test status
Simulation time 474371020 ps
CPU time 0.72 seconds
Started Mar 26 01:50:23 PM PDT 24
Finished Mar 26 01:50:24 PM PDT 24
Peak memory 183616 kb
Host smart-5ae64cc5-c73b-4947-aadc-31e99096eaff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991552897 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.991552897
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.2392892247
Short name T362
Test name
Test status
Simulation time 289824710 ps
CPU time 0.92 seconds
Started Mar 26 01:50:23 PM PDT 24
Finished Mar 26 01:50:24 PM PDT 24
Peak memory 183668 kb
Host smart-26a986bd-f35b-44e1-b158-a66ac62e5d47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392892247 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.2392892247
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.2968194130
Short name T281
Test name
Test status
Simulation time 496978810 ps
CPU time 1.21 seconds
Started Mar 26 01:50:22 PM PDT 24
Finished Mar 26 01:50:23 PM PDT 24
Peak memory 183628 kb
Host smart-535e82c5-b080-40af-9e7d-1de1c11b2b03
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968194130 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.2968194130
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.2465341197
Short name T303
Test name
Test status
Simulation time 388624793 ps
CPU time 0.66 seconds
Started Mar 26 01:50:22 PM PDT 24
Finished Mar 26 01:50:23 PM PDT 24
Peak memory 183676 kb
Host smart-f5d3cc79-e9bd-49d8-9e05-e634ffc69977
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465341197 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.2465341197
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.1473981195
Short name T404
Test name
Test status
Simulation time 416176812 ps
CPU time 1.16 seconds
Started Mar 26 01:49:31 PM PDT 24
Finished Mar 26 01:49:32 PM PDT 24
Peak memory 195800 kb
Host smart-c5f73b1d-94ef-465d-b449-9a922199c571
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473981195 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.1473981195
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.1339231505
Short name T359
Test name
Test status
Simulation time 427266822 ps
CPU time 0.65 seconds
Started Mar 26 01:49:26 PM PDT 24
Finished Mar 26 01:49:26 PM PDT 24
Peak memory 193076 kb
Host smart-78fd30ca-ae0e-496e-8fd5-610500dd3c55
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339231505 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.1339231505
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.2556512337
Short name T332
Test name
Test status
Simulation time 504472564 ps
CPU time 1.23 seconds
Started Mar 26 01:49:25 PM PDT 24
Finished Mar 26 01:49:26 PM PDT 24
Peak memory 183644 kb
Host smart-784f752b-1d06-4c32-81ef-dd4981b3f6ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556512337 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.2556512337
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.2836752280
Short name T356
Test name
Test status
Simulation time 1235056715 ps
CPU time 1.51 seconds
Started Mar 26 01:49:24 PM PDT 24
Finished Mar 26 01:49:26 PM PDT 24
Peak memory 183824 kb
Host smart-3f16ef9a-5fd8-4365-946c-e8cd9eec8d9f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836752280 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon
_timer_same_csr_outstanding.2836752280
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.1462078168
Short name T330
Test name
Test status
Simulation time 397417914 ps
CPU time 1.02 seconds
Started Mar 26 01:49:31 PM PDT 24
Finished Mar 26 01:49:32 PM PDT 24
Peak memory 198172 kb
Host smart-3aa8d530-a653-4df3-b661-b3cda7407d41
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462078168 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.1462078168
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.308192334
Short name T373
Test name
Test status
Simulation time 399696520 ps
CPU time 0.96 seconds
Started Mar 26 01:49:32 PM PDT 24
Finished Mar 26 01:49:34 PM PDT 24
Peak memory 195228 kb
Host smart-4d3d760e-49eb-4b10-b246-4c62469a6b68
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308192334 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.308192334
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.1995445031
Short name T401
Test name
Test status
Simulation time 491007614 ps
CPU time 1.38 seconds
Started Mar 26 01:49:33 PM PDT 24
Finished Mar 26 01:49:34 PM PDT 24
Peak memory 183728 kb
Host smart-7700b291-8c66-46c0-8403-d7afc44a6fb4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995445031 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.1995445031
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.1408253960
Short name T309
Test name
Test status
Simulation time 501835751 ps
CPU time 1.29 seconds
Started Mar 26 01:49:34 PM PDT 24
Finished Mar 26 01:49:36 PM PDT 24
Peak memory 183644 kb
Host smart-7a896938-93df-474b-8927-88dce62e0865
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408253960 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.1408253960
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.3478350003
Short name T397
Test name
Test status
Simulation time 2532087889 ps
CPU time 7.39 seconds
Started Mar 26 01:49:34 PM PDT 24
Finished Mar 26 01:49:42 PM PDT 24
Peak memory 192092 kb
Host smart-de9c0edf-7e18-46d7-b64d-d4e0a193dfb0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478350003 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon
_timer_same_csr_outstanding.3478350003
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.1729182150
Short name T364
Test name
Test status
Simulation time 615986593 ps
CPU time 1.53 seconds
Started Mar 26 01:49:25 PM PDT 24
Finished Mar 26 01:49:27 PM PDT 24
Peak memory 198384 kb
Host smart-afb1156a-ac37-4ac0-990e-e613b46ce065
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729182150 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.1729182150
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.2169366962
Short name T408
Test name
Test status
Simulation time 8949571101 ps
CPU time 3.24 seconds
Started Mar 26 01:49:32 PM PDT 24
Finished Mar 26 01:49:36 PM PDT 24
Peak memory 198132 kb
Host smart-3a415eff-674d-43b6-ae30-e3186f307eae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169366962 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl
_intg_err.2169366962
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.2275814077
Short name T28
Test name
Test status
Simulation time 574328663 ps
CPU time 1.08 seconds
Started Mar 26 01:49:32 PM PDT 24
Finished Mar 26 01:49:33 PM PDT 24
Peak memory 198412 kb
Host smart-884deee7-50cb-484d-b703-fe940e7fa160
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275814077 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.2275814077
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.3372644895
Short name T29
Test name
Test status
Simulation time 307339473 ps
CPU time 1.01 seconds
Started Mar 26 01:49:33 PM PDT 24
Finished Mar 26 01:49:34 PM PDT 24
Peak memory 193084 kb
Host smart-dc3a9f1c-ba8f-4657-a876-b9b8c34aece8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372644895 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.3372644895
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.1124175876
Short name T346
Test name
Test status
Simulation time 448978154 ps
CPU time 1.06 seconds
Started Mar 26 01:49:33 PM PDT 24
Finished Mar 26 01:49:34 PM PDT 24
Peak memory 183692 kb
Host smart-bcb21ca5-596e-4b1c-b289-56fffec72351
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124175876 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.1124175876
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.523143538
Short name T85
Test name
Test status
Simulation time 1701500078 ps
CPU time 1.11 seconds
Started Mar 26 01:49:32 PM PDT 24
Finished Mar 26 01:49:33 PM PDT 24
Peak memory 183756 kb
Host smart-3e43701d-e6bb-4933-b0d5-ab756f02cfb8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523143538 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_
timer_same_csr_outstanding.523143538
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.423166552
Short name T358
Test name
Test status
Simulation time 908239531 ps
CPU time 2.27 seconds
Started Mar 26 01:49:33 PM PDT 24
Finished Mar 26 01:49:36 PM PDT 24
Peak memory 198592 kb
Host smart-fa577762-1e3f-4349-b002-0dc7b396dad2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423166552 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.423166552
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.967705074
Short name T33
Test name
Test status
Simulation time 9101549986 ps
CPU time 2.21 seconds
Started Mar 26 01:49:33 PM PDT 24
Finished Mar 26 01:49:36 PM PDT 24
Peak memory 198112 kb
Host smart-3f64579a-80cb-49ca-bcc2-5e811a77c481
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967705074 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_
intg_err.967705074
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.825743263
Short name T370
Test name
Test status
Simulation time 543136006 ps
CPU time 1.25 seconds
Started Mar 26 01:49:35 PM PDT 24
Finished Mar 26 01:49:37 PM PDT 24
Peak memory 198668 kb
Host smart-9be7a2ee-2cb2-4925-b7a8-b757ed4fbb3c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825743263 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.825743263
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.4149393639
Short name T66
Test name
Test status
Simulation time 362162983 ps
CPU time 0.72 seconds
Started Mar 26 01:49:32 PM PDT 24
Finished Mar 26 01:49:33 PM PDT 24
Peak memory 183744 kb
Host smart-1432fb42-ddc2-436d-9138-2d836eca1b6e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149393639 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.4149393639
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.2908219690
Short name T289
Test name
Test status
Simulation time 445890789 ps
CPU time 0.7 seconds
Started Mar 26 01:49:34 PM PDT 24
Finished Mar 26 01:49:35 PM PDT 24
Peak memory 183640 kb
Host smart-accc7dbe-6eab-4804-84e1-1e18d564e861
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908219690 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.2908219690
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.1011230762
Short name T347
Test name
Test status
Simulation time 2216247017 ps
CPU time 3.83 seconds
Started Mar 26 01:49:34 PM PDT 24
Finished Mar 26 01:49:38 PM PDT 24
Peak memory 194816 kb
Host smart-b69deed6-d66c-4367-a8d4-050c0561ac02
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011230762 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon
_timer_same_csr_outstanding.1011230762
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.3132348918
Short name T337
Test name
Test status
Simulation time 568993596 ps
CPU time 2.91 seconds
Started Mar 26 01:49:34 PM PDT 24
Finished Mar 26 01:49:37 PM PDT 24
Peak memory 198548 kb
Host smart-bf2947a6-4c18-437f-be33-c20854244edf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132348918 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.3132348918
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.1716691913
Short name T407
Test name
Test status
Simulation time 7972393515 ps
CPU time 9.42 seconds
Started Mar 26 01:49:34 PM PDT 24
Finished Mar 26 01:49:44 PM PDT 24
Peak memory 198052 kb
Host smart-f29273e7-0a91-4e69-8a48-2c93114d4eba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716691913 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl
_intg_err.1716691913
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.3760014474
Short name T419
Test name
Test status
Simulation time 474509426 ps
CPU time 0.98 seconds
Started Mar 26 01:49:42 PM PDT 24
Finished Mar 26 01:49:43 PM PDT 24
Peak memory 196236 kb
Host smart-303583c1-2b48-4a3a-a151-cf17e1c4adae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760014474 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.3760014474
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.2449748281
Short name T301
Test name
Test status
Simulation time 445521589 ps
CPU time 1.21 seconds
Started Mar 26 01:49:34 PM PDT 24
Finished Mar 26 01:49:36 PM PDT 24
Peak memory 183448 kb
Host smart-a894af0c-8277-4817-9452-3c346e2f618d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449748281 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.2449748281
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.536987471
Short name T79
Test name
Test status
Simulation time 2884518306 ps
CPU time 1.8 seconds
Started Mar 26 01:49:43 PM PDT 24
Finished Mar 26 01:49:44 PM PDT 24
Peak memory 194464 kb
Host smart-382f2adf-d753-4b72-9a14-22c0a510606f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536987471 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_
timer_same_csr_outstanding.536987471
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.2611381013
Short name T380
Test name
Test status
Simulation time 707587006 ps
CPU time 2.33 seconds
Started Mar 26 01:49:32 PM PDT 24
Finished Mar 26 01:49:35 PM PDT 24
Peak memory 198608 kb
Host smart-005c1215-4a05-42a0-b5a7-23f08757103b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611381013 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.2611381013
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.4066114864
Short name T323
Test name
Test status
Simulation time 4308409756 ps
CPU time 2.66 seconds
Started Mar 26 01:49:32 PM PDT 24
Finished Mar 26 01:49:35 PM PDT 24
Peak memory 197380 kb
Host smart-8cc34002-8aa1-4e0d-b66d-9a46510a860a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066114864 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl
_intg_err.4066114864
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_jump.1356031328
Short name T27
Test name
Test status
Simulation time 385410916 ps
CPU time 1.07 seconds
Started Mar 26 02:44:11 PM PDT 24
Finished Mar 26 02:44:12 PM PDT 24
Peak memory 183496 kb
Host smart-d31a3d66-52a5-40ee-be49-9180ca201ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356031328 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.1356031328
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.2049598047
Short name T131
Test name
Test status
Simulation time 16407264005 ps
CPU time 21.15 seconds
Started Mar 26 02:44:06 PM PDT 24
Finished Mar 26 02:44:27 PM PDT 24
Peak memory 183536 kb
Host smart-b095711c-0e6c-4a8e-bc92-8ad2ba6fd7e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049598047 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.2049598047
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.2132994106
Short name T60
Test name
Test status
Simulation time 577894342 ps
CPU time 0.74 seconds
Started Mar 26 02:44:10 PM PDT 24
Finished Mar 26 02:44:11 PM PDT 24
Peak memory 183484 kb
Host smart-180d105c-a502-49cc-9a82-e5d3c7803dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132994106 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.2132994106
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.577462317
Short name T259
Test name
Test status
Simulation time 330651656395 ps
CPU time 142.61 seconds
Started Mar 26 02:44:08 PM PDT 24
Finished Mar 26 02:46:36 PM PDT 24
Peak memory 183524 kb
Host smart-0e14b6ff-b646-46a6-95e9-3612cd306ac8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577462317 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_al
l.577462317
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.1288631245
Short name T236
Test name
Test status
Simulation time 40289516978 ps
CPU time 351.64 seconds
Started Mar 26 02:44:10 PM PDT 24
Finished Mar 26 02:50:02 PM PDT 24
Peak memory 198484 kb
Host smart-b3bce372-eef2-430a-9ec5-8a776c44d63c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288631245 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.1288631245
Directory /workspace/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.aon_timer_jump.2629673991
Short name T146
Test name
Test status
Simulation time 554998970 ps
CPU time 1.4 seconds
Started Mar 26 02:44:10 PM PDT 24
Finished Mar 26 02:44:12 PM PDT 24
Peak memory 183468 kb
Host smart-6540c85b-7cd8-42d5-87e0-da985d188714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629673991 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.2629673991
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.2535366162
Short name T113
Test name
Test status
Simulation time 21882562698 ps
CPU time 10.57 seconds
Started Mar 26 02:44:07 PM PDT 24
Finished Mar 26 02:44:18 PM PDT 24
Peak memory 191720 kb
Host smart-7b24f734-668b-4b6a-945d-ca46b1ab32ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535366162 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.2535366162
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.3727755002
Short name T15
Test name
Test status
Simulation time 8068271913 ps
CPU time 13.83 seconds
Started Mar 26 02:44:19 PM PDT 24
Finished Mar 26 02:44:33 PM PDT 24
Peak memory 215308 kb
Host smart-54f7530b-de24-488c-803f-0c07683086bb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727755002 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.3727755002
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.470709602
Short name T57
Test name
Test status
Simulation time 371191010 ps
CPU time 1.09 seconds
Started Mar 26 02:44:09 PM PDT 24
Finished Mar 26 02:44:10 PM PDT 24
Peak memory 183484 kb
Host smart-7970af57-8e9c-481f-a497-b1c375af280d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470709602 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.470709602
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.2574597798
Short name T235
Test name
Test status
Simulation time 18977149118 ps
CPU time 14.68 seconds
Started Mar 26 02:44:14 PM PDT 24
Finished Mar 26 02:44:29 PM PDT 24
Peak memory 183548 kb
Host smart-c77816e4-f7fa-494a-81a9-e94df0612efa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574597798 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_a
ll.2574597798
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.256907702
Short name T230
Test name
Test status
Simulation time 143634617398 ps
CPU time 400.44 seconds
Started Mar 26 02:44:09 PM PDT 24
Finished Mar 26 02:50:50 PM PDT 24
Peak memory 198324 kb
Host smart-731ddc5f-dbd1-4148-9ce2-b60fc9a761e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256907702 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.256907702
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.aon_timer_jump.3842989640
Short name T51
Test name
Test status
Simulation time 528049102 ps
CPU time 1.1 seconds
Started Mar 26 02:44:30 PM PDT 24
Finished Mar 26 02:44:31 PM PDT 24
Peak memory 183660 kb
Host smart-7e996bf6-41ad-436d-9148-f05d0a18d961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842989640 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.3842989640
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.3077371369
Short name T213
Test name
Test status
Simulation time 13437813355 ps
CPU time 5.04 seconds
Started Mar 26 02:44:29 PM PDT 24
Finished Mar 26 02:44:35 PM PDT 24
Peak memory 183508 kb
Host smart-38fb4d24-effa-465e-bbb3-4ab70a5ed196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077371369 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.3077371369
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.936857919
Short name T163
Test name
Test status
Simulation time 384251633 ps
CPU time 1.11 seconds
Started Mar 26 02:44:32 PM PDT 24
Finished Mar 26 02:44:33 PM PDT 24
Peak memory 183468 kb
Host smart-3640eb0e-ab22-42cc-829e-cccb2b2916f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936857919 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.936857919
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.141452846
Short name T142
Test name
Test status
Simulation time 124500447983 ps
CPU time 42.36 seconds
Started Mar 26 02:44:24 PM PDT 24
Finished Mar 26 02:45:06 PM PDT 24
Peak memory 183556 kb
Host smart-cb3ebf51-e59d-42d3-bb99-878195341fce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141452846 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_a
ll.141452846
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.3185202446
Short name T36
Test name
Test status
Simulation time 5387004517 ps
CPU time 25.81 seconds
Started Mar 26 02:44:30 PM PDT 24
Finished Mar 26 02:44:56 PM PDT 24
Peak memory 198436 kb
Host smart-1a2e6ac2-0c98-4c14-bedd-53bf1a8b1732
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185202446 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.3185202446
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.aon_timer_jump.4185035551
Short name T175
Test name
Test status
Simulation time 543957131 ps
CPU time 1.35 seconds
Started Mar 26 02:44:24 PM PDT 24
Finished Mar 26 02:44:26 PM PDT 24
Peak memory 183392 kb
Host smart-30a919d3-39cf-4e9c-b13e-3bfeadb0ab4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185035551 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.4185035551
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.3052278347
Short name T144
Test name
Test status
Simulation time 3077543712 ps
CPU time 1.33 seconds
Started Mar 26 02:44:30 PM PDT 24
Finished Mar 26 02:44:32 PM PDT 24
Peak memory 183576 kb
Host smart-9dd1cd88-48e6-420f-a005-ce57187fa0ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052278347 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.3052278347
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.3763108801
Short name T192
Test name
Test status
Simulation time 445701872 ps
CPU time 1.28 seconds
Started Mar 26 02:44:30 PM PDT 24
Finished Mar 26 02:44:31 PM PDT 24
Peak memory 183480 kb
Host smart-16bea5c2-83b0-45ed-acf2-07d4c39701b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763108801 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.3763108801
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.3092242097
Short name T21
Test name
Test status
Simulation time 308686658039 ps
CPU time 88.38 seconds
Started Mar 26 02:44:27 PM PDT 24
Finished Mar 26 02:45:55 PM PDT 24
Peak memory 195080 kb
Host smart-1bff3720-56bc-4c75-bfaa-9087783d460f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092242097 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_
all.3092242097
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.73039822
Short name T9
Test name
Test status
Simulation time 10635380860 ps
CPU time 113.09 seconds
Started Mar 26 02:44:28 PM PDT 24
Finished Mar 26 02:46:21 PM PDT 24
Peak memory 198428 kb
Host smart-4516bf1f-6b62-4b04-b223-1ac32c59b1ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73039822 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand_reset.73039822
Directory /workspace/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.aon_timer_jump.1629246941
Short name T206
Test name
Test status
Simulation time 384807114 ps
CPU time 0.59 seconds
Started Mar 26 02:44:24 PM PDT 24
Finished Mar 26 02:44:25 PM PDT 24
Peak memory 183448 kb
Host smart-666b43d3-09ce-4030-a23e-658bc1439d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629246941 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.1629246941
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.2641174016
Short name T234
Test name
Test status
Simulation time 1740064779 ps
CPU time 1.22 seconds
Started Mar 26 02:44:26 PM PDT 24
Finished Mar 26 02:44:28 PM PDT 24
Peak memory 183476 kb
Host smart-6c3324f4-8120-4559-a480-2de1f3a28eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641174016 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.2641174016
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.1746025718
Short name T5
Test name
Test status
Simulation time 525503228 ps
CPU time 0.88 seconds
Started Mar 26 02:44:28 PM PDT 24
Finished Mar 26 02:44:29 PM PDT 24
Peak memory 183488 kb
Host smart-82aa9c5b-f991-4eb7-bdad-37dc5af6b321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746025718 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.1746025718
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.953660168
Short name T257
Test name
Test status
Simulation time 281031073472 ps
CPU time 120.59 seconds
Started Mar 26 02:44:29 PM PDT 24
Finished Mar 26 02:46:30 PM PDT 24
Peak memory 191784 kb
Host smart-1643a9d9-310c-42fc-b61c-9589703d0922
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953660168 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_a
ll.953660168
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.1031381207
Short name T148
Test name
Test status
Simulation time 29061634229 ps
CPU time 161.07 seconds
Started Mar 26 02:44:31 PM PDT 24
Finished Mar 26 02:47:12 PM PDT 24
Peak memory 198472 kb
Host smart-a1eb86d2-b649-432b-bf9b-1c96eaf8c5f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031381207 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.1031381207
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_jump.1658670366
Short name T203
Test name
Test status
Simulation time 552436550 ps
CPU time 1.4 seconds
Started Mar 26 02:44:27 PM PDT 24
Finished Mar 26 02:44:28 PM PDT 24
Peak memory 183504 kb
Host smart-8c56fb69-869f-42fc-a1a8-7838e67eaf5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658670366 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.1658670366
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.104807100
Short name T127
Test name
Test status
Simulation time 35859887389 ps
CPU time 29.63 seconds
Started Mar 26 02:44:29 PM PDT 24
Finished Mar 26 02:44:59 PM PDT 24
Peak memory 191748 kb
Host smart-94f7ff33-db43-4a5a-8a13-c89b678c583b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104807100 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.104807100
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.1837742521
Short name T253
Test name
Test status
Simulation time 490916087 ps
CPU time 0.8 seconds
Started Mar 26 02:44:27 PM PDT 24
Finished Mar 26 02:44:28 PM PDT 24
Peak memory 183500 kb
Host smart-18831bcb-39f8-4a50-97bf-fce998cebaa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837742521 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.1837742521
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.3926685006
Short name T6
Test name
Test status
Simulation time 111009683383 ps
CPU time 163.43 seconds
Started Mar 26 02:44:28 PM PDT 24
Finished Mar 26 02:47:12 PM PDT 24
Peak memory 183484 kb
Host smart-7b6280b1-916a-4de2-821b-430a35c740f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926685006 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_
all.3926685006
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.1415567616
Short name T53
Test name
Test status
Simulation time 571326072156 ps
CPU time 685.79 seconds
Started Mar 26 02:44:25 PM PDT 24
Finished Mar 26 02:55:51 PM PDT 24
Peak memory 200928 kb
Host smart-3dabbe41-1644-44ba-8270-b3a4b89db160
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415567616 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.1415567616
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.aon_timer_jump.424358347
Short name T280
Test name
Test status
Simulation time 554871341 ps
CPU time 1.46 seconds
Started Mar 26 02:44:25 PM PDT 24
Finished Mar 26 02:44:27 PM PDT 24
Peak memory 183500 kb
Host smart-9e0f8c4d-74d7-4088-b2a7-298dd0893d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424358347 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.424358347
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.2863283598
Short name T124
Test name
Test status
Simulation time 18833766098 ps
CPU time 28.13 seconds
Started Mar 26 02:44:33 PM PDT 24
Finished Mar 26 02:45:02 PM PDT 24
Peak memory 183556 kb
Host smart-23bacc1b-d68c-4120-ad85-985d8985dd35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863283598 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.2863283598
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.3196357000
Short name T58
Test name
Test status
Simulation time 474794546 ps
CPU time 0.66 seconds
Started Mar 26 02:44:24 PM PDT 24
Finished Mar 26 02:44:26 PM PDT 24
Peak memory 183468 kb
Host smart-c1d33ce7-086e-42d0-af3c-26bf2c07c41f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196357000 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.3196357000
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.2174322955
Short name T216
Test name
Test status
Simulation time 161936219287 ps
CPU time 68.16 seconds
Started Mar 26 02:44:25 PM PDT 24
Finished Mar 26 02:45:34 PM PDT 24
Peak memory 194848 kb
Host smart-f1640e93-cd14-4595-bcc7-8524677e3398
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174322955 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_
all.2174322955
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.2434474860
Short name T1
Test name
Test status
Simulation time 124624334216 ps
CPU time 554.72 seconds
Started Mar 26 02:44:28 PM PDT 24
Finished Mar 26 02:53:43 PM PDT 24
Peak memory 198544 kb
Host smart-2ae56588-8168-44a4-b0f7-11cdbc46aaf7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434474860 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.2434474860
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.aon_timer_jump.1123521586
Short name T278
Test name
Test status
Simulation time 453769786 ps
CPU time 1.14 seconds
Started Mar 26 02:44:31 PM PDT 24
Finished Mar 26 02:44:32 PM PDT 24
Peak memory 183316 kb
Host smart-efc89fbb-1d60-4e8e-bc50-ec1adfcc2ede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123521586 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.1123521586
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.556799693
Short name T25
Test name
Test status
Simulation time 26536841081 ps
CPU time 10.2 seconds
Started Mar 26 02:44:29 PM PDT 24
Finished Mar 26 02:44:39 PM PDT 24
Peak memory 183436 kb
Host smart-4f435394-585d-43cb-a411-026be33da0c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556799693 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.556799693
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.2933211304
Short name T180
Test name
Test status
Simulation time 463129558 ps
CPU time 0.71 seconds
Started Mar 26 02:44:27 PM PDT 24
Finished Mar 26 02:44:28 PM PDT 24
Peak memory 183480 kb
Host smart-e6fde87a-e108-4cec-acd9-9d916b2ecfab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933211304 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.2933211304
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.565311208
Short name T218
Test name
Test status
Simulation time 119453675255 ps
CPU time 195.02 seconds
Started Mar 26 02:44:25 PM PDT 24
Finished Mar 26 02:47:41 PM PDT 24
Peak memory 183576 kb
Host smart-7e12b3bd-7087-42d3-b87b-98811833b913
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565311208 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_a
ll.565311208
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.456698684
Short name T226
Test name
Test status
Simulation time 36978848441 ps
CPU time 291.07 seconds
Started Mar 26 02:44:31 PM PDT 24
Finished Mar 26 02:49:22 PM PDT 24
Peak memory 198480 kb
Host smart-a800fba2-4dcf-42b5-a7c5-4a7acf3773e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456698684 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.456698684
Directory /workspace/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.aon_timer_jump.2547336607
Short name T189
Test name
Test status
Simulation time 548545544 ps
CPU time 0.66 seconds
Started Mar 26 02:44:32 PM PDT 24
Finished Mar 26 02:44:32 PM PDT 24
Peak memory 183464 kb
Host smart-8dd995aa-2941-4395-9af6-0e3f69b148e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547336607 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.2547336607
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.4103548478
Short name T169
Test name
Test status
Simulation time 19775641753 ps
CPU time 27.53 seconds
Started Mar 26 02:44:28 PM PDT 24
Finished Mar 26 02:44:56 PM PDT 24
Peak memory 183548 kb
Host smart-3191fb22-48cb-4490-b493-f575f50c112d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103548478 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.4103548478
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.2341629198
Short name T133
Test name
Test status
Simulation time 531997649 ps
CPU time 1.37 seconds
Started Mar 26 02:44:31 PM PDT 24
Finished Mar 26 02:44:32 PM PDT 24
Peak memory 183512 kb
Host smart-8a2f46b5-ee4d-4931-b6cf-a31b10140766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341629198 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.2341629198
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.556902788
Short name T40
Test name
Test status
Simulation time 148316387578 ps
CPU time 18.73 seconds
Started Mar 26 02:44:32 PM PDT 24
Finished Mar 26 02:44:51 PM PDT 24
Peak memory 195284 kb
Host smart-129017f9-f417-4015-9bc9-4a363775e96a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556902788 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_a
ll.556902788
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.372860293
Short name T249
Test name
Test status
Simulation time 49047291677 ps
CPU time 567.81 seconds
Started Mar 26 02:44:31 PM PDT 24
Finished Mar 26 02:53:59 PM PDT 24
Peak memory 198372 kb
Host smart-7b3bb025-499c-46bf-ae14-0684086d5c4d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372860293 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.372860293
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.aon_timer_jump.3337786026
Short name T167
Test name
Test status
Simulation time 556232775 ps
CPU time 1.39 seconds
Started Mar 26 02:44:33 PM PDT 24
Finished Mar 26 02:44:35 PM PDT 24
Peak memory 183492 kb
Host smart-a80436d3-5492-440f-a650-d02d4610a435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337786026 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.3337786026
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.1492344183
Short name T224
Test name
Test status
Simulation time 29785898173 ps
CPU time 5.82 seconds
Started Mar 26 02:44:30 PM PDT 24
Finished Mar 26 02:44:36 PM PDT 24
Peak memory 182900 kb
Host smart-583eae2d-5c3d-4871-8306-9246be9d1650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492344183 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.1492344183
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.678627637
Short name T23
Test name
Test status
Simulation time 531303388 ps
CPU time 0.94 seconds
Started Mar 26 02:44:30 PM PDT 24
Finished Mar 26 02:44:31 PM PDT 24
Peak memory 182608 kb
Host smart-1ce13816-ab14-4924-a069-7c22c31369b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678627637 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.678627637
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.1115296520
Short name T136
Test name
Test status
Simulation time 90295357584 ps
CPU time 140.08 seconds
Started Mar 26 02:44:38 PM PDT 24
Finished Mar 26 02:46:58 PM PDT 24
Peak memory 193664 kb
Host smart-86f0c023-de37-40ab-aab2-98a1f886c854
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115296520 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_
all.1115296520
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_jump.3713657089
Short name T117
Test name
Test status
Simulation time 560356799 ps
CPU time 0.63 seconds
Started Mar 26 02:44:33 PM PDT 24
Finished Mar 26 02:44:34 PM PDT 24
Peak memory 183412 kb
Host smart-91750d8d-d3bc-4c8d-ab10-c6afe17ce88d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713657089 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.3713657089
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.2071484673
Short name T55
Test name
Test status
Simulation time 15673723999 ps
CPU time 25.2 seconds
Started Mar 26 02:44:33 PM PDT 24
Finished Mar 26 02:44:58 PM PDT 24
Peak memory 183428 kb
Host smart-ca74ff6f-4eb9-4860-98f3-acefaf7ab9a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071484673 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.2071484673
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.887265354
Short name T111
Test name
Test status
Simulation time 586313667 ps
CPU time 1.31 seconds
Started Mar 26 02:44:41 PM PDT 24
Finished Mar 26 02:44:43 PM PDT 24
Peak memory 183384 kb
Host smart-9a7d06e1-7ea3-424d-b182-31d76d9c6f5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887265354 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.887265354
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.1780348226
Short name T138
Test name
Test status
Simulation time 267010063267 ps
CPU time 184.13 seconds
Started Mar 26 02:44:36 PM PDT 24
Finished Mar 26 02:47:41 PM PDT 24
Peak memory 183460 kb
Host smart-abca6732-7438-4d9d-9bbf-af05a0f7b80e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780348226 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_
all.1780348226
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.1368573839
Short name T94
Test name
Test status
Simulation time 166417620376 ps
CPU time 312.05 seconds
Started Mar 26 02:44:38 PM PDT 24
Finished Mar 26 02:49:50 PM PDT 24
Peak memory 198528 kb
Host smart-b1877ff3-68d6-4e14-bea9-8bc34dc6323e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368573839 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.1368573839
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.aon_timer_jump.3105070827
Short name T121
Test name
Test status
Simulation time 496562528 ps
CPU time 0.64 seconds
Started Mar 26 02:44:41 PM PDT 24
Finished Mar 26 02:44:41 PM PDT 24
Peak memory 183388 kb
Host smart-7b4dcf45-9616-4226-9666-02a92fedfee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105070827 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.3105070827
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.1892434079
Short name T87
Test name
Test status
Simulation time 11502925137 ps
CPU time 18.48 seconds
Started Mar 26 02:44:36 PM PDT 24
Finished Mar 26 02:44:55 PM PDT 24
Peak memory 183532 kb
Host smart-3f12c538-0338-4806-b1c9-0c79c217852d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892434079 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.1892434079
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.2844123923
Short name T229
Test name
Test status
Simulation time 565268123 ps
CPU time 0.6 seconds
Started Mar 26 02:44:38 PM PDT 24
Finished Mar 26 02:44:39 PM PDT 24
Peak memory 183504 kb
Host smart-379fdadd-6526-4bc6-b284-3d01b290c374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844123923 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.2844123923
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.3046218079
Short name T200
Test name
Test status
Simulation time 176394174038 ps
CPU time 48.12 seconds
Started Mar 26 02:44:39 PM PDT 24
Finished Mar 26 02:45:27 PM PDT 24
Peak memory 183544 kb
Host smart-772f61f0-b4b8-429a-b468-d363c2ac239c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046218079 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_
all.3046218079
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.2922100433
Short name T135
Test name
Test status
Simulation time 74618325707 ps
CPU time 157.91 seconds
Started Mar 26 02:44:36 PM PDT 24
Finished Mar 26 02:47:15 PM PDT 24
Peak memory 198340 kb
Host smart-da125baa-b2c3-4263-873d-73aaade687ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922100433 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.2922100433
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_jump.2155305997
Short name T118
Test name
Test status
Simulation time 524476703 ps
CPU time 0.9 seconds
Started Mar 26 02:44:15 PM PDT 24
Finished Mar 26 02:44:16 PM PDT 24
Peak memory 183444 kb
Host smart-293f7931-8e9b-45e6-a87e-a036148e4f16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155305997 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.2155305997
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.1632491798
Short name T126
Test name
Test status
Simulation time 3604120759 ps
CPU time 6.14 seconds
Started Mar 26 02:44:14 PM PDT 24
Finished Mar 26 02:44:20 PM PDT 24
Peak memory 183488 kb
Host smart-d3c3538a-a2b3-4668-8737-76ba533ce79c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632491798 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.1632491798
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.2806557897
Short name T16
Test name
Test status
Simulation time 4614682018 ps
CPU time 4.37 seconds
Started Mar 26 02:44:16 PM PDT 24
Finished Mar 26 02:44:21 PM PDT 24
Peak memory 215512 kb
Host smart-f4ee6c2f-a12d-4e45-86af-43807264a17b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806557897 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.2806557897
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.1850022255
Short name T190
Test name
Test status
Simulation time 418375840 ps
CPU time 0.71 seconds
Started Mar 26 02:44:16 PM PDT 24
Finished Mar 26 02:44:16 PM PDT 24
Peak memory 183512 kb
Host smart-b28c2b21-c1a3-4b3a-aee5-eb9765bdeb07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850022255 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.1850022255
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_jump.2293476635
Short name T179
Test name
Test status
Simulation time 474595344 ps
CPU time 0.7 seconds
Started Mar 26 02:44:36 PM PDT 24
Finished Mar 26 02:44:37 PM PDT 24
Peak memory 183444 kb
Host smart-a514bdf6-5d85-47e4-bb50-90c0bfc5573e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293476635 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.2293476635
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.3385381640
Short name T231
Test name
Test status
Simulation time 34135242577 ps
CPU time 49.67 seconds
Started Mar 26 02:44:36 PM PDT 24
Finished Mar 26 02:45:26 PM PDT 24
Peak memory 183388 kb
Host smart-0af44b0e-a50d-4174-95be-dabb8f7a81a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385381640 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.3385381640
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.2263064284
Short name T263
Test name
Test status
Simulation time 386495957 ps
CPU time 0.69 seconds
Started Mar 26 02:44:39 PM PDT 24
Finished Mar 26 02:44:40 PM PDT 24
Peak memory 183508 kb
Host smart-4631c72f-9690-4124-ad64-a3e7d4a6c871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263064284 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.2263064284
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.2198899988
Short name T150
Test name
Test status
Simulation time 111773368678 ps
CPU time 46.6 seconds
Started Mar 26 02:44:37 PM PDT 24
Finished Mar 26 02:45:24 PM PDT 24
Peak memory 193524 kb
Host smart-c4ac9143-e42f-4d9a-bee8-81d40d1f3dbe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198899988 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_
all.2198899988
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.4203935273
Short name T38
Test name
Test status
Simulation time 471447591601 ps
CPU time 974.19 seconds
Started Mar 26 02:44:40 PM PDT 24
Finished Mar 26 03:00:55 PM PDT 24
Peak memory 211888 kb
Host smart-45820f67-7246-408d-8c46-1351e5447d85
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203935273 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.4203935273
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_jump.2565870318
Short name T41
Test name
Test status
Simulation time 450134008 ps
CPU time 0.65 seconds
Started Mar 26 02:44:35 PM PDT 24
Finished Mar 26 02:44:36 PM PDT 24
Peak memory 183480 kb
Host smart-fcc86ba0-5b4a-43a7-9d5a-b684a835e396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565870318 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.2565870318
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.456838281
Short name T261
Test name
Test status
Simulation time 13695379286 ps
CPU time 5.24 seconds
Started Mar 26 02:44:35 PM PDT 24
Finished Mar 26 02:44:40 PM PDT 24
Peak memory 191636 kb
Host smart-75a7e3dc-031e-40e5-8c51-42e1bc28fc1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456838281 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.456838281
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.1709972539
Short name T2
Test name
Test status
Simulation time 486117243 ps
CPU time 0.68 seconds
Started Mar 26 02:44:36 PM PDT 24
Finished Mar 26 02:44:37 PM PDT 24
Peak memory 183472 kb
Host smart-ba30e49a-0436-4b62-bff1-1c96c5ff2424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709972539 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.1709972539
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.4180937289
Short name T252
Test name
Test status
Simulation time 63050981573 ps
CPU time 52.06 seconds
Started Mar 26 02:44:34 PM PDT 24
Finished Mar 26 02:45:26 PM PDT 24
Peak memory 183512 kb
Host smart-27e2d039-ddc3-4e3f-b748-66d77e0ffbdd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180937289 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_
all.4180937289
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.87641063
Short name T63
Test name
Test status
Simulation time 32008287267 ps
CPU time 207.63 seconds
Started Mar 26 02:44:38 PM PDT 24
Finished Mar 26 02:48:06 PM PDT 24
Peak memory 198348 kb
Host smart-3d6265f6-5b33-4d6a-932f-8a27de024c46
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87641063 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.87641063
Directory /workspace/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.aon_timer_jump.1713044406
Short name T187
Test name
Test status
Simulation time 380110427 ps
CPU time 0.75 seconds
Started Mar 26 02:44:38 PM PDT 24
Finished Mar 26 02:44:39 PM PDT 24
Peak memory 183512 kb
Host smart-2d74f81c-e805-4978-a864-bb62a783e962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713044406 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.1713044406
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.2631811519
Short name T272
Test name
Test status
Simulation time 42854838843 ps
CPU time 21.93 seconds
Started Mar 26 02:44:41 PM PDT 24
Finished Mar 26 02:45:03 PM PDT 24
Peak memory 191648 kb
Host smart-a118bfd8-4c10-4063-b1a3-38bd7346c6a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631811519 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.2631811519
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.1062514919
Short name T264
Test name
Test status
Simulation time 373323687 ps
CPU time 1.08 seconds
Started Mar 26 02:44:37 PM PDT 24
Finished Mar 26 02:44:39 PM PDT 24
Peak memory 183372 kb
Host smart-75f3bc73-25b7-4f71-b469-7006664d3019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062514919 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.1062514919
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.1022455308
Short name T220
Test name
Test status
Simulation time 482345026490 ps
CPU time 810.82 seconds
Started Mar 26 02:44:36 PM PDT 24
Finished Mar 26 02:58:07 PM PDT 24
Peak memory 183572 kb
Host smart-4c494bc7-98a8-4b03-97aa-b244c225426b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022455308 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_
all.1022455308
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.928956207
Short name T196
Test name
Test status
Simulation time 158043836829 ps
CPU time 452.11 seconds
Started Mar 26 02:44:34 PM PDT 24
Finished Mar 26 02:52:07 PM PDT 24
Peak memory 206556 kb
Host smart-08d3b9c2-94cb-4bda-8477-7ee8e1d2d232
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928956207 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.928956207
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.aon_timer_jump.157847728
Short name T50
Test name
Test status
Simulation time 484248466 ps
CPU time 0.89 seconds
Started Mar 26 02:44:37 PM PDT 24
Finished Mar 26 02:44:38 PM PDT 24
Peak memory 183320 kb
Host smart-6063d837-66ca-4e0b-9b65-f55e87404a9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157847728 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.157847728
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.3453209059
Short name T244
Test name
Test status
Simulation time 8122611139 ps
CPU time 12.13 seconds
Started Mar 26 02:44:41 PM PDT 24
Finished Mar 26 02:44:53 PM PDT 24
Peak memory 191648 kb
Host smart-03d4ad43-f249-4b62-8e9c-9efb241ea508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453209059 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.3453209059
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.3819587085
Short name T211
Test name
Test status
Simulation time 575721492 ps
CPU time 1.3 seconds
Started Mar 26 02:44:33 PM PDT 24
Finished Mar 26 02:44:34 PM PDT 24
Peak memory 183524 kb
Host smart-810b16cf-96f1-47dd-b0a5-22e41664fb1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819587085 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.3819587085
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.3526307056
Short name T145
Test name
Test status
Simulation time 140112876914 ps
CPU time 202.65 seconds
Started Mar 26 02:44:38 PM PDT 24
Finished Mar 26 02:48:01 PM PDT 24
Peak memory 194108 kb
Host smart-6bb3097e-1399-40e4-83a8-32518817d143
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526307056 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_
all.3526307056
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.2843555903
Short name T98
Test name
Test status
Simulation time 77798372995 ps
CPU time 305.21 seconds
Started Mar 26 02:44:36 PM PDT 24
Finished Mar 26 02:49:42 PM PDT 24
Peak memory 198128 kb
Host smart-7ff1d285-952a-4afc-a1c8-3948b9dd8bc1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843555903 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.2843555903
Directory /workspace/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.aon_timer_jump.130973960
Short name T160
Test name
Test status
Simulation time 389049371 ps
CPU time 0.74 seconds
Started Mar 26 02:44:37 PM PDT 24
Finished Mar 26 02:44:38 PM PDT 24
Peak memory 183476 kb
Host smart-e7a91722-4dd1-4add-b17c-389b13142a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130973960 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.130973960
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.131656872
Short name T250
Test name
Test status
Simulation time 1058459848 ps
CPU time 1.4 seconds
Started Mar 26 02:44:33 PM PDT 24
Finished Mar 26 02:44:35 PM PDT 24
Peak memory 183464 kb
Host smart-2725e391-984d-42a7-801c-7c9753912645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131656872 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.131656872
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.310050283
Short name T109
Test name
Test status
Simulation time 406350737 ps
CPU time 0.71 seconds
Started Mar 26 02:44:35 PM PDT 24
Finished Mar 26 02:44:36 PM PDT 24
Peak memory 183424 kb
Host smart-08530bb7-4b5d-488f-ab46-ae784c219e32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310050283 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.310050283
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.422028254
Short name T154
Test name
Test status
Simulation time 88505447335 ps
CPU time 33.04 seconds
Started Mar 26 02:44:32 PM PDT 24
Finished Mar 26 02:45:05 PM PDT 24
Peak memory 193484 kb
Host smart-c86be5c8-0f23-4ca5-96f1-34a7308fbc0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422028254 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_a
ll.422028254
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.1147374915
Short name T93
Test name
Test status
Simulation time 131077492332 ps
CPU time 263.92 seconds
Started Mar 26 02:44:36 PM PDT 24
Finished Mar 26 02:49:01 PM PDT 24
Peak memory 198416 kb
Host smart-8fc16544-8bcf-4fb4-bd18-625b4bd3ba7b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147374915 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand_reset.1147374915
Directory /workspace/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.aon_timer_jump.3390089511
Short name T56
Test name
Test status
Simulation time 526261946 ps
CPU time 1.11 seconds
Started Mar 26 02:44:37 PM PDT 24
Finished Mar 26 02:44:38 PM PDT 24
Peak memory 183196 kb
Host smart-c16f98ef-e61b-439b-9570-be2ec80fce1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390089511 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.3390089511
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.3210891252
Short name T3
Test name
Test status
Simulation time 12196021024 ps
CPU time 14.7 seconds
Started Mar 26 02:44:36 PM PDT 24
Finished Mar 26 02:44:51 PM PDT 24
Peak memory 191700 kb
Host smart-b24eab4f-e2ed-46fd-84ea-f99bc54aec73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210891252 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.3210891252
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.4179959302
Short name T239
Test name
Test status
Simulation time 598210183 ps
CPU time 0.74 seconds
Started Mar 26 02:44:41 PM PDT 24
Finished Mar 26 02:44:42 PM PDT 24
Peak memory 183380 kb
Host smart-95a50b56-bed7-48f1-a7e9-808d8e1d4eb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179959302 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.4179959302
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.1543395318
Short name T199
Test name
Test status
Simulation time 25020527695 ps
CPU time 17.82 seconds
Started Mar 26 02:44:41 PM PDT 24
Finished Mar 26 02:44:58 PM PDT 24
Peak memory 183452 kb
Host smart-47b7e6d4-4c67-4739-a05b-076c8cafca78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543395318 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_
all.1543395318
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.3647058518
Short name T96
Test name
Test status
Simulation time 670000198458 ps
CPU time 371.96 seconds
Started Mar 26 02:44:33 PM PDT 24
Finished Mar 26 02:50:46 PM PDT 24
Peak memory 198420 kb
Host smart-22d0f16e-f0f1-45af-bf04-69fe51cb1481
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647058518 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.3647058518
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.aon_timer_jump.3398879192
Short name T217
Test name
Test status
Simulation time 597233676 ps
CPU time 1.47 seconds
Started Mar 26 02:44:37 PM PDT 24
Finished Mar 26 02:44:39 PM PDT 24
Peak memory 183472 kb
Host smart-6ddab5de-78db-4804-a6f5-1816c343371d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398879192 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.3398879192
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.1349027910
Short name T59
Test name
Test status
Simulation time 32944246943 ps
CPU time 40.74 seconds
Started Mar 26 02:44:34 PM PDT 24
Finished Mar 26 02:45:15 PM PDT 24
Peak memory 191640 kb
Host smart-3c8c22b8-899b-4b57-8bf3-6d4b28a00b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349027910 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.1349027910
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.1537016288
Short name T172
Test name
Test status
Simulation time 427438716 ps
CPU time 0.9 seconds
Started Mar 26 02:44:36 PM PDT 24
Finished Mar 26 02:44:37 PM PDT 24
Peak memory 183436 kb
Host smart-94312eaf-5e79-4378-be9c-c1bb5886663a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537016288 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.1537016288
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.4143046623
Short name T188
Test name
Test status
Simulation time 15346523822 ps
CPU time 163.35 seconds
Started Mar 26 02:44:49 PM PDT 24
Finished Mar 26 02:47:33 PM PDT 24
Peak memory 198440 kb
Host smart-a45c1c31-0f5a-4cdd-bb13-c79730a7b901
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143046623 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.4143046623
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_jump.3945059196
Short name T177
Test name
Test status
Simulation time 500572063 ps
CPU time 0.83 seconds
Started Mar 26 02:44:49 PM PDT 24
Finished Mar 26 02:44:50 PM PDT 24
Peak memory 183516 kb
Host smart-8eae87fe-7be4-4f01-8fd1-a6f28820de8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945059196 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.3945059196
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.3919174276
Short name T186
Test name
Test status
Simulation time 22956474264 ps
CPU time 6.1 seconds
Started Mar 26 02:44:49 PM PDT 24
Finished Mar 26 02:44:56 PM PDT 24
Peak memory 183468 kb
Host smart-4c1b1898-0605-4458-ac05-81333655c2ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919174276 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.3919174276
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.786920780
Short name T176
Test name
Test status
Simulation time 597405971 ps
CPU time 0.79 seconds
Started Mar 26 02:44:54 PM PDT 24
Finished Mar 26 02:44:55 PM PDT 24
Peak memory 183484 kb
Host smart-dfe7b6d9-fd8b-4ab9-888f-0f05ae59cca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786920780 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.786920780
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.3540018059
Short name T31
Test name
Test status
Simulation time 90634319054 ps
CPU time 142.6 seconds
Started Mar 26 02:44:55 PM PDT 24
Finished Mar 26 02:47:17 PM PDT 24
Peak memory 194328 kb
Host smart-3b15a5ce-05d4-4884-a8bc-683161d18add
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540018059 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_
all.3540018059
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.238804102
Short name T222
Test name
Test status
Simulation time 340488563149 ps
CPU time 900.73 seconds
Started Mar 26 02:44:52 PM PDT 24
Finished Mar 26 02:59:53 PM PDT 24
Peak memory 204328 kb
Host smart-9599aa5f-9646-40a9-a851-0c59faf89a32
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238804102 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.238804102
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_jump.1999256653
Short name T208
Test name
Test status
Simulation time 412997871 ps
CPU time 0.68 seconds
Started Mar 26 02:44:48 PM PDT 24
Finished Mar 26 02:44:49 PM PDT 24
Peak memory 183520 kb
Host smart-7402d756-299c-4ba4-8e5e-ec8cb51f6605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999256653 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.1999256653
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.3613256475
Short name T204
Test name
Test status
Simulation time 45859413287 ps
CPU time 16.16 seconds
Started Mar 26 02:44:53 PM PDT 24
Finished Mar 26 02:45:09 PM PDT 24
Peak memory 183548 kb
Host smart-83a6a399-8e9b-4fd3-a028-5bb936b35824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613256475 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.3613256475
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.3031965803
Short name T61
Test name
Test status
Simulation time 433408866 ps
CPU time 0.6 seconds
Started Mar 26 02:44:50 PM PDT 24
Finished Mar 26 02:44:51 PM PDT 24
Peak memory 183504 kb
Host smart-d33723ad-9084-45f6-b723-6f66bd7c6522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031965803 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.3031965803
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.1144443642
Short name T157
Test name
Test status
Simulation time 116132015181 ps
CPU time 10.08 seconds
Started Mar 26 02:44:51 PM PDT 24
Finished Mar 26 02:45:01 PM PDT 24
Peak memory 183528 kb
Host smart-9d4b5812-0c1e-4df4-99ae-f7ac99b9a8e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144443642 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_
all.1144443642
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.1054927729
Short name T92
Test name
Test status
Simulation time 56755974094 ps
CPU time 556.72 seconds
Started Mar 26 02:44:48 PM PDT 24
Finished Mar 26 02:54:05 PM PDT 24
Peak memory 198368 kb
Host smart-dd0f7dc4-f069-419e-8ca4-f19a5b1eb69f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054927729 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.1054927729
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.aon_timer_jump.3961248800
Short name T129
Test name
Test status
Simulation time 354637974 ps
CPU time 1.12 seconds
Started Mar 26 02:44:49 PM PDT 24
Finished Mar 26 02:44:50 PM PDT 24
Peak memory 183484 kb
Host smart-c9692502-8169-46b0-af5e-edfcd411fb8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961248800 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.3961248800
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.2147546332
Short name T158
Test name
Test status
Simulation time 13213395492 ps
CPU time 6.15 seconds
Started Mar 26 02:44:50 PM PDT 24
Finished Mar 26 02:44:57 PM PDT 24
Peak memory 191744 kb
Host smart-1189498e-f28b-476a-8b60-bbdc693ec469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147546332 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.2147546332
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.4263614364
Short name T202
Test name
Test status
Simulation time 371923281 ps
CPU time 0.79 seconds
Started Mar 26 02:44:49 PM PDT 24
Finished Mar 26 02:44:50 PM PDT 24
Peak memory 183476 kb
Host smart-6dc5ae8c-e364-48c9-90ed-554c835ed0ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263614364 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.4263614364
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.24194114
Short name T260
Test name
Test status
Simulation time 229272257181 ps
CPU time 368.43 seconds
Started Mar 26 02:44:48 PM PDT 24
Finished Mar 26 02:50:56 PM PDT 24
Peak memory 194496 kb
Host smart-a367824a-44e3-44e5-a7db-ffaa17eee1a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24194114 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_al
l.24194114
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_jump.782583576
Short name T17
Test name
Test status
Simulation time 511871131 ps
CPU time 1.28 seconds
Started Mar 26 02:44:15 PM PDT 24
Finished Mar 26 02:44:16 PM PDT 24
Peak memory 183656 kb
Host smart-e5448086-6483-46de-80c4-87357fefe0a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782583576 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.782583576
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.105145829
Short name T102
Test name
Test status
Simulation time 40097574074 ps
CPU time 61.57 seconds
Started Mar 26 02:44:14 PM PDT 24
Finished Mar 26 02:45:16 PM PDT 24
Peak memory 183508 kb
Host smart-b7259187-bb4e-4fe1-8bab-e15c8a85abc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105145829 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.105145829
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.3491324249
Short name T13
Test name
Test status
Simulation time 8247546915 ps
CPU time 3.74 seconds
Started Mar 26 02:44:16 PM PDT 24
Finished Mar 26 02:44:20 PM PDT 24
Peak memory 215292 kb
Host smart-8de595bd-29ca-435c-8110-8d76d2c6fdac
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491324249 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.3491324249
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.78057925
Short name T273
Test name
Test status
Simulation time 472157594 ps
CPU time 0.64 seconds
Started Mar 26 02:44:22 PM PDT 24
Finished Mar 26 02:44:23 PM PDT 24
Peak memory 183480 kb
Host smart-e97be303-0659-466e-b9bb-e37f9cb8f23d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78057925 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.78057925
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.1909206639
Short name T247
Test name
Test status
Simulation time 198913147888 ps
CPU time 258.38 seconds
Started Mar 26 02:44:22 PM PDT 24
Finished Mar 26 02:48:41 PM PDT 24
Peak memory 194512 kb
Host smart-4b2420f1-fa46-48ea-bb14-250684913098
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909206639 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_a
ll.1909206639
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.2041328141
Short name T62
Test name
Test status
Simulation time 69559830799 ps
CPU time 515.28 seconds
Started Mar 26 02:44:17 PM PDT 24
Finished Mar 26 02:52:52 PM PDT 24
Peak memory 198412 kb
Host smart-6d739204-d61e-41cc-9081-df4c614acb6f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041328141 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.2041328141
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_jump.1209473748
Short name T246
Test name
Test status
Simulation time 500347670 ps
CPU time 1.06 seconds
Started Mar 26 02:44:51 PM PDT 24
Finished Mar 26 02:44:52 PM PDT 24
Peak memory 183492 kb
Host smart-00e9b0f4-3088-4df6-8ebc-09f44669b0c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209473748 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.1209473748
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.1746166257
Short name T255
Test name
Test status
Simulation time 17676764218 ps
CPU time 24.5 seconds
Started Mar 26 02:44:50 PM PDT 24
Finished Mar 26 02:45:14 PM PDT 24
Peak memory 183556 kb
Host smart-adc9c6b8-03bb-45bf-9939-b57860a33891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746166257 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.1746166257
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.1480744484
Short name T141
Test name
Test status
Simulation time 445528482 ps
CPU time 1.3 seconds
Started Mar 26 02:44:50 PM PDT 24
Finished Mar 26 02:44:52 PM PDT 24
Peak memory 183508 kb
Host smart-9454481a-b280-4391-b544-ccbd2d392209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480744484 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.1480744484
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.533400232
Short name T274
Test name
Test status
Simulation time 121539795631 ps
CPU time 47.93 seconds
Started Mar 26 02:44:50 PM PDT 24
Finished Mar 26 02:45:38 PM PDT 24
Peak memory 183648 kb
Host smart-b21643bf-0a8c-469d-a5c7-dd962b2f3906
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533400232 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_a
ll.533400232
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.3000742322
Short name T168
Test name
Test status
Simulation time 30814370473 ps
CPU time 204.92 seconds
Started Mar 26 02:44:49 PM PDT 24
Finished Mar 26 02:48:14 PM PDT 24
Peak memory 198476 kb
Host smart-a89d1070-3f39-452c-856e-d017631f86d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000742322 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.3000742322
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.aon_timer_jump.1659197923
Short name T120
Test name
Test status
Simulation time 524730252 ps
CPU time 0.59 seconds
Started Mar 26 02:44:52 PM PDT 24
Finished Mar 26 02:44:53 PM PDT 24
Peak memory 183428 kb
Host smart-299b4d42-171c-49c9-9ce6-19f96dd84abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659197923 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.1659197923
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.1487126704
Short name T185
Test name
Test status
Simulation time 51991585507 ps
CPU time 86.18 seconds
Started Mar 26 02:44:54 PM PDT 24
Finished Mar 26 02:46:20 PM PDT 24
Peak memory 191740 kb
Host smart-7a6fdc07-2fbb-4b72-8cff-b30419d835e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487126704 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.1487126704
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.108803072
Short name T43
Test name
Test status
Simulation time 502704570 ps
CPU time 1.27 seconds
Started Mar 26 02:44:49 PM PDT 24
Finished Mar 26 02:44:51 PM PDT 24
Peak memory 183672 kb
Host smart-fd1819c2-d133-4fe2-8975-35d0976c7861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108803072 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.108803072
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.2668440632
Short name T10
Test name
Test status
Simulation time 188814472127 ps
CPU time 71.75 seconds
Started Mar 26 02:44:49 PM PDT 24
Finished Mar 26 02:46:01 PM PDT 24
Peak memory 194456 kb
Host smart-6c88e12c-8670-4a79-8c0c-a425823d7bb4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668440632 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_
all.2668440632
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.1888185175
Short name T101
Test name
Test status
Simulation time 108446343658 ps
CPU time 204.89 seconds
Started Mar 26 02:44:51 PM PDT 24
Finished Mar 26 02:48:16 PM PDT 24
Peak memory 198416 kb
Host smart-137bd634-d172-417b-9236-b6ba11a29c34
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888185175 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.1888185175
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.aon_timer_jump.3579499489
Short name T209
Test name
Test status
Simulation time 350085042 ps
CPU time 1.13 seconds
Started Mar 26 02:44:52 PM PDT 24
Finished Mar 26 02:44:54 PM PDT 24
Peak memory 183464 kb
Host smart-66ef99eb-e963-4347-94ea-9c6fa337cc80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579499489 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.3579499489
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.438247139
Short name T228
Test name
Test status
Simulation time 36218493102 ps
CPU time 15.17 seconds
Started Mar 26 02:44:53 PM PDT 24
Finished Mar 26 02:45:08 PM PDT 24
Peak memory 183572 kb
Host smart-a80bcbca-dd20-41bb-9f13-02d0ee75c08e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438247139 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.438247139
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.937639433
Short name T88
Test name
Test status
Simulation time 478133015 ps
CPU time 0.72 seconds
Started Mar 26 02:44:50 PM PDT 24
Finished Mar 26 02:44:51 PM PDT 24
Peak memory 183412 kb
Host smart-8f5ac2c6-2b55-4524-b9de-e92de30c5e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937639433 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.937639433
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.1045351254
Short name T271
Test name
Test status
Simulation time 216080679567 ps
CPU time 29.47 seconds
Started Mar 26 02:44:51 PM PDT 24
Finished Mar 26 02:45:20 PM PDT 24
Peak memory 194496 kb
Host smart-0256579c-0aee-43b0-a9e0-76d09e9a2439
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045351254 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_
all.1045351254
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_jump.311712364
Short name T258
Test name
Test status
Simulation time 486370677 ps
CPU time 1.44 seconds
Started Mar 26 02:44:51 PM PDT 24
Finished Mar 26 02:44:53 PM PDT 24
Peak memory 183504 kb
Host smart-5ce5fe31-4e71-4014-8080-7a32cfcb34e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311712364 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.311712364
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.2768914977
Short name T207
Test name
Test status
Simulation time 26648476061 ps
CPU time 31.36 seconds
Started Mar 26 02:44:52 PM PDT 24
Finished Mar 26 02:45:24 PM PDT 24
Peak memory 183520 kb
Host smart-4c6f7356-ac11-40ba-8450-d9348d1edf7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768914977 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.2768914977
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.2678353055
Short name T227
Test name
Test status
Simulation time 541611596 ps
CPU time 1.38 seconds
Started Mar 26 02:44:52 PM PDT 24
Finished Mar 26 02:44:53 PM PDT 24
Peak memory 183424 kb
Host smart-846f924f-4038-4f7a-ac6e-e48dc7d7ec68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678353055 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.2678353055
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.3946064685
Short name T254
Test name
Test status
Simulation time 57096598118 ps
CPU time 23.95 seconds
Started Mar 26 02:44:51 PM PDT 24
Finished Mar 26 02:45:15 PM PDT 24
Peak memory 183456 kb
Host smart-0ce3d54d-7e77-455e-b993-e5764b057105
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946064685 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_
all.3946064685
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.712029550
Short name T95
Test name
Test status
Simulation time 64149424688 ps
CPU time 155.23 seconds
Started Mar 26 02:44:49 PM PDT 24
Finished Mar 26 02:47:25 PM PDT 24
Peak memory 198516 kb
Host smart-5b1c6af6-dca3-4938-badd-f9669a8b8b59
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712029550 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.712029550
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.aon_timer_jump.3691227149
Short name T110
Test name
Test status
Simulation time 425859558 ps
CPU time 0.92 seconds
Started Mar 26 02:44:51 PM PDT 24
Finished Mar 26 02:44:52 PM PDT 24
Peak memory 183448 kb
Host smart-efdd128d-2f1c-4d6b-920a-0d4dabc80328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691227149 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.3691227149
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.3201130083
Short name T181
Test name
Test status
Simulation time 22904040062 ps
CPU time 32.75 seconds
Started Mar 26 02:44:51 PM PDT 24
Finished Mar 26 02:45:24 PM PDT 24
Peak memory 183448 kb
Host smart-7602712b-d829-422a-8bdf-46b4ea92da98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201130083 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.3201130083
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.3220228065
Short name T198
Test name
Test status
Simulation time 463943928 ps
CPU time 1.26 seconds
Started Mar 26 02:44:51 PM PDT 24
Finished Mar 26 02:44:52 PM PDT 24
Peak memory 183504 kb
Host smart-0dd6b12e-dca5-44b4-8942-cf95f8f45b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220228065 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.3220228065
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.3047362883
Short name T20
Test name
Test status
Simulation time 428136250863 ps
CPU time 109.06 seconds
Started Mar 26 02:44:53 PM PDT 24
Finished Mar 26 02:46:42 PM PDT 24
Peak memory 183548 kb
Host smart-b96c3b03-88c5-48dd-ae22-288b1e02588e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047362883 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_
all.3047362883
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/35.aon_timer_jump.969792204
Short name T166
Test name
Test status
Simulation time 450451271 ps
CPU time 0.75 seconds
Started Mar 26 02:44:50 PM PDT 24
Finished Mar 26 02:44:51 PM PDT 24
Peak memory 183500 kb
Host smart-0f82e3a5-abae-46c3-8d92-4b9ff3f3c622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969792204 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.969792204
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.2371271415
Short name T140
Test name
Test status
Simulation time 19008014878 ps
CPU time 25.56 seconds
Started Mar 26 02:44:51 PM PDT 24
Finished Mar 26 02:45:17 PM PDT 24
Peak memory 191712 kb
Host smart-c0e9c005-f120-4bf0-b173-8f0c332ee984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371271415 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.2371271415
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.2561349467
Short name T147
Test name
Test status
Simulation time 406838256 ps
CPU time 0.87 seconds
Started Mar 26 02:44:54 PM PDT 24
Finished Mar 26 02:44:55 PM PDT 24
Peak memory 183480 kb
Host smart-cd594fc2-7ced-4e25-85fd-fa766e6fa84d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561349467 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.2561349467
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.3409205304
Short name T182
Test name
Test status
Simulation time 64969110063 ps
CPU time 88.2 seconds
Started Mar 26 02:45:05 PM PDT 24
Finished Mar 26 02:46:33 PM PDT 24
Peak memory 183716 kb
Host smart-69712014-fc96-4143-bfc8-fb9cec13921f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409205304 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_
all.3409205304
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_jump.4016104091
Short name T269
Test name
Test status
Simulation time 472547649 ps
CPU time 0.92 seconds
Started Mar 26 02:45:03 PM PDT 24
Finished Mar 26 02:45:04 PM PDT 24
Peak memory 183492 kb
Host smart-9d151ec6-210f-4570-89ba-caac918e35ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016104091 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.4016104091
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.2395894606
Short name T262
Test name
Test status
Simulation time 53828764276 ps
CPU time 82.61 seconds
Started Mar 26 02:45:04 PM PDT 24
Finished Mar 26 02:46:26 PM PDT 24
Peak memory 191760 kb
Host smart-3110b16a-bd33-48da-a11c-9a287c66ff3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395894606 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.2395894606
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.1928517607
Short name T214
Test name
Test status
Simulation time 577318378 ps
CPU time 0.78 seconds
Started Mar 26 02:45:16 PM PDT 24
Finished Mar 26 02:45:17 PM PDT 24
Peak memory 183444 kb
Host smart-a5637b1a-9875-45df-afc4-34570bb63b9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928517607 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.1928517607
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.3908007511
Short name T221
Test name
Test status
Simulation time 75759468092 ps
CPU time 29.15 seconds
Started Mar 26 02:45:08 PM PDT 24
Finished Mar 26 02:45:37 PM PDT 24
Peak memory 194148 kb
Host smart-824701bc-dbcd-4fbb-99db-e8f447f5c84e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908007511 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_
all.3908007511
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.1332907565
Short name T99
Test name
Test status
Simulation time 66151303594 ps
CPU time 120.73 seconds
Started Mar 26 02:45:03 PM PDT 24
Finished Mar 26 02:47:03 PM PDT 24
Peak memory 198392 kb
Host smart-cc3a0c74-c33c-485f-a6d2-fcc147f38682
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332907565 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.1332907565
Directory /workspace/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.aon_timer_jump.3702173731
Short name T183
Test name
Test status
Simulation time 383185092 ps
CPU time 0.83 seconds
Started Mar 26 02:45:03 PM PDT 24
Finished Mar 26 02:45:04 PM PDT 24
Peak memory 183480 kb
Host smart-95ed6820-edd5-4ef3-92d3-78b643bdaf87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702173731 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.3702173731
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.1727093367
Short name T45
Test name
Test status
Simulation time 8466718440 ps
CPU time 2.43 seconds
Started Mar 26 02:45:05 PM PDT 24
Finished Mar 26 02:45:08 PM PDT 24
Peak memory 191756 kb
Host smart-1ff9620c-09ff-42c0-9673-27fb12bf90f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727093367 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.1727093367
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.3191263455
Short name T243
Test name
Test status
Simulation time 506364806 ps
CPU time 1.32 seconds
Started Mar 26 02:45:05 PM PDT 24
Finished Mar 26 02:45:06 PM PDT 24
Peak memory 183484 kb
Host smart-e1651559-505b-420a-870e-4d742c82b1f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191263455 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.3191263455
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.2558088015
Short name T178
Test name
Test status
Simulation time 173269013618 ps
CPU time 65.12 seconds
Started Mar 26 02:45:05 PM PDT 24
Finished Mar 26 02:46:10 PM PDT 24
Peak memory 183812 kb
Host smart-e71a2322-6e70-4d64-a2b2-4d3106a55be5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558088015 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_
all.2558088015
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.2023635361
Short name T90
Test name
Test status
Simulation time 416788343133 ps
CPU time 1003.62 seconds
Started Mar 26 02:45:04 PM PDT 24
Finished Mar 26 03:01:47 PM PDT 24
Peak memory 204708 kb
Host smart-a6f24d57-ab45-4794-904a-b4752eaf9aad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023635361 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.2023635361
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.aon_timer_jump.3243664497
Short name T108
Test name
Test status
Simulation time 422470795 ps
CPU time 0.72 seconds
Started Mar 26 02:45:04 PM PDT 24
Finished Mar 26 02:45:05 PM PDT 24
Peak memory 183520 kb
Host smart-a440573a-cfa7-4f37-aa14-2da4031d4132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243664497 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.3243664497
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.2636375454
Short name T171
Test name
Test status
Simulation time 43805363007 ps
CPU time 75.76 seconds
Started Mar 26 02:45:07 PM PDT 24
Finished Mar 26 02:46:22 PM PDT 24
Peak memory 183484 kb
Host smart-c5a63a35-bc8e-4040-b978-54371a1b67e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636375454 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.2636375454
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.2761764640
Short name T161
Test name
Test status
Simulation time 368695996 ps
CPU time 1.08 seconds
Started Mar 26 02:45:05 PM PDT 24
Finished Mar 26 02:45:06 PM PDT 24
Peak memory 183432 kb
Host smart-f4c54fff-80c5-496f-9806-c10fdecd87f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761764640 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.2761764640
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.2978975556
Short name T191
Test name
Test status
Simulation time 51776267467 ps
CPU time 16.71 seconds
Started Mar 26 02:45:04 PM PDT 24
Finished Mar 26 02:45:21 PM PDT 24
Peak memory 183460 kb
Host smart-56f7a715-b15d-4a67-bb18-3edef559902e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978975556 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_
all.2978975556
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.3038565589
Short name T37
Test name
Test status
Simulation time 22826068366 ps
CPU time 183.65 seconds
Started Mar 26 02:45:06 PM PDT 24
Finished Mar 26 02:48:09 PM PDT 24
Peak memory 198480 kb
Host smart-0393f9d5-40bf-4a53-820a-6e4157208b0f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038565589 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand_reset.3038565589
Directory /workspace/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.aon_timer_jump.3030167681
Short name T165
Test name
Test status
Simulation time 501675756 ps
CPU time 0.75 seconds
Started Mar 26 02:45:05 PM PDT 24
Finished Mar 26 02:45:06 PM PDT 24
Peak memory 183496 kb
Host smart-a816095f-63e5-4451-a5de-71031e3f754a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030167681 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.3030167681
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.2782424845
Short name T7
Test name
Test status
Simulation time 4799449562 ps
CPU time 4.37 seconds
Started Mar 26 02:45:06 PM PDT 24
Finished Mar 26 02:45:10 PM PDT 24
Peak memory 183548 kb
Host smart-153c445e-0e90-4f0c-9ee3-d38b62cb18c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782424845 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.2782424845
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.1125591573
Short name T153
Test name
Test status
Simulation time 371691503 ps
CPU time 0.74 seconds
Started Mar 26 02:45:06 PM PDT 24
Finished Mar 26 02:45:07 PM PDT 24
Peak memory 183460 kb
Host smart-d1adfa03-d771-4aa8-913e-792ea0bdbef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125591573 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.1125591573
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.3669300375
Short name T130
Test name
Test status
Simulation time 138488493694 ps
CPU time 11.34 seconds
Started Mar 26 02:45:04 PM PDT 24
Finished Mar 26 02:45:15 PM PDT 24
Peak memory 194024 kb
Host smart-c501ff87-b147-4c5b-b7fa-aadaa3ca2b63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669300375 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_
all.3669300375
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.1541132210
Short name T233
Test name
Test status
Simulation time 50982401798 ps
CPU time 231.59 seconds
Started Mar 26 02:45:02 PM PDT 24
Finished Mar 26 02:48:54 PM PDT 24
Peak memory 198364 kb
Host smart-a68f517b-dd90-423a-af67-47ff4b5f012c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541132210 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.1541132210
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_jump.626218241
Short name T49
Test name
Test status
Simulation time 426763288 ps
CPU time 1.31 seconds
Started Mar 26 02:44:14 PM PDT 24
Finished Mar 26 02:44:15 PM PDT 24
Peak memory 183436 kb
Host smart-63197d09-7465-4890-97bb-41d20dca318f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626218241 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.626218241
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.4176301836
Short name T159
Test name
Test status
Simulation time 15173729527 ps
CPU time 6.67 seconds
Started Mar 26 02:44:15 PM PDT 24
Finished Mar 26 02:44:21 PM PDT 24
Peak memory 183568 kb
Host smart-987f7efb-0ef2-42df-97c1-425bfe819a38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176301836 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.4176301836
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.783445178
Short name T12
Test name
Test status
Simulation time 3916858021 ps
CPU time 6.18 seconds
Started Mar 26 02:44:16 PM PDT 24
Finished Mar 26 02:44:23 PM PDT 24
Peak memory 214792 kb
Host smart-e4745605-397d-4aed-a60b-b4d6dc97b540
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783445178 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.783445178
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.3064979739
Short name T44
Test name
Test status
Simulation time 501669058 ps
CPU time 1.27 seconds
Started Mar 26 02:44:15 PM PDT 24
Finished Mar 26 02:44:17 PM PDT 24
Peak memory 183512 kb
Host smart-7e497d11-1d04-4af7-890d-d933718e9a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064979739 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.3064979739
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.3064862241
Short name T242
Test name
Test status
Simulation time 115143637622 ps
CPU time 85.62 seconds
Started Mar 26 02:44:27 PM PDT 24
Finished Mar 26 02:45:53 PM PDT 24
Peak memory 183528 kb
Host smart-5ffc6098-dddf-480d-9447-076a71f5467e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064862241 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_a
ll.3064862241
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.1279572499
Short name T122
Test name
Test status
Simulation time 76476701793 ps
CPU time 205.75 seconds
Started Mar 26 02:44:15 PM PDT 24
Finished Mar 26 02:47:41 PM PDT 24
Peak memory 198472 kb
Host smart-791e337a-e758-4763-962c-6ab2b1738f44
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279572499 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.1279572499
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.aon_timer_jump.1239533128
Short name T232
Test name
Test status
Simulation time 400341599 ps
CPU time 0.69 seconds
Started Mar 26 02:45:05 PM PDT 24
Finished Mar 26 02:45:06 PM PDT 24
Peak memory 183400 kb
Host smart-712fe340-3bec-45c9-a538-25862b2a5118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239533128 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.1239533128
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.3464776750
Short name T197
Test name
Test status
Simulation time 27934890160 ps
CPU time 4 seconds
Started Mar 26 02:45:06 PM PDT 24
Finished Mar 26 02:45:10 PM PDT 24
Peak memory 183544 kb
Host smart-cb019090-4d75-4026-af2e-800b303352b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464776750 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.3464776750
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.2824882677
Short name T119
Test name
Test status
Simulation time 490504539 ps
CPU time 0.81 seconds
Started Mar 26 02:45:06 PM PDT 24
Finished Mar 26 02:45:07 PM PDT 24
Peak memory 183440 kb
Host smart-294c4d4d-8fd6-46b8-8f6b-710d565d84c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824882677 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.2824882677
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.4079280650
Short name T237
Test name
Test status
Simulation time 383516193133 ps
CPU time 678.24 seconds
Started Mar 26 02:45:07 PM PDT 24
Finished Mar 26 02:56:26 PM PDT 24
Peak memory 193656 kb
Host smart-369fb1d3-31c6-4c84-81ad-815ce589f20f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079280650 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_
all.4079280650
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_jump.2896052045
Short name T276
Test name
Test status
Simulation time 529538732 ps
CPU time 1.14 seconds
Started Mar 26 02:45:06 PM PDT 24
Finished Mar 26 02:45:07 PM PDT 24
Peak memory 183516 kb
Host smart-dfbbc05e-8f91-408d-bb6b-27994ee18e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896052045 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.2896052045
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.1584758075
Short name T256
Test name
Test status
Simulation time 22746933381 ps
CPU time 3.32 seconds
Started Mar 26 02:45:05 PM PDT 24
Finished Mar 26 02:45:09 PM PDT 24
Peak memory 191748 kb
Host smart-7cc1bdaa-b870-446c-a9c1-a22b5274f0b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584758075 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.1584758075
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.2235959905
Short name T149
Test name
Test status
Simulation time 402179270 ps
CPU time 0.64 seconds
Started Mar 26 02:45:05 PM PDT 24
Finished Mar 26 02:45:06 PM PDT 24
Peak memory 183396 kb
Host smart-e3bf0794-82d9-49a8-a78b-dbea51cf069f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235959905 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.2235959905
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.3998927371
Short name T248
Test name
Test status
Simulation time 117949734142 ps
CPU time 444.58 seconds
Started Mar 26 02:45:05 PM PDT 24
Finished Mar 26 02:52:29 PM PDT 24
Peak memory 198372 kb
Host smart-921dea28-b7d2-4cbb-97be-f851c447f036
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998927371 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.3998927371
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.aon_timer_jump.2621384174
Short name T24
Test name
Test status
Simulation time 575604919 ps
CPU time 1.57 seconds
Started Mar 26 02:45:06 PM PDT 24
Finished Mar 26 02:45:08 PM PDT 24
Peak memory 183504 kb
Host smart-2d3580b4-bfb4-47f5-8257-9a9e5b88bf0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621384174 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.2621384174
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.1728085170
Short name T164
Test name
Test status
Simulation time 38843893841 ps
CPU time 16.02 seconds
Started Mar 26 02:45:09 PM PDT 24
Finished Mar 26 02:45:25 PM PDT 24
Peak memory 183540 kb
Host smart-adb9ff73-663b-4fab-af0c-285de3dde30e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728085170 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.1728085170
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.2874392867
Short name T26
Test name
Test status
Simulation time 367099756 ps
CPU time 1.11 seconds
Started Mar 26 02:45:04 PM PDT 24
Finished Mar 26 02:45:05 PM PDT 24
Peak memory 183496 kb
Host smart-4473776c-32b9-46de-9a35-978c894b5a64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874392867 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.2874392867
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.628771493
Short name T174
Test name
Test status
Simulation time 154975212060 ps
CPU time 223.96 seconds
Started Mar 26 02:45:06 PM PDT 24
Finished Mar 26 02:48:50 PM PDT 24
Peak memory 193848 kb
Host smart-2d075b55-e34e-4ca2-b845-829f81c4f4d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628771493 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_a
ll.628771493
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.3182973531
Short name T35
Test name
Test status
Simulation time 105642015359 ps
CPU time 218.6 seconds
Started Mar 26 02:45:04 PM PDT 24
Finished Mar 26 02:48:43 PM PDT 24
Peak memory 198448 kb
Host smart-8f31b90b-23f9-47ef-bf89-7b4fcddffec5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182973531 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.3182973531
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.aon_timer_jump.3140921187
Short name T48
Test name
Test status
Simulation time 481377685 ps
CPU time 0.73 seconds
Started Mar 26 02:45:04 PM PDT 24
Finished Mar 26 02:45:05 PM PDT 24
Peak memory 183420 kb
Host smart-e17f7c1a-338a-41d3-aa87-bd1b95cd1c77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140921187 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.3140921187
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.1831018909
Short name T277
Test name
Test status
Simulation time 5384011150 ps
CPU time 2.09 seconds
Started Mar 26 02:45:08 PM PDT 24
Finished Mar 26 02:45:10 PM PDT 24
Peak memory 191740 kb
Host smart-0c4e44dc-40dc-42bd-a8ca-8cac80937010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831018909 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.1831018909
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.1964074595
Short name T112
Test name
Test status
Simulation time 577685792 ps
CPU time 1.41 seconds
Started Mar 26 02:45:09 PM PDT 24
Finished Mar 26 02:45:11 PM PDT 24
Peak memory 183476 kb
Host smart-056a93ef-d479-4698-8a2c-5705b9869f3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964074595 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.1964074595
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.1271982309
Short name T137
Test name
Test status
Simulation time 170700295615 ps
CPU time 128.02 seconds
Started Mar 26 02:45:04 PM PDT 24
Finished Mar 26 02:47:13 PM PDT 24
Peak memory 183536 kb
Host smart-32d0070a-91d7-4463-a65f-c273fc6faa49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271982309 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_
all.1271982309
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.2452529824
Short name T39
Test name
Test status
Simulation time 129675956464 ps
CPU time 355.84 seconds
Started Mar 26 02:45:04 PM PDT 24
Finished Mar 26 02:51:00 PM PDT 24
Peak memory 206636 kb
Host smart-ba1001d0-b6b9-4088-972f-fbd4ef76282c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452529824 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.2452529824
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.aon_timer_jump.3298886117
Short name T143
Test name
Test status
Simulation time 512945588 ps
CPU time 0.72 seconds
Started Mar 26 02:45:03 PM PDT 24
Finished Mar 26 02:45:04 PM PDT 24
Peak memory 183492 kb
Host smart-1b54c16d-81d2-479f-a18e-1b755091f80e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298886117 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.3298886117
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.3563136504
Short name T115
Test name
Test status
Simulation time 51622430029 ps
CPU time 26.37 seconds
Started Mar 26 02:45:04 PM PDT 24
Finished Mar 26 02:45:31 PM PDT 24
Peak memory 183532 kb
Host smart-6f20a9ef-a466-4664-a4c8-1765a2e83b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563136504 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.3563136504
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.218876011
Short name T238
Test name
Test status
Simulation time 428845056 ps
CPU time 1.17 seconds
Started Mar 26 02:45:04 PM PDT 24
Finished Mar 26 02:45:06 PM PDT 24
Peak memory 183472 kb
Host smart-5081e520-7ddd-4a6a-8818-4a4b7566745c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218876011 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.218876011
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.3969203886
Short name T155
Test name
Test status
Simulation time 246349542762 ps
CPU time 400.26 seconds
Started Mar 26 02:45:08 PM PDT 24
Finished Mar 26 02:51:48 PM PDT 24
Peak memory 183552 kb
Host smart-f49bf805-3be2-4cae-894c-728abba919d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969203886 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_
all.3969203886
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.2571653922
Short name T265
Test name
Test status
Simulation time 66369336991 ps
CPU time 136.94 seconds
Started Mar 26 02:45:08 PM PDT 24
Finished Mar 26 02:47:25 PM PDT 24
Peak memory 198376 kb
Host smart-88c767ca-f3f3-4acf-bab0-7c7f0138e5d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571653922 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.2571653922
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.aon_timer_jump.3225259257
Short name T268
Test name
Test status
Simulation time 591838046 ps
CPU time 1.01 seconds
Started Mar 26 02:45:05 PM PDT 24
Finished Mar 26 02:45:06 PM PDT 24
Peak memory 183508 kb
Host smart-4e09538e-7811-4689-9d30-0c346a950787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225259257 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.3225259257
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.2830648588
Short name T128
Test name
Test status
Simulation time 13772201038 ps
CPU time 11.96 seconds
Started Mar 26 02:45:04 PM PDT 24
Finished Mar 26 02:45:16 PM PDT 24
Peak memory 183532 kb
Host smart-bc20c1b7-b470-4f52-8b4d-aa06952a0046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830648588 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.2830648588
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.4973390
Short name T170
Test name
Test status
Simulation time 490558007 ps
CPU time 0.84 seconds
Started Mar 26 02:45:08 PM PDT 24
Finished Mar 26 02:45:09 PM PDT 24
Peak memory 183536 kb
Host smart-bc72c054-9436-42e0-b655-c19bf28c1af3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4973390 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.4973390
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.1848140715
Short name T267
Test name
Test status
Simulation time 351197567252 ps
CPU time 131.57 seconds
Started Mar 26 02:45:08 PM PDT 24
Finished Mar 26 02:47:20 PM PDT 24
Peak memory 195412 kb
Host smart-d5346d26-f729-4b7e-8f57-cb79fee4cb18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848140715 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_
all.1848140715
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.4258659361
Short name T225
Test name
Test status
Simulation time 129206817667 ps
CPU time 212.42 seconds
Started Mar 26 02:45:04 PM PDT 24
Finished Mar 26 02:48:37 PM PDT 24
Peak memory 198452 kb
Host smart-0413fb25-f739-4c35-9e1f-7a026c7ec9a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258659361 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.4258659361
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.aon_timer_jump.2686422117
Short name T107
Test name
Test status
Simulation time 366011484 ps
CPU time 1.14 seconds
Started Mar 26 02:45:06 PM PDT 24
Finished Mar 26 02:45:07 PM PDT 24
Peak memory 183492 kb
Host smart-935dac91-4207-43b2-8994-857fdf3ed145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686422117 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.2686422117
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.2190926762
Short name T86
Test name
Test status
Simulation time 23046880558 ps
CPU time 18.53 seconds
Started Mar 26 02:45:08 PM PDT 24
Finished Mar 26 02:45:27 PM PDT 24
Peak memory 191600 kb
Host smart-14a78356-7f0f-4017-9828-dbf97ecbfd0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190926762 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.2190926762
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.1487025221
Short name T139
Test name
Test status
Simulation time 393687884 ps
CPU time 0.7 seconds
Started Mar 26 02:45:05 PM PDT 24
Finished Mar 26 02:45:06 PM PDT 24
Peak memory 183420 kb
Host smart-a45ba044-0dc4-41d7-805f-5752d3eec24d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487025221 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.1487025221
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.1459099973
Short name T215
Test name
Test status
Simulation time 67823037129 ps
CPU time 114.16 seconds
Started Mar 26 02:45:06 PM PDT 24
Finished Mar 26 02:47:01 PM PDT 24
Peak memory 194356 kb
Host smart-d86c82fc-e45f-44df-83f1-8b837c6afeca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459099973 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_
all.1459099973
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_jump.2747294065
Short name T46
Test name
Test status
Simulation time 357031385 ps
CPU time 0.82 seconds
Started Mar 26 02:45:06 PM PDT 24
Finished Mar 26 02:45:07 PM PDT 24
Peak memory 183444 kb
Host smart-758d12be-660e-4196-b885-865f2522117f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747294065 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.2747294065
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.4017815906
Short name T266
Test name
Test status
Simulation time 40924299856 ps
CPU time 16.54 seconds
Started Mar 26 02:45:09 PM PDT 24
Finished Mar 26 02:45:26 PM PDT 24
Peak memory 183568 kb
Host smart-58c0c3e2-33aa-431a-8052-f5b5e240cc49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017815906 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.4017815906
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.547459285
Short name T125
Test name
Test status
Simulation time 409388585 ps
CPU time 0.68 seconds
Started Mar 26 02:45:09 PM PDT 24
Finished Mar 26 02:45:09 PM PDT 24
Peak memory 183508 kb
Host smart-56d4cd27-63f5-483d-b326-50de81a3c26d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547459285 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.547459285
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.1565716903
Short name T219
Test name
Test status
Simulation time 43505082460 ps
CPU time 16.99 seconds
Started Mar 26 02:45:05 PM PDT 24
Finished Mar 26 02:45:22 PM PDT 24
Peak memory 183564 kb
Host smart-784e537b-68ee-48ec-8148-727bf7a17277
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565716903 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_
all.1565716903
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.1885723522
Short name T91
Test name
Test status
Simulation time 72869168519 ps
CPU time 807.89 seconds
Started Mar 26 02:45:09 PM PDT 24
Finished Mar 26 02:58:37 PM PDT 24
Peak memory 201276 kb
Host smart-bbf792eb-9378-4e5b-9c2a-c9c9a029eb60
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885723522 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.1885723522
Directory /workspace/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_jump.3736766307
Short name T210
Test name
Test status
Simulation time 455825420 ps
CPU time 0.71 seconds
Started Mar 26 02:45:06 PM PDT 24
Finished Mar 26 02:45:06 PM PDT 24
Peak memory 183496 kb
Host smart-f6c8f39b-c822-48b5-88fa-8c55e8807754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736766307 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.3736766307
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.3282329212
Short name T194
Test name
Test status
Simulation time 30971028076 ps
CPU time 12.87 seconds
Started Mar 26 02:45:06 PM PDT 24
Finished Mar 26 02:45:19 PM PDT 24
Peak memory 191684 kb
Host smart-19ab4447-3e63-4c01-8a9a-be879a0c507c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282329212 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.3282329212
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.1052911673
Short name T223
Test name
Test status
Simulation time 470174784 ps
CPU time 0.94 seconds
Started Mar 26 02:45:06 PM PDT 24
Finished Mar 26 02:45:07 PM PDT 24
Peak memory 183484 kb
Host smart-74487e68-0bc3-4782-8e38-6820640d175f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052911673 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.1052911673
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.676580671
Short name T152
Test name
Test status
Simulation time 198861725662 ps
CPU time 307.29 seconds
Started Mar 26 02:45:08 PM PDT 24
Finished Mar 26 02:50:16 PM PDT 24
Peak memory 183728 kb
Host smart-c26073a4-8093-496e-9cdc-0da5247c35d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676580671 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_a
ll.676580671
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.2563272733
Short name T52
Test name
Test status
Simulation time 22624989578 ps
CPU time 153.8 seconds
Started Mar 26 02:45:09 PM PDT 24
Finished Mar 26 02:47:43 PM PDT 24
Peak memory 198452 kb
Host smart-d2cb0e89-0a3c-4f20-8786-95abb0eaedda
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563272733 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.2563272733
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.aon_timer_jump.1062240978
Short name T114
Test name
Test status
Simulation time 522080807 ps
CPU time 1.15 seconds
Started Mar 26 02:45:05 PM PDT 24
Finished Mar 26 02:45:06 PM PDT 24
Peak memory 183488 kb
Host smart-bef63be5-0245-4e02-8194-52736b808e6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062240978 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.1062240978
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.4073691076
Short name T18
Test name
Test status
Simulation time 41111583074 ps
CPU time 64.06 seconds
Started Mar 26 02:45:06 PM PDT 24
Finished Mar 26 02:46:11 PM PDT 24
Peak memory 183440 kb
Host smart-e0d82b73-a5c6-49c6-9942-57ba600637bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073691076 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.4073691076
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.3581665883
Short name T123
Test name
Test status
Simulation time 460717591 ps
CPU time 0.99 seconds
Started Mar 26 02:45:09 PM PDT 24
Finished Mar 26 02:45:10 PM PDT 24
Peak memory 183508 kb
Host smart-f6f20429-77cf-4ba3-bafb-4cc3a5e65c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581665883 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.3581665883
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.2089258916
Short name T116
Test name
Test status
Simulation time 158515778932 ps
CPU time 59.75 seconds
Started Mar 26 02:45:09 PM PDT 24
Finished Mar 26 02:46:09 PM PDT 24
Peak memory 183548 kb
Host smart-f117321c-53c5-480b-9715-1943ff41f4a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089258916 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_
all.2089258916
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.702699426
Short name T245
Test name
Test status
Simulation time 381061815067 ps
CPU time 436.32 seconds
Started Mar 26 02:45:05 PM PDT 24
Finished Mar 26 02:52:22 PM PDT 24
Peak memory 198392 kb
Host smart-7a9b9d85-fb97-4f48-a3f9-770984bf4c03
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702699426 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.702699426
Directory /workspace/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.aon_timer_jump.2254770092
Short name T240
Test name
Test status
Simulation time 567474734 ps
CPU time 0.73 seconds
Started Mar 26 02:44:15 PM PDT 24
Finished Mar 26 02:44:16 PM PDT 24
Peak memory 183424 kb
Host smart-f87d7033-0be5-4fb4-b716-52cb8f1b0df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254770092 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.2254770092
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.2624154623
Short name T275
Test name
Test status
Simulation time 26855119562 ps
CPU time 9.33 seconds
Started Mar 26 02:44:14 PM PDT 24
Finished Mar 26 02:44:23 PM PDT 24
Peak memory 183548 kb
Host smart-5598e963-b716-4909-9f01-3fa61c76da2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624154623 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.2624154623
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.313310773
Short name T193
Test name
Test status
Simulation time 423767805 ps
CPU time 1.14 seconds
Started Mar 26 02:44:14 PM PDT 24
Finished Mar 26 02:44:15 PM PDT 24
Peak memory 183500 kb
Host smart-fca00089-62d9-48bb-9d95-416fbfdff095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313310773 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.313310773
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.579734765
Short name T42
Test name
Test status
Simulation time 101866040612 ps
CPU time 27.82 seconds
Started Mar 26 02:44:32 PM PDT 24
Finished Mar 26 02:44:59 PM PDT 24
Peak memory 183524 kb
Host smart-c44bb358-d589-40e7-baff-a761c1f78358
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579734765 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_al
l.579734765
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.372627725
Short name T100
Test name
Test status
Simulation time 11318655438 ps
CPU time 82.91 seconds
Started Mar 26 02:44:18 PM PDT 24
Finished Mar 26 02:45:41 PM PDT 24
Peak memory 198328 kb
Host smart-ded47fc7-4f07-4198-b883-90613137fc2d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372627725 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.372627725
Directory /workspace/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.aon_timer_jump.463959931
Short name T47
Test name
Test status
Simulation time 624956625 ps
CPU time 0.81 seconds
Started Mar 26 02:44:29 PM PDT 24
Finished Mar 26 02:44:30 PM PDT 24
Peak memory 183480 kb
Host smart-ecbe0881-7cd1-4b31-bd1d-e80e48e56f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463959931 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.463959931
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.3264172819
Short name T205
Test name
Test status
Simulation time 15640993754 ps
CPU time 6.53 seconds
Started Mar 26 02:44:31 PM PDT 24
Finished Mar 26 02:44:37 PM PDT 24
Peak memory 183432 kb
Host smart-45c6567b-1800-4d5a-82ae-1ff44b5cf13e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264172819 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.3264172819
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.1634321270
Short name T156
Test name
Test status
Simulation time 536200731 ps
CPU time 0.74 seconds
Started Mar 26 02:44:30 PM PDT 24
Finished Mar 26 02:44:31 PM PDT 24
Peak memory 183484 kb
Host smart-88e539fb-44a7-45c6-8fcf-9d834e62fc0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634321270 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.1634321270
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.2349060755
Short name T195
Test name
Test status
Simulation time 83974647289 ps
CPU time 127.66 seconds
Started Mar 26 02:44:31 PM PDT 24
Finished Mar 26 02:46:39 PM PDT 24
Peak memory 183516 kb
Host smart-09fcb966-1176-4afe-a71e-6ce672e9fc2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349060755 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_a
ll.2349060755
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.1339911248
Short name T22
Test name
Test status
Simulation time 47036853571 ps
CPU time 251.32 seconds
Started Mar 26 02:44:31 PM PDT 24
Finished Mar 26 02:48:43 PM PDT 24
Peak memory 198448 kb
Host smart-ba94e8d3-2db8-4377-bf51-b96b6fabd632
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339911248 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.1339911248
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.aon_timer_jump.2338603193
Short name T151
Test name
Test status
Simulation time 586341164 ps
CPU time 0.77 seconds
Started Mar 26 02:44:28 PM PDT 24
Finished Mar 26 02:44:29 PM PDT 24
Peak memory 183456 kb
Host smart-2fe3bf37-199b-4492-8173-a09b52b15574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338603193 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.2338603193
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.4030183316
Short name T134
Test name
Test status
Simulation time 8236391946 ps
CPU time 14.58 seconds
Started Mar 26 02:44:28 PM PDT 24
Finished Mar 26 02:44:42 PM PDT 24
Peak memory 183448 kb
Host smart-23a6e49c-9070-43e2-8e2a-d5317de493e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030183316 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.4030183316
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.3256682473
Short name T201
Test name
Test status
Simulation time 520379517 ps
CPU time 0.75 seconds
Started Mar 26 02:44:34 PM PDT 24
Finished Mar 26 02:44:35 PM PDT 24
Peak memory 183488 kb
Host smart-2fe9811d-5323-4f5c-94ad-76bede37820b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256682473 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.3256682473
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.3213255688
Short name T212
Test name
Test status
Simulation time 202358055099 ps
CPU time 58.79 seconds
Started Mar 26 02:44:27 PM PDT 24
Finished Mar 26 02:45:25 PM PDT 24
Peak memory 195572 kb
Host smart-59251401-0f27-42f2-9b73-7bdd4eb6e196
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213255688 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_a
ll.3213255688
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.3664881227
Short name T279
Test name
Test status
Simulation time 23658171151 ps
CPU time 254.48 seconds
Started Mar 26 02:44:28 PM PDT 24
Finished Mar 26 02:48:42 PM PDT 24
Peak memory 198432 kb
Host smart-92e3c07a-8164-4d7a-abfc-12ce286ecb9d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664881227 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.3664881227
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.aon_timer_jump.1435987862
Short name T270
Test name
Test status
Simulation time 567943168 ps
CPU time 0.74 seconds
Started Mar 26 02:44:30 PM PDT 24
Finished Mar 26 02:44:31 PM PDT 24
Peak memory 183492 kb
Host smart-0c8ba7ff-2a29-41f9-bd2d-13ec4ecbbaed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435987862 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.1435987862
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.1495189937
Short name T241
Test name
Test status
Simulation time 9777325029 ps
CPU time 8.2 seconds
Started Mar 26 02:44:26 PM PDT 24
Finished Mar 26 02:44:35 PM PDT 24
Peak memory 183576 kb
Host smart-5efb4585-48df-4bd9-8f47-8c1f6ccdc8f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495189937 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.1495189937
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.370328865
Short name T251
Test name
Test status
Simulation time 470899794 ps
CPU time 0.75 seconds
Started Mar 26 02:44:29 PM PDT 24
Finished Mar 26 02:44:30 PM PDT 24
Peak memory 183500 kb
Host smart-e6adad3f-a9d1-489c-a3cb-6764a50a7042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370328865 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.370328865
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.2348937091
Short name T54
Test name
Test status
Simulation time 77047157745 ps
CPU time 119.87 seconds
Started Mar 26 02:44:29 PM PDT 24
Finished Mar 26 02:46:29 PM PDT 24
Peak memory 183552 kb
Host smart-5811764e-38a8-46f1-b085-db95709c4f02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348937091 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_a
ll.2348937091
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.134131240
Short name T97
Test name
Test status
Simulation time 35870570349 ps
CPU time 134.41 seconds
Started Mar 26 02:44:29 PM PDT 24
Finished Mar 26 02:46:43 PM PDT 24
Peak memory 198328 kb
Host smart-bdf3d0c5-910b-42ef-8184-4c37b35b27c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134131240 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.134131240
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.aon_timer_jump.4107436124
Short name T173
Test name
Test status
Simulation time 468111562 ps
CPU time 0.73 seconds
Started Mar 26 02:44:31 PM PDT 24
Finished Mar 26 02:44:32 PM PDT 24
Peak memory 183508 kb
Host smart-bcc24076-7bf8-4df6-b68c-94281cf9b0ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107436124 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.4107436124
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.1530598152
Short name T132
Test name
Test status
Simulation time 12883443866 ps
CPU time 10.06 seconds
Started Mar 26 02:44:33 PM PDT 24
Finished Mar 26 02:44:43 PM PDT 24
Peak memory 183444 kb
Host smart-1e2da4ae-b53e-44a8-88bc-da893d64b4ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530598152 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.1530598152
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.3338922861
Short name T162
Test name
Test status
Simulation time 564859327 ps
CPU time 1.48 seconds
Started Mar 26 02:44:29 PM PDT 24
Finished Mar 26 02:44:31 PM PDT 24
Peak memory 183420 kb
Host smart-51f1dbc4-e802-4a15-bb53-fb29475f45da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338922861 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.3338922861
Directory /workspace/9.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.68760367
Short name T184
Test name
Test status
Simulation time 114352518886 ps
CPU time 87.48 seconds
Started Mar 26 02:44:29 PM PDT 24
Finished Mar 26 02:45:57 PM PDT 24
Peak memory 183460 kb
Host smart-69a98714-f006-4842-a8c9-0d5d0d3a966f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68760367 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all
.68760367
Directory /workspace/9.aon_timer_stress_all/latest
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