Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
92.98 99.25 93.67 100.00 98.40 99.51 67.06


Total test records in report: 426
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T287 /workspace/coverage/default/29.aon_timer_stress_all.1615012472 Mar 28 12:48:24 PM PDT 24 Mar 28 12:49:41 PM PDT 24 94993718964 ps
T288 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.2228450330 Mar 28 12:30:25 PM PDT 24 Mar 28 12:30:28 PM PDT 24 455111904 ps
T289 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.3875825101 Mar 28 12:30:13 PM PDT 24 Mar 28 12:30:16 PM PDT 24 938500257 ps
T39 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.1964430866 Mar 28 12:30:14 PM PDT 24 Mar 28 12:30:17 PM PDT 24 767034485 ps
T290 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.2643279198 Mar 28 12:29:56 PM PDT 24 Mar 28 12:29:57 PM PDT 24 468983295 ps
T291 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.2358719552 Mar 28 12:30:12 PM PDT 24 Mar 28 12:30:15 PM PDT 24 977638938 ps
T32 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.4038874411 Mar 28 12:29:58 PM PDT 24 Mar 28 12:30:00 PM PDT 24 562742331 ps
T33 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.1897890158 Mar 28 12:30:33 PM PDT 24 Mar 28 12:30:34 PM PDT 24 420289358 ps
T292 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.487369517 Mar 28 12:30:24 PM PDT 24 Mar 28 12:30:26 PM PDT 24 437561991 ps
T293 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.4134415794 Mar 28 12:30:17 PM PDT 24 Mar 28 12:30:19 PM PDT 24 481747813 ps
T34 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.2894916424 Mar 28 12:30:25 PM PDT 24 Mar 28 12:30:27 PM PDT 24 480399721 ps
T294 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.3079657949 Mar 28 12:29:50 PM PDT 24 Mar 28 12:29:54 PM PDT 24 489124624 ps
T56 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.3689122577 Mar 28 12:30:29 PM PDT 24 Mar 28 12:30:30 PM PDT 24 521071778 ps
T35 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.2309054123 Mar 28 12:30:27 PM PDT 24 Mar 28 12:30:30 PM PDT 24 2092626666 ps
T36 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.4265631136 Mar 28 12:29:53 PM PDT 24 Mar 28 12:30:00 PM PDT 24 8828221378 ps
T295 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.3416647192 Mar 28 12:29:47 PM PDT 24 Mar 28 12:29:49 PM PDT 24 467736299 ps
T104 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.1861914818 Mar 28 12:29:48 PM PDT 24 Mar 28 12:29:49 PM PDT 24 472257248 ps
T296 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.3253998578 Mar 28 12:30:19 PM PDT 24 Mar 28 12:30:22 PM PDT 24 461697922 ps
T297 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.1365146076 Mar 28 12:29:50 PM PDT 24 Mar 28 12:29:52 PM PDT 24 749565449 ps
T298 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.1380187198 Mar 28 12:30:26 PM PDT 24 Mar 28 12:30:28 PM PDT 24 419973956 ps
T299 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.1444603785 Mar 28 12:30:27 PM PDT 24 Mar 28 12:30:29 PM PDT 24 295189956 ps
T103 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.1178038142 Mar 28 12:30:08 PM PDT 24 Mar 28 12:30:09 PM PDT 24 527777236 ps
T300 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.1938273562 Mar 28 12:30:18 PM PDT 24 Mar 28 12:30:19 PM PDT 24 431402303 ps
T301 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.1357578586 Mar 28 12:30:25 PM PDT 24 Mar 28 12:30:28 PM PDT 24 306666121 ps
T302 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.2470322165 Mar 28 12:29:49 PM PDT 24 Mar 28 12:29:51 PM PDT 24 370007127 ps
T303 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.2682717145 Mar 28 12:29:47 PM PDT 24 Mar 28 12:29:49 PM PDT 24 763726444 ps
T304 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.434474817 Mar 28 12:29:51 PM PDT 24 Mar 28 12:29:53 PM PDT 24 364494828 ps
T37 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.1304391697 Mar 28 12:30:02 PM PDT 24 Mar 28 12:30:10 PM PDT 24 8117858891 ps
T38 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.1816008839 Mar 28 12:30:08 PM PDT 24 Mar 28 12:30:11 PM PDT 24 7820208330 ps
T305 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.1031950184 Mar 28 12:30:27 PM PDT 24 Mar 28 12:30:29 PM PDT 24 517451020 ps
T306 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.2150252580 Mar 28 12:30:24 PM PDT 24 Mar 28 12:30:25 PM PDT 24 290281279 ps
T100 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.3335905206 Mar 28 12:30:08 PM PDT 24 Mar 28 12:30:12 PM PDT 24 4647951541 ps
T307 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.2225119086 Mar 28 12:29:46 PM PDT 24 Mar 28 12:29:48 PM PDT 24 451871049 ps
T308 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.3050816029 Mar 28 12:29:51 PM PDT 24 Mar 28 12:29:53 PM PDT 24 497799330 ps
T309 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.4025763405 Mar 28 12:29:45 PM PDT 24 Mar 28 12:29:46 PM PDT 24 690561524 ps
T310 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.4089742723 Mar 28 12:30:16 PM PDT 24 Mar 28 12:30:17 PM PDT 24 377641383 ps
T69 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.3113619007 Mar 28 12:29:58 PM PDT 24 Mar 28 12:29:59 PM PDT 24 1576485385 ps
T311 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.344633657 Mar 28 12:30:11 PM PDT 24 Mar 28 12:30:12 PM PDT 24 338318709 ps
T312 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.3053055857 Mar 28 12:30:22 PM PDT 24 Mar 28 12:30:24 PM PDT 24 379676134 ps
T313 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.1022918347 Mar 28 12:30:24 PM PDT 24 Mar 28 12:30:27 PM PDT 24 4722635298 ps
T314 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.1191063314 Mar 28 12:30:21 PM PDT 24 Mar 28 12:30:22 PM PDT 24 292702625 ps
T315 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.1385279709 Mar 28 12:30:22 PM PDT 24 Mar 28 12:30:24 PM PDT 24 521409380 ps
T98 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.575689875 Mar 28 12:29:47 PM PDT 24 Mar 28 12:29:52 PM PDT 24 4068488255 ps
T316 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.4263634602 Mar 28 12:29:46 PM PDT 24 Mar 28 12:29:47 PM PDT 24 274491443 ps
T70 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.3527478047 Mar 28 12:29:51 PM PDT 24 Mar 28 12:29:54 PM PDT 24 1455124813 ps
T317 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.1253361781 Mar 28 12:29:46 PM PDT 24 Mar 28 12:29:47 PM PDT 24 396937289 ps
T71 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.1264426414 Mar 28 12:29:51 PM PDT 24 Mar 28 12:29:52 PM PDT 24 406499042 ps
T72 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.65615647 Mar 28 12:30:07 PM PDT 24 Mar 28 12:30:09 PM PDT 24 2581325330 ps
T318 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.3888310010 Mar 28 12:30:21 PM PDT 24 Mar 28 12:30:22 PM PDT 24 372461076 ps
T99 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.3964421299 Mar 28 12:29:51 PM PDT 24 Mar 28 12:29:55 PM PDT 24 9240246793 ps
T319 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.4112430310 Mar 28 12:29:51 PM PDT 24 Mar 28 12:29:54 PM PDT 24 816957383 ps
T320 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.1714759970 Mar 28 12:30:25 PM PDT 24 Mar 28 12:30:26 PM PDT 24 411670974 ps
T321 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.2561237637 Mar 28 12:30:23 PM PDT 24 Mar 28 12:30:24 PM PDT 24 542634379 ps
T73 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.882232898 Mar 28 12:30:19 PM PDT 24 Mar 28 12:30:23 PM PDT 24 2479273546 ps
T322 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.2270441184 Mar 28 12:30:11 PM PDT 24 Mar 28 12:30:13 PM PDT 24 387304470 ps
T74 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.502274091 Mar 28 12:30:23 PM PDT 24 Mar 28 12:30:25 PM PDT 24 1286526034 ps
T75 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.3637198215 Mar 28 12:29:43 PM PDT 24 Mar 28 12:29:45 PM PDT 24 2290193584 ps
T323 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.3001856141 Mar 28 12:30:13 PM PDT 24 Mar 28 12:30:28 PM PDT 24 8658086426 ps
T76 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.2620240856 Mar 28 12:29:52 PM PDT 24 Mar 28 12:29:53 PM PDT 24 396725196 ps
T324 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.730417982 Mar 28 12:30:05 PM PDT 24 Mar 28 12:30:06 PM PDT 24 1080295901 ps
T325 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.4097131650 Mar 28 12:29:47 PM PDT 24 Mar 28 12:29:49 PM PDT 24 356638742 ps
T326 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.2785599305 Mar 28 12:29:54 PM PDT 24 Mar 28 12:29:56 PM PDT 24 468017330 ps
T327 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.1197149513 Mar 28 12:30:06 PM PDT 24 Mar 28 12:30:08 PM PDT 24 330036608 ps
T328 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.4123838369 Mar 28 12:29:55 PM PDT 24 Mar 28 12:29:56 PM PDT 24 410398544 ps
T329 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.900335762 Mar 28 12:29:50 PM PDT 24 Mar 28 12:29:51 PM PDT 24 483232987 ps
T330 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.1491692635 Mar 28 12:30:07 PM PDT 24 Mar 28 12:30:09 PM PDT 24 1502166885 ps
T331 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.1919662411 Mar 28 12:30:09 PM PDT 24 Mar 28 12:30:10 PM PDT 24 502556477 ps
T332 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.3874045648 Mar 28 12:30:38 PM PDT 24 Mar 28 12:30:39 PM PDT 24 521476465 ps
T333 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.419927744 Mar 28 12:29:57 PM PDT 24 Mar 28 12:29:59 PM PDT 24 459661990 ps
T334 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.2320711050 Mar 28 12:29:50 PM PDT 24 Mar 28 12:29:53 PM PDT 24 1512284583 ps
T335 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.4193892061 Mar 28 12:30:02 PM PDT 24 Mar 28 12:30:05 PM PDT 24 1367781535 ps
T336 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.918182749 Mar 28 12:30:09 PM PDT 24 Mar 28 12:30:12 PM PDT 24 4457234975 ps
T337 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.2086176869 Mar 28 12:29:51 PM PDT 24 Mar 28 12:29:59 PM PDT 24 2437378061 ps
T338 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.573008979 Mar 28 12:30:13 PM PDT 24 Mar 28 12:30:15 PM PDT 24 382132405 ps
T339 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.1732391332 Mar 28 12:30:13 PM PDT 24 Mar 28 12:30:15 PM PDT 24 4689100998 ps
T340 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.506000410 Mar 28 12:30:19 PM PDT 24 Mar 28 12:30:22 PM PDT 24 548204372 ps
T341 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.2173033469 Mar 28 12:30:27 PM PDT 24 Mar 28 12:30:29 PM PDT 24 351118919 ps
T342 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.1342867744 Mar 28 12:29:47 PM PDT 24 Mar 28 12:29:49 PM PDT 24 541095910 ps
T343 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.2221725535 Mar 28 12:30:05 PM PDT 24 Mar 28 12:30:07 PM PDT 24 414227438 ps
T344 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.3831656949 Mar 28 12:30:24 PM PDT 24 Mar 28 12:30:26 PM PDT 24 506685636 ps
T345 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.1787830452 Mar 28 12:30:21 PM PDT 24 Mar 28 12:30:23 PM PDT 24 499247396 ps
T346 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.3988711210 Mar 28 12:30:25 PM PDT 24 Mar 28 12:30:29 PM PDT 24 495523867 ps
T347 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.3367985026 Mar 28 12:30:08 PM PDT 24 Mar 28 12:30:10 PM PDT 24 9609540691 ps
T101 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.3623562769 Mar 28 12:30:09 PM PDT 24 Mar 28 12:30:13 PM PDT 24 8976963736 ps
T348 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.878507556 Mar 28 12:30:23 PM PDT 24 Mar 28 12:30:31 PM PDT 24 8607204757 ps
T349 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.2852711809 Mar 28 12:30:10 PM PDT 24 Mar 28 12:30:12 PM PDT 24 665329449 ps
T350 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.718841542 Mar 28 12:30:19 PM PDT 24 Mar 28 12:30:21 PM PDT 24 392578674 ps
T351 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.139092271 Mar 28 12:30:06 PM PDT 24 Mar 28 12:30:07 PM PDT 24 500064964 ps
T352 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.2913493687 Mar 28 12:29:48 PM PDT 24 Mar 28 12:29:50 PM PDT 24 307040690 ps
T353 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.4200898906 Mar 28 12:30:06 PM PDT 24 Mar 28 12:30:09 PM PDT 24 4628036395 ps
T354 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.1777394951 Mar 28 12:30:27 PM PDT 24 Mar 28 12:30:30 PM PDT 24 516613403 ps
T355 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.2979791232 Mar 28 12:30:20 PM PDT 24 Mar 28 12:30:22 PM PDT 24 302349078 ps
T356 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.2107992348 Mar 28 12:29:50 PM PDT 24 Mar 28 12:29:52 PM PDT 24 374236889 ps
T357 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.3425400797 Mar 28 12:29:55 PM PDT 24 Mar 28 12:29:56 PM PDT 24 1529124390 ps
T358 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.958588309 Mar 28 12:30:13 PM PDT 24 Mar 28 12:30:15 PM PDT 24 654678757 ps
T359 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.2583346412 Mar 28 12:30:10 PM PDT 24 Mar 28 12:30:13 PM PDT 24 4414102108 ps
T360 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.1743876444 Mar 28 12:30:21 PM PDT 24 Mar 28 12:30:22 PM PDT 24 520490772 ps
T361 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.1666797048 Mar 28 12:30:23 PM PDT 24 Mar 28 12:30:25 PM PDT 24 386110419 ps
T362 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.3867405486 Mar 28 12:29:52 PM PDT 24 Mar 28 12:29:52 PM PDT 24 310622484 ps
T363 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.2794592498 Mar 28 12:29:52 PM PDT 24 Mar 28 12:29:56 PM PDT 24 14334399775 ps
T364 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.2705089499 Mar 28 12:29:52 PM PDT 24 Mar 28 12:29:52 PM PDT 24 416944555 ps
T365 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.181093249 Mar 28 12:30:11 PM PDT 24 Mar 28 12:30:15 PM PDT 24 7512663885 ps
T366 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.359883383 Mar 28 12:29:57 PM PDT 24 Mar 28 12:29:58 PM PDT 24 822713708 ps
T367 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.1221604229 Mar 28 12:29:50 PM PDT 24 Mar 28 12:29:52 PM PDT 24 432476584 ps
T368 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.3883832109 Mar 28 12:29:53 PM PDT 24 Mar 28 12:29:54 PM PDT 24 276154834 ps
T369 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.1650465412 Mar 28 12:30:18 PM PDT 24 Mar 28 12:30:20 PM PDT 24 569611642 ps
T57 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.3259191442 Mar 28 12:30:23 PM PDT 24 Mar 28 12:30:24 PM PDT 24 513541625 ps
T58 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.3468004547 Mar 28 12:29:49 PM PDT 24 Mar 28 12:29:50 PM PDT 24 353021484 ps
T370 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.3227456368 Mar 28 12:30:05 PM PDT 24 Mar 28 12:30:06 PM PDT 24 1209285370 ps
T371 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.220784100 Mar 28 12:30:13 PM PDT 24 Mar 28 12:30:14 PM PDT 24 396759348 ps
T372 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.935652640 Mar 28 12:30:02 PM PDT 24 Mar 28 12:30:03 PM PDT 24 449983153 ps
T373 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.3471893777 Mar 28 12:30:10 PM PDT 24 Mar 28 12:30:12 PM PDT 24 842600517 ps
T374 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.4259749964 Mar 28 12:30:20 PM PDT 24 Mar 28 12:30:22 PM PDT 24 414123349 ps
T375 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.199215377 Mar 28 12:30:24 PM PDT 24 Mar 28 12:30:27 PM PDT 24 990366761 ps
T376 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.3829405248 Mar 28 12:29:48 PM PDT 24 Mar 28 12:29:54 PM PDT 24 4397598544 ps
T377 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.3003103353 Mar 28 12:29:51 PM PDT 24 Mar 28 12:29:53 PM PDT 24 466901756 ps
T378 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.4091027171 Mar 28 12:30:29 PM PDT 24 Mar 28 12:30:30 PM PDT 24 497109548 ps
T379 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.1744014450 Mar 28 12:29:45 PM PDT 24 Mar 28 12:29:46 PM PDT 24 984576651 ps
T380 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.1763834514 Mar 28 12:29:57 PM PDT 24 Mar 28 12:29:59 PM PDT 24 486100149 ps
T381 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.333189938 Mar 28 12:30:20 PM PDT 24 Mar 28 12:30:22 PM PDT 24 474433266 ps
T382 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.3410916620 Mar 28 12:30:10 PM PDT 24 Mar 28 12:30:11 PM PDT 24 583539430 ps
T59 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.3088961258 Mar 28 12:29:54 PM PDT 24 Mar 28 12:30:07 PM PDT 24 8026563506 ps
T60 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.801399219 Mar 28 12:30:04 PM PDT 24 Mar 28 12:30:06 PM PDT 24 1328104383 ps
T61 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.3872483799 Mar 28 12:30:02 PM PDT 24 Mar 28 12:30:03 PM PDT 24 410667365 ps
T62 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.1520342719 Mar 28 12:30:05 PM PDT 24 Mar 28 12:30:06 PM PDT 24 405864778 ps
T68 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.1940085941 Mar 28 12:29:49 PM PDT 24 Mar 28 12:29:50 PM PDT 24 420620604 ps
T383 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.1440613369 Mar 28 12:29:46 PM PDT 24 Mar 28 12:29:47 PM PDT 24 574435820 ps
T384 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.2791143764 Mar 28 12:30:00 PM PDT 24 Mar 28 12:30:01 PM PDT 24 378993307 ps
T385 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.2598603068 Mar 28 12:29:54 PM PDT 24 Mar 28 12:29:55 PM PDT 24 331818239 ps
T386 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.1220759532 Mar 28 12:29:49 PM PDT 24 Mar 28 12:29:52 PM PDT 24 1459816030 ps
T387 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.223339105 Mar 28 12:30:05 PM PDT 24 Mar 28 12:30:06 PM PDT 24 519467782 ps
T388 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.2359136110 Mar 28 12:29:58 PM PDT 24 Mar 28 12:29:59 PM PDT 24 2398569350 ps
T389 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.3891557062 Mar 28 12:29:50 PM PDT 24 Mar 28 12:29:52 PM PDT 24 340962188 ps
T390 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.3820741645 Mar 28 12:30:36 PM PDT 24 Mar 28 12:30:39 PM PDT 24 389297160 ps
T391 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.4092172594 Mar 28 12:30:20 PM PDT 24 Mar 28 12:30:21 PM PDT 24 299101719 ps
T392 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.185926320 Mar 28 12:29:46 PM PDT 24 Mar 28 12:29:47 PM PDT 24 308025079 ps
T393 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.3793885946 Mar 28 12:29:53 PM PDT 24 Mar 28 12:29:53 PM PDT 24 481979780 ps
T394 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.4224904426 Mar 28 12:30:24 PM PDT 24 Mar 28 12:30:26 PM PDT 24 664222369 ps
T64 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.841904357 Mar 28 12:29:48 PM PDT 24 Mar 28 12:29:49 PM PDT 24 351333281 ps
T395 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.3057982485 Mar 28 12:29:51 PM PDT 24 Mar 28 12:29:53 PM PDT 24 512700068 ps
T396 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.1471548973 Mar 28 12:29:56 PM PDT 24 Mar 28 12:29:57 PM PDT 24 391686948 ps
T397 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.2667780187 Mar 28 12:30:18 PM PDT 24 Mar 28 12:30:20 PM PDT 24 2294534597 ps
T398 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.744030894 Mar 28 12:30:12 PM PDT 24 Mar 28 12:30:14 PM PDT 24 1971629513 ps
T102 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.1800849067 Mar 28 12:30:25 PM PDT 24 Mar 28 12:30:28 PM PDT 24 4265268392 ps
T399 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.1040766443 Mar 28 12:30:30 PM PDT 24 Mar 28 12:30:31 PM PDT 24 2042070657 ps
T65 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.505784473 Mar 28 12:29:51 PM PDT 24 Mar 28 12:29:55 PM PDT 24 2131929398 ps
T400 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.3426192268 Mar 28 12:30:20 PM PDT 24 Mar 28 12:30:21 PM PDT 24 421277573 ps
T401 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.376515529 Mar 28 12:30:09 PM PDT 24 Mar 28 12:30:10 PM PDT 24 324848673 ps
T402 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.1596725811 Mar 28 12:30:16 PM PDT 24 Mar 28 12:30:17 PM PDT 24 370574465 ps
T403 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.543228786 Mar 28 12:30:25 PM PDT 24 Mar 28 12:30:28 PM PDT 24 318606976 ps
T404 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.2086634297 Mar 28 12:29:47 PM PDT 24 Mar 28 12:29:49 PM PDT 24 388090053 ps
T405 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.3937997769 Mar 28 12:30:24 PM PDT 24 Mar 28 12:30:25 PM PDT 24 284978134 ps
T406 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.3152307917 Mar 28 12:30:18 PM PDT 24 Mar 28 12:30:19 PM PDT 24 610735453 ps
T407 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.3492618017 Mar 28 12:30:24 PM PDT 24 Mar 28 12:30:26 PM PDT 24 453159174 ps
T408 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.1533070285 Mar 28 12:30:09 PM PDT 24 Mar 28 12:30:10 PM PDT 24 393377048 ps
T409 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.220256267 Mar 28 12:30:06 PM PDT 24 Mar 28 12:30:10 PM PDT 24 419613330 ps
T410 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.1700739285 Mar 28 12:30:12 PM PDT 24 Mar 28 12:30:13 PM PDT 24 526969563 ps
T411 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.4040464576 Mar 28 12:29:56 PM PDT 24 Mar 28 12:29:58 PM PDT 24 412173053 ps
T412 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.1034230926 Mar 28 12:30:14 PM PDT 24 Mar 28 12:30:16 PM PDT 24 319245434 ps
T413 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.4073481080 Mar 28 12:30:29 PM PDT 24 Mar 28 12:30:33 PM PDT 24 2412729653 ps
T414 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.3206944197 Mar 28 12:30:25 PM PDT 24 Mar 28 12:30:28 PM PDT 24 308847165 ps
T415 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.2832731131 Mar 28 12:29:59 PM PDT 24 Mar 28 12:30:02 PM PDT 24 446852562 ps
T416 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.2643963723 Mar 28 12:30:27 PM PDT 24 Mar 28 12:30:28 PM PDT 24 543051023 ps
T417 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.3626612857 Mar 28 12:29:49 PM PDT 24 Mar 28 12:29:57 PM PDT 24 4374474356 ps
T67 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.1414561725 Mar 28 12:30:13 PM PDT 24 Mar 28 12:30:16 PM PDT 24 430570684 ps
T418 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.2151172285 Mar 28 12:30:08 PM PDT 24 Mar 28 12:30:10 PM PDT 24 433092851 ps
T419 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.3671058219 Mar 28 12:29:55 PM PDT 24 Mar 28 12:29:59 PM PDT 24 3825766501 ps
T66 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.463091812 Mar 28 12:29:47 PM PDT 24 Mar 28 12:30:01 PM PDT 24 6797909446 ps
T420 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.1848544491 Mar 28 12:30:15 PM PDT 24 Mar 28 12:30:19 PM PDT 24 4370155520 ps
T421 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.222073466 Mar 28 12:30:26 PM PDT 24 Mar 28 12:30:29 PM PDT 24 673929932 ps
T422 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.1232074070 Mar 28 12:30:22 PM PDT 24 Mar 28 12:30:24 PM PDT 24 351078376 ps
T423 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.3646617564 Mar 28 12:30:18 PM PDT 24 Mar 28 12:30:20 PM PDT 24 429303265 ps
T424 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.1576666163 Mar 28 12:30:29 PM PDT 24 Mar 28 12:30:30 PM PDT 24 418907598 ps
T63 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.1999612096 Mar 28 12:30:10 PM PDT 24 Mar 28 12:30:12 PM PDT 24 503069571 ps
T425 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.3433172323 Mar 28 12:30:20 PM PDT 24 Mar 28 12:30:22 PM PDT 24 566134772 ps
T426 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.582216706 Mar 28 12:29:50 PM PDT 24 Mar 28 12:29:52 PM PDT 24 334467612 ps

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.1784221964
Short name T2
Test name
Test status
Simulation time 41332149591 ps
CPU time 232.13 seconds
Started Mar 28 12:48:31 PM PDT 24
Finished Mar 28 12:52:24 PM PDT 24
Peak memory 198276 kb
Host smart-5e3446a4-02c6-42d7-944f-5cd898e16ebf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784221964 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.1784221964
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.4265631136
Short name T36
Test name
Test status
Simulation time 8828221378 ps
CPU time 7.21 seconds
Started Mar 28 12:29:53 PM PDT 24
Finished Mar 28 12:30:00 PM PDT 24
Peak memory 197816 kb
Host smart-97b92fd2-5076-4dbd-a1db-c7a7bdda6e1f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265631136 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_t
l_intg_err.4265631136
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.2014660605
Short name T41
Test name
Test status
Simulation time 572141248964 ps
CPU time 1035.43 seconds
Started Mar 28 12:48:25 PM PDT 24
Finished Mar 28 01:05:43 PM PDT 24
Peak memory 203936 kb
Host smart-74341a20-e416-4642-8ff0-44e78db421a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014660605 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.2014660605
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.3155982735
Short name T1
Test name
Test status
Simulation time 222279842120 ps
CPU time 736.68 seconds
Started Mar 28 12:48:08 PM PDT 24
Finished Mar 28 01:00:25 PM PDT 24
Peak memory 200800 kb
Host smart-71828e7c-8117-4960-a187-c24006ae011c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155982735 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.3155982735
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.2537990081
Short name T19
Test name
Test status
Simulation time 7081695195 ps
CPU time 11.69 seconds
Started Mar 28 12:47:55 PM PDT 24
Finished Mar 28 12:48:07 PM PDT 24
Peak memory 215204 kb
Host smart-466c4a92-0584-4f64-88e3-b6af7398c4f0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537990081 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.2537990081
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.2116689630
Short name T94
Test name
Test status
Simulation time 418578717756 ps
CPU time 86.76 seconds
Started Mar 28 12:48:12 PM PDT 24
Finished Mar 28 12:49:40 PM PDT 24
Peak memory 183528 kb
Host smart-9f8e592c-dbb1-4d7c-a0a6-e95d4a281cd8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116689630 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_a
ll.2116689630
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.505784473
Short name T65
Test name
Test status
Simulation time 2131929398 ps
CPU time 3.25 seconds
Started Mar 28 12:29:51 PM PDT 24
Finished Mar 28 12:29:55 PM PDT 24
Peak memory 190408 kb
Host smart-0d1ec044-28eb-4a22-848c-461f159c9ff1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505784473 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_bi
t_bash.505784473
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.1304391697
Short name T37
Test name
Test status
Simulation time 8117858891 ps
CPU time 7.64 seconds
Started Mar 28 12:30:02 PM PDT 24
Finished Mar 28 12:30:10 PM PDT 24
Peak memory 197868 kb
Host smart-9f1b6e03-b36b-4c27-9123-4bae2d556921
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304391697 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl
_intg_err.1304391697
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.4048104894
Short name T6
Test name
Test status
Simulation time 92270193578 ps
CPU time 516.07 seconds
Started Mar 28 12:48:24 PM PDT 24
Finished Mar 28 12:57:00 PM PDT 24
Peak memory 198708 kb
Host smart-2303ec7e-035a-48d1-a69e-32fdf81fd5a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048104894 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.4048104894
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.2309054123
Short name T35
Test name
Test status
Simulation time 2092626666 ps
CPU time 2.28 seconds
Started Mar 28 12:30:27 PM PDT 24
Finished Mar 28 12:30:30 PM PDT 24
Peak memory 194408 kb
Host smart-087b4f81-fb82-4f91-b01e-a45d0c81f5ac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309054123 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.ao
n_timer_same_csr_outstanding.2309054123
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.4040464576
Short name T411
Test name
Test status
Simulation time 412173053 ps
CPU time 1.32 seconds
Started Mar 28 12:29:56 PM PDT 24
Finished Mar 28 12:29:58 PM PDT 24
Peak memory 183648 kb
Host smart-cf89c9b9-d73a-4701-a608-ceced762a83d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040464576 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_a
liasing.4040464576
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.3088961258
Short name T59
Test name
Test status
Simulation time 8026563506 ps
CPU time 13.38 seconds
Started Mar 28 12:29:54 PM PDT 24
Finished Mar 28 12:30:07 PM PDT 24
Peak memory 183812 kb
Host smart-88e03d15-0f14-4bc5-8fab-3c79d298ff05
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088961258 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_b
it_bash.3088961258
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.4193892061
Short name T335
Test name
Test status
Simulation time 1367781535 ps
CPU time 2.49 seconds
Started Mar 28 12:30:02 PM PDT 24
Finished Mar 28 12:30:05 PM PDT 24
Peak memory 193080 kb
Host smart-40d3a28c-35ef-4b85-9af8-91d2f48b9089
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193892061 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_h
w_reset.4193892061
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.3471893777
Short name T373
Test name
Test status
Simulation time 842600517 ps
CPU time 1.44 seconds
Started Mar 28 12:30:10 PM PDT 24
Finished Mar 28 12:30:12 PM PDT 24
Peak memory 198484 kb
Host smart-b8f864e2-fae3-4e84-a42b-de25030de8c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471893777 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.3471893777
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.3872483799
Short name T61
Test name
Test status
Simulation time 410667365 ps
CPU time 0.8 seconds
Started Mar 28 12:30:02 PM PDT 24
Finished Mar 28 12:30:03 PM PDT 24
Peak memory 192976 kb
Host smart-34b4e697-4871-4416-b356-8313ba7aa6ab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872483799 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.3872483799
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.185926320
Short name T392
Test name
Test status
Simulation time 308025079 ps
CPU time 0.65 seconds
Started Mar 28 12:29:46 PM PDT 24
Finished Mar 28 12:29:47 PM PDT 24
Peak memory 183280 kb
Host smart-aa3f82aa-6287-4386-a4b9-f7ea8ef831e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185926320 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.185926320
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.1763834514
Short name T380
Test name
Test status
Simulation time 486100149 ps
CPU time 1.22 seconds
Started Mar 28 12:29:57 PM PDT 24
Finished Mar 28 12:29:59 PM PDT 24
Peak memory 183460 kb
Host smart-68470a82-bbe7-4bec-9e5c-2c2950e827d3
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763834514 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_t
imer_mem_partial_access.1763834514
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.1034230926
Short name T412
Test name
Test status
Simulation time 319245434 ps
CPU time 0.76 seconds
Started Mar 28 12:30:14 PM PDT 24
Finished Mar 28 12:30:16 PM PDT 24
Peak memory 183612 kb
Host smart-c8a88e00-3919-4e07-b6c6-5234ea6708c4
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034230926 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_w
alk.1034230926
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.3425400797
Short name T357
Test name
Test status
Simulation time 1529124390 ps
CPU time 1.07 seconds
Started Mar 28 12:29:55 PM PDT 24
Finished Mar 28 12:29:56 PM PDT 24
Peak memory 183664 kb
Host smart-f5c9dc3d-d855-4bb7-a979-253dbae83be1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425400797 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon
_timer_same_csr_outstanding.3425400797
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.506000410
Short name T340
Test name
Test status
Simulation time 548204372 ps
CPU time 1.39 seconds
Started Mar 28 12:30:19 PM PDT 24
Finished Mar 28 12:30:22 PM PDT 24
Peak memory 198588 kb
Host smart-d9f36b65-d12e-4e1e-b990-371938107413
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506000410 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.506000410
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.1816008839
Short name T38
Test name
Test status
Simulation time 7820208330 ps
CPU time 3.56 seconds
Started Mar 28 12:30:08 PM PDT 24
Finished Mar 28 12:30:11 PM PDT 24
Peak memory 198012 kb
Host smart-98eb9c99-d121-4ca1-8a14-7476a7f8ca57
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816008839 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl
_intg_err.1816008839
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.1999612096
Short name T63
Test name
Test status
Simulation time 503069571 ps
CPU time 1.44 seconds
Started Mar 28 12:30:10 PM PDT 24
Finished Mar 28 12:30:12 PM PDT 24
Peak memory 182800 kb
Host smart-d60ff50f-5817-4ddf-85dd-caeab758838b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999612096 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_a
liasing.1999612096
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.1964430866
Short name T39
Test name
Test status
Simulation time 767034485 ps
CPU time 1.18 seconds
Started Mar 28 12:30:14 PM PDT 24
Finished Mar 28 12:30:17 PM PDT 24
Peak memory 183660 kb
Host smart-4885b826-572b-4dbd-88fa-34ea76a82f45
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964430866 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_h
w_reset.1964430866
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.2221725535
Short name T343
Test name
Test status
Simulation time 414227438 ps
CPU time 0.83 seconds
Started Mar 28 12:30:05 PM PDT 24
Finished Mar 28 12:30:07 PM PDT 24
Peak memory 194516 kb
Host smart-804632c9-e931-4ff7-84a9-f633540dc75f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221725535 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.2221725535
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.3152307917
Short name T406
Test name
Test status
Simulation time 610735453 ps
CPU time 0.64 seconds
Started Mar 28 12:30:18 PM PDT 24
Finished Mar 28 12:30:19 PM PDT 24
Peak memory 183832 kb
Host smart-c31950bc-6198-4c29-b6d9-6d278b4b9362
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152307917 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.3152307917
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.3416647192
Short name T295
Test name
Test status
Simulation time 467736299 ps
CPU time 0.74 seconds
Started Mar 28 12:29:47 PM PDT 24
Finished Mar 28 12:29:49 PM PDT 24
Peak memory 181640 kb
Host smart-9b3ce92d-7196-4f57-8cd2-6e8900b3ace2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416647192 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.3416647192
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.3883832109
Short name T368
Test name
Test status
Simulation time 276154834 ps
CPU time 0.89 seconds
Started Mar 28 12:29:53 PM PDT 24
Finished Mar 28 12:29:54 PM PDT 24
Peak memory 183416 kb
Host smart-fec5b2d9-ca6f-4e32-9036-e62b605ca656
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883832109 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_t
imer_mem_partial_access.3883832109
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.2086634297
Short name T404
Test name
Test status
Simulation time 388090053 ps
CPU time 1.16 seconds
Started Mar 28 12:29:47 PM PDT 24
Finished Mar 28 12:29:49 PM PDT 24
Peak memory 181860 kb
Host smart-384d82d4-4d96-44ef-98c6-65e5e0722ab4
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086634297 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_w
alk.2086634297
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.1220759532
Short name T386
Test name
Test status
Simulation time 1459816030 ps
CPU time 1.58 seconds
Started Mar 28 12:29:49 PM PDT 24
Finished Mar 28 12:29:52 PM PDT 24
Peak memory 191420 kb
Host smart-7ae1de9c-b0c0-4017-901c-127f37cf453a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220759532 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon
_timer_same_csr_outstanding.1220759532
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.333189938
Short name T381
Test name
Test status
Simulation time 474433266 ps
CPU time 1.61 seconds
Started Mar 28 12:30:20 PM PDT 24
Finished Mar 28 12:30:22 PM PDT 24
Peak memory 198476 kb
Host smart-1a6ff383-de43-4db4-b8e9-e85c6aea13d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333189938 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.333189938
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.222073466
Short name T421
Test name
Test status
Simulation time 673929932 ps
CPU time 0.98 seconds
Started Mar 28 12:30:26 PM PDT 24
Finished Mar 28 12:30:29 PM PDT 24
Peak memory 198272 kb
Host smart-e8c86875-e270-40ce-b92b-9cfd4c34635c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222073466 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.222073466
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.2705089499
Short name T364
Test name
Test status
Simulation time 416944555 ps
CPU time 0.66 seconds
Started Mar 28 12:29:52 PM PDT 24
Finished Mar 28 12:29:52 PM PDT 24
Peak memory 192704 kb
Host smart-b7f9bd9f-d55b-4598-9a9b-64fc81bd796f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705089499 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.2705089499
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.2107992348
Short name T356
Test name
Test status
Simulation time 374236889 ps
CPU time 0.72 seconds
Started Mar 28 12:29:50 PM PDT 24
Finished Mar 28 12:29:52 PM PDT 24
Peak memory 182744 kb
Host smart-f44b5de3-f22f-43a2-9ea5-3c2b8680b70b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107992348 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.2107992348
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.2359136110
Short name T388
Test name
Test status
Simulation time 2398569350 ps
CPU time 1.28 seconds
Started Mar 28 12:29:58 PM PDT 24
Finished Mar 28 12:29:59 PM PDT 24
Peak memory 183796 kb
Host smart-ecbda314-edfc-4af9-9ec9-817063a6ae1f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359136110 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.ao
n_timer_same_csr_outstanding.2359136110
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.1221604229
Short name T367
Test name
Test status
Simulation time 432476584 ps
CPU time 1.59 seconds
Started Mar 28 12:29:50 PM PDT 24
Finished Mar 28 12:29:52 PM PDT 24
Peak memory 198028 kb
Host smart-5694184a-c7dd-491c-b4ac-ef544d8c953f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221604229 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.1221604229
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.1848544491
Short name T420
Test name
Test status
Simulation time 4370155520 ps
CPU time 2.4 seconds
Started Mar 28 12:30:15 PM PDT 24
Finished Mar 28 12:30:19 PM PDT 24
Peak memory 197540 kb
Host smart-b2708153-4123-4cf7-8d59-7ff790d43872
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848544491 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_t
l_intg_err.1848544491
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.4224904426
Short name T394
Test name
Test status
Simulation time 664222369 ps
CPU time 1.28 seconds
Started Mar 28 12:30:24 PM PDT 24
Finished Mar 28 12:30:26 PM PDT 24
Peak memory 198320 kb
Host smart-c53c2002-77f4-4f42-bb53-aa65687b82e2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224904426 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.4224904426
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.3689122577
Short name T56
Test name
Test status
Simulation time 521071778 ps
CPU time 1.3 seconds
Started Mar 28 12:30:29 PM PDT 24
Finished Mar 28 12:30:30 PM PDT 24
Peak memory 183592 kb
Host smart-22a268d1-84ee-48e1-a86b-7caeb2b8f298
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689122577 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.3689122577
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.4263634602
Short name T316
Test name
Test status
Simulation time 274491443 ps
CPU time 0.95 seconds
Started Mar 28 12:29:46 PM PDT 24
Finished Mar 28 12:29:47 PM PDT 24
Peak memory 183488 kb
Host smart-539f9e0c-33a2-4583-a6f8-9c309064ffe7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263634602 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.4263634602
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.1365146076
Short name T297
Test name
Test status
Simulation time 749565449 ps
CPU time 1.2 seconds
Started Mar 28 12:29:50 PM PDT 24
Finished Mar 28 12:29:52 PM PDT 24
Peak memory 197332 kb
Host smart-e0398d50-6cb1-4ec2-b967-db567b126fe6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365146076 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.1365146076
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.3492618017
Short name T407
Test name
Test status
Simulation time 453159174 ps
CPU time 0.89 seconds
Started Mar 28 12:30:24 PM PDT 24
Finished Mar 28 12:30:26 PM PDT 24
Peak memory 197640 kb
Host smart-8f63fbc8-a1be-4023-8257-a957db2cfe4d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492618017 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.3492618017
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.3888310010
Short name T318
Test name
Test status
Simulation time 372461076 ps
CPU time 0.72 seconds
Started Mar 28 12:30:21 PM PDT 24
Finished Mar 28 12:30:22 PM PDT 24
Peak memory 183720 kb
Host smart-a02be82b-e32d-410b-ac30-ef807e46aaf8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888310010 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.3888310010
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.220784100
Short name T371
Test name
Test status
Simulation time 396759348 ps
CPU time 0.88 seconds
Started Mar 28 12:30:13 PM PDT 24
Finished Mar 28 12:30:14 PM PDT 24
Peak memory 183532 kb
Host smart-8c511a99-e30d-4577-a663-2d63201ba901
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220784100 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.220784100
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.502274091
Short name T74
Test name
Test status
Simulation time 1286526034 ps
CPU time 1.13 seconds
Started Mar 28 12:30:23 PM PDT 24
Finished Mar 28 12:30:25 PM PDT 24
Peak memory 183608 kb
Host smart-46f07090-68c9-4e86-b8de-87bb56dbf67b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502274091 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon
_timer_same_csr_outstanding.502274091
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.1777394951
Short name T354
Test name
Test status
Simulation time 516613403 ps
CPU time 2.72 seconds
Started Mar 28 12:30:27 PM PDT 24
Finished Mar 28 12:30:30 PM PDT 24
Peak memory 197216 kb
Host smart-1efa4614-fa2c-4403-b9ca-9f13460f8901
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777394951 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.1777394951
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.3001856141
Short name T323
Test name
Test status
Simulation time 8658086426 ps
CPU time 13.83 seconds
Started Mar 28 12:30:13 PM PDT 24
Finished Mar 28 12:30:28 PM PDT 24
Peak memory 197832 kb
Host smart-42e1cdd2-f026-457d-8d1d-284dfcc9e774
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001856141 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_t
l_intg_err.3001856141
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.3053055857
Short name T312
Test name
Test status
Simulation time 379676134 ps
CPU time 1.18 seconds
Started Mar 28 12:30:22 PM PDT 24
Finished Mar 28 12:30:24 PM PDT 24
Peak memory 195564 kb
Host smart-255d3989-737f-491e-9361-4101ff0a7190
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053055857 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.3053055857
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.4091027171
Short name T378
Test name
Test status
Simulation time 497109548 ps
CPU time 0.75 seconds
Started Mar 28 12:30:29 PM PDT 24
Finished Mar 28 12:30:30 PM PDT 24
Peak memory 183640 kb
Host smart-3ed866d2-f3dc-4812-973d-f6f8d3a896b0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091027171 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.4091027171
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.3410916620
Short name T382
Test name
Test status
Simulation time 583539430 ps
CPU time 0.58 seconds
Started Mar 28 12:30:10 PM PDT 24
Finished Mar 28 12:30:11 PM PDT 24
Peak memory 183500 kb
Host smart-dbb60eab-e581-487a-b8d2-3eef85fb066f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410916620 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.3410916620
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.882232898
Short name T73
Test name
Test status
Simulation time 2479273546 ps
CPU time 2.66 seconds
Started Mar 28 12:30:19 PM PDT 24
Finished Mar 28 12:30:23 PM PDT 24
Peak memory 194504 kb
Host smart-a5f325d0-17b6-4b82-932d-b8c54339a47d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882232898 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon
_timer_same_csr_outstanding.882232898
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.2358719552
Short name T291
Test name
Test status
Simulation time 977638938 ps
CPU time 2.47 seconds
Started Mar 28 12:30:12 PM PDT 24
Finished Mar 28 12:30:15 PM PDT 24
Peak memory 198412 kb
Host smart-92588c86-bed7-43e1-8d40-41a71f4d1f17
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358719552 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.2358719552
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.3367985026
Short name T347
Test name
Test status
Simulation time 9609540691 ps
CPU time 2.11 seconds
Started Mar 28 12:30:08 PM PDT 24
Finished Mar 28 12:30:10 PM PDT 24
Peak memory 197884 kb
Host smart-d1e0fc4c-1e0b-48dc-8801-7bd3689a5649
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367985026 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_t
l_intg_err.3367985026
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.2561237637
Short name T321
Test name
Test status
Simulation time 542634379 ps
CPU time 1.01 seconds
Started Mar 28 12:30:23 PM PDT 24
Finished Mar 28 12:30:24 PM PDT 24
Peak memory 198316 kb
Host smart-ff930012-ff62-4335-bf15-fd732eddd7e7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561237637 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.2561237637
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.1414561725
Short name T67
Test name
Test status
Simulation time 430570684 ps
CPU time 1.21 seconds
Started Mar 28 12:30:13 PM PDT 24
Finished Mar 28 12:30:16 PM PDT 24
Peak memory 183624 kb
Host smart-3e1ab57c-572e-43ef-9b4b-5dcaaf429678
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414561725 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.1414561725
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.2150252580
Short name T306
Test name
Test status
Simulation time 290281279 ps
CPU time 0.97 seconds
Started Mar 28 12:30:24 PM PDT 24
Finished Mar 28 12:30:25 PM PDT 24
Peak memory 183500 kb
Host smart-81a03421-aff4-4f83-a821-216c8c431e50
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150252580 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.2150252580
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.2667780187
Short name T397
Test name
Test status
Simulation time 2294534597 ps
CPU time 1.69 seconds
Started Mar 28 12:30:18 PM PDT 24
Finished Mar 28 12:30:20 PM PDT 24
Peak memory 194332 kb
Host smart-6b452a65-b79c-4f31-b66d-0b825e0771da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667780187 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao
n_timer_same_csr_outstanding.2667780187
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.3057982485
Short name T395
Test name
Test status
Simulation time 512700068 ps
CPU time 1.79 seconds
Started Mar 28 12:29:51 PM PDT 24
Finished Mar 28 12:29:53 PM PDT 24
Peak memory 197948 kb
Host smart-2e6ffa32-6e2b-43e7-b622-4179d1ff5a86
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057982485 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.3057982485
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.878507556
Short name T348
Test name
Test status
Simulation time 8607204757 ps
CPU time 7.61 seconds
Started Mar 28 12:30:23 PM PDT 24
Finished Mar 28 12:30:31 PM PDT 24
Peak memory 197648 kb
Host smart-109e5646-0582-43c5-8aac-7744aeba6b13
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878507556 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl
_intg_err.878507556
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.1919662411
Short name T331
Test name
Test status
Simulation time 502556477 ps
CPU time 0.96 seconds
Started Mar 28 12:30:09 PM PDT 24
Finished Mar 28 12:30:10 PM PDT 24
Peak memory 198352 kb
Host smart-eceb2739-fad9-4237-a4fc-329d2351b3b0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919662411 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.1919662411
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.2620240856
Short name T76
Test name
Test status
Simulation time 396725196 ps
CPU time 0.77 seconds
Started Mar 28 12:29:52 PM PDT 24
Finished Mar 28 12:29:53 PM PDT 24
Peak memory 182820 kb
Host smart-7a2e605e-70f3-4241-8d4c-c9d93c07b3ba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620240856 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.2620240856
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.1938273562
Short name T300
Test name
Test status
Simulation time 431402303 ps
CPU time 0.71 seconds
Started Mar 28 12:30:18 PM PDT 24
Finished Mar 28 12:30:19 PM PDT 24
Peak memory 183224 kb
Host smart-0359a23f-4e5d-4344-bad6-faa116fffa59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938273562 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.1938273562
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.3113619007
Short name T69
Test name
Test status
Simulation time 1576485385 ps
CPU time 1.19 seconds
Started Mar 28 12:29:58 PM PDT 24
Finished Mar 28 12:29:59 PM PDT 24
Peak memory 193028 kb
Host smart-15066638-f78c-468c-92da-0778e3cfbcaa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113619007 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.ao
n_timer_same_csr_outstanding.3113619007
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.2852711809
Short name T349
Test name
Test status
Simulation time 665329449 ps
CPU time 1.8 seconds
Started Mar 28 12:30:10 PM PDT 24
Finished Mar 28 12:30:12 PM PDT 24
Peak memory 198452 kb
Host smart-3a4224ed-597f-480c-a7f3-70d268654061
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852711809 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.2852711809
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.1800849067
Short name T102
Test name
Test status
Simulation time 4265268392 ps
CPU time 1.56 seconds
Started Mar 28 12:30:25 PM PDT 24
Finished Mar 28 12:30:28 PM PDT 24
Peak memory 196208 kb
Host smart-f6fda9de-e0f9-40ce-a69a-780a17c59c24
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800849067 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_t
l_intg_err.1800849067
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.1596725811
Short name T402
Test name
Test status
Simulation time 370574465 ps
CPU time 1.14 seconds
Started Mar 28 12:30:16 PM PDT 24
Finished Mar 28 12:30:17 PM PDT 24
Peak memory 195512 kb
Host smart-fd0b6a45-b786-4d99-82bf-819e36ce7649
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596725811 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.1596725811
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.2151172285
Short name T418
Test name
Test status
Simulation time 433092851 ps
CPU time 0.67 seconds
Started Mar 28 12:30:08 PM PDT 24
Finished Mar 28 12:30:10 PM PDT 24
Peak memory 192880 kb
Host smart-484ec2b9-a19b-4787-8c5d-5b088abab67a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151172285 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.2151172285
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.3253998578
Short name T296
Test name
Test status
Simulation time 461697922 ps
CPU time 1.24 seconds
Started Mar 28 12:30:19 PM PDT 24
Finished Mar 28 12:30:22 PM PDT 24
Peak memory 183432 kb
Host smart-d5b63dba-f73c-45ff-aa03-71f0b132f82f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253998578 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.3253998578
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.744030894
Short name T398
Test name
Test status
Simulation time 1971629513 ps
CPU time 1.03 seconds
Started Mar 28 12:30:12 PM PDT 24
Finished Mar 28 12:30:14 PM PDT 24
Peak memory 193916 kb
Host smart-a8ddf0b4-36d7-4066-96fa-f47c561996b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744030894 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon
_timer_same_csr_outstanding.744030894
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.487369517
Short name T292
Test name
Test status
Simulation time 437561991 ps
CPU time 1.56 seconds
Started Mar 28 12:30:24 PM PDT 24
Finished Mar 28 12:30:26 PM PDT 24
Peak memory 198444 kb
Host smart-7dae4364-a602-41a6-b517-3b0b76da15a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487369517 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.487369517
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.1022918347
Short name T313
Test name
Test status
Simulation time 4722635298 ps
CPU time 2.63 seconds
Started Mar 28 12:30:24 PM PDT 24
Finished Mar 28 12:30:27 PM PDT 24
Peak memory 196272 kb
Host smart-dc4df525-4b5f-4732-8ecd-0c962dd315c4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022918347 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_t
l_intg_err.1022918347
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.344633657
Short name T311
Test name
Test status
Simulation time 338318709 ps
CPU time 1.12 seconds
Started Mar 28 12:30:11 PM PDT 24
Finished Mar 28 12:30:12 PM PDT 24
Peak memory 195160 kb
Host smart-61e6a20d-fb13-4d2c-b180-bd5d903f2f3e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344633657 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.344633657
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.2894916424
Short name T34
Test name
Test status
Simulation time 480399721 ps
CPU time 1.41 seconds
Started Mar 28 12:30:25 PM PDT 24
Finished Mar 28 12:30:27 PM PDT 24
Peak memory 183600 kb
Host smart-968a3acd-94ae-4aba-8be7-7472d0faa538
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894916424 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.2894916424
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.1232074070
Short name T422
Test name
Test status
Simulation time 351078376 ps
CPU time 0.66 seconds
Started Mar 28 12:30:22 PM PDT 24
Finished Mar 28 12:30:24 PM PDT 24
Peak memory 183540 kb
Host smart-226b4832-782d-4eda-850c-513c162cbdc6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232074070 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.1232074070
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.1491692635
Short name T330
Test name
Test status
Simulation time 1502166885 ps
CPU time 1.74 seconds
Started Mar 28 12:30:07 PM PDT 24
Finished Mar 28 12:30:09 PM PDT 24
Peak memory 193196 kb
Host smart-4320f449-d769-47e6-913d-31071081140c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491692635 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.ao
n_timer_same_csr_outstanding.1491692635
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.199215377
Short name T375
Test name
Test status
Simulation time 990366761 ps
CPU time 2.67 seconds
Started Mar 28 12:30:24 PM PDT 24
Finished Mar 28 12:30:27 PM PDT 24
Peak memory 198304 kb
Host smart-2ea50766-8f05-4927-b9ca-a0879c97bab4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199215377 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.199215377
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.3335905206
Short name T100
Test name
Test status
Simulation time 4647951541 ps
CPU time 2.55 seconds
Started Mar 28 12:30:08 PM PDT 24
Finished Mar 28 12:30:12 PM PDT 24
Peak memory 197124 kb
Host smart-e784ddbc-933f-4789-9b5e-5793dc9a3692
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335905206 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_t
l_intg_err.3335905206
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.1385279709
Short name T315
Test name
Test status
Simulation time 521409380 ps
CPU time 0.81 seconds
Started Mar 28 12:30:22 PM PDT 24
Finished Mar 28 12:30:24 PM PDT 24
Peak memory 195688 kb
Host smart-fefc34fa-257f-462c-adee-7910a1172007
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385279709 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.1385279709
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.3259191442
Short name T57
Test name
Test status
Simulation time 513541625 ps
CPU time 1.25 seconds
Started Mar 28 12:30:23 PM PDT 24
Finished Mar 28 12:30:24 PM PDT 24
Peak memory 192940 kb
Host smart-6719c560-9dd2-4166-ae2b-8f8e54b2f3f9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259191442 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.3259191442
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.718841542
Short name T350
Test name
Test status
Simulation time 392578674 ps
CPU time 0.61 seconds
Started Mar 28 12:30:19 PM PDT 24
Finished Mar 28 12:30:21 PM PDT 24
Peak memory 183564 kb
Host smart-b6aca847-af42-4203-86a4-9c8b4e9f18f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718841542 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.718841542
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.4073481080
Short name T413
Test name
Test status
Simulation time 2412729653 ps
CPU time 3.33 seconds
Started Mar 28 12:30:29 PM PDT 24
Finished Mar 28 12:30:33 PM PDT 24
Peak memory 194240 kb
Host smart-03e1761b-8e28-4253-ac28-06ab1e0adf63
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073481080 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.ao
n_timer_same_csr_outstanding.4073481080
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.1650465412
Short name T369
Test name
Test status
Simulation time 569611642 ps
CPU time 2.29 seconds
Started Mar 28 12:30:18 PM PDT 24
Finished Mar 28 12:30:20 PM PDT 24
Peak memory 198492 kb
Host smart-d88deb14-3773-4247-b6ad-76ff215e1ad1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650465412 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.1650465412
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.3671058219
Short name T419
Test name
Test status
Simulation time 3825766501 ps
CPU time 3.79 seconds
Started Mar 28 12:29:55 PM PDT 24
Finished Mar 28 12:29:59 PM PDT 24
Peak memory 196624 kb
Host smart-90cc89d8-3cdd-44cc-8b20-78089c17bef0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671058219 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_t
l_intg_err.3671058219
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.2785599305
Short name T326
Test name
Test status
Simulation time 468017330 ps
CPU time 0.99 seconds
Started Mar 28 12:29:54 PM PDT 24
Finished Mar 28 12:29:56 PM PDT 24
Peak memory 195984 kb
Host smart-e07c07c8-7a89-4082-8d67-ecce5281b86f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785599305 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.2785599305
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.1897890158
Short name T33
Test name
Test status
Simulation time 420289358 ps
CPU time 1.28 seconds
Started Mar 28 12:30:33 PM PDT 24
Finished Mar 28 12:30:34 PM PDT 24
Peak memory 192796 kb
Host smart-9329a9ca-f163-475b-9b35-7b188a8961eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897890158 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.1897890158
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.3426192268
Short name T400
Test name
Test status
Simulation time 421277573 ps
CPU time 0.69 seconds
Started Mar 28 12:30:20 PM PDT 24
Finished Mar 28 12:30:21 PM PDT 24
Peak memory 183504 kb
Host smart-c09496ad-d44b-4fba-af7d-48390f9d3aa2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426192268 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.3426192268
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.1040766443
Short name T399
Test name
Test status
Simulation time 2042070657 ps
CPU time 1.38 seconds
Started Mar 28 12:30:30 PM PDT 24
Finished Mar 28 12:30:31 PM PDT 24
Peak memory 183656 kb
Host smart-8a1c4aee-c912-4b54-9a93-a331d09034ac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040766443 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao
n_timer_same_csr_outstanding.1040766443
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.3820741645
Short name T390
Test name
Test status
Simulation time 389297160 ps
CPU time 2.75 seconds
Started Mar 28 12:30:36 PM PDT 24
Finished Mar 28 12:30:39 PM PDT 24
Peak memory 198444 kb
Host smart-c750c486-86f0-4f3f-81e1-839d9466d908
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820741645 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.3820741645
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.3623562769
Short name T101
Test name
Test status
Simulation time 8976963736 ps
CPU time 3.18 seconds
Started Mar 28 12:30:09 PM PDT 24
Finished Mar 28 12:30:13 PM PDT 24
Peak memory 197608 kb
Host smart-b5f293e2-15fe-4618-b57d-bd74a7c0c585
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623562769 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_t
l_intg_err.3623562769
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.1861914818
Short name T104
Test name
Test status
Simulation time 472257248 ps
CPU time 0.77 seconds
Started Mar 28 12:29:48 PM PDT 24
Finished Mar 28 12:29:49 PM PDT 24
Peak memory 183556 kb
Host smart-1ac2f403-173b-445e-863e-666ee2a3016b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861914818 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_a
liasing.1861914818
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.463091812
Short name T66
Test name
Test status
Simulation time 6797909446 ps
CPU time 13.11 seconds
Started Mar 28 12:29:47 PM PDT 24
Finished Mar 28 12:30:01 PM PDT 24
Peak memory 192284 kb
Host smart-73f978ea-942a-4d48-9d9d-02341d72ed78
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463091812 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_bi
t_bash.463091812
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.2682717145
Short name T303
Test name
Test status
Simulation time 763726444 ps
CPU time 0.98 seconds
Started Mar 28 12:29:47 PM PDT 24
Finished Mar 28 12:29:49 PM PDT 24
Peak memory 183800 kb
Host smart-44921185-4de4-4091-b5b6-0f7dbca9d229
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682717145 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_h
w_reset.2682717145
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.958588309
Short name T358
Test name
Test status
Simulation time 654678757 ps
CPU time 0.97 seconds
Started Mar 28 12:30:13 PM PDT 24
Finished Mar 28 12:30:15 PM PDT 24
Peak memory 198216 kb
Host smart-e6daddc2-b4c6-4772-92b3-29354cd23f3c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958588309 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.958588309
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.1940085941
Short name T68
Test name
Test status
Simulation time 420620604 ps
CPU time 0.71 seconds
Started Mar 28 12:29:49 PM PDT 24
Finished Mar 28 12:29:50 PM PDT 24
Peak memory 183740 kb
Host smart-438f7c0e-6c80-4325-b306-9c1b282edcce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940085941 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.1940085941
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.2470322165
Short name T302
Test name
Test status
Simulation time 370007127 ps
CPU time 0.7 seconds
Started Mar 28 12:29:49 PM PDT 24
Finished Mar 28 12:29:51 PM PDT 24
Peak memory 181556 kb
Host smart-3b085ea6-f9b6-4646-beaa-e56c6a87eadf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470322165 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.2470322165
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.4134415794
Short name T293
Test name
Test status
Simulation time 481747813 ps
CPU time 0.92 seconds
Started Mar 28 12:30:17 PM PDT 24
Finished Mar 28 12:30:19 PM PDT 24
Peak memory 183508 kb
Host smart-b7ac6186-662d-4511-ac99-3def874fc4cd
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134415794 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_t
imer_mem_partial_access.4134415794
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.419927744
Short name T333
Test name
Test status
Simulation time 459661990 ps
CPU time 1.21 seconds
Started Mar 28 12:29:57 PM PDT 24
Finished Mar 28 12:29:59 PM PDT 24
Peak memory 183528 kb
Host smart-f5d1b3bb-2a5c-43ba-b9f2-902cf00b1b23
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419927744 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_wa
lk.419927744
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.3227456368
Short name T370
Test name
Test status
Simulation time 1209285370 ps
CPU time 0.74 seconds
Started Mar 28 12:30:05 PM PDT 24
Finished Mar 28 12:30:06 PM PDT 24
Peak memory 183488 kb
Host smart-2e083c81-4386-4f9d-9feb-ab22e9b39ce2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227456368 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon
_timer_same_csr_outstanding.3227456368
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.3875825101
Short name T289
Test name
Test status
Simulation time 938500257 ps
CPU time 2.57 seconds
Started Mar 28 12:30:13 PM PDT 24
Finished Mar 28 12:30:16 PM PDT 24
Peak memory 198416 kb
Host smart-38be272b-4420-4c52-bcd5-584c90d13129
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875825101 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.3875825101
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.3626612857
Short name T417
Test name
Test status
Simulation time 4374474356 ps
CPU time 7.37 seconds
Started Mar 28 12:29:49 PM PDT 24
Finished Mar 28 12:29:57 PM PDT 24
Peak memory 194416 kb
Host smart-0d7beeec-96b9-40bf-b03e-9db54a4b555d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626612857 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl
_intg_err.3626612857
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.1576666163
Short name T424
Test name
Test status
Simulation time 418907598 ps
CPU time 1.16 seconds
Started Mar 28 12:30:29 PM PDT 24
Finished Mar 28 12:30:30 PM PDT 24
Peak memory 183468 kb
Host smart-c4774c93-8e1a-4bfe-9a98-7ae81bd2d39f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576666163 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.1576666163
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.223339105
Short name T387
Test name
Test status
Simulation time 519467782 ps
CPU time 0.73 seconds
Started Mar 28 12:30:05 PM PDT 24
Finished Mar 28 12:30:06 PM PDT 24
Peak memory 183224 kb
Host smart-71b3293b-8b8c-42f6-9ff4-364be6d798d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223339105 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.223339105
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.1380187198
Short name T298
Test name
Test status
Simulation time 419973956 ps
CPU time 0.9 seconds
Started Mar 28 12:30:26 PM PDT 24
Finished Mar 28 12:30:28 PM PDT 24
Peak memory 183504 kb
Host smart-9a3ef9ea-6f7b-460f-a3b0-481bd2c729a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380187198 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.1380187198
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.573008979
Short name T338
Test name
Test status
Simulation time 382132405 ps
CPU time 0.68 seconds
Started Mar 28 12:30:13 PM PDT 24
Finished Mar 28 12:30:15 PM PDT 24
Peak memory 183436 kb
Host smart-dcf70fd9-858a-4e6d-8e35-9094f2df1b36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573008979 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.573008979
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.3206944197
Short name T414
Test name
Test status
Simulation time 308847165 ps
CPU time 0.81 seconds
Started Mar 28 12:30:25 PM PDT 24
Finished Mar 28 12:30:28 PM PDT 24
Peak memory 183656 kb
Host smart-728dbe19-3443-4a29-aec7-8b73fd5ceec2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206944197 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.3206944197
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.2173033469
Short name T341
Test name
Test status
Simulation time 351118919 ps
CPU time 1.1 seconds
Started Mar 28 12:30:27 PM PDT 24
Finished Mar 28 12:30:29 PM PDT 24
Peak memory 183516 kb
Host smart-9dc1f058-adff-420c-855f-3e8998d2213d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173033469 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.2173033469
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.900335762
Short name T329
Test name
Test status
Simulation time 483232987 ps
CPU time 0.83 seconds
Started Mar 28 12:29:50 PM PDT 24
Finished Mar 28 12:29:51 PM PDT 24
Peak memory 183556 kb
Host smart-15f423da-dc19-4938-acfc-4b24e67916b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900335762 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.900335762
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.4089742723
Short name T310
Test name
Test status
Simulation time 377641383 ps
CPU time 0.85 seconds
Started Mar 28 12:30:16 PM PDT 24
Finished Mar 28 12:30:17 PM PDT 24
Peak memory 183516 kb
Host smart-eccd636c-0b33-4c83-9a92-0ec1c736c113
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089742723 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.4089742723
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.3831656949
Short name T344
Test name
Test status
Simulation time 506685636 ps
CPU time 1.4 seconds
Started Mar 28 12:30:24 PM PDT 24
Finished Mar 28 12:30:26 PM PDT 24
Peak memory 183560 kb
Host smart-cb0253fd-1c3b-4fff-aa3b-7a6ee1ba6439
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831656949 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.3831656949
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.4123838369
Short name T328
Test name
Test status
Simulation time 410398544 ps
CPU time 0.85 seconds
Started Mar 28 12:29:55 PM PDT 24
Finished Mar 28 12:29:56 PM PDT 24
Peak memory 182744 kb
Host smart-b4c00dfa-6b78-4b13-b9b3-ad4aa1c29631
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123838369 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.4123838369
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.3433172323
Short name T425
Test name
Test status
Simulation time 566134772 ps
CPU time 0.84 seconds
Started Mar 28 12:30:20 PM PDT 24
Finished Mar 28 12:30:22 PM PDT 24
Peak memory 183588 kb
Host smart-f4bc6fac-341d-43f1-836b-c557c21889b8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433172323 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_a
liasing.3433172323
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.2794592498
Short name T363
Test name
Test status
Simulation time 14334399775 ps
CPU time 4.05 seconds
Started Mar 28 12:29:52 PM PDT 24
Finished Mar 28 12:29:56 PM PDT 24
Peak memory 191936 kb
Host smart-6c5bb25b-c7b4-47be-8f41-aec68a7662a2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794592498 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_b
it_bash.2794592498
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.359883383
Short name T366
Test name
Test status
Simulation time 822713708 ps
CPU time 0.86 seconds
Started Mar 28 12:29:57 PM PDT 24
Finished Mar 28 12:29:58 PM PDT 24
Peak memory 183352 kb
Host smart-fd3feb5b-8f9b-4527-a851-01740e13a62d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359883383 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_hw
_reset.359883383
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.3003103353
Short name T377
Test name
Test status
Simulation time 466901756 ps
CPU time 0.91 seconds
Started Mar 28 12:29:51 PM PDT 24
Finished Mar 28 12:29:53 PM PDT 24
Peak memory 195932 kb
Host smart-0f566abf-dd8c-44ad-874a-b82ffb6c94f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003103353 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.3003103353
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.3867405486
Short name T362
Test name
Test status
Simulation time 310622484 ps
CPU time 0.67 seconds
Started Mar 28 12:29:52 PM PDT 24
Finished Mar 28 12:29:52 PM PDT 24
Peak memory 183656 kb
Host smart-18a3c285-f2fe-4635-abed-3ec62d4c5b44
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867405486 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.3867405486
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.1253361781
Short name T317
Test name
Test status
Simulation time 396937289 ps
CPU time 0.69 seconds
Started Mar 28 12:29:46 PM PDT 24
Finished Mar 28 12:29:47 PM PDT 24
Peak memory 182960 kb
Host smart-f0ee65d9-d753-444f-8075-e4d05a7f24b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253361781 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.1253361781
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.1533070285
Short name T408
Test name
Test status
Simulation time 393377048 ps
CPU time 0.65 seconds
Started Mar 28 12:30:09 PM PDT 24
Finished Mar 28 12:30:10 PM PDT 24
Peak memory 183416 kb
Host smart-33f3db12-37d6-4c2b-b31e-8b54cb4b3d9f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533070285 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_t
imer_mem_partial_access.1533070285
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.3793885946
Short name T393
Test name
Test status
Simulation time 481979780 ps
CPU time 0.66 seconds
Started Mar 28 12:29:53 PM PDT 24
Finished Mar 28 12:29:53 PM PDT 24
Peak memory 183520 kb
Host smart-288ca80d-9f6c-4e85-a670-d7cc2c916658
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793885946 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_w
alk.3793885946
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.3527478047
Short name T70
Test name
Test status
Simulation time 1455124813 ps
CPU time 2.5 seconds
Started Mar 28 12:29:51 PM PDT 24
Finished Mar 28 12:29:54 PM PDT 24
Peak memory 193280 kb
Host smart-29925508-9743-4c1f-9253-3d425f7914ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527478047 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon
_timer_same_csr_outstanding.3527478047
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.2913493687
Short name T352
Test name
Test status
Simulation time 307040690 ps
CPU time 1.72 seconds
Started Mar 28 12:29:48 PM PDT 24
Finished Mar 28 12:29:50 PM PDT 24
Peak memory 198552 kb
Host smart-5898913d-5795-4a59-827b-343c6fe776c1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913493687 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.2913493687
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.3829405248
Short name T376
Test name
Test status
Simulation time 4397598544 ps
CPU time 6.42 seconds
Started Mar 28 12:29:48 PM PDT 24
Finished Mar 28 12:29:54 PM PDT 24
Peak memory 196432 kb
Host smart-fd0fc02a-14f5-42f3-879d-6faf9d73359b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829405248 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl
_intg_err.3829405248
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.1787830452
Short name T345
Test name
Test status
Simulation time 499247396 ps
CPU time 1.4 seconds
Started Mar 28 12:30:21 PM PDT 24
Finished Mar 28 12:30:23 PM PDT 24
Peak memory 183560 kb
Host smart-781f5f9c-27b6-44e7-974d-c6b61e6ce9e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787830452 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.1787830452
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.2643963723
Short name T416
Test name
Test status
Simulation time 543051023 ps
CPU time 0.72 seconds
Started Mar 28 12:30:27 PM PDT 24
Finished Mar 28 12:30:28 PM PDT 24
Peak memory 183492 kb
Host smart-794760ce-1bd7-4d43-8fc7-652535d17307
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643963723 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.2643963723
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.1197149513
Short name T327
Test name
Test status
Simulation time 330036608 ps
CPU time 0.77 seconds
Started Mar 28 12:30:06 PM PDT 24
Finished Mar 28 12:30:08 PM PDT 24
Peak memory 183508 kb
Host smart-1229ee95-3299-4283-a57b-a5ff4b4b7988
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197149513 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.1197149513
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.1191063314
Short name T314
Test name
Test status
Simulation time 292702625 ps
CPU time 0.98 seconds
Started Mar 28 12:30:21 PM PDT 24
Finished Mar 28 12:30:22 PM PDT 24
Peak memory 183500 kb
Host smart-ed6145fa-0cc1-47b2-b9dd-14ca549a4dfa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191063314 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.1191063314
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.139092271
Short name T351
Test name
Test status
Simulation time 500064964 ps
CPU time 0.65 seconds
Started Mar 28 12:30:06 PM PDT 24
Finished Mar 28 12:30:07 PM PDT 24
Peak memory 183500 kb
Host smart-8441aebe-4ef1-48cf-85bf-e3bcbc1840cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139092271 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.139092271
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.1357578586
Short name T301
Test name
Test status
Simulation time 306666121 ps
CPU time 0.65 seconds
Started Mar 28 12:30:25 PM PDT 24
Finished Mar 28 12:30:28 PM PDT 24
Peak memory 183528 kb
Host smart-78e338c7-fa9d-4b04-aba9-76194097c640
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357578586 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.1357578586
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.543228786
Short name T403
Test name
Test status
Simulation time 318606976 ps
CPU time 0.81 seconds
Started Mar 28 12:30:25 PM PDT 24
Finished Mar 28 12:30:28 PM PDT 24
Peak memory 183532 kb
Host smart-be6d2b4d-df82-4fb5-8ab6-4893aa7e2e8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543228786 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.543228786
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.1666797048
Short name T361
Test name
Test status
Simulation time 386110419 ps
CPU time 1.04 seconds
Started Mar 28 12:30:23 PM PDT 24
Finished Mar 28 12:30:25 PM PDT 24
Peak memory 183432 kb
Host smart-5b4980f2-0d3d-45ef-b424-e9fc03b4f64c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666797048 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.1666797048
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.4259749964
Short name T374
Test name
Test status
Simulation time 414123349 ps
CPU time 1.16 seconds
Started Mar 28 12:30:20 PM PDT 24
Finished Mar 28 12:30:22 PM PDT 24
Peak memory 183420 kb
Host smart-cdc4be12-6962-4448-86dd-0adea85ccec0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259749964 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.4259749964
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.3937997769
Short name T405
Test name
Test status
Simulation time 284978134 ps
CPU time 0.73 seconds
Started Mar 28 12:30:24 PM PDT 24
Finished Mar 28 12:30:25 PM PDT 24
Peak memory 183516 kb
Host smart-39d91bb1-8177-4465-a2d4-766b80c4daaf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937997769 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.3937997769
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.1520342719
Short name T62
Test name
Test status
Simulation time 405864778 ps
CPU time 1.02 seconds
Started Mar 28 12:30:05 PM PDT 24
Finished Mar 28 12:30:06 PM PDT 24
Peak memory 193732 kb
Host smart-569ed111-c3a0-4b64-ba29-2efc1672b6a4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520342719 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_a
liasing.1520342719
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.181093249
Short name T365
Test name
Test status
Simulation time 7512663885 ps
CPU time 2.81 seconds
Started Mar 28 12:30:11 PM PDT 24
Finished Mar 28 12:30:15 PM PDT 24
Peak memory 191112 kb
Host smart-7d36a01f-c46b-4a16-830c-0f5211b64250
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181093249 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_bi
t_bash.181093249
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.801399219
Short name T60
Test name
Test status
Simulation time 1328104383 ps
CPU time 0.87 seconds
Started Mar 28 12:30:04 PM PDT 24
Finished Mar 28 12:30:06 PM PDT 24
Peak memory 192308 kb
Host smart-e95dc6ea-0c67-48fa-a030-27f7787d0f93
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801399219 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_hw
_reset.801399219
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.4025763405
Short name T309
Test name
Test status
Simulation time 690561524 ps
CPU time 0.96 seconds
Started Mar 28 12:29:45 PM PDT 24
Finished Mar 28 12:29:46 PM PDT 24
Peak memory 196832 kb
Host smart-53dc29c3-a12b-421f-81de-0a5e7751d219
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025763405 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.4025763405
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.3468004547
Short name T58
Test name
Test status
Simulation time 353021484 ps
CPU time 0.75 seconds
Started Mar 28 12:29:49 PM PDT 24
Finished Mar 28 12:29:50 PM PDT 24
Peak memory 183596 kb
Host smart-1c6c07bb-3fc5-4218-b2a9-bd62e71ec991
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468004547 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.3468004547
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.1743876444
Short name T360
Test name
Test status
Simulation time 520490772 ps
CPU time 0.77 seconds
Started Mar 28 12:30:21 PM PDT 24
Finished Mar 28 12:30:22 PM PDT 24
Peak memory 183444 kb
Host smart-4583c6e6-ff46-4cd4-9889-b72db2bcb367
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743876444 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.1743876444
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.582216706
Short name T426
Test name
Test status
Simulation time 334467612 ps
CPU time 0.96 seconds
Started Mar 28 12:29:50 PM PDT 24
Finished Mar 28 12:29:52 PM PDT 24
Peak memory 183132 kb
Host smart-51d5ce72-2029-4382-8c4a-e8ee92aae75f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582216706 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_ti
mer_mem_partial_access.582216706
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.3891557062
Short name T389
Test name
Test status
Simulation time 340962188 ps
CPU time 1.04 seconds
Started Mar 28 12:29:50 PM PDT 24
Finished Mar 28 12:29:52 PM PDT 24
Peak memory 182736 kb
Host smart-233e34b0-e049-44bc-a984-c4485ded7233
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891557062 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_w
alk.3891557062
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.3637198215
Short name T75
Test name
Test status
Simulation time 2290193584 ps
CPU time 2.06 seconds
Started Mar 28 12:29:43 PM PDT 24
Finished Mar 28 12:29:45 PM PDT 24
Peak memory 193960 kb
Host smart-aea1ec44-4b58-4d3f-acf7-0f60ef86b77c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637198215 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon
_timer_same_csr_outstanding.3637198215
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.4112430310
Short name T319
Test name
Test status
Simulation time 816957383 ps
CPU time 1.93 seconds
Started Mar 28 12:29:51 PM PDT 24
Finished Mar 28 12:29:54 PM PDT 24
Peak memory 198196 kb
Host smart-3b063f37-6c37-4b8e-acd0-53429a8e2655
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112430310 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.4112430310
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.3964421299
Short name T99
Test name
Test status
Simulation time 9240246793 ps
CPU time 3.69 seconds
Started Mar 28 12:29:51 PM PDT 24
Finished Mar 28 12:29:55 PM PDT 24
Peak memory 197688 kb
Host smart-6452a2e2-ecf3-459c-acd7-7a728ee63604
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964421299 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl
_intg_err.3964421299
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.1031950184
Short name T305
Test name
Test status
Simulation time 517451020 ps
CPU time 1.32 seconds
Started Mar 28 12:30:27 PM PDT 24
Finished Mar 28 12:30:29 PM PDT 24
Peak memory 182172 kb
Host smart-7ab21697-f92a-4b13-bd87-ea8c58941a9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031950184 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.1031950184
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.2979791232
Short name T355
Test name
Test status
Simulation time 302349078 ps
CPU time 0.97 seconds
Started Mar 28 12:30:20 PM PDT 24
Finished Mar 28 12:30:22 PM PDT 24
Peak memory 183424 kb
Host smart-3e1fb7e9-9a8b-4254-a859-8e8bf7247b44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979791232 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.2979791232
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.1444603785
Short name T299
Test name
Test status
Simulation time 295189956 ps
CPU time 0.92 seconds
Started Mar 28 12:30:27 PM PDT 24
Finished Mar 28 12:30:29 PM PDT 24
Peak memory 183428 kb
Host smart-30096e77-092a-4bf6-b825-4c76e78dae3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444603785 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.1444603785
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.376515529
Short name T401
Test name
Test status
Simulation time 324848673 ps
CPU time 0.66 seconds
Started Mar 28 12:30:09 PM PDT 24
Finished Mar 28 12:30:10 PM PDT 24
Peak memory 183432 kb
Host smart-ed5bac76-b9a0-4647-a5a9-68295c7c3216
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376515529 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.376515529
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.4092172594
Short name T391
Test name
Test status
Simulation time 299101719 ps
CPU time 0.67 seconds
Started Mar 28 12:30:20 PM PDT 24
Finished Mar 28 12:30:21 PM PDT 24
Peak memory 183564 kb
Host smart-0f445017-c344-46dc-a3d1-49a9b05c806b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092172594 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.4092172594
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.2228450330
Short name T288
Test name
Test status
Simulation time 455111904 ps
CPU time 0.73 seconds
Started Mar 28 12:30:25 PM PDT 24
Finished Mar 28 12:30:28 PM PDT 24
Peak memory 182216 kb
Host smart-5aabaeb2-d864-4b38-a5d3-5f7052c51e85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228450330 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.2228450330
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.3988711210
Short name T346
Test name
Test status
Simulation time 495523867 ps
CPU time 1.34 seconds
Started Mar 28 12:30:25 PM PDT 24
Finished Mar 28 12:30:29 PM PDT 24
Peak memory 182212 kb
Host smart-befe36be-fb47-4434-89bc-4a530d2a4daf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988711210 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.3988711210
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.3646617564
Short name T423
Test name
Test status
Simulation time 429303265 ps
CPU time 0.8 seconds
Started Mar 28 12:30:18 PM PDT 24
Finished Mar 28 12:30:20 PM PDT 24
Peak memory 183508 kb
Host smart-de10e86a-7c7d-439f-af62-2cad1b862cdd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646617564 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.3646617564
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.3874045648
Short name T332
Test name
Test status
Simulation time 521476465 ps
CPU time 0.93 seconds
Started Mar 28 12:30:38 PM PDT 24
Finished Mar 28 12:30:39 PM PDT 24
Peak memory 183500 kb
Host smart-6a41d9ab-a02f-4bfb-afb7-0cf8caefbbd1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874045648 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.3874045648
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.1714759970
Short name T320
Test name
Test status
Simulation time 411670974 ps
CPU time 0.73 seconds
Started Mar 28 12:30:25 PM PDT 24
Finished Mar 28 12:30:26 PM PDT 24
Peak memory 183500 kb
Host smart-9283e72a-d858-437e-b199-263618317337
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714759970 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.1714759970
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.1471548973
Short name T396
Test name
Test status
Simulation time 391686948 ps
CPU time 1.24 seconds
Started Mar 28 12:29:56 PM PDT 24
Finished Mar 28 12:29:57 PM PDT 24
Peak memory 195736 kb
Host smart-442aa111-81db-40c7-a84e-afcda9e9b806
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471548973 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.1471548973
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.2225119086
Short name T307
Test name
Test status
Simulation time 451871049 ps
CPU time 1.33 seconds
Started Mar 28 12:29:46 PM PDT 24
Finished Mar 28 12:29:48 PM PDT 24
Peak memory 182824 kb
Host smart-cc612897-4895-48e5-aa66-9d2a69a77554
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225119086 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.2225119086
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.935652640
Short name T372
Test name
Test status
Simulation time 449983153 ps
CPU time 0.77 seconds
Started Mar 28 12:30:02 PM PDT 24
Finished Mar 28 12:30:03 PM PDT 24
Peak memory 183516 kb
Host smart-1fbd3c17-0b50-4a79-9be7-a2b8f74f3a9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935652640 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.935652640
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.1744014450
Short name T379
Test name
Test status
Simulation time 984576651 ps
CPU time 1.07 seconds
Started Mar 28 12:29:45 PM PDT 24
Finished Mar 28 12:29:46 PM PDT 24
Peak memory 192844 kb
Host smart-aa9a750b-9cec-48f0-a36e-de6e405d809a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744014450 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon
_timer_same_csr_outstanding.1744014450
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.3079657949
Short name T294
Test name
Test status
Simulation time 489124624 ps
CPU time 2.49 seconds
Started Mar 28 12:29:50 PM PDT 24
Finished Mar 28 12:29:54 PM PDT 24
Peak memory 198128 kb
Host smart-3162fdee-75bd-47f1-9b27-f9e7758961fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079657949 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.3079657949
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.918182749
Short name T336
Test name
Test status
Simulation time 4457234975 ps
CPU time 2.45 seconds
Started Mar 28 12:30:09 PM PDT 24
Finished Mar 28 12:30:12 PM PDT 24
Peak memory 197504 kb
Host smart-8602ba2f-7a0d-4580-9c2f-9ab73aab1214
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918182749 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_
intg_err.918182749
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.3050816029
Short name T308
Test name
Test status
Simulation time 497799330 ps
CPU time 1.48 seconds
Started Mar 28 12:29:51 PM PDT 24
Finished Mar 28 12:29:53 PM PDT 24
Peak memory 194996 kb
Host smart-b0c0e3ac-a6b3-4dea-9d69-c16748321227
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050816029 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.3050816029
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.2598603068
Short name T385
Test name
Test status
Simulation time 331818239 ps
CPU time 1.09 seconds
Started Mar 28 12:29:54 PM PDT 24
Finished Mar 28 12:29:55 PM PDT 24
Peak memory 183748 kb
Host smart-9b94fad6-1ddc-45d4-b737-4b4deccd4e13
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598603068 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.2598603068
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.2270441184
Short name T322
Test name
Test status
Simulation time 387304470 ps
CPU time 1.24 seconds
Started Mar 28 12:30:11 PM PDT 24
Finished Mar 28 12:30:13 PM PDT 24
Peak memory 182520 kb
Host smart-55243681-fdc4-4c67-9a24-308f22a49815
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270441184 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.2270441184
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.2086176869
Short name T337
Test name
Test status
Simulation time 2437378061 ps
CPU time 6.79 seconds
Started Mar 28 12:29:51 PM PDT 24
Finished Mar 28 12:29:59 PM PDT 24
Peak memory 194364 kb
Host smart-d698eb51-3771-4ed9-8ff6-fffe69edaeea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086176869 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon
_timer_same_csr_outstanding.2086176869
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.1342867744
Short name T342
Test name
Test status
Simulation time 541095910 ps
CPU time 1.35 seconds
Started Mar 28 12:29:47 PM PDT 24
Finished Mar 28 12:29:49 PM PDT 24
Peak memory 196200 kb
Host smart-6f59add7-7502-469b-bc8e-60b281c837ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342867744 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.1342867744
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.575689875
Short name T98
Test name
Test status
Simulation time 4068488255 ps
CPU time 3.81 seconds
Started Mar 28 12:29:47 PM PDT 24
Finished Mar 28 12:29:52 PM PDT 24
Peak memory 195780 kb
Host smart-0ea57876-0c95-483c-bda4-8562addc9151
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575689875 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_
intg_err.575689875
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.4038874411
Short name T32
Test name
Test status
Simulation time 562742331 ps
CPU time 1.17 seconds
Started Mar 28 12:29:58 PM PDT 24
Finished Mar 28 12:30:00 PM PDT 24
Peak memory 194412 kb
Host smart-82875898-0c41-451c-a3db-e68e4845b80c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038874411 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.4038874411
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.1264426414
Short name T71
Test name
Test status
Simulation time 406499042 ps
CPU time 0.68 seconds
Started Mar 28 12:29:51 PM PDT 24
Finished Mar 28 12:29:52 PM PDT 24
Peak memory 181716 kb
Host smart-a00c1d24-857d-456e-8eab-32819cccf6b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264426414 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.1264426414
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.1700739285
Short name T410
Test name
Test status
Simulation time 526969563 ps
CPU time 0.68 seconds
Started Mar 28 12:30:12 PM PDT 24
Finished Mar 28 12:30:13 PM PDT 24
Peak memory 183492 kb
Host smart-95dccea5-c609-4138-820f-5b899556438f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700739285 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.1700739285
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.2320711050
Short name T334
Test name
Test status
Simulation time 1512284583 ps
CPU time 1.84 seconds
Started Mar 28 12:29:50 PM PDT 24
Finished Mar 28 12:29:53 PM PDT 24
Peak memory 192856 kb
Host smart-5310a82d-fdd5-4c07-bf80-d01b5f00dce4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320711050 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon
_timer_same_csr_outstanding.2320711050
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.434474817
Short name T304
Test name
Test status
Simulation time 364494828 ps
CPU time 1.46 seconds
Started Mar 28 12:29:51 PM PDT 24
Finished Mar 28 12:29:53 PM PDT 24
Peak memory 196348 kb
Host smart-ac40d4ac-af93-4884-9001-ebdc6b7d14e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434474817 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.434474817
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.1732391332
Short name T339
Test name
Test status
Simulation time 4689100998 ps
CPU time 1.8 seconds
Started Mar 28 12:30:13 PM PDT 24
Finished Mar 28 12:30:15 PM PDT 24
Peak memory 197324 kb
Host smart-5385eb1c-9c12-497a-9a7e-ffe513fb87f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732391332 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl
_intg_err.1732391332
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.1178038142
Short name T103
Test name
Test status
Simulation time 527777236 ps
CPU time 0.95 seconds
Started Mar 28 12:30:08 PM PDT 24
Finished Mar 28 12:30:09 PM PDT 24
Peak memory 196020 kb
Host smart-f2b22555-5ad7-49fa-8a7c-793f6c384210
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178038142 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.1178038142
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.4097131650
Short name T325
Test name
Test status
Simulation time 356638742 ps
CPU time 0.66 seconds
Started Mar 28 12:29:47 PM PDT 24
Finished Mar 28 12:29:49 PM PDT 24
Peak memory 183612 kb
Host smart-6b28edf7-1a5b-48f4-9a9f-21f5453c47bc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097131650 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.4097131650
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.2791143764
Short name T384
Test name
Test status
Simulation time 378993307 ps
CPU time 1.16 seconds
Started Mar 28 12:30:00 PM PDT 24
Finished Mar 28 12:30:01 PM PDT 24
Peak memory 183208 kb
Host smart-af16aca6-c180-4093-81a5-49c879218edb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791143764 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.2791143764
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.730417982
Short name T324
Test name
Test status
Simulation time 1080295901 ps
CPU time 0.95 seconds
Started Mar 28 12:30:05 PM PDT 24
Finished Mar 28 12:30:06 PM PDT 24
Peak memory 192988 kb
Host smart-39074c26-d028-4f95-818a-436ae4ea50ff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730417982 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_
timer_same_csr_outstanding.730417982
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.220256267
Short name T409
Test name
Test status
Simulation time 419613330 ps
CPU time 1.79 seconds
Started Mar 28 12:30:06 PM PDT 24
Finished Mar 28 12:30:10 PM PDT 24
Peak memory 197416 kb
Host smart-0e7d473f-a91e-4bb6-8632-91cc9fb11a22
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220256267 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.220256267
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.4200898906
Short name T353
Test name
Test status
Simulation time 4628036395 ps
CPU time 3.06 seconds
Started Mar 28 12:30:06 PM PDT 24
Finished Mar 28 12:30:09 PM PDT 24
Peak memory 197412 kb
Host smart-81106caa-0bc8-4110-8f57-0e336b8da75b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200898906 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl
_intg_err.4200898906
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.1440613369
Short name T383
Test name
Test status
Simulation time 574435820 ps
CPU time 1.12 seconds
Started Mar 28 12:29:46 PM PDT 24
Finished Mar 28 12:29:47 PM PDT 24
Peak memory 196192 kb
Host smart-75ceb949-5648-404c-ad23-ecfdd7525521
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440613369 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.1440613369
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.841904357
Short name T64
Test name
Test status
Simulation time 351333281 ps
CPU time 0.73 seconds
Started Mar 28 12:29:48 PM PDT 24
Finished Mar 28 12:29:49 PM PDT 24
Peak memory 193244 kb
Host smart-fc3d64f3-d038-4abf-83ff-37f37878b04b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841904357 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.841904357
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.2643279198
Short name T290
Test name
Test status
Simulation time 468983295 ps
CPU time 0.7 seconds
Started Mar 28 12:29:56 PM PDT 24
Finished Mar 28 12:29:57 PM PDT 24
Peak memory 183516 kb
Host smart-7b680a0e-9cf6-437a-b4b9-3abf59f92ccf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643279198 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.2643279198
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.65615647
Short name T72
Test name
Test status
Simulation time 2581325330 ps
CPU time 1.87 seconds
Started Mar 28 12:30:07 PM PDT 24
Finished Mar 28 12:30:09 PM PDT 24
Peak memory 183800 kb
Host smart-d4e9f574-250c-4d80-a184-6dd900143630
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65615647 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_t
imer_same_csr_outstanding.65615647
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.2832731131
Short name T415
Test name
Test status
Simulation time 446852562 ps
CPU time 2.23 seconds
Started Mar 28 12:29:59 PM PDT 24
Finished Mar 28 12:30:02 PM PDT 24
Peak memory 197620 kb
Host smart-11dea470-1664-4e44-96d3-6c765c3ac1bf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832731131 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.2832731131
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.2583346412
Short name T359
Test name
Test status
Simulation time 4414102108 ps
CPU time 2.53 seconds
Started Mar 28 12:30:10 PM PDT 24
Finished Mar 28 12:30:13 PM PDT 24
Peak memory 197568 kb
Host smart-4c0ae5ca-062e-4ae8-8108-bf908dc2a641
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583346412 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl
_intg_err.2583346412
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_jump.612790163
Short name T198
Test name
Test status
Simulation time 501700496 ps
CPU time 0.77 seconds
Started Mar 28 12:47:54 PM PDT 24
Finished Mar 28 12:47:55 PM PDT 24
Peak memory 183328 kb
Host smart-4fed09af-16ed-40a3-97db-db316c2fb135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612790163 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.612790163
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.4205933189
Short name T4
Test name
Test status
Simulation time 25461115423 ps
CPU time 19.47 seconds
Started Mar 28 12:47:56 PM PDT 24
Finished Mar 28 12:48:16 PM PDT 24
Peak memory 191768 kb
Host smart-9bef7f80-82df-4333-a6c3-a47fa6a9a3ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205933189 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.4205933189
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.2401572048
Short name T53
Test name
Test status
Simulation time 450540738 ps
CPU time 0.73 seconds
Started Mar 28 12:47:57 PM PDT 24
Finished Mar 28 12:47:58 PM PDT 24
Peak memory 183508 kb
Host smart-8d8826bc-0714-4258-9ca2-6022e2057eb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401572048 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.2401572048
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.2454090942
Short name T154
Test name
Test status
Simulation time 191527479122 ps
CPU time 254.46 seconds
Started Mar 28 12:47:54 PM PDT 24
Finished Mar 28 12:52:08 PM PDT 24
Peak memory 183404 kb
Host smart-fb046f03-697e-4038-9a27-c698e47c2c7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454090942 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_a
ll.2454090942
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.3076602241
Short name T248
Test name
Test status
Simulation time 85747058944 ps
CPU time 257.37 seconds
Started Mar 28 12:47:57 PM PDT 24
Finished Mar 28 12:52:15 PM PDT 24
Peak memory 198372 kb
Host smart-5f184f7c-8aa9-4a3e-87eb-169e7398d605
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076602241 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.3076602241
Directory /workspace/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.aon_timer_jump.2612703567
Short name T173
Test name
Test status
Simulation time 423426928 ps
CPU time 0.73 seconds
Started Mar 28 12:47:54 PM PDT 24
Finished Mar 28 12:47:55 PM PDT 24
Peak memory 183492 kb
Host smart-96a50072-46cd-4fdb-a738-ecba33821ee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612703567 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.2612703567
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.1806120893
Short name T115
Test name
Test status
Simulation time 40201966888 ps
CPU time 12.63 seconds
Started Mar 28 12:47:57 PM PDT 24
Finished Mar 28 12:48:10 PM PDT 24
Peak memory 183564 kb
Host smart-15800027-f136-4aaf-a4d3-7d2ebe9ab64a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806120893 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.1806120893
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.2242247402
Short name T17
Test name
Test status
Simulation time 7807651454 ps
CPU time 11.74 seconds
Started Mar 28 12:47:54 PM PDT 24
Finished Mar 28 12:48:06 PM PDT 24
Peak memory 215208 kb
Host smart-8ca1077a-15b3-429a-897b-cea7a977525f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242247402 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.2242247402
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.3719855544
Short name T244
Test name
Test status
Simulation time 453668112 ps
CPU time 1.25 seconds
Started Mar 28 12:47:54 PM PDT 24
Finished Mar 28 12:47:55 PM PDT 24
Peak memory 183324 kb
Host smart-fd45e833-5086-48e1-8fe3-06683c866b6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719855544 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.3719855544
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.3180536528
Short name T274
Test name
Test status
Simulation time 46800764559 ps
CPU time 20.53 seconds
Started Mar 28 12:47:55 PM PDT 24
Finished Mar 28 12:48:15 PM PDT 24
Peak memory 191660 kb
Host smart-0064f49c-26d2-4b48-99b6-0f822ad0e6aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180536528 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_a
ll.3180536528
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.2085317789
Short name T156
Test name
Test status
Simulation time 9800872540 ps
CPU time 76.27 seconds
Started Mar 28 12:47:58 PM PDT 24
Finished Mar 28 12:49:15 PM PDT 24
Peak memory 198372 kb
Host smart-838e7897-5691-44a4-8bc1-5f303fe68d8d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085317789 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.2085317789
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.aon_timer_jump.1259387642
Short name T236
Test name
Test status
Simulation time 598880429 ps
CPU time 0.71 seconds
Started Mar 28 12:48:08 PM PDT 24
Finished Mar 28 12:48:09 PM PDT 24
Peak memory 183336 kb
Host smart-7653b366-eed3-439f-b10f-e8f08f76cbcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259387642 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.1259387642
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.240720004
Short name T267
Test name
Test status
Simulation time 21306977914 ps
CPU time 34.18 seconds
Started Mar 28 12:48:07 PM PDT 24
Finished Mar 28 12:48:41 PM PDT 24
Peak memory 191772 kb
Host smart-6703c67b-c870-4244-ae13-7b084a053269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240720004 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.240720004
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.1051227096
Short name T216
Test name
Test status
Simulation time 515653182 ps
CPU time 0.86 seconds
Started Mar 28 12:48:08 PM PDT 24
Finished Mar 28 12:48:09 PM PDT 24
Peak memory 183496 kb
Host smart-11f41be7-d8f4-4eaf-a205-6199780d910e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051227096 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.1051227096
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.258795960
Short name T146
Test name
Test status
Simulation time 80827508904 ps
CPU time 101.18 seconds
Started Mar 28 12:48:07 PM PDT 24
Finished Mar 28 12:49:48 PM PDT 24
Peak memory 183588 kb
Host smart-409d14e4-a7bb-49e2-beae-040f2cc5b0e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258795960 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_a
ll.258795960
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_jump.2144844608
Short name T47
Test name
Test status
Simulation time 491017662 ps
CPU time 0.75 seconds
Started Mar 28 12:48:06 PM PDT 24
Finished Mar 28 12:48:07 PM PDT 24
Peak memory 183504 kb
Host smart-35b5ec06-067d-4caf-a210-2fd53db9b938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144844608 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.2144844608
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.3279979831
Short name T190
Test name
Test status
Simulation time 36032872986 ps
CPU time 12.46 seconds
Started Mar 28 12:48:08 PM PDT 24
Finished Mar 28 12:48:21 PM PDT 24
Peak memory 191816 kb
Host smart-9e34b5ac-f2ba-4868-bd80-73dc10726dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279979831 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.3279979831
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.2040267216
Short name T256
Test name
Test status
Simulation time 532574642 ps
CPU time 0.75 seconds
Started Mar 28 12:48:12 PM PDT 24
Finished Mar 28 12:48:14 PM PDT 24
Peak memory 183376 kb
Host smart-3f379141-591b-4a3d-a42d-33e826dafbe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040267216 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.2040267216
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.1080228574
Short name T191
Test name
Test status
Simulation time 266827255735 ps
CPU time 187.07 seconds
Started Mar 28 12:48:12 PM PDT 24
Finished Mar 28 12:51:19 PM PDT 24
Peak memory 183420 kb
Host smart-2b06dffb-8e30-4909-aca4-2c21417e0d15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080228574 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_
all.1080228574
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.1054080614
Short name T79
Test name
Test status
Simulation time 435166092702 ps
CPU time 714.58 seconds
Started Mar 28 12:48:08 PM PDT 24
Finished Mar 28 01:00:03 PM PDT 24
Peak memory 200280 kb
Host smart-2c13692f-a03b-4688-ad79-c94f1268808d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054080614 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand_reset.1054080614
Directory /workspace/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.aon_timer_jump.2931021316
Short name T111
Test name
Test status
Simulation time 659901301 ps
CPU time 0.63 seconds
Started Mar 28 12:48:08 PM PDT 24
Finished Mar 28 12:48:09 PM PDT 24
Peak memory 183504 kb
Host smart-15eb5f94-e014-42a7-aeb4-ff961713abd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931021316 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.2931021316
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.1152759164
Short name T147
Test name
Test status
Simulation time 34503338075 ps
CPU time 26.95 seconds
Started Mar 28 12:48:07 PM PDT 24
Finished Mar 28 12:48:34 PM PDT 24
Peak memory 183400 kb
Host smart-626bc35d-51ff-4d60-97d0-18d1169444cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152759164 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.1152759164
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.2230090166
Short name T213
Test name
Test status
Simulation time 428310570 ps
CPU time 0.73 seconds
Started Mar 28 12:48:14 PM PDT 24
Finished Mar 28 12:48:16 PM PDT 24
Peak memory 183392 kb
Host smart-55decfab-4db3-4b3f-a30e-ce79c7a99191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230090166 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.2230090166
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.3129217489
Short name T195
Test name
Test status
Simulation time 183381266518 ps
CPU time 135.42 seconds
Started Mar 28 12:48:08 PM PDT 24
Finished Mar 28 12:50:24 PM PDT 24
Peak memory 183384 kb
Host smart-372073a0-e3dc-4d37-ba0c-f93953140a72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129217489 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_
all.3129217489
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.2079374395
Short name T273
Test name
Test status
Simulation time 21618631780 ps
CPU time 165.73 seconds
Started Mar 28 12:48:10 PM PDT 24
Finished Mar 28 12:50:57 PM PDT 24
Peak memory 198344 kb
Host smart-e895c2cf-20ea-4f95-a200-d563226e1b22
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079374395 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.2079374395
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_jump.817460769
Short name T30
Test name
Test status
Simulation time 360149953 ps
CPU time 1.06 seconds
Started Mar 28 12:48:08 PM PDT 24
Finished Mar 28 12:48:10 PM PDT 24
Peak memory 183392 kb
Host smart-7a335920-952c-4ecc-ba2f-ce7f45ccf0aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817460769 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.817460769
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.3656184635
Short name T181
Test name
Test status
Simulation time 45790914080 ps
CPU time 17.53 seconds
Started Mar 28 12:48:07 PM PDT 24
Finished Mar 28 12:48:25 PM PDT 24
Peak memory 183540 kb
Host smart-966f1438-bf52-4d2c-b891-2297ee4e0bf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656184635 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.3656184635
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.3060639340
Short name T264
Test name
Test status
Simulation time 390548204 ps
CPU time 0.86 seconds
Started Mar 28 12:48:11 PM PDT 24
Finished Mar 28 12:48:12 PM PDT 24
Peak memory 183468 kb
Host smart-5906f7f1-4234-4639-ae3d-3dcdb2ec6af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060639340 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.3060639340
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.2527654943
Short name T157
Test name
Test status
Simulation time 55084267761 ps
CPU time 27.79 seconds
Started Mar 28 12:48:08 PM PDT 24
Finished Mar 28 12:48:36 PM PDT 24
Peak memory 194008 kb
Host smart-13dbdd2a-2129-4ee8-8ea8-b5ff3d08bbac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527654943 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_
all.2527654943
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.2116285686
Short name T86
Test name
Test status
Simulation time 159315462908 ps
CPU time 337.78 seconds
Started Mar 28 12:48:08 PM PDT 24
Finished Mar 28 12:53:46 PM PDT 24
Peak memory 198292 kb
Host smart-26941385-07fc-4e97-8a7d-60ea952f0cb5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116285686 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.2116285686
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.aon_timer_jump.898557198
Short name T92
Test name
Test status
Simulation time 486329026 ps
CPU time 0.7 seconds
Started Mar 28 12:48:12 PM PDT 24
Finished Mar 28 12:48:13 PM PDT 24
Peak memory 183376 kb
Host smart-b71f20ff-34dc-4ea8-b73e-73fb1906d25e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898557198 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.898557198
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.3352356281
Short name T120
Test name
Test status
Simulation time 1557224337 ps
CPU time 1.58 seconds
Started Mar 28 12:48:12 PM PDT 24
Finished Mar 28 12:48:15 PM PDT 24
Peak memory 183380 kb
Host smart-ac22567a-0138-4f5d-8e6d-fe853c023af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352356281 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.3352356281
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.3451221850
Short name T281
Test name
Test status
Simulation time 480717512 ps
CPU time 1.3 seconds
Started Mar 28 12:48:11 PM PDT 24
Finished Mar 28 12:48:13 PM PDT 24
Peak memory 183352 kb
Host smart-5a2fc923-7f88-4857-b449-e7fdd5218bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451221850 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.3451221850
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.1758606653
Short name T50
Test name
Test status
Simulation time 69528325558 ps
CPU time 115.35 seconds
Started Mar 28 12:48:10 PM PDT 24
Finished Mar 28 12:50:07 PM PDT 24
Peak memory 193540 kb
Host smart-5dac2d93-f214-4053-9439-d6a1d23f3eb9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758606653 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_
all.1758606653
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.145514588
Short name T96
Test name
Test status
Simulation time 28562923425 ps
CPU time 312.92 seconds
Started Mar 28 12:48:08 PM PDT 24
Finished Mar 28 12:53:21 PM PDT 24
Peak memory 198224 kb
Host smart-707690d3-f2aa-482f-a487-423927ab8d33
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145514588 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.145514588
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.aon_timer_jump.4167622255
Short name T228
Test name
Test status
Simulation time 479005277 ps
CPU time 0.94 seconds
Started Mar 28 12:48:09 PM PDT 24
Finished Mar 28 12:48:10 PM PDT 24
Peak memory 183512 kb
Host smart-0702b1d6-3f58-4034-991e-4010fc3fa87e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167622255 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.4167622255
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.2648867502
Short name T163
Test name
Test status
Simulation time 29717791868 ps
CPU time 13.43 seconds
Started Mar 28 12:48:07 PM PDT 24
Finished Mar 28 12:48:21 PM PDT 24
Peak memory 191744 kb
Host smart-a8377c03-851b-45c0-9ecb-56c9781c4712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648867502 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.2648867502
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.1782452836
Short name T265
Test name
Test status
Simulation time 605686130 ps
CPU time 0.6 seconds
Started Mar 28 12:48:08 PM PDT 24
Finished Mar 28 12:48:08 PM PDT 24
Peak memory 183480 kb
Host smart-aaac6be3-c6db-4265-9f11-7258a4811119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782452836 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.1782452836
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.979461585
Short name T169
Test name
Test status
Simulation time 362769348915 ps
CPU time 266.25 seconds
Started Mar 28 12:48:11 PM PDT 24
Finished Mar 28 12:52:38 PM PDT 24
Peak memory 193072 kb
Host smart-00e0668e-a906-434e-8587-44fdb5cc9625
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979461585 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_a
ll.979461585
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.2484446310
Short name T160
Test name
Test status
Simulation time 178597299532 ps
CPU time 757.84 seconds
Started Mar 28 12:48:08 PM PDT 24
Finished Mar 28 01:00:46 PM PDT 24
Peak memory 201240 kb
Host smart-e3f0c985-1b8e-403a-89df-d1ecaf49dc3c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484446310 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.2484446310
Directory /workspace/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.aon_timer_jump.3960200846
Short name T133
Test name
Test status
Simulation time 545151184 ps
CPU time 0.8 seconds
Started Mar 28 12:48:14 PM PDT 24
Finished Mar 28 12:48:15 PM PDT 24
Peak memory 183332 kb
Host smart-d37052e0-e16e-4ea6-8ab4-4790adeb1688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960200846 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.3960200846
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.2702997516
Short name T123
Test name
Test status
Simulation time 39888874725 ps
CPU time 63.1 seconds
Started Mar 28 12:48:07 PM PDT 24
Finished Mar 28 12:49:11 PM PDT 24
Peak memory 183460 kb
Host smart-11127c3d-03c1-4029-80df-67d186850560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702997516 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.2702997516
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.3526080051
Short name T224
Test name
Test status
Simulation time 544504860 ps
CPU time 0.96 seconds
Started Mar 28 12:48:07 PM PDT 24
Finished Mar 28 12:48:08 PM PDT 24
Peak memory 183500 kb
Host smart-4f30cb55-4a29-4204-b1ba-fa427f15c1ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526080051 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.3526080051
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.3901010350
Short name T138
Test name
Test status
Simulation time 428266728346 ps
CPU time 216.17 seconds
Started Mar 28 12:48:09 PM PDT 24
Finished Mar 28 12:51:45 PM PDT 24
Peak memory 183524 kb
Host smart-446b1f34-9d0c-4fa8-bf89-d49376b02e69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901010350 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_
all.3901010350
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.2185973428
Short name T158
Test name
Test status
Simulation time 47639110906 ps
CPU time 194.31 seconds
Started Mar 28 12:48:11 PM PDT 24
Finished Mar 28 12:51:26 PM PDT 24
Peak memory 198288 kb
Host smart-4283a7f3-5fc1-4dae-86b1-d7fa136e7ce9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185973428 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.2185973428
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.aon_timer_jump.2876273170
Short name T225
Test name
Test status
Simulation time 383503368 ps
CPU time 0.86 seconds
Started Mar 28 12:48:08 PM PDT 24
Finished Mar 28 12:48:09 PM PDT 24
Peak memory 183456 kb
Host smart-1a6fb983-350b-41ce-96de-6a05f690b21f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876273170 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.2876273170
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.4171389426
Short name T54
Test name
Test status
Simulation time 56225480091 ps
CPU time 36.83 seconds
Started Mar 28 12:48:12 PM PDT 24
Finished Mar 28 12:48:50 PM PDT 24
Peak memory 191644 kb
Host smart-f4f69595-2663-41f2-89de-c1f92b779bb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171389426 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.4171389426
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.1397836628
Short name T31
Test name
Test status
Simulation time 428829414 ps
CPU time 0.72 seconds
Started Mar 28 12:48:11 PM PDT 24
Finished Mar 28 12:48:12 PM PDT 24
Peak memory 183372 kb
Host smart-9a926b4d-e9fd-4c24-b18d-399a23860176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397836628 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.1397836628
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.1326802599
Short name T130
Test name
Test status
Simulation time 233814693949 ps
CPU time 353.01 seconds
Started Mar 28 12:48:14 PM PDT 24
Finished Mar 28 12:54:07 PM PDT 24
Peak memory 183396 kb
Host smart-963a8696-b727-44d9-9d2b-0832a6311eb8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326802599 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_
all.1326802599
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.4230658069
Short name T150
Test name
Test status
Simulation time 72420787521 ps
CPU time 194.26 seconds
Started Mar 28 12:48:15 PM PDT 24
Finished Mar 28 12:51:29 PM PDT 24
Peak memory 198284 kb
Host smart-cb49fd10-4b91-4316-832f-3bc17a4525f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230658069 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.4230658069
Directory /workspace/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.aon_timer_jump.1501971761
Short name T276
Test name
Test status
Simulation time 464989578 ps
CPU time 0.72 seconds
Started Mar 28 12:48:09 PM PDT 24
Finished Mar 28 12:48:09 PM PDT 24
Peak memory 183496 kb
Host smart-c51c947a-0762-4aa3-aec2-db5365825b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501971761 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.1501971761
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.2243127614
Short name T214
Test name
Test status
Simulation time 18754040614 ps
CPU time 2.62 seconds
Started Mar 28 12:48:09 PM PDT 24
Finished Mar 28 12:48:12 PM PDT 24
Peak memory 183564 kb
Host smart-431c50fa-195e-4384-833f-ea74afdc8274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243127614 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.2243127614
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.3589076790
Short name T132
Test name
Test status
Simulation time 483299279 ps
CPU time 0.72 seconds
Started Mar 28 12:48:11 PM PDT 24
Finished Mar 28 12:48:12 PM PDT 24
Peak memory 183492 kb
Host smart-074108ca-bae4-4c36-9507-76083e31f589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589076790 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.3589076790
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.1530821747
Short name T250
Test name
Test status
Simulation time 174557730008 ps
CPU time 252.8 seconds
Started Mar 28 12:48:07 PM PDT 24
Finished Mar 28 12:52:20 PM PDT 24
Peak memory 195188 kb
Host smart-be7f1ea6-f4b2-40c2-a3f6-9d4915d9f0c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530821747 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_
all.1530821747
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.548380749
Short name T7
Test name
Test status
Simulation time 60713801838 ps
CPU time 541.7 seconds
Started Mar 28 12:48:08 PM PDT 24
Finished Mar 28 12:57:10 PM PDT 24
Peak memory 198512 kb
Host smart-5fa4236d-140c-471f-b1ba-8db6a14066ab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548380749 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.548380749
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.aon_timer_jump.1548374318
Short name T185
Test name
Test status
Simulation time 406261996 ps
CPU time 0.86 seconds
Started Mar 28 12:48:14 PM PDT 24
Finished Mar 28 12:48:15 PM PDT 24
Peak memory 183332 kb
Host smart-ea709750-2e88-4385-9e7b-ed7c18ae2876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548374318 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.1548374318
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.1786499945
Short name T126
Test name
Test status
Simulation time 14565474787 ps
CPU time 23.01 seconds
Started Mar 28 12:48:13 PM PDT 24
Finished Mar 28 12:48:36 PM PDT 24
Peak memory 191676 kb
Host smart-07c7fcab-7469-478b-813f-02b3c9410043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786499945 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.1786499945
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.2789731805
Short name T221
Test name
Test status
Simulation time 506270789 ps
CPU time 0.84 seconds
Started Mar 28 12:48:14 PM PDT 24
Finished Mar 28 12:48:15 PM PDT 24
Peak memory 183408 kb
Host smart-6e74f5a8-74c3-4d09-a869-95827a018535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789731805 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.2789731805
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.2498498488
Short name T247
Test name
Test status
Simulation time 43798015688 ps
CPU time 63.75 seconds
Started Mar 28 12:48:15 PM PDT 24
Finished Mar 28 12:49:19 PM PDT 24
Peak memory 183412 kb
Host smart-33b900d7-4609-42d3-959f-cb575cc885a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498498488 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_
all.2498498488
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.431099019
Short name T262
Test name
Test status
Simulation time 219877895601 ps
CPU time 337.83 seconds
Started Mar 28 12:48:14 PM PDT 24
Finished Mar 28 12:53:52 PM PDT 24
Peak memory 198284 kb
Host smart-86e3f6cf-d20b-4d1a-8326-6e2e725f2d7f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431099019 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.431099019
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_jump.3646757267
Short name T114
Test name
Test status
Simulation time 498872873 ps
CPU time 0.79 seconds
Started Mar 28 12:47:54 PM PDT 24
Finished Mar 28 12:47:55 PM PDT 24
Peak memory 183480 kb
Host smart-b9f59ebb-8cae-436e-8e8a-64672c00f3b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646757267 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.3646757267
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.4089034805
Short name T227
Test name
Test status
Simulation time 19656992990 ps
CPU time 35.53 seconds
Started Mar 28 12:47:55 PM PDT 24
Finished Mar 28 12:48:31 PM PDT 24
Peak memory 191736 kb
Host smart-c4e8d80a-4fba-47c4-9437-144490253ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089034805 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.4089034805
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.2649725352
Short name T20
Test name
Test status
Simulation time 3908137122 ps
CPU time 1.37 seconds
Started Mar 28 12:47:56 PM PDT 24
Finished Mar 28 12:47:57 PM PDT 24
Peak memory 214780 kb
Host smart-299e3b6a-88d2-4bde-8f1f-3e277ba770d8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649725352 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.2649725352
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.622321010
Short name T135
Test name
Test status
Simulation time 441449123 ps
CPU time 0.97 seconds
Started Mar 28 12:47:57 PM PDT 24
Finished Mar 28 12:47:59 PM PDT 24
Peak memory 183400 kb
Host smart-5542a7fe-a39d-41b8-9ae8-09eb92955e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622321010 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.622321010
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.740815544
Short name T196
Test name
Test status
Simulation time 101447877171 ps
CPU time 155.54 seconds
Started Mar 28 12:47:55 PM PDT 24
Finished Mar 28 12:50:31 PM PDT 24
Peak memory 183580 kb
Host smart-d1df3e74-820c-4a84-8f52-28bcecc000da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740815544 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_al
l.740815544
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.287224706
Short name T80
Test name
Test status
Simulation time 52152343011 ps
CPU time 544.32 seconds
Started Mar 28 12:47:57 PM PDT 24
Finished Mar 28 12:57:02 PM PDT 24
Peak memory 198344 kb
Host smart-2cea73d5-1dc4-4fb8-854e-9513951319d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287224706 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.287224706
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.aon_timer_jump.1111894860
Short name T217
Test name
Test status
Simulation time 574933973 ps
CPU time 1.38 seconds
Started Mar 28 12:48:23 PM PDT 24
Finished Mar 28 12:48:25 PM PDT 24
Peak memory 183500 kb
Host smart-8f0bb9d4-6526-451f-b7e6-dede00bf42a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111894860 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.1111894860
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.622212562
Short name T184
Test name
Test status
Simulation time 39120185317 ps
CPU time 65.69 seconds
Started Mar 28 12:48:15 PM PDT 24
Finished Mar 28 12:49:21 PM PDT 24
Peak memory 183424 kb
Host smart-3025ad1a-9db1-4679-a93d-86b3dad4081b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622212562 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.622212562
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.569930942
Short name T131
Test name
Test status
Simulation time 539128113 ps
CPU time 0.77 seconds
Started Mar 28 12:48:13 PM PDT 24
Finished Mar 28 12:48:14 PM PDT 24
Peak memory 183416 kb
Host smart-cb960364-b56f-42d5-9c85-c7ec3973b81d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569930942 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.569930942
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.1940898950
Short name T9
Test name
Test status
Simulation time 250299558288 ps
CPU time 407.25 seconds
Started Mar 28 12:48:27 PM PDT 24
Finished Mar 28 12:55:15 PM PDT 24
Peak memory 194376 kb
Host smart-d9227dd5-f6b5-4302-bbb2-8353020838f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940898950 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_
all.1940898950
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.192992051
Short name T261
Test name
Test status
Simulation time 96508518192 ps
CPU time 770.45 seconds
Started Mar 28 12:48:32 PM PDT 24
Finished Mar 28 01:01:23 PM PDT 24
Peak memory 201232 kb
Host smart-5cbf6941-e4e2-4744-86e5-d6543e7fc8eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192992051 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.192992051
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_jump.195121965
Short name T110
Test name
Test status
Simulation time 377085394 ps
CPU time 1.09 seconds
Started Mar 28 12:48:30 PM PDT 24
Finished Mar 28 12:48:32 PM PDT 24
Peak memory 183284 kb
Host smart-a6f19354-b4b6-40a8-83a9-2b5608551e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195121965 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.195121965
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.277124201
Short name T200
Test name
Test status
Simulation time 25827728433 ps
CPU time 7.78 seconds
Started Mar 28 12:48:25 PM PDT 24
Finished Mar 28 12:48:35 PM PDT 24
Peak memory 191752 kb
Host smart-6aeae9ab-b0f0-4776-9bfc-9b89496c3f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277124201 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.277124201
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.1006205365
Short name T271
Test name
Test status
Simulation time 484527578 ps
CPU time 0.72 seconds
Started Mar 28 12:48:22 PM PDT 24
Finished Mar 28 12:48:23 PM PDT 24
Peak memory 183552 kb
Host smart-671027db-6a1e-4fb5-a9aa-c200184d4961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006205365 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.1006205365
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.569456566
Short name T128
Test name
Test status
Simulation time 512384625035 ps
CPU time 681.85 seconds
Started Mar 28 12:48:22 PM PDT 24
Finished Mar 28 12:59:44 PM PDT 24
Peak memory 194716 kb
Host smart-b83b0f5b-ab35-4ce1-93de-4481e2443f17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569456566 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_a
ll.569456566
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.1270609067
Short name T81
Test name
Test status
Simulation time 52103534520 ps
CPU time 242.15 seconds
Started Mar 28 12:48:26 PM PDT 24
Finished Mar 28 12:52:30 PM PDT 24
Peak memory 198320 kb
Host smart-69bedc97-d16f-4e38-b5de-e2efec6f1ec0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270609067 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.1270609067
Directory /workspace/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.aon_timer_jump.1593966948
Short name T226
Test name
Test status
Simulation time 458333547 ps
CPU time 0.89 seconds
Started Mar 28 12:48:22 PM PDT 24
Finished Mar 28 12:48:23 PM PDT 24
Peak memory 183512 kb
Host smart-498295d7-e8e2-461b-af79-a4c1ca5ef52f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593966948 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.1593966948
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.1394785154
Short name T117
Test name
Test status
Simulation time 58360238664 ps
CPU time 9.27 seconds
Started Mar 28 12:48:23 PM PDT 24
Finished Mar 28 12:48:33 PM PDT 24
Peak memory 183564 kb
Host smart-ecf5f3e6-e79d-47f0-9896-f76b69089d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394785154 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.1394785154
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.2517981594
Short name T134
Test name
Test status
Simulation time 599141323 ps
CPU time 0.8 seconds
Started Mar 28 12:48:24 PM PDT 24
Finished Mar 28 12:48:26 PM PDT 24
Peak memory 183384 kb
Host smart-26964470-c984-42ec-9ddb-78aa57e9018b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517981594 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.2517981594
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.1664068770
Short name T260
Test name
Test status
Simulation time 256992081926 ps
CPU time 426.81 seconds
Started Mar 28 12:48:23 PM PDT 24
Finished Mar 28 12:55:30 PM PDT 24
Peak memory 183388 kb
Host smart-b839f5bd-cf33-4e47-b085-44e81d9339c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664068770 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_
all.1664068770
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.3349532744
Short name T82
Test name
Test status
Simulation time 58631237887 ps
CPU time 118.15 seconds
Started Mar 28 12:48:20 PM PDT 24
Finished Mar 28 12:50:19 PM PDT 24
Peak memory 198164 kb
Host smart-e588e5c9-96b0-480e-8b85-20a4f0929251
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349532744 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.3349532744
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.aon_timer_jump.204940707
Short name T105
Test name
Test status
Simulation time 395477403 ps
CPU time 0.81 seconds
Started Mar 28 12:48:28 PM PDT 24
Finished Mar 28 12:48:30 PM PDT 24
Peak memory 183408 kb
Host smart-9a0a0bb1-0148-4911-ad4c-ed109227c97b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204940707 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.204940707
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.1631996259
Short name T283
Test name
Test status
Simulation time 7961282991 ps
CPU time 2.09 seconds
Started Mar 28 12:48:23 PM PDT 24
Finished Mar 28 12:48:25 PM PDT 24
Peak memory 183456 kb
Host smart-b69a8bf7-0618-479e-8109-4e1ddf6e6a77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631996259 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.1631996259
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.65172513
Short name T263
Test name
Test status
Simulation time 470175255 ps
CPU time 1.13 seconds
Started Mar 28 12:48:23 PM PDT 24
Finished Mar 28 12:48:24 PM PDT 24
Peak memory 183400 kb
Host smart-d9c9e811-422b-4489-ae2c-868ae44d5adf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65172513 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.65172513
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.1658552710
Short name T218
Test name
Test status
Simulation time 131789702772 ps
CPU time 68.68 seconds
Started Mar 28 12:48:24 PM PDT 24
Finished Mar 28 12:49:33 PM PDT 24
Peak memory 193724 kb
Host smart-e29257d6-eef9-4b06-ba89-d08b6d945379
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658552710 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_
all.1658552710
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.1581918788
Short name T116
Test name
Test status
Simulation time 18719068341 ps
CPU time 59.47 seconds
Started Mar 28 12:48:34 PM PDT 24
Finished Mar 28 12:49:33 PM PDT 24
Peak memory 198244 kb
Host smart-3621967e-0889-4fda-9eae-d2a527c1c59f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581918788 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.1581918788
Directory /workspace/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.aon_timer_jump.2509111832
Short name T251
Test name
Test status
Simulation time 440141021 ps
CPU time 1.26 seconds
Started Mar 28 12:48:26 PM PDT 24
Finished Mar 28 12:48:29 PM PDT 24
Peak memory 183336 kb
Host smart-80298e86-29ea-4fa2-b18e-af1ddc86a86e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509111832 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.2509111832
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.3375477753
Short name T161
Test name
Test status
Simulation time 31998791517 ps
CPU time 4.88 seconds
Started Mar 28 12:48:24 PM PDT 24
Finished Mar 28 12:48:29 PM PDT 24
Peak memory 191768 kb
Host smart-58a17f9d-9b52-4fef-a4ca-1ca92db1f5e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375477753 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.3375477753
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.525158911
Short name T202
Test name
Test status
Simulation time 472756378 ps
CPU time 0.68 seconds
Started Mar 28 12:48:28 PM PDT 24
Finished Mar 28 12:48:30 PM PDT 24
Peak memory 183408 kb
Host smart-f9380a05-2ec5-4b1e-8796-406004696dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525158911 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.525158911
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.2315739667
Short name T238
Test name
Test status
Simulation time 220873819141 ps
CPU time 87.68 seconds
Started Mar 28 12:48:25 PM PDT 24
Finished Mar 28 12:49:53 PM PDT 24
Peak memory 183524 kb
Host smart-6abd7e8f-1cb8-4b4a-b1bf-7e7855daf29e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315739667 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_
all.2315739667
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.3990230090
Short name T78
Test name
Test status
Simulation time 83671315685 ps
CPU time 327.15 seconds
Started Mar 28 12:48:25 PM PDT 24
Finished Mar 28 12:53:55 PM PDT 24
Peak memory 198388 kb
Host smart-5a5daa96-6a58-459a-ad34-d2f08418bd0e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990230090 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand_reset.3990230090
Directory /workspace/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.aon_timer_jump.683847920
Short name T206
Test name
Test status
Simulation time 529511898 ps
CPU time 1.32 seconds
Started Mar 28 12:48:24 PM PDT 24
Finished Mar 28 12:48:25 PM PDT 24
Peak memory 183464 kb
Host smart-4639b348-e0e9-4bcd-874a-bc9a572d861c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683847920 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.683847920
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.3516867699
Short name T46
Test name
Test status
Simulation time 38126596870 ps
CPU time 32.94 seconds
Started Mar 28 12:48:25 PM PDT 24
Finished Mar 28 12:48:59 PM PDT 24
Peak memory 183408 kb
Host smart-67ab5e32-9f93-4c29-baa5-50fdb384f0a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516867699 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.3516867699
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.827335620
Short name T95
Test name
Test status
Simulation time 410750312 ps
CPU time 1.1 seconds
Started Mar 28 12:48:25 PM PDT 24
Finished Mar 28 12:48:28 PM PDT 24
Peak memory 183500 kb
Host smart-9166cb5f-d09b-4c3c-88bc-2a45f790b3ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827335620 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.827335620
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.1219209654
Short name T142
Test name
Test status
Simulation time 65456315948 ps
CPU time 54.52 seconds
Started Mar 28 12:48:24 PM PDT 24
Finished Mar 28 12:49:19 PM PDT 24
Peak memory 194680 kb
Host smart-56dbbeda-6509-4e8f-8bc3-a91ffb19fb76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219209654 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_
all.1219209654
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_jump.3234722417
Short name T49
Test name
Test status
Simulation time 427733515 ps
CPU time 1.19 seconds
Started Mar 28 12:48:24 PM PDT 24
Finished Mar 28 12:48:26 PM PDT 24
Peak memory 183424 kb
Host smart-27210d75-fa4c-4013-923c-2d2882cab3a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234722417 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.3234722417
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.2851510869
Short name T11
Test name
Test status
Simulation time 9775928030 ps
CPU time 17.61 seconds
Started Mar 28 12:48:32 PM PDT 24
Finished Mar 28 12:48:50 PM PDT 24
Peak memory 183352 kb
Host smart-2f3f3fa5-fcd2-4b5b-9556-85b84da58e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851510869 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.2851510869
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.2945140088
Short name T229
Test name
Test status
Simulation time 333302679 ps
CPU time 1.04 seconds
Started Mar 28 12:48:21 PM PDT 24
Finished Mar 28 12:48:22 PM PDT 24
Peak memory 183296 kb
Host smart-a3fa97cf-e395-4215-8921-490266410d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945140088 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.2945140088
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.3711598010
Short name T18
Test name
Test status
Simulation time 56502036017 ps
CPU time 19.73 seconds
Started Mar 28 12:48:23 PM PDT 24
Finished Mar 28 12:48:44 PM PDT 24
Peak memory 195096 kb
Host smart-1faf3ecb-2b0e-4716-81e3-629b2b9ed335
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711598010 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_
all.3711598010
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/27.aon_timer_jump.2604918555
Short name T235
Test name
Test status
Simulation time 332161466 ps
CPU time 1.04 seconds
Started Mar 28 12:48:23 PM PDT 24
Finished Mar 28 12:48:24 PM PDT 24
Peak memory 183500 kb
Host smart-8bc1722f-31e5-4a24-b77b-def444d8bd86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604918555 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.2604918555
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.4207546136
Short name T113
Test name
Test status
Simulation time 11407969520 ps
CPU time 3.15 seconds
Started Mar 28 12:48:24 PM PDT 24
Finished Mar 28 12:48:28 PM PDT 24
Peak memory 183568 kb
Host smart-0f549e53-78c1-44c5-84ae-b4d16634b0e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207546136 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.4207546136
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.23105568
Short name T144
Test name
Test status
Simulation time 411769313 ps
CPU time 0.77 seconds
Started Mar 28 12:48:23 PM PDT 24
Finished Mar 28 12:48:24 PM PDT 24
Peak memory 183476 kb
Host smart-7a860ae5-9622-41f8-83ef-52a5489464ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23105568 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.23105568
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.1427836870
Short name T175
Test name
Test status
Simulation time 59174367636 ps
CPU time 24.1 seconds
Started Mar 28 12:48:25 PM PDT 24
Finished Mar 28 12:48:49 PM PDT 24
Peak memory 183460 kb
Host smart-e6694c91-5a2f-4149-8878-31f3276f7e51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427836870 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_
all.1427836870
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.3146711291
Short name T55
Test name
Test status
Simulation time 91800621880 ps
CPU time 204.28 seconds
Started Mar 28 12:48:24 PM PDT 24
Finished Mar 28 12:51:49 PM PDT 24
Peak memory 198344 kb
Host smart-0c7968c3-84c2-4195-be13-e691b9c3b206
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146711291 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.3146711291
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_jump.3288153322
Short name T125
Test name
Test status
Simulation time 476990399 ps
CPU time 0.58 seconds
Started Mar 28 12:48:24 PM PDT 24
Finished Mar 28 12:48:25 PM PDT 24
Peak memory 183424 kb
Host smart-8d01dfc3-6845-444c-8242-ca89ee25b0c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288153322 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.3288153322
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.2589572046
Short name T8
Test name
Test status
Simulation time 13237722801 ps
CPU time 21.23 seconds
Started Mar 28 12:48:24 PM PDT 24
Finished Mar 28 12:48:45 PM PDT 24
Peak memory 183532 kb
Host smart-01ffb151-606c-4460-a92e-8539ca37e6c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589572046 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.2589572046
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.938756539
Short name T122
Test name
Test status
Simulation time 520584385 ps
CPU time 0.63 seconds
Started Mar 28 12:48:27 PM PDT 24
Finished Mar 28 12:48:28 PM PDT 24
Peak memory 183500 kb
Host smart-311c2808-50db-4667-b2f1-fd488956ca00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938756539 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.938756539
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.1509008453
Short name T137
Test name
Test status
Simulation time 84823987311 ps
CPU time 32.59 seconds
Started Mar 28 12:48:25 PM PDT 24
Finished Mar 28 12:49:00 PM PDT 24
Peak memory 195392 kb
Host smart-51e58f78-1374-4976-b36b-95cef079fa4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509008453 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_
all.1509008453
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.1978703601
Short name T42
Test name
Test status
Simulation time 49421656279 ps
CPU time 197.08 seconds
Started Mar 28 12:48:27 PM PDT 24
Finished Mar 28 12:51:45 PM PDT 24
Peak memory 198512 kb
Host smart-f04ca7e3-fcf6-42bb-82d6-06a947a38ba5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978703601 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.1978703601
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.aon_timer_jump.1409682324
Short name T203
Test name
Test status
Simulation time 472744173 ps
CPU time 0.72 seconds
Started Mar 28 12:48:23 PM PDT 24
Finished Mar 28 12:48:25 PM PDT 24
Peak memory 183512 kb
Host smart-3e5ed6c7-7c5a-4bc1-8dfb-22a8858b5c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409682324 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.1409682324
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.1744840571
Short name T45
Test name
Test status
Simulation time 61556532715 ps
CPU time 48 seconds
Started Mar 28 12:48:27 PM PDT 24
Finished Mar 28 12:49:16 PM PDT 24
Peak memory 191760 kb
Host smart-47566f7a-138a-44a2-8323-35fb2dd15bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744840571 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.1744840571
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.2371208685
Short name T14
Test name
Test status
Simulation time 462338940 ps
CPU time 0.89 seconds
Started Mar 28 12:48:31 PM PDT 24
Finished Mar 28 12:48:32 PM PDT 24
Peak memory 183288 kb
Host smart-60699d10-27d9-46db-acdf-a43d1442d76d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371208685 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.2371208685
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.1615012472
Short name T287
Test name
Test status
Simulation time 94993718964 ps
CPU time 77.13 seconds
Started Mar 28 12:48:24 PM PDT 24
Finished Mar 28 12:49:41 PM PDT 24
Peak memory 183380 kb
Host smart-b9052035-cc7a-456e-98f2-cf9b6924e94e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615012472 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_
all.1615012472
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.4102947860
Short name T97
Test name
Test status
Simulation time 68678487727 ps
CPU time 588.91 seconds
Started Mar 28 12:48:23 PM PDT 24
Finished Mar 28 12:58:13 PM PDT 24
Peak memory 198472 kb
Host smart-af2be40c-8cf1-42f1-9cba-77ce0182063f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102947860 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.4102947860
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.aon_timer_jump.3771467737
Short name T155
Test name
Test status
Simulation time 418354526 ps
CPU time 1.18 seconds
Started Mar 28 12:47:52 PM PDT 24
Finished Mar 28 12:47:54 PM PDT 24
Peak memory 183496 kb
Host smart-8da227fc-8a67-4a03-9ee7-5d0cbc3c2238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771467737 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.3771467737
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.4079162062
Short name T23
Test name
Test status
Simulation time 61380202179 ps
CPU time 95.67 seconds
Started Mar 28 12:47:55 PM PDT 24
Finished Mar 28 12:49:31 PM PDT 24
Peak memory 191656 kb
Host smart-288a3ad6-f695-4fc8-9390-51c37dbd43f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079162062 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.4079162062
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.895102926
Short name T16
Test name
Test status
Simulation time 4519188339 ps
CPU time 3.96 seconds
Started Mar 28 12:47:56 PM PDT 24
Finished Mar 28 12:48:01 PM PDT 24
Peak memory 215160 kb
Host smart-f2b474b2-806c-4ee7-b4dd-50bcdcde4013
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895102926 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.895102926
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.1303007125
Short name T165
Test name
Test status
Simulation time 648727214 ps
CPU time 0.66 seconds
Started Mar 28 12:47:57 PM PDT 24
Finished Mar 28 12:47:58 PM PDT 24
Peak memory 183348 kb
Host smart-266c320a-8fba-4f26-98d4-871d03aef297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303007125 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.1303007125
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.3228212461
Short name T187
Test name
Test status
Simulation time 139558385080 ps
CPU time 94.11 seconds
Started Mar 28 12:47:58 PM PDT 24
Finished Mar 28 12:49:32 PM PDT 24
Peak memory 194076 kb
Host smart-6cd1d20d-cab8-4d22-9006-ddea2b0445c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228212461 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_a
ll.3228212461
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.1059390325
Short name T141
Test name
Test status
Simulation time 64856873371 ps
CPU time 547.92 seconds
Started Mar 28 12:47:54 PM PDT 24
Finished Mar 28 12:57:02 PM PDT 24
Peak memory 198352 kb
Host smart-5fd0477f-dcd4-47cd-a2bc-2fb7cc9c8862
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059390325 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.1059390325
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_jump.1905261219
Short name T3
Test name
Test status
Simulation time 490749770 ps
CPU time 0.66 seconds
Started Mar 28 12:48:23 PM PDT 24
Finished Mar 28 12:48:24 PM PDT 24
Peak memory 183436 kb
Host smart-18e0fbe4-5399-4a5f-8f73-d070a4011774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905261219 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.1905261219
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.2290028953
Short name T272
Test name
Test status
Simulation time 18162363238 ps
CPU time 6.72 seconds
Started Mar 28 12:48:28 PM PDT 24
Finished Mar 28 12:48:35 PM PDT 24
Peak memory 183476 kb
Host smart-2ed39707-2153-480d-b134-e1fa2946d37c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290028953 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.2290028953
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.1067280346
Short name T230
Test name
Test status
Simulation time 581616416 ps
CPU time 1.49 seconds
Started Mar 28 12:48:31 PM PDT 24
Finished Mar 28 12:48:33 PM PDT 24
Peak memory 183284 kb
Host smart-a74330fc-ab38-4256-a73a-47b9ef5a6b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067280346 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.1067280346
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.1876878384
Short name T240
Test name
Test status
Simulation time 86352219802 ps
CPU time 35.6 seconds
Started Mar 28 12:48:23 PM PDT 24
Finished Mar 28 12:48:59 PM PDT 24
Peak memory 183388 kb
Host smart-2e00516f-cdba-4857-8768-f70a548040b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876878384 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_
all.1876878384
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_jump.269073972
Short name T178
Test name
Test status
Simulation time 580615588 ps
CPU time 0.74 seconds
Started Mar 28 12:48:24 PM PDT 24
Finished Mar 28 12:48:25 PM PDT 24
Peak memory 183416 kb
Host smart-30a4c347-4518-47fc-9cbc-b94ce0e06a56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269073972 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.269073972
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.3233083629
Short name T51
Test name
Test status
Simulation time 22948197467 ps
CPU time 32.95 seconds
Started Mar 28 12:48:25 PM PDT 24
Finished Mar 28 12:49:00 PM PDT 24
Peak memory 183516 kb
Host smart-bd6163a1-0c7f-4539-9cf7-f348c1ac1632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233083629 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.3233083629
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.562005684
Short name T258
Test name
Test status
Simulation time 356256733 ps
CPU time 1.09 seconds
Started Mar 28 12:48:22 PM PDT 24
Finished Mar 28 12:48:23 PM PDT 24
Peak memory 183500 kb
Host smart-ce75515f-652e-44ea-b9c3-7ee005e09875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562005684 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.562005684
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.889040213
Short name T270
Test name
Test status
Simulation time 26166875177 ps
CPU time 40.97 seconds
Started Mar 28 12:48:40 PM PDT 24
Finished Mar 28 12:49:21 PM PDT 24
Peak memory 194728 kb
Host smart-032cd838-0798-4f47-b913-f847a8d272b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889040213 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_a
ll.889040213
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.1534042661
Short name T194
Test name
Test status
Simulation time 360145977211 ps
CPU time 362.99 seconds
Started Mar 28 12:48:42 PM PDT 24
Finished Mar 28 12:54:45 PM PDT 24
Peak memory 198440 kb
Host smart-6e3f3655-64c0-4004-8f30-d501ed76f457
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534042661 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.1534042661
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.aon_timer_jump.430494696
Short name T109
Test name
Test status
Simulation time 633744862 ps
CPU time 0.67 seconds
Started Mar 28 12:48:40 PM PDT 24
Finished Mar 28 12:48:41 PM PDT 24
Peak memory 183308 kb
Host smart-7f6bb17e-87ea-47fb-a971-2484d091e151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430494696 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.430494696
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.1959222284
Short name T246
Test name
Test status
Simulation time 33109509893 ps
CPU time 28.38 seconds
Started Mar 28 12:48:41 PM PDT 24
Finished Mar 28 12:49:10 PM PDT 24
Peak memory 191596 kb
Host smart-fb94bb34-f96a-4beb-8b14-f3cc32bffd6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959222284 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.1959222284
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.1856803122
Short name T13
Test name
Test status
Simulation time 414839748 ps
CPU time 0.76 seconds
Started Mar 28 12:48:41 PM PDT 24
Finished Mar 28 12:48:42 PM PDT 24
Peak memory 183348 kb
Host smart-bc731063-4452-4c69-a7c8-b44d2781395d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856803122 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.1856803122
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.2092111831
Short name T241
Test name
Test status
Simulation time 312266117676 ps
CPU time 467.05 seconds
Started Mar 28 12:48:40 PM PDT 24
Finished Mar 28 12:56:27 PM PDT 24
Peak memory 193200 kb
Host smart-0c4a68b3-a1ae-4323-a089-548400fd1e93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092111831 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_
all.2092111831
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.778450320
Short name T275
Test name
Test status
Simulation time 119638715806 ps
CPU time 491.47 seconds
Started Mar 28 12:48:36 PM PDT 24
Finished Mar 28 12:56:48 PM PDT 24
Peak memory 198432 kb
Host smart-d37359c1-43e1-45ec-8a90-b3173023d7e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778450320 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_reset.778450320
Directory /workspace/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.aon_timer_jump.1738155724
Short name T177
Test name
Test status
Simulation time 479404610 ps
CPU time 1.35 seconds
Started Mar 28 12:48:39 PM PDT 24
Finished Mar 28 12:48:41 PM PDT 24
Peak memory 183320 kb
Host smart-efb47bf8-ba56-4259-8723-314b4350ae14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738155724 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.1738155724
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.2910773134
Short name T118
Test name
Test status
Simulation time 36607003097 ps
CPU time 28.31 seconds
Started Mar 28 12:48:41 PM PDT 24
Finished Mar 28 12:49:10 PM PDT 24
Peak memory 183536 kb
Host smart-2b9703ac-b730-4287-97bd-4d39269ea9df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910773134 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.2910773134
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.3384618761
Short name T21
Test name
Test status
Simulation time 557898083 ps
CPU time 0.8 seconds
Started Mar 28 12:48:39 PM PDT 24
Finished Mar 28 12:48:40 PM PDT 24
Peak memory 183484 kb
Host smart-00b49a7e-ae98-4674-b380-f6b62de5d6f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384618761 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.3384618761
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.1152907257
Short name T193
Test name
Test status
Simulation time 447332619662 ps
CPU time 660.75 seconds
Started Mar 28 12:48:39 PM PDT 24
Finished Mar 28 12:59:40 PM PDT 24
Peak memory 183564 kb
Host smart-19a9c945-70f0-4085-9fb9-bbb8a9e36988
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152907257 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_
all.1152907257
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.1313341359
Short name T84
Test name
Test status
Simulation time 32264381061 ps
CPU time 234.15 seconds
Started Mar 28 12:48:41 PM PDT 24
Finished Mar 28 12:52:35 PM PDT 24
Peak memory 198372 kb
Host smart-e3801318-249f-4921-8d9c-73f548f93670
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313341359 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.1313341359
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.aon_timer_jump.3957266375
Short name T268
Test name
Test status
Simulation time 389491861 ps
CPU time 0.69 seconds
Started Mar 28 12:48:44 PM PDT 24
Finished Mar 28 12:48:45 PM PDT 24
Peak memory 183300 kb
Host smart-9a11da2c-d291-44de-a5c1-301a0b4d952b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957266375 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.3957266375
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.4273889872
Short name T278
Test name
Test status
Simulation time 7298363469 ps
CPU time 11.74 seconds
Started Mar 28 12:48:40 PM PDT 24
Finished Mar 28 12:48:53 PM PDT 24
Peak memory 183564 kb
Host smart-7dff20f4-a4ce-4b1d-890e-93650fc0278d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273889872 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.4273889872
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.74979102
Short name T232
Test name
Test status
Simulation time 395435298 ps
CPU time 1.15 seconds
Started Mar 28 12:48:39 PM PDT 24
Finished Mar 28 12:48:41 PM PDT 24
Peak memory 183476 kb
Host smart-e97b216a-a2ce-4a67-8e76-797ded6e454a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74979102 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.74979102
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.2354209082
Short name T215
Test name
Test status
Simulation time 280999171289 ps
CPU time 109.5 seconds
Started Mar 28 12:48:41 PM PDT 24
Finished Mar 28 12:50:31 PM PDT 24
Peak memory 183576 kb
Host smart-0f8a5a0c-2b6e-41d1-9f86-df238f9fe2f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354209082 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_
all.2354209082
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.2389453843
Short name T220
Test name
Test status
Simulation time 9674905920 ps
CPU time 95.77 seconds
Started Mar 28 12:48:43 PM PDT 24
Finished Mar 28 12:50:20 PM PDT 24
Peak memory 198376 kb
Host smart-d1299b35-d83e-489a-a2b8-d65f88ffc419
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389453843 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.2389453843
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.aon_timer_jump.1292558108
Short name T180
Test name
Test status
Simulation time 430820049 ps
CPU time 1.22 seconds
Started Mar 28 12:48:43 PM PDT 24
Finished Mar 28 12:48:44 PM PDT 24
Peak memory 183500 kb
Host smart-21f24b9f-bb58-447a-a4e1-28d1ec99955b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292558108 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.1292558108
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.2483982153
Short name T151
Test name
Test status
Simulation time 23653382587 ps
CPU time 38.87 seconds
Started Mar 28 12:48:40 PM PDT 24
Finished Mar 28 12:49:20 PM PDT 24
Peak memory 191764 kb
Host smart-30f70182-2d7c-4193-8f28-77b808b37413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483982153 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.2483982153
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.3370847166
Short name T22
Test name
Test status
Simulation time 444551252 ps
CPU time 0.62 seconds
Started Mar 28 12:48:43 PM PDT 24
Finished Mar 28 12:48:44 PM PDT 24
Peak memory 183360 kb
Host smart-1339718d-3470-4627-a60a-eee489b02e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370847166 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.3370847166
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.3921597883
Short name T52
Test name
Test status
Simulation time 183563530947 ps
CPU time 157.35 seconds
Started Mar 28 12:48:37 PM PDT 24
Finished Mar 28 12:51:15 PM PDT 24
Peak memory 194820 kb
Host smart-8b8b69e9-4d70-4f99-876d-b76257e1d16d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921597883 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_
all.3921597883
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.3070927038
Short name T280
Test name
Test status
Simulation time 56405132124 ps
CPU time 224.61 seconds
Started Mar 28 12:48:39 PM PDT 24
Finished Mar 28 12:52:24 PM PDT 24
Peak memory 198372 kb
Host smart-8a2ca70e-0fe4-41da-9944-a9874d159679
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070927038 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.3070927038
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.aon_timer_jump.2442212408
Short name T129
Test name
Test status
Simulation time 530520864 ps
CPU time 0.82 seconds
Started Mar 28 12:48:42 PM PDT 24
Finished Mar 28 12:48:42 PM PDT 24
Peak memory 183488 kb
Host smart-24b6a251-1e39-44ad-8954-792179f331e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442212408 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.2442212408
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.1139475114
Short name T26
Test name
Test status
Simulation time 23290634056 ps
CPU time 14.62 seconds
Started Mar 28 12:48:39 PM PDT 24
Finished Mar 28 12:48:53 PM PDT 24
Peak memory 191596 kb
Host smart-232ab46b-82c1-4016-bcc0-8fb8716ea9e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139475114 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.1139475114
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.1421635366
Short name T127
Test name
Test status
Simulation time 492067062 ps
CPU time 0.71 seconds
Started Mar 28 12:48:39 PM PDT 24
Finished Mar 28 12:48:39 PM PDT 24
Peak memory 183400 kb
Host smart-11f36bb0-0e71-4d14-8152-06a697deacbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421635366 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.1421635366
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.1210366739
Short name T174
Test name
Test status
Simulation time 101011925719 ps
CPU time 159.99 seconds
Started Mar 28 12:48:41 PM PDT 24
Finished Mar 28 12:51:21 PM PDT 24
Peak memory 195080 kb
Host smart-45d1a6ee-885c-440f-a4c1-55e9fab2a5e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210366739 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_
all.1210366739
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_jump.1573553246
Short name T266
Test name
Test status
Simulation time 404904283 ps
CPU time 0.76 seconds
Started Mar 28 12:48:39 PM PDT 24
Finished Mar 28 12:48:39 PM PDT 24
Peak memory 183512 kb
Host smart-e70b82a4-349e-4d6c-a327-30a3ca77c3c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573553246 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.1573553246
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.352227104
Short name T239
Test name
Test status
Simulation time 42409954514 ps
CPU time 5.28 seconds
Started Mar 28 12:48:40 PM PDT 24
Finished Mar 28 12:48:46 PM PDT 24
Peak memory 183372 kb
Host smart-d4e84fee-b2a0-4297-a2ba-f3e4e94664d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352227104 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.352227104
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.1423051154
Short name T282
Test name
Test status
Simulation time 371693401 ps
CPU time 1.09 seconds
Started Mar 28 12:48:44 PM PDT 24
Finished Mar 28 12:48:45 PM PDT 24
Peak memory 183292 kb
Host smart-bfd881cb-1a4a-4382-a48a-41116958aa4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423051154 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.1423051154
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.3229639026
Short name T28
Test name
Test status
Simulation time 128497343567 ps
CPU time 30.83 seconds
Started Mar 28 12:48:38 PM PDT 24
Finished Mar 28 12:49:09 PM PDT 24
Peak memory 183576 kb
Host smart-509766dc-fc74-4d04-9e24-9c05b9be61f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229639026 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_
all.3229639026
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.1359582112
Short name T167
Test name
Test status
Simulation time 810043222439 ps
CPU time 766.38 seconds
Started Mar 28 12:48:39 PM PDT 24
Finished Mar 28 01:01:26 PM PDT 24
Peak memory 201936 kb
Host smart-953a9737-c2e2-4cb7-b8ab-c8e6053308d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359582112 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.1359582112
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.aon_timer_jump.2350284293
Short name T124
Test name
Test status
Simulation time 547711328 ps
CPU time 0.76 seconds
Started Mar 28 12:48:41 PM PDT 24
Finished Mar 28 12:48:42 PM PDT 24
Peak memory 183332 kb
Host smart-d78cf4f6-5eb8-4161-a820-376e79eac8f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350284293 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.2350284293
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.3580359441
Short name T140
Test name
Test status
Simulation time 24240586378 ps
CPU time 10.3 seconds
Started Mar 28 12:48:43 PM PDT 24
Finished Mar 28 12:48:53 PM PDT 24
Peak memory 191760 kb
Host smart-4a120c78-176c-46cd-82c4-a3818e52d84f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580359441 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.3580359441
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.1407357046
Short name T152
Test name
Test status
Simulation time 448474119 ps
CPU time 0.86 seconds
Started Mar 28 12:48:41 PM PDT 24
Finished Mar 28 12:48:42 PM PDT 24
Peak memory 183504 kb
Host smart-0cacc901-8123-44e2-b9a4-d212e20ea1f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407357046 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.1407357046
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.530059601
Short name T209
Test name
Test status
Simulation time 228791791202 ps
CPU time 178.73 seconds
Started Mar 28 12:48:43 PM PDT 24
Finished Mar 28 12:51:42 PM PDT 24
Peak memory 193156 kb
Host smart-a158baee-c0b9-43a1-a982-4f78c27fc582
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530059601 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_a
ll.530059601
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.742512534
Short name T24
Test name
Test status
Simulation time 52854233699 ps
CPU time 307.38 seconds
Started Mar 28 12:48:40 PM PDT 24
Finished Mar 28 12:53:48 PM PDT 24
Peak memory 198288 kb
Host smart-cadc09c6-0379-44be-ab77-8cd083366804
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742512534 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand_reset.742512534
Directory /workspace/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.aon_timer_jump.1974597076
Short name T44
Test name
Test status
Simulation time 525648051 ps
CPU time 1.49 seconds
Started Mar 28 12:48:40 PM PDT 24
Finished Mar 28 12:48:42 PM PDT 24
Peak memory 183500 kb
Host smart-de577ab1-4789-42c2-a1de-4848f2aea4e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974597076 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.1974597076
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.2236942849
Short name T255
Test name
Test status
Simulation time 14006094058 ps
CPU time 6.54 seconds
Started Mar 28 12:48:41 PM PDT 24
Finished Mar 28 12:48:47 PM PDT 24
Peak memory 191656 kb
Host smart-aca5138f-b67d-45f4-93d2-d5a1e52b84cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236942849 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.2236942849
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.1298177677
Short name T208
Test name
Test status
Simulation time 384621193 ps
CPU time 0.68 seconds
Started Mar 28 12:48:41 PM PDT 24
Finished Mar 28 12:48:42 PM PDT 24
Peak memory 183492 kb
Host smart-8d01767f-d111-4e11-87ba-62fbd7463248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298177677 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.1298177677
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.94352862
Short name T188
Test name
Test status
Simulation time 102764864635 ps
CPU time 161.56 seconds
Started Mar 28 12:48:42 PM PDT 24
Finished Mar 28 12:51:24 PM PDT 24
Peak memory 183576 kb
Host smart-6e3a996b-bf93-4cf4-8495-4368df135e50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94352862 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_al
l.94352862
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.3236566901
Short name T5
Test name
Test status
Simulation time 130948141368 ps
CPU time 284.64 seconds
Started Mar 28 12:48:40 PM PDT 24
Finished Mar 28 12:53:25 PM PDT 24
Peak memory 198388 kb
Host smart-3a6d7896-d2eb-4612-a8b0-b34f13246fe7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236566901 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.3236566901
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_jump.2326569235
Short name T170
Test name
Test status
Simulation time 557606937 ps
CPU time 0.77 seconds
Started Mar 28 12:47:55 PM PDT 24
Finished Mar 28 12:47:56 PM PDT 24
Peak memory 183480 kb
Host smart-47d5c5a2-3103-4e81-9d65-e3c1715673c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326569235 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.2326569235
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.1987553789
Short name T12
Test name
Test status
Simulation time 35394891567 ps
CPU time 13.09 seconds
Started Mar 28 12:47:53 PM PDT 24
Finished Mar 28 12:48:06 PM PDT 24
Peak memory 191556 kb
Host smart-4e885ef4-be73-4b86-a051-96e7fbab9fb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987553789 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.1987553789
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.2108072077
Short name T15
Test name
Test status
Simulation time 3905172077 ps
CPU time 3.84 seconds
Started Mar 28 12:47:55 PM PDT 24
Finished Mar 28 12:48:00 PM PDT 24
Peak memory 214784 kb
Host smart-bf7107b9-36ee-4d6b-a9b7-11b2f26b3ed4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108072077 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.2108072077
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.2987131759
Short name T182
Test name
Test status
Simulation time 535562492 ps
CPU time 0.75 seconds
Started Mar 28 12:47:56 PM PDT 24
Finished Mar 28 12:47:57 PM PDT 24
Peak memory 183508 kb
Host smart-e2301506-4aea-44fb-bcfe-8a4d1ba905ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987131759 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.2987131759
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.2190941825
Short name T179
Test name
Test status
Simulation time 133789006057 ps
CPU time 41.94 seconds
Started Mar 28 12:47:57 PM PDT 24
Finished Mar 28 12:48:40 PM PDT 24
Peak memory 193020 kb
Host smart-c8a1f090-11a0-4fdc-ad5b-5a13b2dc2e9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190941825 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_a
ll.2190941825
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.4031584031
Short name T43
Test name
Test status
Simulation time 229308216803 ps
CPU time 541.37 seconds
Started Mar 28 12:47:57 PM PDT 24
Finished Mar 28 12:56:59 PM PDT 24
Peak memory 198704 kb
Host smart-da1a57e8-0158-42fa-addf-0932f1d8a8dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031584031 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.4031584031
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.aon_timer_jump.1072412051
Short name T279
Test name
Test status
Simulation time 556306543 ps
CPU time 0.7 seconds
Started Mar 28 12:48:43 PM PDT 24
Finished Mar 28 12:48:44 PM PDT 24
Peak memory 183456 kb
Host smart-ef2af166-1595-4ea2-bbce-b2ed713aed5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072412051 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.1072412051
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.631004246
Short name T91
Test name
Test status
Simulation time 10071637891 ps
CPU time 1.72 seconds
Started Mar 28 12:48:43 PM PDT 24
Finished Mar 28 12:48:46 PM PDT 24
Peak memory 183416 kb
Host smart-d567437b-4c4c-4c78-8394-ddd33651ba2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631004246 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.631004246
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.3644719496
Short name T233
Test name
Test status
Simulation time 522132650 ps
CPU time 0.96 seconds
Started Mar 28 12:48:38 PM PDT 24
Finished Mar 28 12:48:39 PM PDT 24
Peak memory 183372 kb
Host smart-e22232be-391d-4151-8126-bb1935055514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644719496 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.3644719496
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.3152764613
Short name T90
Test name
Test status
Simulation time 278317556178 ps
CPU time 412.33 seconds
Started Mar 28 12:48:43 PM PDT 24
Finished Mar 28 12:55:36 PM PDT 24
Peak memory 193668 kb
Host smart-6bee5f57-d13a-418f-ba6a-89065d7b70b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152764613 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_
all.3152764613
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.4024562640
Short name T277
Test name
Test status
Simulation time 946642503692 ps
CPU time 814.47 seconds
Started Mar 28 12:48:43 PM PDT 24
Finished Mar 28 01:02:18 PM PDT 24
Peak memory 201596 kb
Host smart-5d43cc6f-f087-492e-a0fc-72d562b922d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024562640 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.4024562640
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.aon_timer_jump.1540689330
Short name T25
Test name
Test status
Simulation time 595389627 ps
CPU time 1 seconds
Started Mar 28 12:48:40 PM PDT 24
Finished Mar 28 12:48:42 PM PDT 24
Peak memory 183340 kb
Host smart-c77529f1-0306-4514-a0f8-00c7e050c3a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540689330 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.1540689330
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.578999700
Short name T212
Test name
Test status
Simulation time 29002350449 ps
CPU time 52.99 seconds
Started Mar 28 12:48:39 PM PDT 24
Finished Mar 28 12:49:33 PM PDT 24
Peak memory 183392 kb
Host smart-cd6e416b-ee39-46a4-852b-0c63e50f3672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578999700 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.578999700
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.1204523516
Short name T176
Test name
Test status
Simulation time 517653811 ps
CPU time 1.32 seconds
Started Mar 28 12:48:41 PM PDT 24
Finished Mar 28 12:48:43 PM PDT 24
Peak memory 183476 kb
Host smart-6f3e2a43-57bd-40e9-b6a4-247df8ee4e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204523516 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.1204523516
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.2909364146
Short name T171
Test name
Test status
Simulation time 461146991914 ps
CPU time 738.44 seconds
Started Mar 28 12:48:44 PM PDT 24
Finished Mar 28 01:01:03 PM PDT 24
Peak memory 194952 kb
Host smart-5db424d3-5ea5-47fc-970a-7357f280a656
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909364146 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_
all.2909364146
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.120855663
Short name T40
Test name
Test status
Simulation time 100259348798 ps
CPU time 373.36 seconds
Started Mar 28 12:48:40 PM PDT 24
Finished Mar 28 12:54:54 PM PDT 24
Peak memory 198436 kb
Host smart-6e38fba8-1b05-42e7-ac54-67b0877992d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120855663 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.120855663
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.aon_timer_jump.1676703514
Short name T210
Test name
Test status
Simulation time 365463022 ps
CPU time 1.13 seconds
Started Mar 28 12:48:58 PM PDT 24
Finished Mar 28 12:48:59 PM PDT 24
Peak memory 183508 kb
Host smart-0dfe0ac5-947c-4fa5-b7f9-4601828a8a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676703514 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.1676703514
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.1804093122
Short name T242
Test name
Test status
Simulation time 14592221608 ps
CPU time 5.73 seconds
Started Mar 28 12:48:46 PM PDT 24
Finished Mar 28 12:48:52 PM PDT 24
Peak memory 191556 kb
Host smart-7b2d523d-9e53-4cee-a709-80f54f319699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804093122 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.1804093122
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.3815516426
Short name T286
Test name
Test status
Simulation time 595023127 ps
CPU time 1.01 seconds
Started Mar 28 12:48:42 PM PDT 24
Finished Mar 28 12:48:43 PM PDT 24
Peak memory 183492 kb
Host smart-3ce06d7f-520d-4140-b77e-9c46decd7813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815516426 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.3815516426
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.2747841682
Short name T83
Test name
Test status
Simulation time 68392699354 ps
CPU time 130.23 seconds
Started Mar 28 12:48:59 PM PDT 24
Finished Mar 28 12:51:09 PM PDT 24
Peak memory 198516 kb
Host smart-e6d9a428-e15d-48f2-bfe2-4134d6435fba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747841682 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.2747841682
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.aon_timer_jump.1709934870
Short name T139
Test name
Test status
Simulation time 563236903 ps
CPU time 1.46 seconds
Started Mar 28 12:48:57 PM PDT 24
Finished Mar 28 12:48:59 PM PDT 24
Peak memory 183496 kb
Host smart-1786d9ab-17d4-4b52-b2f5-a036895c2771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709934870 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.1709934870
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.3740885620
Short name T257
Test name
Test status
Simulation time 23301282419 ps
CPU time 38.84 seconds
Started Mar 28 12:48:58 PM PDT 24
Finished Mar 28 12:49:37 PM PDT 24
Peak memory 183564 kb
Host smart-6114fb9f-7d3a-4142-9fac-32d390c1dc47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740885620 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.3740885620
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.3094124896
Short name T231
Test name
Test status
Simulation time 450523481 ps
CPU time 0.7 seconds
Started Mar 28 12:48:58 PM PDT 24
Finished Mar 28 12:48:59 PM PDT 24
Peak memory 183504 kb
Host smart-ec99da36-c7f4-4af9-9a05-bcec5f66cf41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094124896 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.3094124896
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.1786427335
Short name T269
Test name
Test status
Simulation time 91626913282 ps
CPU time 132.68 seconds
Started Mar 28 12:48:57 PM PDT 24
Finished Mar 28 12:51:10 PM PDT 24
Peak memory 193556 kb
Host smart-c861cdc9-98cb-4804-a4e3-2666460f9925
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786427335 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_
all.1786427335
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.3519224890
Short name T77
Test name
Test status
Simulation time 525520136291 ps
CPU time 432.79 seconds
Started Mar 28 12:48:58 PM PDT 24
Finished Mar 28 12:56:11 PM PDT 24
Peak memory 214228 kb
Host smart-d9c93f2f-1e53-47c4-b8ee-1abbf6889178
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519224890 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.3519224890
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.aon_timer_jump.1632614162
Short name T259
Test name
Test status
Simulation time 505730175 ps
CPU time 0.85 seconds
Started Mar 28 12:49:02 PM PDT 24
Finished Mar 28 12:49:03 PM PDT 24
Peak memory 183300 kb
Host smart-7bbb75ab-74a2-48f5-ad65-baee6c470137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632614162 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.1632614162
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.838299714
Short name T249
Test name
Test status
Simulation time 48862111203 ps
CPU time 6.64 seconds
Started Mar 28 12:48:58 PM PDT 24
Finished Mar 28 12:49:05 PM PDT 24
Peak memory 191756 kb
Host smart-751ee167-defa-4966-908c-02c7c2336f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838299714 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.838299714
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.2533230032
Short name T164
Test name
Test status
Simulation time 535556861 ps
CPU time 0.96 seconds
Started Mar 28 12:48:57 PM PDT 24
Finished Mar 28 12:48:58 PM PDT 24
Peak memory 183456 kb
Host smart-cae9878e-76bd-43a1-bb8a-ed825547cd36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533230032 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.2533230032
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.4176575714
Short name T252
Test name
Test status
Simulation time 214700939318 ps
CPU time 288.17 seconds
Started Mar 28 12:48:57 PM PDT 24
Finished Mar 28 12:53:45 PM PDT 24
Peak memory 193908 kb
Host smart-e208f679-aced-4c61-a557-69c70248b78b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176575714 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_
all.4176575714
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.4235924589
Short name T254
Test name
Test status
Simulation time 44823020193 ps
CPU time 366.27 seconds
Started Mar 28 12:48:59 PM PDT 24
Finished Mar 28 12:55:06 PM PDT 24
Peak memory 198340 kb
Host smart-02573efe-6e2c-4812-832b-0de983278135
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235924589 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.4235924589
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.aon_timer_jump.1641565834
Short name T112
Test name
Test status
Simulation time 472932862 ps
CPU time 1.24 seconds
Started Mar 28 12:48:57 PM PDT 24
Finished Mar 28 12:48:59 PM PDT 24
Peak memory 183504 kb
Host smart-b377958c-c017-4098-82ed-0f3e7b1d90c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641565834 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.1641565834
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.3844189162
Short name T199
Test name
Test status
Simulation time 37798000322 ps
CPU time 15.03 seconds
Started Mar 28 12:48:56 PM PDT 24
Finished Mar 28 12:49:11 PM PDT 24
Peak memory 191620 kb
Host smart-b047daf9-3cd3-451d-bbd1-ab255db4ee0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844189162 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.3844189162
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.4111553158
Short name T121
Test name
Test status
Simulation time 572914766 ps
CPU time 1.48 seconds
Started Mar 28 12:48:56 PM PDT 24
Finished Mar 28 12:48:57 PM PDT 24
Peak memory 183368 kb
Host smart-27d9a417-40b8-420c-9f9e-cc747ea619b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111553158 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.4111553158
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.3707569234
Short name T10
Test name
Test status
Simulation time 387119265439 ps
CPU time 168.48 seconds
Started Mar 28 12:48:57 PM PDT 24
Finished Mar 28 12:51:45 PM PDT 24
Peak memory 183564 kb
Host smart-c7e9c8e8-bd7c-4e06-b09d-c7dabe322001
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707569234 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_
all.3707569234
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.293330187
Short name T168
Test name
Test status
Simulation time 61595863378 ps
CPU time 380.33 seconds
Started Mar 28 12:48:58 PM PDT 24
Finished Mar 28 12:55:18 PM PDT 24
Peak memory 198464 kb
Host smart-e37b7943-e5fb-43c3-a40e-648063ef425c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293330187 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.293330187
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.aon_timer_jump.2671092749
Short name T27
Test name
Test status
Simulation time 411626609 ps
CPU time 0.83 seconds
Started Mar 28 12:49:01 PM PDT 24
Finished Mar 28 12:49:02 PM PDT 24
Peak memory 183292 kb
Host smart-0e7e6ffe-4212-4f37-993b-57dc5d5627dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671092749 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.2671092749
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.2719275363
Short name T222
Test name
Test status
Simulation time 18538910870 ps
CPU time 7.95 seconds
Started Mar 28 12:48:59 PM PDT 24
Finished Mar 28 12:49:07 PM PDT 24
Peak memory 191592 kb
Host smart-99fc3fe2-90ac-4d66-a314-7e90c955339f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719275363 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.2719275363
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.3534132486
Short name T119
Test name
Test status
Simulation time 373234782 ps
CPU time 0.86 seconds
Started Mar 28 12:49:00 PM PDT 24
Finished Mar 28 12:49:01 PM PDT 24
Peak memory 183392 kb
Host smart-6241e787-3fe3-4b03-8c39-42b20912967e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534132486 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.3534132486
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.828708083
Short name T211
Test name
Test status
Simulation time 233708564985 ps
CPU time 97.28 seconds
Started Mar 28 12:48:58 PM PDT 24
Finished Mar 28 12:50:35 PM PDT 24
Peak memory 193896 kb
Host smart-e8c9b243-a851-4185-a6ce-9766641f3282
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828708083 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_a
ll.828708083
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.725355080
Short name T29
Test name
Test status
Simulation time 148904669090 ps
CPU time 429.36 seconds
Started Mar 28 12:48:59 PM PDT 24
Finished Mar 28 12:56:09 PM PDT 24
Peak memory 198432 kb
Host smart-ee3ba8f9-ebb4-4c1d-8440-d7fce9d333ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725355080 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.725355080
Directory /workspace/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.aon_timer_jump.3308912269
Short name T166
Test name
Test status
Simulation time 609148095 ps
CPU time 0.74 seconds
Started Mar 28 12:48:57 PM PDT 24
Finished Mar 28 12:48:58 PM PDT 24
Peak memory 183388 kb
Host smart-9c9706e0-f6e0-43f2-96e0-949208c5557b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308912269 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.3308912269
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.2263100532
Short name T192
Test name
Test status
Simulation time 38013727371 ps
CPU time 51.28 seconds
Started Mar 28 12:48:57 PM PDT 24
Finished Mar 28 12:49:49 PM PDT 24
Peak memory 191580 kb
Host smart-fb1029a0-5f30-41e5-9099-817349c449a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263100532 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.2263100532
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.1209257799
Short name T253
Test name
Test status
Simulation time 340037438 ps
CPU time 0.79 seconds
Started Mar 28 12:48:58 PM PDT 24
Finished Mar 28 12:48:59 PM PDT 24
Peak memory 183504 kb
Host smart-7dca0171-9836-467e-a44a-6a3bcf233177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209257799 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.1209257799
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.4051436235
Short name T162
Test name
Test status
Simulation time 192252315560 ps
CPU time 139.27 seconds
Started Mar 28 12:49:00 PM PDT 24
Finished Mar 28 12:51:20 PM PDT 24
Peak memory 194788 kb
Host smart-c97e0623-ac1a-4553-aa31-3f131f5c68c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051436235 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_
all.4051436235
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.1119466009
Short name T172
Test name
Test status
Simulation time 77412166764 ps
CPU time 421.22 seconds
Started Mar 28 12:49:01 PM PDT 24
Finished Mar 28 12:56:03 PM PDT 24
Peak memory 198276 kb
Host smart-dac74e59-9f04-4f50-8bc6-186d5c4715a1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119466009 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.1119466009
Directory /workspace/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_jump.1273619332
Short name T106
Test name
Test status
Simulation time 504244356 ps
CPU time 0.73 seconds
Started Mar 28 12:49:12 PM PDT 24
Finished Mar 28 12:49:13 PM PDT 24
Peak memory 183400 kb
Host smart-e327fa48-f3a2-4841-bd64-0c71411e8ddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273619332 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.1273619332
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.2186535744
Short name T153
Test name
Test status
Simulation time 16433305900 ps
CPU time 6.55 seconds
Started Mar 28 12:48:57 PM PDT 24
Finished Mar 28 12:49:04 PM PDT 24
Peak memory 183432 kb
Host smart-4187fada-d3be-4567-bbdd-0720abfbecdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186535744 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.2186535744
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.957940429
Short name T223
Test name
Test status
Simulation time 513092140 ps
CPU time 1.34 seconds
Started Mar 28 12:48:57 PM PDT 24
Finished Mar 28 12:48:58 PM PDT 24
Peak memory 183376 kb
Host smart-55eac1b5-a0d9-42e6-9ab0-7abe1aca3005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957940429 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.957940429
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.3799284345
Short name T285
Test name
Test status
Simulation time 263469505119 ps
CPU time 394.84 seconds
Started Mar 28 12:48:57 PM PDT 24
Finished Mar 28 12:55:32 PM PDT 24
Peak memory 193708 kb
Host smart-ea809cd6-f601-466f-acba-60851234709d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799284345 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_
all.3799284345
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.2042396033
Short name T87
Test name
Test status
Simulation time 39103331061 ps
CPU time 304.93 seconds
Started Mar 28 12:48:56 PM PDT 24
Finished Mar 28 12:54:01 PM PDT 24
Peak memory 198292 kb
Host smart-c738179d-28ab-4b14-9f5c-eec0879be7b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042396033 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.2042396033
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.aon_timer_jump.3212780836
Short name T149
Test name
Test status
Simulation time 467891804 ps
CPU time 0.87 seconds
Started Mar 28 12:48:56 PM PDT 24
Finished Mar 28 12:48:57 PM PDT 24
Peak memory 183392 kb
Host smart-4af2e033-a73e-477a-84f9-a973fc789032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212780836 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.3212780836
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.3828061655
Short name T234
Test name
Test status
Simulation time 40806521658 ps
CPU time 31.12 seconds
Started Mar 28 12:48:59 PM PDT 24
Finished Mar 28 12:49:30 PM PDT 24
Peak memory 191740 kb
Host smart-f0fde8da-05ef-440e-a51b-753c4b67c99a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828061655 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.3828061655
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.1445702667
Short name T148
Test name
Test status
Simulation time 504616998 ps
CPU time 0.73 seconds
Started Mar 28 12:48:59 PM PDT 24
Finished Mar 28 12:49:00 PM PDT 24
Peak memory 183396 kb
Host smart-7404df8f-0008-447e-bc89-9fa3f9141e26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445702667 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.1445702667
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.1604953976
Short name T201
Test name
Test status
Simulation time 15173241683 ps
CPU time 37.51 seconds
Started Mar 28 12:48:57 PM PDT 24
Finished Mar 28 12:49:35 PM PDT 24
Peak memory 198508 kb
Host smart-e5bac905-087f-4023-a7ff-76956b70b039
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604953976 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.1604953976
Directory /workspace/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.aon_timer_jump.3752592871
Short name T108
Test name
Test status
Simulation time 372755657 ps
CPU time 0.76 seconds
Started Mar 28 12:47:57 PM PDT 24
Finished Mar 28 12:47:58 PM PDT 24
Peak memory 183324 kb
Host smart-8aa444fd-af46-40f3-a49a-efda12d8c12d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752592871 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.3752592871
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.431519366
Short name T93
Test name
Test status
Simulation time 32369660982 ps
CPU time 7.1 seconds
Started Mar 28 12:47:57 PM PDT 24
Finished Mar 28 12:48:04 PM PDT 24
Peak memory 191588 kb
Host smart-87941c03-a0e6-4e82-8560-5a7509336902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431519366 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.431519366
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.3346756056
Short name T219
Test name
Test status
Simulation time 391588948 ps
CPU time 0.66 seconds
Started Mar 28 12:47:55 PM PDT 24
Finished Mar 28 12:47:56 PM PDT 24
Peak memory 183480 kb
Host smart-2aae5323-88ef-43bc-83f8-9f4ad03fc703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346756056 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.3346756056
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.2212099249
Short name T145
Test name
Test status
Simulation time 40135506346 ps
CPU time 61.5 seconds
Started Mar 28 12:47:57 PM PDT 24
Finished Mar 28 12:48:59 PM PDT 24
Peak memory 183248 kb
Host smart-0bcc0c66-1b82-492e-b84f-fde474dbc020
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212099249 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_a
ll.2212099249
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_jump.2066808380
Short name T48
Test name
Test status
Simulation time 543569398 ps
CPU time 1.16 seconds
Started Mar 28 12:47:57 PM PDT 24
Finished Mar 28 12:47:59 PM PDT 24
Peak memory 183396 kb
Host smart-a532ba3f-1974-4d1b-b92f-c5df3315fe23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066808380 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.2066808380
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.1679145945
Short name T245
Test name
Test status
Simulation time 20441749274 ps
CPU time 4.4 seconds
Started Mar 28 12:47:57 PM PDT 24
Finished Mar 28 12:48:02 PM PDT 24
Peak memory 183252 kb
Host smart-dca4e639-5579-45f5-b316-4b25d2a142d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679145945 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.1679145945
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.2100320076
Short name T89
Test name
Test status
Simulation time 538758555 ps
CPU time 0.67 seconds
Started Mar 28 12:47:56 PM PDT 24
Finished Mar 28 12:47:57 PM PDT 24
Peak memory 183492 kb
Host smart-7bd7e698-9e1d-4d8d-adf5-4d3ee471b2c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100320076 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.2100320076
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.3677829332
Short name T243
Test name
Test status
Simulation time 57420530673 ps
CPU time 26.02 seconds
Started Mar 28 12:47:57 PM PDT 24
Finished Mar 28 12:48:24 PM PDT 24
Peak memory 194904 kb
Host smart-387a1c8a-a005-4a21-b1da-47ad665a0a9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677829332 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_a
ll.3677829332
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.3669739758
Short name T88
Test name
Test status
Simulation time 25818321405 ps
CPU time 180.31 seconds
Started Mar 28 12:47:56 PM PDT 24
Finished Mar 28 12:50:57 PM PDT 24
Peak memory 198488 kb
Host smart-00c9cce8-94ba-4bd8-9bdf-753e74bf7b5e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669739758 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.3669739758
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.aon_timer_jump.1794736564
Short name T237
Test name
Test status
Simulation time 379245237 ps
CPU time 0.64 seconds
Started Mar 28 12:48:05 PM PDT 24
Finished Mar 28 12:48:06 PM PDT 24
Peak memory 183496 kb
Host smart-17274e07-142b-46ed-8738-a26c9f6c04e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794736564 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.1794736564
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.3893699873
Short name T197
Test name
Test status
Simulation time 40961508462 ps
CPU time 64.07 seconds
Started Mar 28 12:48:09 PM PDT 24
Finished Mar 28 12:49:13 PM PDT 24
Peak memory 183380 kb
Host smart-35732a76-2de1-4db7-b807-9ba8b8bfd553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893699873 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.3893699873
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.520073964
Short name T207
Test name
Test status
Simulation time 553942445 ps
CPU time 1.31 seconds
Started Mar 28 12:47:57 PM PDT 24
Finished Mar 28 12:47:59 PM PDT 24
Peak memory 183444 kb
Host smart-9b95d6e6-3feb-4bb0-96a2-aaff1436c352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520073964 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.520073964
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.1832987273
Short name T136
Test name
Test status
Simulation time 70726352903 ps
CPU time 126.96 seconds
Started Mar 28 12:48:08 PM PDT 24
Finished Mar 28 12:50:15 PM PDT 24
Peak memory 183572 kb
Host smart-346a56ed-8cae-499b-b495-837a709934eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832987273 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_a
ll.1832987273
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.2208685030
Short name T85
Test name
Test status
Simulation time 187537533451 ps
CPU time 337.99 seconds
Started Mar 28 12:48:06 PM PDT 24
Finished Mar 28 12:53:44 PM PDT 24
Peak memory 198176 kb
Host smart-015c1764-bf93-471f-bb72-66cb323d194e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208685030 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.2208685030
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.aon_timer_jump.2634186763
Short name T107
Test name
Test status
Simulation time 539950558 ps
CPU time 0.84 seconds
Started Mar 28 12:48:08 PM PDT 24
Finished Mar 28 12:48:09 PM PDT 24
Peak memory 183388 kb
Host smart-0b3ce6a0-430b-4b61-8c5c-8e9d9f72e150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634186763 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.2634186763
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.1835744302
Short name T159
Test name
Test status
Simulation time 6041508272 ps
CPU time 9.41 seconds
Started Mar 28 12:48:11 PM PDT 24
Finished Mar 28 12:48:21 PM PDT 24
Peak memory 183492 kb
Host smart-4934c750-db40-47e6-ab86-c0658f5f4189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835744302 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.1835744302
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.1910359259
Short name T143
Test name
Test status
Simulation time 552255517 ps
CPU time 0.76 seconds
Started Mar 28 12:48:08 PM PDT 24
Finished Mar 28 12:48:09 PM PDT 24
Peak memory 183292 kb
Host smart-9e80c22a-2867-44f4-a427-2a68ab2661c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910359259 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.1910359259
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.2408245305
Short name T183
Test name
Test status
Simulation time 91275557246 ps
CPU time 398.33 seconds
Started Mar 28 12:48:07 PM PDT 24
Finished Mar 28 12:54:46 PM PDT 24
Peak memory 198460 kb
Host smart-63ff7460-b231-48c9-8165-4cbb73cb8112
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408245305 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.2408245305
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.aon_timer_jump.3094070651
Short name T204
Test name
Test status
Simulation time 378936773 ps
CPU time 0.69 seconds
Started Mar 28 12:48:07 PM PDT 24
Finished Mar 28 12:48:07 PM PDT 24
Peak memory 183364 kb
Host smart-3a29ce63-738b-40c3-a742-2e1987ac08b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094070651 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.3094070651
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.2411375398
Short name T189
Test name
Test status
Simulation time 24432301062 ps
CPU time 34.98 seconds
Started Mar 28 12:48:08 PM PDT 24
Finished Mar 28 12:48:43 PM PDT 24
Peak memory 183376 kb
Host smart-994096eb-92b7-41ea-a417-727bc4ccabf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411375398 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.2411375398
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.805870033
Short name T284
Test name
Test status
Simulation time 367256209 ps
CPU time 1.13 seconds
Started Mar 28 12:48:12 PM PDT 24
Finished Mar 28 12:48:14 PM PDT 24
Peak memory 183464 kb
Host smart-f1865d5e-551f-4448-9c88-d04ccfc70149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805870033 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.805870033
Directory /workspace/9.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.1213056267
Short name T186
Test name
Test status
Simulation time 189158212537 ps
CPU time 274.87 seconds
Started Mar 28 12:48:07 PM PDT 24
Finished Mar 28 12:52:42 PM PDT 24
Peak memory 195192 kb
Host smart-0889cdd8-58f3-40c2-84d8-514a1bea11f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213056267 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_a
ll.1213056267
Directory /workspace/9.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.3685418620
Short name T205
Test name
Test status
Simulation time 49500586994 ps
CPU time 429.44 seconds
Started Mar 28 12:48:10 PM PDT 24
Finished Mar 28 12:55:19 PM PDT 24
Peak memory 198444 kb
Host smart-a31b2c17-e722-4b2e-8a73-dd8abe8881fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685418620 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.3685418620
Directory /workspace/9.aon_timer_stress_all_with_rand_reset/latest
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