Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
92.98 99.25 93.67 100.00 98.40 99.51 67.06


Total test records in report: 417
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T280 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.576286524 Mar 31 12:24:56 PM PDT 24 Mar 31 12:24:58 PM PDT 24 494394219 ps
T36 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.3394070198 Mar 31 12:24:20 PM PDT 24 Mar 31 12:24:34 PM PDT 24 8485748034 ps
T281 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.1607272761 Mar 31 12:24:46 PM PDT 24 Mar 31 12:24:47 PM PDT 24 430188008 ps
T282 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.4254488486 Mar 31 12:24:36 PM PDT 24 Mar 31 12:24:37 PM PDT 24 521516122 ps
T37 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.2920843499 Mar 31 12:24:30 PM PDT 24 Mar 31 12:24:42 PM PDT 24 8068785233 ps
T283 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.1156269382 Mar 31 12:24:24 PM PDT 24 Mar 31 12:24:25 PM PDT 24 394921813 ps
T65 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.2077168464 Mar 31 12:24:53 PM PDT 24 Mar 31 12:24:54 PM PDT 24 2400758379 ps
T284 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.159086030 Mar 31 12:24:54 PM PDT 24 Mar 31 12:24:57 PM PDT 24 753906561 ps
T285 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.1620758449 Mar 31 12:24:16 PM PDT 24 Mar 31 12:24:20 PM PDT 24 358901102 ps
T286 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.305398143 Mar 31 12:24:19 PM PDT 24 Mar 31 12:24:21 PM PDT 24 360549083 ps
T287 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.2301423425 Mar 31 12:25:07 PM PDT 24 Mar 31 12:25:08 PM PDT 24 529241755 ps
T51 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.3472643601 Mar 31 12:25:04 PM PDT 24 Mar 31 12:25:05 PM PDT 24 405180668 ps
T288 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.3596238254 Mar 31 12:24:35 PM PDT 24 Mar 31 12:24:36 PM PDT 24 414628868 ps
T289 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.563280549 Mar 31 12:24:28 PM PDT 24 Mar 31 12:24:30 PM PDT 24 491443377 ps
T66 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.3020823784 Mar 31 12:24:52 PM PDT 24 Mar 31 12:24:58 PM PDT 24 2199241580 ps
T38 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.3983418539 Mar 31 12:24:36 PM PDT 24 Mar 31 12:24:38 PM PDT 24 4550851959 ps
T290 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.111860275 Mar 31 12:24:25 PM PDT 24 Mar 31 12:24:26 PM PDT 24 428059857 ps
T291 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.168648932 Mar 31 12:24:46 PM PDT 24 Mar 31 12:24:47 PM PDT 24 500738897 ps
T292 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.1087879551 Mar 31 12:26:51 PM PDT 24 Mar 31 12:26:53 PM PDT 24 497460346 ps
T293 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.4254238847 Mar 31 12:24:34 PM PDT 24 Mar 31 12:24:35 PM PDT 24 318672196 ps
T294 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.3296061844 Mar 31 12:24:53 PM PDT 24 Mar 31 12:24:54 PM PDT 24 358703580 ps
T295 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.1541231315 Mar 31 12:24:24 PM PDT 24 Mar 31 12:24:25 PM PDT 24 353364346 ps
T296 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.661492266 Mar 31 12:24:20 PM PDT 24 Mar 31 12:24:22 PM PDT 24 814153860 ps
T297 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.1470537943 Mar 31 12:24:24 PM PDT 24 Mar 31 12:24:26 PM PDT 24 489265458 ps
T298 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.3316726605 Mar 31 12:24:24 PM PDT 24 Mar 31 12:24:25 PM PDT 24 466908462 ps
T67 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.246178915 Mar 31 12:24:19 PM PDT 24 Mar 31 12:24:22 PM PDT 24 2528926730 ps
T299 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.3052606241 Mar 31 12:24:34 PM PDT 24 Mar 31 12:24:36 PM PDT 24 328666094 ps
T300 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.3625672653 Mar 31 12:24:46 PM PDT 24 Mar 31 12:24:47 PM PDT 24 423549174 ps
T301 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.2132158533 Mar 31 12:24:33 PM PDT 24 Mar 31 12:24:34 PM PDT 24 537400929 ps
T302 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.591334600 Mar 31 12:24:37 PM PDT 24 Mar 31 12:24:38 PM PDT 24 516432417 ps
T96 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.3052494270 Mar 31 12:24:43 PM PDT 24 Mar 31 12:24:51 PM PDT 24 4737008255 ps
T303 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.4127399933 Mar 31 12:24:17 PM PDT 24 Mar 31 12:24:20 PM PDT 24 353490263 ps
T304 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.2077978639 Mar 31 12:24:46 PM PDT 24 Mar 31 12:24:47 PM PDT 24 526913764 ps
T305 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.2244191944 Mar 31 12:25:03 PM PDT 24 Mar 31 12:25:04 PM PDT 24 503069773 ps
T52 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.1917982838 Mar 31 12:24:54 PM PDT 24 Mar 31 12:24:55 PM PDT 24 421963402 ps
T306 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.113073974 Mar 31 12:24:51 PM PDT 24 Mar 31 12:24:52 PM PDT 24 464127794 ps
T60 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.3436886763 Mar 31 12:24:51 PM PDT 24 Mar 31 12:24:52 PM PDT 24 571695452 ps
T68 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.1331102984 Mar 31 12:26:43 PM PDT 24 Mar 31 12:26:45 PM PDT 24 2344198748 ps
T307 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.620127743 Mar 31 12:24:20 PM PDT 24 Mar 31 12:24:22 PM PDT 24 376070061 ps
T69 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.2056713774 Mar 31 12:24:42 PM PDT 24 Mar 31 12:24:54 PM PDT 24 1227650413 ps
T308 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.4024180723 Mar 31 12:24:31 PM PDT 24 Mar 31 12:24:32 PM PDT 24 392956847 ps
T309 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.2045982770 Mar 31 12:24:28 PM PDT 24 Mar 31 12:24:29 PM PDT 24 340387021 ps
T70 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.702305169 Mar 31 12:24:32 PM PDT 24 Mar 31 12:24:34 PM PDT 24 1758218216 ps
T94 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.1047914082 Mar 31 12:24:18 PM PDT 24 Mar 31 12:24:30 PM PDT 24 8096998103 ps
T310 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.23613392 Mar 31 12:24:19 PM PDT 24 Mar 31 12:24:22 PM PDT 24 527501990 ps
T311 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.2040401009 Mar 31 12:24:42 PM PDT 24 Mar 31 12:24:43 PM PDT 24 349141492 ps
T312 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.3766726341 Mar 31 12:24:57 PM PDT 24 Mar 31 12:24:58 PM PDT 24 362689146 ps
T313 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.1652910452 Mar 31 12:24:38 PM PDT 24 Mar 31 12:24:38 PM PDT 24 398172150 ps
T314 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.353392045 Mar 31 12:24:20 PM PDT 24 Mar 31 12:24:22 PM PDT 24 516926719 ps
T315 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.2587492344 Mar 31 12:24:16 PM PDT 24 Mar 31 12:24:20 PM PDT 24 473717687 ps
T53 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.1442574900 Mar 31 12:24:18 PM PDT 24 Mar 31 12:24:20 PM PDT 24 477499466 ps
T61 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.980267343 Mar 31 12:24:35 PM PDT 24 Mar 31 12:24:37 PM PDT 24 461621338 ps
T64 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.3754298805 Mar 31 12:24:51 PM PDT 24 Mar 31 12:24:52 PM PDT 24 491148639 ps
T316 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.2599927940 Mar 31 12:24:15 PM PDT 24 Mar 31 12:24:17 PM PDT 24 468558804 ps
T317 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.404213615 Mar 31 12:24:25 PM PDT 24 Mar 31 12:24:25 PM PDT 24 324385823 ps
T98 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.699986636 Mar 31 12:24:42 PM PDT 24 Mar 31 12:24:56 PM PDT 24 8052646738 ps
T54 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.4247111428 Mar 31 12:24:28 PM PDT 24 Mar 31 12:24:29 PM PDT 24 474829725 ps
T318 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.3202234239 Mar 31 12:24:21 PM PDT 24 Mar 31 12:24:22 PM PDT 24 495178042 ps
T71 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.665722735 Mar 31 12:24:48 PM PDT 24 Mar 31 12:24:53 PM PDT 24 1601260070 ps
T319 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.3798200071 Mar 31 12:24:16 PM PDT 24 Mar 31 12:24:25 PM PDT 24 1193949210 ps
T320 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.2686419880 Mar 31 12:24:29 PM PDT 24 Mar 31 12:24:34 PM PDT 24 2038014245 ps
T321 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.2426346998 Mar 31 12:24:50 PM PDT 24 Mar 31 12:24:50 PM PDT 24 482421055 ps
T322 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.924918670 Mar 31 12:24:19 PM PDT 24 Mar 31 12:24:21 PM PDT 24 337852823 ps
T97 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.670277790 Mar 31 12:24:45 PM PDT 24 Mar 31 12:24:52 PM PDT 24 7977307221 ps
T323 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.4136475779 Mar 31 12:24:18 PM PDT 24 Mar 31 12:24:20 PM PDT 24 315362469 ps
T324 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.2674335741 Mar 31 12:24:33 PM PDT 24 Mar 31 12:24:36 PM PDT 24 597804140 ps
T325 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.1622756511 Mar 31 12:24:36 PM PDT 24 Mar 31 12:24:38 PM PDT 24 868580654 ps
T326 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.2828108582 Mar 31 12:24:50 PM PDT 24 Mar 31 12:24:51 PM PDT 24 453578032 ps
T55 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.3749872446 Mar 31 12:24:19 PM PDT 24 Mar 31 12:24:31 PM PDT 24 13124633424 ps
T327 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.1511408431 Mar 31 12:24:22 PM PDT 24 Mar 31 12:24:23 PM PDT 24 515890229 ps
T328 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.676191912 Mar 31 12:24:33 PM PDT 24 Mar 31 12:24:35 PM PDT 24 472266780 ps
T329 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.3552084305 Mar 31 12:25:07 PM PDT 24 Mar 31 12:25:08 PM PDT 24 504657602 ps
T330 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.358148471 Mar 31 12:24:34 PM PDT 24 Mar 31 12:24:35 PM PDT 24 316290984 ps
T331 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.503224313 Mar 31 12:24:32 PM PDT 24 Mar 31 12:24:33 PM PDT 24 593943426 ps
T332 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.1459512069 Mar 31 12:24:20 PM PDT 24 Mar 31 12:24:22 PM PDT 24 524196010 ps
T333 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.3615393979 Mar 31 12:24:43 PM PDT 24 Mar 31 12:24:45 PM PDT 24 407574865 ps
T334 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.3509404549 Mar 31 12:24:37 PM PDT 24 Mar 31 12:24:38 PM PDT 24 386653384 ps
T335 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.1486352337 Mar 31 12:24:28 PM PDT 24 Mar 31 12:24:29 PM PDT 24 610607360 ps
T336 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.3460673621 Mar 31 12:24:20 PM PDT 24 Mar 31 12:24:22 PM PDT 24 415724930 ps
T337 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.4166014612 Mar 31 12:24:19 PM PDT 24 Mar 31 12:24:22 PM PDT 24 690323881 ps
T338 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.1679043138 Mar 31 12:24:26 PM PDT 24 Mar 31 12:24:27 PM PDT 24 379638472 ps
T339 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.2353451106 Mar 31 12:24:25 PM PDT 24 Mar 31 12:24:27 PM PDT 24 505404029 ps
T340 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.1039057731 Mar 31 12:25:12 PM PDT 24 Mar 31 12:25:12 PM PDT 24 420922706 ps
T95 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.2743379272 Mar 31 12:24:38 PM PDT 24 Mar 31 12:24:40 PM PDT 24 9550524208 ps
T341 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.584864242 Mar 31 12:24:21 PM PDT 24 Mar 31 12:24:22 PM PDT 24 444668813 ps
T342 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.3448180324 Mar 31 12:25:05 PM PDT 24 Mar 31 12:25:06 PM PDT 24 2402404493 ps
T343 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.1364021097 Mar 31 12:24:43 PM PDT 24 Mar 31 12:24:44 PM PDT 24 432218085 ps
T344 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.2972455425 Mar 31 12:24:23 PM PDT 24 Mar 31 12:24:24 PM PDT 24 540534270 ps
T345 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.559768009 Mar 31 12:24:24 PM PDT 24 Mar 31 12:24:28 PM PDT 24 8228391750 ps
T346 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.1691311467 Mar 31 12:24:15 PM PDT 24 Mar 31 12:24:18 PM PDT 24 1344604685 ps
T347 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.2499035219 Mar 31 12:24:27 PM PDT 24 Mar 31 12:24:28 PM PDT 24 921322238 ps
T348 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.3135506892 Mar 31 12:24:48 PM PDT 24 Mar 31 12:24:50 PM PDT 24 568040918 ps
T349 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.2657347815 Mar 31 12:24:20 PM PDT 24 Mar 31 12:24:23 PM PDT 24 483770184 ps
T350 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.53473163 Mar 31 12:24:39 PM PDT 24 Mar 31 12:24:40 PM PDT 24 449978206 ps
T351 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.179527521 Mar 31 12:24:14 PM PDT 24 Mar 31 12:24:16 PM PDT 24 332756477 ps
T352 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.3131270199 Mar 31 12:24:32 PM PDT 24 Mar 31 12:24:34 PM PDT 24 438285728 ps
T353 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.3523619958 Mar 31 12:24:49 PM PDT 24 Mar 31 12:24:50 PM PDT 24 269644391 ps
T354 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.343984564 Mar 31 12:26:40 PM PDT 24 Mar 31 12:26:41 PM PDT 24 440209337 ps
T355 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.185498492 Mar 31 12:24:19 PM PDT 24 Mar 31 12:24:21 PM PDT 24 297402449 ps
T356 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.304118975 Mar 31 12:24:56 PM PDT 24 Mar 31 12:24:58 PM PDT 24 1376252088 ps
T62 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.3677072035 Mar 31 12:24:28 PM PDT 24 Mar 31 12:24:30 PM PDT 24 472316540 ps
T357 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.2704079956 Mar 31 12:24:15 PM PDT 24 Mar 31 12:24:17 PM PDT 24 370789127 ps
T358 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.3716047880 Mar 31 12:24:48 PM PDT 24 Mar 31 12:24:49 PM PDT 24 333775213 ps
T359 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.1938020718 Mar 31 12:24:51 PM PDT 24 Mar 31 12:24:52 PM PDT 24 551275261 ps
T360 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.382696064 Mar 31 12:24:57 PM PDT 24 Mar 31 12:24:58 PM PDT 24 1469851347 ps
T63 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.2905564810 Mar 31 12:24:19 PM PDT 24 Mar 31 12:24:22 PM PDT 24 1295157618 ps
T361 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.2069572345 Mar 31 12:24:40 PM PDT 24 Mar 31 12:24:42 PM PDT 24 402590068 ps
T362 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.550796576 Mar 31 12:24:15 PM PDT 24 Mar 31 12:24:17 PM PDT 24 502773694 ps
T363 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.1323662086 Mar 31 12:24:51 PM PDT 24 Mar 31 12:24:53 PM PDT 24 434559169 ps
T364 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.1095253969 Mar 31 12:24:21 PM PDT 24 Mar 31 12:24:23 PM PDT 24 4441370088 ps
T365 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.1005329264 Mar 31 12:26:58 PM PDT 24 Mar 31 12:26:59 PM PDT 24 358497390 ps
T366 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.327255953 Mar 31 12:24:21 PM PDT 24 Mar 31 12:24:24 PM PDT 24 4436471045 ps
T367 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.3975669517 Mar 31 12:25:01 PM PDT 24 Mar 31 12:25:03 PM PDT 24 391920043 ps
T368 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.706190940 Mar 31 12:24:24 PM PDT 24 Mar 31 12:24:30 PM PDT 24 4652780974 ps
T369 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.3066044771 Mar 31 12:24:57 PM PDT 24 Mar 31 12:25:02 PM PDT 24 7101415291 ps
T56 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.957016638 Mar 31 12:24:42 PM PDT 24 Mar 31 12:24:43 PM PDT 24 312851912 ps
T370 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.763147304 Mar 31 12:25:07 PM PDT 24 Mar 31 12:25:11 PM PDT 24 8729585467 ps
T371 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.3783987520 Mar 31 12:24:34 PM PDT 24 Mar 31 12:24:37 PM PDT 24 1455291220 ps
T372 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.1291104432 Mar 31 12:24:24 PM PDT 24 Mar 31 12:24:25 PM PDT 24 382645552 ps
T373 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.430955265 Mar 31 12:24:39 PM PDT 24 Mar 31 12:24:41 PM PDT 24 367992135 ps
T374 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.2531821242 Mar 31 12:24:23 PM PDT 24 Mar 31 12:24:25 PM PDT 24 547620425 ps
T375 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.3939704400 Mar 31 12:24:37 PM PDT 24 Mar 31 12:24:41 PM PDT 24 4443961536 ps
T376 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.3000094187 Mar 31 12:24:37 PM PDT 24 Mar 31 12:24:39 PM PDT 24 413990911 ps
T57 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.1942548044 Mar 31 12:24:15 PM PDT 24 Mar 31 12:24:16 PM PDT 24 426742460 ps
T377 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.4024854232 Mar 31 12:24:39 PM PDT 24 Mar 31 12:24:40 PM PDT 24 509227163 ps
T378 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.399987262 Mar 31 12:24:32 PM PDT 24 Mar 31 12:24:33 PM PDT 24 363996500 ps
T379 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.3437054506 Mar 31 12:24:20 PM PDT 24 Mar 31 12:24:22 PM PDT 24 399376839 ps
T380 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.3346850720 Mar 31 12:24:15 PM PDT 24 Mar 31 12:24:19 PM PDT 24 927346459 ps
T381 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.3465760886 Mar 31 12:24:39 PM PDT 24 Mar 31 12:24:40 PM PDT 24 558301332 ps
T382 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.1034131496 Mar 31 12:24:30 PM PDT 24 Mar 31 12:24:31 PM PDT 24 337308056 ps
T383 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.1653990693 Mar 31 12:24:36 PM PDT 24 Mar 31 12:24:44 PM PDT 24 4592690004 ps
T384 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.571205605 Mar 31 12:26:52 PM PDT 24 Mar 31 12:26:53 PM PDT 24 1379823255 ps
T385 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.3785124948 Mar 31 12:24:43 PM PDT 24 Mar 31 12:24:44 PM PDT 24 300191193 ps
T386 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.1692251286 Mar 31 12:24:50 PM PDT 24 Mar 31 12:24:51 PM PDT 24 2080846685 ps
T387 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.248369083 Mar 31 12:25:10 PM PDT 24 Mar 31 12:25:17 PM PDT 24 4130598585 ps
T388 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.2224644101 Mar 31 12:24:18 PM PDT 24 Mar 31 12:24:21 PM PDT 24 692752221 ps
T389 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.1653052185 Mar 31 12:24:36 PM PDT 24 Mar 31 12:24:38 PM PDT 24 440704544 ps
T390 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.1954329600 Mar 31 12:24:23 PM PDT 24 Mar 31 12:24:24 PM PDT 24 499239272 ps
T391 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.3378321220 Mar 31 12:24:20 PM PDT 24 Mar 31 12:24:22 PM PDT 24 472187014 ps
T392 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.2696259579 Mar 31 12:24:45 PM PDT 24 Mar 31 12:24:46 PM PDT 24 419379024 ps
T393 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.625348401 Mar 31 12:24:29 PM PDT 24 Mar 31 12:24:30 PM PDT 24 349744503 ps
T394 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.1072659492 Mar 31 12:24:23 PM PDT 24 Mar 31 12:24:24 PM PDT 24 432230661 ps
T395 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.192409827 Mar 31 12:24:57 PM PDT 24 Mar 31 12:24:58 PM PDT 24 398215815 ps
T396 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.1744265311 Mar 31 12:24:44 PM PDT 24 Mar 31 12:24:48 PM PDT 24 7048864668 ps
T58 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.1229125003 Mar 31 12:24:17 PM PDT 24 Mar 31 12:24:27 PM PDT 24 3209779846 ps
T397 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.3427691847 Mar 31 12:24:19 PM PDT 24 Mar 31 12:24:22 PM PDT 24 1309166325 ps
T398 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.3964514494 Mar 31 12:24:08 PM PDT 24 Mar 31 12:24:09 PM PDT 24 416241873 ps
T399 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.2285905249 Mar 31 12:24:42 PM PDT 24 Mar 31 12:24:43 PM PDT 24 484741772 ps
T400 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.604214513 Mar 31 12:24:43 PM PDT 24 Mar 31 12:24:45 PM PDT 24 614823086 ps
T401 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.2827409721 Mar 31 12:24:21 PM PDT 24 Mar 31 12:24:23 PM PDT 24 505090768 ps
T402 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.460667951 Mar 31 12:24:17 PM PDT 24 Mar 31 12:24:34 PM PDT 24 8771361339 ps
T403 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.3803207560 Mar 31 12:24:15 PM PDT 24 Mar 31 12:24:22 PM PDT 24 2096754550 ps
T404 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.4154419295 Mar 31 12:24:17 PM PDT 24 Mar 31 12:24:20 PM PDT 24 602603015 ps
T405 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.2338236502 Mar 31 12:24:21 PM PDT 24 Mar 31 12:24:24 PM PDT 24 8350530108 ps
T406 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.3241824519 Mar 31 12:26:52 PM PDT 24 Mar 31 12:26:54 PM PDT 24 506309270 ps
T407 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.1981934275 Mar 31 12:24:53 PM PDT 24 Mar 31 12:24:54 PM PDT 24 617221961 ps
T408 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.4208646160 Mar 31 12:24:34 PM PDT 24 Mar 31 12:24:35 PM PDT 24 1570741726 ps
T409 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.1643447464 Mar 31 12:24:12 PM PDT 24 Mar 31 12:24:12 PM PDT 24 458213605 ps
T410 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.903938156 Mar 31 12:24:24 PM PDT 24 Mar 31 12:24:25 PM PDT 24 363313575 ps
T411 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.3642943871 Mar 31 12:24:31 PM PDT 24 Mar 31 12:24:32 PM PDT 24 454828517 ps
T412 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.3075048375 Mar 31 12:24:57 PM PDT 24 Mar 31 12:25:02 PM PDT 24 8831011609 ps
T413 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.1466997911 Mar 31 12:24:32 PM PDT 24 Mar 31 12:24:33 PM PDT 24 5166699005 ps
T414 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.37097615 Mar 31 12:24:15 PM PDT 24 Mar 31 12:24:17 PM PDT 24 420450041 ps
T59 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.3505957442 Mar 31 12:24:18 PM PDT 24 Mar 31 12:24:20 PM PDT 24 481747244 ps
T415 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.2180131122 Mar 31 12:24:30 PM PDT 24 Mar 31 12:24:32 PM PDT 24 544273397 ps
T416 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.361717518 Mar 31 12:24:49 PM PDT 24 Mar 31 12:24:50 PM PDT 24 402764063 ps
T417 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.901742201 Mar 31 12:24:28 PM PDT 24 Mar 31 12:24:31 PM PDT 24 2815334807 ps

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.1635643174
Short name T2
Test name
Test status
Simulation time 107893856090 ps
CPU time 467.22 seconds
Started Mar 31 12:24:58 PM PDT 24
Finished Mar 31 12:32:46 PM PDT 24
Peak memory 198280 kb
Host smart-9c8b6c68-e28d-4573-a2f4-e69b2458f777
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635643174 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.1635643174
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.3019102718
Short name T39
Test name
Test status
Simulation time 220307983652 ps
CPU time 417.72 seconds
Started Mar 31 12:25:13 PM PDT 24
Finished Mar 31 12:32:16 PM PDT 24
Peak memory 198280 kb
Host smart-fa255276-8e42-4435-a99c-e239e64ccb6e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019102718 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.3019102718
Directory /workspace/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.3394070198
Short name T36
Test name
Test status
Simulation time 8485748034 ps
CPU time 13.26 seconds
Started Mar 31 12:24:20 PM PDT 24
Finished Mar 31 12:24:34 PM PDT 24
Peak memory 197784 kb
Host smart-4e3b5950-2a5a-4557-baf9-14bc6ca2e61f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394070198 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_t
l_intg_err.3394070198
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.3818942510
Short name T78
Test name
Test status
Simulation time 272400396197 ps
CPU time 516.94 seconds
Started Mar 31 12:25:28 PM PDT 24
Finished Mar 31 12:34:05 PM PDT 24
Peak memory 198576 kb
Host smart-daf27b29-0f91-4260-896c-f914dc76aed0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818942510 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.3818942510
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.127891289
Short name T17
Test name
Test status
Simulation time 8573945204 ps
CPU time 3.81 seconds
Started Mar 31 12:25:05 PM PDT 24
Finished Mar 31 12:25:09 PM PDT 24
Peak memory 215404 kb
Host smart-183ea357-c24c-419c-a126-fa28da69adf2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127891289 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.127891289
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.2140171693
Short name T92
Test name
Test status
Simulation time 247367129966 ps
CPU time 82.22 seconds
Started Mar 31 12:24:59 PM PDT 24
Finished Mar 31 12:26:22 PM PDT 24
Peak memory 194276 kb
Host smart-f403df69-b4be-4137-b92e-59c36e2c9f67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140171693 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_
all.2140171693
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.2743379272
Short name T95
Test name
Test status
Simulation time 9550524208 ps
CPU time 1.88 seconds
Started Mar 31 12:24:38 PM PDT 24
Finished Mar 31 12:24:40 PM PDT 24
Peak memory 198028 kb
Host smart-85890ad1-295e-444f-b8f1-325c6b57d24d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743379272 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_t
l_intg_err.2743379272
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.1917982838
Short name T52
Test name
Test status
Simulation time 421963402 ps
CPU time 1.12 seconds
Started Mar 31 12:24:54 PM PDT 24
Finished Mar 31 12:24:55 PM PDT 24
Peak memory 194164 kb
Host smart-21ac2306-0544-480e-a874-cae99484221c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917982838 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_a
liasing.1917982838
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.2077168464
Short name T65
Test name
Test status
Simulation time 2400758379 ps
CPU time 1.4 seconds
Started Mar 31 12:24:53 PM PDT 24
Finished Mar 31 12:24:54 PM PDT 24
Peak memory 194548 kb
Host smart-e81f0b63-709e-4665-8ad1-ffb5a2003d58
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077168464 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon
_timer_same_csr_outstanding.2077168464
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.2704778547
Short name T44
Test name
Test status
Simulation time 16002525703 ps
CPU time 92.28 seconds
Started Mar 31 12:24:50 PM PDT 24
Finished Mar 31 12:26:22 PM PDT 24
Peak memory 198276 kb
Host smart-371b232a-0b53-4148-beae-584ddce5c5c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704778547 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.2704778547
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.978944426
Short name T11
Test name
Test status
Simulation time 587905134 ps
CPU time 0.69 seconds
Started Mar 31 12:24:44 PM PDT 24
Finished Mar 31 12:24:45 PM PDT 24
Peak memory 183276 kb
Host smart-c5a26f61-96b5-4b69-a195-bf2496c96e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978944426 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.978944426
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.1744265311
Short name T396
Test name
Test status
Simulation time 7048864668 ps
CPU time 4.05 seconds
Started Mar 31 12:24:44 PM PDT 24
Finished Mar 31 12:24:48 PM PDT 24
Peak memory 192172 kb
Host smart-efa08ad6-9e2e-4e40-b89c-4fc54b7f7e69
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744265311 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_b
it_bash.1744265311
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.3798200071
Short name T319
Test name
Test status
Simulation time 1193949210 ps
CPU time 2.5 seconds
Started Mar 31 12:24:16 PM PDT 24
Finished Mar 31 12:24:25 PM PDT 24
Peak memory 183760 kb
Host smart-31d6d972-d768-4796-aad3-98f3a83295c0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798200071 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_h
w_reset.3798200071
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.1486352337
Short name T335
Test name
Test status
Simulation time 610607360 ps
CPU time 1.56 seconds
Started Mar 31 12:24:28 PM PDT 24
Finished Mar 31 12:24:29 PM PDT 24
Peak memory 195964 kb
Host smart-77da22ec-aded-4c59-9006-747ff4b8a033
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486352337 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.1486352337
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.3964514494
Short name T398
Test name
Test status
Simulation time 416241873 ps
CPU time 0.68 seconds
Started Mar 31 12:24:08 PM PDT 24
Finished Mar 31 12:24:09 PM PDT 24
Peak memory 183800 kb
Host smart-20e3fc11-ed40-447e-98cc-858381bb1efd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964514494 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.3964514494
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.185498492
Short name T355
Test name
Test status
Simulation time 297402449 ps
CPU time 0.67 seconds
Started Mar 31 12:24:19 PM PDT 24
Finished Mar 31 12:24:21 PM PDT 24
Peak memory 183572 kb
Host smart-4e91a50b-c9b1-46e5-8e76-ac71c83b22f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185498492 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.185498492
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.2069572345
Short name T361
Test name
Test status
Simulation time 402590068 ps
CPU time 1.03 seconds
Started Mar 31 12:24:40 PM PDT 24
Finished Mar 31 12:24:42 PM PDT 24
Peak memory 183484 kb
Host smart-57ab8680-a110-4886-b6b9-b594c344cccd
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069572345 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_t
imer_mem_partial_access.2069572345
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.676191912
Short name T328
Test name
Test status
Simulation time 472266780 ps
CPU time 1.16 seconds
Started Mar 31 12:24:33 PM PDT 24
Finished Mar 31 12:24:35 PM PDT 24
Peak memory 183600 kb
Host smart-3c4d46e1-8f81-48bf-9bbd-46f46c4058ad
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676191912 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_wa
lk.676191912
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.2014415212
Short name T278
Test name
Test status
Simulation time 304980564 ps
CPU time 2.16 seconds
Started Mar 31 12:24:21 PM PDT 24
Finished Mar 31 12:24:24 PM PDT 24
Peak memory 198464 kb
Host smart-482a90a1-6c89-4182-a98f-104643c52639
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014415212 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.2014415212
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.1095253969
Short name T364
Test name
Test status
Simulation time 4441370088 ps
CPU time 1.36 seconds
Started Mar 31 12:24:21 PM PDT 24
Finished Mar 31 12:24:23 PM PDT 24
Peak memory 196432 kb
Host smart-1bfc9bc5-6688-4e81-bf52-ce4f6f23b3b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095253969 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl
_intg_err.1095253969
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.1981934275
Short name T407
Test name
Test status
Simulation time 617221961 ps
CPU time 0.8 seconds
Started Mar 31 12:24:53 PM PDT 24
Finished Mar 31 12:24:54 PM PDT 24
Peak memory 193040 kb
Host smart-4d878431-fec9-4bfc-9646-5e2a09bf212f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981934275 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_a
liasing.1981934275
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.3066044771
Short name T369
Test name
Test status
Simulation time 7101415291 ps
CPU time 4.42 seconds
Started Mar 31 12:24:57 PM PDT 24
Finished Mar 31 12:25:02 PM PDT 24
Peak memory 194260 kb
Host smart-a9813c92-af99-4d5c-b7c9-c3d368c277a3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066044771 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_b
it_bash.3066044771
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.3427691847
Short name T397
Test name
Test status
Simulation time 1309166325 ps
CPU time 1.62 seconds
Started Mar 31 12:24:19 PM PDT 24
Finished Mar 31 12:24:22 PM PDT 24
Peak memory 183612 kb
Host smart-5f389332-e84b-4ed6-893a-3f8950d51201
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427691847 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_h
w_reset.3427691847
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.2704079956
Short name T357
Test name
Test status
Simulation time 370789127 ps
CPU time 0.93 seconds
Started Mar 31 12:24:15 PM PDT 24
Finished Mar 31 12:24:17 PM PDT 24
Peak memory 196048 kb
Host smart-a95213c6-846f-422c-a832-690b6f6fbbc0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704079956 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.2704079956
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.2045982770
Short name T309
Test name
Test status
Simulation time 340387021 ps
CPU time 1.06 seconds
Started Mar 31 12:24:28 PM PDT 24
Finished Mar 31 12:24:29 PM PDT 24
Peak memory 183656 kb
Host smart-995f7d64-98c7-48b4-a2bc-937a6b32ce88
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045982770 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.2045982770
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.1643447464
Short name T409
Test name
Test status
Simulation time 458213605 ps
CPU time 0.66 seconds
Started Mar 31 12:24:12 PM PDT 24
Finished Mar 31 12:24:12 PM PDT 24
Peak memory 183592 kb
Host smart-dbd9b188-4de6-4b24-84ef-0de7f36e9855
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643447464 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.1643447464
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.3766726341
Short name T312
Test name
Test status
Simulation time 362689146 ps
CPU time 1.06 seconds
Started Mar 31 12:24:57 PM PDT 24
Finished Mar 31 12:24:58 PM PDT 24
Peak memory 183508 kb
Host smart-d0058677-67a5-445e-ac9e-cbc758768845
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766726341 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_t
imer_mem_partial_access.3766726341
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.4024854232
Short name T377
Test name
Test status
Simulation time 509227163 ps
CPU time 1.3 seconds
Started Mar 31 12:24:39 PM PDT 24
Finished Mar 31 12:24:40 PM PDT 24
Peak memory 183608 kb
Host smart-12642da2-c466-4d95-89b0-574841d9c723
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024854232 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_w
alk.4024854232
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.3803207560
Short name T403
Test name
Test status
Simulation time 2096754550 ps
CPU time 5.7 seconds
Started Mar 31 12:24:15 PM PDT 24
Finished Mar 31 12:24:22 PM PDT 24
Peak memory 194336 kb
Host smart-19895fe0-7d94-4ce8-9d9d-072036b84b40
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803207560 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon
_timer_same_csr_outstanding.3803207560
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.3346850720
Short name T380
Test name
Test status
Simulation time 927346459 ps
CPU time 1.64 seconds
Started Mar 31 12:24:15 PM PDT 24
Finished Mar 31 12:24:19 PM PDT 24
Peak memory 198464 kb
Host smart-26e14ee7-a223-41b5-ac31-00177164d4f6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346850720 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.3346850720
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.1653990693
Short name T383
Test name
Test status
Simulation time 4592690004 ps
CPU time 7.59 seconds
Started Mar 31 12:24:36 PM PDT 24
Finished Mar 31 12:24:44 PM PDT 24
Peak memory 196536 kb
Host smart-fabe43f3-a5d1-40da-99ad-a89396be8441
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653990693 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl
_intg_err.1653990693
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.2587492344
Short name T315
Test name
Test status
Simulation time 473717687 ps
CPU time 0.97 seconds
Started Mar 31 12:24:16 PM PDT 24
Finished Mar 31 12:24:20 PM PDT 24
Peak memory 195676 kb
Host smart-279826bf-978d-4857-8a1f-720d0fc62ab7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587492344 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.2587492344
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.1938020718
Short name T359
Test name
Test status
Simulation time 551275261 ps
CPU time 0.73 seconds
Started Mar 31 12:24:51 PM PDT 24
Finished Mar 31 12:24:52 PM PDT 24
Peak memory 192976 kb
Host smart-fc5d1436-a266-4a55-b0ac-de0361e6a679
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938020718 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.1938020718
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.358148471
Short name T330
Test name
Test status
Simulation time 316290984 ps
CPU time 0.94 seconds
Started Mar 31 12:24:34 PM PDT 24
Finished Mar 31 12:24:35 PM PDT 24
Peak memory 183600 kb
Host smart-b82e82eb-4a2c-4111-8575-541dc211292d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358148471 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.358148471
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.2944238948
Short name T34
Test name
Test status
Simulation time 2076383019 ps
CPU time 3.34 seconds
Started Mar 31 12:24:18 PM PDT 24
Finished Mar 31 12:24:23 PM PDT 24
Peak memory 194200 kb
Host smart-f2f3deb9-e3f8-4868-bed2-048a983fe5f6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944238948 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.ao
n_timer_same_csr_outstanding.2944238948
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.4166014612
Short name T337
Test name
Test status
Simulation time 690323881 ps
CPU time 2.07 seconds
Started Mar 31 12:24:19 PM PDT 24
Finished Mar 31 12:24:22 PM PDT 24
Peak memory 198400 kb
Host smart-c954006d-7b58-4298-8bf7-05bcaaea994e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166014612 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.4166014612
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.327255953
Short name T366
Test name
Test status
Simulation time 4436471045 ps
CPU time 2.63 seconds
Started Mar 31 12:24:21 PM PDT 24
Finished Mar 31 12:24:24 PM PDT 24
Peak memory 197512 kb
Host smart-eee38f53-2ea2-4689-b234-a94ea5430f6e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327255953 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl
_intg_err.327255953
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.2828108582
Short name T326
Test name
Test status
Simulation time 453578032 ps
CPU time 1.35 seconds
Started Mar 31 12:24:50 PM PDT 24
Finished Mar 31 12:24:51 PM PDT 24
Peak memory 196344 kb
Host smart-3658551e-dda2-46cd-9991-1e1bbdd82ad0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828108582 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.2828108582
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.4127399933
Short name T303
Test name
Test status
Simulation time 353490263 ps
CPU time 0.79 seconds
Started Mar 31 12:24:17 PM PDT 24
Finished Mar 31 12:24:20 PM PDT 24
Peak memory 183828 kb
Host smart-d9b28856-d37e-419b-9c0c-fad435debdb1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127399933 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.4127399933
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.2285905249
Short name T399
Test name
Test status
Simulation time 484741772 ps
CPU time 0.7 seconds
Started Mar 31 12:24:42 PM PDT 24
Finished Mar 31 12:24:43 PM PDT 24
Peak memory 183600 kb
Host smart-fb8871c2-bb24-4177-9af2-d98053bf2566
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285905249 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.2285905249
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.382696064
Short name T360
Test name
Test status
Simulation time 1469851347 ps
CPU time 1.07 seconds
Started Mar 31 12:24:57 PM PDT 24
Finished Mar 31 12:24:58 PM PDT 24
Peak memory 193136 kb
Host smart-92c79ad6-6949-4d5f-93de-1c70f992ee55
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382696064 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon
_timer_same_csr_outstanding.382696064
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.2353451106
Short name T339
Test name
Test status
Simulation time 505404029 ps
CPU time 1.65 seconds
Started Mar 31 12:24:25 PM PDT 24
Finished Mar 31 12:24:27 PM PDT 24
Peak memory 198560 kb
Host smart-2ebbe02c-9c65-4828-8dcd-34c442f4f4ed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353451106 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.2353451106
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.2077978639
Short name T304
Test name
Test status
Simulation time 526913764 ps
CPU time 0.84 seconds
Started Mar 31 12:24:46 PM PDT 24
Finished Mar 31 12:24:47 PM PDT 24
Peak memory 195292 kb
Host smart-c8457721-1229-4344-a378-aeeab04f75ae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077978639 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.2077978639
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.179527521
Short name T351
Test name
Test status
Simulation time 332756477 ps
CPU time 0.65 seconds
Started Mar 31 12:24:14 PM PDT 24
Finished Mar 31 12:24:16 PM PDT 24
Peak memory 183648 kb
Host smart-409a40e7-f1e9-4357-9438-d4d1add8fb46
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179527521 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.179527521
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.1652910452
Short name T313
Test name
Test status
Simulation time 398172150 ps
CPU time 0.67 seconds
Started Mar 31 12:24:38 PM PDT 24
Finished Mar 31 12:24:38 PM PDT 24
Peak memory 183576 kb
Host smart-1cbf396e-005b-4721-8bc0-4c98bab547bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652910452 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.1652910452
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.2056713774
Short name T69
Test name
Test status
Simulation time 1227650413 ps
CPU time 2.15 seconds
Started Mar 31 12:24:42 PM PDT 24
Finished Mar 31 12:24:54 PM PDT 24
Peak memory 193224 kb
Host smart-47c2bd0f-2aa5-4474-b659-8890572f8662
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056713774 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.ao
n_timer_same_csr_outstanding.2056713774
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.159086030
Short name T284
Test name
Test status
Simulation time 753906561 ps
CPU time 2.46 seconds
Started Mar 31 12:24:54 PM PDT 24
Finished Mar 31 12:24:57 PM PDT 24
Peak memory 198500 kb
Host smart-388fd5de-8936-403f-8d13-860ed774870e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159086030 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.159086030
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.3939704400
Short name T375
Test name
Test status
Simulation time 4443961536 ps
CPU time 4.24 seconds
Started Mar 31 12:24:37 PM PDT 24
Finished Mar 31 12:24:41 PM PDT 24
Peak memory 197460 kb
Host smart-d6a0345b-f760-4a2f-a231-4dd4c9dcf982
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939704400 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_t
l_intg_err.3939704400
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.3465760886
Short name T381
Test name
Test status
Simulation time 558301332 ps
CPU time 0.81 seconds
Started Mar 31 12:24:39 PM PDT 24
Finished Mar 31 12:24:40 PM PDT 24
Peak memory 196068 kb
Host smart-20d6664d-a302-42aa-afbf-249ed2f45c25
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465760886 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.3465760886
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.3677072035
Short name T62
Test name
Test status
Simulation time 472316540 ps
CPU time 1.42 seconds
Started Mar 31 12:24:28 PM PDT 24
Finished Mar 31 12:24:30 PM PDT 24
Peak memory 183880 kb
Host smart-1b915f5f-0012-44f4-a133-afdfddac82e6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677072035 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.3677072035
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.3131270199
Short name T352
Test name
Test status
Simulation time 438285728 ps
CPU time 1.28 seconds
Started Mar 31 12:24:32 PM PDT 24
Finished Mar 31 12:24:34 PM PDT 24
Peak memory 183604 kb
Host smart-527ad797-96af-4a42-a910-c525ef760d36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131270199 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.3131270199
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.3783987520
Short name T371
Test name
Test status
Simulation time 1455291220 ps
CPU time 2.38 seconds
Started Mar 31 12:24:34 PM PDT 24
Finished Mar 31 12:24:37 PM PDT 24
Peak memory 193308 kb
Host smart-9b3eb80c-6976-4f26-b086-e3add045fa55
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783987520 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.ao
n_timer_same_csr_outstanding.3783987520
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.35299784
Short name T277
Test name
Test status
Simulation time 367323585 ps
CPU time 2.18 seconds
Started Mar 31 12:24:52 PM PDT 24
Finished Mar 31 12:25:00 PM PDT 24
Peak memory 198508 kb
Host smart-436d706a-67f5-4b63-ac31-cd60fbc15988
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35299784 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.35299784
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.1511408431
Short name T327
Test name
Test status
Simulation time 515890229 ps
CPU time 1.02 seconds
Started Mar 31 12:24:22 PM PDT 24
Finished Mar 31 12:24:23 PM PDT 24
Peak memory 195972 kb
Host smart-2210cddd-3acf-419c-9370-94b1152f1ccb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511408431 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.1511408431
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.957016638
Short name T56
Test name
Test status
Simulation time 312851912 ps
CPU time 0.99 seconds
Started Mar 31 12:24:42 PM PDT 24
Finished Mar 31 12:24:43 PM PDT 24
Peak memory 183676 kb
Host smart-18c7c275-5831-432d-9c41-48ffbb648e51
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957016638 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.957016638
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.399987262
Short name T378
Test name
Test status
Simulation time 363996500 ps
CPU time 1.1 seconds
Started Mar 31 12:24:32 PM PDT 24
Finished Mar 31 12:24:33 PM PDT 24
Peak memory 183520 kb
Host smart-f0730596-158f-4555-be53-5623b1c0da8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399987262 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.399987262
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.3448180324
Short name T342
Test name
Test status
Simulation time 2402404493 ps
CPU time 1.67 seconds
Started Mar 31 12:25:05 PM PDT 24
Finished Mar 31 12:25:06 PM PDT 24
Peak memory 183756 kb
Host smart-09eb7c91-fc65-4dd2-bfc6-40ee146c5f2b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448180324 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao
n_timer_same_csr_outstanding.3448180324
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.1323662086
Short name T363
Test name
Test status
Simulation time 434559169 ps
CPU time 2.09 seconds
Started Mar 31 12:24:51 PM PDT 24
Finished Mar 31 12:24:53 PM PDT 24
Peak memory 198384 kb
Host smart-aa52c1a9-cfc8-49c9-9553-64a0362dcaeb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323662086 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.1323662086
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.1047914082
Short name T94
Test name
Test status
Simulation time 8096998103 ps
CPU time 11.02 seconds
Started Mar 31 12:24:18 PM PDT 24
Finished Mar 31 12:24:30 PM PDT 24
Peak memory 197952 kb
Host smart-5ea2eca0-f59d-4154-a30a-b01f4a5bf9ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047914082 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_t
l_intg_err.1047914082
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.3642943871
Short name T411
Test name
Test status
Simulation time 454828517 ps
CPU time 1.25 seconds
Started Mar 31 12:24:31 PM PDT 24
Finished Mar 31 12:24:32 PM PDT 24
Peak memory 194856 kb
Host smart-2ab9c0f3-ab81-4758-aa06-1a8fff08e4ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642943871 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.3642943871
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.3754298805
Short name T64
Test name
Test status
Simulation time 491148639 ps
CPU time 0.71 seconds
Started Mar 31 12:24:51 PM PDT 24
Finished Mar 31 12:24:52 PM PDT 24
Peak memory 183872 kb
Host smart-ed4e965a-c1b9-4e05-9f1e-00cc2dbc5c94
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754298805 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.3754298805
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.4024180723
Short name T308
Test name
Test status
Simulation time 392956847 ps
CPU time 0.62 seconds
Started Mar 31 12:24:31 PM PDT 24
Finished Mar 31 12:24:32 PM PDT 24
Peak memory 183484 kb
Host smart-2850a14f-dec5-4511-81dc-04dca15de7c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024180723 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.4024180723
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.702305169
Short name T70
Test name
Test status
Simulation time 1758218216 ps
CPU time 2.41 seconds
Started Mar 31 12:24:32 PM PDT 24
Finished Mar 31 12:24:34 PM PDT 24
Peak memory 183700 kb
Host smart-e07bf3c8-fe06-4dac-ade0-6367d08e3d68
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702305169 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon
_timer_same_csr_outstanding.702305169
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.1470537943
Short name T297
Test name
Test status
Simulation time 489265458 ps
CPU time 1.84 seconds
Started Mar 31 12:24:24 PM PDT 24
Finished Mar 31 12:24:26 PM PDT 24
Peak memory 198500 kb
Host smart-04e00f33-1acf-45f7-bcb4-1e01ff4fea1e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470537943 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.1470537943
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.1466997911
Short name T413
Test name
Test status
Simulation time 5166699005 ps
CPU time 1.59 seconds
Started Mar 31 12:24:32 PM PDT 24
Finished Mar 31 12:24:33 PM PDT 24
Peak memory 196452 kb
Host smart-b78c3740-e276-4ac8-abe4-765c9fbfed2e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466997911 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_t
l_intg_err.1466997911
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.1541231315
Short name T295
Test name
Test status
Simulation time 353364346 ps
CPU time 1.11 seconds
Started Mar 31 12:24:24 PM PDT 24
Finished Mar 31 12:24:25 PM PDT 24
Peak memory 198688 kb
Host smart-d39e26a7-9495-44c7-94b4-409849099ce5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541231315 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.1541231315
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.4247111428
Short name T54
Test name
Test status
Simulation time 474829725 ps
CPU time 0.7 seconds
Started Mar 31 12:24:28 PM PDT 24
Finished Mar 31 12:24:29 PM PDT 24
Peak memory 183840 kb
Host smart-f48d8493-1757-4c2f-9d9e-e6ca15e2327d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247111428 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.4247111428
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.4136475779
Short name T323
Test name
Test status
Simulation time 315362469 ps
CPU time 0.78 seconds
Started Mar 31 12:24:18 PM PDT 24
Finished Mar 31 12:24:20 PM PDT 24
Peak memory 183536 kb
Host smart-5eee939f-7a2e-4b98-a632-c6703a9b41d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136475779 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.4136475779
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.1692251286
Short name T386
Test name
Test status
Simulation time 2080846685 ps
CPU time 1.35 seconds
Started Mar 31 12:24:50 PM PDT 24
Finished Mar 31 12:24:51 PM PDT 24
Peak memory 194232 kb
Host smart-f98f7ffb-806a-49af-80b5-e7a518038a2d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692251286 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.ao
n_timer_same_csr_outstanding.1692251286
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.2180131122
Short name T415
Test name
Test status
Simulation time 544273397 ps
CPU time 1.45 seconds
Started Mar 31 12:24:30 PM PDT 24
Finished Mar 31 12:24:32 PM PDT 24
Peak memory 198476 kb
Host smart-ad2c21c8-c1fc-448d-a699-ba7ba1d2275f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180131122 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.2180131122
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.559768009
Short name T345
Test name
Test status
Simulation time 8228391750 ps
CPU time 3.98 seconds
Started Mar 31 12:24:24 PM PDT 24
Finished Mar 31 12:24:28 PM PDT 24
Peak memory 197972 kb
Host smart-6d83dcb3-62cc-4479-8b1f-35ca198efe33
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559768009 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl
_intg_err.559768009
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.3135506892
Short name T348
Test name
Test status
Simulation time 568040918 ps
CPU time 1.08 seconds
Started Mar 31 12:24:48 PM PDT 24
Finished Mar 31 12:24:50 PM PDT 24
Peak memory 195136 kb
Host smart-75800b1b-0eb4-401f-ad0f-42795bab0d18
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135506892 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.3135506892
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.1291104432
Short name T372
Test name
Test status
Simulation time 382645552 ps
CPU time 1.09 seconds
Started Mar 31 12:24:24 PM PDT 24
Finished Mar 31 12:24:25 PM PDT 24
Peak memory 193028 kb
Host smart-e0963e42-9ce3-4957-b9c7-d4ba64da062a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291104432 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.1291104432
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.584864242
Short name T341
Test name
Test status
Simulation time 444668813 ps
CPU time 0.87 seconds
Started Mar 31 12:24:21 PM PDT 24
Finished Mar 31 12:24:22 PM PDT 24
Peak memory 183544 kb
Host smart-28f51d29-e677-4b66-8298-f6e9583a58f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584864242 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.584864242
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.901742201
Short name T417
Test name
Test status
Simulation time 2815334807 ps
CPU time 3.22 seconds
Started Mar 31 12:24:28 PM PDT 24
Finished Mar 31 12:24:31 PM PDT 24
Peak memory 191980 kb
Host smart-3ef7da18-303b-4180-a7b8-ee940ef9c7f6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901742201 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon
_timer_same_csr_outstanding.901742201
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.4254238847
Short name T293
Test name
Test status
Simulation time 318672196 ps
CPU time 1.3 seconds
Started Mar 31 12:24:34 PM PDT 24
Finished Mar 31 12:24:35 PM PDT 24
Peak memory 197716 kb
Host smart-eee42a65-c0a7-4f74-afe7-407cbe240b21
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254238847 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.4254238847
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.699986636
Short name T98
Test name
Test status
Simulation time 8052646738 ps
CPU time 14.27 seconds
Started Mar 31 12:24:42 PM PDT 24
Finished Mar 31 12:24:56 PM PDT 24
Peak memory 198004 kb
Host smart-aaee2644-260b-4743-8f58-5e408f8a4485
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699986636 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl
_intg_err.699986636
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.503224313
Short name T331
Test name
Test status
Simulation time 593943426 ps
CPU time 0.98 seconds
Started Mar 31 12:24:32 PM PDT 24
Finished Mar 31 12:24:33 PM PDT 24
Peak memory 194904 kb
Host smart-a9f7e1de-1db8-4524-8fdd-5b26fac5e9c2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503224313 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.503224313
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.2972455425
Short name T344
Test name
Test status
Simulation time 540534270 ps
CPU time 0.83 seconds
Started Mar 31 12:24:23 PM PDT 24
Finished Mar 31 12:24:24 PM PDT 24
Peak memory 193120 kb
Host smart-70373a5e-aa79-4a4e-8de2-930d1873de3b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972455425 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.2972455425
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.1156269382
Short name T283
Test name
Test status
Simulation time 394921813 ps
CPU time 1.11 seconds
Started Mar 31 12:24:24 PM PDT 24
Finished Mar 31 12:24:25 PM PDT 24
Peak memory 183900 kb
Host smart-96b2056e-e73a-4d85-af4b-b5c92c5dee23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156269382 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.1156269382
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.3020823784
Short name T66
Test name
Test status
Simulation time 2199241580 ps
CPU time 5.03 seconds
Started Mar 31 12:24:52 PM PDT 24
Finished Mar 31 12:24:58 PM PDT 24
Peak memory 183808 kb
Host smart-d45cb222-65ec-46b7-81da-f37bc6701bc1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020823784 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.ao
n_timer_same_csr_outstanding.3020823784
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.430955265
Short name T373
Test name
Test status
Simulation time 367992135 ps
CPU time 1.98 seconds
Started Mar 31 12:24:39 PM PDT 24
Finished Mar 31 12:24:41 PM PDT 24
Peak memory 198488 kb
Host smart-f41a9178-92f8-4614-a645-75ed5e540802
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430955265 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.430955265
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.3983418539
Short name T38
Test name
Test status
Simulation time 4550851959 ps
CPU time 1.88 seconds
Started Mar 31 12:24:36 PM PDT 24
Finished Mar 31 12:24:38 PM PDT 24
Peak memory 196420 kb
Host smart-5e93951c-4da6-412d-a6d3-cb3a69fd5989
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983418539 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_t
l_intg_err.3983418539
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.4154419295
Short name T404
Test name
Test status
Simulation time 602603015 ps
CPU time 1.52 seconds
Started Mar 31 12:24:17 PM PDT 24
Finished Mar 31 12:24:20 PM PDT 24
Peak memory 195892 kb
Host smart-dd51a9bf-febc-405c-8f16-5c9be3d88da3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154419295 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.4154419295
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.2933356648
Short name T33
Test name
Test status
Simulation time 569777155 ps
CPU time 0.66 seconds
Started Mar 31 12:24:41 PM PDT 24
Finished Mar 31 12:24:42 PM PDT 24
Peak memory 193068 kb
Host smart-ede086dd-b163-45eb-86b1-1671b7f3afd0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933356648 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.2933356648
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.3316726605
Short name T298
Test name
Test status
Simulation time 466908462 ps
CPU time 0.88 seconds
Started Mar 31 12:24:24 PM PDT 24
Finished Mar 31 12:24:25 PM PDT 24
Peak memory 183572 kb
Host smart-d41c2e97-04b4-45d8-9884-900b2bcbf2d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316726605 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.3316726605
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.1691311467
Short name T346
Test name
Test status
Simulation time 1344604685 ps
CPU time 1.45 seconds
Started Mar 31 12:24:15 PM PDT 24
Finished Mar 31 12:24:18 PM PDT 24
Peak memory 183612 kb
Host smart-191b8a2d-9662-4e15-8f83-fdc9f19dafa0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691311467 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao
n_timer_same_csr_outstanding.1691311467
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.2657347815
Short name T349
Test name
Test status
Simulation time 483770184 ps
CPU time 1.81 seconds
Started Mar 31 12:24:20 PM PDT 24
Finished Mar 31 12:24:23 PM PDT 24
Peak memory 198560 kb
Host smart-e1b7535b-e35e-4d62-8a9d-ba4ba228548f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657347815 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.2657347815
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.3052494270
Short name T96
Test name
Test status
Simulation time 4737008255 ps
CPU time 8.37 seconds
Started Mar 31 12:24:43 PM PDT 24
Finished Mar 31 12:24:51 PM PDT 24
Peak memory 197460 kb
Host smart-81362fb8-4f9d-4c2a-81cd-3b610f8f0c7c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052494270 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_t
l_intg_err.3052494270
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.563280549
Short name T289
Test name
Test status
Simulation time 491443377 ps
CPU time 1.36 seconds
Started Mar 31 12:24:28 PM PDT 24
Finished Mar 31 12:24:30 PM PDT 24
Peak memory 193036 kb
Host smart-1fa83027-4512-4689-a546-f9ecdadb14a5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563280549 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_al
iasing.563280549
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.980267343
Short name T61
Test name
Test status
Simulation time 461621338 ps
CPU time 2.07 seconds
Started Mar 31 12:24:35 PM PDT 24
Finished Mar 31 12:24:37 PM PDT 24
Peak memory 192148 kb
Host smart-491a723a-86d9-43dc-82ae-d9905151767c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980267343 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_bi
t_bash.980267343
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.2224644101
Short name T388
Test name
Test status
Simulation time 692752221 ps
CPU time 1.6 seconds
Started Mar 31 12:24:18 PM PDT 24
Finished Mar 31 12:24:21 PM PDT 24
Peak memory 183708 kb
Host smart-fa15d4dd-1767-43db-9287-75ea66894bcc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224644101 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_h
w_reset.2224644101
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.3202234239
Short name T318
Test name
Test status
Simulation time 495178042 ps
CPU time 0.97 seconds
Started Mar 31 12:24:21 PM PDT 24
Finished Mar 31 12:24:22 PM PDT 24
Peak memory 195340 kb
Host smart-79c7b38b-3403-4126-8e9a-bf14e082d622
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202234239 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.3202234239
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.3436886763
Short name T60
Test name
Test status
Simulation time 571695452 ps
CPU time 0.63 seconds
Started Mar 31 12:24:51 PM PDT 24
Finished Mar 31 12:24:52 PM PDT 24
Peak memory 193048 kb
Host smart-62e81dd6-cea7-4637-bd9b-0953c1bf19f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436886763 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.3436886763
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.924918670
Short name T322
Test name
Test status
Simulation time 337852823 ps
CPU time 0.64 seconds
Started Mar 31 12:24:19 PM PDT 24
Finished Mar 31 12:24:21 PM PDT 24
Peak memory 183552 kb
Host smart-e1c2ab54-ae8c-41d2-b2a7-695bf7f91934
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924918670 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.924918670
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.625348401
Short name T393
Test name
Test status
Simulation time 349744503 ps
CPU time 0.84 seconds
Started Mar 31 12:24:29 PM PDT 24
Finished Mar 31 12:24:30 PM PDT 24
Peak memory 183492 kb
Host smart-65b379df-9715-415e-b150-6f911ba1b628
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625348401 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_ti
mer_mem_partial_access.625348401
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.1620758449
Short name T285
Test name
Test status
Simulation time 358901102 ps
CPU time 1.03 seconds
Started Mar 31 12:24:16 PM PDT 24
Finished Mar 31 12:24:20 PM PDT 24
Peak memory 183572 kb
Host smart-679f72f5-a8e5-4b40-9a26-90072da138f6
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620758449 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_w
alk.1620758449
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.4208646160
Short name T408
Test name
Test status
Simulation time 1570741726 ps
CPU time 1.19 seconds
Started Mar 31 12:24:34 PM PDT 24
Finished Mar 31 12:24:35 PM PDT 24
Peak memory 193216 kb
Host smart-2931b438-2129-45bf-8380-17bbab512c77
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208646160 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon
_timer_same_csr_outstanding.4208646160
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.2531821242
Short name T374
Test name
Test status
Simulation time 547620425 ps
CPU time 1.35 seconds
Started Mar 31 12:24:23 PM PDT 24
Finished Mar 31 12:24:25 PM PDT 24
Peak memory 198312 kb
Host smart-3c5afec4-cbcf-4219-9f5a-ec685221ab69
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531821242 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.2531821242
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.2920843499
Short name T37
Test name
Test status
Simulation time 8068785233 ps
CPU time 11.75 seconds
Started Mar 31 12:24:30 PM PDT 24
Finished Mar 31 12:24:42 PM PDT 24
Peak memory 198084 kb
Host smart-e7d4a62f-30a6-492f-9789-474c8829e4e7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920843499 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl
_intg_err.2920843499
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.3615393979
Short name T333
Test name
Test status
Simulation time 407574865 ps
CPU time 1.21 seconds
Started Mar 31 12:24:43 PM PDT 24
Finished Mar 31 12:24:45 PM PDT 24
Peak memory 183564 kb
Host smart-fcfc4925-8803-4bfa-a4a6-2f386a90f036
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615393979 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.3615393979
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.3785124948
Short name T385
Test name
Test status
Simulation time 300191193 ps
CPU time 0.75 seconds
Started Mar 31 12:24:43 PM PDT 24
Finished Mar 31 12:24:44 PM PDT 24
Peak memory 183576 kb
Host smart-38149bdc-a78e-4ba2-91fb-74462f8bd618
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785124948 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.3785124948
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.1034131496
Short name T382
Test name
Test status
Simulation time 337308056 ps
CPU time 0.58 seconds
Started Mar 31 12:24:30 PM PDT 24
Finished Mar 31 12:24:31 PM PDT 24
Peak memory 183596 kb
Host smart-693aafb7-cda1-4b71-b519-dca0a656a9ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034131496 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.1034131496
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.1459512069
Short name T332
Test name
Test status
Simulation time 524196010 ps
CPU time 0.76 seconds
Started Mar 31 12:24:20 PM PDT 24
Finished Mar 31 12:24:22 PM PDT 24
Peak memory 183568 kb
Host smart-dfc191ca-ba5d-4ebb-814a-52dcec3b3388
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459512069 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.1459512069
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.404213615
Short name T317
Test name
Test status
Simulation time 324385823 ps
CPU time 0.68 seconds
Started Mar 31 12:24:25 PM PDT 24
Finished Mar 31 12:24:25 PM PDT 24
Peak memory 183560 kb
Host smart-2cd5bc76-f632-40d4-bed6-41202f43fd74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404213615 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.404213615
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.620127743
Short name T307
Test name
Test status
Simulation time 376070061 ps
CPU time 1.02 seconds
Started Mar 31 12:24:20 PM PDT 24
Finished Mar 31 12:24:22 PM PDT 24
Peak memory 183588 kb
Host smart-e9e8b206-5de9-485c-863d-47f0876ce1ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620127743 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.620127743
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.1653052185
Short name T389
Test name
Test status
Simulation time 440704544 ps
CPU time 1.14 seconds
Started Mar 31 12:24:36 PM PDT 24
Finished Mar 31 12:24:38 PM PDT 24
Peak memory 183572 kb
Host smart-8f7baabb-f34c-4998-b71d-4e46573c32c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653052185 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.1653052185
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.361717518
Short name T416
Test name
Test status
Simulation time 402764063 ps
CPU time 0.58 seconds
Started Mar 31 12:24:49 PM PDT 24
Finished Mar 31 12:24:50 PM PDT 24
Peak memory 183536 kb
Host smart-26a9c8f0-41d8-4b10-857d-20932e322eb0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361717518 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.361717518
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.3523619958
Short name T353
Test name
Test status
Simulation time 269644391 ps
CPU time 0.86 seconds
Started Mar 31 12:24:49 PM PDT 24
Finished Mar 31 12:24:50 PM PDT 24
Peak memory 183544 kb
Host smart-007aadb3-a28f-4d4f-9ab0-41159acae6e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523619958 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.3523619958
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.2132158533
Short name T301
Test name
Test status
Simulation time 537400929 ps
CPU time 0.71 seconds
Started Mar 31 12:24:33 PM PDT 24
Finished Mar 31 12:24:34 PM PDT 24
Peak memory 183600 kb
Host smart-412cfe68-8a20-4849-b2d4-94e0df6ec2a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132158533 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.2132158533
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.1942548044
Short name T57
Test name
Test status
Simulation time 426742460 ps
CPU time 0.78 seconds
Started Mar 31 12:24:15 PM PDT 24
Finished Mar 31 12:24:16 PM PDT 24
Peak memory 183736 kb
Host smart-5b2f5c95-c359-454c-98a8-3d9720ba2ce8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942548044 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_a
liasing.1942548044
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.1229125003
Short name T58
Test name
Test status
Simulation time 3209779846 ps
CPU time 8.53 seconds
Started Mar 31 12:24:17 PM PDT 24
Finished Mar 31 12:24:27 PM PDT 24
Peak memory 192232 kb
Host smart-88965478-9812-445f-8c15-10b226c89bb7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229125003 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_b
it_bash.1229125003
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.661492266
Short name T296
Test name
Test status
Simulation time 814153860 ps
CPU time 0.78 seconds
Started Mar 31 12:24:20 PM PDT 24
Finished Mar 31 12:24:22 PM PDT 24
Peak memory 183620 kb
Host smart-ac6f6676-f05b-44fc-9962-651c5a02c8b4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661492266 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_hw
_reset.661492266
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.3437054506
Short name T379
Test name
Test status
Simulation time 399376839 ps
CPU time 0.96 seconds
Started Mar 31 12:24:20 PM PDT 24
Finished Mar 31 12:24:22 PM PDT 24
Peak memory 195892 kb
Host smart-d7e3a3f6-796d-4c21-95b0-3e3e5baa4554
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437054506 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.3437054506
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.3505957442
Short name T59
Test name
Test status
Simulation time 481747244 ps
CPU time 1.2 seconds
Started Mar 31 12:24:18 PM PDT 24
Finished Mar 31 12:24:20 PM PDT 24
Peak memory 183744 kb
Host smart-21288b51-7005-4163-b597-9ee76109307d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505957442 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.3505957442
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.3378321220
Short name T391
Test name
Test status
Simulation time 472187014 ps
CPU time 1.18 seconds
Started Mar 31 12:24:20 PM PDT 24
Finished Mar 31 12:24:22 PM PDT 24
Peak memory 183600 kb
Host smart-e675eb3f-40ee-410b-b6de-09925aea97be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378321220 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.3378321220
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.903938156
Short name T410
Test name
Test status
Simulation time 363313575 ps
CPU time 0.98 seconds
Started Mar 31 12:24:24 PM PDT 24
Finished Mar 31 12:24:25 PM PDT 24
Peak memory 183504 kb
Host smart-12956ffb-dec3-4798-81ca-79e2fa01133e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903938156 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_ti
mer_mem_partial_access.903938156
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.2768435061
Short name T275
Test name
Test status
Simulation time 513077119 ps
CPU time 0.91 seconds
Started Mar 31 12:24:12 PM PDT 24
Finished Mar 31 12:24:13 PM PDT 24
Peak memory 183580 kb
Host smart-4d079f94-af15-49ab-9f6a-7425cbf1d9b8
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768435061 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_w
alk.2768435061
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.2686419880
Short name T320
Test name
Test status
Simulation time 2038014245 ps
CPU time 4.26 seconds
Started Mar 31 12:24:29 PM PDT 24
Finished Mar 31 12:24:34 PM PDT 24
Peak memory 194332 kb
Host smart-70f27e7b-795a-4946-8203-a441012efcc5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686419880 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon
_timer_same_csr_outstanding.2686419880
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.1622756511
Short name T325
Test name
Test status
Simulation time 868580654 ps
CPU time 1.37 seconds
Started Mar 31 12:24:36 PM PDT 24
Finished Mar 31 12:24:38 PM PDT 24
Peak memory 198456 kb
Host smart-8bfd9b4d-1545-4f32-bd39-f6caabb5c202
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622756511 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.1622756511
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.460667951
Short name T402
Test name
Test status
Simulation time 8771361339 ps
CPU time 14.7 seconds
Started Mar 31 12:24:17 PM PDT 24
Finished Mar 31 12:24:34 PM PDT 24
Peak memory 197860 kb
Host smart-c9528852-68dd-4d85-88f2-9f1ba0ed87c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460667951 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_
intg_err.460667951
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.3975669517
Short name T367
Test name
Test status
Simulation time 391920043 ps
CPU time 1.18 seconds
Started Mar 31 12:25:01 PM PDT 24
Finished Mar 31 12:25:03 PM PDT 24
Peak memory 183588 kb
Host smart-5bd8e592-70d8-4f98-a2ab-0120caf162ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975669517 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.3975669517
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.2696259579
Short name T392
Test name
Test status
Simulation time 419379024 ps
CPU time 0.75 seconds
Started Mar 31 12:24:45 PM PDT 24
Finished Mar 31 12:24:46 PM PDT 24
Peak memory 183808 kb
Host smart-0532b082-286b-490a-9f0c-c8d6952246f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696259579 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.2696259579
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.111860275
Short name T290
Test name
Test status
Simulation time 428059857 ps
CPU time 0.66 seconds
Started Mar 31 12:24:25 PM PDT 24
Finished Mar 31 12:24:26 PM PDT 24
Peak memory 183556 kb
Host smart-5893d9a1-fce0-4518-8b9d-da47932c1581
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111860275 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.111860275
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.168648932
Short name T291
Test name
Test status
Simulation time 500738897 ps
CPU time 1.28 seconds
Started Mar 31 12:24:46 PM PDT 24
Finished Mar 31 12:24:47 PM PDT 24
Peak memory 183552 kb
Host smart-ccabd250-997f-4ea2-8ad4-d2688712921e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168648932 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.168648932
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.3052606241
Short name T299
Test name
Test status
Simulation time 328666094 ps
CPU time 1.03 seconds
Started Mar 31 12:24:34 PM PDT 24
Finished Mar 31 12:24:36 PM PDT 24
Peak memory 183600 kb
Host smart-14fd513f-a03a-46b5-8e72-231f5ceba1ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052606241 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.3052606241
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.3625672653
Short name T300
Test name
Test status
Simulation time 423549174 ps
CPU time 0.85 seconds
Started Mar 31 12:24:46 PM PDT 24
Finished Mar 31 12:24:47 PM PDT 24
Peak memory 183552 kb
Host smart-ea83ca4b-cddd-471c-9b48-f8a6189d421a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625672653 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.3625672653
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.576286524
Short name T280
Test name
Test status
Simulation time 494394219 ps
CPU time 1.33 seconds
Started Mar 31 12:24:56 PM PDT 24
Finished Mar 31 12:24:58 PM PDT 24
Peak memory 183540 kb
Host smart-ee065b1c-cf5b-43f1-98d5-fc0087771c84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576286524 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.576286524
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.591334600
Short name T302
Test name
Test status
Simulation time 516432417 ps
CPU time 1.26 seconds
Started Mar 31 12:24:37 PM PDT 24
Finished Mar 31 12:24:38 PM PDT 24
Peak memory 183812 kb
Host smart-635cd115-ded8-44c2-a21e-39205a518ce0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591334600 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.591334600
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.2301423425
Short name T287
Test name
Test status
Simulation time 529241755 ps
CPU time 0.87 seconds
Started Mar 31 12:25:07 PM PDT 24
Finished Mar 31 12:25:08 PM PDT 24
Peak memory 183584 kb
Host smart-087840cf-5d6b-4cc3-8bad-44a675980c0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301423425 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.2301423425
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.4254488486
Short name T282
Test name
Test status
Simulation time 521516122 ps
CPU time 0.84 seconds
Started Mar 31 12:24:36 PM PDT 24
Finished Mar 31 12:24:37 PM PDT 24
Peak memory 183548 kb
Host smart-df6166f3-1d28-428b-aa47-05ef04a7767c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254488486 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.4254488486
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.1442574900
Short name T53
Test name
Test status
Simulation time 477499466 ps
CPU time 0.8 seconds
Started Mar 31 12:24:18 PM PDT 24
Finished Mar 31 12:24:20 PM PDT 24
Peak memory 183596 kb
Host smart-83d5dc5c-fc4a-4dbc-a704-478d5839e311
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442574900 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_a
liasing.1442574900
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.3749872446
Short name T55
Test name
Test status
Simulation time 13124633424 ps
CPU time 10.7 seconds
Started Mar 31 12:24:19 PM PDT 24
Finished Mar 31 12:24:31 PM PDT 24
Peak memory 192180 kb
Host smart-8f952f9a-709c-4528-8e5a-b379a4035051
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749872446 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_b
it_bash.3749872446
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.2905564810
Short name T63
Test name
Test status
Simulation time 1295157618 ps
CPU time 2.09 seconds
Started Mar 31 12:24:19 PM PDT 24
Finished Mar 31 12:24:22 PM PDT 24
Peak memory 183596 kb
Host smart-29269db6-c776-4d16-8be9-b54bc8620b1d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905564810 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_h
w_reset.2905564810
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.3296061844
Short name T294
Test name
Test status
Simulation time 358703580 ps
CPU time 0.74 seconds
Started Mar 31 12:24:53 PM PDT 24
Finished Mar 31 12:24:54 PM PDT 24
Peak memory 194740 kb
Host smart-2b8ce386-74c0-4364-b5a2-79e6c6786dad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296061844 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.3296061844
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.3542426290
Short name T35
Test name
Test status
Simulation time 418745222 ps
CPU time 1.21 seconds
Started Mar 31 12:24:36 PM PDT 24
Finished Mar 31 12:24:38 PM PDT 24
Peak memory 183608 kb
Host smart-8f9b5faf-6640-4d82-88e5-c6778d2ae613
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542426290 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.3542426290
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.2599927940
Short name T316
Test name
Test status
Simulation time 468558804 ps
CPU time 1.2 seconds
Started Mar 31 12:24:15 PM PDT 24
Finished Mar 31 12:24:17 PM PDT 24
Peak memory 183596 kb
Host smart-02de6db7-bc1c-49db-ba68-aa3eb894bcf4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599927940 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.2599927940
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.1072659492
Short name T394
Test name
Test status
Simulation time 432230661 ps
CPU time 0.8 seconds
Started Mar 31 12:24:23 PM PDT 24
Finished Mar 31 12:24:24 PM PDT 24
Peak memory 183484 kb
Host smart-24f02896-d0cf-4061-ba41-cc7c2372fae8
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072659492 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_t
imer_mem_partial_access.1072659492
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.517914
Short name T276
Test name
Test status
Simulation time 583119710 ps
CPU time 0.58 seconds
Started Mar 31 12:24:20 PM PDT 24
Finished Mar 31 12:24:21 PM PDT 24
Peak memory 183592 kb
Host smart-42539e55-e064-4e12-a207-47bc13807be0
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517914 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_walk.517914
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.1331102984
Short name T68
Test name
Test status
Simulation time 2344198748 ps
CPU time 2.7 seconds
Started Mar 31 12:26:43 PM PDT 24
Finished Mar 31 12:26:45 PM PDT 24
Peak memory 194820 kb
Host smart-e52aed27-6f7d-418c-b6b5-469b70ad08e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331102984 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon
_timer_same_csr_outstanding.1331102984
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.2674335741
Short name T324
Test name
Test status
Simulation time 597804140 ps
CPU time 1.95 seconds
Started Mar 31 12:24:33 PM PDT 24
Finished Mar 31 12:24:36 PM PDT 24
Peak memory 198448 kb
Host smart-734e9b40-e109-4823-81c8-9d8aab679463
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674335741 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.2674335741
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.3075048375
Short name T412
Test name
Test status
Simulation time 8831011609 ps
CPU time 4.73 seconds
Started Mar 31 12:24:57 PM PDT 24
Finished Mar 31 12:25:02 PM PDT 24
Peak memory 197748 kb
Host smart-c86cf8e5-4f6e-447e-bfdd-28b22556e730
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075048375 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl
_intg_err.3075048375
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.1039057731
Short name T340
Test name
Test status
Simulation time 420922706 ps
CPU time 0.68 seconds
Started Mar 31 12:25:12 PM PDT 24
Finished Mar 31 12:25:12 PM PDT 24
Peak memory 183548 kb
Host smart-b9ad7e55-509c-4ef2-b4c6-28f2ea55793b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039057731 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.1039057731
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.192409827
Short name T395
Test name
Test status
Simulation time 398215815 ps
CPU time 1.24 seconds
Started Mar 31 12:24:57 PM PDT 24
Finished Mar 31 12:24:58 PM PDT 24
Peak memory 183568 kb
Host smart-b0d9f3c6-3813-4815-989a-9218cfaa79ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192409827 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.192409827
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.3716047880
Short name T358
Test name
Test status
Simulation time 333775213 ps
CPU time 0.74 seconds
Started Mar 31 12:24:48 PM PDT 24
Finished Mar 31 12:24:49 PM PDT 24
Peak memory 183532 kb
Host smart-954b7480-1bcc-4a9a-9b34-09e67cdedf1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716047880 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.3716047880
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.1607272761
Short name T281
Test name
Test status
Simulation time 430188008 ps
CPU time 0.67 seconds
Started Mar 31 12:24:46 PM PDT 24
Finished Mar 31 12:24:47 PM PDT 24
Peak memory 183556 kb
Host smart-72312f68-27b7-4703-b636-9f2b4c21f765
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607272761 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.1607272761
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.3596238254
Short name T288
Test name
Test status
Simulation time 414628868 ps
CPU time 0.62 seconds
Started Mar 31 12:24:35 PM PDT 24
Finished Mar 31 12:24:36 PM PDT 24
Peak memory 183596 kb
Host smart-1f3cc4bf-3d3f-4f02-9d83-66032270e311
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596238254 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.3596238254
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.2040401009
Short name T311
Test name
Test status
Simulation time 349141492 ps
CPU time 0.68 seconds
Started Mar 31 12:24:42 PM PDT 24
Finished Mar 31 12:24:43 PM PDT 24
Peak memory 183532 kb
Host smart-4a1998f3-40f7-4719-acb9-88437d71cd8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040401009 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.2040401009
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.2426346998
Short name T321
Test name
Test status
Simulation time 482421055 ps
CPU time 0.83 seconds
Started Mar 31 12:24:50 PM PDT 24
Finished Mar 31 12:24:50 PM PDT 24
Peak memory 183536 kb
Host smart-c9b2966d-b952-40a7-bcc4-ad9a97c3596a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426346998 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.2426346998
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.2244191944
Short name T305
Test name
Test status
Simulation time 503069773 ps
CPU time 0.73 seconds
Started Mar 31 12:25:03 PM PDT 24
Finished Mar 31 12:25:04 PM PDT 24
Peak memory 183548 kb
Host smart-a9e6ef5e-d22c-468a-9121-c5bebfcca1c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244191944 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.2244191944
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.53473163
Short name T350
Test name
Test status
Simulation time 449978206 ps
CPU time 0.94 seconds
Started Mar 31 12:24:39 PM PDT 24
Finished Mar 31 12:24:40 PM PDT 24
Peak memory 183592 kb
Host smart-80d54c7a-f621-44d5-8da7-f7dd2d352541
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53473163 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.53473163
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.3000094187
Short name T376
Test name
Test status
Simulation time 413990911 ps
CPU time 1.11 seconds
Started Mar 31 12:24:37 PM PDT 24
Finished Mar 31 12:24:39 PM PDT 24
Peak memory 183596 kb
Host smart-b29c5c22-dfae-4402-8a5b-997b33fbe6e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000094187 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.3000094187
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.604214513
Short name T400
Test name
Test status
Simulation time 614823086 ps
CPU time 1.65 seconds
Started Mar 31 12:24:43 PM PDT 24
Finished Mar 31 12:24:45 PM PDT 24
Peak memory 196784 kb
Host smart-558f6c3f-9a96-4645-a4cd-c76417424c0c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604214513 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.604214513
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.2827409721
Short name T401
Test name
Test status
Simulation time 505090768 ps
CPU time 1.25 seconds
Started Mar 31 12:24:21 PM PDT 24
Finished Mar 31 12:24:23 PM PDT 24
Peak memory 192932 kb
Host smart-8e52c368-9c00-4595-b17c-edbea2001671
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827409721 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.2827409721
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.1679043138
Short name T338
Test name
Test status
Simulation time 379638472 ps
CPU time 0.64 seconds
Started Mar 31 12:24:26 PM PDT 24
Finished Mar 31 12:24:27 PM PDT 24
Peak memory 183544 kb
Host smart-3f11df24-b30e-4eda-8888-7f3cc526fe8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679043138 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.1679043138
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.665722735
Short name T71
Test name
Test status
Simulation time 1601260070 ps
CPU time 4.13 seconds
Started Mar 31 12:24:48 PM PDT 24
Finished Mar 31 12:24:53 PM PDT 24
Peak memory 193372 kb
Host smart-aa59ad20-83aa-4b6b-bf0c-54b1d804e090
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665722735 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_
timer_same_csr_outstanding.665722735
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.23613392
Short name T310
Test name
Test status
Simulation time 527501990 ps
CPU time 1.93 seconds
Started Mar 31 12:24:19 PM PDT 24
Finished Mar 31 12:24:22 PM PDT 24
Peak memory 198492 kb
Host smart-573ff3c9-0e9e-41ff-a256-89ae79dc5448
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23613392 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.23613392
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.670277790
Short name T97
Test name
Test status
Simulation time 7977307221 ps
CPU time 6.06 seconds
Started Mar 31 12:24:45 PM PDT 24
Finished Mar 31 12:24:52 PM PDT 24
Peak memory 198036 kb
Host smart-595e6696-311b-4c29-83ab-5059b212368e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670277790 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_
intg_err.670277790
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.3552084305
Short name T329
Test name
Test status
Simulation time 504657602 ps
CPU time 0.84 seconds
Started Mar 31 12:25:07 PM PDT 24
Finished Mar 31 12:25:08 PM PDT 24
Peak memory 197368 kb
Host smart-2359c5c3-52fa-4dc3-9bdd-b139f0498706
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552084305 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.3552084305
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.1364021097
Short name T343
Test name
Test status
Simulation time 432218085 ps
CPU time 1.04 seconds
Started Mar 31 12:24:43 PM PDT 24
Finished Mar 31 12:24:44 PM PDT 24
Peak memory 183636 kb
Host smart-02e3e522-1e1d-404b-a979-5e04cc6670a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364021097 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.1364021097
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.113073974
Short name T306
Test name
Test status
Simulation time 464127794 ps
CPU time 0.7 seconds
Started Mar 31 12:24:51 PM PDT 24
Finished Mar 31 12:24:52 PM PDT 24
Peak memory 183576 kb
Host smart-ad393ab1-4c1c-4b60-a933-b6fb06156937
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113073974 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.113073974
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.2499035219
Short name T347
Test name
Test status
Simulation time 921322238 ps
CPU time 0.86 seconds
Started Mar 31 12:24:27 PM PDT 24
Finished Mar 31 12:24:28 PM PDT 24
Peak memory 193156 kb
Host smart-03fcc87a-8b9e-4374-a626-55730ada8a7b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499035219 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon
_timer_same_csr_outstanding.2499035219
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.3241824519
Short name T406
Test name
Test status
Simulation time 506309270 ps
CPU time 1.72 seconds
Started Mar 31 12:26:52 PM PDT 24
Finished Mar 31 12:26:54 PM PDT 24
Peak memory 198468 kb
Host smart-2b4b49e8-d832-4f11-b90f-9b1b0434d1dc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241824519 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.3241824519
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.248369083
Short name T387
Test name
Test status
Simulation time 4130598585 ps
CPU time 7.03 seconds
Started Mar 31 12:25:10 PM PDT 24
Finished Mar 31 12:25:17 PM PDT 24
Peak memory 197792 kb
Host smart-9fcbb382-baad-47f9-bf3d-dede6fb20957
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248369083 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_
intg_err.248369083
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.37097615
Short name T414
Test name
Test status
Simulation time 420450041 ps
CPU time 1.24 seconds
Started Mar 31 12:24:15 PM PDT 24
Finished Mar 31 12:24:17 PM PDT 24
Peak memory 195112 kb
Host smart-8a803d10-b7e8-4ded-9fdb-e4e3906398f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37097615 -assert nopostproc +UVM_TESTNAME=a
on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.37097615
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.3472643601
Short name T51
Test name
Test status
Simulation time 405180668 ps
CPU time 0.64 seconds
Started Mar 31 12:25:04 PM PDT 24
Finished Mar 31 12:25:05 PM PDT 24
Peak memory 183636 kb
Host smart-01eb33ad-9736-4032-9094-b11065f65278
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472643601 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.3472643601
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.550796576
Short name T362
Test name
Test status
Simulation time 502773694 ps
CPU time 0.87 seconds
Started Mar 31 12:24:15 PM PDT 24
Finished Mar 31 12:24:17 PM PDT 24
Peak memory 183572 kb
Host smart-bcb750be-bf86-4d5a-a1bf-c32547009c52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550796576 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.550796576
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.246178915
Short name T67
Test name
Test status
Simulation time 2528926730 ps
CPU time 1.62 seconds
Started Mar 31 12:24:19 PM PDT 24
Finished Mar 31 12:24:22 PM PDT 24
Peak memory 193192 kb
Host smart-e669b155-2c65-471c-a2b0-3325f482f5ad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246178915 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_
timer_same_csr_outstanding.246178915
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.3509404549
Short name T334
Test name
Test status
Simulation time 386653384 ps
CPU time 1.49 seconds
Started Mar 31 12:24:37 PM PDT 24
Finished Mar 31 12:24:38 PM PDT 24
Peak memory 198500 kb
Host smart-95473676-4d39-4498-ab0e-e0670c540520
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509404549 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.3509404549
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.763147304
Short name T370
Test name
Test status
Simulation time 8729585467 ps
CPU time 3.26 seconds
Started Mar 31 12:25:07 PM PDT 24
Finished Mar 31 12:25:11 PM PDT 24
Peak memory 197880 kb
Host smart-c8d33bbc-6ca8-42cd-a5ee-7af681e8b6e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763147304 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_
intg_err.763147304
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.1005329264
Short name T365
Test name
Test status
Simulation time 358497390 ps
CPU time 0.84 seconds
Started Mar 31 12:26:58 PM PDT 24
Finished Mar 31 12:26:59 PM PDT 24
Peak memory 195020 kb
Host smart-8660fca0-dbc2-4e7b-b650-f747c8c28502
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005329264 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.1005329264
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.343984564
Short name T354
Test name
Test status
Simulation time 440209337 ps
CPU time 1.11 seconds
Started Mar 31 12:26:40 PM PDT 24
Finished Mar 31 12:26:41 PM PDT 24
Peak memory 183636 kb
Host smart-bce432bd-65e1-4c28-ae2c-099bcd36471e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343984564 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.343984564
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.305398143
Short name T286
Test name
Test status
Simulation time 360549083 ps
CPU time 0.65 seconds
Started Mar 31 12:24:19 PM PDT 24
Finished Mar 31 12:24:21 PM PDT 24
Peak memory 183580 kb
Host smart-3620eba3-53c3-469a-a46e-c272b5c12d5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305398143 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.305398143
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.571205605
Short name T384
Test name
Test status
Simulation time 1379823255 ps
CPU time 1.14 seconds
Started Mar 31 12:26:52 PM PDT 24
Finished Mar 31 12:26:53 PM PDT 24
Peak memory 193260 kb
Host smart-6bdb27a2-2649-4a0a-a7eb-cb38ca7b2901
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571205605 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_
timer_same_csr_outstanding.571205605
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.1087879551
Short name T292
Test name
Test status
Simulation time 497460346 ps
CPU time 1.93 seconds
Started Mar 31 12:26:51 PM PDT 24
Finished Mar 31 12:26:53 PM PDT 24
Peak memory 198500 kb
Host smart-a129f822-e090-4828-ae69-50879cd0a468
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087879551 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.1087879551
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.2338236502
Short name T405
Test name
Test status
Simulation time 8350530108 ps
CPU time 2.65 seconds
Started Mar 31 12:24:21 PM PDT 24
Finished Mar 31 12:24:24 PM PDT 24
Peak memory 198320 kb
Host smart-8b04f740-cdba-4b5f-bc3d-03c0983f5327
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338236502 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl
_intg_err.2338236502
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.353392045
Short name T314
Test name
Test status
Simulation time 516926719 ps
CPU time 1.25 seconds
Started Mar 31 12:24:20 PM PDT 24
Finished Mar 31 12:24:22 PM PDT 24
Peak memory 198284 kb
Host smart-993057a0-0ee3-404a-88ca-d35eb4ec0c09
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353392045 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.353392045
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.1954329600
Short name T390
Test name
Test status
Simulation time 499239272 ps
CPU time 0.77 seconds
Started Mar 31 12:24:23 PM PDT 24
Finished Mar 31 12:24:24 PM PDT 24
Peak memory 192988 kb
Host smart-af13a04e-d125-46e3-ae69-c02ff140d8db
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954329600 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.1954329600
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.2003708666
Short name T279
Test name
Test status
Simulation time 356439950 ps
CPU time 1.12 seconds
Started Mar 31 12:24:27 PM PDT 24
Finished Mar 31 12:24:28 PM PDT 24
Peak memory 183604 kb
Host smart-f574abd7-90d0-4a24-bbf6-da3d8b366d54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003708666 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.2003708666
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.304118975
Short name T356
Test name
Test status
Simulation time 1376252088 ps
CPU time 1.87 seconds
Started Mar 31 12:24:56 PM PDT 24
Finished Mar 31 12:24:58 PM PDT 24
Peak memory 183808 kb
Host smart-5b4bc0c3-6012-4343-8fc4-f75e58024e4c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304118975 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_
timer_same_csr_outstanding.304118975
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.3460673621
Short name T336
Test name
Test status
Simulation time 415724930 ps
CPU time 1.03 seconds
Started Mar 31 12:24:20 PM PDT 24
Finished Mar 31 12:24:22 PM PDT 24
Peak memory 197748 kb
Host smart-b1811788-1c32-4668-9d2e-40ac098a460a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460673621 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.3460673621
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.706190940
Short name T368
Test name
Test status
Simulation time 4652780974 ps
CPU time 5.81 seconds
Started Mar 31 12:24:24 PM PDT 24
Finished Mar 31 12:24:30 PM PDT 24
Peak memory 196324 kb
Host smart-7fd4108c-297d-4368-8728-4c1a877d93d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706190940 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_
intg_err.706190940
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_jump.4157083870
Short name T269
Test name
Test status
Simulation time 581886927 ps
CPU time 0.81 seconds
Started Mar 31 12:24:45 PM PDT 24
Finished Mar 31 12:24:51 PM PDT 24
Peak memory 183292 kb
Host smart-1923202c-b203-4d1d-a569-89496b8914a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157083870 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.4157083870
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.1700892399
Short name T202
Test name
Test status
Simulation time 40758363630 ps
CPU time 35.13 seconds
Started Mar 31 12:24:31 PM PDT 24
Finished Mar 31 12:25:07 PM PDT 24
Peak memory 183348 kb
Host smart-230d8453-b179-4744-8cc0-2b535d277276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700892399 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.1700892399
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.2373017075
Short name T230
Test name
Test status
Simulation time 497223650 ps
CPU time 1.32 seconds
Started Mar 31 12:24:52 PM PDT 24
Finished Mar 31 12:24:54 PM PDT 24
Peak memory 183272 kb
Host smart-93fb06ba-ef80-4cfd-93d4-26b4ce474ccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373017075 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.2373017075
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.4106686799
Short name T200
Test name
Test status
Simulation time 84455627124 ps
CPU time 63.12 seconds
Started Mar 31 12:24:46 PM PDT 24
Finished Mar 31 12:25:49 PM PDT 24
Peak memory 183360 kb
Host smart-d6e3e628-f47c-4363-b71d-b6df5803e555
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106686799 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_a
ll.4106686799
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.1592663433
Short name T191
Test name
Test status
Simulation time 50233605443 ps
CPU time 180.95 seconds
Started Mar 31 12:24:25 PM PDT 24
Finished Mar 31 12:27:26 PM PDT 24
Peak memory 198280 kb
Host smart-f6d6f9fd-2ec0-4228-90ab-0ff694ca635f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592663433 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.1592663433
Directory /workspace/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.aon_timer_jump.2147585956
Short name T1
Test name
Test status
Simulation time 615628771 ps
CPU time 1.5 seconds
Started Mar 31 12:24:37 PM PDT 24
Finished Mar 31 12:24:38 PM PDT 24
Peak memory 183308 kb
Host smart-c7ccda43-1bff-41e5-8285-e9ad6f6c2c43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147585956 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.2147585956
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.1127038112
Short name T181
Test name
Test status
Simulation time 2930611520 ps
CPU time 5.69 seconds
Started Mar 31 12:24:56 PM PDT 24
Finished Mar 31 12:25:01 PM PDT 24
Peak memory 183364 kb
Host smart-c6f33988-0c69-4930-9576-48645d324bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127038112 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.1127038112
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.1871498746
Short name T23
Test name
Test status
Simulation time 8116466552 ps
CPU time 3.72 seconds
Started Mar 31 12:24:49 PM PDT 24
Finished Mar 31 12:24:53 PM PDT 24
Peak memory 215076 kb
Host smart-92a032c6-815d-44eb-a417-9bc794cb2ef4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871498746 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.1871498746
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.3513312574
Short name T31
Test name
Test status
Simulation time 197775750132 ps
CPU time 78.97 seconds
Started Mar 31 12:24:53 PM PDT 24
Finished Mar 31 12:26:12 PM PDT 24
Peak memory 195208 kb
Host smart-e91b4dab-53d5-4af5-bdbc-d15e7e3e8dd0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513312574 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_a
ll.3513312574
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/10.aon_timer_jump.352701768
Short name T198
Test name
Test status
Simulation time 439139700 ps
CPU time 1.11 seconds
Started Mar 31 12:25:00 PM PDT 24
Finished Mar 31 12:25:02 PM PDT 24
Peak memory 183308 kb
Host smart-825f2129-851b-47b7-9fcc-02f85d38be22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352701768 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.352701768
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.2382586759
Short name T171
Test name
Test status
Simulation time 15407450911 ps
CPU time 5.98 seconds
Started Mar 31 12:25:00 PM PDT 24
Finished Mar 31 12:25:06 PM PDT 24
Peak memory 191564 kb
Host smart-67d5e795-563d-4de2-8043-525b82560ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382586759 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.2382586759
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.3112708657
Short name T102
Test name
Test status
Simulation time 420554458 ps
CPU time 0.7 seconds
Started Mar 31 12:25:02 PM PDT 24
Finished Mar 31 12:25:03 PM PDT 24
Peak memory 183308 kb
Host smart-e893ed8c-a12b-447c-ae31-966b0589f8cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112708657 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.3112708657
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.1094843159
Short name T207
Test name
Test status
Simulation time 12325885590 ps
CPU time 5.95 seconds
Started Mar 31 12:24:58 PM PDT 24
Finished Mar 31 12:25:04 PM PDT 24
Peak memory 194016 kb
Host smart-cadd05c8-4956-425d-8c78-1201b861b223
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094843159 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_
all.1094843159
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.1688387949
Short name T74
Test name
Test status
Simulation time 79633784637 ps
CPU time 615.47 seconds
Started Mar 31 12:25:11 PM PDT 24
Finished Mar 31 12:35:27 PM PDT 24
Peak memory 199536 kb
Host smart-ff7eb7d4-8593-4ae3-aa11-f28014a59ff8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688387949 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.1688387949
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.aon_timer_jump.1152773057
Short name T177
Test name
Test status
Simulation time 489853965 ps
CPU time 0.9 seconds
Started Mar 31 12:24:54 PM PDT 24
Finished Mar 31 12:24:55 PM PDT 24
Peak memory 183292 kb
Host smart-caadb249-6e1a-4163-8ced-1c149b98dfab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152773057 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.1152773057
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.711430078
Short name T243
Test name
Test status
Simulation time 9727995132 ps
CPU time 8.47 seconds
Started Mar 31 12:25:04 PM PDT 24
Finished Mar 31 12:25:12 PM PDT 24
Peak memory 191564 kb
Host smart-33b174ca-7867-48b8-a3d4-4871f7c0e685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711430078 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.711430078
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.4210597993
Short name T242
Test name
Test status
Simulation time 587517714 ps
CPU time 0.95 seconds
Started Mar 31 12:25:06 PM PDT 24
Finished Mar 31 12:25:07 PM PDT 24
Peak memory 183284 kb
Host smart-732a8c85-ca8b-4fd9-bd3c-3f270acf16c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210597993 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.4210597993
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.4047616870
Short name T222
Test name
Test status
Simulation time 200906909700 ps
CPU time 82.23 seconds
Started Mar 31 12:25:02 PM PDT 24
Finished Mar 31 12:26:24 PM PDT 24
Peak memory 193404 kb
Host smart-1724b0cf-1066-4e67-a6df-debd371076ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047616870 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_
all.4047616870
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.3794045817
Short name T120
Test name
Test status
Simulation time 195105660104 ps
CPU time 833.41 seconds
Started Mar 31 12:25:02 PM PDT 24
Finished Mar 31 12:38:55 PM PDT 24
Peak memory 202112 kb
Host smart-fa69f613-f5cc-46ff-a6c6-0038992effaf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794045817 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand_reset.3794045817
Directory /workspace/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.aon_timer_jump.2857775915
Short name T237
Test name
Test status
Simulation time 619607707 ps
CPU time 0.72 seconds
Started Mar 31 12:25:07 PM PDT 24
Finished Mar 31 12:25:08 PM PDT 24
Peak memory 183328 kb
Host smart-341d7ef7-a70f-4e89-9238-270cc9b4873a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857775915 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.2857775915
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.3067322987
Short name T131
Test name
Test status
Simulation time 2961539433 ps
CPU time 3.13 seconds
Started Mar 31 12:25:09 PM PDT 24
Finished Mar 31 12:25:12 PM PDT 24
Peak memory 183384 kb
Host smart-ed02c565-48ad-416c-902f-b491b02c33be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067322987 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.3067322987
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.2255026350
Short name T273
Test name
Test status
Simulation time 452175110 ps
CPU time 1.2 seconds
Started Mar 31 12:24:59 PM PDT 24
Finished Mar 31 12:25:00 PM PDT 24
Peak memory 183288 kb
Host smart-3500d526-ae6d-46cd-96c3-2f4212853a86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255026350 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.2255026350
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.2547923979
Short name T219
Test name
Test status
Simulation time 168901653725 ps
CPU time 262.46 seconds
Started Mar 31 12:24:52 PM PDT 24
Finished Mar 31 12:29:15 PM PDT 24
Peak memory 183380 kb
Host smart-e2feba74-e851-40b9-a6de-a8c8e3e3d9ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547923979 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_
all.2547923979
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.36042204
Short name T9
Test name
Test status
Simulation time 81067514802 ps
CPU time 162.39 seconds
Started Mar 31 12:25:08 PM PDT 24
Finished Mar 31 12:27:51 PM PDT 24
Peak memory 198264 kb
Host smart-00d398b0-c7fe-4e9c-ad8d-d88d6bd22257
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36042204 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.36042204
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_jump.2508986958
Short name T4
Test name
Test status
Simulation time 466221080 ps
CPU time 1.27 seconds
Started Mar 31 12:24:59 PM PDT 24
Finished Mar 31 12:25:00 PM PDT 24
Peak memory 183316 kb
Host smart-2acd0a55-42d2-48af-b476-2a107a640b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508986958 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.2508986958
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.3284498383
Short name T260
Test name
Test status
Simulation time 21353906015 ps
CPU time 34.73 seconds
Started Mar 31 12:24:38 PM PDT 24
Finished Mar 31 12:25:13 PM PDT 24
Peak memory 183356 kb
Host smart-96c241de-bd74-4615-9d67-8af4a6f4d307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284498383 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.3284498383
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.818317614
Short name T255
Test name
Test status
Simulation time 564041915 ps
CPU time 0.94 seconds
Started Mar 31 12:25:06 PM PDT 24
Finished Mar 31 12:25:07 PM PDT 24
Peak memory 183292 kb
Host smart-0280329b-99bf-43eb-937f-9c88d38f149f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818317614 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.818317614
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.930646519
Short name T195
Test name
Test status
Simulation time 168407656690 ps
CPU time 296.97 seconds
Started Mar 31 12:25:10 PM PDT 24
Finished Mar 31 12:30:07 PM PDT 24
Peak memory 195188 kb
Host smart-9981cdc7-4ec2-4d27-b61e-b7f04396618c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930646519 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_a
ll.930646519
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.1660848873
Short name T223
Test name
Test status
Simulation time 21659378489 ps
CPU time 208.57 seconds
Started Mar 31 12:25:04 PM PDT 24
Finished Mar 31 12:28:32 PM PDT 24
Peak memory 198236 kb
Host smart-28799634-0382-48aa-b9fb-21f73383ab5b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660848873 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.1660848873
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.aon_timer_jump.109489768
Short name T26
Test name
Test status
Simulation time 573097211 ps
CPU time 0.96 seconds
Started Mar 31 12:25:08 PM PDT 24
Finished Mar 31 12:25:09 PM PDT 24
Peak memory 183288 kb
Host smart-624e7339-9867-448f-bebd-d9e4c0877cba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109489768 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.109489768
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.2048525458
Short name T254
Test name
Test status
Simulation time 31732471745 ps
CPU time 22.72 seconds
Started Mar 31 12:25:00 PM PDT 24
Finished Mar 31 12:25:23 PM PDT 24
Peak memory 191584 kb
Host smart-7610210f-69d0-4309-8525-320409cd33af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048525458 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.2048525458
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.757253483
Short name T213
Test name
Test status
Simulation time 581839582 ps
CPU time 0.78 seconds
Started Mar 31 12:24:49 PM PDT 24
Finished Mar 31 12:24:50 PM PDT 24
Peak memory 183416 kb
Host smart-ad42477e-b296-4241-a23b-448cd5eb1706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757253483 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.757253483
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.1918893931
Short name T79
Test name
Test status
Simulation time 31113855335 ps
CPU time 226.37 seconds
Started Mar 31 12:25:08 PM PDT 24
Finished Mar 31 12:28:55 PM PDT 24
Peak memory 198196 kb
Host smart-be5261c3-f5e1-4932-a223-ea775c443393
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918893931 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.1918893931
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.aon_timer_jump.3435497208
Short name T83
Test name
Test status
Simulation time 514170936 ps
CPU time 0.98 seconds
Started Mar 31 12:25:00 PM PDT 24
Finished Mar 31 12:25:02 PM PDT 24
Peak memory 183292 kb
Host smart-2dc30648-2ba6-421d-ac70-5ac45f7656a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435497208 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.3435497208
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.1181389168
Short name T149
Test name
Test status
Simulation time 43881530365 ps
CPU time 61.08 seconds
Started Mar 31 12:25:08 PM PDT 24
Finished Mar 31 12:26:09 PM PDT 24
Peak memory 183376 kb
Host smart-d5beca42-0ada-4575-9170-5c489031c45c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181389168 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.1181389168
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.2120370528
Short name T228
Test name
Test status
Simulation time 602457343 ps
CPU time 0.75 seconds
Started Mar 31 12:24:48 PM PDT 24
Finished Mar 31 12:24:49 PM PDT 24
Peak memory 183264 kb
Host smart-246ef742-9a27-4248-9eb4-420a879ca20c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120370528 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.2120370528
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.3833363678
Short name T10
Test name
Test status
Simulation time 180605184196 ps
CPU time 305.71 seconds
Started Mar 31 12:25:09 PM PDT 24
Finished Mar 31 12:30:16 PM PDT 24
Peak memory 193924 kb
Host smart-a097d69c-2cd4-431b-9ce3-8a53710f6133
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833363678 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_
all.3833363678
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_jump.2439748380
Short name T5
Test name
Test status
Simulation time 365867650 ps
CPU time 0.97 seconds
Started Mar 31 12:24:58 PM PDT 24
Finished Mar 31 12:24:59 PM PDT 24
Peak memory 183284 kb
Host smart-7be5b2a0-f099-41b2-92ee-67e6cccb99a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439748380 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.2439748380
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.370989607
Short name T147
Test name
Test status
Simulation time 14916288683 ps
CPU time 11.57 seconds
Started Mar 31 12:25:09 PM PDT 24
Finished Mar 31 12:25:21 PM PDT 24
Peak memory 183376 kb
Host smart-0557188c-b748-41ea-bf29-8b16b2f252da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370989607 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.370989607
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.2638850491
Short name T134
Test name
Test status
Simulation time 566753331 ps
CPU time 0.66 seconds
Started Mar 31 12:25:08 PM PDT 24
Finished Mar 31 12:25:09 PM PDT 24
Peak memory 183288 kb
Host smart-837b622f-f758-446b-b50d-7708fdb8144a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638850491 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.2638850491
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.1047117937
Short name T271
Test name
Test status
Simulation time 205365548166 ps
CPU time 143.07 seconds
Started Mar 31 12:25:07 PM PDT 24
Finished Mar 31 12:27:31 PM PDT 24
Peak memory 194044 kb
Host smart-5af630b9-4370-4a30-82bc-4755c65312b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047117937 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_
all.1047117937
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.1795896716
Short name T80
Test name
Test status
Simulation time 231237399753 ps
CPU time 417.02 seconds
Started Mar 31 12:25:12 PM PDT 24
Finished Mar 31 12:32:09 PM PDT 24
Peak memory 198240 kb
Host smart-02a6d027-80af-4582-83bb-47a47fd6d50c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795896716 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.1795896716
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.aon_timer_jump.2714308718
Short name T142
Test name
Test status
Simulation time 348054370 ps
CPU time 1.03 seconds
Started Mar 31 12:25:03 PM PDT 24
Finished Mar 31 12:25:04 PM PDT 24
Peak memory 183308 kb
Host smart-4cd90680-ce4b-47e1-a817-93de1250d92f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714308718 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.2714308718
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.603730463
Short name T212
Test name
Test status
Simulation time 29724910229 ps
CPU time 15.62 seconds
Started Mar 31 12:25:25 PM PDT 24
Finished Mar 31 12:25:41 PM PDT 24
Peak memory 183360 kb
Host smart-d5f5b223-5a09-4910-8a39-1dea13260809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603730463 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.603730463
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.836160136
Short name T85
Test name
Test status
Simulation time 457709108 ps
CPU time 1.25 seconds
Started Mar 31 12:25:08 PM PDT 24
Finished Mar 31 12:25:11 PM PDT 24
Peak memory 183316 kb
Host smart-9644b358-3784-46a1-81b1-b64a7b657008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836160136 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.836160136
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.2693552
Short name T43
Test name
Test status
Simulation time 13567137186 ps
CPU time 85.62 seconds
Started Mar 31 12:25:00 PM PDT 24
Finished Mar 31 12:26:26 PM PDT 24
Peak memory 198308 kb
Host smart-61e3fe68-ad54-4c30-8e0c-1ea182230f50
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693552 -assert nopos
tproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.2693552
Directory /workspace/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.aon_timer_jump.914007807
Short name T244
Test name
Test status
Simulation time 371173490 ps
CPU time 0.67 seconds
Started Mar 31 12:25:05 PM PDT 24
Finished Mar 31 12:25:05 PM PDT 24
Peak memory 183308 kb
Host smart-1aff1490-872f-4e86-bbf8-c3412516db20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914007807 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.914007807
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.1163364456
Short name T224
Test name
Test status
Simulation time 61091346968 ps
CPU time 91.13 seconds
Started Mar 31 12:25:01 PM PDT 24
Finished Mar 31 12:26:33 PM PDT 24
Peak memory 183352 kb
Host smart-c449bb18-a092-43b7-bb2c-1882eab3c42a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163364456 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.1163364456
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.4007057571
Short name T248
Test name
Test status
Simulation time 364039932 ps
CPU time 1.13 seconds
Started Mar 31 12:25:11 PM PDT 24
Finished Mar 31 12:25:12 PM PDT 24
Peak memory 183324 kb
Host smart-ff5d5430-f7ec-453c-9b7a-dc323b1f3abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007057571 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.4007057571
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.1815412887
Short name T225
Test name
Test status
Simulation time 252528385479 ps
CPU time 187.42 seconds
Started Mar 31 12:25:10 PM PDT 24
Finished Mar 31 12:28:18 PM PDT 24
Peak memory 183560 kb
Host smart-24727be1-7b2d-4d2e-a745-cce7b303cb6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815412887 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_
all.1815412887
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_jump.3090061440
Short name T166
Test name
Test status
Simulation time 405870746 ps
CPU time 0.63 seconds
Started Mar 31 12:25:05 PM PDT 24
Finished Mar 31 12:25:06 PM PDT 24
Peak memory 183288 kb
Host smart-6df99be9-028d-4348-878b-619ad0c9797b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090061440 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.3090061440
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.1398710537
Short name T169
Test name
Test status
Simulation time 15101772416 ps
CPU time 21.25 seconds
Started Mar 31 12:24:55 PM PDT 24
Finished Mar 31 12:25:16 PM PDT 24
Peak memory 183352 kb
Host smart-d6eedd3d-903a-421c-8e54-99557bc7b442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398710537 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.1398710537
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.2360083157
Short name T262
Test name
Test status
Simulation time 564411282 ps
CPU time 1.4 seconds
Started Mar 31 12:25:01 PM PDT 24
Finished Mar 31 12:25:03 PM PDT 24
Peak memory 183288 kb
Host smart-925e752b-2b93-4191-8ff2-e37d7697315b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360083157 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.2360083157
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.917334044
Short name T227
Test name
Test status
Simulation time 110630284499 ps
CPU time 139.02 seconds
Started Mar 31 12:25:04 PM PDT 24
Finished Mar 31 12:27:23 PM PDT 24
Peak memory 193916 kb
Host smart-adf53a3c-aefa-4063-ab4d-b2568be38cac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917334044 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_a
ll.917334044
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.3101847963
Short name T41
Test name
Test status
Simulation time 8790925116 ps
CPU time 76.75 seconds
Started Mar 31 12:25:04 PM PDT 24
Finished Mar 31 12:26:21 PM PDT 24
Peak memory 198248 kb
Host smart-751888bf-73f9-45e0-9887-268b4aa86f80
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101847963 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.3101847963
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_jump.3051705256
Short name T82
Test name
Test status
Simulation time 503711252 ps
CPU time 1.35 seconds
Started Mar 31 12:24:52 PM PDT 24
Finished Mar 31 12:24:53 PM PDT 24
Peak memory 183276 kb
Host smart-db59c1c5-bd79-47ae-bca6-ba5bfd28af2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051705256 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.3051705256
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.501201933
Short name T157
Test name
Test status
Simulation time 27788502266 ps
CPU time 6.12 seconds
Started Mar 31 12:24:40 PM PDT 24
Finished Mar 31 12:24:46 PM PDT 24
Peak memory 183320 kb
Host smart-1df6ed3f-24b0-4198-8aeb-aff16e2663ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501201933 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.501201933
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.4159999862
Short name T22
Test name
Test status
Simulation time 4203342940 ps
CPU time 6.74 seconds
Started Mar 31 12:24:36 PM PDT 24
Finished Mar 31 12:24:43 PM PDT 24
Peak memory 214572 kb
Host smart-7067accf-f549-4a0d-969c-fa645f245e45
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159999862 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.4159999862
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.3896950053
Short name T116
Test name
Test status
Simulation time 506048074 ps
CPU time 0.79 seconds
Started Mar 31 12:24:42 PM PDT 24
Finished Mar 31 12:24:43 PM PDT 24
Peak memory 183284 kb
Host smart-a89efc68-ca3b-40aa-abb7-980a12c43d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896950053 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.3896950053
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.3994864333
Short name T135
Test name
Test status
Simulation time 217122925178 ps
CPU time 181.83 seconds
Started Mar 31 12:24:26 PM PDT 24
Finished Mar 31 12:27:38 PM PDT 24
Peak memory 183540 kb
Host smart-52aa85a6-e1dd-4640-8607-002402d7137f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994864333 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_a
ll.3994864333
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.2836432937
Short name T50
Test name
Test status
Simulation time 42226125124 ps
CPU time 282.94 seconds
Started Mar 31 12:24:39 PM PDT 24
Finished Mar 31 12:29:23 PM PDT 24
Peak memory 198232 kb
Host smart-8c7d4b81-0ad3-4545-a42b-956a43c870a0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836432937 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.2836432937
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.aon_timer_jump.3553554016
Short name T240
Test name
Test status
Simulation time 354665520 ps
CPU time 1.06 seconds
Started Mar 31 12:25:11 PM PDT 24
Finished Mar 31 12:25:12 PM PDT 24
Peak memory 183300 kb
Host smart-f213cf18-0e44-4d44-b70c-d5754a978921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553554016 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.3553554016
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.1814711722
Short name T28
Test name
Test status
Simulation time 4247389069 ps
CPU time 6.54 seconds
Started Mar 31 12:25:01 PM PDT 24
Finished Mar 31 12:25:07 PM PDT 24
Peak memory 183376 kb
Host smart-6d5d0d36-15de-4adb-b8d8-bab29f46cb28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814711722 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.1814711722
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.3900855597
Short name T208
Test name
Test status
Simulation time 551756760 ps
CPU time 0.59 seconds
Started Mar 31 12:24:58 PM PDT 24
Finished Mar 31 12:24:59 PM PDT 24
Peak memory 183252 kb
Host smart-9b89fd09-d756-4cc9-b211-ea63fc1224c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900855597 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.3900855597
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.3301535098
Short name T141
Test name
Test status
Simulation time 317119258833 ps
CPU time 476.19 seconds
Started Mar 31 12:25:07 PM PDT 24
Finished Mar 31 12:33:04 PM PDT 24
Peak memory 183916 kb
Host smart-0d861eb6-ca3b-4568-82f9-6ec81f001933
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301535098 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_
all.3301535098
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.3509486164
Short name T150
Test name
Test status
Simulation time 129260517594 ps
CPU time 102.34 seconds
Started Mar 31 12:24:55 PM PDT 24
Finished Mar 31 12:26:37 PM PDT 24
Peak memory 198236 kb
Host smart-7af696ac-3bc4-4c63-abee-1e89cdf07b76
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509486164 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.3509486164
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_jump.94747462
Short name T144
Test name
Test status
Simulation time 506638792 ps
CPU time 0.95 seconds
Started Mar 31 12:25:02 PM PDT 24
Finished Mar 31 12:25:04 PM PDT 24
Peak memory 183648 kb
Host smart-6f3b3a5b-6e83-43a6-bedf-d1a641ba4bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94747462 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.94747462
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.3052045119
Short name T87
Test name
Test status
Simulation time 30465722974 ps
CPU time 49.25 seconds
Started Mar 31 12:24:57 PM PDT 24
Finished Mar 31 12:25:46 PM PDT 24
Peak memory 191676 kb
Host smart-d58ddb03-33f0-47dc-b4aa-ba129b99ebe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052045119 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.3052045119
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.3555484329
Short name T229
Test name
Test status
Simulation time 345251545 ps
CPU time 0.86 seconds
Started Mar 31 12:25:05 PM PDT 24
Finished Mar 31 12:25:06 PM PDT 24
Peak memory 183312 kb
Host smart-d0443703-3d81-4753-afbe-dffd81ee5ccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555484329 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.3555484329
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.487714888
Short name T190
Test name
Test status
Simulation time 79019522106 ps
CPU time 23.41 seconds
Started Mar 31 12:25:17 PM PDT 24
Finished Mar 31 12:25:40 PM PDT 24
Peak memory 183480 kb
Host smart-e72576a6-7a29-42bd-bc94-72f4e61c1a37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487714888 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_a
ll.487714888
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.583760230
Short name T77
Test name
Test status
Simulation time 163943442717 ps
CPU time 152.45 seconds
Started Mar 31 12:25:07 PM PDT 24
Finished Mar 31 12:27:40 PM PDT 24
Peak memory 198292 kb
Host smart-a8a5b7bc-222a-43f5-9742-f9919d9fe687
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583760230 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.583760230
Directory /workspace/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.aon_timer_jump.1137776963
Short name T12
Test name
Test status
Simulation time 518560425 ps
CPU time 0.81 seconds
Started Mar 31 12:25:06 PM PDT 24
Finished Mar 31 12:25:07 PM PDT 24
Peak memory 183292 kb
Host smart-2eccf6ee-bd5e-427a-be3f-1bbf06e0666b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137776963 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.1137776963
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.2222567797
Short name T258
Test name
Test status
Simulation time 20812129033 ps
CPU time 28.88 seconds
Started Mar 31 12:25:12 PM PDT 24
Finished Mar 31 12:25:41 PM PDT 24
Peak memory 191548 kb
Host smart-7fe42914-aacd-4074-b0c7-92dfd9a0db67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222567797 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.2222567797
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.387272465
Short name T238
Test name
Test status
Simulation time 428075416 ps
CPU time 0.77 seconds
Started Mar 31 12:24:56 PM PDT 24
Finished Mar 31 12:24:57 PM PDT 24
Peak memory 183276 kb
Host smart-f749d3f8-da41-4b73-a1e8-bfe505888bd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387272465 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.387272465
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.3374939732
Short name T158
Test name
Test status
Simulation time 52055947691 ps
CPU time 29.14 seconds
Started Mar 31 12:25:13 PM PDT 24
Finished Mar 31 12:25:43 PM PDT 24
Peak memory 183368 kb
Host smart-318c779e-75c9-4b86-9a87-61bee25698f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374939732 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_
all.3374939732
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.2307461181
Short name T156
Test name
Test status
Simulation time 49759509099 ps
CPU time 441.65 seconds
Started Mar 31 12:25:07 PM PDT 24
Finished Mar 31 12:32:29 PM PDT 24
Peak memory 198304 kb
Host smart-3b34ec88-822f-49cd-9674-13f75994f1dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307461181 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.2307461181
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.aon_timer_jump.469932591
Short name T117
Test name
Test status
Simulation time 524866341 ps
CPU time 0.72 seconds
Started Mar 31 12:25:11 PM PDT 24
Finished Mar 31 12:25:12 PM PDT 24
Peak memory 183316 kb
Host smart-8a2b28c3-0dca-4322-abab-f011f0d3ef28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469932591 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.469932591
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.2297329317
Short name T132
Test name
Test status
Simulation time 4027701183 ps
CPU time 0.99 seconds
Started Mar 31 12:25:11 PM PDT 24
Finished Mar 31 12:25:12 PM PDT 24
Peak memory 183332 kb
Host smart-a4722f0f-15f2-47a5-b67c-36aa02b171b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297329317 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.2297329317
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.411199640
Short name T24
Test name
Test status
Simulation time 541678670 ps
CPU time 0.93 seconds
Started Mar 31 12:25:14 PM PDT 24
Finished Mar 31 12:25:15 PM PDT 24
Peak memory 183300 kb
Host smart-94745411-04ca-4db3-a78b-cf89efb4a2e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411199640 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.411199640
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.1770327196
Short name T148
Test name
Test status
Simulation time 94029569145 ps
CPU time 41.53 seconds
Started Mar 31 12:25:06 PM PDT 24
Finished Mar 31 12:25:47 PM PDT 24
Peak memory 183348 kb
Host smart-b189a9c4-041b-42c7-bad7-6a45e9a9e52b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770327196 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_
all.1770327196
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_jump.2963255998
Short name T133
Test name
Test status
Simulation time 382223054 ps
CPU time 0.8 seconds
Started Mar 31 12:25:04 PM PDT 24
Finished Mar 31 12:25:15 PM PDT 24
Peak memory 183408 kb
Host smart-4a1d0ec8-b550-4a19-856c-8ae7a16902d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963255998 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.2963255998
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.904135568
Short name T121
Test name
Test status
Simulation time 22921234803 ps
CPU time 4.29 seconds
Started Mar 31 12:25:14 PM PDT 24
Finished Mar 31 12:25:18 PM PDT 24
Peak memory 191564 kb
Host smart-a0b4354f-c6b2-4c22-bfe0-8c300e5b14f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904135568 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.904135568
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.1746860933
Short name T27
Test name
Test status
Simulation time 617144786 ps
CPU time 0.7 seconds
Started Mar 31 12:25:04 PM PDT 24
Finished Mar 31 12:25:05 PM PDT 24
Peak memory 183308 kb
Host smart-2941d6e5-f8b6-4b2f-aa71-011a979cb60a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746860933 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.1746860933
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.3103960659
Short name T20
Test name
Test status
Simulation time 199710304555 ps
CPU time 178.47 seconds
Started Mar 31 12:25:05 PM PDT 24
Finished Mar 31 12:28:04 PM PDT 24
Peak memory 193412 kb
Host smart-5ed8bdaa-527d-4289-8b39-95fa1084848b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103960659 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_
all.3103960659
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/25.aon_timer_jump.4095271698
Short name T115
Test name
Test status
Simulation time 542493254 ps
CPU time 1.36 seconds
Started Mar 31 12:25:28 PM PDT 24
Finished Mar 31 12:25:29 PM PDT 24
Peak memory 183296 kb
Host smart-99cb1cd7-4199-4d35-9b2e-300013d9b7b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095271698 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.4095271698
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.1475308328
Short name T104
Test name
Test status
Simulation time 31058806968 ps
CPU time 21.35 seconds
Started Mar 31 12:25:19 PM PDT 24
Finished Mar 31 12:25:40 PM PDT 24
Peak memory 191632 kb
Host smart-68301e71-3c3a-4b87-b76c-5892904085bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475308328 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.1475308328
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.225637577
Short name T112
Test name
Test status
Simulation time 527695943 ps
CPU time 0.92 seconds
Started Mar 31 12:25:11 PM PDT 24
Finished Mar 31 12:25:12 PM PDT 24
Peak memory 183656 kb
Host smart-faca5c8a-503d-442f-9c08-a56ce4c39f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225637577 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.225637577
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.1853975393
Short name T203
Test name
Test status
Simulation time 265401737645 ps
CPU time 204.57 seconds
Started Mar 31 12:25:09 PM PDT 24
Finished Mar 31 12:28:35 PM PDT 24
Peak memory 193872 kb
Host smart-d7720cfb-7907-4681-8a4b-9bdf8c6e2b20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853975393 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_
all.1853975393
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.3772397827
Short name T30
Test name
Test status
Simulation time 107573161430 ps
CPU time 577.01 seconds
Started Mar 31 12:25:05 PM PDT 24
Finished Mar 31 12:34:52 PM PDT 24
Peak memory 199820 kb
Host smart-be77375c-3412-45b1-91fc-68303d4dec13
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772397827 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.3772397827
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.aon_timer_jump.4127134926
Short name T183
Test name
Test status
Simulation time 549116339 ps
CPU time 1.53 seconds
Started Mar 31 12:25:07 PM PDT 24
Finished Mar 31 12:25:09 PM PDT 24
Peak memory 183392 kb
Host smart-fd60b88e-9bba-43d2-ade8-9d0fdf648b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127134926 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.4127134926
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.3305860122
Short name T108
Test name
Test status
Simulation time 61059772616 ps
CPU time 25.06 seconds
Started Mar 31 12:25:10 PM PDT 24
Finished Mar 31 12:25:35 PM PDT 24
Peak memory 183364 kb
Host smart-d5b4b27f-f0e0-4468-a901-1afcc3ac28e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305860122 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.3305860122
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.2089472809
Short name T245
Test name
Test status
Simulation time 460817332 ps
CPU time 0.63 seconds
Started Mar 31 12:25:05 PM PDT 24
Finished Mar 31 12:25:06 PM PDT 24
Peak memory 183368 kb
Host smart-f35f9ee4-a2c7-46bb-a352-41fa649865fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089472809 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.2089472809
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.889977797
Short name T168
Test name
Test status
Simulation time 164008623567 ps
CPU time 61.46 seconds
Started Mar 31 12:25:04 PM PDT 24
Finished Mar 31 12:26:05 PM PDT 24
Peak memory 194116 kb
Host smart-b9eac663-5201-49ce-8b86-a6038967dc36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889977797 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_a
ll.889977797
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.162837738
Short name T256
Test name
Test status
Simulation time 108723339488 ps
CPU time 291.4 seconds
Started Mar 31 12:24:55 PM PDT 24
Finished Mar 31 12:29:47 PM PDT 24
Peak memory 198248 kb
Host smart-c88721c6-cb7e-4dc0-a805-e45c2ef0fab9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162837738 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.162837738
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_jump.1183908085
Short name T161
Test name
Test status
Simulation time 464372813 ps
CPU time 1.29 seconds
Started Mar 31 12:25:13 PM PDT 24
Finished Mar 31 12:25:14 PM PDT 24
Peak memory 183264 kb
Host smart-ccbd621f-2287-49eb-9d14-d5773abb09cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183908085 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.1183908085
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.3319211778
Short name T145
Test name
Test status
Simulation time 10420935741 ps
CPU time 5.19 seconds
Started Mar 31 12:25:07 PM PDT 24
Finished Mar 31 12:25:13 PM PDT 24
Peak memory 183424 kb
Host smart-1cd163b5-19f7-44e2-a730-8867622385f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319211778 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.3319211778
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.3472083939
Short name T151
Test name
Test status
Simulation time 587001519 ps
CPU time 0.71 seconds
Started Mar 31 12:25:05 PM PDT 24
Finished Mar 31 12:25:06 PM PDT 24
Peak memory 183368 kb
Host smart-9171009d-8b22-41ec-acda-db4bf93b4f59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472083939 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.3472083939
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.1672535121
Short name T257
Test name
Test status
Simulation time 34669039316 ps
CPU time 25.6 seconds
Started Mar 31 12:25:04 PM PDT 24
Finished Mar 31 12:25:30 PM PDT 24
Peak memory 183364 kb
Host smart-6225d45f-3d11-4cf5-84b4-e51177ce6cbe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672535121 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_
all.1672535121
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_jump.977700283
Short name T107
Test name
Test status
Simulation time 619449305 ps
CPU time 0.82 seconds
Started Mar 31 12:24:58 PM PDT 24
Finished Mar 31 12:24:58 PM PDT 24
Peak memory 183312 kb
Host smart-84371e73-b699-47ef-a4ac-f475f2491ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977700283 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.977700283
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.2580391049
Short name T146
Test name
Test status
Simulation time 21075097140 ps
CPU time 31.2 seconds
Started Mar 31 12:25:21 PM PDT 24
Finished Mar 31 12:25:53 PM PDT 24
Peak memory 183352 kb
Host smart-8972fd70-2608-4ada-8a58-ca52525a9dfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580391049 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.2580391049
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.1750932409
Short name T174
Test name
Test status
Simulation time 405726258 ps
CPU time 1.25 seconds
Started Mar 31 12:25:52 PM PDT 24
Finished Mar 31 12:25:54 PM PDT 24
Peak memory 182452 kb
Host smart-84e0843e-489d-4125-bd14-bd2feeb07ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750932409 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.1750932409
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.3285689304
Short name T21
Test name
Test status
Simulation time 5401998653 ps
CPU time 3.06 seconds
Started Mar 31 12:27:34 PM PDT 24
Finished Mar 31 12:27:38 PM PDT 24
Peak memory 183396 kb
Host smart-471f3b60-2d62-449f-aed5-156aae757908
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285689304 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_
all.3285689304
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.1751396124
Short name T76
Test name
Test status
Simulation time 40559156502 ps
CPU time 67.83 seconds
Started Mar 31 12:25:06 PM PDT 24
Finished Mar 31 12:26:14 PM PDT 24
Peak memory 198268 kb
Host smart-f6acea93-1d16-4235-8555-a8cdd71ff584
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751396124 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.1751396124
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.aon_timer_jump.4098347235
Short name T268
Test name
Test status
Simulation time 509935722 ps
CPU time 1.1 seconds
Started Mar 31 12:24:56 PM PDT 24
Finished Mar 31 12:24:58 PM PDT 24
Peak memory 183316 kb
Host smart-5b3e790e-d692-481e-b2b9-d165d01515df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098347235 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.4098347235
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.941947717
Short name T99
Test name
Test status
Simulation time 30376138487 ps
CPU time 12.12 seconds
Started Mar 31 12:25:10 PM PDT 24
Finished Mar 31 12:25:22 PM PDT 24
Peak memory 183348 kb
Host smart-6004763a-308b-4cdb-ae30-fd13dc946c0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941947717 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.941947717
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.1226484441
Short name T165
Test name
Test status
Simulation time 609961264 ps
CPU time 0.76 seconds
Started Mar 31 12:26:03 PM PDT 24
Finished Mar 31 12:26:04 PM PDT 24
Peak memory 183228 kb
Host smart-ebf89227-4f22-43a7-9c83-978e5705a1b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226484441 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.1226484441
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.1995005036
Short name T111
Test name
Test status
Simulation time 4870066980 ps
CPU time 2.68 seconds
Started Mar 31 12:25:07 PM PDT 24
Finished Mar 31 12:25:10 PM PDT 24
Peak memory 183368 kb
Host smart-93925543-c3ea-45e3-8626-3a9a62a6890b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995005036 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_
all.1995005036
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.777529359
Short name T73
Test name
Test status
Simulation time 274623748217 ps
CPU time 625.86 seconds
Started Mar 31 12:25:15 PM PDT 24
Finished Mar 31 12:35:41 PM PDT 24
Peak memory 199720 kb
Host smart-af99002e-7d88-4b9c-ba32-28368760c4a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777529359 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.777529359
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.aon_timer_jump.2398210990
Short name T209
Test name
Test status
Simulation time 594417140 ps
CPU time 1.43 seconds
Started Mar 31 12:24:31 PM PDT 24
Finished Mar 31 12:24:32 PM PDT 24
Peak memory 183288 kb
Host smart-4c103b0a-064d-412a-a43d-feb1e9cd0bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398210990 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.2398210990
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.2643399270
Short name T125
Test name
Test status
Simulation time 29552210857 ps
CPU time 23.06 seconds
Started Mar 31 12:24:45 PM PDT 24
Finished Mar 31 12:25:08 PM PDT 24
Peak memory 183340 kb
Host smart-7b01ad78-ef05-4a54-8959-a0e98bf5823c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643399270 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.2643399270
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.2353999394
Short name T18
Test name
Test status
Simulation time 8079511856 ps
CPU time 6.65 seconds
Started Mar 31 12:24:47 PM PDT 24
Finished Mar 31 12:24:54 PM PDT 24
Peak memory 215384 kb
Host smart-8ea3bec8-97d9-48ab-85f0-4877bbea18d9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353999394 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.2353999394
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.1326243210
Short name T204
Test name
Test status
Simulation time 494406670 ps
CPU time 0.7 seconds
Started Mar 31 12:24:36 PM PDT 24
Finished Mar 31 12:24:36 PM PDT 24
Peak memory 183276 kb
Host smart-2a284626-e66e-4e6f-9437-b38c88f78fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326243210 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.1326243210
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.3644444331
Short name T231
Test name
Test status
Simulation time 99586459539 ps
CPU time 142.33 seconds
Started Mar 31 12:24:38 PM PDT 24
Finished Mar 31 12:27:01 PM PDT 24
Peak memory 194072 kb
Host smart-92b500f9-b5c2-45f5-8533-447a52f8afd8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644444331 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_a
ll.3644444331
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.935620483
Short name T42
Test name
Test status
Simulation time 255799294792 ps
CPU time 304.9 seconds
Started Mar 31 12:24:42 PM PDT 24
Finished Mar 31 12:29:47 PM PDT 24
Peak memory 206476 kb
Host smart-e3350c0e-8f08-4da8-944d-bdfcb1dfa704
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935620483 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.935620483
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_jump.3486856641
Short name T164
Test name
Test status
Simulation time 485225910 ps
CPU time 1.19 seconds
Started Mar 31 12:25:07 PM PDT 24
Finished Mar 31 12:25:09 PM PDT 24
Peak memory 183296 kb
Host smart-a5d35a69-a9d4-4eef-8581-6ca682fdd1e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486856641 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.3486856641
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.2383218597
Short name T246
Test name
Test status
Simulation time 26671448338 ps
CPU time 45.46 seconds
Started Mar 31 12:26:03 PM PDT 24
Finished Mar 31 12:26:49 PM PDT 24
Peak memory 191492 kb
Host smart-f20a1a08-301c-4812-a0d8-42aed8610a3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383218597 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.2383218597
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.110059640
Short name T251
Test name
Test status
Simulation time 365158111 ps
CPU time 1.1 seconds
Started Mar 31 12:27:23 PM PDT 24
Finished Mar 31 12:27:25 PM PDT 24
Peak memory 183320 kb
Host smart-7e68f1c7-754e-436e-ba6f-646fdf76a99a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110059640 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.110059640
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.3069855117
Short name T89
Test name
Test status
Simulation time 147500824706 ps
CPU time 26.32 seconds
Started Mar 31 12:25:05 PM PDT 24
Finished Mar 31 12:25:31 PM PDT 24
Peak memory 183380 kb
Host smart-f6a7911d-dfa1-4cac-be7b-a8a8400780aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069855117 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_
all.3069855117
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.218384502
Short name T45
Test name
Test status
Simulation time 175195724603 ps
CPU time 655.5 seconds
Started Mar 31 12:25:06 PM PDT 24
Finished Mar 31 12:36:02 PM PDT 24
Peak memory 200676 kb
Host smart-88dd6986-bf20-4392-a692-c2b9a7789f67
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218384502 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.218384502
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.aon_timer_jump.2135916917
Short name T188
Test name
Test status
Simulation time 455538564 ps
CPU time 1.3 seconds
Started Mar 31 12:25:34 PM PDT 24
Finished Mar 31 12:25:35 PM PDT 24
Peak memory 183268 kb
Host smart-16414617-253c-4f70-989c-41436c86d8c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135916917 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.2135916917
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.3187080726
Short name T153
Test name
Test status
Simulation time 57094350105 ps
CPU time 66.07 seconds
Started Mar 31 12:24:58 PM PDT 24
Finished Mar 31 12:26:05 PM PDT 24
Peak memory 183352 kb
Host smart-441dedd2-50f4-447d-8cf9-2fd7046a47bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187080726 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.3187080726
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.3893495230
Short name T139
Test name
Test status
Simulation time 444329084 ps
CPU time 1.23 seconds
Started Mar 31 12:25:11 PM PDT 24
Finished Mar 31 12:25:12 PM PDT 24
Peak memory 183292 kb
Host smart-47b39d5a-da29-4735-a44f-a2ee4de6cdf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893495230 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.3893495230
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.4023120032
Short name T214
Test name
Test status
Simulation time 159325859728 ps
CPU time 214.13 seconds
Started Mar 31 12:25:15 PM PDT 24
Finished Mar 31 12:28:49 PM PDT 24
Peak memory 183520 kb
Host smart-c9acc8bf-980f-4222-9d88-70e28388a2b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023120032 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_
all.4023120032
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.3827397863
Short name T48
Test name
Test status
Simulation time 404351932012 ps
CPU time 294.93 seconds
Started Mar 31 12:25:11 PM PDT 24
Finished Mar 31 12:30:06 PM PDT 24
Peak memory 198272 kb
Host smart-c70d8292-c7de-46e4-970f-a4dfeb5540b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827397863 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.3827397863
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.aon_timer_jump.1690455255
Short name T127
Test name
Test status
Simulation time 616430876 ps
CPU time 0.97 seconds
Started Mar 31 12:26:03 PM PDT 24
Finished Mar 31 12:26:04 PM PDT 24
Peak memory 183232 kb
Host smart-7e30960a-598d-4dfc-91b3-f073d040ab03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690455255 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.1690455255
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.1182083475
Short name T193
Test name
Test status
Simulation time 24711471516 ps
CPU time 14.94 seconds
Started Mar 31 12:25:10 PM PDT 24
Finished Mar 31 12:25:25 PM PDT 24
Peak memory 183352 kb
Host smart-36465e97-3807-4333-907f-7ab9b84f3b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182083475 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.1182083475
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.3704946532
Short name T179
Test name
Test status
Simulation time 385678407 ps
CPU time 0.65 seconds
Started Mar 31 12:27:30 PM PDT 24
Finished Mar 31 12:27:31 PM PDT 24
Peak memory 183316 kb
Host smart-1194be15-2dbb-4935-80cc-94a58ecd8470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704946532 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.3704946532
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.2045178102
Short name T159
Test name
Test status
Simulation time 174129412073 ps
CPU time 275.02 seconds
Started Mar 31 12:27:44 PM PDT 24
Finished Mar 31 12:32:19 PM PDT 24
Peak memory 193092 kb
Host smart-7b0acd8d-fb08-41f9-a6fa-338253fa8fcb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045178102 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_
all.2045178102
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.2579723265
Short name T40
Test name
Test status
Simulation time 45575386624 ps
CPU time 242.8 seconds
Started Mar 31 12:25:11 PM PDT 24
Finished Mar 31 12:29:14 PM PDT 24
Peak memory 198224 kb
Host smart-561b1b60-ea7a-4c42-a7a4-4dfc700b8dcf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579723265 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_reset.2579723265
Directory /workspace/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.aon_timer_jump.4150083418
Short name T16
Test name
Test status
Simulation time 489476461 ps
CPU time 0.61 seconds
Started Mar 31 12:25:54 PM PDT 24
Finished Mar 31 12:25:55 PM PDT 24
Peak memory 183304 kb
Host smart-7d83321d-fdcf-4435-bdc8-fa6bb5ace065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150083418 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.4150083418
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.956672529
Short name T218
Test name
Test status
Simulation time 9099334803 ps
CPU time 15.35 seconds
Started Mar 31 12:25:11 PM PDT 24
Finished Mar 31 12:25:26 PM PDT 24
Peak memory 183372 kb
Host smart-33280e68-029c-4362-8bca-6bf839f0893d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956672529 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.956672529
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.1693577790
Short name T250
Test name
Test status
Simulation time 484659280 ps
CPU time 1.32 seconds
Started Mar 31 12:25:13 PM PDT 24
Finished Mar 31 12:25:14 PM PDT 24
Peak memory 183200 kb
Host smart-bcd50d00-9535-4b9e-be13-374f969c9f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693577790 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.1693577790
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.2345579666
Short name T266
Test name
Test status
Simulation time 199458367802 ps
CPU time 265.53 seconds
Started Mar 31 12:26:00 PM PDT 24
Finished Mar 31 12:30:26 PM PDT 24
Peak memory 193876 kb
Host smart-d53af2ab-a67a-4dc7-86f3-ea7d0b273b5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345579666 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_
all.2345579666
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.2321129740
Short name T3
Test name
Test status
Simulation time 98343788920 ps
CPU time 264.42 seconds
Started Mar 31 12:25:12 PM PDT 24
Finished Mar 31 12:29:36 PM PDT 24
Peak memory 198228 kb
Host smart-4c451d5a-22ff-4b3d-85d4-9a0f31580651
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321129740 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.2321129740
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.aon_timer_jump.844290007
Short name T199
Test name
Test status
Simulation time 506173027 ps
CPU time 0.58 seconds
Started Mar 31 12:25:28 PM PDT 24
Finished Mar 31 12:25:29 PM PDT 24
Peak memory 183308 kb
Host smart-c2245050-8fef-4077-a668-bb080ec776ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844290007 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.844290007
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.3165540425
Short name T233
Test name
Test status
Simulation time 34715072437 ps
CPU time 26.64 seconds
Started Mar 31 12:25:05 PM PDT 24
Finished Mar 31 12:25:32 PM PDT 24
Peak memory 183448 kb
Host smart-be9709cf-60ac-426f-b1c3-abc56dd6a123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165540425 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.3165540425
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.2031863557
Short name T184
Test name
Test status
Simulation time 334741623 ps
CPU time 1.07 seconds
Started Mar 31 12:24:57 PM PDT 24
Finished Mar 31 12:24:58 PM PDT 24
Peak memory 183268 kb
Host smart-c21bab0e-527a-4d45-94e3-a683281c6c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031863557 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.2031863557
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.861310567
Short name T180
Test name
Test status
Simulation time 275246227635 ps
CPU time 97.93 seconds
Started Mar 31 12:25:11 PM PDT 24
Finished Mar 31 12:26:49 PM PDT 24
Peak memory 183540 kb
Host smart-fad7afb6-3104-4f1a-9c2a-cd127e6c2e3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861310567 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_a
ll.861310567
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.917350926
Short name T205
Test name
Test status
Simulation time 102594661670 ps
CPU time 275.52 seconds
Started Mar 31 12:25:11 PM PDT 24
Finished Mar 31 12:29:46 PM PDT 24
Peak memory 198256 kb
Host smart-7c99c5f3-2763-4f0a-ac77-2b58ca1cb504
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917350926 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.917350926
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.aon_timer_jump.3499361579
Short name T106
Test name
Test status
Simulation time 540718368 ps
CPU time 0.72 seconds
Started Mar 31 12:25:12 PM PDT 24
Finished Mar 31 12:25:12 PM PDT 24
Peak memory 183324 kb
Host smart-2d65b63c-b087-4063-9f0e-a151da52dcda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499361579 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.3499361579
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.4287072506
Short name T119
Test name
Test status
Simulation time 2257928286 ps
CPU time 4.03 seconds
Started Mar 31 12:25:15 PM PDT 24
Finished Mar 31 12:25:19 PM PDT 24
Peak memory 181456 kb
Host smart-4442bd21-0abb-48eb-8033-320a37a0d332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287072506 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.4287072506
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.3319195197
Short name T129
Test name
Test status
Simulation time 505474282 ps
CPU time 0.73 seconds
Started Mar 31 12:25:20 PM PDT 24
Finished Mar 31 12:25:21 PM PDT 24
Peak memory 183300 kb
Host smart-9211b8a0-f4ea-4b87-9c3a-0c1fab4fa2cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319195197 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.3319195197
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.2892235216
Short name T90
Test name
Test status
Simulation time 107843801186 ps
CPU time 173.49 seconds
Started Mar 31 12:26:01 PM PDT 24
Finished Mar 31 12:28:55 PM PDT 24
Peak memory 194716 kb
Host smart-1431610e-2c75-44d8-b6a4-86d81868bfda
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892235216 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_
all.2892235216
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.3162030954
Short name T49
Test name
Test status
Simulation time 178721887681 ps
CPU time 906.42 seconds
Started Mar 31 12:25:13 PM PDT 24
Finished Mar 31 12:40:19 PM PDT 24
Peak memory 203456 kb
Host smart-0974ecae-aaa3-435c-aa31-a7309fa45278
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162030954 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.3162030954
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.aon_timer_jump.3492374651
Short name T154
Test name
Test status
Simulation time 446337837 ps
CPU time 0.82 seconds
Started Mar 31 12:25:15 PM PDT 24
Finished Mar 31 12:25:16 PM PDT 24
Peak memory 181436 kb
Host smart-23c5ff99-94cd-4bfb-ba40-c7a47490331d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492374651 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.3492374651
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.1783143193
Short name T270
Test name
Test status
Simulation time 11246033925 ps
CPU time 5.07 seconds
Started Mar 31 12:25:18 PM PDT 24
Finished Mar 31 12:25:23 PM PDT 24
Peak memory 183328 kb
Host smart-0a986c3c-48cd-4877-9246-952e6b1a7bb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783143193 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.1783143193
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.1666745790
Short name T105
Test name
Test status
Simulation time 591667027 ps
CPU time 0.91 seconds
Started Mar 31 12:25:06 PM PDT 24
Finished Mar 31 12:25:07 PM PDT 24
Peak memory 183408 kb
Host smart-8e3b58d7-d061-45d2-a23a-ad4d56e06fe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666745790 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.1666745790
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.1440673972
Short name T216
Test name
Test status
Simulation time 211804141967 ps
CPU time 103.2 seconds
Started Mar 31 12:25:05 PM PDT 24
Finished Mar 31 12:26:48 PM PDT 24
Peak memory 183516 kb
Host smart-9428d70e-3237-40ed-bd26-8e4f6c929d24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440673972 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_
all.1440673972
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.3403596990
Short name T232
Test name
Test status
Simulation time 40441954943 ps
CPU time 421.94 seconds
Started Mar 31 12:25:06 PM PDT 24
Finished Mar 31 12:32:08 PM PDT 24
Peak memory 198304 kb
Host smart-8aa3fce3-9d71-418b-bc4c-894ed23a5016
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403596990 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.3403596990
Directory /workspace/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.aon_timer_jump.3431423455
Short name T217
Test name
Test status
Simulation time 496737199 ps
CPU time 0.9 seconds
Started Mar 31 12:25:16 PM PDT 24
Finished Mar 31 12:25:17 PM PDT 24
Peak memory 183240 kb
Host smart-a344edbd-b21f-4673-8f89-bb99819b72f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431423455 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.3431423455
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.711233805
Short name T249
Test name
Test status
Simulation time 41465843285 ps
CPU time 6.58 seconds
Started Mar 31 12:25:11 PM PDT 24
Finished Mar 31 12:25:18 PM PDT 24
Peak memory 183372 kb
Host smart-2ef87a34-dac9-4ed0-9099-df5aa05ab06f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711233805 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.711233805
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.1972361637
Short name T8
Test name
Test status
Simulation time 543044107 ps
CPU time 1.49 seconds
Started Mar 31 12:25:19 PM PDT 24
Finished Mar 31 12:25:20 PM PDT 24
Peak memory 183316 kb
Host smart-dfefa4be-d59f-4ade-a41d-6177349dacb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972361637 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.1972361637
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.766745867
Short name T234
Test name
Test status
Simulation time 135138800215 ps
CPU time 55.46 seconds
Started Mar 31 12:25:34 PM PDT 24
Finished Mar 31 12:26:30 PM PDT 24
Peak memory 183292 kb
Host smart-9c71cd63-03c2-4152-9126-536cad01ecd1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766745867 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_a
ll.766745867
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.2507103274
Short name T176
Test name
Test status
Simulation time 69202342839 ps
CPU time 372.51 seconds
Started Mar 31 12:25:58 PM PDT 24
Finished Mar 31 12:32:11 PM PDT 24
Peak memory 198288 kb
Host smart-e9fc1fa7-64cc-4b57-8a65-7359b23b4ba9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507103274 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.2507103274
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.aon_timer_jump.3072141880
Short name T86
Test name
Test status
Simulation time 567987445 ps
CPU time 0.7 seconds
Started Mar 31 12:25:00 PM PDT 24
Finished Mar 31 12:25:01 PM PDT 24
Peak memory 183316 kb
Host smart-2e444ea1-e18a-459d-a87e-4c378ca65415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072141880 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.3072141880
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.1662675580
Short name T247
Test name
Test status
Simulation time 9536680219 ps
CPU time 1.42 seconds
Started Mar 31 12:25:57 PM PDT 24
Finished Mar 31 12:25:59 PM PDT 24
Peak memory 191564 kb
Host smart-4640f9e7-bce8-4236-b9de-4417bbc590a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662675580 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.1662675580
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.1205292936
Short name T137
Test name
Test status
Simulation time 535854257 ps
CPU time 1.25 seconds
Started Mar 31 12:25:16 PM PDT 24
Finished Mar 31 12:25:23 PM PDT 24
Peak memory 183240 kb
Host smart-07aa5986-9a09-496c-97eb-f5d902ce4a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205292936 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.1205292936
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_jump.1512651317
Short name T13
Test name
Test status
Simulation time 633743317 ps
CPU time 0.88 seconds
Started Mar 31 12:25:15 PM PDT 24
Finished Mar 31 12:25:16 PM PDT 24
Peak memory 181488 kb
Host smart-39baaf70-cb37-469e-a86e-6bd1cbe90bb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512651317 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.1512651317
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.3053389438
Short name T143
Test name
Test status
Simulation time 20338279285 ps
CPU time 33.93 seconds
Started Mar 31 12:25:05 PM PDT 24
Finished Mar 31 12:25:39 PM PDT 24
Peak memory 183476 kb
Host smart-b0bf1fd2-fc2d-4e9e-8ad8-5c580a3be93f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053389438 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.3053389438
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.251147268
Short name T155
Test name
Test status
Simulation time 533851079 ps
CPU time 0.73 seconds
Started Mar 31 12:25:08 PM PDT 24
Finished Mar 31 12:25:09 PM PDT 24
Peak memory 183252 kb
Host smart-42033572-6eec-4018-a22b-03aa37fdc56d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251147268 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.251147268
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.2751381128
Short name T109
Test name
Test status
Simulation time 533113235028 ps
CPU time 50.63 seconds
Started Mar 31 12:25:23 PM PDT 24
Finished Mar 31 12:26:14 PM PDT 24
Peak memory 183400 kb
Host smart-b15f1459-ac50-4e18-9ccf-5b3b07a620ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751381128 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_
all.2751381128
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.4223116093
Short name T75
Test name
Test status
Simulation time 41213209753 ps
CPU time 310.82 seconds
Started Mar 31 12:25:15 PM PDT 24
Finished Mar 31 12:30:26 PM PDT 24
Peak memory 197988 kb
Host smart-0b98e4cb-c441-4461-b08a-663d9bb0aba9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223116093 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.4223116093
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_jump.1133323106
Short name T15
Test name
Test status
Simulation time 449520564 ps
CPU time 0.94 seconds
Started Mar 31 12:24:53 PM PDT 24
Finished Mar 31 12:24:55 PM PDT 24
Peak memory 183272 kb
Host smart-8a4ae3e4-5911-4ead-a3e1-c164be86e6d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133323106 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.1133323106
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.3707864281
Short name T253
Test name
Test status
Simulation time 5651027524 ps
CPU time 2.32 seconds
Started Mar 31 12:24:34 PM PDT 24
Finished Mar 31 12:24:36 PM PDT 24
Peak memory 183332 kb
Host smart-dbd58ea4-233c-4a4d-a08f-5f7298889398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707864281 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.3707864281
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.3611842947
Short name T19
Test name
Test status
Simulation time 3975626262 ps
CPU time 7.08 seconds
Started Mar 31 12:24:42 PM PDT 24
Finished Mar 31 12:24:49 PM PDT 24
Peak memory 214676 kb
Host smart-1650d4ec-d99c-4b40-8e5d-1db9a7606b05
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611842947 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.3611842947
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.1435299424
Short name T206
Test name
Test status
Simulation time 495177107 ps
CPU time 0.97 seconds
Started Mar 31 12:25:02 PM PDT 24
Finished Mar 31 12:25:04 PM PDT 24
Peak memory 183296 kb
Host smart-be281a65-0b21-4c15-9c9c-09dad76fef2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435299424 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.1435299424
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.2027845793
Short name T124
Test name
Test status
Simulation time 94967025383 ps
CPU time 14.2 seconds
Started Mar 31 12:25:06 PM PDT 24
Finished Mar 31 12:25:20 PM PDT 24
Peak memory 183332 kb
Host smart-c441e668-609b-4abd-9d51-5e4e4fa5d052
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027845793 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_a
ll.2027845793
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.1493698091
Short name T264
Test name
Test status
Simulation time 68312319633 ps
CPU time 144.49 seconds
Started Mar 31 12:24:46 PM PDT 24
Finished Mar 31 12:27:11 PM PDT 24
Peak memory 198240 kb
Host smart-c1957bd3-500c-4bd5-8cd4-8ef08e889ae5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493698091 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.1493698091
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.aon_timer_jump.3376242122
Short name T100
Test name
Test status
Simulation time 557228112 ps
CPU time 0.69 seconds
Started Mar 31 12:25:10 PM PDT 24
Finished Mar 31 12:25:11 PM PDT 24
Peak memory 183280 kb
Host smart-7ba058c5-3f0d-4885-928a-cddfbb413baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376242122 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.3376242122
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.389537476
Short name T175
Test name
Test status
Simulation time 19939336406 ps
CPU time 8.02 seconds
Started Mar 31 12:25:15 PM PDT 24
Finished Mar 31 12:25:23 PM PDT 24
Peak memory 181236 kb
Host smart-cd033625-e685-4402-ae66-ce35520e5a6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389537476 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.389537476
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.1535119793
Short name T172
Test name
Test status
Simulation time 580231826 ps
CPU time 0.97 seconds
Started Mar 31 12:25:13 PM PDT 24
Finished Mar 31 12:25:14 PM PDT 24
Peak memory 183316 kb
Host smart-a1534fa0-73e9-4f5c-8290-ea239450ee76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535119793 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.1535119793
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.328897808
Short name T252
Test name
Test status
Simulation time 70930903701 ps
CPU time 69.75 seconds
Started Mar 31 12:25:14 PM PDT 24
Finished Mar 31 12:26:24 PM PDT 24
Peak memory 183532 kb
Host smart-2dc0a40e-b35c-4960-bbb4-a20d1cb8734c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328897808 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_a
ll.328897808
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_jump.589210339
Short name T110
Test name
Test status
Simulation time 510750838 ps
CPU time 1.24 seconds
Started Mar 31 12:25:40 PM PDT 24
Finished Mar 31 12:25:42 PM PDT 24
Peak memory 183192 kb
Host smart-44f70d0f-5db3-4708-8a02-36db989defc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589210339 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.589210339
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.3806815387
Short name T130
Test name
Test status
Simulation time 30650819855 ps
CPU time 52.71 seconds
Started Mar 31 12:25:12 PM PDT 24
Finished Mar 31 12:26:05 PM PDT 24
Peak memory 191556 kb
Host smart-733cca18-dae3-417f-9e53-73c9e232bf59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806815387 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.3806815387
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.3804640893
Short name T128
Test name
Test status
Simulation time 401156869 ps
CPU time 1.07 seconds
Started Mar 31 12:25:05 PM PDT 24
Finished Mar 31 12:25:06 PM PDT 24
Peak memory 183300 kb
Host smart-93ccc860-19e2-4019-a12d-ecda2c063483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804640893 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.3804640893
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.478065681
Short name T210
Test name
Test status
Simulation time 105699249847 ps
CPU time 118.91 seconds
Started Mar 31 12:25:11 PM PDT 24
Finished Mar 31 12:27:10 PM PDT 24
Peak memory 183516 kb
Host smart-5c040d72-b1ff-4e81-b9d3-96566a887c69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478065681 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_a
ll.478065681
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/42.aon_timer_jump.1127733865
Short name T197
Test name
Test status
Simulation time 579347642 ps
CPU time 0.99 seconds
Started Mar 31 12:26:00 PM PDT 24
Finished Mar 31 12:26:01 PM PDT 24
Peak memory 183344 kb
Host smart-9ff707cc-e527-4f6d-9108-8fd65520f0ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127733865 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.1127733865
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.1997806660
Short name T167
Test name
Test status
Simulation time 12206042207 ps
CPU time 18.1 seconds
Started Mar 31 12:26:01 PM PDT 24
Finished Mar 31 12:26:19 PM PDT 24
Peak memory 183356 kb
Host smart-fc37f0d5-d602-4c7d-aac6-c99dc615e7d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997806660 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.1997806660
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.4086761351
Short name T152
Test name
Test status
Simulation time 405654280 ps
CPU time 0.83 seconds
Started Mar 31 12:25:13 PM PDT 24
Finished Mar 31 12:25:14 PM PDT 24
Peak memory 183284 kb
Host smart-38258b06-b328-48f9-9295-b74a4e0a6a10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086761351 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.4086761351
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.3999902713
Short name T265
Test name
Test status
Simulation time 150823769992 ps
CPU time 54.64 seconds
Started Mar 31 12:25:07 PM PDT 24
Finished Mar 31 12:26:02 PM PDT 24
Peak memory 194900 kb
Host smart-569076e2-8a1b-4463-b0fb-52331c7ab737
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999902713 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_
all.3999902713
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.3959067402
Short name T91
Test name
Test status
Simulation time 212483210770 ps
CPU time 614.66 seconds
Started Mar 31 12:25:15 PM PDT 24
Finished Mar 31 12:35:30 PM PDT 24
Peak memory 213764 kb
Host smart-475f2160-6f37-4c9d-aaa8-1b97b9c242a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959067402 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.3959067402
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.aon_timer_jump.1034031178
Short name T103
Test name
Test status
Simulation time 516564485 ps
CPU time 0.71 seconds
Started Mar 31 12:25:16 PM PDT 24
Finished Mar 31 12:25:17 PM PDT 24
Peak memory 183292 kb
Host smart-daa82852-6cdc-4ae7-95a2-04e0d58b4a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034031178 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.1034031178
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.2107715130
Short name T187
Test name
Test status
Simulation time 3931768071 ps
CPU time 1.76 seconds
Started Mar 31 12:25:13 PM PDT 24
Finished Mar 31 12:25:14 PM PDT 24
Peak memory 183364 kb
Host smart-c0e9bf1c-314f-4664-af61-4c8066e2a62a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107715130 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.2107715130
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.403678916
Short name T215
Test name
Test status
Simulation time 378058797 ps
CPU time 0.72 seconds
Started Mar 31 12:25:11 PM PDT 24
Finished Mar 31 12:25:12 PM PDT 24
Peak memory 183700 kb
Host smart-ca3aa6a0-0cc7-49a9-8be1-d5f31da4a404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403678916 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.403678916
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.3800751190
Short name T235
Test name
Test status
Simulation time 170199683358 ps
CPU time 132.23 seconds
Started Mar 31 12:25:34 PM PDT 24
Finished Mar 31 12:27:46 PM PDT 24
Peak memory 183388 kb
Host smart-ef950b51-eb1d-4c6f-b4f4-a6abc118802b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800751190 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_
all.3800751190
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.690526084
Short name T226
Test name
Test status
Simulation time 70557082331 ps
CPU time 547.71 seconds
Started Mar 31 12:25:12 PM PDT 24
Finished Mar 31 12:34:20 PM PDT 24
Peak memory 198252 kb
Host smart-1b8f26cc-21a3-4964-8e49-674a949329d8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690526084 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.690526084
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.aon_timer_jump.2626201892
Short name T6
Test name
Test status
Simulation time 704197904 ps
CPU time 0.61 seconds
Started Mar 31 12:25:00 PM PDT 24
Finished Mar 31 12:25:01 PM PDT 24
Peak memory 183300 kb
Host smart-df3edab7-9a7f-4686-9528-df9022e483ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626201892 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.2626201892
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.2757193505
Short name T46
Test name
Test status
Simulation time 8031051089 ps
CPU time 5.79 seconds
Started Mar 31 12:25:10 PM PDT 24
Finished Mar 31 12:25:16 PM PDT 24
Peak memory 183340 kb
Host smart-5d476077-9aa4-4222-9905-145b8733fc16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757193505 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.2757193505
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.182072958
Short name T101
Test name
Test status
Simulation time 546973530 ps
CPU time 1.39 seconds
Started Mar 31 12:25:21 PM PDT 24
Finished Mar 31 12:25:23 PM PDT 24
Peak memory 183296 kb
Host smart-05758462-7e24-40ab-972e-19afd24ea118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182072958 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.182072958
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.3468098001
Short name T93
Test name
Test status
Simulation time 47205210405 ps
CPU time 19.94 seconds
Started Mar 31 12:25:40 PM PDT 24
Finished Mar 31 12:26:01 PM PDT 24
Peak memory 183348 kb
Host smart-0bef9433-14f2-4f63-a2e3-ad19ef329421
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468098001 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_
all.3468098001
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_jump.3316634118
Short name T272
Test name
Test status
Simulation time 444802961 ps
CPU time 0.6 seconds
Started Mar 31 12:25:24 PM PDT 24
Finished Mar 31 12:25:24 PM PDT 24
Peak memory 183296 kb
Host smart-384a0e40-a945-43df-bdfe-e976081951b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316634118 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.3316634118
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.699526282
Short name T126
Test name
Test status
Simulation time 33099267918 ps
CPU time 12.49 seconds
Started Mar 31 12:25:14 PM PDT 24
Finished Mar 31 12:25:26 PM PDT 24
Peak memory 183372 kb
Host smart-23b30d05-c8c8-4f1e-aa0f-3253d8cf2687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699526282 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.699526282
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.3360451979
Short name T220
Test name
Test status
Simulation time 385586627 ps
CPU time 0.85 seconds
Started Mar 31 12:25:06 PM PDT 24
Finished Mar 31 12:25:07 PM PDT 24
Peak memory 183280 kb
Host smart-197b59e9-0611-4351-a756-e671b161e521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360451979 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.3360451979
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.1032347163
Short name T160
Test name
Test status
Simulation time 9389706789 ps
CPU time 4.92 seconds
Started Mar 31 12:25:11 PM PDT 24
Finished Mar 31 12:25:16 PM PDT 24
Peak memory 183340 kb
Host smart-79387d12-b8bd-4476-b3af-41bd6882e07a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032347163 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_
all.1032347163
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.2415083002
Short name T72
Test name
Test status
Simulation time 40809902999 ps
CPU time 232.77 seconds
Started Mar 31 12:25:30 PM PDT 24
Finished Mar 31 12:29:23 PM PDT 24
Peak memory 198252 kb
Host smart-f97ef8a1-4986-4cfa-8fc9-ad48e96b0769
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415083002 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.2415083002
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.aon_timer_jump.1460365500
Short name T81
Test name
Test status
Simulation time 561904955 ps
CPU time 0.66 seconds
Started Mar 31 12:25:10 PM PDT 24
Finished Mar 31 12:25:11 PM PDT 24
Peak memory 183700 kb
Host smart-54073cd3-3a4a-4eca-b3af-02712e008040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460365500 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.1460365500
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.3526907778
Short name T25
Test name
Test status
Simulation time 20646350382 ps
CPU time 27.59 seconds
Started Mar 31 12:25:06 PM PDT 24
Finished Mar 31 12:25:34 PM PDT 24
Peak memory 191548 kb
Host smart-8fd20e97-4d05-40e7-8a20-cd31579a2bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526907778 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.3526907778
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.2903509176
Short name T221
Test name
Test status
Simulation time 580220456 ps
CPU time 1.51 seconds
Started Mar 31 12:25:12 PM PDT 24
Finished Mar 31 12:25:13 PM PDT 24
Peak memory 183320 kb
Host smart-1e182de5-e7e9-4daa-93d6-0b40582d9809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903509176 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.2903509176
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.3596618192
Short name T201
Test name
Test status
Simulation time 193039898411 ps
CPU time 41.27 seconds
Started Mar 31 12:25:14 PM PDT 24
Finished Mar 31 12:25:56 PM PDT 24
Peak memory 191564 kb
Host smart-0ef2777a-e494-464e-9af7-02df00f05925
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596618192 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_
all.3596618192
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_jump.1387437760
Short name T122
Test name
Test status
Simulation time 421638982 ps
CPU time 0.71 seconds
Started Mar 31 12:25:13 PM PDT 24
Finished Mar 31 12:25:14 PM PDT 24
Peak memory 183328 kb
Host smart-320664bc-59dc-402b-b13f-4a955501ea04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387437760 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.1387437760
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.2816100016
Short name T211
Test name
Test status
Simulation time 4861259139 ps
CPU time 2.45 seconds
Started Mar 31 12:25:14 PM PDT 24
Finished Mar 31 12:25:17 PM PDT 24
Peak memory 183316 kb
Host smart-a1ba720b-1b1e-4b11-b8cf-6c339de4c42b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816100016 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.2816100016
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.3837215977
Short name T194
Test name
Test status
Simulation time 523119561 ps
CPU time 1.45 seconds
Started Mar 31 12:25:14 PM PDT 24
Finished Mar 31 12:25:16 PM PDT 24
Peak memory 183260 kb
Host smart-35b0d434-78d3-4282-9f65-0e99062be8c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837215977 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.3837215977
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.2960953267
Short name T263
Test name
Test status
Simulation time 39935166728 ps
CPU time 291.92 seconds
Started Mar 31 12:25:10 PM PDT 24
Finished Mar 31 12:30:02 PM PDT 24
Peak memory 198256 kb
Host smart-cbad2390-c0d5-437d-a3ab-24196be1cf0a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960953267 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.2960953267
Directory /workspace/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_jump.3536017665
Short name T259
Test name
Test status
Simulation time 541073248 ps
CPU time 1.33 seconds
Started Mar 31 12:25:23 PM PDT 24
Finished Mar 31 12:25:24 PM PDT 24
Peak memory 183316 kb
Host smart-42fc588d-f950-48eb-8eac-6f7d378a7960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536017665 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.3536017665
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.1450665270
Short name T274
Test name
Test status
Simulation time 39904411666 ps
CPU time 15.12 seconds
Started Mar 31 12:25:16 PM PDT 24
Finished Mar 31 12:25:32 PM PDT 24
Peak memory 191480 kb
Host smart-f60420f4-f8cb-43c0-a06d-56ca4ec70069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450665270 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.1450665270
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.2852666612
Short name T114
Test name
Test status
Simulation time 425204640 ps
CPU time 0.67 seconds
Started Mar 31 12:25:11 PM PDT 24
Finished Mar 31 12:25:12 PM PDT 24
Peak memory 183228 kb
Host smart-3dfa9a55-4267-41ef-a485-e0c92d8baadc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852666612 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.2852666612
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.2639523312
Short name T261
Test name
Test status
Simulation time 23044797271 ps
CPU time 115.71 seconds
Started Mar 31 12:25:16 PM PDT 24
Finished Mar 31 12:27:12 PM PDT 24
Peak memory 198148 kb
Host smart-0958852d-992b-48e8-9609-16f6fef8dfa1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639523312 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.2639523312
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.aon_timer_jump.3640004066
Short name T136
Test name
Test status
Simulation time 352334499 ps
CPU time 1.09 seconds
Started Mar 31 12:25:33 PM PDT 24
Finished Mar 31 12:25:35 PM PDT 24
Peak memory 183288 kb
Host smart-5651310b-f687-402a-abd7-f266ec4d3ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640004066 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.3640004066
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.2229080579
Short name T162
Test name
Test status
Simulation time 34964599140 ps
CPU time 56.05 seconds
Started Mar 31 12:25:14 PM PDT 24
Finished Mar 31 12:26:11 PM PDT 24
Peak memory 191536 kb
Host smart-d6970539-bec2-454a-a10c-0e097ee96347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229080579 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.2229080579
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.4027827771
Short name T186
Test name
Test status
Simulation time 352601898 ps
CPU time 0.77 seconds
Started Mar 31 12:25:14 PM PDT 24
Finished Mar 31 12:25:15 PM PDT 24
Peak memory 183184 kb
Host smart-c77ee893-e96a-4708-9e1f-c330ca2f0f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027827771 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.4027827771
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.735524571
Short name T138
Test name
Test status
Simulation time 102812439536 ps
CPU time 154.78 seconds
Started Mar 31 12:25:09 PM PDT 24
Finished Mar 31 12:27:44 PM PDT 24
Peak memory 183368 kb
Host smart-a6edb291-0dc9-4813-96e9-be6f9cfb922b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735524571 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_a
ll.735524571
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.655768007
Short name T241
Test name
Test status
Simulation time 343566799953 ps
CPU time 923.52 seconds
Started Mar 31 12:25:14 PM PDT 24
Finished Mar 31 12:40:38 PM PDT 24
Peak memory 204072 kb
Host smart-7fabad8d-602e-46fa-8312-f7acf1505485
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655768007 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.655768007
Directory /workspace/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.aon_timer_jump.455299736
Short name T182
Test name
Test status
Simulation time 424265063 ps
CPU time 0.67 seconds
Started Mar 31 12:24:36 PM PDT 24
Finished Mar 31 12:24:37 PM PDT 24
Peak memory 183284 kb
Host smart-a30d4186-1dfb-4075-81fe-b05a24227e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455299736 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.455299736
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.132986786
Short name T196
Test name
Test status
Simulation time 39041373112 ps
CPU time 59.29 seconds
Started Mar 31 12:24:52 PM PDT 24
Finished Mar 31 12:25:51 PM PDT 24
Peak memory 191564 kb
Host smart-e7227e9e-3111-464e-8568-32dd7c41d0d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132986786 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.132986786
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.3646392662
Short name T267
Test name
Test status
Simulation time 442323758 ps
CPU time 1.13 seconds
Started Mar 31 12:24:44 PM PDT 24
Finished Mar 31 12:24:46 PM PDT 24
Peak memory 183276 kb
Host smart-1a86a4ff-2c01-4c78-95e2-8bbc100f82cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646392662 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.3646392662
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.1001708452
Short name T123
Test name
Test status
Simulation time 471201458774 ps
CPU time 807.91 seconds
Started Mar 31 12:24:40 PM PDT 24
Finished Mar 31 12:38:08 PM PDT 24
Peak memory 195208 kb
Host smart-291d4bb5-c93a-45d1-a066-b1c09a88d6a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001708452 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_a
ll.1001708452
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_jump.1105914851
Short name T189
Test name
Test status
Simulation time 415554708 ps
CPU time 0.87 seconds
Started Mar 31 12:25:00 PM PDT 24
Finished Mar 31 12:25:01 PM PDT 24
Peak memory 183312 kb
Host smart-0383d8bf-b431-47ef-9e6d-9b69b90aec29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105914851 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.1105914851
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.2184971326
Short name T7
Test name
Test status
Simulation time 42368775257 ps
CPU time 18.25 seconds
Started Mar 31 12:24:52 PM PDT 24
Finished Mar 31 12:25:11 PM PDT 24
Peak memory 191540 kb
Host smart-4a526ee4-d3b2-4671-9645-9303ba33c6ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184971326 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.2184971326
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.2127720171
Short name T118
Test name
Test status
Simulation time 601346725 ps
CPU time 0.79 seconds
Started Mar 31 12:25:00 PM PDT 24
Finished Mar 31 12:25:01 PM PDT 24
Peak memory 183256 kb
Host smart-5382ffff-f12c-436c-b93d-a07b66bd869d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127720171 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.2127720171
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.2488624363
Short name T88
Test name
Test status
Simulation time 90757450455 ps
CPU time 9.87 seconds
Started Mar 31 12:24:39 PM PDT 24
Finished Mar 31 12:24:50 PM PDT 24
Peak memory 193580 kb
Host smart-05e962ff-98aa-44ec-9760-5dee11992cbd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488624363 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_a
ll.2488624363
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.3594913921
Short name T32
Test name
Test status
Simulation time 167457069989 ps
CPU time 639.54 seconds
Started Mar 31 12:24:53 PM PDT 24
Finished Mar 31 12:35:33 PM PDT 24
Peak memory 207748 kb
Host smart-7b031589-74f1-46f8-8b89-f969e6417d01
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594913921 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.3594913921
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.aon_timer_jump.3530049130
Short name T239
Test name
Test status
Simulation time 431442195 ps
CPU time 0.71 seconds
Started Mar 31 12:24:43 PM PDT 24
Finished Mar 31 12:24:44 PM PDT 24
Peak memory 183292 kb
Host smart-ad19000a-041a-4817-8091-ba4dcf6223db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530049130 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.3530049130
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.2756324710
Short name T140
Test name
Test status
Simulation time 8516955095 ps
CPU time 6.1 seconds
Started Mar 31 12:24:50 PM PDT 24
Finished Mar 31 12:24:56 PM PDT 24
Peak memory 183348 kb
Host smart-d9a55ac5-d5bb-494d-bc55-b75ee75d405a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756324710 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.2756324710
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.366176122
Short name T236
Test name
Test status
Simulation time 487336148 ps
CPU time 0.7 seconds
Started Mar 31 12:24:54 PM PDT 24
Finished Mar 31 12:24:55 PM PDT 24
Peak memory 183316 kb
Host smart-14c97902-b0a0-46d7-acf0-07a2812ce0b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366176122 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.366176122
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.1974044371
Short name T173
Test name
Test status
Simulation time 232031646715 ps
CPU time 193.25 seconds
Started Mar 31 12:24:54 PM PDT 24
Finished Mar 31 12:28:07 PM PDT 24
Peak memory 183360 kb
Host smart-b3139923-4bb6-41b6-86a8-c5e2076f22ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974044371 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_a
ll.1974044371
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.3053815286
Short name T170
Test name
Test status
Simulation time 34110421051 ps
CPU time 279.37 seconds
Started Mar 31 12:24:47 PM PDT 24
Finished Mar 31 12:29:27 PM PDT 24
Peak memory 198180 kb
Host smart-776b6d1c-ccde-47d5-bce5-032ad602ee29
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053815286 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.3053815286
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.aon_timer_jump.3930560451
Short name T192
Test name
Test status
Simulation time 593361351 ps
CPU time 0.78 seconds
Started Mar 31 12:24:59 PM PDT 24
Finished Mar 31 12:25:00 PM PDT 24
Peak memory 183300 kb
Host smart-8ef9baa8-2ee5-4f1b-b06b-f09e7487238f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930560451 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.3930560451
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.1560406930
Short name T163
Test name
Test status
Simulation time 43260381033 ps
CPU time 17.53 seconds
Started Mar 31 12:24:49 PM PDT 24
Finished Mar 31 12:25:06 PM PDT 24
Peak memory 183340 kb
Host smart-4b6d5b1d-21e3-49be-9440-87937014b185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560406930 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.1560406930
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.2406827443
Short name T14
Test name
Test status
Simulation time 492288261 ps
CPU time 0.72 seconds
Started Mar 31 12:24:43 PM PDT 24
Finished Mar 31 12:24:44 PM PDT 24
Peak memory 183296 kb
Host smart-cf07b3df-f835-41c3-b9b8-99771537e250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406827443 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.2406827443
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.370021735
Short name T84
Test name
Test status
Simulation time 125739410564 ps
CPU time 96.59 seconds
Started Mar 31 12:24:57 PM PDT 24
Finished Mar 31 12:26:34 PM PDT 24
Peak memory 193076 kb
Host smart-ec0d8635-c994-4b6c-b265-fe8edb2a698a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370021735 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_al
l.370021735
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_jump.1196031559
Short name T178
Test name
Test status
Simulation time 371396273 ps
CPU time 0.79 seconds
Started Mar 31 12:24:49 PM PDT 24
Finished Mar 31 12:24:50 PM PDT 24
Peak memory 183656 kb
Host smart-adbb7a77-58da-4cb1-9b2a-26343f9dcf08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196031559 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.1196031559
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.3680827344
Short name T113
Test name
Test status
Simulation time 29117940180 ps
CPU time 11.15 seconds
Started Mar 31 12:24:50 PM PDT 24
Finished Mar 31 12:25:01 PM PDT 24
Peak memory 183340 kb
Host smart-c92b3cf2-da79-4e68-9e40-d781f85d012c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680827344 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.3680827344
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.1971608608
Short name T185
Test name
Test status
Simulation time 362730879 ps
CPU time 0.66 seconds
Started Mar 31 12:24:46 PM PDT 24
Finished Mar 31 12:24:47 PM PDT 24
Peak memory 183276 kb
Host smart-a6107a02-4a35-4ca0-b477-eaa42b5a6764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971608608 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.1971608608
Directory /workspace/9.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.2376908769
Short name T29
Test name
Test status
Simulation time 365484057598 ps
CPU time 100.78 seconds
Started Mar 31 12:25:10 PM PDT 24
Finished Mar 31 12:26:56 PM PDT 24
Peak memory 193872 kb
Host smart-e2545171-b96f-4276-92ae-f21bc636db73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376908769 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_a
ll.2376908769
Directory /workspace/9.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.2927618726
Short name T47
Test name
Test status
Simulation time 94039643643 ps
CPU time 368.88 seconds
Started Mar 31 12:25:08 PM PDT 24
Finished Mar 31 12:31:17 PM PDT 24
Peak memory 198240 kb
Host smart-fd0a5f06-7492-4835-b5c7-ab4668ee83b0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927618726 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.2927618726
Directory /workspace/9.aon_timer_stress_all_with_rand_reset/latest
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