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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
93.02 99.25 93.67 100.00 98.40 99.51 67.30


Total test records in report: 417
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html
T277 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.1087804052 Apr 02 12:22:21 PM PDT 24 Apr 02 12:22:22 PM PDT 24 294829453 ps
T278 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.2014253583 Apr 02 12:22:14 PM PDT 24 Apr 02 12:22:15 PM PDT 24 484307142 ps
T279 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.1429686279 Apr 02 12:22:42 PM PDT 24 Apr 02 12:22:43 PM PDT 24 539801218 ps
T280 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.548954794 Apr 02 12:22:35 PM PDT 24 Apr 02 12:22:37 PM PDT 24 532369932 ps
T281 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.423908097 Apr 02 12:22:15 PM PDT 24 Apr 02 12:22:16 PM PDT 24 375876106 ps
T55 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.4272040778 Apr 02 12:22:34 PM PDT 24 Apr 02 12:22:35 PM PDT 24 391173763 ps
T44 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.1919140094 Apr 02 12:22:38 PM PDT 24 Apr 02 12:22:39 PM PDT 24 339670682 ps
T56 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.294630004 Apr 02 12:20:56 PM PDT 24 Apr 02 12:20:57 PM PDT 24 484023425 ps
T282 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.954641600 Apr 02 12:20:45 PM PDT 24 Apr 02 12:20:46 PM PDT 24 271480284 ps
T34 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.2543515198 Apr 02 12:23:59 PM PDT 24 Apr 02 12:24:07 PM PDT 24 8259002527 ps
T283 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.2637432560 Apr 02 12:20:53 PM PDT 24 Apr 02 12:20:54 PM PDT 24 453461297 ps
T45 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.3684443950 Apr 02 12:19:59 PM PDT 24 Apr 02 12:20:00 PM PDT 24 365877717 ps
T35 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.1852144752 Apr 02 12:22:21 PM PDT 24 Apr 02 12:22:27 PM PDT 24 4143942904 ps
T284 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.1199231824 Apr 02 12:20:56 PM PDT 24 Apr 02 12:20:57 PM PDT 24 512584196 ps
T77 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.2235928637 Apr 02 12:20:00 PM PDT 24 Apr 02 12:20:06 PM PDT 24 8488630740 ps
T78 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.759851014 Apr 02 12:22:26 PM PDT 24 Apr 02 12:22:39 PM PDT 24 8163518482 ps
T285 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.659261083 Apr 02 12:23:36 PM PDT 24 Apr 02 12:23:37 PM PDT 24 295289040 ps
T286 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.2452104666 Apr 02 12:22:31 PM PDT 24 Apr 02 12:22:32 PM PDT 24 406046891 ps
T287 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.3319073267 Apr 02 12:19:59 PM PDT 24 Apr 02 12:20:02 PM PDT 24 4676543414 ps
T92 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.3821577627 Apr 02 12:20:30 PM PDT 24 Apr 02 12:20:34 PM PDT 24 8571266937 ps
T288 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.2211421118 Apr 02 12:22:30 PM PDT 24 Apr 02 12:22:32 PM PDT 24 316795589 ps
T289 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.1824847524 Apr 02 12:23:35 PM PDT 24 Apr 02 12:23:38 PM PDT 24 552380503 ps
T57 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.3255761000 Apr 02 12:22:20 PM PDT 24 Apr 02 12:22:22 PM PDT 24 2171409873 ps
T58 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.3033603053 Apr 02 12:22:49 PM PDT 24 Apr 02 12:22:53 PM PDT 24 2277375172 ps
T93 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.714156878 Apr 02 12:23:44 PM PDT 24 Apr 02 12:23:47 PM PDT 24 4498988450 ps
T59 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.1136395300 Apr 02 12:22:48 PM PDT 24 Apr 02 12:22:50 PM PDT 24 358297742 ps
T290 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.3730407334 Apr 02 12:21:03 PM PDT 24 Apr 02 12:21:05 PM PDT 24 300813257 ps
T291 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.1623081472 Apr 02 12:23:01 PM PDT 24 Apr 02 12:23:03 PM PDT 24 372348928 ps
T292 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.23719136 Apr 02 12:22:25 PM PDT 24 Apr 02 12:22:27 PM PDT 24 459988141 ps
T293 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.3913503294 Apr 02 12:22:21 PM PDT 24 Apr 02 12:22:24 PM PDT 24 429016147 ps
T294 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.2556720951 Apr 02 12:19:43 PM PDT 24 Apr 02 12:19:45 PM PDT 24 484516224 ps
T295 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.3182902084 Apr 02 12:21:05 PM PDT 24 Apr 02 12:21:06 PM PDT 24 533918691 ps
T296 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.4249963023 Apr 02 12:19:13 PM PDT 24 Apr 02 12:19:14 PM PDT 24 427076513 ps
T94 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.3850896718 Apr 02 12:22:20 PM PDT 24 Apr 02 12:22:28 PM PDT 24 8729545461 ps
T297 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.3230805433 Apr 02 12:19:17 PM PDT 24 Apr 02 12:19:19 PM PDT 24 599550129 ps
T298 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.3283232465 Apr 02 12:22:18 PM PDT 24 Apr 02 12:22:20 PM PDT 24 444639749 ps
T299 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.3586708598 Apr 02 12:22:20 PM PDT 24 Apr 02 12:22:23 PM PDT 24 655206222 ps
T300 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.3009539036 Apr 02 12:23:36 PM PDT 24 Apr 02 12:23:37 PM PDT 24 366895823 ps
T301 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.2408007160 Apr 02 12:22:48 PM PDT 24 Apr 02 12:22:51 PM PDT 24 443723556 ps
T60 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.4100888775 Apr 02 12:20:01 PM PDT 24 Apr 02 12:20:02 PM PDT 24 973684969 ps
T302 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.3154502186 Apr 02 12:20:13 PM PDT 24 Apr 02 12:20:14 PM PDT 24 357949205 ps
T303 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.1171279165 Apr 02 12:22:20 PM PDT 24 Apr 02 12:22:21 PM PDT 24 406546177 ps
T61 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.2700579563 Apr 02 12:22:25 PM PDT 24 Apr 02 12:22:27 PM PDT 24 1061172585 ps
T304 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.2121697713 Apr 02 12:22:26 PM PDT 24 Apr 02 12:22:28 PM PDT 24 562367283 ps
T305 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.2000959703 Apr 02 12:22:19 PM PDT 24 Apr 02 12:22:20 PM PDT 24 1223131166 ps
T46 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.961969770 Apr 02 12:22:49 PM PDT 24 Apr 02 12:22:52 PM PDT 24 651991471 ps
T306 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.1706543794 Apr 02 12:20:58 PM PDT 24 Apr 02 12:20:59 PM PDT 24 2018788999 ps
T307 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.3282760486 Apr 02 12:22:27 PM PDT 24 Apr 02 12:22:29 PM PDT 24 376503561 ps
T308 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.2476438295 Apr 02 12:22:13 PM PDT 24 Apr 02 12:22:15 PM PDT 24 414352367 ps
T309 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.1282876114 Apr 02 12:20:01 PM PDT 24 Apr 02 12:20:03 PM PDT 24 512524420 ps
T310 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.176274177 Apr 02 12:22:14 PM PDT 24 Apr 02 12:22:29 PM PDT 24 8154147594 ps
T311 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.2772242022 Apr 02 12:19:58 PM PDT 24 Apr 02 12:19:59 PM PDT 24 1572983548 ps
T47 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.3299553928 Apr 02 12:19:15 PM PDT 24 Apr 02 12:19:16 PM PDT 24 462128124 ps
T312 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.1149606492 Apr 02 12:22:24 PM PDT 24 Apr 02 12:22:26 PM PDT 24 435686864 ps
T48 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.1975246301 Apr 02 12:22:28 PM PDT 24 Apr 02 12:22:29 PM PDT 24 523060036 ps
T313 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.934206909 Apr 02 12:19:49 PM PDT 24 Apr 02 12:19:51 PM PDT 24 1342000298 ps
T314 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.3578384577 Apr 02 12:22:16 PM PDT 24 Apr 02 12:22:18 PM PDT 24 522413940 ps
T315 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.2020131719 Apr 02 12:23:41 PM PDT 24 Apr 02 12:23:44 PM PDT 24 433432752 ps
T316 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.623923608 Apr 02 12:22:33 PM PDT 24 Apr 02 12:22:34 PM PDT 24 472252085 ps
T317 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.19674652 Apr 02 12:22:19 PM PDT 24 Apr 02 12:22:21 PM PDT 24 401270612 ps
T318 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.1163630542 Apr 02 12:22:48 PM PDT 24 Apr 02 12:22:59 PM PDT 24 8599729013 ps
T319 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.1324087978 Apr 02 12:22:25 PM PDT 24 Apr 02 12:22:30 PM PDT 24 8440044620 ps
T49 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.1268161871 Apr 02 12:22:33 PM PDT 24 Apr 02 12:22:35 PM PDT 24 680134325 ps
T320 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.641483501 Apr 02 12:20:35 PM PDT 24 Apr 02 12:20:36 PM PDT 24 483815144 ps
T321 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.2144290779 Apr 02 12:22:15 PM PDT 24 Apr 02 12:22:18 PM PDT 24 3165041596 ps
T322 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.1228342174 Apr 02 12:22:27 PM PDT 24 Apr 02 12:22:31 PM PDT 24 7563108224 ps
T323 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.916683123 Apr 02 12:22:20 PM PDT 24 Apr 02 12:22:21 PM PDT 24 452235701 ps
T50 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.2930737664 Apr 02 12:20:22 PM PDT 24 Apr 02 12:20:23 PM PDT 24 394699651 ps
T324 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.3447838864 Apr 02 12:22:16 PM PDT 24 Apr 02 12:22:18 PM PDT 24 336373566 ps
T325 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.281169427 Apr 02 12:19:58 PM PDT 24 Apr 02 12:20:13 PM PDT 24 8950908834 ps
T51 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.2581229319 Apr 02 12:22:16 PM PDT 24 Apr 02 12:22:18 PM PDT 24 300149758 ps
T52 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.635903516 Apr 02 12:22:20 PM PDT 24 Apr 02 12:22:40 PM PDT 24 9833711262 ps
T326 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.2532808335 Apr 02 12:20:12 PM PDT 24 Apr 02 12:20:14 PM PDT 24 480052420 ps
T327 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.3228725832 Apr 02 12:22:21 PM PDT 24 Apr 02 12:22:22 PM PDT 24 423581667 ps
T328 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.480868375 Apr 02 12:20:20 PM PDT 24 Apr 02 12:20:22 PM PDT 24 732394424 ps
T329 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.216866115 Apr 02 12:21:10 PM PDT 24 Apr 02 12:21:13 PM PDT 24 533652447 ps
T330 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.3115818197 Apr 02 12:19:59 PM PDT 24 Apr 02 12:20:00 PM PDT 24 468750412 ps
T95 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.4039520328 Apr 02 12:22:20 PM PDT 24 Apr 02 12:22:33 PM PDT 24 8087433791 ps
T331 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.73354590 Apr 02 12:22:48 PM PDT 24 Apr 02 12:22:51 PM PDT 24 633212456 ps
T332 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.3412474975 Apr 02 12:22:15 PM PDT 24 Apr 02 12:22:17 PM PDT 24 523666600 ps
T333 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.1986522468 Apr 02 12:19:43 PM PDT 24 Apr 02 12:19:44 PM PDT 24 344020175 ps
T334 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.2223816455 Apr 02 12:20:26 PM PDT 24 Apr 02 12:20:27 PM PDT 24 558967816 ps
T335 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.1651413042 Apr 02 12:22:41 PM PDT 24 Apr 02 12:22:43 PM PDT 24 447535420 ps
T336 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.3177972899 Apr 02 12:22:44 PM PDT 24 Apr 02 12:22:48 PM PDT 24 1581671523 ps
T337 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.1802648176 Apr 02 12:22:17 PM PDT 24 Apr 02 12:22:19 PM PDT 24 564956701 ps
T338 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.408986577 Apr 02 12:23:35 PM PDT 24 Apr 02 12:23:37 PM PDT 24 787239230 ps
T339 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.112006181 Apr 02 12:22:20 PM PDT 24 Apr 02 12:22:22 PM PDT 24 532059235 ps
T340 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.3677180028 Apr 02 12:22:20 PM PDT 24 Apr 02 12:22:22 PM PDT 24 474394844 ps
T341 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.1945561700 Apr 02 12:22:38 PM PDT 24 Apr 02 12:22:39 PM PDT 24 298656268 ps
T342 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.1359307418 Apr 02 12:22:26 PM PDT 24 Apr 02 12:22:32 PM PDT 24 2499619067 ps
T343 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.3296123821 Apr 02 12:22:31 PM PDT 24 Apr 02 12:22:32 PM PDT 24 654012163 ps
T344 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.3368670001 Apr 02 12:22:33 PM PDT 24 Apr 02 12:22:36 PM PDT 24 461584529 ps
T345 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.2266974791 Apr 02 12:20:48 PM PDT 24 Apr 02 12:20:49 PM PDT 24 355578372 ps
T346 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.3928091503 Apr 02 12:19:50 PM PDT 24 Apr 02 12:19:52 PM PDT 24 1415450397 ps
T347 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.1751229603 Apr 02 12:18:44 PM PDT 24 Apr 02 12:18:44 PM PDT 24 328916514 ps
T348 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.2694920080 Apr 02 12:20:26 PM PDT 24 Apr 02 12:20:27 PM PDT 24 439184901 ps
T349 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.3977470651 Apr 02 12:22:31 PM PDT 24 Apr 02 12:22:32 PM PDT 24 475424255 ps
T350 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.2329688100 Apr 02 12:22:42 PM PDT 24 Apr 02 12:22:43 PM PDT 24 522292935 ps
T351 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.502714899 Apr 02 12:23:39 PM PDT 24 Apr 02 12:23:41 PM PDT 24 433325603 ps
T352 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.3627355183 Apr 02 12:19:59 PM PDT 24 Apr 02 12:20:02 PM PDT 24 1696452308 ps
T353 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.2434824787 Apr 02 12:23:29 PM PDT 24 Apr 02 12:23:30 PM PDT 24 338347858 ps
T354 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.1959197530 Apr 02 12:23:44 PM PDT 24 Apr 02 12:23:44 PM PDT 24 463449349 ps
T355 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.462912419 Apr 02 12:24:03 PM PDT 24 Apr 02 12:24:08 PM PDT 24 7540399805 ps
T356 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.1739223664 Apr 02 12:19:18 PM PDT 24 Apr 02 12:19:20 PM PDT 24 4458979153 ps
T357 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.432199416 Apr 02 12:22:59 PM PDT 24 Apr 02 12:23:00 PM PDT 24 403872867 ps
T358 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.3369551760 Apr 02 12:22:14 PM PDT 24 Apr 02 12:22:16 PM PDT 24 332394331 ps
T359 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.2749920980 Apr 02 12:18:43 PM PDT 24 Apr 02 12:18:46 PM PDT 24 2485722079 ps
T360 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.3710573443 Apr 02 12:22:33 PM PDT 24 Apr 02 12:22:34 PM PDT 24 347484762 ps
T361 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.1791115268 Apr 02 12:22:15 PM PDT 24 Apr 02 12:22:16 PM PDT 24 339131933 ps
T362 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.184453413 Apr 02 12:20:43 PM PDT 24 Apr 02 12:20:44 PM PDT 24 321780536 ps
T363 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.4132223707 Apr 02 12:22:34 PM PDT 24 Apr 02 12:22:35 PM PDT 24 293175252 ps
T364 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.1597256436 Apr 02 12:19:10 PM PDT 24 Apr 02 12:19:12 PM PDT 24 1530993038 ps
T365 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.3128434556 Apr 02 12:19:21 PM PDT 24 Apr 02 12:19:23 PM PDT 24 364438339 ps
T366 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.2782921214 Apr 02 12:22:48 PM PDT 24 Apr 02 12:22:51 PM PDT 24 320424924 ps
T367 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.3836347347 Apr 02 12:22:33 PM PDT 24 Apr 02 12:22:34 PM PDT 24 442774725 ps
T368 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.2322549119 Apr 02 12:22:26 PM PDT 24 Apr 02 12:22:27 PM PDT 24 347639731 ps
T369 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.3110414565 Apr 02 12:20:10 PM PDT 24 Apr 02 12:20:11 PM PDT 24 311702627 ps
T370 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.1061077004 Apr 02 12:22:15 PM PDT 24 Apr 02 12:22:16 PM PDT 24 535413924 ps
T371 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.1018668064 Apr 02 12:23:29 PM PDT 24 Apr 02 12:23:31 PM PDT 24 394413279 ps
T53 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.501029496 Apr 02 12:22:34 PM PDT 24 Apr 02 12:22:35 PM PDT 24 801278176 ps
T372 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.2178398619 Apr 02 12:22:20 PM PDT 24 Apr 02 12:22:22 PM PDT 24 336454330 ps
T373 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.868355768 Apr 02 12:22:24 PM PDT 24 Apr 02 12:22:26 PM PDT 24 335516287 ps
T374 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.1312773708 Apr 02 12:19:57 PM PDT 24 Apr 02 12:19:58 PM PDT 24 280202298 ps
T375 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.1415844284 Apr 02 12:19:57 PM PDT 24 Apr 02 12:19:59 PM PDT 24 321650989 ps
T376 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.3418079838 Apr 02 12:20:08 PM PDT 24 Apr 02 12:20:11 PM PDT 24 1287436369 ps
T377 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.3011035697 Apr 02 12:19:11 PM PDT 24 Apr 02 12:19:13 PM PDT 24 1845190221 ps
T378 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.722841571 Apr 02 12:19:28 PM PDT 24 Apr 02 12:19:29 PM PDT 24 605352851 ps
T379 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.1799949341 Apr 02 12:20:09 PM PDT 24 Apr 02 12:20:10 PM PDT 24 532330759 ps
T380 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.3421868298 Apr 02 12:23:44 PM PDT 24 Apr 02 12:23:47 PM PDT 24 4134436446 ps
T381 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.2968432050 Apr 02 12:22:34 PM PDT 24 Apr 02 12:22:35 PM PDT 24 368736200 ps
T382 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.2981572943 Apr 02 12:22:14 PM PDT 24 Apr 02 12:22:16 PM PDT 24 467545472 ps
T383 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.3037856879 Apr 02 12:22:59 PM PDT 24 Apr 02 12:23:01 PM PDT 24 444438202 ps
T384 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.2528841508 Apr 02 12:22:51 PM PDT 24 Apr 02 12:22:52 PM PDT 24 406394239 ps
T385 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.2667210247 Apr 02 12:22:42 PM PDT 24 Apr 02 12:22:45 PM PDT 24 312710956 ps
T386 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.1572239334 Apr 02 12:22:41 PM PDT 24 Apr 02 12:22:43 PM PDT 24 489580781 ps
T387 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.3130562540 Apr 02 12:22:48 PM PDT 24 Apr 02 12:22:51 PM PDT 24 528609954 ps
T388 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.267491274 Apr 02 12:22:30 PM PDT 24 Apr 02 12:22:31 PM PDT 24 394044264 ps
T389 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.2613363484 Apr 02 12:19:17 PM PDT 24 Apr 02 12:19:18 PM PDT 24 510395486 ps
T390 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.1222923857 Apr 02 12:22:20 PM PDT 24 Apr 02 12:22:21 PM PDT 24 390874751 ps
T391 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.1413458400 Apr 02 12:22:33 PM PDT 24 Apr 02 12:22:34 PM PDT 24 374831261 ps
T392 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.3336830203 Apr 02 12:20:08 PM PDT 24 Apr 02 12:20:10 PM PDT 24 457804947 ps
T393 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.93855803 Apr 02 12:21:24 PM PDT 24 Apr 02 12:21:24 PM PDT 24 378661720 ps
T394 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.2393495019 Apr 02 12:20:08 PM PDT 24 Apr 02 12:20:10 PM PDT 24 1290696117 ps
T395 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.1887112495 Apr 02 12:22:14 PM PDT 24 Apr 02 12:22:18 PM PDT 24 1129314544 ps
T396 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.3297232753 Apr 02 12:19:58 PM PDT 24 Apr 02 12:19:59 PM PDT 24 491858334 ps
T54 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.927147325 Apr 02 12:22:23 PM PDT 24 Apr 02 12:22:41 PM PDT 24 10327640052 ps
T397 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.722424250 Apr 02 12:22:20 PM PDT 24 Apr 02 12:22:22 PM PDT 24 414863006 ps
T398 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.1639001553 Apr 02 12:22:26 PM PDT 24 Apr 02 12:22:28 PM PDT 24 445888371 ps
T399 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.951081032 Apr 02 12:22:18 PM PDT 24 Apr 02 12:22:21 PM PDT 24 415598483 ps
T400 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.2476488145 Apr 02 12:22:34 PM PDT 24 Apr 02 12:22:35 PM PDT 24 1119268269 ps
T401 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.3832909784 Apr 02 12:22:19 PM PDT 24 Apr 02 12:22:27 PM PDT 24 8211116695 ps
T402 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.3153051155 Apr 02 12:22:48 PM PDT 24 Apr 02 12:22:56 PM PDT 24 3910882334 ps
T403 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.2946629485 Apr 02 12:19:18 PM PDT 24 Apr 02 12:19:20 PM PDT 24 701126432 ps
T404 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.472615760 Apr 02 12:22:49 PM PDT 24 Apr 02 12:22:51 PM PDT 24 339711932 ps
T405 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.3562569571 Apr 02 12:22:19 PM PDT 24 Apr 02 12:22:20 PM PDT 24 376071126 ps
T406 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.2958275528 Apr 02 12:19:18 PM PDT 24 Apr 02 12:19:22 PM PDT 24 7847169384 ps
T407 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.737165303 Apr 02 12:23:33 PM PDT 24 Apr 02 12:23:36 PM PDT 24 4246751803 ps
T408 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.3559155396 Apr 02 12:20:42 PM PDT 24 Apr 02 12:20:44 PM PDT 24 441419079 ps
T409 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.1563349417 Apr 02 12:22:34 PM PDT 24 Apr 02 12:22:35 PM PDT 24 461805936 ps
T410 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.2955100970 Apr 02 12:22:20 PM PDT 24 Apr 02 12:22:22 PM PDT 24 375343423 ps
T411 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.448533393 Apr 02 12:22:21 PM PDT 24 Apr 02 12:22:23 PM PDT 24 399686745 ps
T412 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.3355759086 Apr 02 12:23:33 PM PDT 24 Apr 02 12:23:34 PM PDT 24 289295534 ps
T413 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.859645847 Apr 02 12:22:31 PM PDT 24 Apr 02 12:22:33 PM PDT 24 392916578 ps
T414 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.4150535287 Apr 02 12:22:15 PM PDT 24 Apr 02 12:22:17 PM PDT 24 576414596 ps
T415 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.1482036875 Apr 02 12:22:38 PM PDT 24 Apr 02 12:22:40 PM PDT 24 428438428 ps
T416 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.3085375376 Apr 02 12:19:16 PM PDT 24 Apr 02 12:19:17 PM PDT 24 561634777 ps
T417 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.391425723 Apr 02 12:22:20 PM PDT 24 Apr 02 12:22:23 PM PDT 24 1283162907 ps

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.473650208
Short name T6
Test name
Test status
Simulation time 435489285704 ps
CPU time 490.09 seconds
Started Apr 02 12:24:18 PM PDT 24
Finished Apr 02 12:32:29 PM PDT 24
Peak memory 198384 kb
Host smart-f50dfde8-314a-4d2e-9891-f6812a001f94
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473650208 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.473650208
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.587568324
Short name T29
Test name
Test status
Simulation time 42646206008 ps
CPU time 88.77 seconds
Started Apr 02 12:24:17 PM PDT 24
Finished Apr 02 12:25:46 PM PDT 24
Peak memory 198224 kb
Host smart-b3dde6bc-d6af-4761-878d-bf0a71e3a35b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587568324 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.587568324
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.3981433480
Short name T31
Test name
Test status
Simulation time 7870021978 ps
CPU time 13.09 seconds
Started Apr 02 12:22:28 PM PDT 24
Finished Apr 02 12:22:41 PM PDT 24
Peak memory 197836 kb
Host smart-74cf7a1a-2ba6-4b78-9d27-b87571a5e8f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981433480 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl
_intg_err.3981433480
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.2422675161
Short name T62
Test name
Test status
Simulation time 416224641291 ps
CPU time 674.31 seconds
Started Apr 02 12:24:21 PM PDT 24
Finished Apr 02 12:35:35 PM PDT 24
Peak memory 201188 kb
Host smart-b3725891-6726-4936-9465-95905f626ce7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422675161 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.2422675161
Directory /workspace/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.2078082374
Short name T16
Test name
Test status
Simulation time 317622695407 ps
CPU time 245.32 seconds
Started Apr 02 12:24:08 PM PDT 24
Finished Apr 02 12:28:13 PM PDT 24
Peak memory 183316 kb
Host smart-c9e5a20d-f568-4cc7-b6ec-763696921ebc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078082374 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_a
ll.2078082374
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.1268161871
Short name T49
Test name
Test status
Simulation time 680134325 ps
CPU time 1.71 seconds
Started Apr 02 12:22:33 PM PDT 24
Finished Apr 02 12:22:35 PM PDT 24
Peak memory 193852 kb
Host smart-7996bfcf-c456-4dfd-9f9f-504389ffc46c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268161871 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_a
liasing.1268161871
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.2746234870
Short name T14
Test name
Test status
Simulation time 7579967236 ps
CPU time 7.08 seconds
Started Apr 02 12:24:17 PM PDT 24
Finished Apr 02 12:24:24 PM PDT 24
Peak memory 215052 kb
Host smart-27e55387-087e-4da0-9d1e-eda68bdb5e62
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746234870 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.2746234870
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.4039520328
Short name T95
Test name
Test status
Simulation time 8087433791 ps
CPU time 12.1 seconds
Started Apr 02 12:22:20 PM PDT 24
Finished Apr 02 12:22:33 PM PDT 24
Peak memory 196428 kb
Host smart-c943746c-dd83-45bc-8f93-18d0c68e792a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039520328 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_t
l_intg_err.4039520328
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.1136395300
Short name T59
Test name
Test status
Simulation time 358297742 ps
CPU time 0.68 seconds
Started Apr 02 12:22:48 PM PDT 24
Finished Apr 02 12:22:50 PM PDT 24
Peak memory 183800 kb
Host smart-bcd3d90c-fadd-48c5-8661-0bd131692667
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136395300 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.1136395300
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.1271905017
Short name T4
Test name
Test status
Simulation time 31118016819 ps
CPU time 3.77 seconds
Started Apr 02 12:24:16 PM PDT 24
Finished Apr 02 12:24:20 PM PDT 24
Peak memory 183304 kb
Host smart-162250f5-8dc9-4d19-a877-20cacd8312cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271905017 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.1271905017
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.3666054544
Short name T88
Test name
Test status
Simulation time 87089652428 ps
CPU time 35.12 seconds
Started Apr 02 12:24:08 PM PDT 24
Finished Apr 02 12:24:43 PM PDT 24
Peak memory 183424 kb
Host smart-04864210-1fce-4b13-be9e-d189b5711305
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666054544 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_
all.3666054544
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.961969770
Short name T46
Test name
Test status
Simulation time 651991471 ps
CPU time 2.22 seconds
Started Apr 02 12:22:49 PM PDT 24
Finished Apr 02 12:22:52 PM PDT 24
Peak memory 192020 kb
Host smart-1db0667b-13bb-495e-a34b-abe7986c7879
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961969770 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_bi
t_bash.961969770
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.2000959703
Short name T305
Test name
Test status
Simulation time 1223131166 ps
CPU time 0.69 seconds
Started Apr 02 12:22:19 PM PDT 24
Finished Apr 02 12:22:20 PM PDT 24
Peak memory 183172 kb
Host smart-b251191e-0878-4a4c-9410-04533de495c7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000959703 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_h
w_reset.2000959703
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.3336830203
Short name T392
Test name
Test status
Simulation time 457804947 ps
CPU time 1.47 seconds
Started Apr 02 12:20:08 PM PDT 24
Finished Apr 02 12:20:10 PM PDT 24
Peak memory 194872 kb
Host smart-8a5139b8-83f1-4360-af0b-742311aa3cc2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336830203 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.3336830203
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.3355759086
Short name T412
Test name
Test status
Simulation time 289295534 ps
CPU time 0.92 seconds
Started Apr 02 12:23:33 PM PDT 24
Finished Apr 02 12:23:34 PM PDT 24
Peak memory 183516 kb
Host smart-3ef7f7d7-06f2-42c2-97d1-11ae2e3b65dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355759086 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.3355759086
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.659261083
Short name T285
Test name
Test status
Simulation time 295289040 ps
CPU time 0.79 seconds
Started Apr 02 12:23:36 PM PDT 24
Finished Apr 02 12:23:37 PM PDT 24
Peak memory 183168 kb
Host smart-10bab407-1b4a-46ac-9e4a-b00fe9c77af1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659261083 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_ti
mer_mem_partial_access.659261083
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.3562569571
Short name T405
Test name
Test status
Simulation time 376071126 ps
CPU time 0.56 seconds
Started Apr 02 12:22:19 PM PDT 24
Finished Apr 02 12:22:20 PM PDT 24
Peak memory 182984 kb
Host smart-9290d870-7636-48ff-9980-890f9d83c57f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562569571 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_w
alk.3562569571
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.3418079838
Short name T376
Test name
Test status
Simulation time 1287436369 ps
CPU time 2.35 seconds
Started Apr 02 12:20:08 PM PDT 24
Finished Apr 02 12:20:11 PM PDT 24
Peak memory 182704 kb
Host smart-47f66fb9-254f-4cb9-b872-85e833e8b512
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418079838 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon
_timer_same_csr_outstanding.3418079838
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.19674652
Short name T317
Test name
Test status
Simulation time 401270612 ps
CPU time 1.28 seconds
Started Apr 02 12:22:19 PM PDT 24
Finished Apr 02 12:22:21 PM PDT 24
Peak memory 198168 kb
Host smart-57a46bc6-6d15-49b8-849a-e9df07fb7160
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19674652 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.19674652
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.737165303
Short name T407
Test name
Test status
Simulation time 4246751803 ps
CPU time 2.4 seconds
Started Apr 02 12:23:33 PM PDT 24
Finished Apr 02 12:23:36 PM PDT 24
Peak memory 197392 kb
Host smart-eedda61c-c1b2-4ca5-84a5-d84b08413e60
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737165303 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_
intg_err.737165303
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.3677180028
Short name T340
Test name
Test status
Simulation time 474394844 ps
CPU time 1.14 seconds
Started Apr 02 12:22:20 PM PDT 24
Finished Apr 02 12:22:22 PM PDT 24
Peak memory 181388 kb
Host smart-e9f236e1-02e0-48df-a62a-ea725cbc560a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677180028 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_a
liasing.3677180028
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.1228342174
Short name T322
Test name
Test status
Simulation time 7563108224 ps
CPU time 3.85 seconds
Started Apr 02 12:22:27 PM PDT 24
Finished Apr 02 12:22:31 PM PDT 24
Peak memory 192216 kb
Host smart-17c88d15-5af9-4483-8f4e-f1507c253484
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228342174 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_b
it_bash.1228342174
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.408986577
Short name T338
Test name
Test status
Simulation time 787239230 ps
CPU time 0.67 seconds
Started Apr 02 12:23:35 PM PDT 24
Finished Apr 02 12:23:37 PM PDT 24
Peak memory 182360 kb
Host smart-d8c8851e-91d7-41db-924c-20084b27ff47
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408986577 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_hw
_reset.408986577
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.3369551760
Short name T358
Test name
Test status
Simulation time 332394331 ps
CPU time 0.95 seconds
Started Apr 02 12:22:14 PM PDT 24
Finished Apr 02 12:22:16 PM PDT 24
Peak memory 193336 kb
Host smart-f03a361a-061e-47d0-b36e-55fd8365040c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369551760 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.3369551760
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.210195508
Short name T76
Test name
Test status
Simulation time 317847638 ps
CPU time 0.96 seconds
Started Apr 02 12:22:21 PM PDT 24
Finished Apr 02 12:22:22 PM PDT 24
Peak memory 183408 kb
Host smart-7195377e-d4ed-4b2a-bb0b-0405ea13a70b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210195508 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.210195508
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.2178398619
Short name T372
Test name
Test status
Simulation time 336454330 ps
CPU time 1 seconds
Started Apr 02 12:22:20 PM PDT 24
Finished Apr 02 12:22:22 PM PDT 24
Peak memory 183340 kb
Host smart-38372426-bead-4b7e-8a5c-ad92233ff512
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178398619 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.2178398619
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.1751229603
Short name T347
Test name
Test status
Simulation time 328916514 ps
CPU time 0.55 seconds
Started Apr 02 12:18:44 PM PDT 24
Finished Apr 02 12:18:44 PM PDT 24
Peak memory 183844 kb
Host smart-7e3ffdd2-78f2-4e27-9dba-2fc41d24fde7
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751229603 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_t
imer_mem_partial_access.1751229603
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.502714899
Short name T351
Test name
Test status
Simulation time 433325603 ps
CPU time 0.77 seconds
Started Apr 02 12:23:39 PM PDT 24
Finished Apr 02 12:23:41 PM PDT 24
Peak memory 182652 kb
Host smart-f2e05afa-1d49-4a61-80c9-f9c9829dd320
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502714899 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_wa
lk.502714899
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.3033603053
Short name T58
Test name
Test status
Simulation time 2277375172 ps
CPU time 3.03 seconds
Started Apr 02 12:22:49 PM PDT 24
Finished Apr 02 12:22:53 PM PDT 24
Peak memory 183780 kb
Host smart-2c3e65fd-7e2e-40ae-92d4-f6e13c9850fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033603053 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon
_timer_same_csr_outstanding.3033603053
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.1824847524
Short name T289
Test name
Test status
Simulation time 552380503 ps
CPU time 1.72 seconds
Started Apr 02 12:23:35 PM PDT 24
Finished Apr 02 12:23:38 PM PDT 24
Peak memory 197312 kb
Host smart-d5915e4c-51f9-425b-841d-b61a5f5d6de7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824847524 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.1824847524
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.722841571
Short name T378
Test name
Test status
Simulation time 605352851 ps
CPU time 0.95 seconds
Started Apr 02 12:19:28 PM PDT 24
Finished Apr 02 12:19:29 PM PDT 24
Peak memory 197292 kb
Host smart-61ea1514-1148-41c4-922a-f8c6a4be2043
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722841571 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.722841571
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.3299553928
Short name T47
Test name
Test status
Simulation time 462128124 ps
CPU time 0.7 seconds
Started Apr 02 12:19:15 PM PDT 24
Finished Apr 02 12:19:16 PM PDT 24
Peak memory 183712 kb
Host smart-8b550556-4fd7-4849-95ee-c2bc051f81da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299553928 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.3299553928
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.1018668064
Short name T371
Test name
Test status
Simulation time 394413279 ps
CPU time 0.57 seconds
Started Apr 02 12:23:29 PM PDT 24
Finished Apr 02 12:23:31 PM PDT 24
Peak memory 183220 kb
Host smart-c5689b68-8182-4457-a15c-50f28674903c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018668064 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.1018668064
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.2700579563
Short name T61
Test name
Test status
Simulation time 1061172585 ps
CPU time 1.46 seconds
Started Apr 02 12:22:25 PM PDT 24
Finished Apr 02 12:22:27 PM PDT 24
Peak memory 182636 kb
Host smart-2ccea58b-b9c1-45fd-98eb-86cd6ce5795b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700579563 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.ao
n_timer_same_csr_outstanding.2700579563
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.1639001553
Short name T398
Test name
Test status
Simulation time 445888371 ps
CPU time 1.82 seconds
Started Apr 02 12:22:26 PM PDT 24
Finished Apr 02 12:22:28 PM PDT 24
Peak memory 198064 kb
Host smart-4d263cb9-4989-45d1-ab1c-6ceada279373
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639001553 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.1639001553
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.714156878
Short name T93
Test name
Test status
Simulation time 4498988450 ps
CPU time 3.18 seconds
Started Apr 02 12:23:44 PM PDT 24
Finished Apr 02 12:23:47 PM PDT 24
Peak memory 197668 kb
Host smart-6170d665-7fbb-4c09-81d0-69602f447643
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714156878 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl
_intg_err.714156878
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.1986522468
Short name T333
Test name
Test status
Simulation time 344020175 ps
CPU time 0.81 seconds
Started Apr 02 12:19:43 PM PDT 24
Finished Apr 02 12:19:44 PM PDT 24
Peak memory 195816 kb
Host smart-a225e6a1-3283-4eed-9552-8404cfc0368f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986522468 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.1986522468
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.3578384577
Short name T314
Test name
Test status
Simulation time 522413940 ps
CPU time 0.89 seconds
Started Apr 02 12:22:16 PM PDT 24
Finished Apr 02 12:22:18 PM PDT 24
Peak memory 191856 kb
Host smart-2bd8ba8c-40fd-4eb7-8ec7-ea76b7b57069
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578384577 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.3578384577
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.2955100970
Short name T410
Test name
Test status
Simulation time 375343423 ps
CPU time 1.17 seconds
Started Apr 02 12:22:20 PM PDT 24
Finished Apr 02 12:22:22 PM PDT 24
Peak memory 182108 kb
Host smart-460541bc-aa55-4a4d-b100-7855628962c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955100970 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.2955100970
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.934206909
Short name T313
Test name
Test status
Simulation time 1342000298 ps
CPU time 1.5 seconds
Started Apr 02 12:19:49 PM PDT 24
Finished Apr 02 12:19:51 PM PDT 24
Peak memory 183832 kb
Host smart-9df3ac34-a9e5-4322-ab1b-ae5430e90740
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934206909 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon
_timer_same_csr_outstanding.934206909
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.3586708598
Short name T299
Test name
Test status
Simulation time 655206222 ps
CPU time 2.43 seconds
Started Apr 02 12:22:20 PM PDT 24
Finished Apr 02 12:22:23 PM PDT 24
Peak memory 197496 kb
Host smart-c788e229-2554-4985-a39c-b39b1062d35d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586708598 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.3586708598
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.3821577627
Short name T92
Test name
Test status
Simulation time 8571266937 ps
CPU time 4.19 seconds
Started Apr 02 12:20:30 PM PDT 24
Finished Apr 02 12:20:34 PM PDT 24
Peak memory 197892 kb
Host smart-ae48cccd-8056-4324-b8ef-6755a6be13ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821577627 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_t
l_intg_err.3821577627
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.3412474975
Short name T332
Test name
Test status
Simulation time 523666600 ps
CPU time 1.33 seconds
Started Apr 02 12:22:15 PM PDT 24
Finished Apr 02 12:22:17 PM PDT 24
Peak memory 195868 kb
Host smart-c82d9a89-7063-416e-b1c5-f35ac631256f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412474975 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.3412474975
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.859645847
Short name T413
Test name
Test status
Simulation time 392916578 ps
CPU time 0.72 seconds
Started Apr 02 12:22:31 PM PDT 24
Finished Apr 02 12:22:33 PM PDT 24
Peak memory 182980 kb
Host smart-f42f8cfa-8e8f-413a-9b88-b1a6d0e17012
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859645847 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.859645847
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.423908097
Short name T281
Test name
Test status
Simulation time 375876106 ps
CPU time 0.7 seconds
Started Apr 02 12:22:15 PM PDT 24
Finished Apr 02 12:22:16 PM PDT 24
Peak memory 181976 kb
Host smart-74be4b11-e78a-477b-8587-6cde522c5380
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423908097 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.423908097
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.1706543794
Short name T306
Test name
Test status
Simulation time 2018788999 ps
CPU time 1.12 seconds
Started Apr 02 12:20:58 PM PDT 24
Finished Apr 02 12:20:59 PM PDT 24
Peak memory 194172 kb
Host smart-3d247e08-363d-4e31-9208-df2264dcfb77
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706543794 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.ao
n_timer_same_csr_outstanding.1706543794
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.2556720951
Short name T294
Test name
Test status
Simulation time 484516224 ps
CPU time 2.11 seconds
Started Apr 02 12:19:43 PM PDT 24
Finished Apr 02 12:19:45 PM PDT 24
Peak memory 198364 kb
Host smart-dcb445db-127f-4774-94fe-7b354ee24638
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556720951 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.2556720951
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.3832909784
Short name T401
Test name
Test status
Simulation time 8211116695 ps
CPU time 6.88 seconds
Started Apr 02 12:22:19 PM PDT 24
Finished Apr 02 12:22:27 PM PDT 24
Peak memory 197496 kb
Host smart-531c7636-2395-4cd0-9311-ee694aceca5c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832909784 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_t
l_intg_err.3832909784
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.1482036875
Short name T415
Test name
Test status
Simulation time 428438428 ps
CPU time 1.32 seconds
Started Apr 02 12:22:38 PM PDT 24
Finished Apr 02 12:22:40 PM PDT 24
Peak memory 194636 kb
Host smart-9babb76b-17ec-40b0-9890-b56c5fbcaba3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482036875 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.1482036875
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.2322549119
Short name T368
Test name
Test status
Simulation time 347639731 ps
CPU time 0.67 seconds
Started Apr 02 12:22:26 PM PDT 24
Finished Apr 02 12:22:27 PM PDT 24
Peak memory 183652 kb
Host smart-6df8f151-c9c1-410a-929a-d01dace8f499
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322549119 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.2322549119
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.3559155396
Short name T408
Test name
Test status
Simulation time 441419079 ps
CPU time 1.29 seconds
Started Apr 02 12:20:42 PM PDT 24
Finished Apr 02 12:20:44 PM PDT 24
Peak memory 183632 kb
Host smart-874dac8d-e4c8-4e10-8a1d-ea0bab153429
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559155396 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.3559155396
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.3928091503
Short name T346
Test name
Test status
Simulation time 1415450397 ps
CPU time 1.8 seconds
Started Apr 02 12:19:50 PM PDT 24
Finished Apr 02 12:19:52 PM PDT 24
Peak memory 193120 kb
Host smart-1866a121-2f59-4a31-bcbe-55b9e32a9b63
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928091503 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.ao
n_timer_same_csr_outstanding.3928091503
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.480868375
Short name T328
Test name
Test status
Simulation time 732394424 ps
CPU time 1.73 seconds
Started Apr 02 12:20:20 PM PDT 24
Finished Apr 02 12:20:22 PM PDT 24
Peak memory 198452 kb
Host smart-35599fbc-1a9f-42fc-a8a4-1a1ce7a75995
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480868375 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.480868375
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.3130562540
Short name T387
Test name
Test status
Simulation time 528609954 ps
CPU time 1.31 seconds
Started Apr 02 12:22:48 PM PDT 24
Finished Apr 02 12:22:51 PM PDT 24
Peak memory 195812 kb
Host smart-9d6cbd4e-7485-4b72-b949-f79bcbef5e06
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130562540 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.3130562540
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.916683123
Short name T323
Test name
Test status
Simulation time 452235701 ps
CPU time 0.78 seconds
Started Apr 02 12:22:20 PM PDT 24
Finished Apr 02 12:22:21 PM PDT 24
Peak memory 191556 kb
Host smart-c99a250c-05b8-41d9-8cf3-33086502f1ff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916683123 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.916683123
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.3228725832
Short name T327
Test name
Test status
Simulation time 423581667 ps
CPU time 0.85 seconds
Started Apr 02 12:22:21 PM PDT 24
Finished Apr 02 12:22:22 PM PDT 24
Peak memory 183324 kb
Host smart-26425f2b-0f0f-4057-a285-b285ffbdd57f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228725832 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.3228725832
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.3627355183
Short name T352
Test name
Test status
Simulation time 1696452308 ps
CPU time 3.03 seconds
Started Apr 02 12:19:59 PM PDT 24
Finished Apr 02 12:20:02 PM PDT 24
Peak memory 183764 kb
Host smart-71d400c6-dd77-4c14-9c44-8cf175d801f6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627355183 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao
n_timer_same_csr_outstanding.3627355183
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.112006181
Short name T339
Test name
Test status
Simulation time 532059235 ps
CPU time 1.34 seconds
Started Apr 02 12:22:20 PM PDT 24
Finished Apr 02 12:22:22 PM PDT 24
Peak memory 196828 kb
Host smart-cd98ffae-8a14-43f5-ac22-f4c613546393
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112006181 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.112006181
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.1324087978
Short name T319
Test name
Test status
Simulation time 8440044620 ps
CPU time 4.01 seconds
Started Apr 02 12:22:25 PM PDT 24
Finished Apr 02 12:22:30 PM PDT 24
Peak memory 197080 kb
Host smart-f6f16830-846d-421f-be10-64df2737023e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324087978 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_t
l_intg_err.1324087978
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.3115818197
Short name T330
Test name
Test status
Simulation time 468750412 ps
CPU time 0.99 seconds
Started Apr 02 12:19:59 PM PDT 24
Finished Apr 02 12:20:00 PM PDT 24
Peak memory 197336 kb
Host smart-0a4b5185-7a6f-476b-b117-ae607191d622
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115818197 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.3115818197
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.1415844284
Short name T375
Test name
Test status
Simulation time 321650989 ps
CPU time 1.09 seconds
Started Apr 02 12:19:57 PM PDT 24
Finished Apr 02 12:19:59 PM PDT 24
Peak memory 183972 kb
Host smart-49847677-9d5e-450e-a4bb-ddc9c3b77dde
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415844284 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.1415844284
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.1312773708
Short name T374
Test name
Test status
Simulation time 280202298 ps
CPU time 0.99 seconds
Started Apr 02 12:19:57 PM PDT 24
Finished Apr 02 12:19:58 PM PDT 24
Peak memory 183544 kb
Host smart-1348e097-c5c3-4a93-ac3a-a7e0ef8a1e7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312773708 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.1312773708
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.657283123
Short name T32
Test name
Test status
Simulation time 1023182303 ps
CPU time 1.07 seconds
Started Apr 02 12:22:20 PM PDT 24
Finished Apr 02 12:22:22 PM PDT 24
Peak memory 183436 kb
Host smart-ad775aee-7589-4b6b-9ce3-abb89962bf8f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657283123 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon
_timer_same_csr_outstanding.657283123
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.1623081472
Short name T291
Test name
Test status
Simulation time 372348928 ps
CPU time 1.49 seconds
Started Apr 02 12:23:01 PM PDT 24
Finished Apr 02 12:23:03 PM PDT 24
Peak memory 198448 kb
Host smart-06f99b6e-9ec8-4695-8862-b4b554d72fb4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623081472 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.1623081472
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.281169427
Short name T325
Test name
Test status
Simulation time 8950908834 ps
CPU time 15.08 seconds
Started Apr 02 12:19:58 PM PDT 24
Finished Apr 02 12:20:13 PM PDT 24
Peak memory 198028 kb
Host smart-2fe97731-1f90-410f-b191-4ab64399330e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281169427 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl
_intg_err.281169427
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.1199231824
Short name T284
Test name
Test status
Simulation time 512584196 ps
CPU time 1.39 seconds
Started Apr 02 12:20:56 PM PDT 24
Finished Apr 02 12:20:57 PM PDT 24
Peak memory 195644 kb
Host smart-489835a5-27e6-4173-916e-3edca70fe255
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199231824 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.1199231824
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.2782921214
Short name T366
Test name
Test status
Simulation time 320424924 ps
CPU time 0.73 seconds
Started Apr 02 12:22:48 PM PDT 24
Finished Apr 02 12:22:51 PM PDT 24
Peak memory 182932 kb
Host smart-b08c8c03-23a5-4c6a-bdc9-e06dd9b2117e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782921214 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.2782921214
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.2408007160
Short name T301
Test name
Test status
Simulation time 443723556 ps
CPU time 1.18 seconds
Started Apr 02 12:22:48 PM PDT 24
Finished Apr 02 12:22:51 PM PDT 24
Peak memory 182336 kb
Host smart-4a451651-8109-48d0-b8c0-f71c739cd32b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408007160 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.2408007160
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.2772242022
Short name T311
Test name
Test status
Simulation time 1572983548 ps
CPU time 1.53 seconds
Started Apr 02 12:19:58 PM PDT 24
Finished Apr 02 12:19:59 PM PDT 24
Peak memory 183804 kb
Host smart-54c51a8c-6348-451c-9883-f447f639711a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772242022 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.ao
n_timer_same_csr_outstanding.2772242022
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.3297232753
Short name T396
Test name
Test status
Simulation time 491858334 ps
CPU time 1.33 seconds
Started Apr 02 12:19:58 PM PDT 24
Finished Apr 02 12:19:59 PM PDT 24
Peak memory 198544 kb
Host smart-5f577088-e94c-4569-a565-4d06384fe119
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297232753 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.3297232753
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.2235928637
Short name T77
Test name
Test status
Simulation time 8488630740 ps
CPU time 6.07 seconds
Started Apr 02 12:20:00 PM PDT 24
Finished Apr 02 12:20:06 PM PDT 24
Peak memory 197848 kb
Host smart-d795c1cd-607a-49e4-8ea5-6624a6b89658
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235928637 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_t
l_intg_err.2235928637
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.1282876114
Short name T309
Test name
Test status
Simulation time 512524420 ps
CPU time 1.56 seconds
Started Apr 02 12:20:01 PM PDT 24
Finished Apr 02 12:20:03 PM PDT 24
Peak memory 195636 kb
Host smart-17c5faa3-95e1-4276-9a1e-3f18ea970a05
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282876114 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.1282876114
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.3154502186
Short name T302
Test name
Test status
Simulation time 357949205 ps
CPU time 1.08 seconds
Started Apr 02 12:20:13 PM PDT 24
Finished Apr 02 12:20:14 PM PDT 24
Peak memory 183980 kb
Host smart-82dbfcd8-fef5-4ccc-8d70-680900637542
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154502186 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.3154502186
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.1799949341
Short name T379
Test name
Test status
Simulation time 532330759 ps
CPU time 0.73 seconds
Started Apr 02 12:20:09 PM PDT 24
Finished Apr 02 12:20:10 PM PDT 24
Peak memory 183632 kb
Host smart-772b64fa-1b5c-4007-83e9-5f146c4b9431
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799949341 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.1799949341
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.4100888775
Short name T60
Test name
Test status
Simulation time 973684969 ps
CPU time 1.11 seconds
Started Apr 02 12:20:01 PM PDT 24
Finished Apr 02 12:20:02 PM PDT 24
Peak memory 193204 kb
Host smart-5069985d-a311-4ec7-bbd9-3301849508d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100888775 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.ao
n_timer_same_csr_outstanding.4100888775
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.3110414565
Short name T369
Test name
Test status
Simulation time 311702627 ps
CPU time 1.63 seconds
Started Apr 02 12:20:10 PM PDT 24
Finished Apr 02 12:20:11 PM PDT 24
Peak memory 198336 kb
Host smart-ec576d46-0631-4238-b3fe-db8ecb32af62
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110414565 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.3110414565
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.3319073267
Short name T287
Test name
Test status
Simulation time 4676543414 ps
CPU time 2.31 seconds
Started Apr 02 12:19:59 PM PDT 24
Finished Apr 02 12:20:02 PM PDT 24
Peak memory 196728 kb
Host smart-649408c3-ecb8-46f3-b2f8-382bd70ff809
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319073267 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_t
l_intg_err.3319073267
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.2121697713
Short name T304
Test name
Test status
Simulation time 562367283 ps
CPU time 0.83 seconds
Started Apr 02 12:22:26 PM PDT 24
Finished Apr 02 12:22:28 PM PDT 24
Peak memory 195248 kb
Host smart-bd5001c2-110e-4a96-a05e-b6c59f59ac37
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121697713 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.2121697713
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.267491274
Short name T388
Test name
Test status
Simulation time 394044264 ps
CPU time 0.74 seconds
Started Apr 02 12:22:30 PM PDT 24
Finished Apr 02 12:22:31 PM PDT 24
Peak memory 192788 kb
Host smart-9bf5804b-a69d-464b-a901-472d49f1a2cf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267491274 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.267491274
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.2223816455
Short name T334
Test name
Test status
Simulation time 558967816 ps
CPU time 0.59 seconds
Started Apr 02 12:20:26 PM PDT 24
Finished Apr 02 12:20:27 PM PDT 24
Peak memory 183628 kb
Host smart-3df0da48-9540-43f1-91a3-fc817dcece89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223816455 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.2223816455
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.3177972899
Short name T336
Test name
Test status
Simulation time 1581671523 ps
CPU time 3.77 seconds
Started Apr 02 12:22:44 PM PDT 24
Finished Apr 02 12:22:48 PM PDT 24
Peak memory 193164 kb
Host smart-ea764846-0c8f-4e22-910b-2a48651170e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177972899 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.ao
n_timer_same_csr_outstanding.3177972899
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.2532808335
Short name T326
Test name
Test status
Simulation time 480052420 ps
CPU time 1.75 seconds
Started Apr 02 12:20:12 PM PDT 24
Finished Apr 02 12:20:14 PM PDT 24
Peak memory 198540 kb
Host smart-eac2b4cd-d05e-40c3-bff5-ae9398a6e507
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532808335 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.2532808335
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.1163630542
Short name T318
Test name
Test status
Simulation time 8599729013 ps
CPU time 8.73 seconds
Started Apr 02 12:22:48 PM PDT 24
Finished Apr 02 12:22:59 PM PDT 24
Peak memory 197732 kb
Host smart-151c2b61-2ff3-4718-9b8c-eb6c6f63d6e1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163630542 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_t
l_intg_err.1163630542
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.4150535287
Short name T414
Test name
Test status
Simulation time 576414596 ps
CPU time 1.53 seconds
Started Apr 02 12:22:15 PM PDT 24
Finished Apr 02 12:22:17 PM PDT 24
Peak memory 194744 kb
Host smart-59290f47-a05e-48c0-9242-cf3682841ff6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150535287 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.4150535287
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.2581229319
Short name T51
Test name
Test status
Simulation time 300149758 ps
CPU time 0.99 seconds
Started Apr 02 12:22:16 PM PDT 24
Finished Apr 02 12:22:18 PM PDT 24
Peak memory 183364 kb
Host smart-9b905990-4e0e-4ed5-bb4a-12e28fb2d688
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581229319 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.2581229319
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.3447838864
Short name T324
Test name
Test status
Simulation time 336373566 ps
CPU time 1 seconds
Started Apr 02 12:22:16 PM PDT 24
Finished Apr 02 12:22:18 PM PDT 24
Peak memory 182912 kb
Host smart-a437ee9f-f0f4-4e50-a6a1-6e63744b8119
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447838864 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.3447838864
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.2144290779
Short name T321
Test name
Test status
Simulation time 3165041596 ps
CPU time 2.76 seconds
Started Apr 02 12:22:15 PM PDT 24
Finished Apr 02 12:22:18 PM PDT 24
Peak memory 193076 kb
Host smart-9674a964-963c-43de-97b7-382a85b6564e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144290779 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao
n_timer_same_csr_outstanding.2144290779
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.3730407334
Short name T290
Test name
Test status
Simulation time 300813257 ps
CPU time 1.79 seconds
Started Apr 02 12:21:03 PM PDT 24
Finished Apr 02 12:21:05 PM PDT 24
Peak memory 198436 kb
Host smart-9f1fcbf1-5f1d-4f35-ba9f-accf1b69d30f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730407334 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.3730407334
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.759851014
Short name T78
Test name
Test status
Simulation time 8163518482 ps
CPU time 11.88 seconds
Started Apr 02 12:22:26 PM PDT 24
Finished Apr 02 12:22:39 PM PDT 24
Peak memory 196844 kb
Host smart-87500fef-c607-4d4d-99e3-ca3d98384811
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759851014 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl
_intg_err.759851014
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.501029496
Short name T53
Test name
Test status
Simulation time 801278176 ps
CPU time 0.8 seconds
Started Apr 02 12:22:34 PM PDT 24
Finished Apr 02 12:22:35 PM PDT 24
Peak memory 193676 kb
Host smart-a5a2a339-daab-44ab-8ca4-8e4a1e243cc2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501029496 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_al
iasing.501029496
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.462912419
Short name T355
Test name
Test status
Simulation time 7540399805 ps
CPU time 5.23 seconds
Started Apr 02 12:24:03 PM PDT 24
Finished Apr 02 12:24:08 PM PDT 24
Peak memory 183916 kb
Host smart-04a89df3-279a-4f14-a53d-82b703c4ab9b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462912419 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_bi
t_bash.462912419
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.2393495019
Short name T394
Test name
Test status
Simulation time 1290696117 ps
CPU time 1.47 seconds
Started Apr 02 12:20:08 PM PDT 24
Finished Apr 02 12:20:10 PM PDT 24
Peak memory 182880 kb
Host smart-bd2282ab-709d-4666-b9ea-eaf46aa522fc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393495019 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_h
w_reset.2393495019
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.472615760
Short name T404
Test name
Test status
Simulation time 339711932 ps
CPU time 1.12 seconds
Started Apr 02 12:22:49 PM PDT 24
Finished Apr 02 12:22:51 PM PDT 24
Peak memory 195800 kb
Host smart-ee06315d-8bf5-4daa-bb54-c217222a7adb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472615760 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.472615760
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.3182902084
Short name T295
Test name
Test status
Simulation time 533918691 ps
CPU time 0.79 seconds
Started Apr 02 12:21:05 PM PDT 24
Finished Apr 02 12:21:06 PM PDT 24
Peak memory 183720 kb
Host smart-25ba534e-da5d-4e80-9298-58ba1476afdf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182902084 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.3182902084
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.216866115
Short name T329
Test name
Test status
Simulation time 533652447 ps
CPU time 0.74 seconds
Started Apr 02 12:21:10 PM PDT 24
Finished Apr 02 12:21:13 PM PDT 24
Peak memory 183636 kb
Host smart-f7f987fd-56cc-4887-b25a-78f835e0bcf9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216866115 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.216866115
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.2211421118
Short name T288
Test name
Test status
Simulation time 316795589 ps
CPU time 0.66 seconds
Started Apr 02 12:22:30 PM PDT 24
Finished Apr 02 12:22:32 PM PDT 24
Peak memory 182632 kb
Host smart-ece5bc9b-d843-4fa8-b75c-fc7dbf1fb542
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211421118 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_t
imer_mem_partial_access.2211421118
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.3009539036
Short name T300
Test name
Test status
Simulation time 366895823 ps
CPU time 0.63 seconds
Started Apr 02 12:23:36 PM PDT 24
Finished Apr 02 12:23:37 PM PDT 24
Peak memory 182888 kb
Host smart-6e3d229b-cdb5-423b-9526-83e99d34618e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009539036 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_w
alk.3009539036
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.2154374036
Short name T30
Test name
Test status
Simulation time 1088310120 ps
CPU time 1.06 seconds
Started Apr 02 12:22:20 PM PDT 24
Finished Apr 02 12:22:22 PM PDT 24
Peak memory 183772 kb
Host smart-9e05bb37-7b8b-4704-86eb-f04f5e2ffe5b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154374036 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon
_timer_same_csr_outstanding.2154374036
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.3282760486
Short name T307
Test name
Test status
Simulation time 376503561 ps
CPU time 1.49 seconds
Started Apr 02 12:22:27 PM PDT 24
Finished Apr 02 12:22:29 PM PDT 24
Peak memory 198280 kb
Host smart-031b1eaf-01c9-4e9d-a0f4-f0e4d6d25560
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282760486 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.3282760486
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.2543515198
Short name T34
Test name
Test status
Simulation time 8259002527 ps
CPU time 7.86 seconds
Started Apr 02 12:23:59 PM PDT 24
Finished Apr 02 12:24:07 PM PDT 24
Peak memory 197816 kb
Host smart-35c18678-0609-4a94-87a7-324be8286749
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543515198 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl
_intg_err.2543515198
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.1791115268
Short name T361
Test name
Test status
Simulation time 339131933 ps
CPU time 0.6 seconds
Started Apr 02 12:22:15 PM PDT 24
Finished Apr 02 12:22:16 PM PDT 24
Peak memory 183160 kb
Host smart-7ce5fcc5-a930-46ae-b156-69300a24bc87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791115268 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.1791115268
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.2694920080
Short name T348
Test name
Test status
Simulation time 439184901 ps
CPU time 0.72 seconds
Started Apr 02 12:20:26 PM PDT 24
Finished Apr 02 12:20:27 PM PDT 24
Peak memory 183620 kb
Host smart-257dc794-104f-4a40-8f72-e17d69de48fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694920080 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.2694920080
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.1563349417
Short name T409
Test name
Test status
Simulation time 461805936 ps
CPU time 0.7 seconds
Started Apr 02 12:22:34 PM PDT 24
Finished Apr 02 12:22:35 PM PDT 24
Peak memory 183468 kb
Host smart-1c5ebc7d-c99a-479c-b66e-4a471044a0f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563349417 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.1563349417
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.641483501
Short name T320
Test name
Test status
Simulation time 483815144 ps
CPU time 0.74 seconds
Started Apr 02 12:20:35 PM PDT 24
Finished Apr 02 12:20:36 PM PDT 24
Peak memory 183656 kb
Host smart-836d0d22-80ef-40d7-8b5e-87447f2188f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641483501 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.641483501
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.2452104666
Short name T286
Test name
Test status
Simulation time 406046891 ps
CPU time 0.68 seconds
Started Apr 02 12:22:31 PM PDT 24
Finished Apr 02 12:22:32 PM PDT 24
Peak memory 183432 kb
Host smart-2964f974-316b-4caf-9c25-b40cb766700e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452104666 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.2452104666
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.1222923857
Short name T390
Test name
Test status
Simulation time 390874751 ps
CPU time 0.67 seconds
Started Apr 02 12:22:20 PM PDT 24
Finished Apr 02 12:22:21 PM PDT 24
Peak memory 183224 kb
Host smart-b48c6711-6810-4d1e-81b4-4b48cbd81062
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222923857 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.1222923857
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.2968432050
Short name T381
Test name
Test status
Simulation time 368736200 ps
CPU time 0.97 seconds
Started Apr 02 12:22:34 PM PDT 24
Finished Apr 02 12:22:35 PM PDT 24
Peak memory 183468 kb
Host smart-f2680b96-bd13-4859-9a29-7cb50ff64e93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968432050 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.2968432050
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.1572239334
Short name T386
Test name
Test status
Simulation time 489580781 ps
CPU time 0.66 seconds
Started Apr 02 12:22:41 PM PDT 24
Finished Apr 02 12:22:43 PM PDT 24
Peak memory 183408 kb
Host smart-15cb8eda-0a4f-4540-a666-8a3b641da224
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572239334 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.1572239334
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.1429686279
Short name T279
Test name
Test status
Simulation time 539801218 ps
CPU time 0.67 seconds
Started Apr 02 12:22:42 PM PDT 24
Finished Apr 02 12:22:43 PM PDT 24
Peak memory 183404 kb
Host smart-510be79b-509d-4ab7-a234-152efb22fb4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429686279 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.1429686279
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.2014253583
Short name T278
Test name
Test status
Simulation time 484307142 ps
CPU time 0.66 seconds
Started Apr 02 12:22:14 PM PDT 24
Finished Apr 02 12:22:15 PM PDT 24
Peak memory 182680 kb
Host smart-317fe520-c5fa-42fe-84b3-4750d3132817
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014253583 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.2014253583
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.3684443950
Short name T45
Test name
Test status
Simulation time 365877717 ps
CPU time 0.82 seconds
Started Apr 02 12:19:59 PM PDT 24
Finished Apr 02 12:20:00 PM PDT 24
Peak memory 183708 kb
Host smart-02526c01-8a09-4237-ad21-af16970639cd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684443950 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_a
liasing.3684443950
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.927147325
Short name T54
Test name
Test status
Simulation time 10327640052 ps
CPU time 17.11 seconds
Started Apr 02 12:22:23 PM PDT 24
Finished Apr 02 12:22:41 PM PDT 24
Peak memory 192688 kb
Host smart-6da1e393-f697-49ed-ae16-6fbe0927e2bf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927147325 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_bi
t_bash.927147325
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.2476488145
Short name T400
Test name
Test status
Simulation time 1119268269 ps
CPU time 1.51 seconds
Started Apr 02 12:22:34 PM PDT 24
Finished Apr 02 12:22:35 PM PDT 24
Peak memory 192856 kb
Host smart-7d45a575-cfd0-4223-a7a6-d03f5531ba31
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476488145 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_h
w_reset.2476488145
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.3710573443
Short name T360
Test name
Test status
Simulation time 347484762 ps
CPU time 0.7 seconds
Started Apr 02 12:22:33 PM PDT 24
Finished Apr 02 12:22:34 PM PDT 24
Peak memory 194460 kb
Host smart-d30fc5db-8a48-41ec-a9d9-5cc9150ff473
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710573443 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.3710573443
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.4272040778
Short name T55
Test name
Test status
Simulation time 391173763 ps
CPU time 0.6 seconds
Started Apr 02 12:22:34 PM PDT 24
Finished Apr 02 12:22:35 PM PDT 24
Peak memory 183616 kb
Host smart-a2750e73-4ec2-4f71-8afe-8b3798d6bca4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272040778 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.4272040778
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.3836347347
Short name T367
Test name
Test status
Simulation time 442774725 ps
CPU time 0.64 seconds
Started Apr 02 12:22:33 PM PDT 24
Finished Apr 02 12:22:34 PM PDT 24
Peak memory 183216 kb
Host smart-38454358-476f-495e-81b6-174b3630dcb1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836347347 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.3836347347
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.722424250
Short name T397
Test name
Test status
Simulation time 414863006 ps
CPU time 1.04 seconds
Started Apr 02 12:22:20 PM PDT 24
Finished Apr 02 12:22:22 PM PDT 24
Peak memory 181784 kb
Host smart-63e459f3-d4f5-4618-b902-468a52d67e8a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722424250 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_ti
mer_mem_partial_access.722424250
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.4132223707
Short name T363
Test name
Test status
Simulation time 293175252 ps
CPU time 0.93 seconds
Started Apr 02 12:22:34 PM PDT 24
Finished Apr 02 12:22:35 PM PDT 24
Peak memory 183264 kb
Host smart-c57de48e-ed32-42ee-bc79-0af5fa92676d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132223707 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_w
alk.4132223707
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.3255761000
Short name T57
Test name
Test status
Simulation time 2171409873 ps
CPU time 1.56 seconds
Started Apr 02 12:22:20 PM PDT 24
Finished Apr 02 12:22:22 PM PDT 24
Peak memory 192468 kb
Host smart-333cb9dd-8ccd-42d0-92a4-9c01c4ddeb5b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255761000 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon
_timer_same_csr_outstanding.3255761000
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.2915971865
Short name T276
Test name
Test status
Simulation time 496812063 ps
CPU time 1.97 seconds
Started Apr 02 12:22:21 PM PDT 24
Finished Apr 02 12:22:23 PM PDT 24
Peak memory 198092 kb
Host smart-fa967970-f2de-4178-ad19-5953118df7df
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915971865 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.2915971865
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.3850896718
Short name T94
Test name
Test status
Simulation time 8729545461 ps
CPU time 7.22 seconds
Started Apr 02 12:22:20 PM PDT 24
Finished Apr 02 12:22:28 PM PDT 24
Peak memory 195736 kb
Host smart-96a6f3e7-153b-484e-a8fe-3fce78254034
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850896718 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl
_intg_err.3850896718
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.1802648176
Short name T337
Test name
Test status
Simulation time 564956701 ps
CPU time 0.62 seconds
Started Apr 02 12:22:17 PM PDT 24
Finished Apr 02 12:22:19 PM PDT 24
Peak memory 182720 kb
Host smart-92c8a34f-af98-4bcf-a63f-21746d415685
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802648176 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.1802648176
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.3977470651
Short name T349
Test name
Test status
Simulation time 475424255 ps
CPU time 1.21 seconds
Started Apr 02 12:22:31 PM PDT 24
Finished Apr 02 12:22:32 PM PDT 24
Peak memory 182904 kb
Host smart-8edc2564-430e-4789-a8f0-fb1595984e5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977470651 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.3977470651
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.2266974791
Short name T345
Test name
Test status
Simulation time 355578372 ps
CPU time 0.77 seconds
Started Apr 02 12:20:48 PM PDT 24
Finished Apr 02 12:20:49 PM PDT 24
Peak memory 183548 kb
Host smart-3ba1010d-5865-40ea-b439-062085fc4db2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266974791 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.2266974791
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.3296123821
Short name T343
Test name
Test status
Simulation time 654012163 ps
CPU time 0.57 seconds
Started Apr 02 12:22:31 PM PDT 24
Finished Apr 02 12:22:32 PM PDT 24
Peak memory 182992 kb
Host smart-29220250-24be-45d8-b4b4-b21984617dde
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296123821 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.3296123821
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.548954794
Short name T280
Test name
Test status
Simulation time 532369932 ps
CPU time 0.71 seconds
Started Apr 02 12:22:35 PM PDT 24
Finished Apr 02 12:22:37 PM PDT 24
Peak memory 182628 kb
Host smart-d5d5716a-b742-489e-84ee-be85ebe87585
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548954794 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.548954794
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.2528841508
Short name T384
Test name
Test status
Simulation time 406394239 ps
CPU time 1.07 seconds
Started Apr 02 12:22:51 PM PDT 24
Finished Apr 02 12:22:52 PM PDT 24
Peak memory 183444 kb
Host smart-e41a23f0-5b48-4939-acb5-65277c9e63ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528841508 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.2528841508
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.324213925
Short name T275
Test name
Test status
Simulation time 363655143 ps
CPU time 1 seconds
Started Apr 02 12:23:41 PM PDT 24
Finished Apr 02 12:23:48 PM PDT 24
Peak memory 183300 kb
Host smart-9df2746d-a9e7-4119-8796-6858ed212fa5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324213925 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.324213925
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.2476438295
Short name T308
Test name
Test status
Simulation time 414352367 ps
CPU time 1.3 seconds
Started Apr 02 12:22:13 PM PDT 24
Finished Apr 02 12:22:15 PM PDT 24
Peak memory 183484 kb
Host smart-f89fd721-7efe-4044-875c-0b4da05b0ce1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476438295 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.2476438295
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.2020131719
Short name T315
Test name
Test status
Simulation time 433432752 ps
CPU time 1.2 seconds
Started Apr 02 12:23:41 PM PDT 24
Finished Apr 02 12:23:44 PM PDT 24
Peak memory 183200 kb
Host smart-cfca341c-a885-4556-a1e3-46d4dfbb4bc9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020131719 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.2020131719
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.3283232465
Short name T298
Test name
Test status
Simulation time 444639749 ps
CPU time 0.64 seconds
Started Apr 02 12:22:18 PM PDT 24
Finished Apr 02 12:22:20 PM PDT 24
Peak memory 182212 kb
Host smart-fd33b089-588f-4303-9e15-19a9318d759a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283232465 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.3283232465
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.1975246301
Short name T48
Test name
Test status
Simulation time 523060036 ps
CPU time 0.95 seconds
Started Apr 02 12:22:28 PM PDT 24
Finished Apr 02 12:22:29 PM PDT 24
Peak memory 182804 kb
Host smart-0c3395ce-e5f5-404f-9d83-779103f06a7b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975246301 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_a
liasing.1975246301
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.635903516
Short name T52
Test name
Test status
Simulation time 9833711262 ps
CPU time 19.12 seconds
Started Apr 02 12:22:20 PM PDT 24
Finished Apr 02 12:22:40 PM PDT 24
Peak memory 190456 kb
Host smart-ad81bc3f-6169-4314-bebb-209cbe5f9db8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635903516 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_bi
t_bash.635903516
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.391425723
Short name T417
Test name
Test status
Simulation time 1283162907 ps
CPU time 2.27 seconds
Started Apr 02 12:22:20 PM PDT 24
Finished Apr 02 12:22:23 PM PDT 24
Peak memory 182220 kb
Host smart-87e7ff86-ea1c-415b-a6ff-e9714ccb8a77
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391425723 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_hw
_reset.391425723
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.23719136
Short name T292
Test name
Test status
Simulation time 459988141 ps
CPU time 0.98 seconds
Started Apr 02 12:22:25 PM PDT 24
Finished Apr 02 12:22:27 PM PDT 24
Peak memory 194308 kb
Host smart-ab590b57-e3f5-4c98-9600-6a2f6b1cbc90
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23719136 -assert nopostproc +UVM_TESTNAME=a
on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.23719136
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.1413458400
Short name T391
Test name
Test status
Simulation time 374831261 ps
CPU time 1.11 seconds
Started Apr 02 12:22:33 PM PDT 24
Finished Apr 02 12:22:34 PM PDT 24
Peak memory 183580 kb
Host smart-ffad4fbe-e66f-4724-b40a-b59194597526
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413458400 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.1413458400
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.1171279165
Short name T303
Test name
Test status
Simulation time 406546177 ps
CPU time 0.7 seconds
Started Apr 02 12:22:20 PM PDT 24
Finished Apr 02 12:22:21 PM PDT 24
Peak memory 181604 kb
Host smart-f6b467e4-5175-4d98-8aff-83feb6d0a37b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171279165 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.1171279165
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.3128434556
Short name T365
Test name
Test status
Simulation time 364438339 ps
CPU time 0.97 seconds
Started Apr 02 12:19:21 PM PDT 24
Finished Apr 02 12:19:23 PM PDT 24
Peak memory 183828 kb
Host smart-0a8a5449-48ec-465a-8f02-54ceba130c2d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128434556 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_t
imer_mem_partial_access.3128434556
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.623923608
Short name T316
Test name
Test status
Simulation time 472252085 ps
CPU time 1.22 seconds
Started Apr 02 12:22:33 PM PDT 24
Finished Apr 02 12:22:34 PM PDT 24
Peak memory 183236 kb
Host smart-bd3701b6-1d2b-482b-adcc-1b0e8e00399f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623923608 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_wa
lk.623923608
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.2749920980
Short name T359
Test name
Test status
Simulation time 2485722079 ps
CPU time 2.46 seconds
Started Apr 02 12:18:43 PM PDT 24
Finished Apr 02 12:18:46 PM PDT 24
Peak memory 184220 kb
Host smart-75354afd-5a24-402c-bf8b-0f6a9f29e6fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749920980 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon
_timer_same_csr_outstanding.2749920980
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.3368670001
Short name T344
Test name
Test status
Simulation time 461584529 ps
CPU time 2.38 seconds
Started Apr 02 12:22:33 PM PDT 24
Finished Apr 02 12:22:36 PM PDT 24
Peak memory 198140 kb
Host smart-08f4f88b-f8d3-4a93-be03-59e34a4235bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368670001 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.3368670001
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.1852144752
Short name T35
Test name
Test status
Simulation time 4143942904 ps
CPU time 6.3 seconds
Started Apr 02 12:22:21 PM PDT 24
Finished Apr 02 12:22:27 PM PDT 24
Peak memory 197260 kb
Host smart-fa190009-c428-4a3f-8e7e-0c68ebda1bdd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852144752 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl
_intg_err.1852144752
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.954641600
Short name T282
Test name
Test status
Simulation time 271480284 ps
CPU time 0.94 seconds
Started Apr 02 12:20:45 PM PDT 24
Finished Apr 02 12:20:46 PM PDT 24
Peak memory 183624 kb
Host smart-a0639e29-d29c-4f82-8609-e98669c0ed6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954641600 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.954641600
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.1149606492
Short name T312
Test name
Test status
Simulation time 435686864 ps
CPU time 1.18 seconds
Started Apr 02 12:22:24 PM PDT 24
Finished Apr 02 12:22:26 PM PDT 24
Peak memory 182460 kb
Host smart-b10c2c78-5191-40c6-85fe-03fbaffc6b75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149606492 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.1149606492
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.868355768
Short name T373
Test name
Test status
Simulation time 335516287 ps
CPU time 1.1 seconds
Started Apr 02 12:22:24 PM PDT 24
Finished Apr 02 12:22:26 PM PDT 24
Peak memory 182468 kb
Host smart-fa2e0f9a-acce-4efe-a2c9-415cd8fe91d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868355768 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.868355768
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.2637432560
Short name T283
Test name
Test status
Simulation time 453461297 ps
CPU time 1.25 seconds
Started Apr 02 12:20:53 PM PDT 24
Finished Apr 02 12:20:54 PM PDT 24
Peak memory 183624 kb
Host smart-ecb4e1f0-9391-4103-9e19-a2d3afdf1a34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637432560 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.2637432560
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.1651413042
Short name T335
Test name
Test status
Simulation time 447535420 ps
CPU time 1.22 seconds
Started Apr 02 12:22:41 PM PDT 24
Finished Apr 02 12:22:43 PM PDT 24
Peak memory 183408 kb
Host smart-418391f1-2bcc-48ba-aa80-4d69df85b969
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651413042 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.1651413042
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.184453413
Short name T362
Test name
Test status
Simulation time 321780536 ps
CPU time 0.77 seconds
Started Apr 02 12:20:43 PM PDT 24
Finished Apr 02 12:20:44 PM PDT 24
Peak memory 183492 kb
Host smart-c8235464-ffbf-4d30-80f6-1ecbe2d6d16f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184453413 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.184453413
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.2329688100
Short name T350
Test name
Test status
Simulation time 522292935 ps
CPU time 0.75 seconds
Started Apr 02 12:22:42 PM PDT 24
Finished Apr 02 12:22:43 PM PDT 24
Peak memory 183384 kb
Host smart-7e912e94-c8fd-4244-b5fe-b8a5a4a84e2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329688100 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.2329688100
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.448533393
Short name T411
Test name
Test status
Simulation time 399686745 ps
CPU time 1.22 seconds
Started Apr 02 12:22:21 PM PDT 24
Finished Apr 02 12:22:23 PM PDT 24
Peak memory 183424 kb
Host smart-494b55f1-ba4c-43e4-abb4-fd2c19f5400c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448533393 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.448533393
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.951081032
Short name T399
Test name
Test status
Simulation time 415598483 ps
CPU time 1.15 seconds
Started Apr 02 12:22:18 PM PDT 24
Finished Apr 02 12:22:21 PM PDT 24
Peak memory 182360 kb
Host smart-6b7963ec-a4ef-4dd4-80a9-3fc4ac8747b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951081032 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.951081032
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.2193344094
Short name T274
Test name
Test status
Simulation time 326093236 ps
CPU time 0.63 seconds
Started Apr 02 12:22:42 PM PDT 24
Finished Apr 02 12:22:43 PM PDT 24
Peak memory 183408 kb
Host smart-ecc5dff1-af1c-4186-ac84-0c4f8cbf3c3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193344094 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.2193344094
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.2981572943
Short name T382
Test name
Test status
Simulation time 467545472 ps
CPU time 0.98 seconds
Started Apr 02 12:22:14 PM PDT 24
Finished Apr 02 12:22:16 PM PDT 24
Peak memory 195084 kb
Host smart-cbbc7757-81b0-4b7e-ab61-a898637cf07e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981572943 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.2981572943
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.1061077004
Short name T370
Test name
Test status
Simulation time 535413924 ps
CPU time 0.79 seconds
Started Apr 02 12:22:15 PM PDT 24
Finished Apr 02 12:22:16 PM PDT 24
Peak memory 192020 kb
Host smart-ba45b0b9-c4f5-4bbb-88c5-35b0163b0898
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061077004 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.1061077004
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.1945561700
Short name T341
Test name
Test status
Simulation time 298656268 ps
CPU time 0.63 seconds
Started Apr 02 12:22:38 PM PDT 24
Finished Apr 02 12:22:39 PM PDT 24
Peak memory 182508 kb
Host smart-c70c1924-703f-47fd-b315-79f746a8fe5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945561700 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.1945561700
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.1597256436
Short name T364
Test name
Test status
Simulation time 1530993038 ps
CPU time 1.5 seconds
Started Apr 02 12:19:10 PM PDT 24
Finished Apr 02 12:19:12 PM PDT 24
Peak memory 193216 kb
Host smart-7e48d6a7-e0c9-4ce9-b9cf-616c756d76f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597256436 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon
_timer_same_csr_outstanding.1597256436
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.73354590
Short name T331
Test name
Test status
Simulation time 633212456 ps
CPU time 2.28 seconds
Started Apr 02 12:22:48 PM PDT 24
Finished Apr 02 12:22:51 PM PDT 24
Peak memory 197216 kb
Host smart-5cdd09d6-8ede-4842-a20b-c853862c2469
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73354590 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.73354590
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.3153051155
Short name T402
Test name
Test status
Simulation time 3910882334 ps
CPU time 7.34 seconds
Started Apr 02 12:22:48 PM PDT 24
Finished Apr 02 12:22:56 PM PDT 24
Peak memory 196688 kb
Host smart-4f553758-f850-43cb-9135-d485425c4603
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153051155 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl
_intg_err.3153051155
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.2667210247
Short name T385
Test name
Test status
Simulation time 312710956 ps
CPU time 1.15 seconds
Started Apr 02 12:22:42 PM PDT 24
Finished Apr 02 12:22:45 PM PDT 24
Peak memory 194244 kb
Host smart-cac92701-992e-486e-843d-dec86c2e2808
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667210247 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.2667210247
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.1919140094
Short name T44
Test name
Test status
Simulation time 339670682 ps
CPU time 0.68 seconds
Started Apr 02 12:22:38 PM PDT 24
Finished Apr 02 12:22:39 PM PDT 24
Peak memory 182628 kb
Host smart-1c6205f4-3ac4-4b27-97fd-02bfe460369a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919140094 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.1919140094
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.432199416
Short name T357
Test name
Test status
Simulation time 403872867 ps
CPU time 0.67 seconds
Started Apr 02 12:22:59 PM PDT 24
Finished Apr 02 12:23:00 PM PDT 24
Peak memory 183488 kb
Host smart-4dcf8c22-2421-41c2-8a27-b1c631486bf5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432199416 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.432199416
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.1887112495
Short name T395
Test name
Test status
Simulation time 1129314544 ps
CPU time 3.28 seconds
Started Apr 02 12:22:14 PM PDT 24
Finished Apr 02 12:22:18 PM PDT 24
Peak memory 192404 kb
Host smart-2e7bc350-d6da-4491-aa92-e043ff68ca1c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887112495 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon
_timer_same_csr_outstanding.1887112495
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.3037856879
Short name T383
Test name
Test status
Simulation time 444438202 ps
CPU time 2.19 seconds
Started Apr 02 12:22:59 PM PDT 24
Finished Apr 02 12:23:01 PM PDT 24
Peak memory 198444 kb
Host smart-8fd5fcf6-e1f9-43ae-839f-4fdfa02a7654
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037856879 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.3037856879
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.176274177
Short name T310
Test name
Test status
Simulation time 8154147594 ps
CPU time 13.7 seconds
Started Apr 02 12:22:14 PM PDT 24
Finished Apr 02 12:22:29 PM PDT 24
Peak memory 196912 kb
Host smart-65a7c057-9739-4118-9eaa-cb1589e93aca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176274177 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_
intg_err.176274177
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.93855803
Short name T393
Test name
Test status
Simulation time 378661720 ps
CPU time 0.86 seconds
Started Apr 02 12:21:24 PM PDT 24
Finished Apr 02 12:21:24 PM PDT 24
Peak memory 196244 kb
Host smart-956c1554-c078-4dbd-90fd-c7965b7f1309
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93855803 -assert nopostproc +UVM_TESTNAME=a
on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.93855803
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.2930737664
Short name T50
Test name
Test status
Simulation time 394699651 ps
CPU time 1.12 seconds
Started Apr 02 12:20:22 PM PDT 24
Finished Apr 02 12:20:23 PM PDT 24
Peak memory 192996 kb
Host smart-42e0a32b-d471-4197-8385-e2207ef0c6c5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930737664 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.2930737664
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.1087804052
Short name T277
Test name
Test status
Simulation time 294829453 ps
CPU time 0.94 seconds
Started Apr 02 12:22:21 PM PDT 24
Finished Apr 02 12:22:22 PM PDT 24
Peak memory 182924 kb
Host smart-27c270a5-9901-4412-8970-0348a2106044
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087804052 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.1087804052
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.1359307418
Short name T342
Test name
Test status
Simulation time 2499619067 ps
CPU time 5.06 seconds
Started Apr 02 12:22:26 PM PDT 24
Finished Apr 02 12:22:32 PM PDT 24
Peak memory 183508 kb
Host smart-a3117fd0-0246-4710-b4e1-6ae7cfbcf62b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359307418 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon
_timer_same_csr_outstanding.1359307418
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.3913503294
Short name T293
Test name
Test status
Simulation time 429016147 ps
CPU time 2.71 seconds
Started Apr 02 12:22:21 PM PDT 24
Finished Apr 02 12:22:24 PM PDT 24
Peak memory 197836 kb
Host smart-04ca53fe-95d9-4d69-ac0d-604f558341bf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913503294 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.3913503294
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.1739223664
Short name T356
Test name
Test status
Simulation time 4458979153 ps
CPU time 2.75 seconds
Started Apr 02 12:19:18 PM PDT 24
Finished Apr 02 12:19:20 PM PDT 24
Peak memory 196192 kb
Host smart-43ab8516-364e-4d90-8eba-d8cd8f50ac94
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739223664 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl
_intg_err.1739223664
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.2434824787
Short name T353
Test name
Test status
Simulation time 338347858 ps
CPU time 0.84 seconds
Started Apr 02 12:23:29 PM PDT 24
Finished Apr 02 12:23:30 PM PDT 24
Peak memory 194780 kb
Host smart-d507150a-697d-4adf-99d3-69a50728d601
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434824787 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.2434824787
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.294630004
Short name T56
Test name
Test status
Simulation time 484023425 ps
CPU time 1.25 seconds
Started Apr 02 12:20:56 PM PDT 24
Finished Apr 02 12:20:57 PM PDT 24
Peak memory 183868 kb
Host smart-7bab2400-c6fb-496d-8734-2ffc11d9d41e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294630004 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.294630004
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.1959197530
Short name T354
Test name
Test status
Simulation time 463449349 ps
CPU time 0.68 seconds
Started Apr 02 12:23:44 PM PDT 24
Finished Apr 02 12:23:44 PM PDT 24
Peak memory 183484 kb
Host smart-b5c9855b-7d7b-486a-947d-2b9ddcf334a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959197530 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.1959197530
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.3011035697
Short name T377
Test name
Test status
Simulation time 1845190221 ps
CPU time 1.93 seconds
Started Apr 02 12:19:11 PM PDT 24
Finished Apr 02 12:19:13 PM PDT 24
Peak memory 183924 kb
Host smart-57ad320a-4c2b-428b-afa6-fc0af58aea1f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011035697 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon
_timer_same_csr_outstanding.3011035697
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.3230805433
Short name T297
Test name
Test status
Simulation time 599550129 ps
CPU time 1.75 seconds
Started Apr 02 12:19:17 PM PDT 24
Finished Apr 02 12:19:19 PM PDT 24
Peak memory 198536 kb
Host smart-575df651-6e2f-4ce4-b2db-a37c0f99dd52
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230805433 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.3230805433
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.3421868298
Short name T380
Test name
Test status
Simulation time 4134436446 ps
CPU time 2.54 seconds
Started Apr 02 12:23:44 PM PDT 24
Finished Apr 02 12:23:47 PM PDT 24
Peak memory 197068 kb
Host smart-b93a177d-2051-4156-b6d0-0f21d1b5de19
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421868298 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl
_intg_err.3421868298
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.3085375376
Short name T416
Test name
Test status
Simulation time 561634777 ps
CPU time 0.98 seconds
Started Apr 02 12:19:16 PM PDT 24
Finished Apr 02 12:19:17 PM PDT 24
Peak memory 197540 kb
Host smart-aca80d0d-7af5-4ec1-b5d0-af77fffb00e6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085375376 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.3085375376
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.4249963023
Short name T296
Test name
Test status
Simulation time 427076513 ps
CPU time 0.63 seconds
Started Apr 02 12:19:13 PM PDT 24
Finished Apr 02 12:19:14 PM PDT 24
Peak memory 191928 kb
Host smart-68a7b313-101d-4a27-8d39-2ef20d1a05ff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249963023 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.4249963023
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.2613363484
Short name T389
Test name
Test status
Simulation time 510395486 ps
CPU time 0.76 seconds
Started Apr 02 12:19:17 PM PDT 24
Finished Apr 02 12:19:18 PM PDT 24
Peak memory 183612 kb
Host smart-6674bb4e-15d8-4390-8bd3-33722e302bc1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613363484 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.2613363484
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.2019472125
Short name T33
Test name
Test status
Simulation time 1493142936 ps
CPU time 0.89 seconds
Started Apr 02 12:22:33 PM PDT 24
Finished Apr 02 12:22:34 PM PDT 24
Peak memory 182104 kb
Host smart-23d761da-52df-4efd-a3e1-00907d0d547a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019472125 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon
_timer_same_csr_outstanding.2019472125
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.2946629485
Short name T403
Test name
Test status
Simulation time 701126432 ps
CPU time 1.91 seconds
Started Apr 02 12:19:18 PM PDT 24
Finished Apr 02 12:19:20 PM PDT 24
Peak memory 198564 kb
Host smart-380a0194-a68c-46a0-ad27-40d07afc7d22
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946629485 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.2946629485
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.2958275528
Short name T406
Test name
Test status
Simulation time 7847169384 ps
CPU time 4.04 seconds
Started Apr 02 12:19:18 PM PDT 24
Finished Apr 02 12:19:22 PM PDT 24
Peak memory 198056 kb
Host smart-6b4c7b23-39c3-491e-9832-136222741555
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958275528 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl
_intg_err.2958275528
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_jump.3051352620
Short name T182
Test name
Test status
Simulation time 436731338 ps
CPU time 0.87 seconds
Started Apr 02 12:23:57 PM PDT 24
Finished Apr 02 12:23:58 PM PDT 24
Peak memory 183288 kb
Host smart-4dd28c6c-2b7f-49fa-b956-1a84d8157793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051352620 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.3051352620
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.4039122627
Short name T229
Test name
Test status
Simulation time 17725067954 ps
CPU time 28.34 seconds
Started Apr 02 12:23:54 PM PDT 24
Finished Apr 02 12:24:23 PM PDT 24
Peak memory 191480 kb
Host smart-c5f45c73-5ba8-49c0-bae6-73caa3f57e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039122627 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.4039122627
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.2602120197
Short name T194
Test name
Test status
Simulation time 356186075 ps
CPU time 0.65 seconds
Started Apr 02 12:23:50 PM PDT 24
Finished Apr 02 12:23:51 PM PDT 24
Peak memory 183188 kb
Host smart-e61acea6-ea2b-454c-b2dc-f6316f7dd4bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602120197 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.2602120197
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.2775723651
Short name T110
Test name
Test status
Simulation time 219484456932 ps
CPU time 364.79 seconds
Started Apr 02 12:24:13 PM PDT 24
Finished Apr 02 12:30:18 PM PDT 24
Peak memory 193912 kb
Host smart-7033bf5b-1f60-45e5-8139-e0bc0f831b11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775723651 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_a
ll.2775723651
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_jump.437124490
Short name T133
Test name
Test status
Simulation time 406577384 ps
CPU time 0.73 seconds
Started Apr 02 12:24:11 PM PDT 24
Finished Apr 02 12:24:12 PM PDT 24
Peak memory 183240 kb
Host smart-a87a0751-c7d3-4564-bb35-34102d2228f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437124490 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.437124490
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.2572442110
Short name T13
Test name
Test status
Simulation time 8415687528 ps
CPU time 2.7 seconds
Started Apr 02 12:24:39 PM PDT 24
Finished Apr 02 12:24:42 PM PDT 24
Peak memory 215156 kb
Host smart-23937b4e-1547-40b3-93de-d55cab97bace
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572442110 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.2572442110
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.2326722662
Short name T105
Test name
Test status
Simulation time 505465728 ps
CPU time 1.33 seconds
Started Apr 02 12:24:21 PM PDT 24
Finished Apr 02 12:24:22 PM PDT 24
Peak memory 183208 kb
Host smart-549fe402-2523-47ee-9d1f-5e23aab34fe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326722662 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.2326722662
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.2339268537
Short name T91
Test name
Test status
Simulation time 769693076884 ps
CPU time 1290.54 seconds
Started Apr 02 12:24:00 PM PDT 24
Finished Apr 02 12:45:31 PM PDT 24
Peak memory 193168 kb
Host smart-7ef76c97-355a-4f5f-a46b-f31d23fa7073
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339268537 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_a
ll.2339268537
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.3585210820
Short name T37
Test name
Test status
Simulation time 111734500500 ps
CPU time 240.87 seconds
Started Apr 02 12:23:50 PM PDT 24
Finished Apr 02 12:27:51 PM PDT 24
Peak memory 198180 kb
Host smart-6da40a7d-5dc1-4b6f-b717-bd006192adc0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585210820 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.3585210820
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.aon_timer_jump.2735435547
Short name T227
Test name
Test status
Simulation time 423768671 ps
CPU time 0.86 seconds
Started Apr 02 12:24:09 PM PDT 24
Finished Apr 02 12:24:10 PM PDT 24
Peak memory 183332 kb
Host smart-0bfc24ca-ee5d-49d8-be91-dd3441c454e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735435547 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.2735435547
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.1267912334
Short name T11
Test name
Test status
Simulation time 33835021648 ps
CPU time 24.24 seconds
Started Apr 02 12:24:13 PM PDT 24
Finished Apr 02 12:24:37 PM PDT 24
Peak memory 191468 kb
Host smart-51525b2d-7a9c-4813-989d-8970b30d5923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267912334 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.1267912334
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.716211960
Short name T232
Test name
Test status
Simulation time 492170069 ps
CPU time 0.75 seconds
Started Apr 02 12:24:08 PM PDT 24
Finished Apr 02 12:24:09 PM PDT 24
Peak memory 183184 kb
Host smart-acc64543-a0e2-46c5-84bd-b1e46f3c84e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716211960 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.716211960
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.1487614425
Short name T143
Test name
Test status
Simulation time 143288763985 ps
CPU time 177.57 seconds
Started Apr 02 12:24:06 PM PDT 24
Finished Apr 02 12:27:04 PM PDT 24
Peak memory 194668 kb
Host smart-d948c9b9-baf8-422b-9c06-d97cc5de3cc5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487614425 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_
all.1487614425
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.3867897382
Short name T74
Test name
Test status
Simulation time 93542402609 ps
CPU time 183.82 seconds
Started Apr 02 12:24:16 PM PDT 24
Finished Apr 02 12:27:20 PM PDT 24
Peak memory 198196 kb
Host smart-c4ea72bb-4521-4a98-bf7c-32e069f012d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867897382 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.3867897382
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.aon_timer_jump.1695797817
Short name T210
Test name
Test status
Simulation time 374266973 ps
CPU time 1.06 seconds
Started Apr 02 12:24:06 PM PDT 24
Finished Apr 02 12:24:08 PM PDT 24
Peak memory 183252 kb
Host smart-4ed352ca-c852-40ce-805e-55d71bba583e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695797817 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.1695797817
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.1549003937
Short name T115
Test name
Test status
Simulation time 11902791283 ps
CPU time 5.93 seconds
Started Apr 02 12:24:18 PM PDT 24
Finished Apr 02 12:24:24 PM PDT 24
Peak memory 191328 kb
Host smart-5341d9c7-6b72-460c-897f-8449892a881d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549003937 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.1549003937
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.2055011774
Short name T135
Test name
Test status
Simulation time 569544682 ps
CPU time 0.79 seconds
Started Apr 02 12:23:59 PM PDT 24
Finished Apr 02 12:24:00 PM PDT 24
Peak memory 182464 kb
Host smart-fca0d9a6-16cf-4e3c-837f-7d0c0e4f0281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055011774 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.2055011774
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.2230467417
Short name T254
Test name
Test status
Simulation time 189428627366 ps
CPU time 535.44 seconds
Started Apr 02 12:24:13 PM PDT 24
Finished Apr 02 12:33:09 PM PDT 24
Peak memory 198876 kb
Host smart-ab39c350-76a4-45a6-9572-9a77492019d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230467417 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand_reset.2230467417
Directory /workspace/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.aon_timer_jump.2678113748
Short name T269
Test name
Test status
Simulation time 417995779 ps
CPU time 0.89 seconds
Started Apr 02 12:24:12 PM PDT 24
Finished Apr 02 12:24:13 PM PDT 24
Peak memory 183208 kb
Host smart-51590a84-043c-4040-bb3f-8f34b4b022f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678113748 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.2678113748
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.59790507
Short name T256
Test name
Test status
Simulation time 37980972057 ps
CPU time 56.58 seconds
Started Apr 02 12:24:12 PM PDT 24
Finished Apr 02 12:25:09 PM PDT 24
Peak memory 191456 kb
Host smart-e8095543-3c3c-49db-ba5a-d01e6a5efb16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59790507 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.59790507
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.3429686835
Short name T212
Test name
Test status
Simulation time 554848556 ps
CPU time 0.72 seconds
Started Apr 02 12:24:09 PM PDT 24
Finished Apr 02 12:24:10 PM PDT 24
Peak memory 183216 kb
Host smart-8e724a46-c97e-4afd-a8cf-aa8e23cb9ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429686835 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.3429686835
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.4023154095
Short name T141
Test name
Test status
Simulation time 193133000506 ps
CPU time 331.95 seconds
Started Apr 02 12:24:08 PM PDT 24
Finished Apr 02 12:29:40 PM PDT 24
Peak memory 193580 kb
Host smart-25cdb161-6b63-4a9a-b5a0-bba0337b257c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023154095 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_
all.4023154095
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.3182802133
Short name T68
Test name
Test status
Simulation time 78208191439 ps
CPU time 836.67 seconds
Started Apr 02 12:24:13 PM PDT 24
Finished Apr 02 12:38:10 PM PDT 24
Peak memory 202256 kb
Host smart-6017a21e-6d99-4a84-9d1e-4e7935a56e0e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182802133 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.3182802133
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_jump.996496368
Short name T41
Test name
Test status
Simulation time 521363084 ps
CPU time 0.88 seconds
Started Apr 02 12:24:11 PM PDT 24
Finished Apr 02 12:24:12 PM PDT 24
Peak memory 183252 kb
Host smart-b4faa493-7c9a-447a-b1e3-dfc7d3f77848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996496368 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.996496368
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.259979114
Short name T230
Test name
Test status
Simulation time 20065312103 ps
CPU time 12.72 seconds
Started Apr 02 12:24:06 PM PDT 24
Finished Apr 02 12:24:19 PM PDT 24
Peak memory 190724 kb
Host smart-931dc4d2-588a-46ff-ac19-d0b9c05bc26c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259979114 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.259979114
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.1696216729
Short name T145
Test name
Test status
Simulation time 619921492 ps
CPU time 0.69 seconds
Started Apr 02 12:24:10 PM PDT 24
Finished Apr 02 12:24:11 PM PDT 24
Peak memory 183324 kb
Host smart-c785e0fe-2087-4ae4-855f-69d8e8509c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696216729 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.1696216729
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_jump.2742069624
Short name T98
Test name
Test status
Simulation time 582832107 ps
CPU time 1.52 seconds
Started Apr 02 12:24:01 PM PDT 24
Finished Apr 02 12:24:03 PM PDT 24
Peak memory 183252 kb
Host smart-7d4c6abd-8c62-4427-a7b1-4b49dd031c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742069624 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.2742069624
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.416722987
Short name T233
Test name
Test status
Simulation time 26058139645 ps
CPU time 3.79 seconds
Started Apr 02 12:24:09 PM PDT 24
Finished Apr 02 12:24:13 PM PDT 24
Peak memory 191480 kb
Host smart-0d013d62-3f31-4d4e-8b44-1ae92098dd6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416722987 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.416722987
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.2729004657
Short name T134
Test name
Test status
Simulation time 476089702 ps
CPU time 0.82 seconds
Started Apr 02 12:24:05 PM PDT 24
Finished Apr 02 12:24:05 PM PDT 24
Peak memory 183184 kb
Host smart-5a649cfe-009a-42be-b30e-22a4a68d0731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729004657 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.2729004657
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.3891027065
Short name T250
Test name
Test status
Simulation time 76334334761 ps
CPU time 81.44 seconds
Started Apr 02 12:23:59 PM PDT 24
Finished Apr 02 12:25:21 PM PDT 24
Peak memory 194276 kb
Host smart-25ce20a0-7b15-4939-999c-950ce3e59314
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891027065 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_
all.3891027065
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.3039933089
Short name T177
Test name
Test status
Simulation time 21013766041 ps
CPU time 231.73 seconds
Started Apr 02 12:24:21 PM PDT 24
Finished Apr 02 12:28:12 PM PDT 24
Peak memory 198232 kb
Host smart-50121228-d47f-498f-919f-eceab8cc6d86
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039933089 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.3039933089
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.aon_timer_jump.3921390192
Short name T208
Test name
Test status
Simulation time 428453186 ps
CPU time 1.27 seconds
Started Apr 02 12:24:14 PM PDT 24
Finished Apr 02 12:24:15 PM PDT 24
Peak memory 183248 kb
Host smart-21e107a8-535c-4249-8c27-ad9257c51a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921390192 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.3921390192
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.3896461171
Short name T140
Test name
Test status
Simulation time 8508114982 ps
CPU time 6.5 seconds
Started Apr 02 12:24:08 PM PDT 24
Finished Apr 02 12:24:15 PM PDT 24
Peak memory 183432 kb
Host smart-4c43afa9-946a-4e2a-ab8a-4149b3584dda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896461171 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.3896461171
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.1119683922
Short name T255
Test name
Test status
Simulation time 383290302 ps
CPU time 0.68 seconds
Started Apr 02 12:24:01 PM PDT 24
Finished Apr 02 12:24:01 PM PDT 24
Peak memory 183208 kb
Host smart-a2aa952b-6b8c-4b6d-b34f-9424a0463319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119683922 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.1119683922
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.661606144
Short name T211
Test name
Test status
Simulation time 212452975108 ps
CPU time 350.71 seconds
Started Apr 02 12:24:07 PM PDT 24
Finished Apr 02 12:29:58 PM PDT 24
Peak memory 183496 kb
Host smart-2e94ff59-2377-468a-8c33-09cff6257b0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661606144 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_a
ll.661606144
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_jump.357112567
Short name T21
Test name
Test status
Simulation time 483835809 ps
CPU time 0.75 seconds
Started Apr 02 12:24:56 PM PDT 24
Finished Apr 02 12:24:57 PM PDT 24
Peak memory 183228 kb
Host smart-4da1a5ac-316c-4b17-a57e-e8c40afeb4d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357112567 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.357112567
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.1851271205
Short name T160
Test name
Test status
Simulation time 19277732438 ps
CPU time 6.94 seconds
Started Apr 02 12:24:28 PM PDT 24
Finished Apr 02 12:24:35 PM PDT 24
Peak memory 191520 kb
Host smart-e099d973-54e0-4abf-a766-720695245c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851271205 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.1851271205
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.285505134
Short name T205
Test name
Test status
Simulation time 394042411 ps
CPU time 0.99 seconds
Started Apr 02 12:24:17 PM PDT 24
Finished Apr 02 12:24:18 PM PDT 24
Peak memory 183220 kb
Host smart-0ca8b0a7-f029-4931-9276-fa1b269d9919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285505134 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.285505134
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.3879566005
Short name T22
Test name
Test status
Simulation time 230811185687 ps
CPU time 188.57 seconds
Started Apr 02 12:24:17 PM PDT 24
Finished Apr 02 12:27:26 PM PDT 24
Peak memory 195048 kb
Host smart-0c48722e-901b-4566-960b-561ffd4331aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879566005 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_
all.3879566005
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.774366008
Short name T221
Test name
Test status
Simulation time 22804652566 ps
CPU time 54.46 seconds
Started Apr 02 12:24:08 PM PDT 24
Finished Apr 02 12:25:02 PM PDT 24
Peak memory 198200 kb
Host smart-a7d501e0-4b06-41e5-b102-4d3e98722b49
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774366008 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.774366008
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.aon_timer_jump.1575642688
Short name T219
Test name
Test status
Simulation time 538494276 ps
CPU time 0.71 seconds
Started Apr 02 12:24:29 PM PDT 24
Finished Apr 02 12:24:29 PM PDT 24
Peak memory 183148 kb
Host smart-13ad4d7a-5ed5-4503-bfd1-a725eb79cc31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575642688 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.1575642688
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.3942658979
Short name T104
Test name
Test status
Simulation time 4189756518 ps
CPU time 3.81 seconds
Started Apr 02 12:24:22 PM PDT 24
Finished Apr 02 12:24:26 PM PDT 24
Peak memory 183316 kb
Host smart-5985ceec-2ec4-44e0-9b4c-137df8191543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942658979 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.3942658979
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.412929181
Short name T263
Test name
Test status
Simulation time 585613209 ps
CPU time 0.59 seconds
Started Apr 02 12:24:16 PM PDT 24
Finished Apr 02 12:24:17 PM PDT 24
Peak memory 183228 kb
Host smart-ee4c5958-0127-4ebb-9862-8b06e61d629c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412929181 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.412929181
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_jump.1738464544
Short name T147
Test name
Test status
Simulation time 412025158 ps
CPU time 1.2 seconds
Started Apr 02 12:24:18 PM PDT 24
Finished Apr 02 12:24:19 PM PDT 24
Peak memory 183056 kb
Host smart-d788091e-988f-4e8f-960c-67074eff1d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738464544 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.1738464544
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.258635545
Short name T149
Test name
Test status
Simulation time 58070020504 ps
CPU time 89.67 seconds
Started Apr 02 12:24:17 PM PDT 24
Finished Apr 02 12:25:47 PM PDT 24
Peak memory 183276 kb
Host smart-fb8d3d63-a41f-447f-9ac4-540a5128ff82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258635545 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.258635545
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.73700447
Short name T176
Test name
Test status
Simulation time 407841364 ps
CPU time 1.27 seconds
Started Apr 02 12:24:21 PM PDT 24
Finished Apr 02 12:24:22 PM PDT 24
Peak memory 183364 kb
Host smart-dc6facd3-df6b-46bf-b6aa-103331a77638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73700447 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.73700447
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.3647290049
Short name T224
Test name
Test status
Simulation time 372670647261 ps
CPU time 127.84 seconds
Started Apr 02 12:24:05 PM PDT 24
Finished Apr 02 12:26:13 PM PDT 24
Peak memory 194796 kb
Host smart-f52e09e0-8931-4ac5-a11a-4d14c755de82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647290049 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_
all.3647290049
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.2756083224
Short name T175
Test name
Test status
Simulation time 10678593371 ps
CPU time 103.72 seconds
Started Apr 02 12:24:06 PM PDT 24
Finished Apr 02 12:25:50 PM PDT 24
Peak memory 198200 kb
Host smart-00a923d8-0b62-4805-9e06-51ba1a51bb73
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756083224 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.2756083224
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.aon_timer_jump.2772964860
Short name T102
Test name
Test status
Simulation time 350980008 ps
CPU time 1.04 seconds
Started Apr 02 12:24:26 PM PDT 24
Finished Apr 02 12:24:27 PM PDT 24
Peak memory 183220 kb
Host smart-7ba6dd7a-a36d-471f-840d-39d32fbae68e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772964860 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.2772964860
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.3477334982
Short name T24
Test name
Test status
Simulation time 36289675827 ps
CPU time 58.49 seconds
Started Apr 02 12:24:19 PM PDT 24
Finished Apr 02 12:25:17 PM PDT 24
Peak memory 183232 kb
Host smart-17c3423a-92fb-48ff-aec6-302b397c20fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477334982 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.3477334982
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.521894718
Short name T258
Test name
Test status
Simulation time 575884297 ps
CPU time 0.98 seconds
Started Apr 02 12:24:15 PM PDT 24
Finished Apr 02 12:24:16 PM PDT 24
Peak memory 183268 kb
Host smart-18026abc-964a-4cae-919f-9c043df05020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521894718 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.521894718
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.2984334473
Short name T261
Test name
Test status
Simulation time 140796597075 ps
CPU time 54.41 seconds
Started Apr 02 12:24:10 PM PDT 24
Finished Apr 02 12:25:05 PM PDT 24
Peak memory 183388 kb
Host smart-af1dd20a-9237-4fb5-bc82-53c3fea88b10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984334473 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_
all.2984334473
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.3657163035
Short name T117
Test name
Test status
Simulation time 69574929829 ps
CPU time 192.52 seconds
Started Apr 02 12:24:22 PM PDT 24
Finished Apr 02 12:27:35 PM PDT 24
Peak memory 197992 kb
Host smart-ffb74f05-a0fb-4073-a018-bf3a06a6ae3d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657163035 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.3657163035
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_jump.4033984417
Short name T252
Test name
Test status
Simulation time 452463023 ps
CPU time 1.39 seconds
Started Apr 02 12:24:07 PM PDT 24
Finished Apr 02 12:24:10 PM PDT 24
Peak memory 182432 kb
Host smart-360aa5ba-8f9d-4e5f-ab0c-fea0abde6123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033984417 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.4033984417
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.3898375332
Short name T125
Test name
Test status
Simulation time 18395251890 ps
CPU time 4.43 seconds
Started Apr 02 12:24:04 PM PDT 24
Finished Apr 02 12:24:09 PM PDT 24
Peak memory 183308 kb
Host smart-769e3693-d62b-40df-8367-d91891f6c169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898375332 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.3898375332
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.3116955256
Short name T15
Test name
Test status
Simulation time 7737879828 ps
CPU time 11.26 seconds
Started Apr 02 12:24:08 PM PDT 24
Finished Apr 02 12:24:19 PM PDT 24
Peak memory 215032 kb
Host smart-205466cc-289d-4acb-bb48-4973e182a528
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116955256 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.3116955256
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.1018607640
Short name T249
Test name
Test status
Simulation time 570229383 ps
CPU time 0.74 seconds
Started Apr 02 12:24:09 PM PDT 24
Finished Apr 02 12:24:11 PM PDT 24
Peak memory 183240 kb
Host smart-bab0deb8-ec3a-4737-8888-bd14e8fb3a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018607640 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.1018607640
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_jump.1848525004
Short name T248
Test name
Test status
Simulation time 518940048 ps
CPU time 0.92 seconds
Started Apr 02 12:24:18 PM PDT 24
Finished Apr 02 12:24:19 PM PDT 24
Peak memory 183228 kb
Host smart-f6a98715-bcff-4632-adea-ae83490cf8a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848525004 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.1848525004
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.331078909
Short name T246
Test name
Test status
Simulation time 33287794606 ps
CPU time 49.78 seconds
Started Apr 02 12:24:15 PM PDT 24
Finished Apr 02 12:25:05 PM PDT 24
Peak memory 183308 kb
Host smart-49972835-7164-4040-8a38-d5f0d677d196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331078909 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.331078909
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.3689606941
Short name T193
Test name
Test status
Simulation time 407012970 ps
CPU time 1.08 seconds
Started Apr 02 12:24:35 PM PDT 24
Finished Apr 02 12:24:36 PM PDT 24
Peak memory 183144 kb
Host smart-f912acea-c51b-4b82-8fb0-1e97530dee15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689606941 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.3689606941
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.4196094660
Short name T132
Test name
Test status
Simulation time 117653039267 ps
CPU time 53.89 seconds
Started Apr 02 12:24:08 PM PDT 24
Finished Apr 02 12:25:02 PM PDT 24
Peak memory 193628 kb
Host smart-4742636b-fc83-4154-841c-852c51a32df5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196094660 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_
all.4196094660
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/21.aon_timer_jump.3851783754
Short name T106
Test name
Test status
Simulation time 525056650 ps
CPU time 0.76 seconds
Started Apr 02 12:24:07 PM PDT 24
Finished Apr 02 12:24:08 PM PDT 24
Peak memory 183340 kb
Host smart-13144aca-4f19-4327-9823-3295d77a70e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851783754 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.3851783754
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.4240448285
Short name T197
Test name
Test status
Simulation time 49341235428 ps
CPU time 19.81 seconds
Started Apr 02 12:24:08 PM PDT 24
Finished Apr 02 12:24:28 PM PDT 24
Peak memory 191512 kb
Host smart-a1c31c8c-b34b-43ab-ac08-a1a8902059c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240448285 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.4240448285
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.522896206
Short name T185
Test name
Test status
Simulation time 470132795 ps
CPU time 0.88 seconds
Started Apr 02 12:24:17 PM PDT 24
Finished Apr 02 12:24:18 PM PDT 24
Peak memory 183308 kb
Host smart-eca5ac49-1db9-4e75-a752-ca3e8d5eb356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522896206 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.522896206
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.101490932
Short name T123
Test name
Test status
Simulation time 145363725602 ps
CPU time 239.68 seconds
Started Apr 02 12:24:12 PM PDT 24
Finished Apr 02 12:28:12 PM PDT 24
Peak memory 183316 kb
Host smart-42a49f06-71b1-4b75-8504-be8b37d492c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101490932 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_a
ll.101490932
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.3068631193
Short name T241
Test name
Test status
Simulation time 100705566926 ps
CPU time 221.52 seconds
Started Apr 02 12:24:38 PM PDT 24
Finished Apr 02 12:28:20 PM PDT 24
Peak memory 198260 kb
Host smart-fac3a848-e591-409b-a623-a7df6ee5d5fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068631193 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.3068631193
Directory /workspace/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.aon_timer_jump.3764805540
Short name T266
Test name
Test status
Simulation time 387059907 ps
CPU time 1.14 seconds
Started Apr 02 12:24:16 PM PDT 24
Finished Apr 02 12:24:17 PM PDT 24
Peak memory 183272 kb
Host smart-e89e15c7-ea35-4dbb-8aa0-0c63665b277d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764805540 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.3764805540
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.2210168469
Short name T85
Test name
Test status
Simulation time 27824396877 ps
CPU time 20.1 seconds
Started Apr 02 12:24:35 PM PDT 24
Finished Apr 02 12:24:55 PM PDT 24
Peak memory 183280 kb
Host smart-a6dd0333-7760-4908-a4fe-492da68fb82c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210168469 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.2210168469
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.1070397056
Short name T109
Test name
Test status
Simulation time 540935340 ps
CPU time 1.44 seconds
Started Apr 02 12:24:06 PM PDT 24
Finished Apr 02 12:24:08 PM PDT 24
Peak memory 183204 kb
Host smart-3671ccd3-1e28-41a7-8f01-359ff7893027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070397056 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.1070397056
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.4207154861
Short name T178
Test name
Test status
Simulation time 246639945281 ps
CPU time 87.87 seconds
Started Apr 02 12:24:23 PM PDT 24
Finished Apr 02 12:25:52 PM PDT 24
Peak memory 192684 kb
Host smart-f47c349c-4b45-4c57-a373-5a896517d02f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207154861 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_
all.4207154861
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.940733621
Short name T267
Test name
Test status
Simulation time 72184425317 ps
CPU time 575.78 seconds
Started Apr 02 12:24:22 PM PDT 24
Finished Apr 02 12:33:57 PM PDT 24
Peak memory 206256 kb
Host smart-ff47eeff-fd4c-4155-be11-f2e4ff570781
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940733621 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.940733621
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.aon_timer_jump.2763735466
Short name T164
Test name
Test status
Simulation time 345006517 ps
CPU time 1.02 seconds
Started Apr 02 12:24:11 PM PDT 24
Finished Apr 02 12:24:13 PM PDT 24
Peak memory 183212 kb
Host smart-e63c56aa-ebad-4464-9954-5bffed3bf172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763735466 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.2763735466
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.3440745315
Short name T199
Test name
Test status
Simulation time 9218700108 ps
CPU time 13.71 seconds
Started Apr 02 12:24:10 PM PDT 24
Finished Apr 02 12:24:24 PM PDT 24
Peak memory 183268 kb
Host smart-cb2ca3d0-8568-4a95-8fd7-7774718d49be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440745315 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.3440745315
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.4085196740
Short name T114
Test name
Test status
Simulation time 456378523 ps
CPU time 0.88 seconds
Started Apr 02 12:24:14 PM PDT 24
Finished Apr 02 12:24:15 PM PDT 24
Peak memory 183260 kb
Host smart-e7dfaae9-c267-46f5-b9e1-861246ca4646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085196740 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.4085196740
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.1766018302
Short name T5
Test name
Test status
Simulation time 54722282924 ps
CPU time 68.57 seconds
Started Apr 02 12:24:17 PM PDT 24
Finished Apr 02 12:25:25 PM PDT 24
Peak memory 193604 kb
Host smart-d7ed81b7-7ffe-4972-8990-082dde8f6467
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766018302 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_
all.1766018302
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_jump.1925092788
Short name T243
Test name
Test status
Simulation time 490101155 ps
CPU time 1.32 seconds
Started Apr 02 12:24:13 PM PDT 24
Finished Apr 02 12:24:15 PM PDT 24
Peak memory 183224 kb
Host smart-cdc0b7a5-8274-433a-b96a-2b334659f816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925092788 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.1925092788
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.3921116697
Short name T136
Test name
Test status
Simulation time 4176557327 ps
CPU time 1.68 seconds
Started Apr 02 12:24:55 PM PDT 24
Finished Apr 02 12:24:57 PM PDT 24
Peak memory 183308 kb
Host smart-7e4e3132-d536-4137-8cdb-96b506731603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921116697 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.3921116697
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.1909217319
Short name T231
Test name
Test status
Simulation time 575108586 ps
CPU time 1.32 seconds
Started Apr 02 12:24:16 PM PDT 24
Finished Apr 02 12:24:17 PM PDT 24
Peak memory 183224 kb
Host smart-7834d335-ed4c-4e9b-b9a3-aa356e790e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909217319 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.1909217319
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.3431888901
Short name T166
Test name
Test status
Simulation time 97220976005 ps
CPU time 37 seconds
Started Apr 02 12:24:12 PM PDT 24
Finished Apr 02 12:24:49 PM PDT 24
Peak memory 191492 kb
Host smart-af26b0d0-cf1b-4d16-95dd-36d35b1c404d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431888901 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_
all.3431888901
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.2755712143
Short name T71
Test name
Test status
Simulation time 92695702203 ps
CPU time 605.38 seconds
Started Apr 02 12:24:28 PM PDT 24
Finished Apr 02 12:34:34 PM PDT 24
Peak memory 198832 kb
Host smart-5b79aee0-cf57-47da-b2c6-61f36c095489
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755712143 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand_reset.2755712143
Directory /workspace/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.aon_timer_jump.870257492
Short name T272
Test name
Test status
Simulation time 608864847 ps
CPU time 0.71 seconds
Started Apr 02 12:24:15 PM PDT 24
Finished Apr 02 12:24:16 PM PDT 24
Peak memory 183256 kb
Host smart-29e250e6-74d1-4aa3-abe7-9c7484bec2c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870257492 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.870257492
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.1509405236
Short name T90
Test name
Test status
Simulation time 34864303530 ps
CPU time 61.43 seconds
Started Apr 02 12:24:14 PM PDT 24
Finished Apr 02 12:25:15 PM PDT 24
Peak memory 183280 kb
Host smart-0e6e569c-f18f-44e1-a2fc-d57aeeb7c56a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509405236 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.1509405236
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.961345847
Short name T82
Test name
Test status
Simulation time 482118036 ps
CPU time 1.02 seconds
Started Apr 02 12:24:52 PM PDT 24
Finished Apr 02 12:24:53 PM PDT 24
Peak memory 183176 kb
Host smart-ccb53b8c-41ec-4bce-a046-88781220c82c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961345847 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.961345847
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.784563360
Short name T87
Test name
Test status
Simulation time 508785599090 ps
CPU time 203.44 seconds
Started Apr 02 12:24:06 PM PDT 24
Finished Apr 02 12:27:29 PM PDT 24
Peak memory 194804 kb
Host smart-ad93fa96-a360-4f4d-9cf1-1a8610e26dc9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784563360 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_a
ll.784563360
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.732831022
Short name T240
Test name
Test status
Simulation time 25787363281 ps
CPU time 267.79 seconds
Started Apr 02 12:24:13 PM PDT 24
Finished Apr 02 12:28:42 PM PDT 24
Peak memory 198180 kb
Host smart-e1c7d2b9-e4fc-4204-a236-d28f26eaa137
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732831022 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.732831022
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.aon_timer_jump.439822391
Short name T190
Test name
Test status
Simulation time 457376837 ps
CPU time 1.26 seconds
Started Apr 02 12:24:17 PM PDT 24
Finished Apr 02 12:24:18 PM PDT 24
Peak memory 183300 kb
Host smart-0edf6fc8-2fa9-4b6c-b14d-51d6a7caa360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439822391 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.439822391
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.3714969618
Short name T121
Test name
Test status
Simulation time 2954961127 ps
CPU time 4.75 seconds
Started Apr 02 12:24:19 PM PDT 24
Finished Apr 02 12:24:24 PM PDT 24
Peak memory 183244 kb
Host smart-6b16b1d4-01ce-4305-a58c-4bfa70b77687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714969618 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.3714969618
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.3041644080
Short name T162
Test name
Test status
Simulation time 388252180 ps
CPU time 0.68 seconds
Started Apr 02 12:24:12 PM PDT 24
Finished Apr 02 12:24:13 PM PDT 24
Peak memory 183264 kb
Host smart-77edb7b9-94f2-4bc1-a841-0e7ce2874fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041644080 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.3041644080
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.3618424108
Short name T89
Test name
Test status
Simulation time 91253378381 ps
CPU time 87.91 seconds
Started Apr 02 12:24:20 PM PDT 24
Finished Apr 02 12:25:48 PM PDT 24
Peak memory 183280 kb
Host smart-746bb7c1-20be-48f3-837d-f36c7c1d0d00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618424108 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_
all.3618424108
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.66614802
Short name T148
Test name
Test status
Simulation time 82623306955 ps
CPU time 223.07 seconds
Started Apr 02 12:24:07 PM PDT 24
Finished Apr 02 12:27:50 PM PDT 24
Peak memory 198264 kb
Host smart-a2075fb7-47c3-4863-8701-ae91a7a65a0a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66614802 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.66614802
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_jump.68836256
Short name T23
Test name
Test status
Simulation time 394275501 ps
CPU time 1.3 seconds
Started Apr 02 12:24:03 PM PDT 24
Finished Apr 02 12:24:05 PM PDT 24
Peak memory 183228 kb
Host smart-7b67fe43-38ee-425f-9617-53ad5e00d782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68836256 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.68836256
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.757694543
Short name T226
Test name
Test status
Simulation time 35289155540 ps
CPU time 27.41 seconds
Started Apr 02 12:24:23 PM PDT 24
Finished Apr 02 12:24:51 PM PDT 24
Peak memory 183272 kb
Host smart-744f71fb-2ee5-4456-8eba-5ef37d06bdf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757694543 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.757694543
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.2739117082
Short name T167
Test name
Test status
Simulation time 585659704 ps
CPU time 0.64 seconds
Started Apr 02 12:24:15 PM PDT 24
Finished Apr 02 12:24:16 PM PDT 24
Peak memory 183204 kb
Host smart-7881ff67-e3ab-474e-8391-09f3a635866c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739117082 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.2739117082
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.120723744
Short name T101
Test name
Test status
Simulation time 206167785530 ps
CPU time 308.32 seconds
Started Apr 02 12:24:17 PM PDT 24
Finished Apr 02 12:29:26 PM PDT 24
Peak memory 193808 kb
Host smart-627b1730-f74c-494d-8dcb-5055dfbee697
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120723744 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_a
ll.120723744
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.2963983016
Short name T65
Test name
Test status
Simulation time 27745877127 ps
CPU time 207.97 seconds
Started Apr 02 12:24:15 PM PDT 24
Finished Apr 02 12:27:43 PM PDT 24
Peak memory 198132 kb
Host smart-18d7304a-887c-4c95-beec-14cb8fc0729a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963983016 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.2963983016
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_jump.3745538790
Short name T97
Test name
Test status
Simulation time 468840830 ps
CPU time 1.24 seconds
Started Apr 02 12:24:19 PM PDT 24
Finished Apr 02 12:24:20 PM PDT 24
Peak memory 183228 kb
Host smart-c1a9107d-91a4-41ac-b8a2-497519a42d66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745538790 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.3745538790
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.717704580
Short name T173
Test name
Test status
Simulation time 46032434128 ps
CPU time 32.86 seconds
Started Apr 02 12:24:19 PM PDT 24
Finished Apr 02 12:24:52 PM PDT 24
Peak memory 182100 kb
Host smart-e5560aca-969e-4a12-81f4-e407405e5a29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717704580 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.717704580
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.1873103017
Short name T191
Test name
Test status
Simulation time 497844886 ps
CPU time 1.33 seconds
Started Apr 02 12:24:19 PM PDT 24
Finished Apr 02 12:24:21 PM PDT 24
Peak memory 182092 kb
Host smart-774fabdb-9b34-40d8-8d32-fee58aa53cf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873103017 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.1873103017
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.1726909236
Short name T271
Test name
Test status
Simulation time 4493478891 ps
CPU time 8.22 seconds
Started Apr 02 12:24:11 PM PDT 24
Finished Apr 02 12:24:19 PM PDT 24
Peak memory 183396 kb
Host smart-7415500e-a447-4499-b856-ac9d9fac2020
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726909236 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_
all.1726909236
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.1366921186
Short name T38
Test name
Test status
Simulation time 20137790989 ps
CPU time 156.16 seconds
Started Apr 02 12:24:13 PM PDT 24
Finished Apr 02 12:26:49 PM PDT 24
Peak memory 198148 kb
Host smart-5de2c483-5c82-4c19-ad95-edf7fc51466b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366921186 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.1366921186
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.aon_timer_jump.543344110
Short name T183
Test name
Test status
Simulation time 347795391 ps
CPU time 1.12 seconds
Started Apr 02 12:24:06 PM PDT 24
Finished Apr 02 12:24:08 PM PDT 24
Peak memory 183228 kb
Host smart-204f8eba-4e85-45dc-ab0a-fb452f341be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543344110 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.543344110
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.308126835
Short name T154
Test name
Test status
Simulation time 17561188396 ps
CPU time 8.11 seconds
Started Apr 02 12:24:16 PM PDT 24
Finished Apr 02 12:24:24 PM PDT 24
Peak memory 183412 kb
Host smart-bb158157-ff4b-4e05-a04a-196060bf9962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308126835 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.308126835
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.1809058508
Short name T262
Test name
Test status
Simulation time 566509864 ps
CPU time 0.65 seconds
Started Apr 02 12:24:15 PM PDT 24
Finished Apr 02 12:24:16 PM PDT 24
Peak memory 183268 kb
Host smart-d70c5008-3e76-4dc4-b1e6-fa62d2496702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809058508 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.1809058508
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.176243300
Short name T184
Test name
Test status
Simulation time 68963621319 ps
CPU time 26.83 seconds
Started Apr 02 12:24:15 PM PDT 24
Finished Apr 02 12:24:42 PM PDT 24
Peak memory 194020 kb
Host smart-6a063642-bc0a-44b9-9bb5-8fddc9abe3ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176243300 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_a
ll.176243300
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.253303106
Short name T195
Test name
Test status
Simulation time 261999293112 ps
CPU time 750.78 seconds
Started Apr 02 12:24:12 PM PDT 24
Finished Apr 02 12:36:43 PM PDT 24
Peak memory 201932 kb
Host smart-89117e75-a046-4068-8572-a7179bfb51db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253303106 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.253303106
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.aon_timer_jump.3245365249
Short name T268
Test name
Test status
Simulation time 580417039 ps
CPU time 1.35 seconds
Started Apr 02 12:24:02 PM PDT 24
Finished Apr 02 12:24:03 PM PDT 24
Peak memory 182968 kb
Host smart-5e72f590-2136-48a1-9435-42b88662c1cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245365249 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.3245365249
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.2368460228
Short name T244
Test name
Test status
Simulation time 33601632045 ps
CPU time 13.21 seconds
Started Apr 02 12:24:20 PM PDT 24
Finished Apr 02 12:24:33 PM PDT 24
Peak memory 183312 kb
Host smart-ce8ac1a7-f434-4bd8-9d05-9bf8c3086a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368460228 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.2368460228
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.1213591871
Short name T18
Test name
Test status
Simulation time 4286202115 ps
CPU time 1.71 seconds
Started Apr 02 12:24:13 PM PDT 24
Finished Apr 02 12:24:15 PM PDT 24
Peak memory 214624 kb
Host smart-6d79fa85-d4a5-4738-8a7c-67b726de08b5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213591871 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.1213591871
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.3490693989
Short name T130
Test name
Test status
Simulation time 380905123 ps
CPU time 0.72 seconds
Started Apr 02 12:24:05 PM PDT 24
Finished Apr 02 12:24:06 PM PDT 24
Peak memory 182228 kb
Host smart-1ce55cea-d9fc-4f64-913c-ef2218640fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490693989 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.3490693989
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.1681483734
Short name T189
Test name
Test status
Simulation time 94462717994 ps
CPU time 145.02 seconds
Started Apr 02 12:24:15 PM PDT 24
Finished Apr 02 12:26:40 PM PDT 24
Peak memory 195140 kb
Host smart-87ca5d36-c70a-4952-87f3-791a4fe02f32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681483734 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_a
ll.1681483734
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.2581329500
Short name T155
Test name
Test status
Simulation time 161913392713 ps
CPU time 436.08 seconds
Started Apr 02 12:24:23 PM PDT 24
Finished Apr 02 12:31:39 PM PDT 24
Peak memory 198192 kb
Host smart-fb4c9a5e-6b94-4188-b1aa-3cf95cf22ebe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581329500 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.2581329500
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_jump.1657627375
Short name T180
Test name
Test status
Simulation time 566202815 ps
CPU time 1.43 seconds
Started Apr 02 12:24:17 PM PDT 24
Finished Apr 02 12:24:18 PM PDT 24
Peak memory 183228 kb
Host smart-3115a636-da61-42e4-b7a4-ab9ff7284db4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657627375 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.1657627375
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.3247681407
Short name T127
Test name
Test status
Simulation time 23837241488 ps
CPU time 12.64 seconds
Started Apr 02 12:24:18 PM PDT 24
Finished Apr 02 12:24:31 PM PDT 24
Peak memory 183272 kb
Host smart-423900dc-ed61-4731-88a8-932328b66475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247681407 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.3247681407
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.1428083258
Short name T228
Test name
Test status
Simulation time 457450591 ps
CPU time 1.45 seconds
Started Apr 02 12:24:07 PM PDT 24
Finished Apr 02 12:24:09 PM PDT 24
Peak memory 183184 kb
Host smart-619886f4-d00c-44b8-ae30-a002907539e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428083258 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.1428083258
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.13060506
Short name T42
Test name
Test status
Simulation time 204993768296 ps
CPU time 165.89 seconds
Started Apr 02 12:24:18 PM PDT 24
Finished Apr 02 12:27:04 PM PDT 24
Peak memory 183296 kb
Host smart-9179eb3c-6a90-4bab-8849-2066301294d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13060506 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_al
l.13060506
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.3862202316
Short name T200
Test name
Test status
Simulation time 12021598467 ps
CPU time 99.91 seconds
Started Apr 02 12:24:09 PM PDT 24
Finished Apr 02 12:25:49 PM PDT 24
Peak memory 198268 kb
Host smart-2597775c-6ae3-42cb-9cde-0852f6687596
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862202316 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.3862202316
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.aon_timer_jump.1986123623
Short name T239
Test name
Test status
Simulation time 362738250 ps
CPU time 1.17 seconds
Started Apr 02 12:24:19 PM PDT 24
Finished Apr 02 12:24:20 PM PDT 24
Peak memory 183212 kb
Host smart-024430a4-cc96-43b0-9947-cd29f8e1fa1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986123623 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.1986123623
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.1415283611
Short name T156
Test name
Test status
Simulation time 32785457792 ps
CPU time 15.05 seconds
Started Apr 02 12:24:15 PM PDT 24
Finished Apr 02 12:24:30 PM PDT 24
Peak memory 183308 kb
Host smart-3369d2e4-e3fd-44c6-b116-d32aaad15477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415283611 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.1415283611
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.793490806
Short name T222
Test name
Test status
Simulation time 472071777 ps
CPU time 0.82 seconds
Started Apr 02 12:24:10 PM PDT 24
Finished Apr 02 12:24:11 PM PDT 24
Peak memory 183228 kb
Host smart-c3b93154-b731-47c0-aa10-e136bd58dbcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793490806 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.793490806
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.1185534891
Short name T216
Test name
Test status
Simulation time 176115644034 ps
CPU time 65.01 seconds
Started Apr 02 12:25:01 PM PDT 24
Finished Apr 02 12:26:07 PM PDT 24
Peak memory 183300 kb
Host smart-d3199b24-046c-444b-9880-debdd582e9d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185534891 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_
all.1185534891
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.2293665288
Short name T223
Test name
Test status
Simulation time 89670371877 ps
CPU time 957.73 seconds
Started Apr 02 12:24:21 PM PDT 24
Finished Apr 02 12:40:19 PM PDT 24
Peak memory 206548 kb
Host smart-49b75f16-7451-4334-bdbd-b27ff08260cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293665288 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.2293665288
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.aon_timer_jump.3793806615
Short name T209
Test name
Test status
Simulation time 415740002 ps
CPU time 0.94 seconds
Started Apr 02 12:24:19 PM PDT 24
Finished Apr 02 12:24:20 PM PDT 24
Peak memory 183252 kb
Host smart-91c595fd-c3ad-4c4e-8fe3-776b1dbb051d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793806615 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.3793806615
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.1632002813
Short name T273
Test name
Test status
Simulation time 5589246392 ps
CPU time 10.39 seconds
Started Apr 02 12:24:18 PM PDT 24
Finished Apr 02 12:24:29 PM PDT 24
Peak memory 183332 kb
Host smart-1300fb28-6a5a-4f49-8769-d4def7de3b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632002813 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.1632002813
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.3255896133
Short name T146
Test name
Test status
Simulation time 512061101 ps
CPU time 0.68 seconds
Started Apr 02 12:24:17 PM PDT 24
Finished Apr 02 12:24:18 PM PDT 24
Peak memory 183336 kb
Host smart-72189022-a710-4d8c-aa66-1cf053f3ecfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255896133 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.3255896133
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.599120222
Short name T107
Test name
Test status
Simulation time 427482468120 ps
CPU time 667.66 seconds
Started Apr 02 12:24:15 PM PDT 24
Finished Apr 02 12:35:23 PM PDT 24
Peak memory 194428 kb
Host smart-24ecd49e-9f4b-4ae9-9cee-c5967418a016
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599120222 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_a
ll.599120222
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.1482842054
Short name T131
Test name
Test status
Simulation time 231580444398 ps
CPU time 555.11 seconds
Started Apr 02 12:24:41 PM PDT 24
Finished Apr 02 12:33:56 PM PDT 24
Peak memory 207268 kb
Host smart-f3ad4674-c922-441d-8a5a-17650a55ac44
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482842054 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_reset.1482842054
Directory /workspace/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.aon_timer_jump.2062209875
Short name T103
Test name
Test status
Simulation time 388262657 ps
CPU time 0.72 seconds
Started Apr 02 12:24:34 PM PDT 24
Finished Apr 02 12:24:34 PM PDT 24
Peak memory 183272 kb
Host smart-57b4823d-d084-4b5c-b707-8651bf8e6770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062209875 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.2062209875
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.3525977845
Short name T181
Test name
Test status
Simulation time 25275129538 ps
CPU time 37.38 seconds
Started Apr 02 12:24:13 PM PDT 24
Finished Apr 02 12:24:51 PM PDT 24
Peak memory 191488 kb
Host smart-c8677516-a385-47f5-8aaf-4b71d4d58111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525977845 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.3525977845
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.2276609963
Short name T19
Test name
Test status
Simulation time 480466496 ps
CPU time 1.32 seconds
Started Apr 02 12:24:12 PM PDT 24
Finished Apr 02 12:24:14 PM PDT 24
Peak memory 183192 kb
Host smart-d5d9c2bd-b7ac-4fb3-96fd-d718f18f79d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276609963 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.2276609963
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.1146450571
Short name T83
Test name
Test status
Simulation time 352975089866 ps
CPU time 514.59 seconds
Started Apr 02 12:24:17 PM PDT 24
Finished Apr 02 12:32:52 PM PDT 24
Peak memory 191548 kb
Host smart-a007802c-449f-4b85-b245-6c3686cdb6a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146450571 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_
all.1146450571
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.3363267793
Short name T1
Test name
Test status
Simulation time 59302884085 ps
CPU time 265.1 seconds
Started Apr 02 12:24:20 PM PDT 24
Finished Apr 02 12:28:46 PM PDT 24
Peak memory 197452 kb
Host smart-0519fd99-a6b4-47eb-8899-c43f9e91745d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363267793 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.3363267793
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.aon_timer_jump.2242210602
Short name T153
Test name
Test status
Simulation time 414503294 ps
CPU time 0.71 seconds
Started Apr 02 12:24:17 PM PDT 24
Finished Apr 02 12:24:18 PM PDT 24
Peak memory 183196 kb
Host smart-fac2fc69-ccbb-4fac-ad87-109581c23030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242210602 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.2242210602
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.2213606721
Short name T122
Test name
Test status
Simulation time 22986809639 ps
CPU time 5.27 seconds
Started Apr 02 12:24:36 PM PDT 24
Finished Apr 02 12:24:42 PM PDT 24
Peak memory 191484 kb
Host smart-5ac2eb6c-fe75-42aa-898c-40c15ec23020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213606721 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.2213606721
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.221517308
Short name T187
Test name
Test status
Simulation time 514330789 ps
CPU time 0.69 seconds
Started Apr 02 12:24:22 PM PDT 24
Finished Apr 02 12:24:23 PM PDT 24
Peak memory 183224 kb
Host smart-348c428b-0b75-4257-bfcc-0a6543f14862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221517308 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.221517308
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.1528850115
Short name T100
Test name
Test status
Simulation time 139745836678 ps
CPU time 23.23 seconds
Started Apr 02 12:24:16 PM PDT 24
Finished Apr 02 12:24:39 PM PDT 24
Peak memory 183484 kb
Host smart-31041d29-a001-4b35-890d-d0edf739bf27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528850115 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_
all.1528850115
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/35.aon_timer_jump.4172691096
Short name T28
Test name
Test status
Simulation time 550467090 ps
CPU time 1.05 seconds
Started Apr 02 12:24:19 PM PDT 24
Finished Apr 02 12:24:20 PM PDT 24
Peak memory 183284 kb
Host smart-1a2991bd-d240-464b-8e39-edb246b362c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172691096 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.4172691096
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.3240126784
Short name T128
Test name
Test status
Simulation time 43488024049 ps
CPU time 15.92 seconds
Started Apr 02 12:24:15 PM PDT 24
Finished Apr 02 12:24:31 PM PDT 24
Peak memory 183332 kb
Host smart-fac12854-999b-4e94-aad5-f2607dbe0ac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240126784 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.3240126784
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.1429081089
Short name T119
Test name
Test status
Simulation time 493882384 ps
CPU time 1.26 seconds
Started Apr 02 12:24:11 PM PDT 24
Finished Apr 02 12:24:12 PM PDT 24
Peak memory 183192 kb
Host smart-3c34fafa-dbdb-43b7-9c18-c41e1dc9bb14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429081089 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.1429081089
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.3135456305
Short name T159
Test name
Test status
Simulation time 224959688313 ps
CPU time 66.08 seconds
Started Apr 02 12:24:22 PM PDT 24
Finished Apr 02 12:25:28 PM PDT 24
Peak memory 194236 kb
Host smart-6f8f3689-f1a5-48cb-b203-3cb974ca3f73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135456305 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_
all.3135456305
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_jump.4169485746
Short name T79
Test name
Test status
Simulation time 351512323 ps
CPU time 0.97 seconds
Started Apr 02 12:24:21 PM PDT 24
Finished Apr 02 12:24:22 PM PDT 24
Peak memory 183260 kb
Host smart-dea424dd-9289-4346-8fee-703404bc9d68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169485746 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.4169485746
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.1423329526
Short name T169
Test name
Test status
Simulation time 23135838231 ps
CPU time 8.05 seconds
Started Apr 02 12:24:19 PM PDT 24
Finished Apr 02 12:24:27 PM PDT 24
Peak memory 191488 kb
Host smart-c0137332-bd8c-4203-a3c2-a350cdbc3480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423329526 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.1423329526
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.3075089509
Short name T96
Test name
Test status
Simulation time 618274073 ps
CPU time 1.33 seconds
Started Apr 02 12:24:22 PM PDT 24
Finished Apr 02 12:24:24 PM PDT 24
Peak memory 183244 kb
Host smart-8caabb3d-98fd-4c7c-99a4-bf358e20fc3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075089509 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.3075089509
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.2513020506
Short name T207
Test name
Test status
Simulation time 213241708902 ps
CPU time 345.42 seconds
Started Apr 02 12:24:32 PM PDT 24
Finished Apr 02 12:30:18 PM PDT 24
Peak memory 193760 kb
Host smart-e7457b79-1d4e-4050-af90-846bb09e1502
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513020506 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_
all.2513020506
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.1458046069
Short name T116
Test name
Test status
Simulation time 76011397832 ps
CPU time 340.27 seconds
Started Apr 02 12:24:19 PM PDT 24
Finished Apr 02 12:29:59 PM PDT 24
Peak memory 206440 kb
Host smart-0e888225-579b-4664-a822-947b0673e197
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458046069 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.1458046069
Directory /workspace/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.aon_timer_jump.2753785571
Short name T9
Test name
Test status
Simulation time 438889870 ps
CPU time 0.75 seconds
Started Apr 02 12:24:18 PM PDT 24
Finished Apr 02 12:24:19 PM PDT 24
Peak memory 183248 kb
Host smart-16c3442a-a50c-4df1-a70b-0e4cd01b7e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753785571 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.2753785571
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.4040057715
Short name T63
Test name
Test status
Simulation time 35559063566 ps
CPU time 12.82 seconds
Started Apr 02 12:24:21 PM PDT 24
Finished Apr 02 12:24:33 PM PDT 24
Peak memory 183272 kb
Host smart-b8531ea7-d75f-4560-a8f6-dfbb288120d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040057715 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.4040057715
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.2510149356
Short name T124
Test name
Test status
Simulation time 602445482 ps
CPU time 1.14 seconds
Started Apr 02 12:24:22 PM PDT 24
Finished Apr 02 12:24:24 PM PDT 24
Peak memory 183236 kb
Host smart-4ef19744-f5d3-4605-b13a-ef0b641af089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510149356 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.2510149356
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.4051010068
Short name T257
Test name
Test status
Simulation time 95994299933 ps
CPU time 71.84 seconds
Started Apr 02 12:24:18 PM PDT 24
Finished Apr 02 12:25:30 PM PDT 24
Peak memory 193716 kb
Host smart-a6065ce2-e69e-44f4-8e02-5b44664be887
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051010068 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_
all.4051010068
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.2919584254
Short name T39
Test name
Test status
Simulation time 22536428813 ps
CPU time 160.3 seconds
Started Apr 02 12:24:20 PM PDT 24
Finished Apr 02 12:27:01 PM PDT 24
Peak memory 198116 kb
Host smart-5a7648fd-b2e7-4c04-88f0-edf0f1bfe95f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919584254 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.2919584254
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.aon_timer_jump.187702779
Short name T129
Test name
Test status
Simulation time 392772039 ps
CPU time 1.14 seconds
Started Apr 02 12:24:16 PM PDT 24
Finished Apr 02 12:24:17 PM PDT 24
Peak memory 183252 kb
Host smart-2afd1103-2884-4577-a09a-abca9fb85580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187702779 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.187702779
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.3312471711
Short name T151
Test name
Test status
Simulation time 24181860374 ps
CPU time 7.07 seconds
Started Apr 02 12:24:16 PM PDT 24
Finished Apr 02 12:24:23 PM PDT 24
Peak memory 183304 kb
Host smart-263a53d3-3c7c-4d93-bee0-f716d8254853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312471711 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.3312471711
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.1808831609
Short name T26
Test name
Test status
Simulation time 406931257 ps
CPU time 0.68 seconds
Started Apr 02 12:24:21 PM PDT 24
Finished Apr 02 12:24:22 PM PDT 24
Peak memory 183140 kb
Host smart-f71b0e52-7e31-49c3-88c7-4986c74eb9d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808831609 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.1808831609
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.2947748168
Short name T84
Test name
Test status
Simulation time 97463627838 ps
CPU time 145.06 seconds
Started Apr 02 12:24:16 PM PDT 24
Finished Apr 02 12:26:41 PM PDT 24
Peak memory 183296 kb
Host smart-d6a26aca-9675-40ed-bca4-5648c34ed01a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947748168 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_
all.2947748168
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.475399580
Short name T40
Test name
Test status
Simulation time 45218217076 ps
CPU time 224.81 seconds
Started Apr 02 12:24:22 PM PDT 24
Finished Apr 02 12:28:07 PM PDT 24
Peak memory 198212 kb
Host smart-ebc67fae-f443-440a-a3d3-5c5d830d4b0d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475399580 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand_reset.475399580
Directory /workspace/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.aon_timer_jump.1283641242
Short name T112
Test name
Test status
Simulation time 487477134 ps
CPU time 1.34 seconds
Started Apr 02 12:24:18 PM PDT 24
Finished Apr 02 12:24:19 PM PDT 24
Peak memory 183220 kb
Host smart-3d3854b2-0794-4a73-8758-a62388a826f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283641242 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.1283641242
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.3707407596
Short name T126
Test name
Test status
Simulation time 8684467094 ps
CPU time 14.05 seconds
Started Apr 02 12:24:21 PM PDT 24
Finished Apr 02 12:24:36 PM PDT 24
Peak memory 183276 kb
Host smart-7d49442f-b6bb-4326-8add-2c68f8c59dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707407596 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.3707407596
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.4135044008
Short name T215
Test name
Test status
Simulation time 552262469 ps
CPU time 0.7 seconds
Started Apr 02 12:24:19 PM PDT 24
Finished Apr 02 12:24:20 PM PDT 24
Peak memory 183196 kb
Host smart-d7a2bc74-9c43-482e-a2b0-ab3f23ef0816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135044008 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.4135044008
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.2331645078
Short name T138
Test name
Test status
Simulation time 66728823135 ps
CPU time 94.73 seconds
Started Apr 02 12:24:36 PM PDT 24
Finished Apr 02 12:26:11 PM PDT 24
Peak memory 193704 kb
Host smart-4ef73c0e-6b4f-456e-9c8b-c3d2c638a324
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331645078 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_
all.2331645078
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.2427561341
Short name T36
Test name
Test status
Simulation time 52074685688 ps
CPU time 449.85 seconds
Started Apr 02 12:24:18 PM PDT 24
Finished Apr 02 12:31:48 PM PDT 24
Peak memory 198200 kb
Host smart-be665a2a-1e30-4592-8d6c-4fda3a6b817d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427561341 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.2427561341
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_jump.3397872006
Short name T204
Test name
Test status
Simulation time 590474908 ps
CPU time 1.43 seconds
Started Apr 02 12:24:54 PM PDT 24
Finished Apr 02 12:24:56 PM PDT 24
Peak memory 183184 kb
Host smart-7de61eac-7f2f-49c5-af3b-7504b841d559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397872006 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.3397872006
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.3341334303
Short name T20
Test name
Test status
Simulation time 20180119420 ps
CPU time 8.36 seconds
Started Apr 02 12:24:16 PM PDT 24
Finished Apr 02 12:24:25 PM PDT 24
Peak memory 183364 kb
Host smart-e0902325-49ce-47b7-b509-b202f535485a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341334303 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.3341334303
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.1287510418
Short name T17
Test name
Test status
Simulation time 7560930400 ps
CPU time 12.16 seconds
Started Apr 02 12:23:52 PM PDT 24
Finished Apr 02 12:24:04 PM PDT 24
Peak memory 215000 kb
Host smart-d2293442-c51c-4532-b04c-8f256a6fb247
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287510418 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.1287510418
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.4126995115
Short name T214
Test name
Test status
Simulation time 594588530 ps
CPU time 0.73 seconds
Started Apr 02 12:24:10 PM PDT 24
Finished Apr 02 12:24:11 PM PDT 24
Peak memory 183316 kb
Host smart-b1c65ffb-a859-4573-adb3-d41ea9faf0d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126995115 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.4126995115
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.1804450010
Short name T217
Test name
Test status
Simulation time 56649833965 ps
CPU time 89.72 seconds
Started Apr 02 12:24:03 PM PDT 24
Finished Apr 02 12:25:32 PM PDT 24
Peak memory 192932 kb
Host smart-3c3016a7-87b4-4765-9e37-f0596300c112
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804450010 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_a
ll.1804450010
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.1760966105
Short name T69
Test name
Test status
Simulation time 178227734535 ps
CPU time 1103.2 seconds
Started Apr 02 12:24:14 PM PDT 24
Finished Apr 02 12:42:37 PM PDT 24
Peak memory 204260 kb
Host smart-4c9ee1b9-1a35-484a-98f9-0d21c57a9c85
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760966105 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.1760966105
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.aon_timer_jump.2419881290
Short name T43
Test name
Test status
Simulation time 497978438 ps
CPU time 1.35 seconds
Started Apr 02 12:24:20 PM PDT 24
Finished Apr 02 12:24:22 PM PDT 24
Peak memory 183220 kb
Host smart-0e17001d-be92-4fb5-8300-79e8d4cc78b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419881290 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.2419881290
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.3638210060
Short name T12
Test name
Test status
Simulation time 5653026877 ps
CPU time 9.65 seconds
Started Apr 02 12:24:16 PM PDT 24
Finished Apr 02 12:24:26 PM PDT 24
Peak memory 183340 kb
Host smart-3bfa1f08-f18d-409a-851a-72879aa63dd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638210060 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.3638210060
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.3670043609
Short name T118
Test name
Test status
Simulation time 455718456 ps
CPU time 0.63 seconds
Started Apr 02 12:24:22 PM PDT 24
Finished Apr 02 12:24:27 PM PDT 24
Peak memory 183216 kb
Host smart-d2b93c2d-6f87-4f94-89f3-fc7c86e8145e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670043609 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.3670043609
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.3584216426
Short name T113
Test name
Test status
Simulation time 3804478965 ps
CPU time 3.77 seconds
Started Apr 02 12:24:21 PM PDT 24
Finished Apr 02 12:24:24 PM PDT 24
Peak memory 193880 kb
Host smart-b2857738-baaa-46f6-835f-50a519b75a6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584216426 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_
all.3584216426
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.112195348
Short name T67
Test name
Test status
Simulation time 379849100918 ps
CPU time 505.01 seconds
Started Apr 02 12:24:21 PM PDT 24
Finished Apr 02 12:32:47 PM PDT 24
Peak memory 198208 kb
Host smart-6599035d-8f2a-4c62-9a67-524824180181
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112195348 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.112195348
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.aon_timer_jump.2974498314
Short name T157
Test name
Test status
Simulation time 626299840 ps
CPU time 0.99 seconds
Started Apr 02 12:24:22 PM PDT 24
Finished Apr 02 12:24:23 PM PDT 24
Peak memory 183228 kb
Host smart-a3835da1-5c1b-4e62-8bdb-4475a12f0a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974498314 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.2974498314
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.163705179
Short name T25
Test name
Test status
Simulation time 53357156362 ps
CPU time 21.09 seconds
Started Apr 02 12:24:21 PM PDT 24
Finished Apr 02 12:24:42 PM PDT 24
Peak memory 183276 kb
Host smart-f9ad846d-d103-4ae9-be6e-99f3bff7812b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163705179 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.163705179
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.817446324
Short name T220
Test name
Test status
Simulation time 527250904 ps
CPU time 0.63 seconds
Started Apr 02 12:24:51 PM PDT 24
Finished Apr 02 12:24:52 PM PDT 24
Peak memory 183224 kb
Host smart-89564506-4bf3-4071-91b2-c3c2c5713bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817446324 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.817446324
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.60279967
Short name T186
Test name
Test status
Simulation time 290896385888 ps
CPU time 397.78 seconds
Started Apr 02 12:24:18 PM PDT 24
Finished Apr 02 12:30:56 PM PDT 24
Peak memory 194720 kb
Host smart-bf0d4615-1157-465e-b2b1-c96dd49fa9ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60279967 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_al
l.60279967
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.1245923720
Short name T73
Test name
Test status
Simulation time 3116630678 ps
CPU time 17.82 seconds
Started Apr 02 12:24:22 PM PDT 24
Finished Apr 02 12:24:40 PM PDT 24
Peak memory 198160 kb
Host smart-8cd89774-352c-4490-86a8-1d043cc3ed6b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245923720 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.1245923720
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.aon_timer_jump.73199836
Short name T168
Test name
Test status
Simulation time 516976975 ps
CPU time 1.22 seconds
Started Apr 02 12:24:25 PM PDT 24
Finished Apr 02 12:24:26 PM PDT 24
Peak memory 183224 kb
Host smart-05530d17-d333-489c-b7e9-97308439ebfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73199836 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.73199836
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.2247795060
Short name T206
Test name
Test status
Simulation time 53989733255 ps
CPU time 85.19 seconds
Started Apr 02 12:24:23 PM PDT 24
Finished Apr 02 12:25:48 PM PDT 24
Peak memory 183284 kb
Host smart-22036e54-bf5b-47a4-8c47-25d0bf52dcf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247795060 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.2247795060
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.1203985972
Short name T174
Test name
Test status
Simulation time 477601028 ps
CPU time 1.25 seconds
Started Apr 02 12:24:23 PM PDT 24
Finished Apr 02 12:24:29 PM PDT 24
Peak memory 183364 kb
Host smart-70e16115-ea21-4991-bae9-7109eea954a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203985972 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.1203985972
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.4218702351
Short name T259
Test name
Test status
Simulation time 142128365019 ps
CPU time 52.79 seconds
Started Apr 02 12:24:25 PM PDT 24
Finished Apr 02 12:25:18 PM PDT 24
Peak memory 194876 kb
Host smart-46eff8fb-8fab-4c04-b72a-2b06867a0c1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218702351 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_
all.4218702351
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_jump.2786093781
Short name T235
Test name
Test status
Simulation time 534285682 ps
CPU time 0.71 seconds
Started Apr 02 12:24:24 PM PDT 24
Finished Apr 02 12:24:25 PM PDT 24
Peak memory 183228 kb
Host smart-438ac7a6-2c93-4397-b82a-3447d0b7a343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786093781 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.2786093781
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.2125087396
Short name T179
Test name
Test status
Simulation time 33749638723 ps
CPU time 25.65 seconds
Started Apr 02 12:24:54 PM PDT 24
Finished Apr 02 12:25:19 PM PDT 24
Peak memory 191504 kb
Host smart-68438f16-9cac-44b3-bdea-a86aa773729a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125087396 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.2125087396
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.231579221
Short name T198
Test name
Test status
Simulation time 447939258 ps
CPU time 0.94 seconds
Started Apr 02 12:24:34 PM PDT 24
Finished Apr 02 12:24:35 PM PDT 24
Peak memory 183220 kb
Host smart-dcea5e83-3ec4-4b40-ae39-12ff83547406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231579221 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.231579221
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.325158424
Short name T27
Test name
Test status
Simulation time 120918689240 ps
CPU time 93.02 seconds
Started Apr 02 12:24:23 PM PDT 24
Finished Apr 02 12:25:56 PM PDT 24
Peak memory 194824 kb
Host smart-35f0245e-f4b1-435a-abe9-1a134ca09fe0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325158424 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_a
ll.325158424
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_jump.4261753885
Short name T108
Test name
Test status
Simulation time 504863270 ps
CPU time 0.78 seconds
Started Apr 02 12:24:48 PM PDT 24
Finished Apr 02 12:24:48 PM PDT 24
Peak memory 183228 kb
Host smart-a104153d-93b4-4d07-8c5b-fb07a9a14f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261753885 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.4261753885
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.3253412973
Short name T99
Test name
Test status
Simulation time 38604487472 ps
CPU time 52.84 seconds
Started Apr 02 12:24:24 PM PDT 24
Finished Apr 02 12:25:17 PM PDT 24
Peak memory 191628 kb
Host smart-30913327-a6b2-4011-a780-c80edd643a2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253412973 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.3253412973
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.308479747
Short name T245
Test name
Test status
Simulation time 552086115 ps
CPU time 0.71 seconds
Started Apr 02 12:24:21 PM PDT 24
Finished Apr 02 12:24:22 PM PDT 24
Peak memory 183192 kb
Host smart-1d71e6ca-cbba-4be4-9e7b-70224c2b9663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308479747 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.308479747
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.241874537
Short name T2
Test name
Test status
Simulation time 118792770433 ps
CPU time 49.38 seconds
Started Apr 02 12:24:31 PM PDT 24
Finished Apr 02 12:25:20 PM PDT 24
Peak memory 183328 kb
Host smart-7702f0d6-01de-4b09-bd25-e92899e6d098
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241874537 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_a
ll.241874537
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.1158223699
Short name T7
Test name
Test status
Simulation time 205298494677 ps
CPU time 170.89 seconds
Started Apr 02 12:24:23 PM PDT 24
Finished Apr 02 12:27:14 PM PDT 24
Peak memory 198104 kb
Host smart-332dd7c9-84f9-4ac6-a7a6-77d80b4f6a69
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158223699 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.1158223699
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.aon_timer_jump.3703712601
Short name T120
Test name
Test status
Simulation time 497135031 ps
CPU time 0.72 seconds
Started Apr 02 12:24:22 PM PDT 24
Finished Apr 02 12:24:23 PM PDT 24
Peak memory 183228 kb
Host smart-fc1d1399-0acd-4de4-a374-10f3c38a5192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703712601 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.3703712601
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.3002694546
Short name T165
Test name
Test status
Simulation time 18040869565 ps
CPU time 13.68 seconds
Started Apr 02 12:24:23 PM PDT 24
Finished Apr 02 12:24:37 PM PDT 24
Peak memory 183284 kb
Host smart-59e5c7cf-0ba1-4e66-a34c-ab26973ba78e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002694546 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.3002694546
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.1428936362
Short name T111
Test name
Test status
Simulation time 440176200 ps
CPU time 0.75 seconds
Started Apr 02 12:24:43 PM PDT 24
Finished Apr 02 12:24:44 PM PDT 24
Peak memory 183236 kb
Host smart-d5e4abb9-ca83-4fc2-88d5-59b5df8c6db4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428936362 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.1428936362
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.996105090
Short name T139
Test name
Test status
Simulation time 135251956593 ps
CPU time 106.97 seconds
Started Apr 02 12:24:27 PM PDT 24
Finished Apr 02 12:26:15 PM PDT 24
Peak memory 183468 kb
Host smart-ca68dc65-2fde-45b7-8217-cd7532c2222e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996105090 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_a
ll.996105090
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.3520480374
Short name T260
Test name
Test status
Simulation time 141906784291 ps
CPU time 306.32 seconds
Started Apr 02 12:24:23 PM PDT 24
Finished Apr 02 12:29:29 PM PDT 24
Peak memory 198144 kb
Host smart-5e27c7f3-463e-46ff-a41a-190f94a03ccc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520480374 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.3520480374
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.aon_timer_jump.1481817015
Short name T170
Test name
Test status
Simulation time 362402244 ps
CPU time 1.23 seconds
Started Apr 02 12:24:18 PM PDT 24
Finished Apr 02 12:24:20 PM PDT 24
Peak memory 183208 kb
Host smart-3ae8ec1d-7d81-4815-9c06-27633d13fa6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481817015 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.1481817015
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.1914120275
Short name T172
Test name
Test status
Simulation time 21202433644 ps
CPU time 30.33 seconds
Started Apr 02 12:24:17 PM PDT 24
Finished Apr 02 12:24:48 PM PDT 24
Peak memory 191516 kb
Host smart-9b143bb4-eecb-40b2-ae97-a0a604c2c6ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914120275 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.1914120275
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.3116774692
Short name T264
Test name
Test status
Simulation time 375145889 ps
CPU time 1.12 seconds
Started Apr 02 12:24:20 PM PDT 24
Finished Apr 02 12:24:22 PM PDT 24
Peak memory 183180 kb
Host smart-d2489d20-78d9-45a4-bfee-bfce12668834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116774692 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.3116774692
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.1868703931
Short name T213
Test name
Test status
Simulation time 5001999293 ps
CPU time 4.04 seconds
Started Apr 02 12:24:50 PM PDT 24
Finished Apr 02 12:24:54 PM PDT 24
Peak memory 183296 kb
Host smart-97880cdf-3298-4371-a138-a09abd55e544
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868703931 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_
all.1868703931
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_jump.3453198947
Short name T253
Test name
Test status
Simulation time 577800403 ps
CPU time 0.61 seconds
Started Apr 02 12:24:23 PM PDT 24
Finished Apr 02 12:24:24 PM PDT 24
Peak memory 183256 kb
Host smart-613a2338-64a6-424a-8ac9-70a05a3bf335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453198947 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.3453198947
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.3658617755
Short name T142
Test name
Test status
Simulation time 10244348858 ps
CPU time 4.57 seconds
Started Apr 02 12:25:09 PM PDT 24
Finished Apr 02 12:25:14 PM PDT 24
Peak memory 183304 kb
Host smart-bc655ee9-98ee-4759-8af6-80461afa8366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658617755 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.3658617755
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.782942006
Short name T163
Test name
Test status
Simulation time 342244609 ps
CPU time 1.04 seconds
Started Apr 02 12:24:20 PM PDT 24
Finished Apr 02 12:24:21 PM PDT 24
Peak memory 183172 kb
Host smart-28620109-41e5-4fe1-bd66-a1fff937922e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782942006 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.782942006
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.3474849826
Short name T247
Test name
Test status
Simulation time 234021184540 ps
CPU time 53.38 seconds
Started Apr 02 12:24:22 PM PDT 24
Finished Apr 02 12:25:15 PM PDT 24
Peak memory 195124 kb
Host smart-99b623b7-1873-4383-8428-737c108ca5d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474849826 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_
all.3474849826
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.963873494
Short name T192
Test name
Test status
Simulation time 6342009487 ps
CPU time 18.19 seconds
Started Apr 02 12:24:19 PM PDT 24
Finished Apr 02 12:24:37 PM PDT 24
Peak memory 198152 kb
Host smart-3c28e9df-b2d9-4544-b1d8-64c46794e05b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963873494 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.963873494
Directory /workspace/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_jump.76382024
Short name T238
Test name
Test status
Simulation time 465072479 ps
CPU time 0.73 seconds
Started Apr 02 12:24:23 PM PDT 24
Finished Apr 02 12:24:24 PM PDT 24
Peak memory 183232 kb
Host smart-dcab2e0e-3e3d-4b57-9f29-fc2bf384649c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76382024 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.76382024
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.2918108678
Short name T188
Test name
Test status
Simulation time 11582925343 ps
CPU time 4.26 seconds
Started Apr 02 12:24:32 PM PDT 24
Finished Apr 02 12:24:36 PM PDT 24
Peak memory 191500 kb
Host smart-4cc0816a-af50-4775-926b-6d9262b4c959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918108678 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.2918108678
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.2382249502
Short name T8
Test name
Test status
Simulation time 351605477 ps
CPU time 1.03 seconds
Started Apr 02 12:25:01 PM PDT 24
Finished Apr 02 12:25:02 PM PDT 24
Peak memory 183236 kb
Host smart-f118bac9-11ce-482b-96d0-e5b13404031b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382249502 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.2382249502
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.3390312731
Short name T150
Test name
Test status
Simulation time 163206126067 ps
CPU time 29.93 seconds
Started Apr 02 12:24:24 PM PDT 24
Finished Apr 02 12:24:54 PM PDT 24
Peak memory 183316 kb
Host smart-65b5bc46-1479-4bdc-b438-ef50ae48a903
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390312731 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_
all.3390312731
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.1214936122
Short name T3
Test name
Test status
Simulation time 70395182815 ps
CPU time 800.31 seconds
Started Apr 02 12:24:45 PM PDT 24
Finished Apr 02 12:38:06 PM PDT 24
Peak memory 200964 kb
Host smart-2dec2f81-8bea-4ca4-8c2b-ba6ad802e0a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214936122 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.1214936122
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.aon_timer_jump.56630280
Short name T10
Test name
Test status
Simulation time 431235927 ps
CPU time 0.71 seconds
Started Apr 02 12:24:21 PM PDT 24
Finished Apr 02 12:24:22 PM PDT 24
Peak memory 183228 kb
Host smart-ccb5d240-0476-4a3a-a59a-0e75c9617a61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56630280 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.56630280
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.2408967207
Short name T242
Test name
Test status
Simulation time 13305875679 ps
CPU time 2.18 seconds
Started Apr 02 12:25:02 PM PDT 24
Finished Apr 02 12:25:04 PM PDT 24
Peak memory 191532 kb
Host smart-7a0809d1-5386-43e6-b2e1-10a4d840a3c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408967207 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.2408967207
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.1604910401
Short name T265
Test name
Test status
Simulation time 512163463 ps
CPU time 0.72 seconds
Started Apr 02 12:24:22 PM PDT 24
Finished Apr 02 12:24:23 PM PDT 24
Peak memory 183168 kb
Host smart-bbbe2608-a79c-4ca7-969d-91d3a2c614fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604910401 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.1604910401
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.84421343
Short name T86
Test name
Test status
Simulation time 122247872532 ps
CPU time 46.72 seconds
Started Apr 02 12:24:20 PM PDT 24
Finished Apr 02 12:25:07 PM PDT 24
Peak memory 183484 kb
Host smart-73c977ed-0fa3-47f7-8ad0-6db90b735030
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84421343 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_al
l.84421343
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_jump.3577533774
Short name T196
Test name
Test status
Simulation time 406026961 ps
CPU time 0.66 seconds
Started Apr 02 12:24:18 PM PDT 24
Finished Apr 02 12:24:19 PM PDT 24
Peak memory 183232 kb
Host smart-04156696-dab1-49fb-ae30-e17a99865801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577533774 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.3577533774
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.58712573
Short name T64
Test name
Test status
Simulation time 17895492021 ps
CPU time 3.96 seconds
Started Apr 02 12:24:13 PM PDT 24
Finished Apr 02 12:24:17 PM PDT 24
Peak memory 191508 kb
Host smart-18e4b241-1af0-4b61-8ae3-ec4f26d248a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58712573 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.58712573
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.1874090001
Short name T202
Test name
Test status
Simulation time 403318018 ps
CPU time 1.07 seconds
Started Apr 02 12:24:00 PM PDT 24
Finished Apr 02 12:24:01 PM PDT 24
Peak memory 183244 kb
Host smart-ab1069b1-1f55-41e6-b200-150153e9ca4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874090001 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.1874090001
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.526201160
Short name T201
Test name
Test status
Simulation time 111660416652 ps
CPU time 171.12 seconds
Started Apr 02 12:24:05 PM PDT 24
Finished Apr 02 12:26:56 PM PDT 24
Peak memory 194096 kb
Host smart-ddcaad6b-9943-4ada-bb25-b42f2c33af78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526201160 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_al
l.526201160
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.2611845840
Short name T70
Test name
Test status
Simulation time 313111704060 ps
CPU time 626.36 seconds
Started Apr 02 12:24:02 PM PDT 24
Finished Apr 02 12:34:28 PM PDT 24
Peak memory 199232 kb
Host smart-b44b615d-b3bd-434a-befd-28a3bf9f0ec6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611845840 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.2611845840
Directory /workspace/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.aon_timer_jump.3231644073
Short name T251
Test name
Test status
Simulation time 457414756 ps
CPU time 0.68 seconds
Started Apr 02 12:23:55 PM PDT 24
Finished Apr 02 12:23:56 PM PDT 24
Peak memory 183252 kb
Host smart-3a18e75e-6a38-4c1f-bac6-68dc2afdadad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231644073 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.3231644073
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.1820283118
Short name T203
Test name
Test status
Simulation time 60263905790 ps
CPU time 21.59 seconds
Started Apr 02 12:24:18 PM PDT 24
Finished Apr 02 12:24:40 PM PDT 24
Peak memory 183304 kb
Host smart-653c7cb7-de4b-419b-9c67-8cd7680a54de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820283118 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.1820283118
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.3252825527
Short name T80
Test name
Test status
Simulation time 527361373 ps
CPU time 0.76 seconds
Started Apr 02 12:24:07 PM PDT 24
Finished Apr 02 12:24:08 PM PDT 24
Peak memory 183236 kb
Host smart-718fbb34-ad61-43ec-812e-a72734361674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252825527 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.3252825527
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.1645581456
Short name T237
Test name
Test status
Simulation time 51872140619 ps
CPU time 19.93 seconds
Started Apr 02 12:24:17 PM PDT 24
Finished Apr 02 12:24:37 PM PDT 24
Peak memory 193852 kb
Host smart-e8d9a522-77e5-495b-857e-5ad835c9039d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645581456 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_a
ll.1645581456
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.3759831178
Short name T72
Test name
Test status
Simulation time 137298780593 ps
CPU time 241.95 seconds
Started Apr 02 12:24:03 PM PDT 24
Finished Apr 02 12:28:05 PM PDT 24
Peak memory 198032 kb
Host smart-ed60fe73-4f2d-4842-9b5a-949f616e458d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759831178 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.3759831178
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.aon_timer_jump.2302852198
Short name T225
Test name
Test status
Simulation time 595294213 ps
CPU time 0.84 seconds
Started Apr 02 12:24:09 PM PDT 24
Finished Apr 02 12:24:10 PM PDT 24
Peak memory 183352 kb
Host smart-f2420bd1-4e25-4c3b-aa57-12c844ab405c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302852198 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.2302852198
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.2321838075
Short name T171
Test name
Test status
Simulation time 59109705564 ps
CPU time 23.33 seconds
Started Apr 02 12:24:01 PM PDT 24
Finished Apr 02 12:24:24 PM PDT 24
Peak memory 183304 kb
Host smart-a0792dc2-61a6-429f-ac26-adaaf32d8168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321838075 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.2321838075
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.2934864454
Short name T152
Test name
Test status
Simulation time 514970061 ps
CPU time 1.2 seconds
Started Apr 02 12:24:18 PM PDT 24
Finished Apr 02 12:24:19 PM PDT 24
Peak memory 183188 kb
Host smart-4d94bcb2-e098-4882-9f56-cc8cd4936023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934864454 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.2934864454
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.2149938592
Short name T236
Test name
Test status
Simulation time 213126566384 ps
CPU time 45.65 seconds
Started Apr 02 12:23:57 PM PDT 24
Finished Apr 02 12:24:43 PM PDT 24
Peak memory 183264 kb
Host smart-ed855126-2e55-4358-a763-4382de774f38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149938592 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_a
ll.2149938592
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_jump.3931575200
Short name T137
Test name
Test status
Simulation time 454699241 ps
CPU time 1.23 seconds
Started Apr 02 12:24:11 PM PDT 24
Finished Apr 02 12:24:12 PM PDT 24
Peak memory 183324 kb
Host smart-5a761edc-e688-47c5-a714-f149c8fc68e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931575200 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.3931575200
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.4247259824
Short name T234
Test name
Test status
Simulation time 37772502186 ps
CPU time 13.41 seconds
Started Apr 02 12:24:13 PM PDT 24
Finished Apr 02 12:24:27 PM PDT 24
Peak memory 183432 kb
Host smart-a3d0c726-da59-4eb7-a626-610475d2a95a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247259824 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.4247259824
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.3762892579
Short name T218
Test name
Test status
Simulation time 518313958 ps
CPU time 1.39 seconds
Started Apr 02 12:24:13 PM PDT 24
Finished Apr 02 12:24:15 PM PDT 24
Peak memory 183248 kb
Host smart-0f0d9f29-fc39-4824-9118-bfdd7e1dd857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762892579 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.3762892579
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.2243932802
Short name T144
Test name
Test status
Simulation time 264795920856 ps
CPU time 202.87 seconds
Started Apr 02 12:24:00 PM PDT 24
Finished Apr 02 12:27:23 PM PDT 24
Peak memory 183232 kb
Host smart-53365bf0-9f84-4a3f-bed3-17a3b721f37a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243932802 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_a
ll.2243932802
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.896194295
Short name T75
Test name
Test status
Simulation time 42713005307 ps
CPU time 75.14 seconds
Started Apr 02 12:24:03 PM PDT 24
Finished Apr 02 12:25:18 PM PDT 24
Peak memory 198208 kb
Host smart-ccc70890-dd54-41c7-82e2-ca7510a14e41
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896194295 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.896194295
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.aon_timer_jump.2542910518
Short name T270
Test name
Test status
Simulation time 548253142 ps
CPU time 0.94 seconds
Started Apr 02 12:24:18 PM PDT 24
Finished Apr 02 12:24:19 PM PDT 24
Peak memory 183196 kb
Host smart-274a28ce-9037-41eb-8ed7-6d11b863f1e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542910518 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.2542910518
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.1562470678
Short name T158
Test name
Test status
Simulation time 2897138616 ps
CPU time 2.68 seconds
Started Apr 02 12:24:06 PM PDT 24
Finished Apr 02 12:24:09 PM PDT 24
Peak memory 183272 kb
Host smart-2e64e7c9-2527-4387-8b23-a3ee74a23c5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562470678 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.1562470678
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.1264597202
Short name T81
Test name
Test status
Simulation time 587147453 ps
CPU time 0.71 seconds
Started Apr 02 12:24:06 PM PDT 24
Finished Apr 02 12:24:07 PM PDT 24
Peak memory 183240 kb
Host smart-ad10f066-421c-47a1-8623-afa26d820479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264597202 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.1264597202
Directory /workspace/9.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.3560191586
Short name T161
Test name
Test status
Simulation time 83900303588 ps
CPU time 28.54 seconds
Started Apr 02 12:24:05 PM PDT 24
Finished Apr 02 12:24:34 PM PDT 24
Peak memory 191596 kb
Host smart-6e0f804b-db7f-4450-a55c-e5096d86fd6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560191586 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_a
ll.3560191586
Directory /workspace/9.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.700614883
Short name T66
Test name
Test status
Simulation time 42256593624 ps
CPU time 147.02 seconds
Started Apr 02 12:24:09 PM PDT 24
Finished Apr 02 12:26:36 PM PDT 24
Peak memory 198212 kb
Host smart-fc598ca8-9ed6-4880-9140-1e82aa9b0486
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700614883 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.700614883
Directory /workspace/9.aon_timer_stress_all_with_rand_reset/latest
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