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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
92.98 99.25 93.67 100.00 98.40 99.51 67.06


Total test records in report: 420
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T280 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.3768727492 Apr 04 12:29:45 PM PDT 24 Apr 04 12:29:46 PM PDT 24 327941924 ps
T68 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.1147437227 Apr 04 12:29:05 PM PDT 24 Apr 04 12:29:06 PM PDT 24 1130208612 ps
T281 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.632521032 Apr 04 12:29:38 PM PDT 24 Apr 04 12:29:40 PM PDT 24 764119673 ps
T44 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.2787500748 Apr 04 12:28:44 PM PDT 24 Apr 04 12:28:45 PM PDT 24 444153656 ps
T36 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.2029552857 Apr 04 12:27:34 PM PDT 24 Apr 04 12:27:41 PM PDT 24 7888974435 ps
T45 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.3815859761 Apr 04 12:28:35 PM PDT 24 Apr 04 12:28:55 PM PDT 24 7333988625 ps
T282 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.2855693090 Apr 04 12:28:54 PM PDT 24 Apr 04 12:28:55 PM PDT 24 537956249 ps
T69 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.372170424 Apr 04 12:29:08 PM PDT 24 Apr 04 12:29:10 PM PDT 24 3037704010 ps
T283 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.1964436757 Apr 04 12:27:34 PM PDT 24 Apr 04 12:27:36 PM PDT 24 327557348 ps
T70 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.2181738571 Apr 04 12:28:45 PM PDT 24 Apr 04 12:28:48 PM PDT 24 2393979992 ps
T37 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.407675115 Apr 04 12:27:46 PM PDT 24 Apr 04 12:27:49 PM PDT 24 4583054905 ps
T284 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.2317975056 Apr 04 12:28:52 PM PDT 24 Apr 04 12:28:52 PM PDT 24 374909347 ps
T285 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.1851921302 Apr 04 12:28:44 PM PDT 24 Apr 04 12:28:46 PM PDT 24 351935995 ps
T46 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.1213271003 Apr 04 12:27:37 PM PDT 24 Apr 04 12:27:48 PM PDT 24 13953389688 ps
T47 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.4210407627 Apr 04 12:29:03 PM PDT 24 Apr 04 12:29:11 PM PDT 24 7155061618 ps
T286 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.2212189914 Apr 04 12:33:25 PM PDT 24 Apr 04 12:33:26 PM PDT 24 497010736 ps
T287 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.2634015176 Apr 04 12:31:44 PM PDT 24 Apr 04 12:31:45 PM PDT 24 395402989 ps
T288 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.689723747 Apr 04 12:27:37 PM PDT 24 Apr 04 12:27:38 PM PDT 24 322550506 ps
T71 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.3374257942 Apr 04 12:27:56 PM PDT 24 Apr 04 12:27:58 PM PDT 24 513944920 ps
T289 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.2280732091 Apr 04 12:29:49 PM PDT 24 Apr 04 12:29:50 PM PDT 24 371962519 ps
T290 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.732468239 Apr 04 12:28:53 PM PDT 24 Apr 04 12:28:54 PM PDT 24 324083092 ps
T291 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.1358488805 Apr 04 12:28:49 PM PDT 24 Apr 04 12:28:51 PM PDT 24 710255397 ps
T292 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.2320091861 Apr 04 12:28:45 PM PDT 24 Apr 04 12:28:47 PM PDT 24 635753152 ps
T293 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.3252841063 Apr 04 12:27:35 PM PDT 24 Apr 04 12:27:36 PM PDT 24 339336367 ps
T98 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.879355035 Apr 04 12:28:36 PM PDT 24 Apr 04 12:28:43 PM PDT 24 4394817508 ps
T294 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.2399600952 Apr 04 12:27:48 PM PDT 24 Apr 04 12:28:02 PM PDT 24 7850206245 ps
T295 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.3761514715 Apr 04 12:29:19 PM PDT 24 Apr 04 12:29:21 PM PDT 24 502158336 ps
T95 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.3411314382 Apr 04 12:29:06 PM PDT 24 Apr 04 12:29:09 PM PDT 24 4649704571 ps
T296 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.3672214568 Apr 04 12:28:52 PM PDT 24 Apr 04 12:28:53 PM PDT 24 586091893 ps
T297 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.3477996516 Apr 04 12:29:46 PM PDT 24 Apr 04 12:29:58 PM PDT 24 7868795530 ps
T48 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.1445360382 Apr 04 12:29:05 PM PDT 24 Apr 04 12:29:06 PM PDT 24 462545106 ps
T49 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.683053626 Apr 04 12:27:44 PM PDT 24 Apr 04 12:27:45 PM PDT 24 521228362 ps
T298 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.4102591332 Apr 04 12:27:47 PM PDT 24 Apr 04 12:27:47 PM PDT 24 352151012 ps
T72 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.1478178784 Apr 04 12:28:51 PM PDT 24 Apr 04 12:28:53 PM PDT 24 2238247375 ps
T73 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.29466076 Apr 04 12:29:46 PM PDT 24 Apr 04 12:29:47 PM PDT 24 2452254356 ps
T299 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.890037041 Apr 04 12:27:51 PM PDT 24 Apr 04 12:27:52 PM PDT 24 492073162 ps
T50 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.4057242224 Apr 04 12:27:45 PM PDT 24 Apr 04 12:27:46 PM PDT 24 436041396 ps
T300 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.1026488840 Apr 04 12:28:44 PM PDT 24 Apr 04 12:28:46 PM PDT 24 4643603466 ps
T301 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.3780670522 Apr 04 12:29:59 PM PDT 24 Apr 04 12:30:00 PM PDT 24 398009357 ps
T74 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.2032477361 Apr 04 12:28:45 PM PDT 24 Apr 04 12:28:46 PM PDT 24 371333207 ps
T302 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.3379795551 Apr 04 12:27:45 PM PDT 24 Apr 04 12:27:46 PM PDT 24 299934545 ps
T303 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.2784749090 Apr 04 12:29:06 PM PDT 24 Apr 04 12:29:08 PM PDT 24 1260099053 ps
T304 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.3863206590 Apr 04 12:30:02 PM PDT 24 Apr 04 12:30:04 PM PDT 24 1691540215 ps
T51 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.3212411308 Apr 04 12:28:38 PM PDT 24 Apr 04 12:28:40 PM PDT 24 651204926 ps
T305 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.2101254865 Apr 04 12:28:54 PM PDT 24 Apr 04 12:28:56 PM PDT 24 481379909 ps
T306 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.302468407 Apr 04 12:27:41 PM PDT 24 Apr 04 12:27:45 PM PDT 24 1634679582 ps
T307 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.677258779 Apr 04 12:28:19 PM PDT 24 Apr 04 12:28:19 PM PDT 24 401455427 ps
T308 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.32837839 Apr 04 12:29:56 PM PDT 24 Apr 04 12:29:58 PM PDT 24 412045109 ps
T309 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.1839421346 Apr 04 12:28:57 PM PDT 24 Apr 04 12:29:11 PM PDT 24 8224417001 ps
T310 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.1610014461 Apr 04 12:28:57 PM PDT 24 Apr 04 12:28:58 PM PDT 24 405202865 ps
T311 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.1809382386 Apr 04 12:29:18 PM PDT 24 Apr 04 12:29:20 PM PDT 24 1048735872 ps
T312 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.479305212 Apr 04 12:29:10 PM PDT 24 Apr 04 12:29:11 PM PDT 24 474981915 ps
T54 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.180038906 Apr 04 12:28:48 PM PDT 24 Apr 04 12:28:50 PM PDT 24 535376999 ps
T313 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.4239808709 Apr 04 12:27:44 PM PDT 24 Apr 04 12:27:45 PM PDT 24 647964818 ps
T314 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.884349633 Apr 04 12:29:42 PM PDT 24 Apr 04 12:29:44 PM PDT 24 510985547 ps
T55 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.2809786962 Apr 04 12:28:46 PM PDT 24 Apr 04 12:28:47 PM PDT 24 407614171 ps
T315 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.1295221149 Apr 04 12:27:48 PM PDT 24 Apr 04 12:27:49 PM PDT 24 648796614 ps
T67 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.2165270471 Apr 04 12:28:37 PM PDT 24 Apr 04 12:28:39 PM PDT 24 352378768 ps
T316 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.1786137659 Apr 04 12:27:43 PM PDT 24 Apr 04 12:27:58 PM PDT 24 8392270020 ps
T317 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.1591025172 Apr 04 12:28:45 PM PDT 24 Apr 04 12:28:50 PM PDT 24 2882982517 ps
T52 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.855398316 Apr 04 12:27:36 PM PDT 24 Apr 04 12:27:43 PM PDT 24 3801311470 ps
T56 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.1314031649 Apr 04 12:28:16 PM PDT 24 Apr 04 12:28:17 PM PDT 24 466073558 ps
T318 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.804155512 Apr 04 12:27:37 PM PDT 24 Apr 04 12:27:38 PM PDT 24 538005292 ps
T319 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.1090030852 Apr 04 12:28:43 PM PDT 24 Apr 04 12:28:44 PM PDT 24 477111917 ps
T320 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.251343041 Apr 04 12:28:54 PM PDT 24 Apr 04 12:28:58 PM PDT 24 2117766201 ps
T53 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.1999726102 Apr 04 12:27:47 PM PDT 24 Apr 04 12:27:48 PM PDT 24 500692412 ps
T321 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.4199890874 Apr 04 12:28:50 PM PDT 24 Apr 04 12:28:51 PM PDT 24 451620485 ps
T322 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.3735315334 Apr 04 12:28:51 PM PDT 24 Apr 04 12:28:52 PM PDT 24 264655152 ps
T323 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.3502239625 Apr 04 12:28:53 PM PDT 24 Apr 04 12:28:53 PM PDT 24 532684695 ps
T324 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.174563231 Apr 04 12:28:19 PM PDT 24 Apr 04 12:28:20 PM PDT 24 378812308 ps
T325 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.4021044770 Apr 04 12:28:45 PM PDT 24 Apr 04 12:28:46 PM PDT 24 577576777 ps
T96 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.1880183497 Apr 04 12:28:35 PM PDT 24 Apr 04 12:28:37 PM PDT 24 4304675990 ps
T326 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.3677237727 Apr 04 12:29:22 PM PDT 24 Apr 04 12:29:23 PM PDT 24 473325055 ps
T327 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.1401510741 Apr 04 12:27:42 PM PDT 24 Apr 04 12:27:44 PM PDT 24 992380699 ps
T328 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.1808817255 Apr 04 12:28:51 PM PDT 24 Apr 04 12:28:52 PM PDT 24 438573037 ps
T329 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.813737698 Apr 04 12:29:45 PM PDT 24 Apr 04 12:29:46 PM PDT 24 277402470 ps
T330 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.995444332 Apr 04 12:28:41 PM PDT 24 Apr 04 12:28:42 PM PDT 24 1008292343 ps
T331 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.112849151 Apr 04 12:28:45 PM PDT 24 Apr 04 12:28:50 PM PDT 24 4761422043 ps
T332 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.2595225573 Apr 04 12:28:51 PM PDT 24 Apr 04 12:28:52 PM PDT 24 614347263 ps
T333 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.2331982114 Apr 04 12:27:48 PM PDT 24 Apr 04 12:27:51 PM PDT 24 594656940 ps
T334 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.3808703245 Apr 04 12:29:48 PM PDT 24 Apr 04 12:29:49 PM PDT 24 438730696 ps
T335 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.632311385 Apr 04 12:29:22 PM PDT 24 Apr 04 12:29:23 PM PDT 24 479989873 ps
T336 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.3893067996 Apr 04 12:30:03 PM PDT 24 Apr 04 12:30:04 PM PDT 24 406997093 ps
T337 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.323400148 Apr 04 12:28:53 PM PDT 24 Apr 04 12:28:54 PM PDT 24 326196612 ps
T338 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.2768806499 Apr 04 12:29:40 PM PDT 24 Apr 04 12:29:41 PM PDT 24 443308659 ps
T339 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.1998093522 Apr 04 12:29:43 PM PDT 24 Apr 04 12:29:44 PM PDT 24 412406668 ps
T340 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.3198741177 Apr 04 12:27:44 PM PDT 24 Apr 04 12:27:46 PM PDT 24 855229907 ps
T341 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.182626624 Apr 04 12:29:06 PM PDT 24 Apr 04 12:29:07 PM PDT 24 508505098 ps
T342 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.3167321750 Apr 04 12:28:30 PM PDT 24 Apr 04 12:28:31 PM PDT 24 433837776 ps
T343 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.2311735235 Apr 04 12:27:36 PM PDT 24 Apr 04 12:27:37 PM PDT 24 447767162 ps
T344 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.1212722402 Apr 04 12:27:43 PM PDT 24 Apr 04 12:27:44 PM PDT 24 1851904552 ps
T345 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.26509998 Apr 04 12:28:53 PM PDT 24 Apr 04 12:29:02 PM PDT 24 7031019886 ps
T346 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.3990761977 Apr 04 12:28:45 PM PDT 24 Apr 04 12:28:47 PM PDT 24 461721220 ps
T347 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.759565268 Apr 04 12:27:46 PM PDT 24 Apr 04 12:27:49 PM PDT 24 492833464 ps
T348 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.37997859 Apr 04 12:28:53 PM PDT 24 Apr 04 12:28:54 PM PDT 24 404024935 ps
T349 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.1031741424 Apr 04 12:32:04 PM PDT 24 Apr 04 12:32:05 PM PDT 24 329782585 ps
T350 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.4097616094 Apr 04 12:27:36 PM PDT 24 Apr 04 12:27:38 PM PDT 24 523000428 ps
T351 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.2730123213 Apr 04 12:27:42 PM PDT 24 Apr 04 12:27:44 PM PDT 24 578195564 ps
T57 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.941066077 Apr 04 12:29:39 PM PDT 24 Apr 04 12:29:39 PM PDT 24 312798780 ps
T352 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.3906212776 Apr 04 12:31:01 PM PDT 24 Apr 04 12:31:03 PM PDT 24 674206082 ps
T353 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.1433377389 Apr 04 12:29:37 PM PDT 24 Apr 04 12:29:39 PM PDT 24 462673095 ps
T94 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.556477676 Apr 04 12:28:53 PM PDT 24 Apr 04 12:29:06 PM PDT 24 8114870962 ps
T354 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.3350374153 Apr 04 12:29:49 PM PDT 24 Apr 04 12:29:50 PM PDT 24 435255775 ps
T355 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.1924448830 Apr 04 12:27:34 PM PDT 24 Apr 04 12:27:35 PM PDT 24 615861168 ps
T356 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.3586717027 Apr 04 12:29:57 PM PDT 24 Apr 04 12:29:58 PM PDT 24 396318123 ps
T357 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.1745986931 Apr 04 12:28:51 PM PDT 24 Apr 04 12:28:52 PM PDT 24 535468490 ps
T358 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.618998947 Apr 04 12:28:54 PM PDT 24 Apr 04 12:28:57 PM PDT 24 300170754 ps
T359 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.476935427 Apr 04 12:28:52 PM PDT 24 Apr 04 12:28:53 PM PDT 24 300677650 ps
T360 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.2408362069 Apr 04 12:29:23 PM PDT 24 Apr 04 12:29:25 PM PDT 24 421525094 ps
T361 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.2231323265 Apr 04 12:29:39 PM PDT 24 Apr 04 12:29:40 PM PDT 24 415140772 ps
T362 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.3532409346 Apr 04 12:29:21 PM PDT 24 Apr 04 12:29:22 PM PDT 24 465189068 ps
T363 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.1186030411 Apr 04 12:29:18 PM PDT 24 Apr 04 12:29:19 PM PDT 24 353462378 ps
T364 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.1179490785 Apr 04 12:28:18 PM PDT 24 Apr 04 12:28:23 PM PDT 24 2137239478 ps
T365 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.3807764342 Apr 04 12:28:53 PM PDT 24 Apr 04 12:28:54 PM PDT 24 406740686 ps
T366 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.2940719781 Apr 04 12:27:47 PM PDT 24 Apr 04 12:27:48 PM PDT 24 457109132 ps
T367 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.2785474185 Apr 04 12:28:43 PM PDT 24 Apr 04 12:28:44 PM PDT 24 369050140 ps
T368 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.3872363596 Apr 04 12:29:12 PM PDT 24 Apr 04 12:29:13 PM PDT 24 371635180 ps
T369 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.458880674 Apr 04 12:27:26 PM PDT 24 Apr 04 12:27:27 PM PDT 24 516877129 ps
T370 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.1915495312 Apr 04 12:28:51 PM PDT 24 Apr 04 12:28:51 PM PDT 24 289396198 ps
T371 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.1691333891 Apr 04 12:29:49 PM PDT 24 Apr 04 12:29:51 PM PDT 24 406348046 ps
T372 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.4255528678 Apr 04 12:27:46 PM PDT 24 Apr 04 12:27:50 PM PDT 24 2009693677 ps
T373 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.1572890779 Apr 04 12:29:25 PM PDT 24 Apr 04 12:29:30 PM PDT 24 2138273523 ps
T374 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.1575504304 Apr 04 12:27:35 PM PDT 24 Apr 04 12:27:36 PM PDT 24 401085065 ps
T375 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.1545300118 Apr 04 12:29:46 PM PDT 24 Apr 04 12:29:47 PM PDT 24 395420121 ps
T376 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.2842665947 Apr 04 12:29:04 PM PDT 24 Apr 04 12:29:06 PM PDT 24 417474427 ps
T377 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.463271151 Apr 04 12:28:55 PM PDT 24 Apr 04 12:28:57 PM PDT 24 501325089 ps
T378 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.1089805322 Apr 04 12:29:45 PM PDT 24 Apr 04 12:29:46 PM PDT 24 417690927 ps
T379 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.2821011394 Apr 04 12:27:46 PM PDT 24 Apr 04 12:27:48 PM PDT 24 1507938617 ps
T380 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.2700177298 Apr 04 12:27:49 PM PDT 24 Apr 04 12:27:50 PM PDT 24 417756296 ps
T381 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.2669954126 Apr 04 12:28:57 PM PDT 24 Apr 04 12:28:57 PM PDT 24 312978125 ps
T382 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.1279637401 Apr 04 12:27:35 PM PDT 24 Apr 04 12:27:38 PM PDT 24 1024958029 ps
T383 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.1646204166 Apr 04 12:29:23 PM PDT 24 Apr 04 12:29:36 PM PDT 24 8048500074 ps
T384 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.2594325481 Apr 04 12:27:35 PM PDT 24 Apr 04 12:27:36 PM PDT 24 293242915 ps
T385 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.1394170216 Apr 04 12:27:46 PM PDT 24 Apr 04 12:27:48 PM PDT 24 4506141822 ps
T386 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.2165172002 Apr 04 12:27:37 PM PDT 24 Apr 04 12:27:39 PM PDT 24 1737317980 ps
T387 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.2464067788 Apr 04 12:27:43 PM PDT 24 Apr 04 12:27:48 PM PDT 24 4334434858 ps
T388 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.16542954 Apr 04 12:27:41 PM PDT 24 Apr 04 12:27:42 PM PDT 24 488461133 ps
T389 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.3320720442 Apr 04 12:29:49 PM PDT 24 Apr 04 12:29:51 PM PDT 24 473757795 ps
T390 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.1705911080 Apr 04 12:27:44 PM PDT 24 Apr 04 12:27:46 PM PDT 24 655636640 ps
T391 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.2546572483 Apr 04 12:29:39 PM PDT 24 Apr 04 12:29:40 PM PDT 24 408258345 ps
T392 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.331206962 Apr 04 12:28:51 PM PDT 24 Apr 04 12:28:52 PM PDT 24 519482820 ps
T393 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.2193784842 Apr 04 12:28:54 PM PDT 24 Apr 04 12:28:56 PM PDT 24 948402884 ps
T394 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.2778703143 Apr 04 12:29:46 PM PDT 24 Apr 04 12:29:48 PM PDT 24 574772199 ps
T395 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.956255944 Apr 04 12:27:44 PM PDT 24 Apr 04 12:27:47 PM PDT 24 569002363 ps
T396 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.355537490 Apr 04 12:27:48 PM PDT 24 Apr 04 12:27:50 PM PDT 24 1432405951 ps
T397 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.3716464712 Apr 04 12:27:49 PM PDT 24 Apr 04 12:27:53 PM PDT 24 1367675327 ps
T398 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.3249481671 Apr 04 12:28:45 PM PDT 24 Apr 04 12:28:47 PM PDT 24 288950846 ps
T399 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.3427622158 Apr 04 12:28:45 PM PDT 24 Apr 04 12:28:46 PM PDT 24 287370489 ps
T400 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.2797846700 Apr 04 12:28:45 PM PDT 24 Apr 04 12:28:50 PM PDT 24 4786849759 ps
T401 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.1422808754 Apr 04 12:29:25 PM PDT 24 Apr 04 12:29:26 PM PDT 24 442950982 ps
T402 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.3161214718 Apr 04 12:27:45 PM PDT 24 Apr 04 12:27:47 PM PDT 24 589683416 ps
T403 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.961827696 Apr 04 12:27:45 PM PDT 24 Apr 04 12:27:46 PM PDT 24 383150403 ps
T404 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.2732509108 Apr 04 12:28:51 PM PDT 24 Apr 04 12:28:52 PM PDT 24 524063911 ps
T405 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.298232247 Apr 04 12:27:47 PM PDT 24 Apr 04 12:27:48 PM PDT 24 421666510 ps
T406 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.1420504792 Apr 04 12:27:35 PM PDT 24 Apr 04 12:27:36 PM PDT 24 1130626325 ps
T407 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.567980460 Apr 04 12:28:14 PM PDT 24 Apr 04 12:28:15 PM PDT 24 317311479 ps
T408 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.3836754787 Apr 04 12:27:36 PM PDT 24 Apr 04 12:27:37 PM PDT 24 494116872 ps
T409 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.369046940 Apr 04 12:27:46 PM PDT 24 Apr 04 12:27:49 PM PDT 24 4543750142 ps
T410 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.2520439824 Apr 04 12:27:47 PM PDT 24 Apr 04 12:27:51 PM PDT 24 3707914652 ps
T411 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.1881148198 Apr 04 12:29:02 PM PDT 24 Apr 04 12:29:03 PM PDT 24 375967270 ps
T97 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.2105880471 Apr 04 12:27:50 PM PDT 24 Apr 04 12:27:53 PM PDT 24 4503826601 ps
T412 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.4281794559 Apr 04 12:27:35 PM PDT 24 Apr 04 12:27:36 PM PDT 24 419540351 ps
T413 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.1938049207 Apr 04 12:29:38 PM PDT 24 Apr 04 12:29:39 PM PDT 24 335207499 ps
T414 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.3665048475 Apr 04 12:29:04 PM PDT 24 Apr 04 12:29:05 PM PDT 24 348896506 ps
T415 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.2825083170 Apr 04 12:29:45 PM PDT 24 Apr 04 12:29:46 PM PDT 24 393952740 ps
T416 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.1520265001 Apr 04 12:29:38 PM PDT 24 Apr 04 12:29:40 PM PDT 24 477573219 ps
T417 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.10838250 Apr 04 12:28:49 PM PDT 24 Apr 04 12:28:51 PM PDT 24 621978303 ps
T418 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.575843845 Apr 04 12:29:40 PM PDT 24 Apr 04 12:29:41 PM PDT 24 494006513 ps
T419 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.1973608592 Apr 04 12:27:48 PM PDT 24 Apr 04 12:27:49 PM PDT 24 534711731 ps
T420 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.1566273018 Apr 04 12:28:49 PM PDT 24 Apr 04 12:28:50 PM PDT 24 329131799 ps

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.1432928872
Short name T8
Test name
Test status
Simulation time 732293782113 ps
CPU time 476.2 seconds
Started Apr 04 02:48:03 PM PDT 24
Finished Apr 04 02:55:59 PM PDT 24
Peak memory 198340 kb
Host smart-89292294-c7bb-4cde-ab2a-02f32a248e27
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432928872 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.1432928872
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.1122383965
Short name T25
Test name
Test status
Simulation time 65084806354 ps
CPU time 181.29 seconds
Started Apr 04 02:48:09 PM PDT 24
Finished Apr 04 02:51:10 PM PDT 24
Peak memory 198296 kb
Host smart-c38e33bc-412d-4333-8e57-c7c75668bd0f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122383965 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.1122383965
Directory /workspace/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.807408389
Short name T34
Test name
Test status
Simulation time 8378311001 ps
CPU time 13.34 seconds
Started Apr 04 12:30:11 PM PDT 24
Finished Apr 04 12:30:24 PM PDT 24
Peak memory 198060 kb
Host smart-0d54b532-c368-4a53-8774-97c01fd16350
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807408389 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_
intg_err.807408389
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.3824383889
Short name T10
Test name
Test status
Simulation time 177223090774 ps
CPU time 289.09 seconds
Started Apr 04 02:47:52 PM PDT 24
Finished Apr 04 02:52:41 PM PDT 24
Peak memory 198304 kb
Host smart-f8b3a90b-911c-4f84-89bb-2a97fc907c1d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824383889 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.3824383889
Directory /workspace/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.3282593486
Short name T17
Test name
Test status
Simulation time 8374418990 ps
CPU time 5.23 seconds
Started Apr 04 02:47:31 PM PDT 24
Finished Apr 04 02:47:36 PM PDT 24
Peak memory 215088 kb
Host smart-e8f9d45c-125a-4ee2-aeb0-2c880fd2ae8d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282593486 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.3282593486
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.3675211205
Short name T145
Test name
Test status
Simulation time 177772669580 ps
CPU time 666.83 seconds
Started Apr 04 02:47:35 PM PDT 24
Finished Apr 04 02:58:42 PM PDT 24
Peak memory 207724 kb
Host smart-dbe56679-32b8-4b17-baae-47157f9d022d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675211205 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.3675211205
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.2787500748
Short name T44
Test name
Test status
Simulation time 444153656 ps
CPU time 1.22 seconds
Started Apr 04 12:28:44 PM PDT 24
Finished Apr 04 12:28:45 PM PDT 24
Peak memory 183824 kb
Host smart-26bb480c-f39b-4b6f-bd24-1d16f8454ad1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787500748 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.2787500748
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.1424556659
Short name T87
Test name
Test status
Simulation time 503040742236 ps
CPU time 191.67 seconds
Started Apr 04 02:47:32 PM PDT 24
Finished Apr 04 02:50:44 PM PDT 24
Peak memory 191508 kb
Host smart-13b60943-45c9-434b-895f-c2e0029bcebe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424556659 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_a
ll.1424556659
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.2029552857
Short name T36
Test name
Test status
Simulation time 7888974435 ps
CPU time 7.12 seconds
Started Apr 04 12:27:34 PM PDT 24
Finished Apr 04 12:27:41 PM PDT 24
Peak memory 198004 kb
Host smart-e88767b2-2ebb-466f-b432-4ceb44c7e992
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029552857 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl
_intg_err.2029552857
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.2373475782
Short name T80
Test name
Test status
Simulation time 35005676749 ps
CPU time 248.64 seconds
Started Apr 04 02:47:36 PM PDT 24
Finished Apr 04 02:51:45 PM PDT 24
Peak memory 198344 kb
Host smart-6ab3ad9c-059b-4d0a-ad3e-ebc201748e5b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373475782 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.2373475782
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.1880183497
Short name T96
Test name
Test status
Simulation time 4304675990 ps
CPU time 2.17 seconds
Started Apr 04 12:28:35 PM PDT 24
Finished Apr 04 12:28:37 PM PDT 24
Peak memory 196716 kb
Host smart-60fdf50f-21e6-4fa2-887b-95206864c7ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880183497 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_t
l_intg_err.1880183497
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.1575504304
Short name T374
Test name
Test status
Simulation time 401085065 ps
CPU time 0.88 seconds
Started Apr 04 12:27:35 PM PDT 24
Finished Apr 04 12:27:36 PM PDT 24
Peak memory 193216 kb
Host smart-c60c1cc1-60f5-4f89-a587-bca221f592ea
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575504304 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_a
liasing.1575504304
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.1213271003
Short name T46
Test name
Test status
Simulation time 13953389688 ps
CPU time 10.63 seconds
Started Apr 04 12:27:37 PM PDT 24
Finished Apr 04 12:27:48 PM PDT 24
Peak memory 192292 kb
Host smart-00eb4961-e240-41a2-a1ee-6c4d4beefe18
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213271003 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_b
it_bash.1213271003
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.1279637401
Short name T382
Test name
Test status
Simulation time 1024958029 ps
CPU time 2.09 seconds
Started Apr 04 12:27:35 PM PDT 24
Finished Apr 04 12:27:38 PM PDT 24
Peak memory 192768 kb
Host smart-13e29529-c519-46d8-a413-192d61f7dc66
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279637401 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_h
w_reset.1279637401
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.2546572483
Short name T391
Test name
Test status
Simulation time 408258345 ps
CPU time 0.77 seconds
Started Apr 04 12:29:39 PM PDT 24
Finished Apr 04 12:29:40 PM PDT 24
Peak memory 195164 kb
Host smart-e3c2921b-26fb-457c-960c-672022cb5d71
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546572483 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.2546572483
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.804155512
Short name T318
Test name
Test status
Simulation time 538005292 ps
CPU time 0.77 seconds
Started Apr 04 12:27:37 PM PDT 24
Finished Apr 04 12:27:38 PM PDT 24
Peak memory 193300 kb
Host smart-df455da1-e613-45a9-91b5-62ecde313299
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804155512 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.804155512
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.4097616094
Short name T350
Test name
Test status
Simulation time 523000428 ps
CPU time 0.94 seconds
Started Apr 04 12:27:36 PM PDT 24
Finished Apr 04 12:27:38 PM PDT 24
Peak memory 183632 kb
Host smart-9c6c0970-1604-48ad-a9ab-3ee7f965c33e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097616094 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.4097616094
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.4281794559
Short name T412
Test name
Test status
Simulation time 419540351 ps
CPU time 1.17 seconds
Started Apr 04 12:27:35 PM PDT 24
Finished Apr 04 12:27:36 PM PDT 24
Peak memory 183308 kb
Host smart-3f1dc8fd-8db3-4197-b583-b6c56cbc4065
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281794559 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_t
imer_mem_partial_access.4281794559
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.3252841063
Short name T293
Test name
Test status
Simulation time 339336367 ps
CPU time 0.68 seconds
Started Apr 04 12:27:35 PM PDT 24
Finished Apr 04 12:27:36 PM PDT 24
Peak memory 183640 kb
Host smart-e7a80a4e-514a-4b86-9fec-6ddba49b37cc
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252841063 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_w
alk.3252841063
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.302468407
Short name T306
Test name
Test status
Simulation time 1634679582 ps
CPU time 4.36 seconds
Started Apr 04 12:27:41 PM PDT 24
Finished Apr 04 12:27:45 PM PDT 24
Peak memory 193388 kb
Host smart-de6e5a6c-48d3-4173-ac33-b87003c985eb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302468407 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_
timer_same_csr_outstanding.302468407
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.1964436757
Short name T283
Test name
Test status
Simulation time 327557348 ps
CPU time 1.67 seconds
Started Apr 04 12:27:34 PM PDT 24
Finished Apr 04 12:27:36 PM PDT 24
Peak memory 198712 kb
Host smart-25832589-7522-4824-87ce-528bb5852f28
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964436757 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.1964436757
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.1646204166
Short name T383
Test name
Test status
Simulation time 8048500074 ps
CPU time 13.07 seconds
Started Apr 04 12:29:23 PM PDT 24
Finished Apr 04 12:29:36 PM PDT 24
Peak memory 198228 kb
Host smart-656cd1fb-3c06-4375-928f-7a482cc5eb3c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646204166 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl
_intg_err.1646204166
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.458880674
Short name T369
Test name
Test status
Simulation time 516877129 ps
CPU time 1.12 seconds
Started Apr 04 12:27:26 PM PDT 24
Finished Apr 04 12:27:27 PM PDT 24
Peak memory 194188 kb
Host smart-39ede870-a597-41c7-8178-e47f0bf73b52
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458880674 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_al
iasing.458880674
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.855398316
Short name T52
Test name
Test status
Simulation time 3801311470 ps
CPU time 6.82 seconds
Started Apr 04 12:27:36 PM PDT 24
Finished Apr 04 12:27:43 PM PDT 24
Peak memory 191992 kb
Host smart-1641d1bc-522b-45af-ab2e-dadc78a397c0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855398316 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_bi
t_bash.855398316
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.1420504792
Short name T406
Test name
Test status
Simulation time 1130626325 ps
CPU time 1.03 seconds
Started Apr 04 12:27:35 PM PDT 24
Finished Apr 04 12:27:36 PM PDT 24
Peak memory 183780 kb
Host smart-5e70fdca-dcd8-443c-8340-e2d49eec97ef
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420504792 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_h
w_reset.1420504792
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.37997859
Short name T348
Test name
Test status
Simulation time 404024935 ps
CPU time 0.9 seconds
Started Apr 04 12:28:53 PM PDT 24
Finished Apr 04 12:28:54 PM PDT 24
Peak memory 194808 kb
Host smart-7a94f34e-5b93-4da1-806a-396ebda93b61
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37997859 -assert nopostproc +UVM_TESTNAME=a
on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.37997859
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.3836754787
Short name T408
Test name
Test status
Simulation time 494116872 ps
CPU time 1.01 seconds
Started Apr 04 12:27:36 PM PDT 24
Finished Apr 04 12:27:37 PM PDT 24
Peak memory 183676 kb
Host smart-b058d911-68b3-4181-b988-a20a6eaf516f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836754787 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.3836754787
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.2311735235
Short name T343
Test name
Test status
Simulation time 447767162 ps
CPU time 0.91 seconds
Started Apr 04 12:27:36 PM PDT 24
Finished Apr 04 12:27:37 PM PDT 24
Peak memory 183692 kb
Host smart-0b93dae8-104f-4cb2-8b07-2e471ad8b37b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311735235 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.2311735235
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.689723747
Short name T288
Test name
Test status
Simulation time 322550506 ps
CPU time 0.74 seconds
Started Apr 04 12:27:37 PM PDT 24
Finished Apr 04 12:27:38 PM PDT 24
Peak memory 183628 kb
Host smart-de3a6cea-1632-436b-90e7-88ffaaa9dba0
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689723747 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_ti
mer_mem_partial_access.689723747
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.2594325481
Short name T384
Test name
Test status
Simulation time 293242915 ps
CPU time 0.69 seconds
Started Apr 04 12:27:35 PM PDT 24
Finished Apr 04 12:27:36 PM PDT 24
Peak memory 183644 kb
Host smart-17448011-91ca-4f52-890a-8d319017cf09
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594325481 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_w
alk.2594325481
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.251343041
Short name T320
Test name
Test status
Simulation time 2117766201 ps
CPU time 4.8 seconds
Started Apr 04 12:28:54 PM PDT 24
Finished Apr 04 12:28:58 PM PDT 24
Peak memory 191956 kb
Host smart-fe8e6f30-5d6c-4abd-9ba1-8dec1482381a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251343041 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_
timer_same_csr_outstanding.251343041
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.1924448830
Short name T355
Test name
Test status
Simulation time 615861168 ps
CPU time 1.24 seconds
Started Apr 04 12:27:34 PM PDT 24
Finished Apr 04 12:27:35 PM PDT 24
Peak memory 197312 kb
Host smart-3cedb172-0a71-4644-a576-d7421ebca6bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924448830 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.1924448830
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.3161214718
Short name T402
Test name
Test status
Simulation time 589683416 ps
CPU time 1.65 seconds
Started Apr 04 12:27:45 PM PDT 24
Finished Apr 04 12:27:47 PM PDT 24
Peak memory 195860 kb
Host smart-6e1b0df1-7853-4556-98c0-20f73a94f4a4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161214718 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.3161214718
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.2940719781
Short name T366
Test name
Test status
Simulation time 457109132 ps
CPU time 0.73 seconds
Started Apr 04 12:27:47 PM PDT 24
Finished Apr 04 12:27:48 PM PDT 24
Peak memory 184088 kb
Host smart-83fb8c53-761c-4822-982b-7a0a06fcaa14
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940719781 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.2940719781
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.298232247
Short name T405
Test name
Test status
Simulation time 421666510 ps
CPU time 0.68 seconds
Started Apr 04 12:27:47 PM PDT 24
Finished Apr 04 12:27:48 PM PDT 24
Peak memory 183472 kb
Host smart-90c4aae6-af67-4e10-baf2-60d68370d03d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298232247 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.298232247
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.4255528678
Short name T372
Test name
Test status
Simulation time 2009693677 ps
CPU time 3.7 seconds
Started Apr 04 12:27:46 PM PDT 24
Finished Apr 04 12:27:50 PM PDT 24
Peak memory 194616 kb
Host smart-d9acdebf-045c-425f-b175-a6fe4eddd484
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255528678 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.ao
n_timer_same_csr_outstanding.4255528678
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.956255944
Short name T395
Test name
Test status
Simulation time 569002363 ps
CPU time 2.45 seconds
Started Apr 04 12:27:44 PM PDT 24
Finished Apr 04 12:27:47 PM PDT 24
Peak memory 198668 kb
Host smart-8629349c-faf1-4827-91e1-2c9529ab51d1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956255944 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.956255944
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.1394170216
Short name T385
Test name
Test status
Simulation time 4506141822 ps
CPU time 2.55 seconds
Started Apr 04 12:27:46 PM PDT 24
Finished Apr 04 12:27:48 PM PDT 24
Peak memory 197504 kb
Host smart-13fe17e9-7818-469e-9568-a6c6f17529b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394170216 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_t
l_intg_err.1394170216
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.2730123213
Short name T351
Test name
Test status
Simulation time 578195564 ps
CPU time 1.53 seconds
Started Apr 04 12:27:42 PM PDT 24
Finished Apr 04 12:27:44 PM PDT 24
Peak memory 195872 kb
Host smart-ad88742c-b892-445d-b028-348962c71d78
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730123213 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.2730123213
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.683053626
Short name T49
Test name
Test status
Simulation time 521228362 ps
CPU time 1.36 seconds
Started Apr 04 12:27:44 PM PDT 24
Finished Apr 04 12:27:45 PM PDT 24
Peak memory 184020 kb
Host smart-138286e4-0565-4656-84b6-45d17b34643a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683053626 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.683053626
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.1973608592
Short name T419
Test name
Test status
Simulation time 534711731 ps
CPU time 0.71 seconds
Started Apr 04 12:27:48 PM PDT 24
Finished Apr 04 12:27:49 PM PDT 24
Peak memory 183716 kb
Host smart-5f71fec2-77f3-4486-ad71-b98c20092741
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973608592 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.1973608592
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.1401510741
Short name T327
Test name
Test status
Simulation time 992380699 ps
CPU time 1.84 seconds
Started Apr 04 12:27:42 PM PDT 24
Finished Apr 04 12:27:44 PM PDT 24
Peak memory 193360 kb
Host smart-b4cdbe5d-6136-4426-9d19-da0151bb59cb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401510741 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.ao
n_timer_same_csr_outstanding.1401510741
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.1212722402
Short name T344
Test name
Test status
Simulation time 1851904552 ps
CPU time 1.52 seconds
Started Apr 04 12:27:43 PM PDT 24
Finished Apr 04 12:27:44 PM PDT 24
Peak memory 198664 kb
Host smart-cd46252d-9f57-4e51-abd7-a650979a4c09
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212722402 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.1212722402
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.2520439824
Short name T410
Test name
Test status
Simulation time 3707914652 ps
CPU time 3.92 seconds
Started Apr 04 12:27:47 PM PDT 24
Finished Apr 04 12:27:51 PM PDT 24
Peak memory 197516 kb
Host smart-75631d07-3ca7-4dcf-abe7-9385d66014b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520439824 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_t
l_intg_err.2520439824
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.3532409346
Short name T362
Test name
Test status
Simulation time 465189068 ps
CPU time 1.02 seconds
Started Apr 04 12:29:21 PM PDT 24
Finished Apr 04 12:29:22 PM PDT 24
Peak memory 196064 kb
Host smart-548a39fc-754e-4504-95e9-ea11dbaedef9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532409346 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.3532409346
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.4057242224
Short name T50
Test name
Test status
Simulation time 436041396 ps
CPU time 0.72 seconds
Started Apr 04 12:27:45 PM PDT 24
Finished Apr 04 12:27:46 PM PDT 24
Peak memory 190580 kb
Host smart-b549429a-aaf3-4831-b3c8-a56a462bf0f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057242224 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.4057242224
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.16542954
Short name T388
Test name
Test status
Simulation time 488461133 ps
CPU time 0.72 seconds
Started Apr 04 12:27:41 PM PDT 24
Finished Apr 04 12:27:42 PM PDT 24
Peak memory 183628 kb
Host smart-c830e574-4b46-477c-9331-afaa360193e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16542954 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.16542954
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.3021338908
Short name T33
Test name
Test status
Simulation time 2575916479 ps
CPU time 2.37 seconds
Started Apr 04 12:27:47 PM PDT 24
Finished Apr 04 12:27:49 PM PDT 24
Peak memory 194360 kb
Host smart-63d7f673-04e1-4925-8e75-a3b467bc7fe6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021338908 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.ao
n_timer_same_csr_outstanding.3021338908
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.4199890874
Short name T321
Test name
Test status
Simulation time 451620485 ps
CPU time 1.16 seconds
Started Apr 04 12:28:50 PM PDT 24
Finished Apr 04 12:28:51 PM PDT 24
Peak memory 198304 kb
Host smart-461a1c58-ad3a-4d92-9a10-dd06fbd4b76b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199890874 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.4199890874
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.407675115
Short name T37
Test name
Test status
Simulation time 4583054905 ps
CPU time 2.55 seconds
Started Apr 04 12:27:46 PM PDT 24
Finished Apr 04 12:27:49 PM PDT 24
Peak memory 194776 kb
Host smart-87f6bce0-9c7d-4601-bbd9-b48cb7c39768
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407675115 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl
_intg_err.407675115
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.2595225573
Short name T332
Test name
Test status
Simulation time 614347263 ps
CPU time 1.48 seconds
Started Apr 04 12:28:51 PM PDT 24
Finished Apr 04 12:28:52 PM PDT 24
Peak memory 195968 kb
Host smart-326352a2-7b08-4014-8f4d-6b275c2e9f7d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595225573 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.2595225573
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.1808817255
Short name T328
Test name
Test status
Simulation time 438573037 ps
CPU time 1.17 seconds
Started Apr 04 12:28:51 PM PDT 24
Finished Apr 04 12:28:52 PM PDT 24
Peak memory 193196 kb
Host smart-f0e60d0b-c7ee-46ba-a08b-6a0be9b4c596
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808817255 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.1808817255
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.4102591332
Short name T298
Test name
Test status
Simulation time 352151012 ps
CPU time 0.6 seconds
Started Apr 04 12:27:47 PM PDT 24
Finished Apr 04 12:27:47 PM PDT 24
Peak memory 183432 kb
Host smart-9dc4ba56-bc0e-4912-9f7d-257cb19ad2f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102591332 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.4102591332
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.372170424
Short name T69
Test name
Test status
Simulation time 3037704010 ps
CPU time 1.87 seconds
Started Apr 04 12:29:08 PM PDT 24
Finished Apr 04 12:29:10 PM PDT 24
Peak memory 194768 kb
Host smart-2e2d5493-76ea-4c69-bfad-38c76ec4f7b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372170424 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon
_timer_same_csr_outstanding.372170424
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.759565268
Short name T347
Test name
Test status
Simulation time 492833464 ps
CPU time 2.55 seconds
Started Apr 04 12:27:46 PM PDT 24
Finished Apr 04 12:27:49 PM PDT 24
Peak memory 197884 kb
Host smart-db7c275b-b284-426e-9de3-b82d51450078
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759565268 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.759565268
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.2464067788
Short name T387
Test name
Test status
Simulation time 4334434858 ps
CPU time 4.62 seconds
Started Apr 04 12:27:43 PM PDT 24
Finished Apr 04 12:27:48 PM PDT 24
Peak memory 197608 kb
Host smart-8bc74f87-f87d-45c3-a5cd-1c68228dce6f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464067788 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_t
l_intg_err.2464067788
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.2732509108
Short name T404
Test name
Test status
Simulation time 524063911 ps
CPU time 1.4 seconds
Started Apr 04 12:28:51 PM PDT 24
Finished Apr 04 12:28:52 PM PDT 24
Peak memory 195576 kb
Host smart-55cfeda0-df49-43be-a8f2-0a89fab507d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732509108 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.2732509108
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.331206962
Short name T392
Test name
Test status
Simulation time 519482820 ps
CPU time 1.32 seconds
Started Apr 04 12:28:51 PM PDT 24
Finished Apr 04 12:28:52 PM PDT 24
Peak memory 183728 kb
Host smart-0cdca182-1c6d-4e8b-a787-cc36aeffc42e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331206962 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.331206962
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.3768727492
Short name T280
Test name
Test status
Simulation time 327941924 ps
CPU time 0.78 seconds
Started Apr 04 12:29:45 PM PDT 24
Finished Apr 04 12:29:46 PM PDT 24
Peak memory 183720 kb
Host smart-dae86c2a-13e2-4781-ae2c-06e48d3e2991
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768727492 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.3768727492
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.2181738571
Short name T70
Test name
Test status
Simulation time 2393979992 ps
CPU time 2.1 seconds
Started Apr 04 12:28:45 PM PDT 24
Finished Apr 04 12:28:48 PM PDT 24
Peak memory 194452 kb
Host smart-2eff53b9-f987-41ee-9f7a-394630005b35
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181738571 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao
n_timer_same_csr_outstanding.2181738571
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.3761514715
Short name T295
Test name
Test status
Simulation time 502158336 ps
CPU time 1.9 seconds
Started Apr 04 12:29:19 PM PDT 24
Finished Apr 04 12:29:21 PM PDT 24
Peak memory 198520 kb
Host smart-9a621b68-6845-46af-b33e-8d3c31836b32
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761514715 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.3761514715
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.3477996516
Short name T297
Test name
Test status
Simulation time 7868795530 ps
CPU time 12.58 seconds
Started Apr 04 12:29:46 PM PDT 24
Finished Apr 04 12:29:58 PM PDT 24
Peak memory 197916 kb
Host smart-06fe3c88-06ec-4257-9b94-1b3c411a5898
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477996516 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_t
l_intg_err.3477996516
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.2855693090
Short name T282
Test name
Test status
Simulation time 537956249 ps
CPU time 0.83 seconds
Started Apr 04 12:28:54 PM PDT 24
Finished Apr 04 12:28:55 PM PDT 24
Peak memory 196028 kb
Host smart-7e7632be-4fc8-449f-aa76-be5c95d7656c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855693090 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.2855693090
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.3735315334
Short name T322
Test name
Test status
Simulation time 264655152 ps
CPU time 0.9 seconds
Started Apr 04 12:28:51 PM PDT 24
Finished Apr 04 12:28:52 PM PDT 24
Peak memory 183704 kb
Host smart-d266e439-756c-4491-ac0e-cf2c51c91a47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735315334 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.3735315334
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.1809382386
Short name T311
Test name
Test status
Simulation time 1048735872 ps
CPU time 1.95 seconds
Started Apr 04 12:29:18 PM PDT 24
Finished Apr 04 12:29:20 PM PDT 24
Peak memory 193428 kb
Host smart-19da07a4-c8b6-459f-8d43-170d84620c26
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809382386 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.ao
n_timer_same_csr_outstanding.1809382386
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.3906212776
Short name T352
Test name
Test status
Simulation time 674206082 ps
CPU time 1.91 seconds
Started Apr 04 12:31:01 PM PDT 24
Finished Apr 04 12:31:03 PM PDT 24
Peak memory 198744 kb
Host smart-9728d8a3-320d-43ce-9662-b8c5f30bdde3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906212776 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.3906212776
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.879355035
Short name T98
Test name
Test status
Simulation time 4394817508 ps
CPU time 6.75 seconds
Started Apr 04 12:28:36 PM PDT 24
Finished Apr 04 12:28:43 PM PDT 24
Peak memory 197676 kb
Host smart-9915d802-4d9e-494b-a2c1-8401e25cf5c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879355035 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl
_intg_err.879355035
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.463271151
Short name T377
Test name
Test status
Simulation time 501325089 ps
CPU time 1.34 seconds
Started Apr 04 12:28:55 PM PDT 24
Finished Apr 04 12:28:57 PM PDT 24
Peak memory 196172 kb
Host smart-a52a552f-e67f-4737-907b-3264aee99be5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463271151 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.463271151
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.3427622158
Short name T399
Test name
Test status
Simulation time 287370489 ps
CPU time 1.02 seconds
Started Apr 04 12:28:45 PM PDT 24
Finished Apr 04 12:28:46 PM PDT 24
Peak memory 183976 kb
Host smart-392566c1-abb1-4f1a-b6d1-885ccd9e9fd6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427622158 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.3427622158
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.2842665947
Short name T376
Test name
Test status
Simulation time 417474427 ps
CPU time 1.2 seconds
Started Apr 04 12:29:04 PM PDT 24
Finished Apr 04 12:29:06 PM PDT 24
Peak memory 183932 kb
Host smart-e367d8f1-15c1-4c7b-983e-4b7ce20e89f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842665947 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.2842665947
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.1478178784
Short name T72
Test name
Test status
Simulation time 2238247375 ps
CPU time 1.97 seconds
Started Apr 04 12:28:51 PM PDT 24
Finished Apr 04 12:28:53 PM PDT 24
Peak memory 194696 kb
Host smart-d73ef667-e739-4c5b-8462-8d5da5ea1ccb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478178784 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.ao
n_timer_same_csr_outstanding.1478178784
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.3863206590
Short name T304
Test name
Test status
Simulation time 1691540215 ps
CPU time 1.97 seconds
Started Apr 04 12:30:02 PM PDT 24
Finished Apr 04 12:30:04 PM PDT 24
Peak memory 198796 kb
Host smart-aa888bba-0974-4aec-85e5-32549960bb82
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863206590 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.3863206590
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.1433377389
Short name T353
Test name
Test status
Simulation time 462673095 ps
CPU time 1.42 seconds
Started Apr 04 12:29:37 PM PDT 24
Finished Apr 04 12:29:39 PM PDT 24
Peak memory 195216 kb
Host smart-6d0c6fad-8856-4112-8f7b-1f9e0005a11b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433377389 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.1433377389
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.2032477361
Short name T74
Test name
Test status
Simulation time 371333207 ps
CPU time 0.7 seconds
Started Apr 04 12:28:45 PM PDT 24
Finished Apr 04 12:28:46 PM PDT 24
Peak memory 183816 kb
Host smart-258a1cfc-b27b-45cd-bdf1-607bfd97af37
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032477361 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.2032477361
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.1745986931
Short name T357
Test name
Test status
Simulation time 535468490 ps
CPU time 0.73 seconds
Started Apr 04 12:28:51 PM PDT 24
Finished Apr 04 12:28:52 PM PDT 24
Peak memory 183728 kb
Host smart-12b85316-3992-460f-923c-e90acf6109ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745986931 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.1745986931
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.1591025172
Short name T317
Test name
Test status
Simulation time 2882982517 ps
CPU time 5.17 seconds
Started Apr 04 12:28:45 PM PDT 24
Finished Apr 04 12:28:50 PM PDT 24
Peak memory 194784 kb
Host smart-0963b05d-5271-445e-9fdf-ac00b68a57d0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591025172 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.ao
n_timer_same_csr_outstanding.1591025172
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.2320091861
Short name T292
Test name
Test status
Simulation time 635753152 ps
CPU time 1.52 seconds
Started Apr 04 12:28:45 PM PDT 24
Finished Apr 04 12:28:47 PM PDT 24
Peak memory 198652 kb
Host smart-ee18044e-6020-4912-86fb-4df5a666df62
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320091861 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.2320091861
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.112849151
Short name T331
Test name
Test status
Simulation time 4761422043 ps
CPU time 4.49 seconds
Started Apr 04 12:28:45 PM PDT 24
Finished Apr 04 12:28:50 PM PDT 24
Peak memory 196272 kb
Host smart-04020893-7588-48ef-83a1-4325aab3410a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112849151 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl
_intg_err.112849151
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.4021044770
Short name T325
Test name
Test status
Simulation time 577576777 ps
CPU time 1.12 seconds
Started Apr 04 12:28:45 PM PDT 24
Finished Apr 04 12:28:46 PM PDT 24
Peak memory 196160 kb
Host smart-b7342a6c-c6e0-4663-b8b8-6fe6ff7ddb1c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021044770 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.4021044770
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.1186030411
Short name T363
Test name
Test status
Simulation time 353462378 ps
CPU time 1.18 seconds
Started Apr 04 12:29:18 PM PDT 24
Finished Apr 04 12:29:19 PM PDT 24
Peak memory 183992 kb
Host smart-1049c32b-b5e5-4bf5-ba16-431910fa963e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186030411 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.1186030411
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.1915495312
Short name T370
Test name
Test status
Simulation time 289396198 ps
CPU time 0.66 seconds
Started Apr 04 12:28:51 PM PDT 24
Finished Apr 04 12:28:51 PM PDT 24
Peak memory 183696 kb
Host smart-5321086e-de95-4b8f-8418-0cf177717edc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915495312 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.1915495312
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.29466076
Short name T73
Test name
Test status
Simulation time 2452254356 ps
CPU time 1.57 seconds
Started Apr 04 12:29:46 PM PDT 24
Finished Apr 04 12:29:47 PM PDT 24
Peak memory 183888 kb
Host smart-63405988-ec64-496f-9ff0-c1365cb30891
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29466076 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_
timer_same_csr_outstanding.29466076
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.3990761977
Short name T346
Test name
Test status
Simulation time 461721220 ps
CPU time 1.7 seconds
Started Apr 04 12:28:45 PM PDT 24
Finished Apr 04 12:28:47 PM PDT 24
Peak memory 198428 kb
Host smart-e7670f2c-cf6d-4bdd-a204-9a77347ae1cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990761977 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.3990761977
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.1026488840
Short name T300
Test name
Test status
Simulation time 4643603466 ps
CPU time 1.38 seconds
Started Apr 04 12:28:44 PM PDT 24
Finished Apr 04 12:28:46 PM PDT 24
Peak memory 196564 kb
Host smart-3880c66f-ee8c-4cef-8ee3-f21175a08eb2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026488840 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_t
l_intg_err.1026488840
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.1610014461
Short name T310
Test name
Test status
Simulation time 405202865 ps
CPU time 1.22 seconds
Started Apr 04 12:28:57 PM PDT 24
Finished Apr 04 12:28:58 PM PDT 24
Peak memory 196928 kb
Host smart-dffa80dc-f1b3-4d9d-8f58-f5f10f03dab7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610014461 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.1610014461
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.2809786962
Short name T55
Test name
Test status
Simulation time 407614171 ps
CPU time 0.9 seconds
Started Apr 04 12:28:46 PM PDT 24
Finished Apr 04 12:28:47 PM PDT 24
Peak memory 183856 kb
Host smart-0fa89ff9-7e64-4262-aa74-e2c9dd318939
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809786962 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.2809786962
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.3807764342
Short name T365
Test name
Test status
Simulation time 406740686 ps
CPU time 1.08 seconds
Started Apr 04 12:28:53 PM PDT 24
Finished Apr 04 12:28:54 PM PDT 24
Peak memory 183756 kb
Host smart-99c937c2-d297-4c88-9973-006acd98f7bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807764342 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.3807764342
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.995444332
Short name T330
Test name
Test status
Simulation time 1008292343 ps
CPU time 0.93 seconds
Started Apr 04 12:28:41 PM PDT 24
Finished Apr 04 12:28:42 PM PDT 24
Peak memory 184216 kb
Host smart-b5b84b5c-cdad-461e-a888-492e2b7fd25a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995444332 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon
_timer_same_csr_outstanding.995444332
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.3249481671
Short name T398
Test name
Test status
Simulation time 288950846 ps
CPU time 1.51 seconds
Started Apr 04 12:28:45 PM PDT 24
Finished Apr 04 12:28:47 PM PDT 24
Peak memory 198664 kb
Host smart-a768b8c0-3b58-4733-bc1b-2a9c4b9c4450
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249481671 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.3249481671
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.1839421346
Short name T309
Test name
Test status
Simulation time 8224417001 ps
CPU time 14.41 seconds
Started Apr 04 12:28:57 PM PDT 24
Finished Apr 04 12:29:11 PM PDT 24
Peak memory 197884 kb
Host smart-566fca8e-bc1d-4533-ae67-0fb734b20b87
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839421346 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_t
l_intg_err.1839421346
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.180038906
Short name T54
Test name
Test status
Simulation time 535376999 ps
CPU time 1.42 seconds
Started Apr 04 12:28:48 PM PDT 24
Finished Apr 04 12:28:50 PM PDT 24
Peak memory 193512 kb
Host smart-071781b9-568e-4500-b5ba-c9760810c2ef
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180038906 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_al
iasing.180038906
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.26509998
Short name T345
Test name
Test status
Simulation time 7031019886 ps
CPU time 9.52 seconds
Started Apr 04 12:28:53 PM PDT 24
Finished Apr 04 12:29:02 PM PDT 24
Peak memory 191020 kb
Host smart-48fea369-8adb-407c-bb5d-b9baa7d2e18d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26509998 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_bit
_bash.26509998
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.2193784842
Short name T393
Test name
Test status
Simulation time 948402884 ps
CPU time 1.97 seconds
Started Apr 04 12:28:54 PM PDT 24
Finished Apr 04 12:28:56 PM PDT 24
Peak memory 193116 kb
Host smart-40c8696b-c246-4ef1-ad8a-f22d20c6c57b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193784842 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_h
w_reset.2193784842
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.3672214568
Short name T296
Test name
Test status
Simulation time 586091893 ps
CPU time 1.13 seconds
Started Apr 04 12:28:52 PM PDT 24
Finished Apr 04 12:28:53 PM PDT 24
Peak memory 193948 kb
Host smart-3cba7b37-922f-413a-b9f4-1b8a7925bb3a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672214568 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.3672214568
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.941066077
Short name T57
Test name
Test status
Simulation time 312798780 ps
CPU time 0.84 seconds
Started Apr 04 12:29:39 PM PDT 24
Finished Apr 04 12:29:39 PM PDT 24
Peak memory 193076 kb
Host smart-b4fc264d-8afe-446f-95cc-38181c7b6040
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941066077 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.941066077
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.2669954126
Short name T381
Test name
Test status
Simulation time 312978125 ps
CPU time 0.63 seconds
Started Apr 04 12:28:57 PM PDT 24
Finished Apr 04 12:28:57 PM PDT 24
Peak memory 183860 kb
Host smart-0a3142ff-4249-40da-ac98-33278389375d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669954126 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.2669954126
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.732468239
Short name T290
Test name
Test status
Simulation time 324083092 ps
CPU time 0.65 seconds
Started Apr 04 12:28:53 PM PDT 24
Finished Apr 04 12:28:54 PM PDT 24
Peak memory 182696 kb
Host smart-8f20d273-54dd-469a-b532-bcbcfe3ca69a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732468239 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_ti
mer_mem_partial_access.732468239
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.323400148
Short name T337
Test name
Test status
Simulation time 326196612 ps
CPU time 0.66 seconds
Started Apr 04 12:28:53 PM PDT 24
Finished Apr 04 12:28:54 PM PDT 24
Peak memory 183340 kb
Host smart-ab2d1daf-f39c-4f3c-8b5d-54c7b237d94e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323400148 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_wa
lk.323400148
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.2784749090
Short name T303
Test name
Test status
Simulation time 1260099053 ps
CPU time 1.23 seconds
Started Apr 04 12:29:06 PM PDT 24
Finished Apr 04 12:29:08 PM PDT 24
Peak memory 183932 kb
Host smart-b1fdbdc3-74fb-4a33-9d12-9f229b1f31f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784749090 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon
_timer_same_csr_outstanding.2784749090
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.618998947
Short name T358
Test name
Test status
Simulation time 300170754 ps
CPU time 2.42 seconds
Started Apr 04 12:28:54 PM PDT 24
Finished Apr 04 12:28:57 PM PDT 24
Peak memory 198724 kb
Host smart-930e4ff8-b246-4bf5-b2a3-6ac84c9ae50f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618998947 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.618998947
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.556477676
Short name T94
Test name
Test status
Simulation time 8114870962 ps
CPU time 12.29 seconds
Started Apr 04 12:28:53 PM PDT 24
Finished Apr 04 12:29:06 PM PDT 24
Peak memory 196604 kb
Host smart-3575cf64-9c0e-46d8-a05c-a66f031f155d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556477676 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_
intg_err.556477676
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.813737698
Short name T329
Test name
Test status
Simulation time 277402470 ps
CPU time 0.89 seconds
Started Apr 04 12:29:45 PM PDT 24
Finished Apr 04 12:29:46 PM PDT 24
Peak memory 183732 kb
Host smart-9c144a5a-a2ff-4d8c-97eb-3c705b0b62ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813737698 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.813737698
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.2785474185
Short name T367
Test name
Test status
Simulation time 369050140 ps
CPU time 0.7 seconds
Started Apr 04 12:28:43 PM PDT 24
Finished Apr 04 12:28:44 PM PDT 24
Peak memory 183784 kb
Host smart-6f48f1d8-e8dd-4514-a0b6-e7a07fab2e20
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785474185 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.2785474185
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.2231323265
Short name T361
Test name
Test status
Simulation time 415140772 ps
CPU time 1.16 seconds
Started Apr 04 12:29:39 PM PDT 24
Finished Apr 04 12:29:40 PM PDT 24
Peak memory 183708 kb
Host smart-9e0af736-613a-4332-92bf-da9cf2676883
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231323265 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.2231323265
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.1851921302
Short name T285
Test name
Test status
Simulation time 351935995 ps
CPU time 1.16 seconds
Started Apr 04 12:28:44 PM PDT 24
Finished Apr 04 12:28:46 PM PDT 24
Peak memory 183804 kb
Host smart-a2a04335-ed14-4582-9091-013fde475597
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851921302 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.1851921302
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.2825083170
Short name T415
Test name
Test status
Simulation time 393952740 ps
CPU time 0.68 seconds
Started Apr 04 12:29:45 PM PDT 24
Finished Apr 04 12:29:46 PM PDT 24
Peak memory 183752 kb
Host smart-5989b190-d434-4e2c-9a8f-3d917f0d590b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825083170 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.2825083170
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.1881148198
Short name T411
Test name
Test status
Simulation time 375967270 ps
CPU time 0.71 seconds
Started Apr 04 12:29:02 PM PDT 24
Finished Apr 04 12:29:03 PM PDT 24
Peak memory 183792 kb
Host smart-0d49fd2c-7b23-499c-8f9c-0444b97bc1c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881148198 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.1881148198
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.3677237727
Short name T326
Test name
Test status
Simulation time 473325055 ps
CPU time 0.89 seconds
Started Apr 04 12:29:22 PM PDT 24
Finished Apr 04 12:29:23 PM PDT 24
Peak memory 183900 kb
Host smart-5670e4b0-2456-483b-94ff-ab54008f9a3a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677237727 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.3677237727
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.1691333891
Short name T371
Test name
Test status
Simulation time 406348046 ps
CPU time 1.14 seconds
Started Apr 04 12:29:49 PM PDT 24
Finished Apr 04 12:29:51 PM PDT 24
Peak memory 183756 kb
Host smart-d4cedebd-a7e5-4568-854f-657ae4059212
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691333891 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.1691333891
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.479305212
Short name T312
Test name
Test status
Simulation time 474981915 ps
CPU time 1.39 seconds
Started Apr 04 12:29:10 PM PDT 24
Finished Apr 04 12:29:11 PM PDT 24
Peak memory 183796 kb
Host smart-b0e9444c-845c-472b-8747-b682a9b551e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479305212 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.479305212
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.3808703245
Short name T334
Test name
Test status
Simulation time 438730696 ps
CPU time 1.14 seconds
Started Apr 04 12:29:48 PM PDT 24
Finished Apr 04 12:29:49 PM PDT 24
Peak memory 183756 kb
Host smart-0940fa87-37c8-4043-abc5-91c364ec5dad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808703245 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.3808703245
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.1314031649
Short name T56
Test name
Test status
Simulation time 466073558 ps
CPU time 1.15 seconds
Started Apr 04 12:28:16 PM PDT 24
Finished Apr 04 12:28:17 PM PDT 24
Peak memory 183792 kb
Host smart-1dd23cde-6434-4f95-9549-16f2e47547ad
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314031649 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_a
liasing.1314031649
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.4210407627
Short name T47
Test name
Test status
Simulation time 7155061618 ps
CPU time 7.3 seconds
Started Apr 04 12:29:03 PM PDT 24
Finished Apr 04 12:29:11 PM PDT 24
Peak memory 190668 kb
Host smart-d20a9b0e-d8f7-4af4-bb9b-2bff90e25302
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210407627 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_b
it_bash.4210407627
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.632521032
Short name T281
Test name
Test status
Simulation time 764119673 ps
CPU time 0.86 seconds
Started Apr 04 12:29:38 PM PDT 24
Finished Apr 04 12:29:40 PM PDT 24
Peak memory 183892 kb
Host smart-30553d88-8793-410c-a150-22ea94f29dae
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632521032 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_hw
_reset.632521032
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.1422808754
Short name T401
Test name
Test status
Simulation time 442950982 ps
CPU time 0.98 seconds
Started Apr 04 12:29:25 PM PDT 24
Finished Apr 04 12:29:26 PM PDT 24
Peak memory 198388 kb
Host smart-802e95b8-8da1-4529-9e34-6ee2a2394dd7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422808754 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.1422808754
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.2228334847
Short name T35
Test name
Test status
Simulation time 515674883 ps
CPU time 1.39 seconds
Started Apr 04 12:29:03 PM PDT 24
Finished Apr 04 12:29:05 PM PDT 24
Peak memory 191112 kb
Host smart-961c71ba-3691-42f1-8a8e-c26898e07fce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228334847 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.2228334847
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.174563231
Short name T324
Test name
Test status
Simulation time 378812308 ps
CPU time 0.66 seconds
Started Apr 04 12:28:19 PM PDT 24
Finished Apr 04 12:28:20 PM PDT 24
Peak memory 183716 kb
Host smart-2d26f48a-abf7-4d04-8f10-56c746da1bec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174563231 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.174563231
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.476935427
Short name T359
Test name
Test status
Simulation time 300677650 ps
CPU time 0.61 seconds
Started Apr 04 12:28:52 PM PDT 24
Finished Apr 04 12:28:53 PM PDT 24
Peak memory 182216 kb
Host smart-ce8ce929-c4ef-41fb-b739-63d380d26584
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476935427 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_ti
mer_mem_partial_access.476935427
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.182626624
Short name T341
Test name
Test status
Simulation time 508505098 ps
CPU time 0.91 seconds
Started Apr 04 12:29:06 PM PDT 24
Finished Apr 04 12:29:07 PM PDT 24
Peak memory 183728 kb
Host smart-e80cca97-98f1-4c8c-b9cb-36eb9baa9f3a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182626624 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_wa
lk.182626624
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.1572890779
Short name T373
Test name
Test status
Simulation time 2138273523 ps
CPU time 3.99 seconds
Started Apr 04 12:29:25 PM PDT 24
Finished Apr 04 12:29:30 PM PDT 24
Peak memory 194456 kb
Host smart-cab925b5-d971-44d1-a14f-e1d76682fd49
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572890779 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon
_timer_same_csr_outstanding.1572890779
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.4064856928
Short name T278
Test name
Test status
Simulation time 406973928 ps
CPU time 1.77 seconds
Started Apr 04 12:28:53 PM PDT 24
Finished Apr 04 12:28:55 PM PDT 24
Peak memory 198552 kb
Host smart-7fa7c4c3-2d58-4085-93ec-a42fc2cde284
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064856928 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.4064856928
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.3411314382
Short name T95
Test name
Test status
Simulation time 4649704571 ps
CPU time 2.6 seconds
Started Apr 04 12:29:06 PM PDT 24
Finished Apr 04 12:29:09 PM PDT 24
Peak memory 196648 kb
Host smart-5913f6ca-9c56-4fec-af11-c67bfc830404
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411314382 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl
_intg_err.3411314382
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.3872363596
Short name T368
Test name
Test status
Simulation time 371635180 ps
CPU time 1.13 seconds
Started Apr 04 12:29:12 PM PDT 24
Finished Apr 04 12:29:13 PM PDT 24
Peak memory 183892 kb
Host smart-58714ea5-4b6e-423c-a381-ebf0ed09d42d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872363596 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.3872363596
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.1090030852
Short name T319
Test name
Test status
Simulation time 477111917 ps
CPU time 1.29 seconds
Started Apr 04 12:28:43 PM PDT 24
Finished Apr 04 12:28:44 PM PDT 24
Peak memory 183920 kb
Host smart-8b09c93e-f39d-4da2-b3c4-93f89d618cf9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090030852 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.1090030852
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.1998093522
Short name T339
Test name
Test status
Simulation time 412406668 ps
CPU time 1.06 seconds
Started Apr 04 12:29:43 PM PDT 24
Finished Apr 04 12:29:44 PM PDT 24
Peak memory 183712 kb
Host smart-0aeb63ba-8236-474d-b908-a52a47be4f98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998093522 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.1998093522
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.2768806499
Short name T338
Test name
Test status
Simulation time 443308659 ps
CPU time 0.66 seconds
Started Apr 04 12:29:40 PM PDT 24
Finished Apr 04 12:29:41 PM PDT 24
Peak memory 183716 kb
Host smart-02fd6655-92dd-44bb-bda3-fd7a78446923
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768806499 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.2768806499
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.2408362069
Short name T360
Test name
Test status
Simulation time 421525094 ps
CPU time 1.25 seconds
Started Apr 04 12:29:23 PM PDT 24
Finished Apr 04 12:29:25 PM PDT 24
Peak memory 183896 kb
Host smart-72d0f803-38ae-4abb-9adb-3a0c5674afe5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408362069 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.2408362069
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.2212189914
Short name T286
Test name
Test status
Simulation time 497010736 ps
CPU time 0.75 seconds
Started Apr 04 12:33:25 PM PDT 24
Finished Apr 04 12:33:26 PM PDT 24
Peak memory 182268 kb
Host smart-4657d998-db17-495f-9817-d412fd8747d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212189914 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.2212189914
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.32837839
Short name T308
Test name
Test status
Simulation time 412045109 ps
CPU time 1.28 seconds
Started Apr 04 12:29:56 PM PDT 24
Finished Apr 04 12:29:58 PM PDT 24
Peak memory 183748 kb
Host smart-6f3c0afa-44ea-4ae8-9646-8f4f6a2eab96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32837839 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.32837839
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.1545300118
Short name T375
Test name
Test status
Simulation time 395420121 ps
CPU time 1.18 seconds
Started Apr 04 12:29:46 PM PDT 24
Finished Apr 04 12:29:47 PM PDT 24
Peak memory 183756 kb
Host smart-9c95b2c5-cc85-4e76-bec9-e3c2d3b09d8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545300118 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.1545300118
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.884349633
Short name T314
Test name
Test status
Simulation time 510985547 ps
CPU time 1.3 seconds
Started Apr 04 12:29:42 PM PDT 24
Finished Apr 04 12:29:44 PM PDT 24
Peak memory 183916 kb
Host smart-daee41c2-51f4-4f86-a671-b00b2aeea374
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884349633 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.884349633
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.1031741424
Short name T349
Test name
Test status
Simulation time 329782585 ps
CPU time 0.67 seconds
Started Apr 04 12:32:04 PM PDT 24
Finished Apr 04 12:32:05 PM PDT 24
Peak memory 183772 kb
Host smart-4b08f61a-8e98-45a0-8060-a167b6edbecf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031741424 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.1031741424
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.1445360382
Short name T48
Test name
Test status
Simulation time 462545106 ps
CPU time 0.85 seconds
Started Apr 04 12:29:05 PM PDT 24
Finished Apr 04 12:29:06 PM PDT 24
Peak memory 193272 kb
Host smart-d3e98e06-7796-4be6-9e31-176e1853e71a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445360382 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_a
liasing.1445360382
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.3815859761
Short name T45
Test name
Test status
Simulation time 7333988625 ps
CPU time 19.51 seconds
Started Apr 04 12:28:35 PM PDT 24
Finished Apr 04 12:28:55 PM PDT 24
Peak memory 192268 kb
Host smart-225d75a5-237e-4dc6-a97d-f25321edc0a9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815859761 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_b
it_bash.3815859761
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.3212411308
Short name T51
Test name
Test status
Simulation time 651204926 ps
CPU time 1.64 seconds
Started Apr 04 12:28:38 PM PDT 24
Finished Apr 04 12:28:40 PM PDT 24
Peak memory 183864 kb
Host smart-d619e01e-e09a-4b1e-9c5b-bfe4a12ea4af
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212411308 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_h
w_reset.3212411308
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.1089805322
Short name T378
Test name
Test status
Simulation time 417690927 ps
CPU time 0.95 seconds
Started Apr 04 12:29:45 PM PDT 24
Finished Apr 04 12:29:46 PM PDT 24
Peak memory 196188 kb
Host smart-2fe02c03-26fd-4329-8e20-f098916c3139
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089805322 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.1089805322
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.2165270471
Short name T67
Test name
Test status
Simulation time 352378768 ps
CPU time 0.67 seconds
Started Apr 04 12:28:37 PM PDT 24
Finished Apr 04 12:28:39 PM PDT 24
Peak memory 193168 kb
Host smart-d611b1a8-1bbe-4136-828d-fbb4e188dd00
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165270471 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.2165270471
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.632311385
Short name T335
Test name
Test status
Simulation time 479989873 ps
CPU time 0.91 seconds
Started Apr 04 12:29:22 PM PDT 24
Finished Apr 04 12:29:23 PM PDT 24
Peak memory 183636 kb
Host smart-5649c493-0b5c-49c3-b1e3-95488370af5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632311385 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.632311385
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.677258779
Short name T307
Test name
Test status
Simulation time 401455427 ps
CPU time 0.61 seconds
Started Apr 04 12:28:19 PM PDT 24
Finished Apr 04 12:28:19 PM PDT 24
Peak memory 183648 kb
Host smart-707e589a-7634-4fc0-aa30-32eb5cfbe7e5
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677258779 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_ti
mer_mem_partial_access.677258779
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.567980460
Short name T407
Test name
Test status
Simulation time 317311479 ps
CPU time 0.78 seconds
Started Apr 04 12:28:14 PM PDT 24
Finished Apr 04 12:28:15 PM PDT 24
Peak memory 183752 kb
Host smart-1b540147-f4d2-4624-9b94-63f796d03d65
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567980460 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_wa
lk.567980460
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.1179490785
Short name T364
Test name
Test status
Simulation time 2137239478 ps
CPU time 4.78 seconds
Started Apr 04 12:28:18 PM PDT 24
Finished Apr 04 12:28:23 PM PDT 24
Peak memory 194572 kb
Host smart-0c29ae43-1651-4a03-b1d4-776c7419524d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179490785 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon
_timer_same_csr_outstanding.1179490785
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.3320720442
Short name T389
Test name
Test status
Simulation time 473757795 ps
CPU time 1.57 seconds
Started Apr 04 12:29:49 PM PDT 24
Finished Apr 04 12:29:51 PM PDT 24
Peak memory 198684 kb
Host smart-7933ae4e-1bca-4186-8859-9001e2c91f0a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320720442 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.3320720442
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.2797846700
Short name T400
Test name
Test status
Simulation time 4786849759 ps
CPU time 4.87 seconds
Started Apr 04 12:28:45 PM PDT 24
Finished Apr 04 12:28:50 PM PDT 24
Peak memory 196592 kb
Host smart-d2e9ad3c-4771-46c1-81e6-52be12f64680
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797846700 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl
_intg_err.2797846700
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.2634015176
Short name T287
Test name
Test status
Simulation time 395402989 ps
CPU time 0.71 seconds
Started Apr 04 12:31:44 PM PDT 24
Finished Apr 04 12:31:45 PM PDT 24
Peak memory 183828 kb
Host smart-f563af86-ea67-4dc0-9006-90c31983bad8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634015176 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.2634015176
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.1520265001
Short name T416
Test name
Test status
Simulation time 477573219 ps
CPU time 1.16 seconds
Started Apr 04 12:29:38 PM PDT 24
Finished Apr 04 12:29:40 PM PDT 24
Peak memory 183856 kb
Host smart-29230839-7b52-43cd-a062-f19e12d6dacd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520265001 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.1520265001
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.3893067996
Short name T336
Test name
Test status
Simulation time 406997093 ps
CPU time 0.84 seconds
Started Apr 04 12:30:03 PM PDT 24
Finished Apr 04 12:30:04 PM PDT 24
Peak memory 183880 kb
Host smart-4edbca7b-7930-4d6f-9331-7ab05c084890
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893067996 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.3893067996
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.2280732091
Short name T289
Test name
Test status
Simulation time 371962519 ps
CPU time 0.79 seconds
Started Apr 04 12:29:49 PM PDT 24
Finished Apr 04 12:29:50 PM PDT 24
Peak memory 183708 kb
Host smart-f8f24962-8973-4a90-86a6-b18842b169bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280732091 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.2280732091
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.3586717027
Short name T356
Test name
Test status
Simulation time 396318123 ps
CPU time 1.11 seconds
Started Apr 04 12:29:57 PM PDT 24
Finished Apr 04 12:29:58 PM PDT 24
Peak memory 183752 kb
Host smart-d3b40d3f-4668-4fe0-a6cf-79e41be9b0f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586717027 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.3586717027
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.575843845
Short name T418
Test name
Test status
Simulation time 494006513 ps
CPU time 0.64 seconds
Started Apr 04 12:29:40 PM PDT 24
Finished Apr 04 12:29:41 PM PDT 24
Peak memory 183868 kb
Host smart-57238285-682b-40e0-b53c-a816457faa96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575843845 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.575843845
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.1938049207
Short name T413
Test name
Test status
Simulation time 335207499 ps
CPU time 0.72 seconds
Started Apr 04 12:29:38 PM PDT 24
Finished Apr 04 12:29:39 PM PDT 24
Peak memory 183756 kb
Host smart-ccf02f09-8ada-4de1-ac85-347b8120ef35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938049207 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.1938049207
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.2317975056
Short name T284
Test name
Test status
Simulation time 374909347 ps
CPU time 0.61 seconds
Started Apr 04 12:28:52 PM PDT 24
Finished Apr 04 12:28:52 PM PDT 24
Peak memory 183824 kb
Host smart-2245ffc3-ab2a-469d-8ea0-8cc5a9f5e61c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317975056 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.2317975056
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.3780670522
Short name T301
Test name
Test status
Simulation time 398009357 ps
CPU time 1.08 seconds
Started Apr 04 12:29:59 PM PDT 24
Finished Apr 04 12:30:00 PM PDT 24
Peak memory 183788 kb
Host smart-a50caf9a-111c-4156-b51e-5723f253e585
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780670522 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.3780670522
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.3502239625
Short name T323
Test name
Test status
Simulation time 532684695 ps
CPU time 0.72 seconds
Started Apr 04 12:28:53 PM PDT 24
Finished Apr 04 12:28:53 PM PDT 24
Peak memory 183756 kb
Host smart-4f3a4f1f-5eb4-4ada-8fe8-9e03af30e7b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502239625 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.3502239625
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.2778703143
Short name T394
Test name
Test status
Simulation time 574772199 ps
CPU time 1.55 seconds
Started Apr 04 12:29:46 PM PDT 24
Finished Apr 04 12:29:48 PM PDT 24
Peak memory 196160 kb
Host smart-4b64ba07-1302-4e24-9cca-798cc0e6be3c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778703143 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.2778703143
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.3350374153
Short name T354
Test name
Test status
Simulation time 435255775 ps
CPU time 0.61 seconds
Started Apr 04 12:29:49 PM PDT 24
Finished Apr 04 12:29:50 PM PDT 24
Peak memory 183768 kb
Host smart-2739f5f0-a4de-46c5-bb26-f3ba941bc7da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350374153 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.3350374153
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.3167321750
Short name T342
Test name
Test status
Simulation time 433837776 ps
CPU time 1.31 seconds
Started Apr 04 12:28:30 PM PDT 24
Finished Apr 04 12:28:31 PM PDT 24
Peak memory 183728 kb
Host smart-cd4863fd-9b39-46ef-ad79-7be05d732acf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167321750 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.3167321750
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.1147437227
Short name T68
Test name
Test status
Simulation time 1130208612 ps
CPU time 1.2 seconds
Started Apr 04 12:29:05 PM PDT 24
Finished Apr 04 12:29:06 PM PDT 24
Peak memory 193352 kb
Host smart-fc4b9d73-eaa4-4ff9-86ef-c14243a67a21
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147437227 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon
_timer_same_csr_outstanding.1147437227
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.852736767
Short name T279
Test name
Test status
Simulation time 651663614 ps
CPU time 2.09 seconds
Started Apr 04 12:28:49 PM PDT 24
Finished Apr 04 12:28:51 PM PDT 24
Peak memory 198732 kb
Host smart-a7d4957f-7925-4ac8-bf1e-1fee153513e6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852736767 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.852736767
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.1295221149
Short name T315
Test name
Test status
Simulation time 648796614 ps
CPU time 1.02 seconds
Started Apr 04 12:27:48 PM PDT 24
Finished Apr 04 12:27:49 PM PDT 24
Peak memory 197508 kb
Host smart-64d93fea-2ad0-4724-a91b-dc47281cf33b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295221149 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.1295221149
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.2101254865
Short name T305
Test name
Test status
Simulation time 481379909 ps
CPU time 1.31 seconds
Started Apr 04 12:28:54 PM PDT 24
Finished Apr 04 12:28:56 PM PDT 24
Peak memory 183744 kb
Host smart-6fe2f6e0-69b2-4d0e-abb6-b5ad92a0bb7f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101254865 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.2101254865
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.3665048475
Short name T414
Test name
Test status
Simulation time 348896506 ps
CPU time 0.65 seconds
Started Apr 04 12:29:04 PM PDT 24
Finished Apr 04 12:29:05 PM PDT 24
Peak memory 183412 kb
Host smart-3be26ffc-51d4-4067-aea5-af79ab5bb8d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665048475 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.3665048475
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.3716464712
Short name T397
Test name
Test status
Simulation time 1367675327 ps
CPU time 3.98 seconds
Started Apr 04 12:27:49 PM PDT 24
Finished Apr 04 12:27:53 PM PDT 24
Peak memory 193064 kb
Host smart-341bb446-a691-4d50-90e9-9a993a4c6655
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716464712 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon
_timer_same_csr_outstanding.3716464712
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.2331982114
Short name T333
Test name
Test status
Simulation time 594656940 ps
CPU time 2.85 seconds
Started Apr 04 12:27:48 PM PDT 24
Finished Apr 04 12:27:51 PM PDT 24
Peak memory 198300 kb
Host smart-ae57d509-0805-4a43-84f4-c8d3afaa56d6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331982114 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.2331982114
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.2105880471
Short name T97
Test name
Test status
Simulation time 4503826601 ps
CPU time 3.36 seconds
Started Apr 04 12:27:50 PM PDT 24
Finished Apr 04 12:27:53 PM PDT 24
Peak memory 196136 kb
Host smart-7e199b33-aaa0-4f0b-bb25-977bac497fa1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105880471 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl
_intg_err.2105880471
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.1358488805
Short name T291
Test name
Test status
Simulation time 710255397 ps
CPU time 0.92 seconds
Started Apr 04 12:28:49 PM PDT 24
Finished Apr 04 12:28:51 PM PDT 24
Peak memory 195880 kb
Host smart-3fc2ade1-0a63-4229-a11d-ddceb99d226a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358488805 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.1358488805
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.1999726102
Short name T53
Test name
Test status
Simulation time 500692412 ps
CPU time 0.69 seconds
Started Apr 04 12:27:47 PM PDT 24
Finished Apr 04 12:27:48 PM PDT 24
Peak memory 183584 kb
Host smart-8711c3dc-68a1-4a64-a2e1-0781f883f072
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999726102 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.1999726102
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.3379795551
Short name T302
Test name
Test status
Simulation time 299934545 ps
CPU time 0.6 seconds
Started Apr 04 12:27:45 PM PDT 24
Finished Apr 04 12:27:46 PM PDT 24
Peak memory 182676 kb
Host smart-ab201bae-5f56-4ea2-aa6b-832a47b5247a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379795551 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.3379795551
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.2165172002
Short name T386
Test name
Test status
Simulation time 1737317980 ps
CPU time 1.9 seconds
Started Apr 04 12:27:37 PM PDT 24
Finished Apr 04 12:27:39 PM PDT 24
Peak memory 193428 kb
Host smart-7413370a-1e2e-4e61-8c1a-1d4785933614
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165172002 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon
_timer_same_csr_outstanding.2165172002
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.1705911080
Short name T390
Test name
Test status
Simulation time 655636640 ps
CPU time 2.31 seconds
Started Apr 04 12:27:44 PM PDT 24
Finished Apr 04 12:27:46 PM PDT 24
Peak memory 198660 kb
Host smart-26c7b6f8-9dd3-4669-b4f0-8b2db835ac89
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705911080 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.1705911080
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.1786137659
Short name T316
Test name
Test status
Simulation time 8392270020 ps
CPU time 15.11 seconds
Started Apr 04 12:27:43 PM PDT 24
Finished Apr 04 12:27:58 PM PDT 24
Peak memory 197936 kb
Host smart-c4f3ddd8-40a3-4c07-9086-2d44bcb7257a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786137659 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl
_intg_err.1786137659
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.961827696
Short name T403
Test name
Test status
Simulation time 383150403 ps
CPU time 0.78 seconds
Started Apr 04 12:27:45 PM PDT 24
Finished Apr 04 12:27:46 PM PDT 24
Peak memory 193472 kb
Host smart-84d5b728-7309-43c6-b265-e784556e998a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961827696 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.961827696
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.1566273018
Short name T420
Test name
Test status
Simulation time 329131799 ps
CPU time 0.88 seconds
Started Apr 04 12:28:49 PM PDT 24
Finished Apr 04 12:28:50 PM PDT 24
Peak memory 191380 kb
Host smart-cb3e1e74-a296-430a-967f-29aad4057366
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566273018 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.1566273018
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.2700177298
Short name T380
Test name
Test status
Simulation time 417756296 ps
CPU time 1.1 seconds
Started Apr 04 12:27:49 PM PDT 24
Finished Apr 04 12:27:50 PM PDT 24
Peak memory 183704 kb
Host smart-c688e612-2d24-4b28-b55c-d695bcf64b4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700177298 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.2700177298
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.2821011394
Short name T379
Test name
Test status
Simulation time 1507938617 ps
CPU time 1.76 seconds
Started Apr 04 12:27:46 PM PDT 24
Finished Apr 04 12:27:48 PM PDT 24
Peak memory 192644 kb
Host smart-85e3ff2f-0684-44bf-b059-09609aa3e104
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821011394 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon
_timer_same_csr_outstanding.2821011394
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.3198741177
Short name T340
Test name
Test status
Simulation time 855229907 ps
CPU time 2.51 seconds
Started Apr 04 12:27:44 PM PDT 24
Finished Apr 04 12:27:46 PM PDT 24
Peak memory 198620 kb
Host smart-d790b301-8cf0-4dc2-9dae-4dd6e67f9acd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198741177 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.3198741177
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.2399600952
Short name T294
Test name
Test status
Simulation time 7850206245 ps
CPU time 13.86 seconds
Started Apr 04 12:27:48 PM PDT 24
Finished Apr 04 12:28:02 PM PDT 24
Peak memory 198048 kb
Host smart-bd7c11fa-923e-44b3-9afa-f0b883df0b93
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399600952 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl
_intg_err.2399600952
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.10838250
Short name T417
Test name
Test status
Simulation time 621978303 ps
CPU time 1.14 seconds
Started Apr 04 12:28:49 PM PDT 24
Finished Apr 04 12:28:51 PM PDT 24
Peak memory 197100 kb
Host smart-79023666-f9c2-45df-a88c-8ce627fc6f12
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10838250 -assert nopostproc +UVM_TESTNAME=a
on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.10838250
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.3374257942
Short name T71
Test name
Test status
Simulation time 513944920 ps
CPU time 1.36 seconds
Started Apr 04 12:27:56 PM PDT 24
Finished Apr 04 12:27:58 PM PDT 24
Peak memory 183732 kb
Host smart-ada335df-ef7b-49be-aa2e-58b1e0d0ae53
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374257942 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.3374257942
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.890037041
Short name T299
Test name
Test status
Simulation time 492073162 ps
CPU time 0.72 seconds
Started Apr 04 12:27:51 PM PDT 24
Finished Apr 04 12:27:52 PM PDT 24
Peak memory 183696 kb
Host smart-4dea8d60-ede3-4edf-8f96-fa41cd55984c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890037041 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.890037041
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.355537490
Short name T396
Test name
Test status
Simulation time 1432405951 ps
CPU time 1.6 seconds
Started Apr 04 12:27:48 PM PDT 24
Finished Apr 04 12:27:50 PM PDT 24
Peak memory 193284 kb
Host smart-dd02642b-64d2-43a1-a245-db86b4d2684b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355537490 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_
timer_same_csr_outstanding.355537490
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.4239808709
Short name T313
Test name
Test status
Simulation time 647964818 ps
CPU time 1.52 seconds
Started Apr 04 12:27:44 PM PDT 24
Finished Apr 04 12:27:45 PM PDT 24
Peak memory 198672 kb
Host smart-a5e40493-01bb-4ab9-90a7-48cef3dc79e7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239808709 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.4239808709
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.369046940
Short name T409
Test name
Test status
Simulation time 4543750142 ps
CPU time 2.66 seconds
Started Apr 04 12:27:46 PM PDT 24
Finished Apr 04 12:27:49 PM PDT 24
Peak memory 197528 kb
Host smart-4b791300-7a93-4d08-ba97-97bb48137d10
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369046940 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_
intg_err.369046940
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_jump.2033396616
Short name T134
Test name
Test status
Simulation time 426598614 ps
CPU time 1.17 seconds
Started Apr 04 02:47:27 PM PDT 24
Finished Apr 04 02:47:30 PM PDT 24
Peak memory 183220 kb
Host smart-5478623d-1b3d-4ead-8e0c-d43e8683142e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033396616 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.2033396616
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.449209342
Short name T269
Test name
Test status
Simulation time 12068939407 ps
CPU time 9.15 seconds
Started Apr 04 02:47:34 PM PDT 24
Finished Apr 04 02:47:43 PM PDT 24
Peak memory 183352 kb
Host smart-5f5d7d20-5cc9-483a-bbc7-5964a948e071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449209342 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.449209342
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.4230600846
Short name T257
Test name
Test status
Simulation time 577925964 ps
CPU time 0.72 seconds
Started Apr 04 02:47:34 PM PDT 24
Finished Apr 04 02:47:35 PM PDT 24
Peak memory 183284 kb
Host smart-0e58bc83-5807-41e4-bd41-7e13eff1b463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230600846 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.4230600846
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.2841086588
Short name T122
Test name
Test status
Simulation time 98281059826 ps
CPU time 135.8 seconds
Started Apr 04 02:47:34 PM PDT 24
Finished Apr 04 02:49:50 PM PDT 24
Peak memory 193948 kb
Host smart-19dfae20-1fad-4ab0-b9be-859f50545b8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841086588 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_a
ll.2841086588
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.358068755
Short name T82
Test name
Test status
Simulation time 206555643843 ps
CPU time 244.41 seconds
Started Apr 04 02:47:30 PM PDT 24
Finished Apr 04 02:51:35 PM PDT 24
Peak memory 198212 kb
Host smart-08e2b716-e2d2-48bd-93db-e10dd0b7c8e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358068755 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.358068755
Directory /workspace/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.aon_timer_jump.3520038593
Short name T99
Test name
Test status
Simulation time 586857707 ps
CPU time 0.97 seconds
Started Apr 04 02:47:31 PM PDT 24
Finished Apr 04 02:47:32 PM PDT 24
Peak memory 183184 kb
Host smart-8d0462c5-194f-4b9a-8132-91117b5a294b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520038593 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.3520038593
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.220134135
Short name T175
Test name
Test status
Simulation time 11463568946 ps
CPU time 17.96 seconds
Started Apr 04 02:47:26 PM PDT 24
Finished Apr 04 02:47:44 PM PDT 24
Peak memory 183336 kb
Host smart-34f658cd-4fbd-41ef-96b9-9ca4b48888f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220134135 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.220134135
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.4206657055
Short name T19
Test name
Test status
Simulation time 8722324992 ps
CPU time 3.75 seconds
Started Apr 04 02:47:28 PM PDT 24
Finished Apr 04 02:47:33 PM PDT 24
Peak memory 215204 kb
Host smart-92c45548-2eb3-4c0f-ba94-37ed3928adf8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206657055 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.4206657055
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.1399255915
Short name T203
Test name
Test status
Simulation time 372468284 ps
CPU time 1.01 seconds
Started Apr 04 02:47:26 PM PDT 24
Finished Apr 04 02:47:28 PM PDT 24
Peak memory 183204 kb
Host smart-c6c3feb5-eaa4-4185-80ed-43e73a98bf27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399255915 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.1399255915
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.718615020
Short name T132
Test name
Test status
Simulation time 223796310633 ps
CPU time 286.54 seconds
Started Apr 04 02:47:32 PM PDT 24
Finished Apr 04 02:52:19 PM PDT 24
Peak memory 193868 kb
Host smart-776822c5-b30c-4e11-a595-8cb7ab89e8d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718615020 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_al
l.718615020
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/10.aon_timer_jump.1664221316
Short name T149
Test name
Test status
Simulation time 383111510 ps
CPU time 0.71 seconds
Started Apr 04 02:47:42 PM PDT 24
Finished Apr 04 02:47:44 PM PDT 24
Peak memory 183276 kb
Host smart-4c730dbf-8df0-4fe0-8e6d-1396fd7a8a0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664221316 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.1664221316
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.4263601539
Short name T261
Test name
Test status
Simulation time 27671693880 ps
CPU time 18.83 seconds
Started Apr 04 02:47:36 PM PDT 24
Finished Apr 04 02:47:55 PM PDT 24
Peak memory 183336 kb
Host smart-fb99ede4-50ae-4898-9f78-717ad2f4325f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263601539 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.4263601539
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.1917115296
Short name T174
Test name
Test status
Simulation time 372837879 ps
CPU time 1.15 seconds
Started Apr 04 02:47:41 PM PDT 24
Finished Apr 04 02:47:43 PM PDT 24
Peak memory 183260 kb
Host smart-4b77b170-56fe-4c58-97dd-ecf35dc014f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917115296 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.1917115296
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.2888292710
Short name T92
Test name
Test status
Simulation time 212222696823 ps
CPU time 302.84 seconds
Started Apr 04 02:47:37 PM PDT 24
Finished Apr 04 02:52:40 PM PDT 24
Peak memory 183360 kb
Host smart-1a9135f1-71c8-4e62-9588-3afc9813182d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888292710 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_
all.2888292710
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_jump.3814234971
Short name T116
Test name
Test status
Simulation time 397240499 ps
CPU time 1.18 seconds
Started Apr 04 02:47:36 PM PDT 24
Finished Apr 04 02:47:38 PM PDT 24
Peak memory 183296 kb
Host smart-1e8b1087-0cd8-4614-96d3-feaef6c6f7b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814234971 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.3814234971
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.686877253
Short name T128
Test name
Test status
Simulation time 9383330517 ps
CPU time 9.04 seconds
Started Apr 04 02:47:42 PM PDT 24
Finished Apr 04 02:47:51 PM PDT 24
Peak memory 183360 kb
Host smart-07aa098a-bff5-4e30-897c-cceadc2cd20b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686877253 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.686877253
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.1020955815
Short name T141
Test name
Test status
Simulation time 444463389 ps
CPU time 0.86 seconds
Started Apr 04 02:47:41 PM PDT 24
Finished Apr 04 02:47:42 PM PDT 24
Peak memory 183292 kb
Host smart-84c3bdd1-88e6-4051-9350-767918d23f33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020955815 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.1020955815
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.415152472
Short name T89
Test name
Test status
Simulation time 197835875151 ps
CPU time 302.86 seconds
Started Apr 04 02:47:38 PM PDT 24
Finished Apr 04 02:52:41 PM PDT 24
Peak memory 183312 kb
Host smart-23876ae4-a86c-4f00-94db-4ad394742cc7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415152472 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_a
ll.415152472
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_jump.1715181703
Short name T151
Test name
Test status
Simulation time 430613691 ps
CPU time 0.66 seconds
Started Apr 04 02:47:45 PM PDT 24
Finished Apr 04 02:47:46 PM PDT 24
Peak memory 183244 kb
Host smart-2f1154e1-ef6d-4e06-be0d-9324e0517c1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715181703 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.1715181703
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.410020375
Short name T107
Test name
Test status
Simulation time 56771042300 ps
CPU time 44.23 seconds
Started Apr 04 02:47:38 PM PDT 24
Finished Apr 04 02:48:22 PM PDT 24
Peak memory 183308 kb
Host smart-6009b56e-6463-4fce-b5a9-dd6834bc9b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410020375 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.410020375
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.3288908255
Short name T227
Test name
Test status
Simulation time 334298587 ps
CPU time 1.11 seconds
Started Apr 04 02:47:41 PM PDT 24
Finished Apr 04 02:47:43 PM PDT 24
Peak memory 183260 kb
Host smart-8ef485bc-1df0-4bfb-bf47-4c3e27dd1fce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288908255 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.3288908255
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.551334703
Short name T60
Test name
Test status
Simulation time 189436821117 ps
CPU time 76.27 seconds
Started Apr 04 02:47:45 PM PDT 24
Finished Apr 04 02:49:01 PM PDT 24
Peak memory 183456 kb
Host smart-ed8e3f21-5578-473b-9fb1-dd2b760038a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551334703 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_a
ll.551334703
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/13.aon_timer_jump.2456045514
Short name T229
Test name
Test status
Simulation time 390549499 ps
CPU time 0.83 seconds
Started Apr 04 02:47:40 PM PDT 24
Finished Apr 04 02:47:40 PM PDT 24
Peak memory 183296 kb
Host smart-cc2c4666-d101-4be7-85b1-04be6c1525d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456045514 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.2456045514
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.1340803425
Short name T254
Test name
Test status
Simulation time 11443386261 ps
CPU time 18.92 seconds
Started Apr 04 02:47:46 PM PDT 24
Finished Apr 04 02:48:06 PM PDT 24
Peak memory 183316 kb
Host smart-724f1c17-c0f2-4faf-990d-37bb848c257d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340803425 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.1340803425
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.3718885015
Short name T166
Test name
Test status
Simulation time 505322987 ps
CPU time 1.24 seconds
Started Apr 04 02:47:38 PM PDT 24
Finished Apr 04 02:47:40 PM PDT 24
Peak memory 183212 kb
Host smart-66e84fc6-a90a-43bd-ba41-6455d8fd1735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718885015 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.3718885015
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.690120320
Short name T196
Test name
Test status
Simulation time 109843707501 ps
CPU time 40.41 seconds
Started Apr 04 02:47:40 PM PDT 24
Finished Apr 04 02:48:21 PM PDT 24
Peak memory 183360 kb
Host smart-d274661c-1fd0-4125-ba74-c05624b5b1c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690120320 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_a
ll.690120320
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_jump.944939334
Short name T184
Test name
Test status
Simulation time 388832055 ps
CPU time 0.82 seconds
Started Apr 04 02:47:42 PM PDT 24
Finished Apr 04 02:47:44 PM PDT 24
Peak memory 183292 kb
Host smart-c5991784-de64-4a5f-b715-e703a3a679ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944939334 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.944939334
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.1067985445
Short name T194
Test name
Test status
Simulation time 17240677647 ps
CPU time 5.41 seconds
Started Apr 04 02:47:45 PM PDT 24
Finished Apr 04 02:47:50 PM PDT 24
Peak memory 183312 kb
Host smart-49ee4d7e-cb9d-44c3-89f8-f5384827741c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067985445 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.1067985445
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.2269184988
Short name T248
Test name
Test status
Simulation time 609380016 ps
CPU time 0.69 seconds
Started Apr 04 02:47:37 PM PDT 24
Finished Apr 04 02:47:37 PM PDT 24
Peak memory 183276 kb
Host smart-35bb6b76-afca-48a0-bbc1-13aace2bf11d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269184988 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.2269184988
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.1308288560
Short name T273
Test name
Test status
Simulation time 175914677846 ps
CPU time 47.53 seconds
Started Apr 04 02:47:39 PM PDT 24
Finished Apr 04 02:48:26 PM PDT 24
Peak memory 194604 kb
Host smart-276cc59d-6810-497d-b370-19b58a06d429
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308288560 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_
all.1308288560
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.3353886354
Short name T81
Test name
Test status
Simulation time 53406110375 ps
CPU time 199.61 seconds
Started Apr 04 02:47:36 PM PDT 24
Finished Apr 04 02:50:56 PM PDT 24
Peak memory 198244 kb
Host smart-f9d08d16-3231-4f89-adfa-fb1491f3e17a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353886354 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.3353886354
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.aon_timer_jump.1336572318
Short name T202
Test name
Test status
Simulation time 574186501 ps
CPU time 1.53 seconds
Started Apr 04 02:47:37 PM PDT 24
Finished Apr 04 02:47:39 PM PDT 24
Peak memory 183220 kb
Host smart-e1484b66-3dd4-460f-adac-74cc7d5c34d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336572318 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.1336572318
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.3923876878
Short name T139
Test name
Test status
Simulation time 43791873587 ps
CPU time 32.11 seconds
Started Apr 04 02:47:36 PM PDT 24
Finished Apr 04 02:48:08 PM PDT 24
Peak memory 183364 kb
Host smart-04925bb1-b13d-4268-8860-87c1d35a66de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923876878 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.3923876878
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.145195573
Short name T137
Test name
Test status
Simulation time 444593049 ps
CPU time 0.67 seconds
Started Apr 04 02:47:38 PM PDT 24
Finished Apr 04 02:47:39 PM PDT 24
Peak memory 183216 kb
Host smart-6d42b80d-b7ea-4252-bc47-0e4ba5240edb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145195573 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.145195573
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.1449839174
Short name T181
Test name
Test status
Simulation time 39652918721 ps
CPU time 31.56 seconds
Started Apr 04 02:47:40 PM PDT 24
Finished Apr 04 02:48:12 PM PDT 24
Peak memory 183352 kb
Host smart-d36853df-31c7-4182-acbf-c1adf37bb5de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449839174 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_
all.1449839174
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.1009314626
Short name T114
Test name
Test status
Simulation time 22380084153 ps
CPU time 186.72 seconds
Started Apr 04 02:47:38 PM PDT 24
Finished Apr 04 02:50:45 PM PDT 24
Peak memory 198340 kb
Host smart-fe53f828-4fe4-4004-a110-cdfe86d873f5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009314626 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.1009314626
Directory /workspace/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.aon_timer_jump.1007420436
Short name T138
Test name
Test status
Simulation time 480251782 ps
CPU time 1.23 seconds
Started Apr 04 02:47:46 PM PDT 24
Finished Apr 04 02:47:47 PM PDT 24
Peak memory 183244 kb
Host smart-45f969c3-754a-4cb7-af54-983ab6df7fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007420436 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.1007420436
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.1357587956
Short name T15
Test name
Test status
Simulation time 53156826956 ps
CPU time 20.39 seconds
Started Apr 04 02:47:37 PM PDT 24
Finished Apr 04 02:47:58 PM PDT 24
Peak memory 183368 kb
Host smart-e63a15e1-e59d-4fe7-8995-727cd44ae86c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357587956 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.1357587956
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.2185273257
Short name T266
Test name
Test status
Simulation time 415789113 ps
CPU time 0.59 seconds
Started Apr 04 02:47:46 PM PDT 24
Finished Apr 04 02:47:47 PM PDT 24
Peak memory 183248 kb
Host smart-fc5e3605-5e9b-4b81-8600-adcc86c9470c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185273257 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.2185273257
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.810447636
Short name T178
Test name
Test status
Simulation time 347276514928 ps
CPU time 458.26 seconds
Started Apr 04 02:47:38 PM PDT 24
Finished Apr 04 02:55:17 PM PDT 24
Peak memory 195096 kb
Host smart-8f10b4cf-5ba2-44a6-8b27-8bcad8c2957b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810447636 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_a
ll.810447636
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.351919044
Short name T38
Test name
Test status
Simulation time 242524622262 ps
CPU time 464.12 seconds
Started Apr 04 02:47:45 PM PDT 24
Finished Apr 04 02:55:29 PM PDT 24
Peak memory 198264 kb
Host smart-c70c381d-4c42-4ffc-a629-1764f87fd4e9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351919044 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.351919044
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.aon_timer_jump.4099210121
Short name T233
Test name
Test status
Simulation time 568503702 ps
CPU time 0.94 seconds
Started Apr 04 02:47:41 PM PDT 24
Finished Apr 04 02:47:42 PM PDT 24
Peak memory 183216 kb
Host smart-d17a1af5-37ed-455b-9fc6-775e269d7364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099210121 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.4099210121
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.1893168376
Short name T113
Test name
Test status
Simulation time 1445949191 ps
CPU time 1.45 seconds
Started Apr 04 02:47:40 PM PDT 24
Finished Apr 04 02:47:41 PM PDT 24
Peak memory 183288 kb
Host smart-4a1bb6d3-786d-4c2d-a9f3-af7e663b25cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893168376 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.1893168376
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.3724759105
Short name T169
Test name
Test status
Simulation time 569504628 ps
CPU time 1.35 seconds
Started Apr 04 02:47:43 PM PDT 24
Finished Apr 04 02:47:44 PM PDT 24
Peak memory 183288 kb
Host smart-e09efb8b-29ab-4149-8501-e8d1a32f7158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724759105 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.3724759105
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.1974511187
Short name T129
Test name
Test status
Simulation time 275835654852 ps
CPU time 411.18 seconds
Started Apr 04 02:47:41 PM PDT 24
Finished Apr 04 02:54:33 PM PDT 24
Peak memory 195160 kb
Host smart-ac3dee3f-a369-4008-b7da-c7e5f42d3b00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974511187 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_
all.1974511187
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.4091400051
Short name T182
Test name
Test status
Simulation time 63798046431 ps
CPU time 149.86 seconds
Started Apr 04 02:47:41 PM PDT 24
Finished Apr 04 02:50:11 PM PDT 24
Peak memory 198216 kb
Host smart-9aa22cce-c8b7-4dff-8626-41d5d8722c2c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091400051 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.4091400051
Directory /workspace/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.aon_timer_jump.2372985028
Short name T23
Test name
Test status
Simulation time 629246932 ps
CPU time 1.44 seconds
Started Apr 04 02:47:41 PM PDT 24
Finished Apr 04 02:47:42 PM PDT 24
Peak memory 183216 kb
Host smart-fd7cd3ca-b7fb-4d4b-97b1-ad804617eb50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372985028 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.2372985028
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.1172365996
Short name T232
Test name
Test status
Simulation time 30520031661 ps
CPU time 12.59 seconds
Started Apr 04 02:47:45 PM PDT 24
Finished Apr 04 02:47:58 PM PDT 24
Peak memory 183316 kb
Host smart-3a477476-6f09-4d0a-9f03-e34cbf6275e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172365996 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.1172365996
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.602524659
Short name T234
Test name
Test status
Simulation time 357423133 ps
CPU time 0.82 seconds
Started Apr 04 02:47:40 PM PDT 24
Finished Apr 04 02:47:40 PM PDT 24
Peak memory 183304 kb
Host smart-f91eb255-34fc-4a5d-9908-4a5b0bd37cca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602524659 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.602524659
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.944989889
Short name T27
Test name
Test status
Simulation time 19088385954 ps
CPU time 31.5 seconds
Started Apr 04 02:48:00 PM PDT 24
Finished Apr 04 02:48:32 PM PDT 24
Peak memory 194356 kb
Host smart-5bc9769b-9670-4e69-85d5-ca16f68615ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944989889 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_a
ll.944989889
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.3675205567
Short name T32
Test name
Test status
Simulation time 16152043528 ps
CPU time 96.55 seconds
Started Apr 04 02:47:41 PM PDT 24
Finished Apr 04 02:49:18 PM PDT 24
Peak memory 198212 kb
Host smart-64909f0b-4d3e-467d-9c76-09fbe9cdfff2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675205567 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.3675205567
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.aon_timer_jump.1869784407
Short name T105
Test name
Test status
Simulation time 353521108 ps
CPU time 1.15 seconds
Started Apr 04 02:47:57 PM PDT 24
Finished Apr 04 02:47:58 PM PDT 24
Peak memory 183284 kb
Host smart-9bbd0d00-080b-4471-8e0e-edbd515de26e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869784407 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.1869784407
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.407156148
Short name T168
Test name
Test status
Simulation time 16011292843 ps
CPU time 6.1 seconds
Started Apr 04 02:47:53 PM PDT 24
Finished Apr 04 02:48:00 PM PDT 24
Peak memory 183280 kb
Host smart-618fa5a2-7191-4c7d-8246-3f80ced39cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407156148 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.407156148
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.980622403
Short name T30
Test name
Test status
Simulation time 517733049 ps
CPU time 1.36 seconds
Started Apr 04 02:48:00 PM PDT 24
Finished Apr 04 02:48:01 PM PDT 24
Peak memory 183312 kb
Host smart-9718944c-16d0-414f-b945-fe89931af0eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980622403 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.980622403
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.3653655539
Short name T140
Test name
Test status
Simulation time 16394573545 ps
CPU time 167.93 seconds
Started Apr 04 02:47:55 PM PDT 24
Finished Apr 04 02:50:44 PM PDT 24
Peak memory 198304 kb
Host smart-caafb8dd-adff-4bbf-b04b-a6f6fc7f9946
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653655539 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.3653655539
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_jump.2937539007
Short name T124
Test name
Test status
Simulation time 379642783 ps
CPU time 0.83 seconds
Started Apr 04 02:47:32 PM PDT 24
Finished Apr 04 02:47:33 PM PDT 24
Peak memory 183388 kb
Host smart-215c6213-3a15-4671-9b83-39053cbf6992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937539007 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.2937539007
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.3240645733
Short name T142
Test name
Test status
Simulation time 10754355342 ps
CPU time 16.64 seconds
Started Apr 04 02:47:33 PM PDT 24
Finished Apr 04 02:47:49 PM PDT 24
Peak memory 183300 kb
Host smart-a7e3e695-dacb-439d-a7c1-8d7d2c366c4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240645733 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.3240645733
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.4248836716
Short name T22
Test name
Test status
Simulation time 4215601691 ps
CPU time 3.69 seconds
Started Apr 04 02:47:25 PM PDT 24
Finished Apr 04 02:47:29 PM PDT 24
Peak memory 215028 kb
Host smart-0ec2da47-ee12-4a3f-af6e-695ebc7cd36f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248836716 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.4248836716
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.1291839728
Short name T250
Test name
Test status
Simulation time 596174792 ps
CPU time 0.95 seconds
Started Apr 04 02:47:34 PM PDT 24
Finished Apr 04 02:47:35 PM PDT 24
Peak memory 183308 kb
Host smart-958f4a1a-5292-4b62-b9f3-61dda2993101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291839728 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.1291839728
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.1225417499
Short name T93
Test name
Test status
Simulation time 186828564243 ps
CPU time 63.79 seconds
Started Apr 04 02:47:34 PM PDT 24
Finished Apr 04 02:48:38 PM PDT 24
Peak memory 183544 kb
Host smart-d4f426c6-1e64-4940-80e0-8f29dca0ca79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225417499 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_a
ll.1225417499
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.565358979
Short name T41
Test name
Test status
Simulation time 43629741690 ps
CPU time 309.01 seconds
Started Apr 04 02:47:32 PM PDT 24
Finished Apr 04 02:52:42 PM PDT 24
Peak memory 198316 kb
Host smart-da07bfbf-b893-48d9-968e-452e51fa934b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565358979 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.565358979
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.aon_timer_jump.1333182120
Short name T5
Test name
Test status
Simulation time 506775562 ps
CPU time 0.74 seconds
Started Apr 04 02:47:57 PM PDT 24
Finished Apr 04 02:47:58 PM PDT 24
Peak memory 183312 kb
Host smart-b06c7161-5b33-44d7-9e57-3f39d8df50db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333182120 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.1333182120
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.111321871
Short name T157
Test name
Test status
Simulation time 55316613709 ps
CPU time 23.27 seconds
Started Apr 04 02:47:55 PM PDT 24
Finished Apr 04 02:48:19 PM PDT 24
Peak memory 183344 kb
Host smart-9d558adf-3842-4f33-a6b3-73d151e7cf56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111321871 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.111321871
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.283373624
Short name T190
Test name
Test status
Simulation time 516904040 ps
CPU time 0.76 seconds
Started Apr 04 02:47:56 PM PDT 24
Finished Apr 04 02:47:57 PM PDT 24
Peak memory 183268 kb
Host smart-17d16212-833e-47da-a992-defd857838e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283373624 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.283373624
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.1424177834
Short name T102
Test name
Test status
Simulation time 57811494425 ps
CPU time 22.54 seconds
Started Apr 04 02:47:53 PM PDT 24
Finished Apr 04 02:48:16 PM PDT 24
Peak memory 183364 kb
Host smart-cac8deb0-f144-410d-9145-e0b678dad4ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424177834 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_
all.1424177834
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.1180789457
Short name T76
Test name
Test status
Simulation time 65682608532 ps
CPU time 340.33 seconds
Started Apr 04 02:47:54 PM PDT 24
Finished Apr 04 02:53:35 PM PDT 24
Peak memory 198272 kb
Host smart-8ade4ea4-14fb-48de-8bf3-d336f6b3884e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180789457 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.1180789457
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_jump.2530709428
Short name T146
Test name
Test status
Simulation time 471203146 ps
CPU time 1.3 seconds
Started Apr 04 02:47:56 PM PDT 24
Finished Apr 04 02:47:57 PM PDT 24
Peak memory 183144 kb
Host smart-2ac4b976-4223-4ee4-946d-f11a6ea7cb3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530709428 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.2530709428
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.1997262444
Short name T119
Test name
Test status
Simulation time 4835160707 ps
CPU time 2.24 seconds
Started Apr 04 02:47:55 PM PDT 24
Finished Apr 04 02:47:58 PM PDT 24
Peak memory 183364 kb
Host smart-12ff0a4b-607c-4c33-91d1-f4d3b213709d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997262444 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.1997262444
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.949062577
Short name T245
Test name
Test status
Simulation time 567394721 ps
CPU time 0.73 seconds
Started Apr 04 02:47:54 PM PDT 24
Finished Apr 04 02:47:55 PM PDT 24
Peak memory 183244 kb
Host smart-98a04238-dbce-4659-bd4b-c240e0b20511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949062577 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.949062577
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.2600750006
Short name T173
Test name
Test status
Simulation time 154446046306 ps
CPU time 237.03 seconds
Started Apr 04 02:47:55 PM PDT 24
Finished Apr 04 02:51:52 PM PDT 24
Peak memory 194580 kb
Host smart-dfcbb1a2-1227-4f88-90c3-7204bf3eee4c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600750006 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_
all.2600750006
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_jump.2810898404
Short name T219
Test name
Test status
Simulation time 511827350 ps
CPU time 0.97 seconds
Started Apr 04 02:47:58 PM PDT 24
Finished Apr 04 02:47:59 PM PDT 24
Peak memory 182904 kb
Host smart-a033d56a-a624-417e-94f0-1d1a3609cc6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810898404 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.2810898404
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.2758776486
Short name T239
Test name
Test status
Simulation time 58588282715 ps
CPU time 90.63 seconds
Started Apr 04 02:47:58 PM PDT 24
Finished Apr 04 02:49:29 PM PDT 24
Peak memory 183360 kb
Host smart-0b8af11e-14ee-4e49-8e1c-c004f911c6cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758776486 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.2758776486
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.2850822322
Short name T216
Test name
Test status
Simulation time 471683606 ps
CPU time 0.97 seconds
Started Apr 04 02:48:00 PM PDT 24
Finished Apr 04 02:48:01 PM PDT 24
Peak memory 183236 kb
Host smart-a4d7f11c-e9e1-47c9-9382-10fa81d7d119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850822322 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.2850822322
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.2083101983
Short name T214
Test name
Test status
Simulation time 39871583862 ps
CPU time 17.17 seconds
Started Apr 04 02:47:56 PM PDT 24
Finished Apr 04 02:48:13 PM PDT 24
Peak memory 183368 kb
Host smart-89ffb3aa-96f7-48cf-a85a-3d060f6471e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083101983 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_
all.2083101983
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.2289173307
Short name T130
Test name
Test status
Simulation time 42425784669 ps
CPU time 468.31 seconds
Started Apr 04 02:47:54 PM PDT 24
Finished Apr 04 02:55:42 PM PDT 24
Peak memory 198320 kb
Host smart-1cd9b6bc-380f-4e19-98df-e2174fbe9894
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289173307 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.2289173307
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.aon_timer_jump.3750950608
Short name T218
Test name
Test status
Simulation time 409067165 ps
CPU time 1.21 seconds
Started Apr 04 02:47:57 PM PDT 24
Finished Apr 04 02:47:59 PM PDT 24
Peak memory 183276 kb
Host smart-c647af30-37ae-4dd3-9e59-de721ccb42a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750950608 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.3750950608
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.3562471453
Short name T13
Test name
Test status
Simulation time 32457389348 ps
CPU time 13.01 seconds
Started Apr 04 02:47:56 PM PDT 24
Finished Apr 04 02:48:09 PM PDT 24
Peak memory 183352 kb
Host smart-c682a7d8-f315-4c50-b8ba-9c3db35789db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562471453 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.3562471453
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.238824514
Short name T100
Test name
Test status
Simulation time 469757730 ps
CPU time 0.83 seconds
Started Apr 04 02:47:59 PM PDT 24
Finished Apr 04 02:48:00 PM PDT 24
Peak memory 183244 kb
Host smart-76925b45-946a-4762-9bf0-bbf963ac765c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238824514 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.238824514
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.1785327226
Short name T235
Test name
Test status
Simulation time 78162191559 ps
CPU time 600.73 seconds
Started Apr 04 02:47:57 PM PDT 24
Finished Apr 04 02:57:58 PM PDT 24
Peak memory 199028 kb
Host smart-4a6d7283-4c66-43f0-ac0f-ecb6b4c5026b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785327226 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.1785327226
Directory /workspace/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.aon_timer_jump.1745998648
Short name T108
Test name
Test status
Simulation time 440930086 ps
CPU time 0.68 seconds
Started Apr 04 02:47:56 PM PDT 24
Finished Apr 04 02:47:57 PM PDT 24
Peak memory 183280 kb
Host smart-99066029-4759-4af2-99d9-25fff5e4084f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745998648 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.1745998648
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.2652595645
Short name T86
Test name
Test status
Simulation time 8825891806 ps
CPU time 2.41 seconds
Started Apr 04 02:47:52 PM PDT 24
Finished Apr 04 02:47:55 PM PDT 24
Peak memory 183364 kb
Host smart-db59b4b9-1760-489b-ab33-f91c5da7b3c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652595645 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.2652595645
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.2993167663
Short name T28
Test name
Test status
Simulation time 496523648 ps
CPU time 0.92 seconds
Started Apr 04 02:47:54 PM PDT 24
Finished Apr 04 02:47:55 PM PDT 24
Peak memory 183240 kb
Host smart-b48e3ac8-3f03-4a89-9818-292de8706122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993167663 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.2993167663
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.875498232
Short name T217
Test name
Test status
Simulation time 36570715527 ps
CPU time 5.27 seconds
Started Apr 04 02:47:53 PM PDT 24
Finished Apr 04 02:47:58 PM PDT 24
Peak memory 193448 kb
Host smart-517e506e-2f7b-46f6-aae3-d0f0612b3628
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875498232 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_a
ll.875498232
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.3218980723
Short name T79
Test name
Test status
Simulation time 306161857735 ps
CPU time 701.26 seconds
Started Apr 04 02:47:56 PM PDT 24
Finished Apr 04 02:59:38 PM PDT 24
Peak memory 200904 kb
Host smart-4a573e08-6e67-4417-9ad6-389082b170c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218980723 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand_reset.3218980723
Directory /workspace/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.aon_timer_jump.456802366
Short name T223
Test name
Test status
Simulation time 557579848 ps
CPU time 1.41 seconds
Started Apr 04 02:47:55 PM PDT 24
Finished Apr 04 02:47:56 PM PDT 24
Peak memory 183352 kb
Host smart-908bcb5e-9b07-450b-b74a-bd6cf1a64afb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456802366 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.456802366
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.2302526448
Short name T91
Test name
Test status
Simulation time 35192256672 ps
CPU time 52.3 seconds
Started Apr 04 02:47:55 PM PDT 24
Finished Apr 04 02:48:47 PM PDT 24
Peak memory 183348 kb
Host smart-5b30c01e-c535-4a1f-b1ef-64e20cacb7bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302526448 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.2302526448
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.3502899752
Short name T255
Test name
Test status
Simulation time 537408107 ps
CPU time 1.26 seconds
Started Apr 04 02:47:54 PM PDT 24
Finished Apr 04 02:47:55 PM PDT 24
Peak memory 183280 kb
Host smart-b3f03874-a83c-49e0-9a5d-a2ff90f4575d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502899752 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.3502899752
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.2641240005
Short name T135
Test name
Test status
Simulation time 379797104355 ps
CPU time 308.26 seconds
Started Apr 04 02:47:59 PM PDT 24
Finished Apr 04 02:53:08 PM PDT 24
Peak memory 183328 kb
Host smart-5e045c66-a184-4043-aaa3-bf893dbb1d16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641240005 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_
all.2641240005
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.1457805861
Short name T43
Test name
Test status
Simulation time 27464392156 ps
CPU time 186.05 seconds
Started Apr 04 02:47:54 PM PDT 24
Finished Apr 04 02:51:00 PM PDT 24
Peak memory 198356 kb
Host smart-4acd59f2-df92-4050-9a99-2858a4bef95d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457805861 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.1457805861
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.aon_timer_jump.2982726482
Short name T147
Test name
Test status
Simulation time 465735930 ps
CPU time 0.74 seconds
Started Apr 04 02:47:53 PM PDT 24
Finished Apr 04 02:47:53 PM PDT 24
Peak memory 183268 kb
Host smart-7427e392-ee07-46f4-bb40-e8a0fcc84bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982726482 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.2982726482
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.1424327435
Short name T272
Test name
Test status
Simulation time 27160013387 ps
CPU time 40.56 seconds
Started Apr 04 02:47:56 PM PDT 24
Finished Apr 04 02:48:36 PM PDT 24
Peak memory 183328 kb
Host smart-a6ffd349-f670-48e1-9ebe-e335e6b8658e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424327435 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.1424327435
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.1701836921
Short name T171
Test name
Test status
Simulation time 593072439 ps
CPU time 1.44 seconds
Started Apr 04 02:47:56 PM PDT 24
Finished Apr 04 02:47:57 PM PDT 24
Peak memory 183260 kb
Host smart-81b3bc62-cb37-4908-97b2-150d872e8af7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701836921 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.1701836921
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.517470276
Short name T240
Test name
Test status
Simulation time 112432437727 ps
CPU time 79.38 seconds
Started Apr 04 02:47:53 PM PDT 24
Finished Apr 04 02:49:12 PM PDT 24
Peak memory 192912 kb
Host smart-d4cfa931-4289-49d0-940f-6dc02b3b2d42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517470276 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_a
ll.517470276
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.2638426909
Short name T64
Test name
Test status
Simulation time 80639597647 ps
CPU time 161.69 seconds
Started Apr 04 02:47:54 PM PDT 24
Finished Apr 04 02:50:36 PM PDT 24
Peak memory 206512 kb
Host smart-d11e94e8-d2c3-4471-a7ff-aef24f6b1cd8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638426909 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.2638426909
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_jump.2204743450
Short name T183
Test name
Test status
Simulation time 448099453 ps
CPU time 0.72 seconds
Started Apr 04 02:47:54 PM PDT 24
Finished Apr 04 02:47:54 PM PDT 24
Peak memory 183240 kb
Host smart-3e8037b7-b74d-4b1a-9b80-6f449b056ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204743450 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.2204743450
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.1897324723
Short name T164
Test name
Test status
Simulation time 17131370783 ps
CPU time 30.2 seconds
Started Apr 04 02:47:53 PM PDT 24
Finished Apr 04 02:48:24 PM PDT 24
Peak memory 183280 kb
Host smart-0eb4eeab-f054-4325-9bdb-c5c36621d75a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897324723 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.1897324723
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.336464203
Short name T123
Test name
Test status
Simulation time 347951986 ps
CPU time 1.01 seconds
Started Apr 04 02:47:52 PM PDT 24
Finished Apr 04 02:47:53 PM PDT 24
Peak memory 183260 kb
Host smart-7d2e26b0-a59b-4e5c-92a6-6827e3bfc8e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336464203 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.336464203
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.3271921447
Short name T90
Test name
Test status
Simulation time 289182906427 ps
CPU time 427.33 seconds
Started Apr 04 02:47:52 PM PDT 24
Finished Apr 04 02:54:59 PM PDT 24
Peak memory 193768 kb
Host smart-9393bca9-4486-4710-9e12-5a336fe4a5c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271921447 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_
all.3271921447
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.2720173273
Short name T225
Test name
Test status
Simulation time 238180459303 ps
CPU time 458.71 seconds
Started Apr 04 02:47:55 PM PDT 24
Finished Apr 04 02:55:34 PM PDT 24
Peak memory 198356 kb
Host smart-82f34f3d-48a4-48f5-8f7f-0b44a56c8c2b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720173273 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.2720173273
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_jump.1447641939
Short name T179
Test name
Test status
Simulation time 614247716 ps
CPU time 0.67 seconds
Started Apr 04 02:47:56 PM PDT 24
Finished Apr 04 02:47:57 PM PDT 24
Peak memory 183352 kb
Host smart-a7e8150a-25b3-49d7-b3c0-173bfd7d200e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447641939 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.1447641939
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.3704622622
Short name T193
Test name
Test status
Simulation time 20995394248 ps
CPU time 7.98 seconds
Started Apr 04 02:47:55 PM PDT 24
Finished Apr 04 02:48:04 PM PDT 24
Peak memory 183340 kb
Host smart-c4cf7410-e6f8-414c-bc80-f87ddd40cff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704622622 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.3704622622
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.3873165638
Short name T236
Test name
Test status
Simulation time 479665598 ps
CPU time 1.24 seconds
Started Apr 04 02:47:56 PM PDT 24
Finished Apr 04 02:47:57 PM PDT 24
Peak memory 183292 kb
Host smart-6b04723f-b5e0-4451-b719-d20eb8e142d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873165638 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.3873165638
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.1576521113
Short name T268
Test name
Test status
Simulation time 506557288530 ps
CPU time 202.12 seconds
Started Apr 04 02:47:59 PM PDT 24
Finished Apr 04 02:51:21 PM PDT 24
Peak memory 195108 kb
Host smart-2b039795-937c-42aa-a60d-5c523b95b279
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576521113 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_
all.1576521113
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.2133727601
Short name T39
Test name
Test status
Simulation time 25596722429 ps
CPU time 204.02 seconds
Started Apr 04 02:47:56 PM PDT 24
Finished Apr 04 02:51:21 PM PDT 24
Peak memory 198292 kb
Host smart-71d8dfe2-48e2-4716-b517-fe11614ce563
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133727601 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.2133727601
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.aon_timer_jump.2003468307
Short name T133
Test name
Test status
Simulation time 406478226 ps
CPU time 1.11 seconds
Started Apr 04 02:47:59 PM PDT 24
Finished Apr 04 02:48:00 PM PDT 24
Peak memory 183332 kb
Host smart-384e877b-dc5a-42c9-8911-167b1293cd73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003468307 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.2003468307
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.2223327246
Short name T187
Test name
Test status
Simulation time 36429968857 ps
CPU time 49.68 seconds
Started Apr 04 02:47:52 PM PDT 24
Finished Apr 04 02:48:42 PM PDT 24
Peak memory 183236 kb
Host smart-53ec556c-99b4-49af-8be3-52ebb97f24ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223327246 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.2223327246
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.1115212809
Short name T275
Test name
Test status
Simulation time 635448355 ps
CPU time 0.78 seconds
Started Apr 04 02:47:58 PM PDT 24
Finished Apr 04 02:47:58 PM PDT 24
Peak memory 183288 kb
Host smart-12d74762-02a2-4faa-9fe4-e79df506f13e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115212809 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.1115212809
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.4172626368
Short name T152
Test name
Test status
Simulation time 307836189518 ps
CPU time 46.75 seconds
Started Apr 04 02:47:55 PM PDT 24
Finished Apr 04 02:48:42 PM PDT 24
Peak memory 194768 kb
Host smart-7ed2028a-2763-4cd8-b4a7-604a9242f998
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172626368 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_
all.4172626368
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.3205165990
Short name T162
Test name
Test status
Simulation time 217368767176 ps
CPU time 667.71 seconds
Started Apr 04 02:47:56 PM PDT 24
Finished Apr 04 02:59:04 PM PDT 24
Peak memory 199864 kb
Host smart-20323f6b-ba0c-4811-85bc-45650465a0cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205165990 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.3205165990
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.aon_timer_jump.1009395526
Short name T9
Test name
Test status
Simulation time 534110042 ps
CPU time 0.96 seconds
Started Apr 04 02:47:32 PM PDT 24
Finished Apr 04 02:47:34 PM PDT 24
Peak memory 183372 kb
Host smart-8847fe0d-0ae5-418d-b7d4-4818ff9b1251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009395526 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.1009395526
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.2365458599
Short name T155
Test name
Test status
Simulation time 30202727845 ps
CPU time 4.87 seconds
Started Apr 04 02:47:27 PM PDT 24
Finished Apr 04 02:47:33 PM PDT 24
Peak memory 183400 kb
Host smart-e0d244d5-0fcb-430d-9ad1-b88e1ca954b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365458599 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.2365458599
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.296315097
Short name T18
Test name
Test status
Simulation time 4561245271 ps
CPU time 2.57 seconds
Started Apr 04 02:47:27 PM PDT 24
Finished Apr 04 02:47:31 PM PDT 24
Peak memory 215016 kb
Host smart-abbc40f2-df17-4faf-8978-906e6dd02ac8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296315097 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.296315097
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.1166190191
Short name T199
Test name
Test status
Simulation time 397621995 ps
CPU time 0.64 seconds
Started Apr 04 02:47:27 PM PDT 24
Finished Apr 04 02:47:30 PM PDT 24
Peak memory 183328 kb
Host smart-081c7e4f-279d-41ff-ab92-ba16c80d4dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166190191 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.1166190191
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.2943542637
Short name T189
Test name
Test status
Simulation time 81486142646 ps
CPU time 8.94 seconds
Started Apr 04 02:47:26 PM PDT 24
Finished Apr 04 02:47:35 PM PDT 24
Peak memory 195216 kb
Host smart-f5b9580f-1946-4010-9379-e18ab108a8c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943542637 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_a
ll.2943542637
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.1441428815
Short name T259
Test name
Test status
Simulation time 53852155052 ps
CPU time 156.44 seconds
Started Apr 04 02:47:33 PM PDT 24
Finished Apr 04 02:50:10 PM PDT 24
Peak memory 214048 kb
Host smart-22cb753f-4b38-4a3f-b93e-6dcbc3fb90f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441428815 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.1441428815
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_jump.1174287656
Short name T63
Test name
Test status
Simulation time 550706706 ps
CPU time 1.15 seconds
Started Apr 04 02:47:59 PM PDT 24
Finished Apr 04 02:48:00 PM PDT 24
Peak memory 183332 kb
Host smart-7aa649b4-06d2-477e-8540-a6e53d35a54a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174287656 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.1174287656
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.809347426
Short name T205
Test name
Test status
Simulation time 8967993195 ps
CPU time 6.77 seconds
Started Apr 04 02:47:59 PM PDT 24
Finished Apr 04 02:48:06 PM PDT 24
Peak memory 183304 kb
Host smart-345edc2d-147c-44cf-9dc9-043f7f7a41e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809347426 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.809347426
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.3831945523
Short name T241
Test name
Test status
Simulation time 367048508 ps
CPU time 0.8 seconds
Started Apr 04 02:47:59 PM PDT 24
Finished Apr 04 02:48:00 PM PDT 24
Peak memory 183312 kb
Host smart-61c80ca6-006b-4f4a-9d68-7ddeae510060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831945523 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.3831945523
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.2167276280
Short name T62
Test name
Test status
Simulation time 335917918885 ps
CPU time 195 seconds
Started Apr 04 02:47:58 PM PDT 24
Finished Apr 04 02:51:13 PM PDT 24
Peak memory 183244 kb
Host smart-8640c714-d6c9-4513-9d2b-7856934a73a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167276280 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_
all.2167276280
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_jump.3285565932
Short name T244
Test name
Test status
Simulation time 555791205 ps
CPU time 0.71 seconds
Started Apr 04 02:47:56 PM PDT 24
Finished Apr 04 02:47:57 PM PDT 24
Peak memory 183276 kb
Host smart-f5f7f2e1-b13e-46df-a7c5-8490541e2db8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285565932 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.3285565932
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.4026565803
Short name T88
Test name
Test status
Simulation time 18026285656 ps
CPU time 8.51 seconds
Started Apr 04 02:47:59 PM PDT 24
Finished Apr 04 02:48:07 PM PDT 24
Peak memory 183416 kb
Host smart-3e68e0de-25e8-4bdf-8fdd-1d48fa2a1d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026565803 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.4026565803
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.4206561775
Short name T195
Test name
Test status
Simulation time 403032398 ps
CPU time 1.19 seconds
Started Apr 04 02:47:56 PM PDT 24
Finished Apr 04 02:47:57 PM PDT 24
Peak memory 183216 kb
Host smart-a5c3e908-b589-45b5-8b14-eb55ce5e175a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206561775 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.4206561775
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.1908451904
Short name T267
Test name
Test status
Simulation time 132099339118 ps
CPU time 13.93 seconds
Started Apr 04 02:47:59 PM PDT 24
Finished Apr 04 02:48:13 PM PDT 24
Peak memory 194048 kb
Host smart-9d1ceed2-414b-4147-874e-29537a6492f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908451904 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_
all.1908451904
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.4260789817
Short name T263
Test name
Test status
Simulation time 40649645791 ps
CPU time 94.39 seconds
Started Apr 04 02:47:55 PM PDT 24
Finished Apr 04 02:49:30 PM PDT 24
Peak memory 198264 kb
Host smart-e48a19bb-a203-49bc-8384-83b93aafe501
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260789817 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.4260789817
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.aon_timer_jump.580710340
Short name T172
Test name
Test status
Simulation time 585599613 ps
CPU time 0.76 seconds
Started Apr 04 02:47:55 PM PDT 24
Finished Apr 04 02:47:56 PM PDT 24
Peak memory 183284 kb
Host smart-1b8843ec-552f-4458-a312-f02130a506db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580710340 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.580710340
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.4146305521
Short name T11
Test name
Test status
Simulation time 13583118361 ps
CPU time 6.34 seconds
Started Apr 04 02:47:55 PM PDT 24
Finished Apr 04 02:48:02 PM PDT 24
Peak memory 183364 kb
Host smart-ccfd5491-0074-40b0-b610-f962850d0dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146305521 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.4146305521
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.1215197452
Short name T117
Test name
Test status
Simulation time 508147760 ps
CPU time 1.31 seconds
Started Apr 04 02:47:58 PM PDT 24
Finished Apr 04 02:47:59 PM PDT 24
Peak memory 183196 kb
Host smart-1e673d01-4198-4d61-befe-25541887de54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215197452 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.1215197452
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.3643764496
Short name T209
Test name
Test status
Simulation time 140365616943 ps
CPU time 52.39 seconds
Started Apr 04 02:47:55 PM PDT 24
Finished Apr 04 02:48:47 PM PDT 24
Peak memory 183308 kb
Host smart-329c0470-6636-4d98-8d40-6bf932b89f91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643764496 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_
all.3643764496
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.3984543510
Short name T78
Test name
Test status
Simulation time 119271205305 ps
CPU time 327.06 seconds
Started Apr 04 02:47:55 PM PDT 24
Finished Apr 04 02:53:22 PM PDT 24
Peak memory 198280 kb
Host smart-0135e861-2a71-4783-a83d-a904b5d501d8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984543510 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_reset.3984543510
Directory /workspace/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.aon_timer_jump.40322257
Short name T42
Test name
Test status
Simulation time 384697231 ps
CPU time 1.14 seconds
Started Apr 04 02:47:58 PM PDT 24
Finished Apr 04 02:47:59 PM PDT 24
Peak memory 182952 kb
Host smart-28e0e4a3-5db2-436e-b73b-3b3ec104dc78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40322257 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.40322257
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.1118911992
Short name T103
Test name
Test status
Simulation time 19863128750 ps
CPU time 7.96 seconds
Started Apr 04 02:48:00 PM PDT 24
Finished Apr 04 02:48:08 PM PDT 24
Peak memory 183360 kb
Host smart-07b269dd-bd5c-46ca-8ff5-a064bb3da699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118911992 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.1118911992
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.3125692649
Short name T161
Test name
Test status
Simulation time 553532353 ps
CPU time 0.95 seconds
Started Apr 04 02:47:59 PM PDT 24
Finished Apr 04 02:48:00 PM PDT 24
Peak memory 183196 kb
Host smart-801a8426-77f3-4f8c-8d00-07d26cb19b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125692649 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.3125692649
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.778250486
Short name T20
Test name
Test status
Simulation time 544263310084 ps
CPU time 117.02 seconds
Started Apr 04 02:47:58 PM PDT 24
Finished Apr 04 02:49:55 PM PDT 24
Peak memory 183384 kb
Host smart-1b1abce5-24b9-44eb-922b-3ecf00a08cbf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778250486 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_a
ll.778250486
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.2469144682
Short name T212
Test name
Test status
Simulation time 22234953765 ps
CPU time 180.77 seconds
Started Apr 04 02:47:56 PM PDT 24
Finished Apr 04 02:50:57 PM PDT 24
Peak memory 198248 kb
Host smart-26c67f34-cc6d-406f-914b-d508011c1549
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469144682 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.2469144682
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.aon_timer_jump.3863236547
Short name T153
Test name
Test status
Simulation time 421093314 ps
CPU time 0.69 seconds
Started Apr 04 02:47:56 PM PDT 24
Finished Apr 04 02:47:57 PM PDT 24
Peak memory 183232 kb
Host smart-0a2460fc-9a8b-4509-8e6b-990a5e9709c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863236547 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.3863236547
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.1048759051
Short name T104
Test name
Test status
Simulation time 34906961658 ps
CPU time 53.99 seconds
Started Apr 04 02:47:56 PM PDT 24
Finished Apr 04 02:48:50 PM PDT 24
Peak memory 183276 kb
Host smart-6438f03a-63de-4852-90b0-f73c794692ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048759051 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.1048759051
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.2899085675
Short name T154
Test name
Test status
Simulation time 455793570 ps
CPU time 0.64 seconds
Started Apr 04 02:47:54 PM PDT 24
Finished Apr 04 02:47:55 PM PDT 24
Peak memory 183288 kb
Host smart-ec1fa54f-7d9f-480e-a746-276c3a507a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899085675 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.2899085675
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.491550746
Short name T249
Test name
Test status
Simulation time 305607091321 ps
CPU time 459.36 seconds
Started Apr 04 02:48:09 PM PDT 24
Finished Apr 04 02:55:49 PM PDT 24
Peak memory 183292 kb
Host smart-09d53854-b525-4027-b653-d0fe5b69de1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491550746 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_a
ll.491550746
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.566458499
Short name T270
Test name
Test status
Simulation time 78241876074 ps
CPU time 153.91 seconds
Started Apr 04 02:48:05 PM PDT 24
Finished Apr 04 02:50:39 PM PDT 24
Peak memory 198416 kb
Host smart-6b68b5be-8f63-4579-a4ed-34b7e058bd21
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566458499 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.566458499
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.aon_timer_jump.277692228
Short name T112
Test name
Test status
Simulation time 500901312 ps
CPU time 0.92 seconds
Started Apr 04 02:48:05 PM PDT 24
Finished Apr 04 02:48:06 PM PDT 24
Peak memory 183312 kb
Host smart-663082eb-44a7-44bf-ad80-a060561bb41f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277692228 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.277692228
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.342281882
Short name T148
Test name
Test status
Simulation time 1193062027 ps
CPU time 2.45 seconds
Started Apr 04 02:48:03 PM PDT 24
Finished Apr 04 02:48:05 PM PDT 24
Peak memory 183284 kb
Host smart-cab91128-2153-4956-a368-d64f4e662321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342281882 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.342281882
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.3007559192
Short name T211
Test name
Test status
Simulation time 536453490 ps
CPU time 0.72 seconds
Started Apr 04 02:48:08 PM PDT 24
Finished Apr 04 02:48:09 PM PDT 24
Peak memory 183292 kb
Host smart-88efe84a-6657-4ab2-9d2b-f5e82b4adc0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007559192 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.3007559192
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.796252824
Short name T143
Test name
Test status
Simulation time 226240114539 ps
CPU time 381.09 seconds
Started Apr 04 02:48:09 PM PDT 24
Finished Apr 04 02:54:30 PM PDT 24
Peak memory 183348 kb
Host smart-6452fc20-ef63-430e-9fb9-a7f01766f6f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796252824 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_a
ll.796252824
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.1930149760
Short name T83
Test name
Test status
Simulation time 177103831580 ps
CPU time 337.01 seconds
Started Apr 04 02:48:06 PM PDT 24
Finished Apr 04 02:53:43 PM PDT 24
Peak memory 198340 kb
Host smart-78bd781b-f0b5-4cdf-aed1-90e3d275c8f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930149760 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.1930149760
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.aon_timer_jump.1401100334
Short name T136
Test name
Test status
Simulation time 506990293 ps
CPU time 0.75 seconds
Started Apr 04 02:48:08 PM PDT 24
Finished Apr 04 02:48:09 PM PDT 24
Peak memory 183192 kb
Host smart-df6c487e-19c2-40c5-a559-a82fdc2331fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401100334 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.1401100334
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.2986823363
Short name T125
Test name
Test status
Simulation time 34458957850 ps
CPU time 28 seconds
Started Apr 04 02:48:02 PM PDT 24
Finished Apr 04 02:48:30 PM PDT 24
Peak memory 183348 kb
Host smart-c7d7fb32-94d1-4ab0-8796-b6b08bb73882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986823363 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.2986823363
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.3777331823
Short name T213
Test name
Test status
Simulation time 418326354 ps
CPU time 0.63 seconds
Started Apr 04 02:48:03 PM PDT 24
Finished Apr 04 02:48:04 PM PDT 24
Peak memory 183216 kb
Host smart-543870ee-72fa-46f1-b214-aee23e50a6db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777331823 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.3777331823
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.3295150409
Short name T120
Test name
Test status
Simulation time 413591620601 ps
CPU time 630.37 seconds
Started Apr 04 02:48:07 PM PDT 24
Finished Apr 04 02:58:38 PM PDT 24
Peak memory 195080 kb
Host smart-960b05ca-1a54-4a2a-9776-7adf32dec858
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295150409 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_
all.3295150409
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.4265364226
Short name T85
Test name
Test status
Simulation time 118746303782 ps
CPU time 345.38 seconds
Started Apr 04 02:48:03 PM PDT 24
Finished Apr 04 02:53:48 PM PDT 24
Peak memory 198312 kb
Host smart-58c0bd6a-a4c7-4cda-a7dc-1dc48a097b6d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265364226 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.4265364226
Directory /workspace/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.aon_timer_jump.2523353360
Short name T185
Test name
Test status
Simulation time 357111315 ps
CPU time 1.09 seconds
Started Apr 04 02:48:13 PM PDT 24
Finished Apr 04 02:48:14 PM PDT 24
Peak memory 183352 kb
Host smart-4bb34274-deb5-4570-bc39-290cefaa9bad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523353360 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.2523353360
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.1120699902
Short name T163
Test name
Test status
Simulation time 13580055830 ps
CPU time 5.4 seconds
Started Apr 04 02:48:08 PM PDT 24
Finished Apr 04 02:48:14 PM PDT 24
Peak memory 183360 kb
Host smart-3cc97d14-987b-41c9-a727-34a796f799a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120699902 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.1120699902
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.914585961
Short name T106
Test name
Test status
Simulation time 472922279 ps
CPU time 0.91 seconds
Started Apr 04 02:48:07 PM PDT 24
Finished Apr 04 02:48:08 PM PDT 24
Peak memory 183200 kb
Host smart-0f8de207-67be-49ad-b0dc-efa1df5820a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914585961 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.914585961
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.2314802886
Short name T6
Test name
Test status
Simulation time 250979998661 ps
CPU time 384.68 seconds
Started Apr 04 02:48:06 PM PDT 24
Finished Apr 04 02:54:31 PM PDT 24
Peak memory 183352 kb
Host smart-da6922bb-b26d-4dcc-b40d-788ae7917991
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314802886 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_
all.2314802886
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.1958896758
Short name T75
Test name
Test status
Simulation time 53520094728 ps
CPU time 328.02 seconds
Started Apr 04 02:48:12 PM PDT 24
Finished Apr 04 02:53:40 PM PDT 24
Peak memory 197924 kb
Host smart-14efd622-547a-4795-ac9f-cc647972e653
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958896758 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.1958896758
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.aon_timer_jump.3791214269
Short name T222
Test name
Test status
Simulation time 418263704 ps
CPU time 1.14 seconds
Started Apr 04 02:48:10 PM PDT 24
Finished Apr 04 02:48:11 PM PDT 24
Peak memory 183296 kb
Host smart-47509172-63ba-4989-98f6-4bf522fdd428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791214269 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.3791214269
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.2572795226
Short name T243
Test name
Test status
Simulation time 56719301015 ps
CPU time 36.36 seconds
Started Apr 04 02:48:07 PM PDT 24
Finished Apr 04 02:48:43 PM PDT 24
Peak memory 183364 kb
Host smart-0903f28e-1600-4afd-9c9f-a8487f8b15f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572795226 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.2572795226
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.2599887531
Short name T191
Test name
Test status
Simulation time 386328764 ps
CPU time 1.11 seconds
Started Apr 04 02:48:13 PM PDT 24
Finished Apr 04 02:48:14 PM PDT 24
Peak memory 183300 kb
Host smart-43376e77-88dc-44d4-bbf0-bc5087a98a79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599887531 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.2599887531
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.244512140
Short name T238
Test name
Test status
Simulation time 218145219047 ps
CPU time 51.82 seconds
Started Apr 04 02:48:07 PM PDT 24
Finished Apr 04 02:48:58 PM PDT 24
Peak memory 193844 kb
Host smart-16addc24-f1f8-4092-a74f-be9b51d8a316
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244512140 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_a
ll.244512140
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.3537462896
Short name T271
Test name
Test status
Simulation time 46365965478 ps
CPU time 356.15 seconds
Started Apr 04 02:48:10 PM PDT 24
Finished Apr 04 02:54:06 PM PDT 24
Peak memory 198292 kb
Host smart-623ad08b-0eb6-467d-aae7-c40d05e39710
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537462896 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand_reset.3537462896
Directory /workspace/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.aon_timer_jump.1673418004
Short name T208
Test name
Test status
Simulation time 359614049 ps
CPU time 0.68 seconds
Started Apr 04 02:48:07 PM PDT 24
Finished Apr 04 02:48:08 PM PDT 24
Peak memory 183232 kb
Host smart-59fa2acd-8855-49f7-ab15-542d3ac37e11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673418004 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.1673418004
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.2383815531
Short name T24
Test name
Test status
Simulation time 16248377481 ps
CPU time 4.13 seconds
Started Apr 04 02:48:08 PM PDT 24
Finished Apr 04 02:48:12 PM PDT 24
Peak memory 183364 kb
Host smart-be0593dd-ec0e-4b37-a88d-4c2bd976e3e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383815531 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.2383815531
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.2075217080
Short name T260
Test name
Test status
Simulation time 556136460 ps
CPU time 0.74 seconds
Started Apr 04 02:48:09 PM PDT 24
Finished Apr 04 02:48:10 PM PDT 24
Peak memory 183288 kb
Host smart-7514012d-6e6e-471f-9bd1-a013c7e480b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075217080 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.2075217080
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.1564470211
Short name T150
Test name
Test status
Simulation time 30830012836 ps
CPU time 51.29 seconds
Started Apr 04 02:48:06 PM PDT 24
Finished Apr 04 02:48:57 PM PDT 24
Peak memory 183496 kb
Host smart-f08804a7-44eb-4b23-8dc5-772392486f85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564470211 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_
all.1564470211
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.1998814631
Short name T167
Test name
Test status
Simulation time 232946306824 ps
CPU time 190.22 seconds
Started Apr 04 02:48:09 PM PDT 24
Finished Apr 04 02:51:20 PM PDT 24
Peak memory 198276 kb
Host smart-39f2f276-8afb-4910-8b76-cec4e262a191
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998814631 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.1998814631
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_jump.3058945080
Short name T252
Test name
Test status
Simulation time 516794598 ps
CPU time 0.76 seconds
Started Apr 04 02:47:32 PM PDT 24
Finished Apr 04 02:47:33 PM PDT 24
Peak memory 183212 kb
Host smart-29c5fb68-0120-4610-9a2a-f78373075b13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058945080 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.3058945080
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.3215066363
Short name T126
Test name
Test status
Simulation time 3524745144 ps
CPU time 5.66 seconds
Started Apr 04 02:47:28 PM PDT 24
Finished Apr 04 02:47:35 PM PDT 24
Peak memory 183360 kb
Host smart-37167bef-0662-4e03-bfac-91db01fb66cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215066363 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.3215066363
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.1211396895
Short name T21
Test name
Test status
Simulation time 4262790888 ps
CPU time 1.59 seconds
Started Apr 04 02:47:33 PM PDT 24
Finished Apr 04 02:47:35 PM PDT 24
Peak memory 214756 kb
Host smart-ad2015e2-c39f-41c8-aefc-0bdb03050497
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211396895 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.1211396895
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.4208262444
Short name T206
Test name
Test status
Simulation time 495800021 ps
CPU time 0.76 seconds
Started Apr 04 02:47:32 PM PDT 24
Finished Apr 04 02:47:33 PM PDT 24
Peak memory 183376 kb
Host smart-99468f06-0dee-40ee-86ad-99be6aaac39b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208262444 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.4208262444
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.1243707663
Short name T84
Test name
Test status
Simulation time 109782467187 ps
CPU time 617.52 seconds
Started Apr 04 02:47:33 PM PDT 24
Finished Apr 04 02:57:50 PM PDT 24
Peak memory 199308 kb
Host smart-8a8872fd-8fdb-4891-9462-1dc7446f2f5f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243707663 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.1243707663
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.aon_timer_jump.1963248704
Short name T274
Test name
Test status
Simulation time 582134820 ps
CPU time 1.57 seconds
Started Apr 04 02:48:07 PM PDT 24
Finished Apr 04 02:48:08 PM PDT 24
Peak memory 183196 kb
Host smart-a33dad22-8511-4f12-8e36-082e4cd3395d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963248704 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.1963248704
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.1349536451
Short name T207
Test name
Test status
Simulation time 33477476156 ps
CPU time 49.46 seconds
Started Apr 04 02:48:06 PM PDT 24
Finished Apr 04 02:48:56 PM PDT 24
Peak memory 183264 kb
Host smart-d977585f-5939-4fa6-b775-2e9bb6932008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349536451 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.1349536451
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.4199635019
Short name T58
Test name
Test status
Simulation time 374169590 ps
CPU time 1.01 seconds
Started Apr 04 02:48:03 PM PDT 24
Finished Apr 04 02:48:04 PM PDT 24
Peak memory 183304 kb
Host smart-322feba8-452c-499b-a86e-432457e68eae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199635019 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.4199635019
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.1640680692
Short name T165
Test name
Test status
Simulation time 47288210607 ps
CPU time 29.03 seconds
Started Apr 04 02:48:05 PM PDT 24
Finished Apr 04 02:48:34 PM PDT 24
Peak memory 183384 kb
Host smart-66372202-a02d-47d1-820a-858eaf0be95b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640680692 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_
all.1640680692
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_jump.3513228169
Short name T158
Test name
Test status
Simulation time 524077312 ps
CPU time 0.73 seconds
Started Apr 04 02:48:09 PM PDT 24
Finished Apr 04 02:48:10 PM PDT 24
Peak memory 183228 kb
Host smart-bee00376-759e-4122-af37-6450c47f35bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513228169 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.3513228169
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.636414244
Short name T118
Test name
Test status
Simulation time 11311870593 ps
CPU time 16.44 seconds
Started Apr 04 02:48:09 PM PDT 24
Finished Apr 04 02:48:25 PM PDT 24
Peak memory 183284 kb
Host smart-07d5788e-2b7c-40e9-8db4-06f04a1386c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636414244 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.636414244
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.1211210857
Short name T230
Test name
Test status
Simulation time 469364814 ps
CPU time 1.22 seconds
Started Apr 04 02:48:11 PM PDT 24
Finished Apr 04 02:48:12 PM PDT 24
Peak memory 183264 kb
Host smart-7cea317b-b1d8-422f-9985-cde4bea9ac5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211210857 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.1211210857
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.3648199919
Short name T221
Test name
Test status
Simulation time 120604892986 ps
CPU time 108.78 seconds
Started Apr 04 02:48:11 PM PDT 24
Finished Apr 04 02:50:00 PM PDT 24
Peak memory 195100 kb
Host smart-577c6a33-b6c2-42af-8bf5-c084d4fc4efd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648199919 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_
all.3648199919
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.505685420
Short name T256
Test name
Test status
Simulation time 1777058904969 ps
CPU time 773.89 seconds
Started Apr 04 02:48:07 PM PDT 24
Finished Apr 04 03:01:01 PM PDT 24
Peak memory 206496 kb
Host smart-1b059db4-ce83-4216-9a83-40925c14ea90
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505685420 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.505685420
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.aon_timer_jump.2186832705
Short name T16
Test name
Test status
Simulation time 435600972 ps
CPU time 1.23 seconds
Started Apr 04 02:48:09 PM PDT 24
Finished Apr 04 02:48:11 PM PDT 24
Peak memory 183276 kb
Host smart-70d8c964-3ad8-49d1-8797-e7dc29b26fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186832705 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.2186832705
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.3472826273
Short name T160
Test name
Test status
Simulation time 16091075887 ps
CPU time 21.89 seconds
Started Apr 04 02:48:09 PM PDT 24
Finished Apr 04 02:48:31 PM PDT 24
Peak memory 183288 kb
Host smart-7321dfdf-c8e2-4f1f-bb97-faf2f131bf15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472826273 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.3472826273
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.2470252023
Short name T111
Test name
Test status
Simulation time 543096045 ps
CPU time 1.3 seconds
Started Apr 04 02:48:06 PM PDT 24
Finished Apr 04 02:48:08 PM PDT 24
Peak memory 183280 kb
Host smart-3d07f3b6-33e1-47ad-ab3c-b34995f028af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470252023 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.2470252023
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.127310154
Short name T29
Test name
Test status
Simulation time 286013363507 ps
CPU time 440.47 seconds
Started Apr 04 02:48:06 PM PDT 24
Finished Apr 04 02:55:26 PM PDT 24
Peak memory 183416 kb
Host smart-ddd20776-f81c-413b-be66-1c99e896b553
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127310154 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_a
ll.127310154
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_jump.3629457259
Short name T1
Test name
Test status
Simulation time 372213529 ps
CPU time 1.05 seconds
Started Apr 04 02:48:08 PM PDT 24
Finished Apr 04 02:48:09 PM PDT 24
Peak memory 183300 kb
Host smart-959fe0bd-51ef-4322-b02c-b0f5778ba21a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629457259 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.3629457259
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.1023731517
Short name T198
Test name
Test status
Simulation time 1430903679 ps
CPU time 1.66 seconds
Started Apr 04 02:48:09 PM PDT 24
Finished Apr 04 02:48:10 PM PDT 24
Peak memory 183300 kb
Host smart-e27b7aad-269e-4a60-b5b3-70f1eaa9d07a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023731517 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.1023731517
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.2300695086
Short name T159
Test name
Test status
Simulation time 402329156 ps
CPU time 1.11 seconds
Started Apr 04 02:48:10 PM PDT 24
Finished Apr 04 02:48:11 PM PDT 24
Peak memory 183312 kb
Host smart-6249224a-d693-4d7d-b6ba-70a7bbee9fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300695086 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.2300695086
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.589589668
Short name T197
Test name
Test status
Simulation time 55066347772 ps
CPU time 25.71 seconds
Started Apr 04 02:48:06 PM PDT 24
Finished Apr 04 02:48:31 PM PDT 24
Peak memory 183332 kb
Host smart-9a31344f-cff3-4297-abc4-bc23fd764535
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589589668 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_a
ll.589589668
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.2527960567
Short name T177
Test name
Test status
Simulation time 52492068258 ps
CPU time 341.08 seconds
Started Apr 04 02:48:06 PM PDT 24
Finished Apr 04 02:53:47 PM PDT 24
Peak memory 198300 kb
Host smart-3619ad1e-ab6f-4e2c-a575-c5149db0950a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527960567 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.2527960567
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.aon_timer_jump.2873383794
Short name T186
Test name
Test status
Simulation time 540865511 ps
CPU time 1.29 seconds
Started Apr 04 02:48:06 PM PDT 24
Finished Apr 04 02:48:07 PM PDT 24
Peak memory 183228 kb
Host smart-b7c5046d-74a3-485a-8a1c-456131014dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873383794 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.2873383794
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.1003171719
Short name T176
Test name
Test status
Simulation time 32627912350 ps
CPU time 4.03 seconds
Started Apr 04 02:48:15 PM PDT 24
Finished Apr 04 02:48:19 PM PDT 24
Peak memory 183372 kb
Host smart-ad068cd9-645f-4b37-a0f4-9842a98a61fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003171719 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.1003171719
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.1489213679
Short name T180
Test name
Test status
Simulation time 468553285 ps
CPU time 1.22 seconds
Started Apr 04 02:48:12 PM PDT 24
Finished Apr 04 02:48:13 PM PDT 24
Peak memory 182900 kb
Host smart-b431f864-f06e-4c61-aa2d-35979fe76daa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489213679 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.1489213679
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.4000210491
Short name T14
Test name
Test status
Simulation time 80256925577 ps
CPU time 115.62 seconds
Started Apr 04 02:48:14 PM PDT 24
Finished Apr 04 02:50:10 PM PDT 24
Peak memory 193612 kb
Host smart-ef2c99f9-5bcc-42b5-9853-746d1851f618
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000210491 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_
all.4000210491
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_jump.2884112198
Short name T115
Test name
Test status
Simulation time 519573932 ps
CPU time 0.75 seconds
Started Apr 04 02:48:06 PM PDT 24
Finished Apr 04 02:48:06 PM PDT 24
Peak memory 183284 kb
Host smart-b79eabc5-9aa9-490c-b168-f6275c886542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884112198 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.2884112198
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.67497546
Short name T258
Test name
Test status
Simulation time 38025700270 ps
CPU time 23.73 seconds
Started Apr 04 02:48:06 PM PDT 24
Finished Apr 04 02:48:29 PM PDT 24
Peak memory 183328 kb
Host smart-d6ea4ba0-736e-4295-9f6e-89150cf93a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67497546 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.67497546
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.2466653091
Short name T247
Test name
Test status
Simulation time 387731344 ps
CPU time 1.16 seconds
Started Apr 04 02:48:05 PM PDT 24
Finished Apr 04 02:48:06 PM PDT 24
Peak memory 183308 kb
Host smart-9c96a983-f22c-47c2-b338-39534e04e102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466653091 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.2466653091
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.2759999547
Short name T156
Test name
Test status
Simulation time 52710339268 ps
CPU time 75.27 seconds
Started Apr 04 02:48:07 PM PDT 24
Finished Apr 04 02:49:22 PM PDT 24
Peak memory 183376 kb
Host smart-b4e97e3d-5ea6-4ccc-94dd-0a964b91a973
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759999547 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_
all.2759999547
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.205244156
Short name T7
Test name
Test status
Simulation time 237320000452 ps
CPU time 949.23 seconds
Started Apr 04 02:48:06 PM PDT 24
Finished Apr 04 03:03:55 PM PDT 24
Peak memory 203296 kb
Host smart-dadf9574-bad3-4950-a3df-ddf653346e52
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205244156 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.205244156
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.aon_timer_jump.386429190
Short name T3
Test name
Test status
Simulation time 406674327 ps
CPU time 1 seconds
Started Apr 04 02:48:05 PM PDT 24
Finished Apr 04 02:48:06 PM PDT 24
Peak memory 183284 kb
Host smart-02ca0f8e-b154-4522-96aa-af669ec0c8d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386429190 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.386429190
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.332219683
Short name T131
Test name
Test status
Simulation time 40587183226 ps
CPU time 69.32 seconds
Started Apr 04 02:48:03 PM PDT 24
Finished Apr 04 02:49:12 PM PDT 24
Peak memory 183392 kb
Host smart-ac83826a-2c3c-468a-97d7-00bfc7de9abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332219683 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.332219683
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.195430352
Short name T127
Test name
Test status
Simulation time 602989937 ps
CPU time 0.73 seconds
Started Apr 04 02:48:07 PM PDT 24
Finished Apr 04 02:48:08 PM PDT 24
Peak memory 183308 kb
Host smart-2b1c23a2-b371-4a31-b295-7da55c959c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195430352 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.195430352
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.70536099
Short name T65
Test name
Test status
Simulation time 224727264701 ps
CPU time 181.18 seconds
Started Apr 04 02:48:06 PM PDT 24
Finished Apr 04 02:51:07 PM PDT 24
Peak memory 194176 kb
Host smart-3f124f8e-0631-4e1d-ac76-38f7c1b64a88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70536099 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_al
l.70536099
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_jump.753081531
Short name T242
Test name
Test status
Simulation time 442868843 ps
CPU time 1.12 seconds
Started Apr 04 02:48:10 PM PDT 24
Finished Apr 04 02:48:11 PM PDT 24
Peak memory 183220 kb
Host smart-56123cab-1adf-4ce2-9bb5-8c5e3a737248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753081531 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.753081531
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.2815049486
Short name T246
Test name
Test status
Simulation time 35076447085 ps
CPU time 55.14 seconds
Started Apr 04 02:48:08 PM PDT 24
Finished Apr 04 02:49:03 PM PDT 24
Peak memory 183296 kb
Host smart-b39e2a67-bf55-4aee-8b81-de9e233dd98e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815049486 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.2815049486
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.1876248908
Short name T188
Test name
Test status
Simulation time 440296284 ps
CPU time 0.64 seconds
Started Apr 04 02:48:12 PM PDT 24
Finished Apr 04 02:48:12 PM PDT 24
Peak memory 183264 kb
Host smart-5d0378ef-f64b-4c97-877a-098ca31e3363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876248908 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.1876248908
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.2359150512
Short name T262
Test name
Test status
Simulation time 139802930594 ps
CPU time 195.67 seconds
Started Apr 04 02:48:10 PM PDT 24
Finished Apr 04 02:51:26 PM PDT 24
Peak memory 183368 kb
Host smart-38aad643-6acc-49c9-af48-95af8bb7b84c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359150512 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_
all.2359150512
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_jump.1972203825
Short name T200
Test name
Test status
Simulation time 413090120 ps
CPU time 0.69 seconds
Started Apr 04 02:48:10 PM PDT 24
Finished Apr 04 02:48:11 PM PDT 24
Peak memory 183268 kb
Host smart-6cd0d7a1-c5d7-46d0-be75-3a49d8d84d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972203825 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.1972203825
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.2451866507
Short name T276
Test name
Test status
Simulation time 2208493274 ps
CPU time 3.27 seconds
Started Apr 04 02:48:13 PM PDT 24
Finished Apr 04 02:48:17 PM PDT 24
Peak memory 183408 kb
Host smart-ea80a0c7-96c5-483c-86fa-edc3bfb5f649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451866507 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.2451866507
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.391371960
Short name T226
Test name
Test status
Simulation time 408603159 ps
CPU time 0.58 seconds
Started Apr 04 02:48:14 PM PDT 24
Finished Apr 04 02:48:14 PM PDT 24
Peak memory 183356 kb
Host smart-72eb7ac5-fbb9-4d0f-9337-dd7c14952508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391371960 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.391371960
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.1675884780
Short name T66
Test name
Test status
Simulation time 34809204916 ps
CPU time 55.91 seconds
Started Apr 04 02:48:14 PM PDT 24
Finished Apr 04 02:49:10 PM PDT 24
Peak memory 193708 kb
Host smart-68f887e6-4ed0-4516-a388-013f76000b0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675884780 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_
all.1675884780
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.2393351271
Short name T220
Test name
Test status
Simulation time 78870612618 ps
CPU time 224.26 seconds
Started Apr 04 02:48:11 PM PDT 24
Finished Apr 04 02:51:56 PM PDT 24
Peak memory 198336 kb
Host smart-9d50ec61-b604-4483-9688-6cfd7a50fee4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393351271 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.2393351271
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.aon_timer_jump.313167611
Short name T109
Test name
Test status
Simulation time 598097476 ps
CPU time 1.45 seconds
Started Apr 04 02:48:07 PM PDT 24
Finished Apr 04 02:48:09 PM PDT 24
Peak memory 183184 kb
Host smart-fa60b1f0-d150-456a-b940-0e8bb2758abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313167611 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.313167611
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.1742758075
Short name T215
Test name
Test status
Simulation time 10413375668 ps
CPU time 4.5 seconds
Started Apr 04 02:48:13 PM PDT 24
Finished Apr 04 02:48:17 PM PDT 24
Peak memory 183356 kb
Host smart-aa02056e-eca5-4045-81f5-f47a8e038cc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742758075 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.1742758075
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.3090297793
Short name T224
Test name
Test status
Simulation time 443350920 ps
CPU time 1.29 seconds
Started Apr 04 02:48:10 PM PDT 24
Finished Apr 04 02:48:11 PM PDT 24
Peak memory 183276 kb
Host smart-5354e6b0-34f2-48b1-8625-90ee43543bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090297793 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.3090297793
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.3974955473
Short name T237
Test name
Test status
Simulation time 243997476310 ps
CPU time 376.54 seconds
Started Apr 04 02:48:13 PM PDT 24
Finished Apr 04 02:54:29 PM PDT 24
Peak memory 193032 kb
Host smart-2fff922a-3343-4304-be39-8bb2ec3b7871
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974955473 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_
all.3974955473
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.2796682813
Short name T40
Test name
Test status
Simulation time 17889144635 ps
CPU time 123.82 seconds
Started Apr 04 02:48:12 PM PDT 24
Finished Apr 04 02:50:16 PM PDT 24
Peak memory 198332 kb
Host smart-2bcfcde4-ad91-48ce-b1d3-04c33574308b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796682813 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.2796682813
Directory /workspace/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.aon_timer_jump.4213045977
Short name T121
Test name
Test status
Simulation time 508359390 ps
CPU time 0.74 seconds
Started Apr 04 02:47:27 PM PDT 24
Finished Apr 04 02:47:29 PM PDT 24
Peak memory 183260 kb
Host smart-db394201-ca23-4565-b19f-d44c73b386ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213045977 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.4213045977
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.2243661022
Short name T192
Test name
Test status
Simulation time 55460850390 ps
CPU time 70.79 seconds
Started Apr 04 02:47:27 PM PDT 24
Finished Apr 04 02:48:40 PM PDT 24
Peak memory 183268 kb
Host smart-f7af95ec-b916-4a13-8869-8880beb4615e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243661022 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.2243661022
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.3146250759
Short name T264
Test name
Test status
Simulation time 568896489 ps
CPU time 0.99 seconds
Started Apr 04 02:47:58 PM PDT 24
Finished Apr 04 02:47:59 PM PDT 24
Peak memory 183376 kb
Host smart-5568e09d-40a7-4693-ac9b-582b4e567a24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146250759 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.3146250759
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.1142100876
Short name T201
Test name
Test status
Simulation time 92671326831 ps
CPU time 36.61 seconds
Started Apr 04 02:47:28 PM PDT 24
Finished Apr 04 02:48:06 PM PDT 24
Peak memory 194816 kb
Host smart-181b3a4f-2cd3-4754-9b46-5b4a6841fd6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142100876 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_a
ll.1142100876
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.2947986366
Short name T2
Test name
Test status
Simulation time 16092353606 ps
CPU time 68.82 seconds
Started Apr 04 02:47:26 PM PDT 24
Finished Apr 04 02:48:35 PM PDT 24
Peak memory 198276 kb
Host smart-04cf521b-04b6-4986-8bd8-9cfafaaab7ce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947986366 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.2947986366
Directory /workspace/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.aon_timer_jump.4210819152
Short name T4
Test name
Test status
Simulation time 445433858 ps
CPU time 1.2 seconds
Started Apr 04 02:47:31 PM PDT 24
Finished Apr 04 02:47:33 PM PDT 24
Peak memory 183212 kb
Host smart-316158cf-6087-4e99-8403-90b2f0a23474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210819152 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.4210819152
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.2355489808
Short name T110
Test name
Test status
Simulation time 39247649740 ps
CPU time 57.25 seconds
Started Apr 04 02:47:32 PM PDT 24
Finished Apr 04 02:48:30 PM PDT 24
Peak memory 183284 kb
Host smart-883c7277-5009-40a0-b4c6-62a71a328aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355489808 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.2355489808
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.434839419
Short name T12
Test name
Test status
Simulation time 512668035 ps
CPU time 1.36 seconds
Started Apr 04 02:47:27 PM PDT 24
Finished Apr 04 02:47:28 PM PDT 24
Peak memory 183280 kb
Host smart-0f50978b-5163-4892-ace3-ae3d3744371e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434839419 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.434839419
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.666295507
Short name T277
Test name
Test status
Simulation time 34153503738 ps
CPU time 54.34 seconds
Started Apr 04 02:47:45 PM PDT 24
Finished Apr 04 02:48:39 PM PDT 24
Peak memory 183312 kb
Host smart-b1e206a6-877f-4836-bee6-097e5d88d837
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666295507 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_al
l.666295507
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.3166564892
Short name T77
Test name
Test status
Simulation time 244906209891 ps
CPU time 457.27 seconds
Started Apr 04 02:47:27 PM PDT 24
Finished Apr 04 02:55:04 PM PDT 24
Peak memory 198260 kb
Host smart-67ab09a4-1257-48d2-be9e-499abf32380a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166564892 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.3166564892
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.aon_timer_jump.2024253282
Short name T31
Test name
Test status
Simulation time 492175365 ps
CPU time 0.91 seconds
Started Apr 04 02:47:40 PM PDT 24
Finished Apr 04 02:47:41 PM PDT 24
Peak memory 183260 kb
Host smart-95609fbd-c176-4b98-9094-d8666eb1af20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024253282 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.2024253282
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.177934997
Short name T170
Test name
Test status
Simulation time 2364004422 ps
CPU time 1.45 seconds
Started Apr 04 02:47:42 PM PDT 24
Finished Apr 04 02:47:44 PM PDT 24
Peak memory 183368 kb
Host smart-e685594c-982e-43ac-a164-f6c8c81b27b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177934997 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.177934997
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.3644787157
Short name T210
Test name
Test status
Simulation time 603588488 ps
CPU time 0.78 seconds
Started Apr 04 02:47:37 PM PDT 24
Finished Apr 04 02:47:38 PM PDT 24
Peak memory 183264 kb
Host smart-20ae8527-536d-414a-9c58-4e0476ad664c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644787157 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.3644787157
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.484600915
Short name T265
Test name
Test status
Simulation time 266869205177 ps
CPU time 181.92 seconds
Started Apr 04 02:47:37 PM PDT 24
Finished Apr 04 02:50:39 PM PDT 24
Peak memory 194692 kb
Host smart-e2e95e20-c7c4-4e98-a8db-8790f9dc6bd6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484600915 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_al
l.484600915
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_jump.3295589727
Short name T101
Test name
Test status
Simulation time 548169039 ps
CPU time 0.77 seconds
Started Apr 04 02:47:46 PM PDT 24
Finished Apr 04 02:47:47 PM PDT 24
Peak memory 183240 kb
Host smart-b3786612-7d68-4e7e-8c76-5b57be00ef5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295589727 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.3295589727
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.2951779263
Short name T144
Test name
Test status
Simulation time 7110757859 ps
CPU time 2.29 seconds
Started Apr 04 02:47:45 PM PDT 24
Finished Apr 04 02:47:48 PM PDT 24
Peak memory 183312 kb
Host smart-09ef661d-4036-492e-9ea3-676460dea6a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951779263 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.2951779263
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.3252077143
Short name T59
Test name
Test status
Simulation time 472441304 ps
CPU time 0.69 seconds
Started Apr 04 02:47:36 PM PDT 24
Finished Apr 04 02:47:37 PM PDT 24
Peak memory 183260 kb
Host smart-0eb4a151-efbb-48e9-86fc-80c9e784eaf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252077143 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.3252077143
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.3196693358
Short name T228
Test name
Test status
Simulation time 210177036864 ps
CPU time 290.83 seconds
Started Apr 04 02:47:38 PM PDT 24
Finished Apr 04 02:52:29 PM PDT 24
Peak memory 183308 kb
Host smart-0c8094cd-45e6-4122-b710-03ea595508d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196693358 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_a
ll.3196693358
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.874162890
Short name T61
Test name
Test status
Simulation time 911555508481 ps
CPU time 573 seconds
Started Apr 04 02:47:46 PM PDT 24
Finished Apr 04 02:57:19 PM PDT 24
Peak memory 206488 kb
Host smart-549cb436-5ea7-4d8e-b759-70e001b131de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874162890 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.874162890
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.aon_timer_jump.1654856340
Short name T251
Test name
Test status
Simulation time 379287695 ps
CPU time 1.24 seconds
Started Apr 04 02:47:38 PM PDT 24
Finished Apr 04 02:47:40 PM PDT 24
Peak memory 183280 kb
Host smart-c3c6849b-2e3d-4433-acd8-d9f5f94969e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654856340 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.1654856340
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.4090894216
Short name T204
Test name
Test status
Simulation time 31863616255 ps
CPU time 44.51 seconds
Started Apr 04 02:47:41 PM PDT 24
Finished Apr 04 02:48:25 PM PDT 24
Peak memory 183372 kb
Host smart-292d8a61-952d-485e-851c-5dd8601164a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090894216 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.4090894216
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.2686273168
Short name T26
Test name
Test status
Simulation time 338715326 ps
CPU time 0.84 seconds
Started Apr 04 02:47:40 PM PDT 24
Finished Apr 04 02:47:41 PM PDT 24
Peak memory 183260 kb
Host smart-10673f00-d872-4dc5-8566-317153fbe64f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686273168 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.2686273168
Directory /workspace/9.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.939418776
Short name T231
Test name
Test status
Simulation time 217836447837 ps
CPU time 303.6 seconds
Started Apr 04 02:47:40 PM PDT 24
Finished Apr 04 02:52:43 PM PDT 24
Peak memory 194836 kb
Host smart-0d3f107d-56c2-4b75-94f9-23218b4d2c44
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939418776 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_al
l.939418776
Directory /workspace/9.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.2704798318
Short name T253
Test name
Test status
Simulation time 79564033888 ps
CPU time 657.19 seconds
Started Apr 04 02:47:40 PM PDT 24
Finished Apr 04 02:58:37 PM PDT 24
Peak memory 199552 kb
Host smart-b1817880-5f66-42a4-a6f9-0d970df6d721
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704798318 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.2704798318
Directory /workspace/9.aon_timer_stress_all_with_rand_reset/latest
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