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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
92.98 99.25 93.67 100.00 98.40 99.51 67.06


Total test records in report: 414
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T40 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.1650736679 Apr 18 01:41:21 PM PDT 24 Apr 18 01:41:22 PM PDT 24 955500879 ps
T281 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.1069893997 Apr 18 01:41:50 PM PDT 24 Apr 18 01:41:51 PM PDT 24 356267609 ps
T41 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.1984031632 Apr 18 01:41:14 PM PDT 24 Apr 18 01:41:19 PM PDT 24 8532878403 ps
T75 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.4247263769 Apr 18 01:41:26 PM PDT 24 Apr 18 01:41:31 PM PDT 24 2468434050 ps
T282 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.616869903 Apr 18 01:41:49 PM PDT 24 Apr 18 01:41:51 PM PDT 24 339648291 ps
T42 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.2773072510 Apr 18 01:41:43 PM PDT 24 Apr 18 01:41:46 PM PDT 24 4275934378 ps
T283 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.3715769733 Apr 18 01:41:19 PM PDT 24 Apr 18 01:41:20 PM PDT 24 426394634 ps
T284 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.1382305733 Apr 18 01:41:45 PM PDT 24 Apr 18 01:41:47 PM PDT 24 385265882 ps
T285 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.3406615916 Apr 18 01:41:54 PM PDT 24 Apr 18 01:41:55 PM PDT 24 534230271 ps
T286 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.1733329658 Apr 18 01:41:20 PM PDT 24 Apr 18 01:41:21 PM PDT 24 295928427 ps
T287 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.3430200513 Apr 18 01:41:26 PM PDT 24 Apr 18 01:41:27 PM PDT 24 470519725 ps
T288 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.3633136998 Apr 18 01:41:34 PM PDT 24 Apr 18 01:41:36 PM PDT 24 496814342 ps
T289 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.4139797942 Apr 18 01:41:37 PM PDT 24 Apr 18 01:41:40 PM PDT 24 466044235 ps
T104 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.3293646812 Apr 18 01:41:38 PM PDT 24 Apr 18 01:41:40 PM PDT 24 543677570 ps
T290 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.405747924 Apr 18 01:41:42 PM PDT 24 Apr 18 01:41:45 PM PDT 24 567207496 ps
T291 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.2807572245 Apr 18 01:41:21 PM PDT 24 Apr 18 01:41:25 PM PDT 24 475240156 ps
T76 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.3585843129 Apr 18 01:41:26 PM PDT 24 Apr 18 01:41:32 PM PDT 24 2642614694 ps
T62 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.1208707432 Apr 18 01:41:14 PM PDT 24 Apr 18 01:41:17 PM PDT 24 642860561 ps
T292 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.4183188972 Apr 18 01:41:09 PM PDT 24 Apr 18 01:41:10 PM PDT 24 452342126 ps
T63 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.782911959 Apr 18 01:41:21 PM PDT 24 Apr 18 01:41:22 PM PDT 24 493411816 ps
T43 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.1587597902 Apr 18 01:41:25 PM PDT 24 Apr 18 01:41:34 PM PDT 24 8674680456 ps
T293 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.439300384 Apr 18 01:41:13 PM PDT 24 Apr 18 01:41:14 PM PDT 24 555511878 ps
T294 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.3383015688 Apr 18 01:41:10 PM PDT 24 Apr 18 01:41:12 PM PDT 24 741764442 ps
T295 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.1822198096 Apr 18 01:41:40 PM PDT 24 Apr 18 01:41:42 PM PDT 24 565940964 ps
T64 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.230698044 Apr 18 01:41:24 PM PDT 24 Apr 18 01:41:50 PM PDT 24 9813325967 ps
T77 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.966136946 Apr 18 01:41:25 PM PDT 24 Apr 18 01:41:31 PM PDT 24 2733078704 ps
T78 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.862068745 Apr 18 01:41:39 PM PDT 24 Apr 18 01:41:41 PM PDT 24 397012596 ps
T296 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.1477939156 Apr 18 01:41:50 PM PDT 24 Apr 18 01:41:51 PM PDT 24 377994126 ps
T297 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.3808228326 Apr 18 01:41:13 PM PDT 24 Apr 18 01:41:14 PM PDT 24 555825814 ps
T298 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.2894042788 Apr 18 01:41:45 PM PDT 24 Apr 18 01:41:46 PM PDT 24 471248817 ps
T299 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.1586609752 Apr 18 01:41:20 PM PDT 24 Apr 18 01:41:21 PM PDT 24 502451624 ps
T300 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.459841149 Apr 18 01:41:46 PM PDT 24 Apr 18 01:41:48 PM PDT 24 414867653 ps
T65 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.3453202 Apr 18 01:41:44 PM PDT 24 Apr 18 01:41:45 PM PDT 24 518352203 ps
T301 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.1357508087 Apr 18 01:41:55 PM PDT 24 Apr 18 01:41:56 PM PDT 24 520969104 ps
T302 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.2522671690 Apr 18 01:41:19 PM PDT 24 Apr 18 01:41:20 PM PDT 24 338842409 ps
T303 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.975295613 Apr 18 01:41:21 PM PDT 24 Apr 18 01:41:23 PM PDT 24 708266012 ps
T103 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.4132826391 Apr 18 01:41:41 PM PDT 24 Apr 18 01:41:44 PM PDT 24 4238980613 ps
T100 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.3603887066 Apr 18 01:41:24 PM PDT 24 Apr 18 01:41:40 PM PDT 24 8383697489 ps
T304 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.225473160 Apr 18 01:41:42 PM PDT 24 Apr 18 01:41:44 PM PDT 24 387165194 ps
T79 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.3818379060 Apr 18 01:41:31 PM PDT 24 Apr 18 01:41:32 PM PDT 24 325730766 ps
T305 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.3277570104 Apr 18 01:41:14 PM PDT 24 Apr 18 01:41:15 PM PDT 24 514955920 ps
T306 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.498887818 Apr 18 01:41:21 PM PDT 24 Apr 18 01:41:23 PM PDT 24 486696749 ps
T307 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.3531307050 Apr 18 01:41:21 PM PDT 24 Apr 18 01:41:26 PM PDT 24 8216789141 ps
T308 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.1296548999 Apr 18 01:41:44 PM PDT 24 Apr 18 01:41:46 PM PDT 24 537958125 ps
T66 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.3200130370 Apr 18 01:41:52 PM PDT 24 Apr 18 01:41:53 PM PDT 24 1246497883 ps
T67 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.365831309 Apr 18 01:41:44 PM PDT 24 Apr 18 01:41:46 PM PDT 24 345179713 ps
T309 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.2583676976 Apr 18 01:41:25 PM PDT 24 Apr 18 01:41:27 PM PDT 24 367501214 ps
T310 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.1143699985 Apr 18 01:41:38 PM PDT 24 Apr 18 01:41:40 PM PDT 24 381954328 ps
T311 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.3078430883 Apr 18 01:41:24 PM PDT 24 Apr 18 01:41:25 PM PDT 24 319024167 ps
T312 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.3448649638 Apr 18 01:41:33 PM PDT 24 Apr 18 01:41:34 PM PDT 24 387582747 ps
T71 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.1455616499 Apr 18 01:41:40 PM PDT 24 Apr 18 01:41:42 PM PDT 24 414838096 ps
T313 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.348794404 Apr 18 01:41:08 PM PDT 24 Apr 18 01:41:21 PM PDT 24 7995546910 ps
T80 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.1773022608 Apr 18 01:41:39 PM PDT 24 Apr 18 01:41:41 PM PDT 24 1587437433 ps
T314 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.1869201854 Apr 18 01:41:14 PM PDT 24 Apr 18 01:41:16 PM PDT 24 557139415 ps
T315 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.4284817409 Apr 18 01:41:45 PM PDT 24 Apr 18 01:41:47 PM PDT 24 328598819 ps
T72 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.914444567 Apr 18 01:41:15 PM PDT 24 Apr 18 01:41:17 PM PDT 24 556274441 ps
T316 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.2206459507 Apr 18 01:41:43 PM PDT 24 Apr 18 01:41:45 PM PDT 24 283881958 ps
T317 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.3922001873 Apr 18 01:41:32 PM PDT 24 Apr 18 01:41:34 PM PDT 24 472932849 ps
T318 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.2553460593 Apr 18 01:41:50 PM PDT 24 Apr 18 01:41:51 PM PDT 24 285341401 ps
T101 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.1772465781 Apr 18 01:41:46 PM PDT 24 Apr 18 01:41:54 PM PDT 24 8537488034 ps
T81 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.125723495 Apr 18 01:41:46 PM PDT 24 Apr 18 01:41:47 PM PDT 24 2625792110 ps
T319 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.920596500 Apr 18 01:41:23 PM PDT 24 Apr 18 01:41:24 PM PDT 24 384939059 ps
T82 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.1734236434 Apr 18 01:41:42 PM PDT 24 Apr 18 01:41:43 PM PDT 24 327622173 ps
T320 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.248466351 Apr 18 01:41:26 PM PDT 24 Apr 18 01:41:27 PM PDT 24 398920094 ps
T321 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.687137110 Apr 18 01:41:32 PM PDT 24 Apr 18 01:41:34 PM PDT 24 478771355 ps
T322 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.3999683485 Apr 18 01:41:28 PM PDT 24 Apr 18 01:41:32 PM PDT 24 2327558299 ps
T68 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.768935529 Apr 18 01:41:14 PM PDT 24 Apr 18 01:41:23 PM PDT 24 13399546990 ps
T323 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.1329395027 Apr 18 01:41:33 PM PDT 24 Apr 18 01:41:35 PM PDT 24 417041720 ps
T324 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.2200908959 Apr 18 01:41:42 PM PDT 24 Apr 18 01:41:43 PM PDT 24 490636769 ps
T325 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.1769819457 Apr 18 01:41:52 PM PDT 24 Apr 18 01:41:53 PM PDT 24 314582294 ps
T326 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.1453373388 Apr 18 01:41:44 PM PDT 24 Apr 18 01:41:45 PM PDT 24 417618830 ps
T327 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.2608454006 Apr 18 01:41:25 PM PDT 24 Apr 18 01:41:27 PM PDT 24 554617133 ps
T328 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.1507863595 Apr 18 01:41:35 PM PDT 24 Apr 18 01:41:37 PM PDT 24 1327149196 ps
T329 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.4214353648 Apr 18 01:41:44 PM PDT 24 Apr 18 01:41:45 PM PDT 24 464487398 ps
T330 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.3769377452 Apr 18 01:41:21 PM PDT 24 Apr 18 01:41:24 PM PDT 24 419593847 ps
T331 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.1206592640 Apr 18 01:41:25 PM PDT 24 Apr 18 01:41:28 PM PDT 24 4574122405 ps
T332 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.2803309181 Apr 18 01:41:32 PM PDT 24 Apr 18 01:41:35 PM PDT 24 4311783243 ps
T333 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.2313122646 Apr 18 01:41:50 PM PDT 24 Apr 18 01:41:51 PM PDT 24 434817792 ps
T334 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.1842192321 Apr 18 01:41:44 PM PDT 24 Apr 18 01:41:45 PM PDT 24 491339851 ps
T102 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.2777128826 Apr 18 01:41:46 PM PDT 24 Apr 18 01:41:53 PM PDT 24 8179866032 ps
T335 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.3083727249 Apr 18 01:41:40 PM PDT 24 Apr 18 01:41:41 PM PDT 24 304747188 ps
T336 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.3945396798 Apr 18 01:41:14 PM PDT 24 Apr 18 01:41:36 PM PDT 24 14078533453 ps
T69 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.1991804836 Apr 18 01:41:19 PM PDT 24 Apr 18 01:41:21 PM PDT 24 546653677 ps
T337 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.631546636 Apr 18 01:41:55 PM PDT 24 Apr 18 01:41:56 PM PDT 24 336391904 ps
T338 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.1609875130 Apr 18 01:41:32 PM PDT 24 Apr 18 01:41:34 PM PDT 24 467135177 ps
T339 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.1917403000 Apr 18 01:41:21 PM PDT 24 Apr 18 01:41:22 PM PDT 24 303804121 ps
T340 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.3801227639 Apr 18 01:41:40 PM PDT 24 Apr 18 01:41:44 PM PDT 24 1294182229 ps
T341 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.2783046590 Apr 18 01:41:25 PM PDT 24 Apr 18 01:41:26 PM PDT 24 491584965 ps
T342 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.3668840026 Apr 18 01:41:33 PM PDT 24 Apr 18 01:41:36 PM PDT 24 507583252 ps
T73 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.1507519858 Apr 18 01:41:27 PM PDT 24 Apr 18 01:41:28 PM PDT 24 344666771 ps
T343 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.3204235737 Apr 18 01:41:54 PM PDT 24 Apr 18 01:41:55 PM PDT 24 591819086 ps
T344 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.3954929208 Apr 18 01:41:15 PM PDT 24 Apr 18 01:41:16 PM PDT 24 303901945 ps
T345 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.3864489028 Apr 18 01:41:44 PM PDT 24 Apr 18 01:41:45 PM PDT 24 391118936 ps
T346 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.2499685956 Apr 18 01:41:40 PM PDT 24 Apr 18 01:41:49 PM PDT 24 4338715902 ps
T347 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.2012999879 Apr 18 01:41:35 PM PDT 24 Apr 18 01:41:37 PM PDT 24 331835891 ps
T348 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.1679417745 Apr 18 01:41:21 PM PDT 24 Apr 18 01:41:23 PM PDT 24 361111397 ps
T349 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.341614863 Apr 18 01:41:53 PM PDT 24 Apr 18 01:41:58 PM PDT 24 1801218690 ps
T74 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.3519737296 Apr 18 01:41:22 PM PDT 24 Apr 18 01:41:24 PM PDT 24 1181671230 ps
T350 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.4214449219 Apr 18 01:41:21 PM PDT 24 Apr 18 01:41:25 PM PDT 24 2530423173 ps
T351 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.1812184690 Apr 18 01:41:33 PM PDT 24 Apr 18 01:41:38 PM PDT 24 1221131937 ps
T352 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.4186130238 Apr 18 01:41:54 PM PDT 24 Apr 18 01:41:55 PM PDT 24 397193480 ps
T353 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.1191019449 Apr 18 01:41:21 PM PDT 24 Apr 18 01:41:22 PM PDT 24 493819775 ps
T354 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.28650722 Apr 18 01:41:21 PM PDT 24 Apr 18 01:41:29 PM PDT 24 4286910134 ps
T355 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.2231938378 Apr 18 01:41:33 PM PDT 24 Apr 18 01:41:36 PM PDT 24 4692274980 ps
T356 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.4083160870 Apr 18 01:41:52 PM PDT 24 Apr 18 01:41:53 PM PDT 24 449076767 ps
T357 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.1842546193 Apr 18 01:41:49 PM PDT 24 Apr 18 01:41:50 PM PDT 24 514967871 ps
T358 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.2687577937 Apr 18 01:41:38 PM PDT 24 Apr 18 01:41:39 PM PDT 24 354820870 ps
T359 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.132823768 Apr 18 01:41:34 PM PDT 24 Apr 18 01:41:36 PM PDT 24 1336299628 ps
T360 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.4085520423 Apr 18 01:41:44 PM PDT 24 Apr 18 01:41:45 PM PDT 24 451613647 ps
T361 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.3101589218 Apr 18 01:41:32 PM PDT 24 Apr 18 01:41:35 PM PDT 24 8438531324 ps
T362 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.1886061602 Apr 18 01:41:40 PM PDT 24 Apr 18 01:41:42 PM PDT 24 415351707 ps
T363 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.2679486434 Apr 18 01:41:42 PM PDT 24 Apr 18 01:41:44 PM PDT 24 425921573 ps
T364 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.3382406055 Apr 18 01:41:23 PM PDT 24 Apr 18 01:41:25 PM PDT 24 518809250 ps
T365 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.1753127117 Apr 18 01:41:24 PM PDT 24 Apr 18 01:41:27 PM PDT 24 600997707 ps
T366 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.1131732215 Apr 18 01:41:17 PM PDT 24 Apr 18 01:41:20 PM PDT 24 423538654 ps
T367 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.2881191168 Apr 18 01:41:13 PM PDT 24 Apr 18 01:41:19 PM PDT 24 2172641285 ps
T368 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.3845667051 Apr 18 01:41:37 PM PDT 24 Apr 18 01:41:39 PM PDT 24 412572223 ps
T369 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.1975190994 Apr 18 01:41:41 PM PDT 24 Apr 18 01:41:45 PM PDT 24 909038700 ps
T370 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.1229011427 Apr 18 01:41:19 PM PDT 24 Apr 18 01:41:20 PM PDT 24 446418118 ps
T371 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.3013382338 Apr 18 01:41:50 PM PDT 24 Apr 18 01:41:51 PM PDT 24 599630398 ps
T372 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.3612508600 Apr 18 01:41:40 PM PDT 24 Apr 18 01:41:42 PM PDT 24 1441444417 ps
T373 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.3540430151 Apr 18 01:41:37 PM PDT 24 Apr 18 01:41:40 PM PDT 24 431833846 ps
T374 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.3250693449 Apr 18 01:41:35 PM PDT 24 Apr 18 01:41:36 PM PDT 24 458883703 ps
T375 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.1577496278 Apr 18 01:41:49 PM PDT 24 Apr 18 01:41:56 PM PDT 24 2557716529 ps
T376 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.1461858316 Apr 18 01:41:38 PM PDT 24 Apr 18 01:41:39 PM PDT 24 556477679 ps
T377 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.1067256487 Apr 18 01:41:52 PM PDT 24 Apr 18 01:41:53 PM PDT 24 379530949 ps
T378 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.723851188 Apr 18 01:41:18 PM PDT 24 Apr 18 01:41:19 PM PDT 24 338394400 ps
T379 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.3635863787 Apr 18 01:41:50 PM PDT 24 Apr 18 01:41:51 PM PDT 24 475935737 ps
T380 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.1550463140 Apr 18 01:41:58 PM PDT 24 Apr 18 01:42:02 PM PDT 24 4143095657 ps
T381 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.31414406 Apr 18 01:41:48 PM PDT 24 Apr 18 01:41:49 PM PDT 24 303697035 ps
T382 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.936597573 Apr 18 01:41:19 PM PDT 24 Apr 18 01:41:21 PM PDT 24 533270908 ps
T383 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.3935415041 Apr 18 01:41:50 PM PDT 24 Apr 18 01:41:51 PM PDT 24 434870850 ps
T384 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.384288397 Apr 18 01:41:26 PM PDT 24 Apr 18 01:41:29 PM PDT 24 837114922 ps
T385 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.1354121872 Apr 18 01:41:54 PM PDT 24 Apr 18 01:41:57 PM PDT 24 365171254 ps
T386 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.1066738164 Apr 18 01:41:25 PM PDT 24 Apr 18 01:41:27 PM PDT 24 4546501038 ps
T387 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.1253318800 Apr 18 01:41:42 PM PDT 24 Apr 18 01:41:44 PM PDT 24 461548054 ps
T388 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.42830373 Apr 18 01:41:54 PM PDT 24 Apr 18 01:41:56 PM PDT 24 504496198 ps
T389 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.1974568930 Apr 18 01:41:39 PM PDT 24 Apr 18 01:41:54 PM PDT 24 8182672811 ps
T390 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.3236241841 Apr 18 01:41:54 PM PDT 24 Apr 18 01:41:55 PM PDT 24 395651759 ps
T391 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.2502461820 Apr 18 01:41:33 PM PDT 24 Apr 18 01:41:34 PM PDT 24 702313163 ps
T392 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.3578500137 Apr 18 01:41:33 PM PDT 24 Apr 18 01:41:36 PM PDT 24 1564619451 ps
T393 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.3222683711 Apr 18 01:41:24 PM PDT 24 Apr 18 01:41:26 PM PDT 24 512975801 ps
T394 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.207799821 Apr 18 01:41:16 PM PDT 24 Apr 18 01:41:17 PM PDT 24 513373129 ps
T395 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.946188028 Apr 18 01:41:51 PM PDT 24 Apr 18 01:41:52 PM PDT 24 284019704 ps
T396 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.2311225952 Apr 18 01:41:39 PM PDT 24 Apr 18 01:41:42 PM PDT 24 4001627872 ps
T397 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.2141187924 Apr 18 01:41:20 PM PDT 24 Apr 18 01:41:55 PM PDT 24 13657743680 ps
T398 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.1178109653 Apr 18 01:41:42 PM PDT 24 Apr 18 01:41:46 PM PDT 24 1296619796 ps
T399 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.1326835039 Apr 18 01:41:34 PM PDT 24 Apr 18 01:41:36 PM PDT 24 474081194 ps
T400 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.3958066102 Apr 18 01:41:32 PM PDT 24 Apr 18 01:41:33 PM PDT 24 284985501 ps
T401 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.1144421861 Apr 18 01:41:53 PM PDT 24 Apr 18 01:41:54 PM PDT 24 652007965 ps
T402 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.2802828294 Apr 18 01:41:24 PM PDT 24 Apr 18 01:41:26 PM PDT 24 2975237031 ps
T403 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.280867807 Apr 18 01:41:40 PM PDT 24 Apr 18 01:41:42 PM PDT 24 476217930 ps
T404 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.1259529091 Apr 18 01:41:10 PM PDT 24 Apr 18 01:41:12 PM PDT 24 344221933 ps
T405 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.1069585635 Apr 18 01:41:41 PM PDT 24 Apr 18 01:41:42 PM PDT 24 2205065131 ps
T406 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.2980887168 Apr 18 01:41:54 PM PDT 24 Apr 18 01:41:56 PM PDT 24 303895448 ps
T407 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.2978975760 Apr 18 01:41:38 PM PDT 24 Apr 18 01:41:39 PM PDT 24 606086485 ps
T408 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.461532409 Apr 18 01:41:49 PM PDT 24 Apr 18 01:41:50 PM PDT 24 340552161 ps
T409 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.2478246248 Apr 18 01:41:12 PM PDT 24 Apr 18 01:41:13 PM PDT 24 485631715 ps
T410 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.948244520 Apr 18 01:41:21 PM PDT 24 Apr 18 01:41:23 PM PDT 24 457007293 ps
T70 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.1148837493 Apr 18 01:41:16 PM PDT 24 Apr 18 01:41:17 PM PDT 24 442232437 ps
T411 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.2364533065 Apr 18 01:41:32 PM PDT 24 Apr 18 01:41:39 PM PDT 24 3940066921 ps
T412 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.1880272708 Apr 18 01:41:39 PM PDT 24 Apr 18 01:41:44 PM PDT 24 2330893062 ps
T413 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.688643839 Apr 18 01:41:54 PM PDT 24 Apr 18 01:41:55 PM PDT 24 395813901 ps
T414 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.1557445226 Apr 18 01:41:07 PM PDT 24 Apr 18 01:41:10 PM PDT 24 334944910 ps

Test location /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.1972962060
Short name T8
Test name
Test status
Simulation time 27615168920 ps
CPU time 296.6 seconds
Started Apr 18 01:40:51 PM PDT 24
Finished Apr 18 01:45:48 PM PDT 24
Peak memory 198304 kb
Host smart-ba95821b-ce2e-4b5e-959c-5adf1290d18b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972962060 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_reset.1972962060
Directory /workspace/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.2199645474
Short name T13
Test name
Test status
Simulation time 84982871613 ps
CPU time 173.54 seconds
Started Apr 18 01:40:20 PM PDT 24
Finished Apr 18 01:43:14 PM PDT 24
Peak memory 198300 kb
Host smart-1184ae5c-e1b6-4cab-84bf-13ca2e6808d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199645474 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.2199645474
Directory /workspace/9.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.1984031632
Short name T41
Test name
Test status
Simulation time 8532878403 ps
CPU time 4.23 seconds
Started Apr 18 01:41:14 PM PDT 24
Finished Apr 18 01:41:19 PM PDT 24
Peak memory 198276 kb
Host smart-6710652a-f497-4ab6-902f-aa176abbe6e6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984031632 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl
_intg_err.1984031632
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.3076875006
Short name T45
Test name
Test status
Simulation time 99577934331 ps
CPU time 745.07 seconds
Started Apr 18 01:41:02 PM PDT 24
Finished Apr 18 01:53:28 PM PDT 24
Peak memory 200760 kb
Host smart-475575a9-47fe-4230-b429-55ecd756bcb6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076875006 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.3076875006
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.2984012620
Short name T17
Test name
Test status
Simulation time 8118743383 ps
CPU time 6.76 seconds
Started Apr 18 01:40:12 PM PDT 24
Finished Apr 18 01:40:19 PM PDT 24
Peak memory 215284 kb
Host smart-3e96aa98-390a-48d2-a57d-5471a1d9bb6b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984012620 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.2984012620
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.135108485
Short name T9
Test name
Test status
Simulation time 229188005801 ps
CPU time 23.05 seconds
Started Apr 18 01:40:52 PM PDT 24
Finished Apr 18 01:41:15 PM PDT 24
Peak memory 193796 kb
Host smart-d592f489-43fe-4835-baff-dc9b512fc70f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135108485 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_a
ll.135108485
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.127463202
Short name T26
Test name
Test status
Simulation time 212144917475 ps
CPU time 588.81 seconds
Started Apr 18 01:40:15 PM PDT 24
Finished Apr 18 01:50:05 PM PDT 24
Peak memory 199848 kb
Host smart-04f49207-f7bd-42aa-90a3-2deac5240791
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127463202 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.127463202
Directory /workspace/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.914444567
Short name T72
Test name
Test status
Simulation time 556274441 ps
CPU time 1.5 seconds
Started Apr 18 01:41:15 PM PDT 24
Finished Apr 18 01:41:17 PM PDT 24
Peak memory 193340 kb
Host smart-d1d43888-98bc-4dc5-bd0f-fdf89f3b6318
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914444567 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.914444567
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.2777128826
Short name T102
Test name
Test status
Simulation time 8179866032 ps
CPU time 6.38 seconds
Started Apr 18 01:41:46 PM PDT 24
Finished Apr 18 01:41:53 PM PDT 24
Peak memory 198408 kb
Host smart-8b547ec7-3ff1-4c4b-a76d-82e3a7a4680a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777128826 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_t
l_intg_err.2777128826
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.2574306326
Short name T99
Test name
Test status
Simulation time 231619578917 ps
CPU time 345.37 seconds
Started Apr 18 01:40:23 PM PDT 24
Finished Apr 18 01:46:09 PM PDT 24
Peak memory 183380 kb
Host smart-014f46d5-71ca-4584-aa7a-d0120e109271
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574306326 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_
all.2574306326
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.3808228326
Short name T297
Test name
Test status
Simulation time 555825814 ps
CPU time 0.82 seconds
Started Apr 18 01:41:13 PM PDT 24
Finished Apr 18 01:41:14 PM PDT 24
Peak memory 193256 kb
Host smart-69b3a28b-75bd-450e-8576-a4a552725018
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808228326 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_a
liasing.3808228326
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.3945396798
Short name T336
Test name
Test status
Simulation time 14078533453 ps
CPU time 21.46 seconds
Started Apr 18 01:41:14 PM PDT 24
Finished Apr 18 01:41:36 PM PDT 24
Peak memory 192472 kb
Host smart-d4c9422c-d448-4409-9cf7-0185cec099b8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945396798 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_b
it_bash.3945396798
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.3383015688
Short name T294
Test name
Test status
Simulation time 741764442 ps
CPU time 1.79 seconds
Started Apr 18 01:41:10 PM PDT 24
Finished Apr 18 01:41:12 PM PDT 24
Peak memory 184040 kb
Host smart-94f9c2d9-7693-4e22-8cdc-651cdd7ae437
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383015688 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_h
w_reset.3383015688
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.3277570104
Short name T305
Test name
Test status
Simulation time 514955920 ps
CPU time 0.99 seconds
Started Apr 18 01:41:14 PM PDT 24
Finished Apr 18 01:41:15 PM PDT 24
Peak memory 195716 kb
Host smart-9ae2ee3f-60a3-4b5e-a5f6-02d8b2eca5f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277570104 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.3277570104
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.4183188972
Short name T292
Test name
Test status
Simulation time 452342126 ps
CPU time 0.7 seconds
Started Apr 18 01:41:09 PM PDT 24
Finished Apr 18 01:41:10 PM PDT 24
Peak memory 183936 kb
Host smart-cc3d89da-dd79-4b91-bc19-c1541e3fec8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183188972 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.4183188972
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.3009741832
Short name T277
Test name
Test status
Simulation time 483014027 ps
CPU time 0.69 seconds
Started Apr 18 01:41:10 PM PDT 24
Finished Apr 18 01:41:11 PM PDT 24
Peak memory 183868 kb
Host smart-24d34013-b85f-4a38-90c9-befef3507253
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009741832 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_t
imer_mem_partial_access.3009741832
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.1259529091
Short name T404
Test name
Test status
Simulation time 344221933 ps
CPU time 0.75 seconds
Started Apr 18 01:41:10 PM PDT 24
Finished Apr 18 01:41:12 PM PDT 24
Peak memory 183880 kb
Host smart-eac8099e-68d5-4687-852d-7c021d6d67b1
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259529091 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_w
alk.1259529091
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.2881191168
Short name T367
Test name
Test status
Simulation time 2172641285 ps
CPU time 5.74 seconds
Started Apr 18 01:41:13 PM PDT 24
Finished Apr 18 01:41:19 PM PDT 24
Peak memory 193748 kb
Host smart-306662ab-f587-4ba8-9834-f8faa420a092
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881191168 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon
_timer_same_csr_outstanding.2881191168
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.1557445226
Short name T414
Test name
Test status
Simulation time 334944910 ps
CPU time 2.09 seconds
Started Apr 18 01:41:07 PM PDT 24
Finished Apr 18 01:41:10 PM PDT 24
Peak memory 198864 kb
Host smart-4e6c4363-6838-492d-93fc-6a44360ba1c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557445226 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.1557445226
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.348794404
Short name T313
Test name
Test status
Simulation time 7995546910 ps
CPU time 12.93 seconds
Started Apr 18 01:41:08 PM PDT 24
Finished Apr 18 01:41:21 PM PDT 24
Peak memory 198276 kb
Host smart-700619dd-c329-4b05-a674-a645561cbc45
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348794404 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_
intg_err.348794404
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.1208707432
Short name T62
Test name
Test status
Simulation time 642860561 ps
CPU time 1.76 seconds
Started Apr 18 01:41:14 PM PDT 24
Finished Apr 18 01:41:17 PM PDT 24
Peak memory 194472 kb
Host smart-f589d65e-a11d-454b-84b5-81b473cc84f7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208707432 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_a
liasing.1208707432
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.768935529
Short name T68
Test name
Test status
Simulation time 13399546990 ps
CPU time 8.46 seconds
Started Apr 18 01:41:14 PM PDT 24
Finished Apr 18 01:41:23 PM PDT 24
Peak memory 195640 kb
Host smart-46f1e54a-44aa-4206-98d5-cc0599e6ebbf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768935529 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_bi
t_bash.768935529
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.756405620
Short name T44
Test name
Test status
Simulation time 1241581404 ps
CPU time 2.32 seconds
Started Apr 18 01:41:15 PM PDT 24
Finished Apr 18 01:41:18 PM PDT 24
Peak memory 184040 kb
Host smart-2cb502e1-64c1-444b-a6ee-3a9dfc6bd13a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756405620 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_hw
_reset.756405620
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.439300384
Short name T293
Test name
Test status
Simulation time 555511878 ps
CPU time 0.88 seconds
Started Apr 18 01:41:13 PM PDT 24
Finished Apr 18 01:41:14 PM PDT 24
Peak memory 196560 kb
Host smart-8530d2d7-c246-40af-a0c3-2c73bb06cfd3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439300384 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.439300384
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.1148837493
Short name T70
Test name
Test status
Simulation time 442232437 ps
CPU time 1.3 seconds
Started Apr 18 01:41:16 PM PDT 24
Finished Apr 18 01:41:17 PM PDT 24
Peak memory 193404 kb
Host smart-f30ecf6c-1167-4815-b594-e46e30bb6059
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148837493 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.1148837493
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.2478246248
Short name T409
Test name
Test status
Simulation time 485631715 ps
CPU time 0.74 seconds
Started Apr 18 01:41:12 PM PDT 24
Finished Apr 18 01:41:13 PM PDT 24
Peak memory 183912 kb
Host smart-51bee0f1-228f-4bd4-afaa-495268e0b504
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478246248 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.2478246248
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.3954929208
Short name T344
Test name
Test status
Simulation time 303901945 ps
CPU time 0.6 seconds
Started Apr 18 01:41:15 PM PDT 24
Finished Apr 18 01:41:16 PM PDT 24
Peak memory 183872 kb
Host smart-02b5c625-36bb-46ea-9131-c94d506f087f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954929208 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_t
imer_mem_partial_access.3954929208
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.207799821
Short name T394
Test name
Test status
Simulation time 513373129 ps
CPU time 0.71 seconds
Started Apr 18 01:41:16 PM PDT 24
Finished Apr 18 01:41:17 PM PDT 24
Peak memory 183868 kb
Host smart-73dda985-7d62-438f-a6a6-fd32585b85c3
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207799821 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_wa
lk.207799821
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.1577496278
Short name T375
Test name
Test status
Simulation time 2557716529 ps
CPU time 5.9 seconds
Started Apr 18 01:41:49 PM PDT 24
Finished Apr 18 01:41:56 PM PDT 24
Peak memory 184156 kb
Host smart-895ad7f2-f63a-47a7-a5b3-58cd357d469b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577496278 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon
_timer_same_csr_outstanding.1577496278
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.1869201854
Short name T314
Test name
Test status
Simulation time 557139415 ps
CPU time 1.15 seconds
Started Apr 18 01:41:14 PM PDT 24
Finished Apr 18 01:41:16 PM PDT 24
Peak memory 198668 kb
Host smart-5548352d-4921-4732-8c4f-71aa7c1c4f7d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869201854 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.1869201854
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.3922001873
Short name T317
Test name
Test status
Simulation time 472932849 ps
CPU time 1.4 seconds
Started Apr 18 01:41:32 PM PDT 24
Finished Apr 18 01:41:34 PM PDT 24
Peak memory 195712 kb
Host smart-d3ba8ad6-a2ab-4248-9444-5b543edf3203
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922001873 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.3922001873
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.1609875130
Short name T338
Test name
Test status
Simulation time 467135177 ps
CPU time 1.29 seconds
Started Apr 18 01:41:32 PM PDT 24
Finished Apr 18 01:41:34 PM PDT 24
Peak memory 183924 kb
Host smart-ba7787fb-4b49-4c34-b4ce-497186b9c092
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609875130 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.1609875130
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.3633136998
Short name T288
Test name
Test status
Simulation time 496814342 ps
CPU time 1.16 seconds
Started Apr 18 01:41:34 PM PDT 24
Finished Apr 18 01:41:36 PM PDT 24
Peak memory 183948 kb
Host smart-78010a53-5fbe-4deb-b1bf-46721da277c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633136998 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.3633136998
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.3578500137
Short name T392
Test name
Test status
Simulation time 1564619451 ps
CPU time 2.69 seconds
Started Apr 18 01:41:33 PM PDT 24
Finished Apr 18 01:41:36 PM PDT 24
Peak memory 193596 kb
Host smart-8de921c7-483d-4649-9cf3-b2d438b1d3d0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578500137 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.ao
n_timer_same_csr_outstanding.3578500137
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.2502461820
Short name T391
Test name
Test status
Simulation time 702313163 ps
CPU time 1.26 seconds
Started Apr 18 01:41:33 PM PDT 24
Finished Apr 18 01:41:34 PM PDT 24
Peak memory 198900 kb
Host smart-a042e1c0-515e-407c-a187-4ccefad27431
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502461820 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.2502461820
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.2364533065
Short name T411
Test name
Test status
Simulation time 3940066921 ps
CPU time 6.05 seconds
Started Apr 18 01:41:32 PM PDT 24
Finished Apr 18 01:41:39 PM PDT 24
Peak memory 197872 kb
Host smart-015cbe5b-088c-463f-91b1-a6d680b2ff19
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364533065 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_t
l_intg_err.2364533065
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.1253318800
Short name T387
Test name
Test status
Simulation time 461548054 ps
CPU time 1.38 seconds
Started Apr 18 01:41:42 PM PDT 24
Finished Apr 18 01:41:44 PM PDT 24
Peak memory 196192 kb
Host smart-2b4911c3-cb37-49d2-bb7b-1fcd8ab6fc47
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253318800 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.1253318800
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.862068745
Short name T78
Test name
Test status
Simulation time 397012596 ps
CPU time 1.07 seconds
Started Apr 18 01:41:39 PM PDT 24
Finished Apr 18 01:41:41 PM PDT 24
Peak memory 193244 kb
Host smart-cbeddb2b-1749-4c0a-8f16-dc7227204601
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862068745 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.862068745
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.3448649638
Short name T312
Test name
Test status
Simulation time 387582747 ps
CPU time 1.06 seconds
Started Apr 18 01:41:33 PM PDT 24
Finished Apr 18 01:41:34 PM PDT 24
Peak memory 183960 kb
Host smart-5af95686-7dc4-4e3b-8952-ffbe82c1bb78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448649638 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.3448649638
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.3612508600
Short name T372
Test name
Test status
Simulation time 1441444417 ps
CPU time 1.13 seconds
Started Apr 18 01:41:40 PM PDT 24
Finished Apr 18 01:41:42 PM PDT 24
Peak memory 193544 kb
Host smart-4c37c93f-c9f4-441b-ba09-73eb08dc7898
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612508600 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.ao
n_timer_same_csr_outstanding.3612508600
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.3668840026
Short name T342
Test name
Test status
Simulation time 507583252 ps
CPU time 2 seconds
Started Apr 18 01:41:33 PM PDT 24
Finished Apr 18 01:41:36 PM PDT 24
Peak memory 198756 kb
Host smart-7246d3b9-80e4-44b4-b38f-5895231cdcae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668840026 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.3668840026
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.3101589218
Short name T361
Test name
Test status
Simulation time 8438531324 ps
CPU time 2.17 seconds
Started Apr 18 01:41:32 PM PDT 24
Finished Apr 18 01:41:35 PM PDT 24
Peak memory 198464 kb
Host smart-cfbf69d3-9531-4359-a295-9c3b4b364e44
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101589218 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_t
l_intg_err.3101589218
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.3845667051
Short name T368
Test name
Test status
Simulation time 412572223 ps
CPU time 0.83 seconds
Started Apr 18 01:41:37 PM PDT 24
Finished Apr 18 01:41:39 PM PDT 24
Peak memory 196400 kb
Host smart-e21a02cb-1fa7-4cea-915d-a8e45f1d566a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845667051 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.3845667051
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.1468701893
Short name T35
Test name
Test status
Simulation time 309710026 ps
CPU time 0.74 seconds
Started Apr 18 01:41:38 PM PDT 24
Finished Apr 18 01:41:39 PM PDT 24
Peak memory 184180 kb
Host smart-922f5263-f564-49a6-86a3-13694ed3e4d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468701893 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.1468701893
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.3083727249
Short name T335
Test name
Test status
Simulation time 304747188 ps
CPU time 0.64 seconds
Started Apr 18 01:41:40 PM PDT 24
Finished Apr 18 01:41:41 PM PDT 24
Peak memory 183948 kb
Host smart-29069505-9c0f-4df4-bbbd-a126d22ca694
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083727249 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.3083727249
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.1773022608
Short name T80
Test name
Test status
Simulation time 1587437433 ps
CPU time 1.5 seconds
Started Apr 18 01:41:39 PM PDT 24
Finished Apr 18 01:41:41 PM PDT 24
Peak memory 193500 kb
Host smart-f3565cad-65fd-46b2-9782-6541a2f8632e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773022608 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.ao
n_timer_same_csr_outstanding.1773022608
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.405747924
Short name T290
Test name
Test status
Simulation time 567207496 ps
CPU time 2.26 seconds
Started Apr 18 01:41:42 PM PDT 24
Finished Apr 18 01:41:45 PM PDT 24
Peak memory 198920 kb
Host smart-b875f81f-d7a1-4f7e-aeca-fe38b5f2579e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405747924 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.405747924
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.2499685956
Short name T346
Test name
Test status
Simulation time 4338715902 ps
CPU time 7.63 seconds
Started Apr 18 01:41:40 PM PDT 24
Finished Apr 18 01:41:49 PM PDT 24
Peak memory 197920 kb
Host smart-a985ecfd-0370-485b-ae6a-582b8d38e8ad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499685956 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_t
l_intg_err.2499685956
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.3293646812
Short name T104
Test name
Test status
Simulation time 543677570 ps
CPU time 1.37 seconds
Started Apr 18 01:41:38 PM PDT 24
Finished Apr 18 01:41:40 PM PDT 24
Peak memory 196168 kb
Host smart-c96f306d-fda9-4fac-b25f-7357563be864
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293646812 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.3293646812
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.1734236434
Short name T82
Test name
Test status
Simulation time 327622173 ps
CPU time 0.94 seconds
Started Apr 18 01:41:42 PM PDT 24
Finished Apr 18 01:41:43 PM PDT 24
Peak memory 193440 kb
Host smart-cf53998d-db6d-4da0-b7d2-2191e94644d7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734236434 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.1734236434
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.2200908959
Short name T324
Test name
Test status
Simulation time 490636769 ps
CPU time 0.72 seconds
Started Apr 18 01:41:42 PM PDT 24
Finished Apr 18 01:41:43 PM PDT 24
Peak memory 183932 kb
Host smart-a03d9ee3-c267-4088-9c18-846e74b0cc77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200908959 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.2200908959
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.1880272708
Short name T412
Test name
Test status
Simulation time 2330893062 ps
CPU time 3.94 seconds
Started Apr 18 01:41:39 PM PDT 24
Finished Apr 18 01:41:44 PM PDT 24
Peak memory 194960 kb
Host smart-625bf012-09b0-4547-96a0-d151d4be6dad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880272708 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.ao
n_timer_same_csr_outstanding.1880272708
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.1143699985
Short name T310
Test name
Test status
Simulation time 381954328 ps
CPU time 1.97 seconds
Started Apr 18 01:41:38 PM PDT 24
Finished Apr 18 01:41:40 PM PDT 24
Peak memory 198892 kb
Host smart-8de5f06d-86f0-4cb9-905b-9292a6bb3bf3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143699985 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.1143699985
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.1772465781
Short name T101
Test name
Test status
Simulation time 8537488034 ps
CPU time 7.76 seconds
Started Apr 18 01:41:46 PM PDT 24
Finished Apr 18 01:41:54 PM PDT 24
Peak memory 198208 kb
Host smart-3c6a5652-f914-4f68-9f02-e3ad862bb51f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772465781 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_t
l_intg_err.1772465781
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.1117304145
Short name T106
Test name
Test status
Simulation time 554890972 ps
CPU time 1.58 seconds
Started Apr 18 01:41:45 PM PDT 24
Finished Apr 18 01:41:47 PM PDT 24
Peak memory 196056 kb
Host smart-45ab03f7-b410-4618-abef-900c283f3c9b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117304145 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.1117304145
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.365831309
Short name T67
Test name
Test status
Simulation time 345179713 ps
CPU time 1.13 seconds
Started Apr 18 01:41:44 PM PDT 24
Finished Apr 18 01:41:46 PM PDT 24
Peak memory 193236 kb
Host smart-0a29f245-cac2-491d-b3ce-52f5d4812ed3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365831309 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.365831309
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.280867807
Short name T403
Test name
Test status
Simulation time 476217930 ps
CPU time 0.74 seconds
Started Apr 18 01:41:40 PM PDT 24
Finished Apr 18 01:41:42 PM PDT 24
Peak memory 183972 kb
Host smart-9926a707-f5b8-4938-8b80-99ad0016c4c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280867807 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.280867807
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.3801227639
Short name T340
Test name
Test status
Simulation time 1294182229 ps
CPU time 2.71 seconds
Started Apr 18 01:41:40 PM PDT 24
Finished Apr 18 01:41:44 PM PDT 24
Peak memory 184020 kb
Host smart-286ff524-5882-4099-ac2c-af38a7526904
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801227639 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao
n_timer_same_csr_outstanding.3801227639
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.4139797942
Short name T289
Test name
Test status
Simulation time 466044235 ps
CPU time 2.12 seconds
Started Apr 18 01:41:37 PM PDT 24
Finished Apr 18 01:41:40 PM PDT 24
Peak memory 198848 kb
Host smart-97414451-6e4b-4719-98d8-f442b9d2e950
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139797942 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.4139797942
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.1974568930
Short name T389
Test name
Test status
Simulation time 8182672811 ps
CPU time 14.06 seconds
Started Apr 18 01:41:39 PM PDT 24
Finished Apr 18 01:41:54 PM PDT 24
Peak memory 198284 kb
Host smart-b2383106-f0c2-4be0-83a8-78aff7b2ba67
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974568930 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_t
l_intg_err.1974568930
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.1822198096
Short name T295
Test name
Test status
Simulation time 565940964 ps
CPU time 1.07 seconds
Started Apr 18 01:41:40 PM PDT 24
Finished Apr 18 01:41:42 PM PDT 24
Peak memory 196260 kb
Host smart-d1cbdaf1-3948-49c8-a4e2-f59f1ebd2da4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822198096 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.1822198096
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.1886061602
Short name T362
Test name
Test status
Simulation time 415351707 ps
CPU time 0.72 seconds
Started Apr 18 01:41:40 PM PDT 24
Finished Apr 18 01:41:42 PM PDT 24
Peak memory 184092 kb
Host smart-1cf2a107-9890-4316-b79e-da78cca69e9c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886061602 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.1886061602
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.2687577937
Short name T358
Test name
Test status
Simulation time 354820870 ps
CPU time 0.59 seconds
Started Apr 18 01:41:38 PM PDT 24
Finished Apr 18 01:41:39 PM PDT 24
Peak memory 183936 kb
Host smart-c25e9148-fb9e-48b6-a4de-0e38c1aedf1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687577937 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.2687577937
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.1178109653
Short name T398
Test name
Test status
Simulation time 1296619796 ps
CPU time 3.67 seconds
Started Apr 18 01:41:42 PM PDT 24
Finished Apr 18 01:41:46 PM PDT 24
Peak memory 193556 kb
Host smart-c20e9a35-f931-4758-b55d-16a5c9046cfb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178109653 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.ao
n_timer_same_csr_outstanding.1178109653
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.1382305733
Short name T284
Test name
Test status
Simulation time 385265882 ps
CPU time 1.87 seconds
Started Apr 18 01:41:45 PM PDT 24
Finished Apr 18 01:41:47 PM PDT 24
Peak memory 198764 kb
Host smart-f5786caf-4592-4b07-aebe-756a6434bc4b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382305733 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.1382305733
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.2978975760
Short name T407
Test name
Test status
Simulation time 606086485 ps
CPU time 0.93 seconds
Started Apr 18 01:41:38 PM PDT 24
Finished Apr 18 01:41:39 PM PDT 24
Peak memory 197668 kb
Host smart-b8b13185-a138-4d9c-8059-f568aae5155a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978975760 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.2978975760
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.1455616499
Short name T71
Test name
Test status
Simulation time 414838096 ps
CPU time 1.26 seconds
Started Apr 18 01:41:40 PM PDT 24
Finished Apr 18 01:41:42 PM PDT 24
Peak memory 193336 kb
Host smart-d39b8771-c608-49f4-a4d9-763ccf552f95
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455616499 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.1455616499
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.1461858316
Short name T376
Test name
Test status
Simulation time 556477679 ps
CPU time 0.65 seconds
Started Apr 18 01:41:38 PM PDT 24
Finished Apr 18 01:41:39 PM PDT 24
Peak memory 183888 kb
Host smart-8825abd1-18e1-47cc-b1cd-82039a378365
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461858316 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.1461858316
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.1069585635
Short name T405
Test name
Test status
Simulation time 2205065131 ps
CPU time 1.05 seconds
Started Apr 18 01:41:41 PM PDT 24
Finished Apr 18 01:41:42 PM PDT 24
Peak memory 194936 kb
Host smart-8be496e2-657a-4e75-af66-ccd0dbda05de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069585635 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.ao
n_timer_same_csr_outstanding.1069585635
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.1975190994
Short name T369
Test name
Test status
Simulation time 909038700 ps
CPU time 2.78 seconds
Started Apr 18 01:41:41 PM PDT 24
Finished Apr 18 01:41:45 PM PDT 24
Peak memory 198812 kb
Host smart-9aae99f2-9d60-4b35-866d-73dbdc22ef15
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975190994 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.1975190994
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.2311225952
Short name T396
Test name
Test status
Simulation time 4001627872 ps
CPU time 2.76 seconds
Started Apr 18 01:41:39 PM PDT 24
Finished Apr 18 01:41:42 PM PDT 24
Peak memory 197852 kb
Host smart-75641766-a8f9-4ac1-be5a-d288f0cfe87f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311225952 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_t
l_intg_err.2311225952
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.1296548999
Short name T308
Test name
Test status
Simulation time 537958125 ps
CPU time 1.18 seconds
Started Apr 18 01:41:44 PM PDT 24
Finished Apr 18 01:41:46 PM PDT 24
Peak memory 198744 kb
Host smart-605dce54-bc12-4247-a390-f7ac1abf5137
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296548999 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.1296548999
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.4186130238
Short name T352
Test name
Test status
Simulation time 397193480 ps
CPU time 0.67 seconds
Started Apr 18 01:41:54 PM PDT 24
Finished Apr 18 01:41:55 PM PDT 24
Peak memory 183944 kb
Host smart-cae9a095-dc22-4b20-bb5d-4c390612dbf7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186130238 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.4186130238
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.31414406
Short name T381
Test name
Test status
Simulation time 303697035 ps
CPU time 0.74 seconds
Started Apr 18 01:41:48 PM PDT 24
Finished Apr 18 01:41:49 PM PDT 24
Peak memory 183984 kb
Host smart-34cd4a33-48f0-4cce-9761-64d28eeaebad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31414406 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.31414406
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.125723495
Short name T81
Test name
Test status
Simulation time 2625792110 ps
CPU time 1.03 seconds
Started Apr 18 01:41:46 PM PDT 24
Finished Apr 18 01:41:47 PM PDT 24
Peak memory 194716 kb
Host smart-9e153dd9-accd-4421-83bc-348511aa129f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125723495 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon
_timer_same_csr_outstanding.125723495
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.3540430151
Short name T373
Test name
Test status
Simulation time 431833846 ps
CPU time 2.52 seconds
Started Apr 18 01:41:37 PM PDT 24
Finished Apr 18 01:41:40 PM PDT 24
Peak memory 198836 kb
Host smart-c9593059-da81-48f7-9cb0-74aeb8ad79f1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540430151 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.3540430151
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.4132826391
Short name T103
Test name
Test status
Simulation time 4238980613 ps
CPU time 2.44 seconds
Started Apr 18 01:41:41 PM PDT 24
Finished Apr 18 01:41:44 PM PDT 24
Peak memory 197796 kb
Host smart-da1e10eb-233a-469a-b3f9-43a250dd9527
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132826391 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_t
l_intg_err.4132826391
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.1453373388
Short name T326
Test name
Test status
Simulation time 417618830 ps
CPU time 1.18 seconds
Started Apr 18 01:41:44 PM PDT 24
Finished Apr 18 01:41:45 PM PDT 24
Peak memory 196520 kb
Host smart-9328c6bb-591a-4ebd-a11a-32bde159f691
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453373388 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.1453373388
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.688643839
Short name T413
Test name
Test status
Simulation time 395813901 ps
CPU time 1.17 seconds
Started Apr 18 01:41:54 PM PDT 24
Finished Apr 18 01:41:55 PM PDT 24
Peak memory 184224 kb
Host smart-cdcba389-6e74-43c5-8d53-06c16c43f633
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688643839 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.688643839
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.4284817409
Short name T315
Test name
Test status
Simulation time 328598819 ps
CPU time 1.08 seconds
Started Apr 18 01:41:45 PM PDT 24
Finished Apr 18 01:41:47 PM PDT 24
Peak memory 183948 kb
Host smart-a1728fea-8e63-4891-8261-60c967a3ed78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284817409 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.4284817409
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.1980038708
Short name T39
Test name
Test status
Simulation time 2659820131 ps
CPU time 6.82 seconds
Started Apr 18 01:41:46 PM PDT 24
Finished Apr 18 01:41:53 PM PDT 24
Peak memory 184072 kb
Host smart-abc5547e-7614-45bb-a210-32fe94419785
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980038708 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.ao
n_timer_same_csr_outstanding.1980038708
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.1354121872
Short name T385
Test name
Test status
Simulation time 365171254 ps
CPU time 2.14 seconds
Started Apr 18 01:41:54 PM PDT 24
Finished Apr 18 01:41:57 PM PDT 24
Peak memory 198820 kb
Host smart-7e7454fd-ea4b-4875-a2e9-9cf04d0dd8d1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354121872 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.1354121872
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.2773072510
Short name T42
Test name
Test status
Simulation time 4275934378 ps
CPU time 2.45 seconds
Started Apr 18 01:41:43 PM PDT 24
Finished Apr 18 01:41:46 PM PDT 24
Peak memory 196472 kb
Host smart-1b7e4e3b-b928-4dec-ab79-d157e8db9f3d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773072510 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_t
l_intg_err.2773072510
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.1842192321
Short name T334
Test name
Test status
Simulation time 491339851 ps
CPU time 0.87 seconds
Started Apr 18 01:41:44 PM PDT 24
Finished Apr 18 01:41:45 PM PDT 24
Peak memory 195540 kb
Host smart-6c82d7c4-30b2-44bd-a66b-94b51c259e95
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842192321 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.1842192321
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.3453202
Short name T65
Test name
Test status
Simulation time 518352203 ps
CPU time 1.29 seconds
Started Apr 18 01:41:44 PM PDT 24
Finished Apr 18 01:41:45 PM PDT 24
Peak memory 192336 kb
Host smart-5b94cac3-c086-43b0-a660-c99e37632c8a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453202 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.3453202
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.225473160
Short name T304
Test name
Test status
Simulation time 387165194 ps
CPU time 0.8 seconds
Started Apr 18 01:41:42 PM PDT 24
Finished Apr 18 01:41:44 PM PDT 24
Peak memory 183952 kb
Host smart-55884f39-b372-4cdc-91b9-4a4c187d0266
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225473160 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.225473160
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.341614863
Short name T349
Test name
Test status
Simulation time 1801218690 ps
CPU time 4.83 seconds
Started Apr 18 01:41:53 PM PDT 24
Finished Apr 18 01:41:58 PM PDT 24
Peak memory 184216 kb
Host smart-2482cf92-b182-4ef3-93f2-e76867b8ec54
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341614863 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon
_timer_same_csr_outstanding.341614863
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.459841149
Short name T300
Test name
Test status
Simulation time 414867653 ps
CPU time 1.92 seconds
Started Apr 18 01:41:46 PM PDT 24
Finished Apr 18 01:41:48 PM PDT 24
Peak memory 198788 kb
Host smart-9b7f6b4a-64e1-4736-aa6e-6093446ddbf9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459841149 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.459841149
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.1550463140
Short name T380
Test name
Test status
Simulation time 4143095657 ps
CPU time 3.59 seconds
Started Apr 18 01:41:58 PM PDT 24
Finished Apr 18 01:42:02 PM PDT 24
Peak memory 196504 kb
Host smart-5525061f-f3a7-433a-93aa-cbb417a3fa95
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550463140 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_t
l_intg_err.1550463140
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.936597573
Short name T382
Test name
Test status
Simulation time 533270908 ps
CPU time 1.68 seconds
Started Apr 18 01:41:19 PM PDT 24
Finished Apr 18 01:41:21 PM PDT 24
Peak memory 194132 kb
Host smart-eea4a211-2340-4e97-96cf-7198a72baf6d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936597573 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_al
iasing.936597573
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.2141187924
Short name T397
Test name
Test status
Simulation time 13657743680 ps
CPU time 33.69 seconds
Started Apr 18 01:41:20 PM PDT 24
Finished Apr 18 01:41:55 PM PDT 24
Peak memory 184268 kb
Host smart-c82fe0fa-46d3-48a9-8bff-80e4da66d562
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141187924 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_b
it_bash.2141187924
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.975295613
Short name T303
Test name
Test status
Simulation time 708266012 ps
CPU time 1.79 seconds
Started Apr 18 01:41:21 PM PDT 24
Finished Apr 18 01:41:23 PM PDT 24
Peak memory 184008 kb
Host smart-6c1c7f97-9cdb-491a-9a01-7bf23e80bb77
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975295613 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_hw
_reset.975295613
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.1229011427
Short name T370
Test name
Test status
Simulation time 446418118 ps
CPU time 0.67 seconds
Started Apr 18 01:41:19 PM PDT 24
Finished Apr 18 01:41:20 PM PDT 24
Peak memory 196080 kb
Host smart-e24288e4-2dae-4572-83b5-78db8e5ba8a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229011427 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.1229011427
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.782911959
Short name T63
Test name
Test status
Simulation time 493411816 ps
CPU time 1.33 seconds
Started Apr 18 01:41:21 PM PDT 24
Finished Apr 18 01:41:22 PM PDT 24
Peak memory 184188 kb
Host smart-f73c96c3-ab56-4a23-afa5-c32396d3b2bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782911959 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.782911959
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.2522671690
Short name T302
Test name
Test status
Simulation time 338842409 ps
CPU time 0.59 seconds
Started Apr 18 01:41:19 PM PDT 24
Finished Apr 18 01:41:20 PM PDT 24
Peak memory 183944 kb
Host smart-20b4a7e8-4038-47e9-a2c1-3006a60707ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522671690 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.2522671690
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.1586609752
Short name T299
Test name
Test status
Simulation time 502451624 ps
CPU time 0.56 seconds
Started Apr 18 01:41:20 PM PDT 24
Finished Apr 18 01:41:21 PM PDT 24
Peak memory 183872 kb
Host smart-683bc9a5-5e55-47e4-8e28-1d6516c831bc
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586609752 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_t
imer_mem_partial_access.1586609752
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.1191019449
Short name T353
Test name
Test status
Simulation time 493819775 ps
CPU time 1.27 seconds
Started Apr 18 01:41:21 PM PDT 24
Finished Apr 18 01:41:22 PM PDT 24
Peak memory 183880 kb
Host smart-04b9a112-7ecc-452b-9766-e8873c2c884a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191019449 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_w
alk.1191019449
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.966136946
Short name T77
Test name
Test status
Simulation time 2733078704 ps
CPU time 5.62 seconds
Started Apr 18 01:41:25 PM PDT 24
Finished Apr 18 01:41:31 PM PDT 24
Peak memory 194156 kb
Host smart-400cb690-8ca7-4499-88f7-d179092c1724
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966136946 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_
timer_same_csr_outstanding.966136946
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.1131732215
Short name T366
Test name
Test status
Simulation time 423538654 ps
CPU time 2.54 seconds
Started Apr 18 01:41:17 PM PDT 24
Finished Apr 18 01:41:20 PM PDT 24
Peak memory 198880 kb
Host smart-650cd844-7afb-40fe-ae11-c6d29c21396f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131732215 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.1131732215
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.3531307050
Short name T307
Test name
Test status
Simulation time 8216789141 ps
CPU time 4.2 seconds
Started Apr 18 01:41:21 PM PDT 24
Finished Apr 18 01:41:26 PM PDT 24
Peak memory 198268 kb
Host smart-6d7494d3-05c7-41d4-9b31-04c64a603acc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531307050 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl
_intg_err.3531307050
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.3204235737
Short name T343
Test name
Test status
Simulation time 591819086 ps
CPU time 0.64 seconds
Started Apr 18 01:41:54 PM PDT 24
Finished Apr 18 01:41:55 PM PDT 24
Peak memory 183928 kb
Host smart-f2e24288-ac71-458c-a031-535598a5cefa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204235737 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.3204235737
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.4085520423
Short name T360
Test name
Test status
Simulation time 451613647 ps
CPU time 0.68 seconds
Started Apr 18 01:41:44 PM PDT 24
Finished Apr 18 01:41:45 PM PDT 24
Peak memory 183952 kb
Host smart-9786f7af-f931-4ef3-bb90-63bb03553dd7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085520423 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.4085520423
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.2894042788
Short name T298
Test name
Test status
Simulation time 471248817 ps
CPU time 0.89 seconds
Started Apr 18 01:41:45 PM PDT 24
Finished Apr 18 01:41:46 PM PDT 24
Peak memory 183944 kb
Host smart-26a57103-9fd3-44cd-9887-102e48fe1de8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894042788 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.2894042788
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.576288507
Short name T279
Test name
Test status
Simulation time 279332115 ps
CPU time 0.82 seconds
Started Apr 18 01:41:55 PM PDT 24
Finished Apr 18 01:41:57 PM PDT 24
Peak memory 183928 kb
Host smart-bad80a0d-2694-4fb9-8e05-a975468286e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576288507 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.576288507
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.4214353648
Short name T329
Test name
Test status
Simulation time 464487398 ps
CPU time 0.68 seconds
Started Apr 18 01:41:44 PM PDT 24
Finished Apr 18 01:41:45 PM PDT 24
Peak memory 183964 kb
Host smart-904cfc75-a0c4-4422-9001-6b183f95a8bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214353648 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.4214353648
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.3235805125
Short name T280
Test name
Test status
Simulation time 356968840 ps
CPU time 0.66 seconds
Started Apr 18 01:41:43 PM PDT 24
Finished Apr 18 01:41:44 PM PDT 24
Peak memory 183932 kb
Host smart-9567bcbf-8330-4e26-97a2-3cb788422e52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235805125 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.3235805125
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.3864489028
Short name T345
Test name
Test status
Simulation time 391118936 ps
CPU time 0.55 seconds
Started Apr 18 01:41:44 PM PDT 24
Finished Apr 18 01:41:45 PM PDT 24
Peak memory 183956 kb
Host smart-033c0700-5e28-4608-81ff-6cabbebd769e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864489028 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.3864489028
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.1144421861
Short name T401
Test name
Test status
Simulation time 652007965 ps
CPU time 0.57 seconds
Started Apr 18 01:41:53 PM PDT 24
Finished Apr 18 01:41:54 PM PDT 24
Peak memory 183928 kb
Host smart-70ad8b89-7f0f-4bbf-a94e-04a294158bd9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144421861 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.1144421861
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.2679486434
Short name T363
Test name
Test status
Simulation time 425921573 ps
CPU time 0.99 seconds
Started Apr 18 01:41:42 PM PDT 24
Finished Apr 18 01:41:44 PM PDT 24
Peak memory 183948 kb
Host smart-e8aa1905-a835-42eb-938f-2e00b3171200
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679486434 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.2679486434
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.2206459507
Short name T316
Test name
Test status
Simulation time 283881958 ps
CPU time 0.74 seconds
Started Apr 18 01:41:43 PM PDT 24
Finished Apr 18 01:41:45 PM PDT 24
Peak memory 183904 kb
Host smart-393b7b57-d62f-487b-be94-c33b30ddb164
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206459507 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.2206459507
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.920596500
Short name T319
Test name
Test status
Simulation time 384939059 ps
CPU time 1.08 seconds
Started Apr 18 01:41:23 PM PDT 24
Finished Apr 18 01:41:24 PM PDT 24
Peak memory 193496 kb
Host smart-ae244045-aa09-4bb0-ab4b-40ccda79966c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920596500 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_al
iasing.920596500
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.3519737296
Short name T74
Test name
Test status
Simulation time 1181671230 ps
CPU time 1.59 seconds
Started Apr 18 01:41:22 PM PDT 24
Finished Apr 18 01:41:24 PM PDT 24
Peak memory 192444 kb
Host smart-66beb3cb-0813-4db2-8533-d3e7b81fc6e3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519737296 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_b
it_bash.3519737296
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.1650736679
Short name T40
Test name
Test status
Simulation time 955500879 ps
CPU time 0.9 seconds
Started Apr 18 01:41:21 PM PDT 24
Finished Apr 18 01:41:22 PM PDT 24
Peak memory 184024 kb
Host smart-5246d029-1d0e-41a5-aa27-d42e44713bf5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650736679 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_h
w_reset.1650736679
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.2439003634
Short name T105
Test name
Test status
Simulation time 492177989 ps
CPU time 1.5 seconds
Started Apr 18 01:41:21 PM PDT 24
Finished Apr 18 01:41:23 PM PDT 24
Peak memory 196652 kb
Host smart-03d40031-7f0f-4c3e-9115-f09d78862f8d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439003634 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.2439003634
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.498887818
Short name T306
Test name
Test status
Simulation time 486696749 ps
CPU time 1.3 seconds
Started Apr 18 01:41:21 PM PDT 24
Finished Apr 18 01:41:23 PM PDT 24
Peak memory 183932 kb
Host smart-277d7f84-b3ae-489b-9dba-2dddf9715de1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498887818 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.498887818
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.1679417745
Short name T348
Test name
Test status
Simulation time 361111397 ps
CPU time 1.03 seconds
Started Apr 18 01:41:21 PM PDT 24
Finished Apr 18 01:41:23 PM PDT 24
Peak memory 183932 kb
Host smart-74cf5bde-e899-4a6c-a25f-20f80c28a96e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679417745 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.1679417745
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.723851188
Short name T378
Test name
Test status
Simulation time 338394400 ps
CPU time 0.75 seconds
Started Apr 18 01:41:18 PM PDT 24
Finished Apr 18 01:41:19 PM PDT 24
Peak memory 183884 kb
Host smart-89b3f246-0645-4395-bdaa-3f284de13743
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723851188 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_ti
mer_mem_partial_access.723851188
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.948244520
Short name T410
Test name
Test status
Simulation time 457007293 ps
CPU time 1.05 seconds
Started Apr 18 01:41:21 PM PDT 24
Finished Apr 18 01:41:23 PM PDT 24
Peak memory 183856 kb
Host smart-5def29b7-0658-4636-842a-fcf1fcba52bf
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948244520 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_wa
lk.948244520
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.4214449219
Short name T350
Test name
Test status
Simulation time 2530423173 ps
CPU time 3.46 seconds
Started Apr 18 01:41:21 PM PDT 24
Finished Apr 18 01:41:25 PM PDT 24
Peak memory 194760 kb
Host smart-33e7e295-1eca-47b7-8637-eec70f274aca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214449219 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon
_timer_same_csr_outstanding.4214449219
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.3769377452
Short name T330
Test name
Test status
Simulation time 419593847 ps
CPU time 2.54 seconds
Started Apr 18 01:41:21 PM PDT 24
Finished Apr 18 01:41:24 PM PDT 24
Peak memory 198804 kb
Host smart-27a33b30-53c9-4e1b-93a5-6af3c571867d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769377452 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.3769377452
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.28650722
Short name T354
Test name
Test status
Simulation time 4286910134 ps
CPU time 8.02 seconds
Started Apr 18 01:41:21 PM PDT 24
Finished Apr 18 01:41:29 PM PDT 24
Peak memory 198044 kb
Host smart-8697ddb1-d532-448c-ac9b-6e617b1c17a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28650722 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_i
ntg_err.28650722
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.3013382338
Short name T371
Test name
Test status
Simulation time 599630398 ps
CPU time 0.59 seconds
Started Apr 18 01:41:50 PM PDT 24
Finished Apr 18 01:41:51 PM PDT 24
Peak memory 183932 kb
Host smart-174e24a6-3fd4-472b-aa20-d0165ac9d0b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013382338 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.3013382338
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.3406615916
Short name T285
Test name
Test status
Simulation time 534230271 ps
CPU time 0.72 seconds
Started Apr 18 01:41:54 PM PDT 24
Finished Apr 18 01:41:55 PM PDT 24
Peak memory 183948 kb
Host smart-6b0d28a2-2247-407b-a014-4b349a05a967
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406615916 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.3406615916
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.4083160870
Short name T356
Test name
Test status
Simulation time 449076767 ps
CPU time 1.25 seconds
Started Apr 18 01:41:52 PM PDT 24
Finished Apr 18 01:41:53 PM PDT 24
Peak memory 183960 kb
Host smart-46ebe335-5d8b-4275-8f4d-a318821f8935
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083160870 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.4083160870
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.2313122646
Short name T333
Test name
Test status
Simulation time 434817792 ps
CPU time 0.75 seconds
Started Apr 18 01:41:50 PM PDT 24
Finished Apr 18 01:41:51 PM PDT 24
Peak memory 183936 kb
Host smart-8798ff30-7409-459b-8b3c-159b58e940e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313122646 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.2313122646
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.2980887168
Short name T406
Test name
Test status
Simulation time 303895448 ps
CPU time 1.01 seconds
Started Apr 18 01:41:54 PM PDT 24
Finished Apr 18 01:41:56 PM PDT 24
Peak memory 183956 kb
Host smart-ce2c7f3d-06da-4fae-8c1a-8a078041433d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980887168 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.2980887168
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.1769819457
Short name T325
Test name
Test status
Simulation time 314582294 ps
CPU time 1.01 seconds
Started Apr 18 01:41:52 PM PDT 24
Finished Apr 18 01:41:53 PM PDT 24
Peak memory 183944 kb
Host smart-b4b5dfc2-066e-4b54-be5c-3264985a52e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769819457 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.1769819457
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.3236241841
Short name T390
Test name
Test status
Simulation time 395651759 ps
CPU time 1 seconds
Started Apr 18 01:41:54 PM PDT 24
Finished Apr 18 01:41:55 PM PDT 24
Peak memory 183900 kb
Host smart-d04a5f61-316e-4a9d-b62c-e87b6fa48bf2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236241841 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.3236241841
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.631546636
Short name T337
Test name
Test status
Simulation time 336391904 ps
CPU time 1.08 seconds
Started Apr 18 01:41:55 PM PDT 24
Finished Apr 18 01:41:56 PM PDT 24
Peak memory 183972 kb
Host smart-0bfd4f45-c1f3-4dd0-aa10-d570c8c0d9e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631546636 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.631546636
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.1069893997
Short name T281
Test name
Test status
Simulation time 356267609 ps
CPU time 0.84 seconds
Started Apr 18 01:41:50 PM PDT 24
Finished Apr 18 01:41:51 PM PDT 24
Peak memory 183936 kb
Host smart-69e22024-359b-4409-9b9a-8e013d878d04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069893997 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.1069893997
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.2553460593
Short name T318
Test name
Test status
Simulation time 285341401 ps
CPU time 0.63 seconds
Started Apr 18 01:41:50 PM PDT 24
Finished Apr 18 01:41:51 PM PDT 24
Peak memory 183956 kb
Host smart-08d36878-6d73-440e-96e5-f423da396eb6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553460593 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.2553460593
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.1991804836
Short name T69
Test name
Test status
Simulation time 546653677 ps
CPU time 1.01 seconds
Started Apr 18 01:41:19 PM PDT 24
Finished Apr 18 01:41:21 PM PDT 24
Peak memory 184028 kb
Host smart-a6ac39fe-fde5-4027-b763-035bdb598883
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991804836 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_a
liasing.1991804836
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.230698044
Short name T64
Test name
Test status
Simulation time 9813325967 ps
CPU time 24.78 seconds
Started Apr 18 01:41:24 PM PDT 24
Finished Apr 18 01:41:50 PM PDT 24
Peak memory 192380 kb
Host smart-ba6bc76d-182f-42dd-ae98-da557a38204f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230698044 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_bi
t_bash.230698044
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.3200130370
Short name T66
Test name
Test status
Simulation time 1246497883 ps
CPU time 0.86 seconds
Started Apr 18 01:41:52 PM PDT 24
Finished Apr 18 01:41:53 PM PDT 24
Peak memory 193252 kb
Host smart-5dfd6d06-fb1f-4cf7-9865-847dbfff6013
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200130370 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_h
w_reset.3200130370
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.46764790
Short name T37
Test name
Test status
Simulation time 417105627 ps
CPU time 1.3 seconds
Started Apr 18 01:41:25 PM PDT 24
Finished Apr 18 01:41:27 PM PDT 24
Peak memory 195852 kb
Host smart-91ebe37f-3f10-48d0-b659-7a9f90cec36b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46764790 -assert nopostproc +UVM_TESTNAME=a
on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.46764790
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.2783046590
Short name T341
Test name
Test status
Simulation time 491584965 ps
CPU time 1.27 seconds
Started Apr 18 01:41:25 PM PDT 24
Finished Apr 18 01:41:26 PM PDT 24
Peak memory 193104 kb
Host smart-7359ad94-2f24-486d-a9b1-f317a8fa0b52
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783046590 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.2783046590
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.1917403000
Short name T339
Test name
Test status
Simulation time 303804121 ps
CPU time 0.69 seconds
Started Apr 18 01:41:21 PM PDT 24
Finished Apr 18 01:41:22 PM PDT 24
Peak memory 183944 kb
Host smart-d73a8663-ae20-4778-8b7d-5b7dd8aa827c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917403000 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.1917403000
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.1733329658
Short name T286
Test name
Test status
Simulation time 295928427 ps
CPU time 0.96 seconds
Started Apr 18 01:41:20 PM PDT 24
Finished Apr 18 01:41:21 PM PDT 24
Peak memory 183892 kb
Host smart-11d1bdef-afc7-46ad-ad22-26a325787670
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733329658 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_t
imer_mem_partial_access.1733329658
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.3715769733
Short name T283
Test name
Test status
Simulation time 426394634 ps
CPU time 0.64 seconds
Started Apr 18 01:41:19 PM PDT 24
Finished Apr 18 01:41:20 PM PDT 24
Peak memory 183828 kb
Host smart-97a8caa5-5e11-4f4f-8106-e5676ff8a448
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715769733 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_w
alk.3715769733
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.4247263769
Short name T75
Test name
Test status
Simulation time 2468434050 ps
CPU time 3.75 seconds
Started Apr 18 01:41:26 PM PDT 24
Finished Apr 18 01:41:31 PM PDT 24
Peak memory 195208 kb
Host smart-b1ac0941-31ea-4710-ad12-a244bc5badfe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247263769 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon
_timer_same_csr_outstanding.4247263769
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.2807572245
Short name T291
Test name
Test status
Simulation time 475240156 ps
CPU time 2.73 seconds
Started Apr 18 01:41:21 PM PDT 24
Finished Apr 18 01:41:25 PM PDT 24
Peak memory 198868 kb
Host smart-2a1f9d82-20ff-44c7-9d27-0b9c14abb59c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807572245 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.2807572245
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.3603887066
Short name T100
Test name
Test status
Simulation time 8383697489 ps
CPU time 15.23 seconds
Started Apr 18 01:41:24 PM PDT 24
Finished Apr 18 01:41:40 PM PDT 24
Peak memory 198168 kb
Host smart-4f7d6a9d-f842-4d31-ab0d-9445400e050a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603887066 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl
_intg_err.3603887066
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.461532409
Short name T408
Test name
Test status
Simulation time 340552161 ps
CPU time 1.03 seconds
Started Apr 18 01:41:49 PM PDT 24
Finished Apr 18 01:41:50 PM PDT 24
Peak memory 183940 kb
Host smart-669ad13e-6741-4f91-9965-41e04f5d55ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461532409 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.461532409
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.1067256487
Short name T377
Test name
Test status
Simulation time 379530949 ps
CPU time 0.81 seconds
Started Apr 18 01:41:52 PM PDT 24
Finished Apr 18 01:41:53 PM PDT 24
Peak memory 183940 kb
Host smart-72f65733-b56a-4ec3-b6dd-c8f03d24d99f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067256487 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.1067256487
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.1842546193
Short name T357
Test name
Test status
Simulation time 514967871 ps
CPU time 0.7 seconds
Started Apr 18 01:41:49 PM PDT 24
Finished Apr 18 01:41:50 PM PDT 24
Peak memory 183960 kb
Host smart-b29e981b-c7a3-4d77-871f-27dac7fe347b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842546193 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.1842546193
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.946188028
Short name T395
Test name
Test status
Simulation time 284019704 ps
CPU time 0.94 seconds
Started Apr 18 01:41:51 PM PDT 24
Finished Apr 18 01:41:52 PM PDT 24
Peak memory 183944 kb
Host smart-57c732b3-0cbe-458d-a2ba-fcfe7181f42e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946188028 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.946188028
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.42830373
Short name T388
Test name
Test status
Simulation time 504496198 ps
CPU time 1.34 seconds
Started Apr 18 01:41:54 PM PDT 24
Finished Apr 18 01:41:56 PM PDT 24
Peak memory 183952 kb
Host smart-4c3e36f5-16d0-4fbd-ab65-f6832f955cd5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42830373 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.42830373
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.1357508087
Short name T301
Test name
Test status
Simulation time 520969104 ps
CPU time 0.79 seconds
Started Apr 18 01:41:55 PM PDT 24
Finished Apr 18 01:41:56 PM PDT 24
Peak memory 183964 kb
Host smart-ad7835a5-2b63-46c1-84d6-54562db7586b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357508087 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.1357508087
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.3635863787
Short name T379
Test name
Test status
Simulation time 475935737 ps
CPU time 0.94 seconds
Started Apr 18 01:41:50 PM PDT 24
Finished Apr 18 01:41:51 PM PDT 24
Peak memory 183892 kb
Host smart-6258ff2a-abaf-4918-a99c-fb89d52f2022
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635863787 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.3635863787
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.3935415041
Short name T383
Test name
Test status
Simulation time 434870850 ps
CPU time 0.81 seconds
Started Apr 18 01:41:50 PM PDT 24
Finished Apr 18 01:41:51 PM PDT 24
Peak memory 183972 kb
Host smart-504c3ce2-8ffd-48f6-ac0b-8315f3653c50
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935415041 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.3935415041
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.616869903
Short name T282
Test name
Test status
Simulation time 339648291 ps
CPU time 1.01 seconds
Started Apr 18 01:41:49 PM PDT 24
Finished Apr 18 01:41:51 PM PDT 24
Peak memory 183968 kb
Host smart-4c50fbcf-a4d1-4c7d-ac03-41cb76d9d38e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616869903 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.616869903
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.1477939156
Short name T296
Test name
Test status
Simulation time 377994126 ps
CPU time 0.69 seconds
Started Apr 18 01:41:50 PM PDT 24
Finished Apr 18 01:41:51 PM PDT 24
Peak memory 183912 kb
Host smart-0cffe33f-8638-44de-b1c6-a14d9b6185c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477939156 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.1477939156
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.248466351
Short name T320
Test name
Test status
Simulation time 398920094 ps
CPU time 1.21 seconds
Started Apr 18 01:41:26 PM PDT 24
Finished Apr 18 01:41:27 PM PDT 24
Peak memory 196720 kb
Host smart-b43ca4c2-8800-4e79-87eb-08c3bbf4a4e8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248466351 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.248466351
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.1507519858
Short name T73
Test name
Test status
Simulation time 344666771 ps
CPU time 0.69 seconds
Started Apr 18 01:41:27 PM PDT 24
Finished Apr 18 01:41:28 PM PDT 24
Peak memory 193376 kb
Host smart-6ae09633-1978-4040-a0ca-249ed97ea81f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507519858 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.1507519858
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.3430200513
Short name T287
Test name
Test status
Simulation time 470519725 ps
CPU time 1.17 seconds
Started Apr 18 01:41:26 PM PDT 24
Finished Apr 18 01:41:27 PM PDT 24
Peak memory 183936 kb
Host smart-d2434e47-03d0-462c-b3d3-0368de9219a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430200513 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.3430200513
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.3999683485
Short name T322
Test name
Test status
Simulation time 2327558299 ps
CPU time 3.94 seconds
Started Apr 18 01:41:28 PM PDT 24
Finished Apr 18 01:41:32 PM PDT 24
Peak memory 194704 kb
Host smart-2400da6d-dd5b-4588-a073-3a49aaef707a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999683485 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon
_timer_same_csr_outstanding.3999683485
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.384288397
Short name T384
Test name
Test status
Simulation time 837114922 ps
CPU time 2.23 seconds
Started Apr 18 01:41:26 PM PDT 24
Finished Apr 18 01:41:29 PM PDT 24
Peak memory 198772 kb
Host smart-24350182-6558-4320-932f-0c9972a0db3d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384288397 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.384288397
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.1206592640
Short name T331
Test name
Test status
Simulation time 4574122405 ps
CPU time 2.64 seconds
Started Apr 18 01:41:25 PM PDT 24
Finished Apr 18 01:41:28 PM PDT 24
Peak memory 197708 kb
Host smart-ec77ccd8-eb55-4a06-915f-efc17b206cf6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206592640 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl
_intg_err.1206592640
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.3231754420
Short name T36
Test name
Test status
Simulation time 436550588 ps
CPU time 0.74 seconds
Started Apr 18 01:41:26 PM PDT 24
Finished Apr 18 01:41:27 PM PDT 24
Peak memory 196192 kb
Host smart-6524bd49-ce3c-4eec-b53e-a5f5e0118da2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231754420 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.3231754420
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.2583676976
Short name T309
Test name
Test status
Simulation time 367501214 ps
CPU time 0.66 seconds
Started Apr 18 01:41:25 PM PDT 24
Finished Apr 18 01:41:27 PM PDT 24
Peak memory 184164 kb
Host smart-a483bf6b-eb8e-4ba0-8683-00afdc35ccbd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583676976 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.2583676976
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.3222683711
Short name T393
Test name
Test status
Simulation time 512975801 ps
CPU time 0.75 seconds
Started Apr 18 01:41:24 PM PDT 24
Finished Apr 18 01:41:26 PM PDT 24
Peak memory 183940 kb
Host smart-a0240ae4-28a9-42f7-91f2-499163d644f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222683711 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.3222683711
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.2802828294
Short name T402
Test name
Test status
Simulation time 2975237031 ps
CPU time 1.64 seconds
Started Apr 18 01:41:24 PM PDT 24
Finished Apr 18 01:41:26 PM PDT 24
Peak memory 195180 kb
Host smart-935abee4-a226-4fc3-84f9-23b3f90e160a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802828294 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon
_timer_same_csr_outstanding.2802828294
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.2608454006
Short name T327
Test name
Test status
Simulation time 554617133 ps
CPU time 1.33 seconds
Started Apr 18 01:41:25 PM PDT 24
Finished Apr 18 01:41:27 PM PDT 24
Peak memory 198836 kb
Host smart-66013c52-7a48-4874-a673-cd0b00e643c1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608454006 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.2608454006
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.1587597902
Short name T43
Test name
Test status
Simulation time 8674680456 ps
CPU time 8.5 seconds
Started Apr 18 01:41:25 PM PDT 24
Finished Apr 18 01:41:34 PM PDT 24
Peak memory 198140 kb
Host smart-8d65b298-b5ee-49f9-a2ee-2f987b83f4ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587597902 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl
_intg_err.1587597902
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.1753127117
Short name T365
Test name
Test status
Simulation time 600997707 ps
CPU time 1.51 seconds
Started Apr 18 01:41:24 PM PDT 24
Finished Apr 18 01:41:27 PM PDT 24
Peak memory 196440 kb
Host smart-62e73333-50de-4b7e-9d2a-fc322e3099b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753127117 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.1753127117
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.3818379060
Short name T79
Test name
Test status
Simulation time 325730766 ps
CPU time 1.11 seconds
Started Apr 18 01:41:31 PM PDT 24
Finished Apr 18 01:41:32 PM PDT 24
Peak memory 193120 kb
Host smart-3360d919-fe09-465c-9997-f0df5650dc4a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818379060 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.3818379060
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.3078430883
Short name T311
Test name
Test status
Simulation time 319024167 ps
CPU time 1 seconds
Started Apr 18 01:41:24 PM PDT 24
Finished Apr 18 01:41:25 PM PDT 24
Peak memory 183916 kb
Host smart-b1d06c3c-1b11-4133-b0f7-798665ec9b95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078430883 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.3078430883
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.3585843129
Short name T76
Test name
Test status
Simulation time 2642614694 ps
CPU time 5.47 seconds
Started Apr 18 01:41:26 PM PDT 24
Finished Apr 18 01:41:32 PM PDT 24
Peak memory 184108 kb
Host smart-360ed379-b396-47e9-ba31-036f69dc29f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585843129 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon
_timer_same_csr_outstanding.3585843129
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.3382406055
Short name T364
Test name
Test status
Simulation time 518809250 ps
CPU time 1.42 seconds
Started Apr 18 01:41:23 PM PDT 24
Finished Apr 18 01:41:25 PM PDT 24
Peak memory 196736 kb
Host smart-f1988316-21a6-4d4c-87c8-02ea07ec2bd0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382406055 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.3382406055
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.1066738164
Short name T386
Test name
Test status
Simulation time 4546501038 ps
CPU time 1.91 seconds
Started Apr 18 01:41:25 PM PDT 24
Finished Apr 18 01:41:27 PM PDT 24
Peak memory 197572 kb
Host smart-8f997dec-6c8e-4d12-9eba-2b940dc181da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066738164 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl
_intg_err.1066738164
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.1326835039
Short name T399
Test name
Test status
Simulation time 474081194 ps
CPU time 1.08 seconds
Started Apr 18 01:41:34 PM PDT 24
Finished Apr 18 01:41:36 PM PDT 24
Peak memory 197144 kb
Host smart-b73ca66f-5fcc-4ed7-986f-9b28de88a5cb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326835039 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.1326835039
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.687137110
Short name T321
Test name
Test status
Simulation time 478771355 ps
CPU time 1.39 seconds
Started Apr 18 01:41:32 PM PDT 24
Finished Apr 18 01:41:34 PM PDT 24
Peak memory 193216 kb
Host smart-b17cf414-6b0c-4249-b076-6e3d38f82006
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687137110 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.687137110
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.2012999879
Short name T347
Test name
Test status
Simulation time 331835891 ps
CPU time 0.63 seconds
Started Apr 18 01:41:35 PM PDT 24
Finished Apr 18 01:41:37 PM PDT 24
Peak memory 183952 kb
Host smart-f84772c2-e985-4169-b95c-bdbf23570567
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012999879 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.2012999879
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.132823768
Short name T359
Test name
Test status
Simulation time 1336299628 ps
CPU time 1.11 seconds
Started Apr 18 01:41:34 PM PDT 24
Finished Apr 18 01:41:36 PM PDT 24
Peak memory 193584 kb
Host smart-ab0e144a-a4bd-4171-b1ba-f75ed419083b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132823768 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_
timer_same_csr_outstanding.132823768
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.1999398738
Short name T278
Test name
Test status
Simulation time 338063098 ps
CPU time 2.06 seconds
Started Apr 18 01:41:32 PM PDT 24
Finished Apr 18 01:41:34 PM PDT 24
Peak memory 198832 kb
Host smart-41b0a65f-a4e1-424d-88c3-391921e6c0d0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999398738 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.1999398738
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.2231938378
Short name T355
Test name
Test status
Simulation time 4692274980 ps
CPU time 3.02 seconds
Started Apr 18 01:41:33 PM PDT 24
Finished Apr 18 01:41:36 PM PDT 24
Peak memory 196816 kb
Host smart-6c6c2130-cb4f-47bb-bab5-94f020a8b942
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231938378 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl
_intg_err.2231938378
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.1329395027
Short name T323
Test name
Test status
Simulation time 417041720 ps
CPU time 1 seconds
Started Apr 18 01:41:33 PM PDT 24
Finished Apr 18 01:41:35 PM PDT 24
Peak memory 196536 kb
Host smart-7229b2df-526e-49ce-b2cb-14731988ba79
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329395027 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.1329395027
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.3250693449
Short name T374
Test name
Test status
Simulation time 458883703 ps
CPU time 0.74 seconds
Started Apr 18 01:41:35 PM PDT 24
Finished Apr 18 01:41:36 PM PDT 24
Peak memory 183952 kb
Host smart-b530cec9-a31c-4cca-93e9-a468d0cefa82
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250693449 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.3250693449
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.3958066102
Short name T400
Test name
Test status
Simulation time 284985501 ps
CPU time 0.71 seconds
Started Apr 18 01:41:32 PM PDT 24
Finished Apr 18 01:41:33 PM PDT 24
Peak memory 183964 kb
Host smart-d90c6495-9e0a-4553-84da-38adeac6e101
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958066102 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.3958066102
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.1812184690
Short name T351
Test name
Test status
Simulation time 1221131937 ps
CPU time 4.16 seconds
Started Apr 18 01:41:33 PM PDT 24
Finished Apr 18 01:41:38 PM PDT 24
Peak memory 193748 kb
Host smart-5fc3d994-98f5-4bfb-98ef-c7528272814b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812184690 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon
_timer_same_csr_outstanding.1812184690
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.1507863595
Short name T328
Test name
Test status
Simulation time 1327149196 ps
CPU time 1.52 seconds
Started Apr 18 01:41:35 PM PDT 24
Finished Apr 18 01:41:37 PM PDT 24
Peak memory 198804 kb
Host smart-5d77f587-f371-4723-bd2b-118a5c59b3b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507863595 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.1507863595
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.2803309181
Short name T332
Test name
Test status
Simulation time 4311783243 ps
CPU time 2.48 seconds
Started Apr 18 01:41:32 PM PDT 24
Finished Apr 18 01:41:35 PM PDT 24
Peak memory 198000 kb
Host smart-5af21960-4a8f-4228-b5a7-66e16c3f69ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803309181 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl
_intg_err.2803309181
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_jump.1307098569
Short name T162
Test name
Test status
Simulation time 560151412 ps
CPU time 0.98 seconds
Started Apr 18 01:40:12 PM PDT 24
Finished Apr 18 01:40:13 PM PDT 24
Peak memory 183308 kb
Host smart-eb11b6c3-fb1c-4af1-b3bf-634505342669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307098569 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.1307098569
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.2641545489
Short name T135
Test name
Test status
Simulation time 17891766827 ps
CPU time 15.51 seconds
Started Apr 18 01:40:12 PM PDT 24
Finished Apr 18 01:40:28 PM PDT 24
Peak memory 183288 kb
Host smart-995d6ba1-3215-4db2-9a13-90359cc27c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641545489 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.2641545489
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.3118274696
Short name T257
Test name
Test status
Simulation time 537416785 ps
CPU time 0.76 seconds
Started Apr 18 01:40:13 PM PDT 24
Finished Apr 18 01:40:14 PM PDT 24
Peak memory 183300 kb
Host smart-33201318-fb62-49b0-8c44-cbf308bf34a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118274696 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.3118274696
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.3432455069
Short name T256
Test name
Test status
Simulation time 257626102685 ps
CPU time 91.12 seconds
Started Apr 18 01:40:13 PM PDT 24
Finished Apr 18 01:41:45 PM PDT 24
Peak memory 183472 kb
Host smart-1c51e9cb-6325-42be-9f1b-290541551acc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432455069 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_a
ll.3432455069
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_jump.1455799326
Short name T153
Test name
Test status
Simulation time 371098259 ps
CPU time 1.01 seconds
Started Apr 18 01:40:13 PM PDT 24
Finished Apr 18 01:40:15 PM PDT 24
Peak memory 183316 kb
Host smart-b0e2b210-7d45-4ba6-aaf1-7ac1614eb2d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455799326 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.1455799326
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.225510259
Short name T158
Test name
Test status
Simulation time 2287193246 ps
CPU time 1.47 seconds
Started Apr 18 01:40:12 PM PDT 24
Finished Apr 18 01:40:14 PM PDT 24
Peak memory 183212 kb
Host smart-acbf7303-f894-44d1-9e05-d738af1658fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225510259 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.225510259
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.2208751577
Short name T18
Test name
Test status
Simulation time 4337040826 ps
CPU time 1.26 seconds
Started Apr 18 01:40:15 PM PDT 24
Finished Apr 18 01:40:17 PM PDT 24
Peak memory 215068 kb
Host smart-00da7e4a-eaef-48d6-a33c-49fe2754ce1b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208751577 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.2208751577
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.2039906360
Short name T231
Test name
Test status
Simulation time 438511106 ps
CPU time 0.57 seconds
Started Apr 18 01:40:10 PM PDT 24
Finished Apr 18 01:40:12 PM PDT 24
Peak memory 183300 kb
Host smart-230b99ea-3de7-4814-b72c-3fb3dc4e961c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039906360 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.2039906360
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.2742759235
Short name T29
Test name
Test status
Simulation time 328509022898 ps
CPU time 236.84 seconds
Started Apr 18 01:40:15 PM PDT 24
Finished Apr 18 01:44:13 PM PDT 24
Peak memory 193016 kb
Host smart-b9666237-4f1d-45e3-bdee-d54876b7a4b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742759235 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_a
ll.2742759235
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.3271876368
Short name T223
Test name
Test status
Simulation time 84291868961 ps
CPU time 258.14 seconds
Started Apr 18 01:40:12 PM PDT 24
Finished Apr 18 01:44:31 PM PDT 24
Peak memory 198268 kb
Host smart-8a94d080-52b5-4020-9845-b37d126db769
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271876368 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.3271876368
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.aon_timer_jump.3558845447
Short name T122
Test name
Test status
Simulation time 383869403 ps
CPU time 1.2 seconds
Started Apr 18 01:40:18 PM PDT 24
Finished Apr 18 01:40:20 PM PDT 24
Peak memory 183312 kb
Host smart-b667f3c5-a235-4970-83c2-7f87b34d7bd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558845447 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.3558845447
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.4188474613
Short name T218
Test name
Test status
Simulation time 10866999711 ps
CPU time 2.39 seconds
Started Apr 18 01:40:17 PM PDT 24
Finished Apr 18 01:40:20 PM PDT 24
Peak memory 183324 kb
Host smart-4b4a5681-c1b1-4fe5-9336-713dc9b536da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188474613 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.4188474613
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.1399856529
Short name T125
Test name
Test status
Simulation time 573343220 ps
CPU time 0.6 seconds
Started Apr 18 01:40:22 PM PDT 24
Finished Apr 18 01:40:23 PM PDT 24
Peak memory 183256 kb
Host smart-97428e5b-9f26-4a39-9104-41092c9cbf99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399856529 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.1399856529
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.3147372596
Short name T111
Test name
Test status
Simulation time 41590756701 ps
CPU time 65.56 seconds
Started Apr 18 01:40:24 PM PDT 24
Finished Apr 18 01:41:30 PM PDT 24
Peak memory 183368 kb
Host smart-293f469b-370d-46cb-9615-c5960b191f73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147372596 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_
all.3147372596
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_jump.3821923536
Short name T139
Test name
Test status
Simulation time 456334612 ps
CPU time 0.7 seconds
Started Apr 18 01:40:23 PM PDT 24
Finished Apr 18 01:40:24 PM PDT 24
Peak memory 183284 kb
Host smart-a418ef28-a55a-471e-bffd-8b4a44f0cd7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821923536 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.3821923536
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.1801352101
Short name T4
Test name
Test status
Simulation time 30711540282 ps
CPU time 40.61 seconds
Started Apr 18 01:40:23 PM PDT 24
Finished Apr 18 01:41:04 PM PDT 24
Peak memory 183356 kb
Host smart-668902ec-c38e-41fa-a0f8-ea4814bd3213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801352101 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.1801352101
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.200997321
Short name T123
Test name
Test status
Simulation time 379668548 ps
CPU time 1.23 seconds
Started Apr 18 01:40:23 PM PDT 24
Finished Apr 18 01:40:25 PM PDT 24
Peak memory 183252 kb
Host smart-276b875a-2589-4ad4-8ac5-838efafc79fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200997321 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.200997321
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.1972526216
Short name T95
Test name
Test status
Simulation time 176387172309 ps
CPU time 74.08 seconds
Started Apr 18 01:40:25 PM PDT 24
Finished Apr 18 01:41:40 PM PDT 24
Peak memory 195100 kb
Host smart-23074725-cf09-4f30-9d14-8fb0c82fe09f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972526216 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_
all.1972526216
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.3671899715
Short name T183
Test name
Test status
Simulation time 56451042742 ps
CPU time 384.39 seconds
Started Apr 18 01:40:25 PM PDT 24
Finished Apr 18 01:46:50 PM PDT 24
Peak memory 198100 kb
Host smart-71a2eae1-a17b-49be-9801-e30df40a5409
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671899715 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand_reset.3671899715
Directory /workspace/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.aon_timer_jump.1702863240
Short name T199
Test name
Test status
Simulation time 543131186 ps
CPU time 0.79 seconds
Started Apr 18 01:40:23 PM PDT 24
Finished Apr 18 01:40:24 PM PDT 24
Peak memory 183300 kb
Host smart-04ff5487-63bc-4658-a232-94d6c308597c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702863240 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.1702863240
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.576715355
Short name T58
Test name
Test status
Simulation time 31467981356 ps
CPU time 9.21 seconds
Started Apr 18 01:40:22 PM PDT 24
Finished Apr 18 01:40:32 PM PDT 24
Peak memory 183348 kb
Host smart-d53c0a8a-3105-48cd-80d7-58bffaa24fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576715355 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.576715355
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.291193009
Short name T189
Test name
Test status
Simulation time 374561187 ps
CPU time 0.82 seconds
Started Apr 18 01:40:23 PM PDT 24
Finished Apr 18 01:40:25 PM PDT 24
Peak memory 183288 kb
Host smart-d6042ec1-a85f-4532-a975-7cd106d188aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291193009 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.291193009
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.3161926713
Short name T182
Test name
Test status
Simulation time 240981361434 ps
CPU time 100.5 seconds
Started Apr 18 01:40:22 PM PDT 24
Finished Apr 18 01:42:03 PM PDT 24
Peak memory 183520 kb
Host smart-bfa4f57e-68e9-4b07-92b6-23194c5ca3bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161926713 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_
all.3161926713
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.453672069
Short name T60
Test name
Test status
Simulation time 65483126471 ps
CPU time 532.19 seconds
Started Apr 18 01:40:23 PM PDT 24
Finished Apr 18 01:49:16 PM PDT 24
Peak memory 198260 kb
Host smart-3ad24a75-2d78-44dc-883a-5f96224daa54
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453672069 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.453672069
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_jump.3388517292
Short name T206
Test name
Test status
Simulation time 572307552 ps
CPU time 0.63 seconds
Started Apr 18 01:40:24 PM PDT 24
Finished Apr 18 01:40:25 PM PDT 24
Peak memory 183300 kb
Host smart-52cf078a-e48c-4a32-9b21-0689044440ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388517292 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.3388517292
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.3281814990
Short name T1
Test name
Test status
Simulation time 18243345047 ps
CPU time 14.75 seconds
Started Apr 18 01:40:23 PM PDT 24
Finished Apr 18 01:40:38 PM PDT 24
Peak memory 183200 kb
Host smart-d6e4bcfa-4409-43b6-aafd-7d9967c915ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281814990 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.3281814990
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.1838602955
Short name T110
Test name
Test status
Simulation time 532047408 ps
CPU time 0.72 seconds
Started Apr 18 01:40:23 PM PDT 24
Finished Apr 18 01:40:24 PM PDT 24
Peak memory 183304 kb
Host smart-8043051c-ab30-4236-ba45-5b4f407873bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838602955 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.1838602955
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.3002615460
Short name T220
Test name
Test status
Simulation time 2004896491 ps
CPU time 13.04 seconds
Started Apr 18 01:40:29 PM PDT 24
Finished Apr 18 01:40:43 PM PDT 24
Peak memory 198272 kb
Host smart-492dd483-9b44-4d6a-a096-c556619d950e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002615460 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.3002615460
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.aon_timer_jump.396694806
Short name T179
Test name
Test status
Simulation time 613470403 ps
CPU time 0.75 seconds
Started Apr 18 01:40:23 PM PDT 24
Finished Apr 18 01:40:25 PM PDT 24
Peak memory 183296 kb
Host smart-9fad8e03-2ef3-4f22-8952-ce93cc0d2b66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396694806 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.396694806
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.606120785
Short name T154
Test name
Test status
Simulation time 13468701491 ps
CPU time 4.82 seconds
Started Apr 18 01:40:26 PM PDT 24
Finished Apr 18 01:40:31 PM PDT 24
Peak memory 183284 kb
Host smart-c8d091db-360a-4a5e-9b9e-246dc18574e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606120785 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.606120785
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.2382584688
Short name T147
Test name
Test status
Simulation time 427863750 ps
CPU time 0.78 seconds
Started Apr 18 01:40:23 PM PDT 24
Finished Apr 18 01:40:24 PM PDT 24
Peak memory 183304 kb
Host smart-926f836d-57fd-4ab3-b08c-d9895d492d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382584688 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.2382584688
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.4181069636
Short name T144
Test name
Test status
Simulation time 245417505487 ps
CPU time 187.39 seconds
Started Apr 18 01:40:25 PM PDT 24
Finished Apr 18 01:43:33 PM PDT 24
Peak memory 192936 kb
Host smart-5eded2f0-78c3-47ba-a086-2a21078bba73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181069636 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_
all.4181069636
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.2304956243
Short name T195
Test name
Test status
Simulation time 9950230281 ps
CPU time 112.15 seconds
Started Apr 18 01:40:23 PM PDT 24
Finished Apr 18 01:42:16 PM PDT 24
Peak memory 198264 kb
Host smart-d22f227d-4b8d-408e-a6c1-0aa20e4fb960
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304956243 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.2304956243
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.aon_timer_jump.1570667563
Short name T211
Test name
Test status
Simulation time 515941931 ps
CPU time 0.61 seconds
Started Apr 18 01:40:30 PM PDT 24
Finished Apr 18 01:40:30 PM PDT 24
Peak memory 183316 kb
Host smart-9ef58692-7420-45a1-9a8a-d523abe5b4d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570667563 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.1570667563
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.3358497016
Short name T142
Test name
Test status
Simulation time 53835954502 ps
CPU time 80.45 seconds
Started Apr 18 01:40:25 PM PDT 24
Finished Apr 18 01:41:46 PM PDT 24
Peak memory 183288 kb
Host smart-39af7189-3f6b-4d55-89e0-4dfb19fbbf1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358497016 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.3358497016
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.842318500
Short name T243
Test name
Test status
Simulation time 423529002 ps
CPU time 1.12 seconds
Started Apr 18 01:40:37 PM PDT 24
Finished Apr 18 01:40:39 PM PDT 24
Peak memory 183348 kb
Host smart-f91c75e6-97ec-432c-bcde-c0b06e3ccf34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842318500 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.842318500
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.2967655120
Short name T90
Test name
Test status
Simulation time 92180427383 ps
CPU time 430.7 seconds
Started Apr 18 01:40:28 PM PDT 24
Finished Apr 18 01:47:39 PM PDT 24
Peak memory 198348 kb
Host smart-e4a7d74f-a6e1-49f4-8e5f-e773ca4a1f73
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967655120 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.2967655120
Directory /workspace/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.aon_timer_jump.2535738119
Short name T262
Test name
Test status
Simulation time 537751477 ps
CPU time 0.67 seconds
Started Apr 18 01:40:26 PM PDT 24
Finished Apr 18 01:40:27 PM PDT 24
Peak memory 183300 kb
Host smart-f4a2b297-3ae9-4b0a-ab8c-3e8912a2bafd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535738119 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.2535738119
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.34548944
Short name T165
Test name
Test status
Simulation time 6058888287 ps
CPU time 9.66 seconds
Started Apr 18 01:40:29 PM PDT 24
Finished Apr 18 01:40:39 PM PDT 24
Peak memory 183300 kb
Host smart-835626d4-0062-41a4-96e1-a67fa0c3f73b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34548944 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.34548944
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.2840121186
Short name T187
Test name
Test status
Simulation time 447115539 ps
CPU time 1.22 seconds
Started Apr 18 01:40:29 PM PDT 24
Finished Apr 18 01:40:30 PM PDT 24
Peak memory 183308 kb
Host smart-c0c85e94-abad-4e55-b234-f8b3f3ffd4ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840121186 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.2840121186
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.1449175296
Short name T172
Test name
Test status
Simulation time 252857709193 ps
CPU time 175.93 seconds
Started Apr 18 01:40:28 PM PDT 24
Finished Apr 18 01:43:24 PM PDT 24
Peak memory 183372 kb
Host smart-32bc4c7a-e4eb-402c-96d3-1d38ddc94acd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449175296 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_
all.1449175296
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.3445570406
Short name T203
Test name
Test status
Simulation time 123186397588 ps
CPU time 347.37 seconds
Started Apr 18 01:40:30 PM PDT 24
Finished Apr 18 01:46:17 PM PDT 24
Peak memory 198332 kb
Host smart-83ebeb3d-c63b-47e0-9292-e5b74ab3d1e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445570406 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.3445570406
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.aon_timer_jump.1258660168
Short name T226
Test name
Test status
Simulation time 535822924 ps
CPU time 0.69 seconds
Started Apr 18 01:40:28 PM PDT 24
Finished Apr 18 01:40:29 PM PDT 24
Peak memory 183300 kb
Host smart-781fecea-c29f-4f71-8988-38d7cb0bd148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258660168 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.1258660168
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.4196014917
Short name T3
Test name
Test status
Simulation time 44668349397 ps
CPU time 65.18 seconds
Started Apr 18 01:40:29 PM PDT 24
Finished Apr 18 01:41:34 PM PDT 24
Peak memory 183340 kb
Host smart-81f87197-d35e-4f87-8415-6c9c5408e48f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196014917 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.4196014917
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.36789237
Short name T31
Test name
Test status
Simulation time 525386194 ps
CPU time 0.71 seconds
Started Apr 18 01:40:28 PM PDT 24
Finished Apr 18 01:40:29 PM PDT 24
Peak memory 183316 kb
Host smart-f2e4c555-455d-4cfe-ab10-acf1f12c3b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36789237 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.36789237
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.4247973684
Short name T138
Test name
Test status
Simulation time 446210625484 ps
CPU time 115.78 seconds
Started Apr 18 01:40:28 PM PDT 24
Finished Apr 18 01:42:24 PM PDT 24
Peak memory 195120 kb
Host smart-14d965f7-fdb1-4ef5-ae09-b633cae73cd7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247973684 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_
all.4247973684
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.3814238447
Short name T248
Test name
Test status
Simulation time 128889502423 ps
CPU time 439.47 seconds
Started Apr 18 01:40:31 PM PDT 24
Finished Apr 18 01:47:51 PM PDT 24
Peak memory 198180 kb
Host smart-1c8aa229-e2e0-47f9-aead-c03514445ed2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814238447 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.3814238447
Directory /workspace/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.aon_timer_jump.3162431567
Short name T148
Test name
Test status
Simulation time 510370405 ps
CPU time 0.66 seconds
Started Apr 18 01:40:27 PM PDT 24
Finished Apr 18 01:40:28 PM PDT 24
Peak memory 183268 kb
Host smart-9bd5cb68-bdaf-4d56-a04e-557abe112a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162431567 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.3162431567
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.2043120754
Short name T149
Test name
Test status
Simulation time 44596045365 ps
CPU time 62 seconds
Started Apr 18 01:40:29 PM PDT 24
Finished Apr 18 01:41:31 PM PDT 24
Peak memory 183364 kb
Host smart-0b6f3c46-41a1-4517-8704-07986a5db8b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043120754 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.2043120754
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.3054228588
Short name T229
Test name
Test status
Simulation time 422992716 ps
CPU time 1.22 seconds
Started Apr 18 01:40:31 PM PDT 24
Finished Apr 18 01:40:33 PM PDT 24
Peak memory 183196 kb
Host smart-9d08b918-8b83-4864-874a-99b32890e200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054228588 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.3054228588
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.3141495533
Short name T54
Test name
Test status
Simulation time 123270047841 ps
CPU time 47.75 seconds
Started Apr 18 01:40:34 PM PDT 24
Finished Apr 18 01:41:22 PM PDT 24
Peak memory 193904 kb
Host smart-f3838a4d-4ed0-4e22-b766-e1a599b27302
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141495533 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_
all.3141495533
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.2642301739
Short name T92
Test name
Test status
Simulation time 65331584596 ps
CPU time 229.97 seconds
Started Apr 18 01:40:33 PM PDT 24
Finished Apr 18 01:44:23 PM PDT 24
Peak memory 198328 kb
Host smart-4019f680-d408-470c-95bc-3df11a90b841
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642301739 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.2642301739
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.aon_timer_jump.1636367583
Short name T107
Test name
Test status
Simulation time 401526168 ps
CPU time 0.72 seconds
Started Apr 18 01:40:36 PM PDT 24
Finished Apr 18 01:40:37 PM PDT 24
Peak memory 183292 kb
Host smart-9ada3abd-f7ed-4f81-87bd-498ecf230a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636367583 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.1636367583
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.1885122184
Short name T240
Test name
Test status
Simulation time 27008880528 ps
CPU time 20.64 seconds
Started Apr 18 01:40:36 PM PDT 24
Finished Apr 18 01:40:57 PM PDT 24
Peak memory 183304 kb
Host smart-de411874-0f12-4619-b362-7a6333c2501e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885122184 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.1885122184
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.3669033316
Short name T270
Test name
Test status
Simulation time 519336907 ps
CPU time 0.75 seconds
Started Apr 18 01:40:37 PM PDT 24
Finished Apr 18 01:40:38 PM PDT 24
Peak memory 183304 kb
Host smart-9b3a0ca3-1f42-4ce9-ba6d-030eabeac426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669033316 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.3669033316
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.1352946336
Short name T210
Test name
Test status
Simulation time 410620057737 ps
CPU time 392.18 seconds
Started Apr 18 01:40:35 PM PDT 24
Finished Apr 18 01:47:08 PM PDT 24
Peak memory 183424 kb
Host smart-6faf0eb2-b762-4d2d-ad53-f8f04ab4fbb7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352946336 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_
all.1352946336
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.452734156
Short name T48
Test name
Test status
Simulation time 89301779648 ps
CPU time 515.38 seconds
Started Apr 18 01:40:36 PM PDT 24
Finished Apr 18 01:49:12 PM PDT 24
Peak memory 198564 kb
Host smart-040a93ba-d7b3-4d70-bd0f-3fc21014d902
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452734156 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.452734156
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_jump.209438888
Short name T155
Test name
Test status
Simulation time 429295817 ps
CPU time 0.7 seconds
Started Apr 18 01:40:22 PM PDT 24
Finished Apr 18 01:40:23 PM PDT 24
Peak memory 183256 kb
Host smart-04eacdc8-e344-48f0-a72b-0a66b5ccb2aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209438888 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.209438888
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.3965266674
Short name T175
Test name
Test status
Simulation time 39432803336 ps
CPU time 60.41 seconds
Started Apr 18 01:40:14 PM PDT 24
Finished Apr 18 01:41:14 PM PDT 24
Peak memory 183288 kb
Host smart-053d661c-8f70-4f70-aa6e-c2c482175f77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965266674 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.3965266674
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.2873307864
Short name T15
Test name
Test status
Simulation time 4540496898 ps
CPU time 7.26 seconds
Started Apr 18 01:40:24 PM PDT 24
Finished Apr 18 01:40:31 PM PDT 24
Peak memory 215508 kb
Host smart-16185a18-23c7-4df7-bb97-052b8c914d92
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873307864 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.2873307864
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.2372544836
Short name T228
Test name
Test status
Simulation time 561032628 ps
CPU time 1.32 seconds
Started Apr 18 01:40:12 PM PDT 24
Finished Apr 18 01:40:14 PM PDT 24
Peak memory 183248 kb
Host smart-49e519b1-2186-43c8-905c-d370e4ba3e87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372544836 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.2372544836
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.25088264
Short name T260
Test name
Test status
Simulation time 681427803104 ps
CPU time 74.75 seconds
Started Apr 18 01:40:22 PM PDT 24
Finished Apr 18 01:41:37 PM PDT 24
Peak memory 194836 kb
Host smart-06ebbc4b-94e5-46a2-838e-2ad2ae712a13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25088264 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all
.25088264
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_jump.729681734
Short name T247
Test name
Test status
Simulation time 383072552 ps
CPU time 1.15 seconds
Started Apr 18 01:40:35 PM PDT 24
Finished Apr 18 01:40:37 PM PDT 24
Peak memory 183216 kb
Host smart-049e0371-b974-413f-966f-0d4773703651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729681734 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.729681734
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.405929631
Short name T269
Test name
Test status
Simulation time 7982486068 ps
CPU time 13 seconds
Started Apr 18 01:40:34 PM PDT 24
Finished Apr 18 01:40:48 PM PDT 24
Peak memory 183348 kb
Host smart-db016601-9deb-4c37-9149-4184e865b388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405929631 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.405929631
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.471588626
Short name T198
Test name
Test status
Simulation time 550978038 ps
CPU time 0.74 seconds
Started Apr 18 01:40:35 PM PDT 24
Finished Apr 18 01:40:36 PM PDT 24
Peak memory 183268 kb
Host smart-7ac9c27c-bc3f-477d-82d3-bc089ef827a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471588626 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.471588626
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.2880128351
Short name T271
Test name
Test status
Simulation time 403318706626 ps
CPU time 61.57 seconds
Started Apr 18 01:40:35 PM PDT 24
Finished Apr 18 01:41:38 PM PDT 24
Peak memory 193804 kb
Host smart-a4d62cf1-6f1f-430b-97c1-addf241af452
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880128351 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_
all.2880128351
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.419673862
Short name T88
Test name
Test status
Simulation time 92543604362 ps
CPU time 238.43 seconds
Started Apr 18 01:40:34 PM PDT 24
Finished Apr 18 01:44:33 PM PDT 24
Peak memory 214272 kb
Host smart-7b628d20-7c14-44cd-9de4-f0320fe5b5fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419673862 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.419673862
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_jump.2658090194
Short name T112
Test name
Test status
Simulation time 363735016 ps
CPU time 1.09 seconds
Started Apr 18 01:40:35 PM PDT 24
Finished Apr 18 01:40:37 PM PDT 24
Peak memory 183300 kb
Host smart-86aa623b-6b95-44f7-aa9c-6782ddcfad9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658090194 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.2658090194
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.1505579167
Short name T109
Test name
Test status
Simulation time 27963908963 ps
CPU time 15.61 seconds
Started Apr 18 01:40:36 PM PDT 24
Finished Apr 18 01:40:52 PM PDT 24
Peak memory 183344 kb
Host smart-5ac8ebf0-12b5-459f-91ea-a6e0f269c7aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505579167 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.1505579167
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.1806318162
Short name T157
Test name
Test status
Simulation time 343297234 ps
CPU time 1.1 seconds
Started Apr 18 01:40:34 PM PDT 24
Finished Apr 18 01:40:35 PM PDT 24
Peak memory 183280 kb
Host smart-c720c573-3401-441e-bf29-ee0631d0c6a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806318162 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.1806318162
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.64200195
Short name T55
Test name
Test status
Simulation time 730727966611 ps
CPU time 386.33 seconds
Started Apr 18 01:40:43 PM PDT 24
Finished Apr 18 01:47:10 PM PDT 24
Peak memory 194016 kb
Host smart-8af9077a-4939-4c0d-b0ec-06ccb640cb61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64200195 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_al
l.64200195
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_jump.1531649906
Short name T250
Test name
Test status
Simulation time 463724017 ps
CPU time 1.26 seconds
Started Apr 18 01:40:40 PM PDT 24
Finished Apr 18 01:40:42 PM PDT 24
Peak memory 183292 kb
Host smart-5f1cec27-37dc-48b0-af72-93753c067ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531649906 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.1531649906
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.2178775860
Short name T2
Test name
Test status
Simulation time 32658127543 ps
CPU time 11.71 seconds
Started Apr 18 01:40:42 PM PDT 24
Finished Apr 18 01:40:54 PM PDT 24
Peak memory 183284 kb
Host smart-f65439c8-e9a2-4f11-98f4-f8ee3452f4bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178775860 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.2178775860
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.304668436
Short name T177
Test name
Test status
Simulation time 664879155 ps
CPU time 0.6 seconds
Started Apr 18 01:40:44 PM PDT 24
Finished Apr 18 01:40:45 PM PDT 24
Peak memory 183280 kb
Host smart-f0009301-6e0a-499c-b0f9-6f7830603d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304668436 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.304668436
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.3300743412
Short name T272
Test name
Test status
Simulation time 252696636815 ps
CPU time 322.42 seconds
Started Apr 18 01:40:44 PM PDT 24
Finished Apr 18 01:46:08 PM PDT 24
Peak memory 193532 kb
Host smart-750e3991-1d4f-4264-9ae5-6c96ec24e512
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300743412 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_
all.3300743412
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.27760427
Short name T89
Test name
Test status
Simulation time 103706139565 ps
CPU time 484.18 seconds
Started Apr 18 01:40:43 PM PDT 24
Finished Apr 18 01:48:48 PM PDT 24
Peak memory 206464 kb
Host smart-f4cf8579-319f-466e-9bc5-b965212bb5e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27760427 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.27760427
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.aon_timer_jump.3621617906
Short name T173
Test name
Test status
Simulation time 405578774 ps
CPU time 1.17 seconds
Started Apr 18 01:40:40 PM PDT 24
Finished Apr 18 01:40:41 PM PDT 24
Peak memory 183312 kb
Host smart-3ebd7592-3151-4b1a-9ceb-64c4e5ac7d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621617906 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.3621617906
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.2459884485
Short name T246
Test name
Test status
Simulation time 21039904478 ps
CPU time 8.41 seconds
Started Apr 18 01:40:42 PM PDT 24
Finished Apr 18 01:40:51 PM PDT 24
Peak memory 183364 kb
Host smart-2fac6da7-f587-4e27-be38-b480d84de666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459884485 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.2459884485
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.379145507
Short name T25
Test name
Test status
Simulation time 528683064 ps
CPU time 0.73 seconds
Started Apr 18 01:40:41 PM PDT 24
Finished Apr 18 01:40:43 PM PDT 24
Peak memory 183252 kb
Host smart-d88c74cc-5c7c-4ebb-b6d1-188694ea259d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379145507 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.379145507
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.4259001960
Short name T98
Test name
Test status
Simulation time 76083509201 ps
CPU time 31.16 seconds
Started Apr 18 01:40:41 PM PDT 24
Finished Apr 18 01:41:13 PM PDT 24
Peak memory 193644 kb
Host smart-af1d266c-8ee8-475a-b40b-dd0b75ecf767
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259001960 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_
all.4259001960
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.3171820510
Short name T161
Test name
Test status
Simulation time 4326373256 ps
CPU time 31.36 seconds
Started Apr 18 01:40:42 PM PDT 24
Finished Apr 18 01:41:14 PM PDT 24
Peak memory 198232 kb
Host smart-86db2ad0-d045-48d9-9ac4-389e8d8c4dd2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171820510 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.3171820510
Directory /workspace/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.aon_timer_jump.419913516
Short name T192
Test name
Test status
Simulation time 586673056 ps
CPU time 1.43 seconds
Started Apr 18 01:40:41 PM PDT 24
Finished Apr 18 01:40:43 PM PDT 24
Peak memory 183252 kb
Host smart-b2a4a224-afaa-447a-957f-43de84f25553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419913516 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.419913516
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.3442181949
Short name T169
Test name
Test status
Simulation time 5683223108 ps
CPU time 3.06 seconds
Started Apr 18 01:40:41 PM PDT 24
Finished Apr 18 01:40:45 PM PDT 24
Peak memory 183348 kb
Host smart-ca366523-4321-468b-88c2-6c392ce671a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442181949 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.3442181949
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.2720987133
Short name T212
Test name
Test status
Simulation time 556183599 ps
CPU time 1.2 seconds
Started Apr 18 01:40:43 PM PDT 24
Finished Apr 18 01:40:44 PM PDT 24
Peak memory 183284 kb
Host smart-bab194dd-1f40-43ae-adc7-90896356e5c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720987133 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.2720987133
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.3261926312
Short name T259
Test name
Test status
Simulation time 313225972881 ps
CPU time 185.98 seconds
Started Apr 18 01:40:41 PM PDT 24
Finished Apr 18 01:43:48 PM PDT 24
Peak memory 183268 kb
Host smart-1d4bedfb-9551-4938-8d79-4f8e2503b729
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261926312 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_
all.3261926312
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.1128062072
Short name T213
Test name
Test status
Simulation time 1009158428672 ps
CPU time 817.42 seconds
Started Apr 18 01:40:57 PM PDT 24
Finished Apr 18 01:54:35 PM PDT 24
Peak memory 201472 kb
Host smart-c73ff7c4-0dbb-4e67-be71-1a29b2ab76a0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128062072 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand_reset.1128062072
Directory /workspace/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.aon_timer_jump.3852899625
Short name T115
Test name
Test status
Simulation time 378426405 ps
CPU time 0.67 seconds
Started Apr 18 01:40:43 PM PDT 24
Finished Apr 18 01:40:44 PM PDT 24
Peak memory 183300 kb
Host smart-675bb34d-ee88-45b8-aef6-17167b6ddd74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852899625 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.3852899625
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.1000608049
Short name T168
Test name
Test status
Simulation time 30707087410 ps
CPU time 42.67 seconds
Started Apr 18 01:40:43 PM PDT 24
Finished Apr 18 01:41:26 PM PDT 24
Peak memory 183360 kb
Host smart-ad34880c-f32a-413f-ae35-9d2e1357be9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000608049 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.1000608049
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.2602199039
Short name T57
Test name
Test status
Simulation time 572109831 ps
CPU time 1.41 seconds
Started Apr 18 01:40:41 PM PDT 24
Finished Apr 18 01:40:43 PM PDT 24
Peak memory 183260 kb
Host smart-0cd46115-4c72-4e8c-b397-95621c73b38e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602199039 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.2602199039
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.1923015254
Short name T185
Test name
Test status
Simulation time 190385116114 ps
CPU time 172.64 seconds
Started Apr 18 01:40:39 PM PDT 24
Finished Apr 18 01:43:32 PM PDT 24
Peak memory 183372 kb
Host smart-20c36499-490f-4de2-888a-3b2cf803b7d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923015254 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_
all.1923015254
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_jump.3717505408
Short name T268
Test name
Test status
Simulation time 521501761 ps
CPU time 1.33 seconds
Started Apr 18 01:40:43 PM PDT 24
Finished Apr 18 01:40:45 PM PDT 24
Peak memory 183320 kb
Host smart-735c7fc6-054b-486e-a175-d3897e5e6e4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717505408 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.3717505408
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.3033552138
Short name T214
Test name
Test status
Simulation time 33154628515 ps
CPU time 26.6 seconds
Started Apr 18 01:40:43 PM PDT 24
Finished Apr 18 01:41:11 PM PDT 24
Peak memory 183328 kb
Host smart-da8fc0af-8198-4e8c-8bf3-2201863e8295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033552138 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.3033552138
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.3286206516
Short name T184
Test name
Test status
Simulation time 380850229 ps
CPU time 0.69 seconds
Started Apr 18 01:40:41 PM PDT 24
Finished Apr 18 01:40:42 PM PDT 24
Peak memory 183272 kb
Host smart-eeec5812-b57d-41f8-a8a2-9dcbd1b8534a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286206516 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.3286206516
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.1839201919
Short name T7
Test name
Test status
Simulation time 116008284312 ps
CPU time 11.7 seconds
Started Apr 18 01:40:45 PM PDT 24
Finished Apr 18 01:40:58 PM PDT 24
Peak memory 183060 kb
Host smart-adb96316-7fb0-4615-b115-030a1ce6c7dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839201919 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_
all.1839201919
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.4026079449
Short name T86
Test name
Test status
Simulation time 249447523024 ps
CPU time 374.06 seconds
Started Apr 18 01:40:47 PM PDT 24
Finished Apr 18 01:47:01 PM PDT 24
Peak memory 206460 kb
Host smart-b056e5da-8f7b-4fb6-ab55-c0d51ef8af93
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026079449 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.4026079449
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_jump.3803035872
Short name T163
Test name
Test status
Simulation time 441922931 ps
CPU time 0.78 seconds
Started Apr 18 01:40:45 PM PDT 24
Finished Apr 18 01:40:47 PM PDT 24
Peak memory 183300 kb
Host smart-000a5a2a-3951-4645-b73f-dd4f05ef09ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803035872 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.3803035872
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.825871701
Short name T28
Test name
Test status
Simulation time 15336092208 ps
CPU time 11.83 seconds
Started Apr 18 01:40:46 PM PDT 24
Finished Apr 18 01:40:58 PM PDT 24
Peak memory 183364 kb
Host smart-3bf626b1-1702-40ca-baf1-974d04366fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825871701 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.825871701
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.2373003600
Short name T261
Test name
Test status
Simulation time 409787055 ps
CPU time 0.71 seconds
Started Apr 18 01:40:46 PM PDT 24
Finished Apr 18 01:40:48 PM PDT 24
Peak memory 183188 kb
Host smart-18c5c397-9865-48c7-8916-6f28337cd8e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373003600 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.2373003600
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.4063318693
Short name T97
Test name
Test status
Simulation time 107218823381 ps
CPU time 68.06 seconds
Started Apr 18 01:40:46 PM PDT 24
Finished Apr 18 01:41:55 PM PDT 24
Peak memory 183280 kb
Host smart-ba6999a5-62b4-4824-b0bc-40b85404bbdb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063318693 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_
all.4063318693
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_jump.16762881
Short name T129
Test name
Test status
Simulation time 540342027 ps
CPU time 1.41 seconds
Started Apr 18 01:40:45 PM PDT 24
Finished Apr 18 01:40:47 PM PDT 24
Peak memory 182704 kb
Host smart-c8761ff3-a2cb-4d7d-a864-017533954475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16762881 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.16762881
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.3992582487
Short name T215
Test name
Test status
Simulation time 35372420588 ps
CPU time 48.04 seconds
Started Apr 18 01:40:47 PM PDT 24
Finished Apr 18 01:41:35 PM PDT 24
Peak memory 183352 kb
Host smart-9a065ed0-13be-41c3-a1d7-2f4063741ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992582487 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.3992582487
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.2833414562
Short name T217
Test name
Test status
Simulation time 387880005 ps
CPU time 1.14 seconds
Started Apr 18 01:40:43 PM PDT 24
Finished Apr 18 01:40:45 PM PDT 24
Peak memory 183256 kb
Host smart-f017b5aa-25c5-4afa-81bb-2b0c8b646612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833414562 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.2833414562
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.179646200
Short name T242
Test name
Test status
Simulation time 157761062083 ps
CPU time 248.69 seconds
Started Apr 18 01:40:44 PM PDT 24
Finished Apr 18 01:44:54 PM PDT 24
Peak memory 183384 kb
Host smart-17bb26a6-363e-415d-adb1-082fdfcd4cdc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179646200 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_a
ll.179646200
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.2424229300
Short name T38
Test name
Test status
Simulation time 148679650847 ps
CPU time 801.86 seconds
Started Apr 18 01:40:44 PM PDT 24
Finished Apr 18 01:54:07 PM PDT 24
Peak memory 202084 kb
Host smart-46885f18-109a-4924-ba91-2d81e2714d2c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424229300 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.2424229300
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.aon_timer_jump.285911184
Short name T59
Test name
Test status
Simulation time 449852449 ps
CPU time 1.17 seconds
Started Apr 18 01:40:51 PM PDT 24
Finished Apr 18 01:40:52 PM PDT 24
Peak memory 183256 kb
Host smart-cf554d69-68e5-4181-aa6d-e2d5170022c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285911184 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.285911184
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.1327521412
Short name T237
Test name
Test status
Simulation time 40543831509 ps
CPU time 53.69 seconds
Started Apr 18 01:40:49 PM PDT 24
Finished Apr 18 01:41:43 PM PDT 24
Peak memory 183340 kb
Host smart-7799a1fb-b86b-4445-b269-b8fbe0897d53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327521412 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.1327521412
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.413863487
Short name T145
Test name
Test status
Simulation time 425270431 ps
CPU time 0.66 seconds
Started Apr 18 01:40:45 PM PDT 24
Finished Apr 18 01:40:47 PM PDT 24
Peak memory 183292 kb
Host smart-aaf64788-ec92-4b72-af93-c456d8bbdae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413863487 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.413863487
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.2561295393
Short name T201
Test name
Test status
Simulation time 60921171378 ps
CPU time 36.82 seconds
Started Apr 18 01:40:52 PM PDT 24
Finished Apr 18 01:41:29 PM PDT 24
Peak memory 193852 kb
Host smart-5b2eaaa4-c6a9-4716-bc12-836c466be4c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561295393 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_
all.2561295393
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_jump.4068653544
Short name T222
Test name
Test status
Simulation time 408930474 ps
CPU time 1.11 seconds
Started Apr 18 01:40:18 PM PDT 24
Finished Apr 18 01:40:20 PM PDT 24
Peak memory 183196 kb
Host smart-daab8624-9c07-4dd8-bf8a-ccee603b234a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068653544 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.4068653544
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.4068650263
Short name T23
Test name
Test status
Simulation time 43856095591 ps
CPU time 61.84 seconds
Started Apr 18 01:40:21 PM PDT 24
Finished Apr 18 01:41:23 PM PDT 24
Peak memory 183296 kb
Host smart-7720cbe5-02a0-4f4b-ad16-bc5ba0626230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068650263 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.4068650263
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.2405860089
Short name T19
Test name
Test status
Simulation time 3727664679 ps
CPU time 6.61 seconds
Started Apr 18 01:40:19 PM PDT 24
Finished Apr 18 01:40:26 PM PDT 24
Peak memory 214796 kb
Host smart-0b6d2ff2-12e6-4728-97d5-4a6ad89fec3d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405860089 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.2405860089
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.960566829
Short name T152
Test name
Test status
Simulation time 370370608 ps
CPU time 1.09 seconds
Started Apr 18 01:40:20 PM PDT 24
Finished Apr 18 01:40:21 PM PDT 24
Peak memory 183212 kb
Host smart-a899ccfd-54c7-408a-b7e9-088b32f041f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960566829 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.960566829
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.1843340565
Short name T194
Test name
Test status
Simulation time 148488428263 ps
CPU time 209.18 seconds
Started Apr 18 01:40:19 PM PDT 24
Finished Apr 18 01:43:49 PM PDT 24
Peak memory 183316 kb
Host smart-74b5d017-ad3d-485f-b86e-8e970a509c80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843340565 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_a
ll.1843340565
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.120020005
Short name T49
Test name
Test status
Simulation time 19146896325 ps
CPU time 140.52 seconds
Started Apr 18 01:40:20 PM PDT 24
Finished Apr 18 01:42:41 PM PDT 24
Peak memory 198280 kb
Host smart-85d0169d-05f0-4324-a585-ab16985ce818
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120020005 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.120020005
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_jump.3297184744
Short name T114
Test name
Test status
Simulation time 423184244 ps
CPU time 0.69 seconds
Started Apr 18 01:40:52 PM PDT 24
Finished Apr 18 01:40:53 PM PDT 24
Peak memory 183312 kb
Host smart-9ca7f09b-a55b-4c3e-9b0a-c8a4f54beec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297184744 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.3297184744
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.4072373655
Short name T170
Test name
Test status
Simulation time 7124168995 ps
CPU time 3.44 seconds
Started Apr 18 01:41:00 PM PDT 24
Finished Apr 18 01:41:04 PM PDT 24
Peak memory 183364 kb
Host smart-e7136d87-668b-4647-acfb-89d8b2b0e565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072373655 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.4072373655
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.3120266174
Short name T124
Test name
Test status
Simulation time 411204207 ps
CPU time 0.72 seconds
Started Apr 18 01:40:54 PM PDT 24
Finished Apr 18 01:40:55 PM PDT 24
Peak memory 183300 kb
Host smart-8f20191d-b3ea-4b46-86f6-82f60238a8d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120266174 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.3120266174
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.3033176058
Short name T216
Test name
Test status
Simulation time 94834220511 ps
CPU time 31.88 seconds
Started Apr 18 01:40:53 PM PDT 24
Finished Apr 18 01:41:25 PM PDT 24
Peak memory 183352 kb
Host smart-4a2218e0-73eb-41c6-88b9-c5d23b1f8cc2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033176058 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_
all.3033176058
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.3925146639
Short name T91
Test name
Test status
Simulation time 66176016386 ps
CPU time 254.99 seconds
Started Apr 18 01:40:50 PM PDT 24
Finished Apr 18 01:45:05 PM PDT 24
Peak memory 198240 kb
Host smart-d00202f6-d0a0-443c-a76b-c5ff6419d9cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925146639 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.3925146639
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.aon_timer_jump.990801395
Short name T174
Test name
Test status
Simulation time 617096564 ps
CPU time 0.77 seconds
Started Apr 18 01:40:56 PM PDT 24
Finished Apr 18 01:40:57 PM PDT 24
Peak memory 183296 kb
Host smart-0a7138bf-2253-4e37-a86d-870ed49a0950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990801395 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.990801395
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.236822815
Short name T20
Test name
Test status
Simulation time 13567096822 ps
CPU time 21.71 seconds
Started Apr 18 01:40:50 PM PDT 24
Finished Apr 18 01:41:12 PM PDT 24
Peak memory 183368 kb
Host smart-40247a5c-4dde-4368-8f5f-4686d1fc09de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236822815 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.236822815
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.504574551
Short name T263
Test name
Test status
Simulation time 391180953 ps
CPU time 1.03 seconds
Started Apr 18 01:40:50 PM PDT 24
Finished Apr 18 01:40:51 PM PDT 24
Peak memory 183272 kb
Host smart-f5c84644-3eec-4149-97d3-d13881f68ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504574551 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.504574551
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.3951373278
Short name T265
Test name
Test status
Simulation time 36328891985 ps
CPU time 210.88 seconds
Started Apr 18 01:40:54 PM PDT 24
Finished Apr 18 01:44:25 PM PDT 24
Peak memory 198320 kb
Host smart-51c579ea-9ae0-4833-9e1f-24fce745cc46
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951373278 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.3951373278
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.aon_timer_jump.2567886860
Short name T276
Test name
Test status
Simulation time 365225092 ps
CPU time 1.12 seconds
Started Apr 18 01:40:51 PM PDT 24
Finished Apr 18 01:40:53 PM PDT 24
Peak memory 183300 kb
Host smart-e3831111-d38a-4a79-a27f-f9d5a9585b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567886860 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.2567886860
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.1640200015
Short name T119
Test name
Test status
Simulation time 39525518661 ps
CPU time 38.85 seconds
Started Apr 18 01:40:58 PM PDT 24
Finished Apr 18 01:41:37 PM PDT 24
Peak memory 183364 kb
Host smart-4d18e1e1-a206-4b59-a464-647af94f70c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640200015 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.1640200015
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.3712239104
Short name T200
Test name
Test status
Simulation time 448258795 ps
CPU time 1.2 seconds
Started Apr 18 01:40:56 PM PDT 24
Finished Apr 18 01:40:58 PM PDT 24
Peak memory 183304 kb
Host smart-e8b6a7e4-4551-4e47-a6fb-55307595b160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712239104 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.3712239104
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.1915485308
Short name T83
Test name
Test status
Simulation time 165729161197 ps
CPU time 215.77 seconds
Started Apr 18 01:40:51 PM PDT 24
Finished Apr 18 01:44:27 PM PDT 24
Peak memory 193912 kb
Host smart-9a9126f6-62db-42ee-aed5-ea91de7ae4aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915485308 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_
all.1915485308
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_jump.3954464086
Short name T21
Test name
Test status
Simulation time 418743895 ps
CPU time 1.12 seconds
Started Apr 18 01:40:54 PM PDT 24
Finished Apr 18 01:40:55 PM PDT 24
Peak memory 183248 kb
Host smart-9227be4b-bc61-4251-baba-790f23f70759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954464086 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.3954464086
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.1851463247
Short name T140
Test name
Test status
Simulation time 15705363650 ps
CPU time 5.5 seconds
Started Apr 18 01:40:59 PM PDT 24
Finished Apr 18 01:41:05 PM PDT 24
Peak memory 183284 kb
Host smart-ec75e3b8-1c2c-4b26-8d49-5f4519a74a5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851463247 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.1851463247
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.1457326546
Short name T235
Test name
Test status
Simulation time 611145718 ps
CPU time 0.95 seconds
Started Apr 18 01:40:55 PM PDT 24
Finished Apr 18 01:40:57 PM PDT 24
Peak memory 183308 kb
Host smart-cb941926-ee59-45ed-b48e-edc9d17dbfcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457326546 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.1457326546
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.3359166319
Short name T205
Test name
Test status
Simulation time 41566116012 ps
CPU time 15.15 seconds
Started Apr 18 01:40:49 PM PDT 24
Finished Apr 18 01:41:05 PM PDT 24
Peak memory 191516 kb
Host smart-2690649d-f41d-474f-b3a2-65802ed465cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359166319 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_
all.3359166319
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_jump.2171503181
Short name T22
Test name
Test status
Simulation time 399737090 ps
CPU time 0.82 seconds
Started Apr 18 01:40:56 PM PDT 24
Finished Apr 18 01:40:58 PM PDT 24
Peak memory 183276 kb
Host smart-33b9b314-1f87-468c-9a47-3dd8dfeccb4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171503181 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.2171503181
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.3076085824
Short name T255
Test name
Test status
Simulation time 1188583707 ps
CPU time 1.03 seconds
Started Apr 18 01:40:57 PM PDT 24
Finished Apr 18 01:40:59 PM PDT 24
Peak memory 183268 kb
Host smart-dfb9ce1a-45f4-4c0b-934d-ef693b660933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076085824 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.3076085824
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.3136893229
Short name T274
Test name
Test status
Simulation time 500732404 ps
CPU time 0.72 seconds
Started Apr 18 01:40:51 PM PDT 24
Finished Apr 18 01:40:52 PM PDT 24
Peak memory 183296 kb
Host smart-78eab2f6-0d46-4371-af73-80e7a493a5ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136893229 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.3136893229
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.2070562648
Short name T51
Test name
Test status
Simulation time 110874324638 ps
CPU time 129.48 seconds
Started Apr 18 01:40:55 PM PDT 24
Finished Apr 18 01:43:05 PM PDT 24
Peak memory 194900 kb
Host smart-34db0a0f-1f3b-455a-a203-6b07e0f363ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070562648 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_
all.2070562648
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.3796379932
Short name T94
Test name
Test status
Simulation time 282220151961 ps
CPU time 522.3 seconds
Started Apr 18 01:40:56 PM PDT 24
Finished Apr 18 01:49:38 PM PDT 24
Peak memory 198456 kb
Host smart-b82c93f5-fc1a-4c7d-8c3e-f2697e71257a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796379932 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.3796379932
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.aon_timer_jump.1349800929
Short name T233
Test name
Test status
Simulation time 407383863 ps
CPU time 1.25 seconds
Started Apr 18 01:40:59 PM PDT 24
Finished Apr 18 01:41:01 PM PDT 24
Peak memory 183308 kb
Host smart-358d6b83-f68c-40b3-a0d5-4e10ffad941f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349800929 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.1349800929
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.4150189058
Short name T178
Test name
Test status
Simulation time 24768022817 ps
CPU time 35.76 seconds
Started Apr 18 01:40:56 PM PDT 24
Finished Apr 18 01:41:32 PM PDT 24
Peak memory 183348 kb
Host smart-048ee599-2030-4b8c-bd75-7aab1ba0e4c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150189058 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.4150189058
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.3114325857
Short name T275
Test name
Test status
Simulation time 579856097 ps
CPU time 1.03 seconds
Started Apr 18 01:40:56 PM PDT 24
Finished Apr 18 01:40:58 PM PDT 24
Peak memory 183200 kb
Host smart-71f8efa7-aaa8-4aa7-86f3-cd1649a2514c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114325857 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.3114325857
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.3254973532
Short name T258
Test name
Test status
Simulation time 58114420143 ps
CPU time 24.35 seconds
Started Apr 18 01:41:00 PM PDT 24
Finished Apr 18 01:41:25 PM PDT 24
Peak memory 194620 kb
Host smart-b1a03b89-64b6-449d-a975-99b7dc11f010
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254973532 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_
all.3254973532
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.2509400650
Short name T93
Test name
Test status
Simulation time 461092107133 ps
CPU time 448.96 seconds
Started Apr 18 01:40:59 PM PDT 24
Finished Apr 18 01:48:28 PM PDT 24
Peak memory 214080 kb
Host smart-588cc738-7ecf-4c21-8ca4-1e70db0d1a68
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509400650 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.2509400650
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.aon_timer_jump.937684990
Short name T241
Test name
Test status
Simulation time 502092906 ps
CPU time 1.28 seconds
Started Apr 18 01:40:59 PM PDT 24
Finished Apr 18 01:41:01 PM PDT 24
Peak memory 183216 kb
Host smart-cf0fd109-9659-4280-863c-5418fd88acb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937684990 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.937684990
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.363389061
Short name T52
Test name
Test status
Simulation time 30300361851 ps
CPU time 11.95 seconds
Started Apr 18 01:40:57 PM PDT 24
Finished Apr 18 01:41:10 PM PDT 24
Peak memory 183348 kb
Host smart-05f7e089-885b-4871-9f19-28999dff8690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363389061 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.363389061
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.3270319022
Short name T160
Test name
Test status
Simulation time 597871350 ps
CPU time 0.99 seconds
Started Apr 18 01:40:58 PM PDT 24
Finished Apr 18 01:41:00 PM PDT 24
Peak memory 183228 kb
Host smart-30923bb0-07ad-4d66-8daa-c722cd04c384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270319022 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.3270319022
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.3307299075
Short name T96
Test name
Test status
Simulation time 403910799621 ps
CPU time 651.61 seconds
Started Apr 18 01:40:56 PM PDT 24
Finished Apr 18 01:51:48 PM PDT 24
Peak memory 193368 kb
Host smart-20dcc417-ae01-4d32-8ece-7252b84d4b23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307299075 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_
all.3307299075
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.3887911589
Short name T234
Test name
Test status
Simulation time 567280891879 ps
CPU time 1263.17 seconds
Started Apr 18 01:41:00 PM PDT 24
Finished Apr 18 02:02:04 PM PDT 24
Peak memory 208308 kb
Host smart-c91bdd25-bbb6-44b7-8224-07ff9017316e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887911589 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.3887911589
Directory /workspace/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.aon_timer_jump.3124889737
Short name T180
Test name
Test status
Simulation time 598607978 ps
CPU time 0.72 seconds
Started Apr 18 01:40:56 PM PDT 24
Finished Apr 18 01:40:57 PM PDT 24
Peak memory 183304 kb
Host smart-b0b635bb-113e-47f5-8f1d-916767cec88d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124889737 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.3124889737
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.1453768392
Short name T225
Test name
Test status
Simulation time 4978046773 ps
CPU time 7.48 seconds
Started Apr 18 01:40:55 PM PDT 24
Finished Apr 18 01:41:02 PM PDT 24
Peak memory 183360 kb
Host smart-ba3f7d4d-413b-4c62-ae69-418035eba0f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453768392 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.1453768392
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.3451551439
Short name T156
Test name
Test status
Simulation time 563832648 ps
CPU time 0.74 seconds
Started Apr 18 01:40:55 PM PDT 24
Finished Apr 18 01:40:56 PM PDT 24
Peak memory 183268 kb
Host smart-69afeae8-7b39-4d96-9974-b55940ebefab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451551439 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.3451551439
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.3748367381
Short name T151
Test name
Test status
Simulation time 184072788944 ps
CPU time 558.32 seconds
Started Apr 18 01:40:58 PM PDT 24
Finished Apr 18 01:50:16 PM PDT 24
Peak memory 199184 kb
Host smart-9c5e6b7f-64e0-430c-942a-33a4ba8cc893
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748367381 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.3748367381
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.aon_timer_jump.1862889912
Short name T176
Test name
Test status
Simulation time 372261635 ps
CPU time 0.68 seconds
Started Apr 18 01:40:59 PM PDT 24
Finished Apr 18 01:41:00 PM PDT 24
Peak memory 183220 kb
Host smart-a0d96e51-8e04-43da-a803-02888cc3c107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862889912 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.1862889912
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.3020675122
Short name T150
Test name
Test status
Simulation time 27488768321 ps
CPU time 43.8 seconds
Started Apr 18 01:40:59 PM PDT 24
Finished Apr 18 01:41:43 PM PDT 24
Peak memory 183408 kb
Host smart-8cc54f61-9799-41b4-9797-7766f3f1a292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020675122 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.3020675122
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.3865781400
Short name T253
Test name
Test status
Simulation time 419794439 ps
CPU time 0.86 seconds
Started Apr 18 01:41:02 PM PDT 24
Finished Apr 18 01:41:04 PM PDT 24
Peak memory 183260 kb
Host smart-8bfc1dbc-0d8a-4238-8d48-60a6361db2dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865781400 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.3865781400
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.306500023
Short name T30
Test name
Test status
Simulation time 174053372552 ps
CPU time 287.35 seconds
Started Apr 18 01:40:57 PM PDT 24
Finished Apr 18 01:45:45 PM PDT 24
Peak memory 183380 kb
Host smart-06dc18cb-cf9a-4442-ac9d-a9eacd3a3482
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306500023 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_a
ll.306500023
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.2104682082
Short name T47
Test name
Test status
Simulation time 290941546588 ps
CPU time 617.42 seconds
Started Apr 18 01:40:59 PM PDT 24
Finished Apr 18 01:51:17 PM PDT 24
Peak memory 206452 kb
Host smart-536a3cb0-babe-4af9-989d-291e4082247f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104682082 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand_reset.2104682082
Directory /workspace/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.aon_timer_jump.1985810968
Short name T134
Test name
Test status
Simulation time 435013590 ps
CPU time 0.67 seconds
Started Apr 18 01:40:57 PM PDT 24
Finished Apr 18 01:40:58 PM PDT 24
Peak memory 183308 kb
Host smart-6c686e02-0654-4c45-95f3-39b6966e6a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985810968 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.1985810968
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.3032649509
Short name T181
Test name
Test status
Simulation time 10283558079 ps
CPU time 16.5 seconds
Started Apr 18 01:41:01 PM PDT 24
Finished Apr 18 01:41:18 PM PDT 24
Peak memory 183364 kb
Host smart-326f963b-a818-4c76-8d1a-c2310076b6e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032649509 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.3032649509
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.4071298031
Short name T136
Test name
Test status
Simulation time 626740823 ps
CPU time 0.71 seconds
Started Apr 18 01:41:00 PM PDT 24
Finished Apr 18 01:41:01 PM PDT 24
Peak memory 183292 kb
Host smart-46eb0f1c-dfa7-47cf-b801-ea30efe2f0f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071298031 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.4071298031
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.4108258237
Short name T197
Test name
Test status
Simulation time 37630948140 ps
CPU time 52.68 seconds
Started Apr 18 01:40:57 PM PDT 24
Finished Apr 18 01:41:50 PM PDT 24
Peak memory 193716 kb
Host smart-e919808b-a750-4c7f-9e5a-faa07b491520
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108258237 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_
all.4108258237
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.3765171622
Short name T61
Test name
Test status
Simulation time 232567499493 ps
CPU time 857.68 seconds
Started Apr 18 01:40:58 PM PDT 24
Finished Apr 18 01:55:16 PM PDT 24
Peak memory 201580 kb
Host smart-ca0bc341-c44f-4937-aab8-d25cc6b6c5b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765171622 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.3765171622
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_jump.560630741
Short name T130
Test name
Test status
Simulation time 516589373 ps
CPU time 0.57 seconds
Started Apr 18 01:40:17 PM PDT 24
Finished Apr 18 01:40:18 PM PDT 24
Peak memory 183312 kb
Host smart-076f3449-f376-4717-bd06-b83181647633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560630741 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.560630741
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.771906326
Short name T34
Test name
Test status
Simulation time 20508464935 ps
CPU time 31.14 seconds
Started Apr 18 01:40:18 PM PDT 24
Finished Apr 18 01:40:49 PM PDT 24
Peak memory 183364 kb
Host smart-3e194f41-0008-4c28-a3d3-3badc473a929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771906326 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.771906326
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.2156974653
Short name T16
Test name
Test status
Simulation time 8272607771 ps
CPU time 14.3 seconds
Started Apr 18 01:40:16 PM PDT 24
Finished Apr 18 01:40:31 PM PDT 24
Peak memory 215252 kb
Host smart-fd5e077b-355f-483e-9541-99ca670e6a92
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156974653 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.2156974653
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.3878986144
Short name T164
Test name
Test status
Simulation time 350894425 ps
CPU time 1.07 seconds
Started Apr 18 01:40:20 PM PDT 24
Finished Apr 18 01:40:22 PM PDT 24
Peak memory 183288 kb
Host smart-e7f010b1-6edc-4c6e-930f-f20c40a075b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878986144 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.3878986144
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.851276859
Short name T236
Test name
Test status
Simulation time 79620805176 ps
CPU time 104.28 seconds
Started Apr 18 01:40:18 PM PDT 24
Finished Apr 18 01:42:03 PM PDT 24
Peak memory 193788 kb
Host smart-720cfc35-78fc-4ae6-8178-32732d0b8ff5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851276859 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_al
l.851276859
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_jump.891542907
Short name T27
Test name
Test status
Simulation time 478457049 ps
CPU time 1.28 seconds
Started Apr 18 01:40:57 PM PDT 24
Finished Apr 18 01:40:59 PM PDT 24
Peak memory 183284 kb
Host smart-ce449f72-ad81-44d3-b214-44eb482779da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891542907 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.891542907
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.1269119344
Short name T239
Test name
Test status
Simulation time 17408700068 ps
CPU time 14.97 seconds
Started Apr 18 01:40:57 PM PDT 24
Finished Apr 18 01:41:13 PM PDT 24
Peak memory 183372 kb
Host smart-fa9c4110-4f1f-409e-a867-9276f17688ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269119344 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.1269119344
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.1484034480
Short name T232
Test name
Test status
Simulation time 444838133 ps
CPU time 0.72 seconds
Started Apr 18 01:40:59 PM PDT 24
Finished Apr 18 01:41:00 PM PDT 24
Peak memory 183368 kb
Host smart-53139f72-e123-41cb-99ab-815299d8d44b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484034480 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.1484034480
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.2856024344
Short name T133
Test name
Test status
Simulation time 42608525687 ps
CPU time 12.88 seconds
Started Apr 18 01:40:56 PM PDT 24
Finished Apr 18 01:41:10 PM PDT 24
Peak memory 183380 kb
Host smart-e19abe7a-5dfe-4076-bbc5-d6c3e36b5af3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856024344 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_
all.2856024344
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.3737618886
Short name T14
Test name
Test status
Simulation time 35865008687 ps
CPU time 146.04 seconds
Started Apr 18 01:41:01 PM PDT 24
Finished Apr 18 01:43:27 PM PDT 24
Peak memory 198332 kb
Host smart-6fcaf587-bfd5-4230-b282-e3991bec758b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737618886 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.3737618886
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.aon_timer_jump.2997386297
Short name T6
Test name
Test status
Simulation time 554046629 ps
CPU time 0.67 seconds
Started Apr 18 01:40:59 PM PDT 24
Finished Apr 18 01:41:00 PM PDT 24
Peak memory 183368 kb
Host smart-72379d6f-0228-4641-a7f4-32da83d041c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997386297 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.2997386297
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.3049441426
Short name T50
Test name
Test status
Simulation time 22714751036 ps
CPU time 16.28 seconds
Started Apr 18 01:40:56 PM PDT 24
Finished Apr 18 01:41:14 PM PDT 24
Peak memory 183352 kb
Host smart-47376564-2e58-4d36-83a4-3fd6281b7b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049441426 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.3049441426
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.2361194064
Short name T245
Test name
Test status
Simulation time 388836356 ps
CPU time 0.59 seconds
Started Apr 18 01:40:57 PM PDT 24
Finished Apr 18 01:40:58 PM PDT 24
Peak memory 183340 kb
Host smart-7cbbddd6-ecb8-4082-95fa-bcf84dc54d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361194064 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.2361194064
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.3896380388
Short name T193
Test name
Test status
Simulation time 414757458841 ps
CPU time 282.68 seconds
Started Apr 18 01:41:03 PM PDT 24
Finished Apr 18 01:45:47 PM PDT 24
Peak memory 183364 kb
Host smart-769bc432-3133-40a8-a7ec-d4d75bec4d77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896380388 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_
all.3896380388
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.298576342
Short name T244
Test name
Test status
Simulation time 102015633210 ps
CPU time 417.16 seconds
Started Apr 18 01:41:04 PM PDT 24
Finished Apr 18 01:48:01 PM PDT 24
Peak memory 198360 kb
Host smart-c5b6f65f-74cb-49f0-a793-66636546f89a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298576342 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.298576342
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.aon_timer_jump.2164348598
Short name T167
Test name
Test status
Simulation time 556114973 ps
CPU time 1.31 seconds
Started Apr 18 01:41:02 PM PDT 24
Finished Apr 18 01:41:04 PM PDT 24
Peak memory 183256 kb
Host smart-fbe366a9-5745-4657-a32c-8954e37f5753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164348598 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.2164348598
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.1761850189
Short name T227
Test name
Test status
Simulation time 32720416930 ps
CPU time 14.12 seconds
Started Apr 18 01:41:04 PM PDT 24
Finished Apr 18 01:41:18 PM PDT 24
Peak memory 183312 kb
Host smart-96e9fd90-d917-4123-a838-0c2e7abb8354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761850189 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.1761850189
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.1682359956
Short name T159
Test name
Test status
Simulation time 599997356 ps
CPU time 1.03 seconds
Started Apr 18 01:41:03 PM PDT 24
Finished Apr 18 01:41:05 PM PDT 24
Peak memory 183312 kb
Host smart-ea64e48d-0029-4fb4-834a-9f53fe04b2c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682359956 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.1682359956
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.3201520697
Short name T191
Test name
Test status
Simulation time 146417849776 ps
CPU time 117.9 seconds
Started Apr 18 01:41:04 PM PDT 24
Finished Apr 18 01:43:02 PM PDT 24
Peak memory 183312 kb
Host smart-a81e62ee-ab2a-412c-98f2-19d0d72b9b3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201520697 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_
all.3201520697
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_jump.2615304992
Short name T137
Test name
Test status
Simulation time 629526984 ps
CPU time 0.69 seconds
Started Apr 18 01:41:02 PM PDT 24
Finished Apr 18 01:41:03 PM PDT 24
Peak memory 183204 kb
Host smart-e5522739-153a-40d1-8088-1c17a10770e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615304992 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.2615304992
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.1155795069
Short name T273
Test name
Test status
Simulation time 23907051885 ps
CPU time 9.68 seconds
Started Apr 18 01:41:02 PM PDT 24
Finished Apr 18 01:41:12 PM PDT 24
Peak memory 183352 kb
Host smart-9a9719fc-f986-4b7e-ac89-40be0e94aeb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155795069 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.1155795069
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.3048229720
Short name T84
Test name
Test status
Simulation time 494308407 ps
CPU time 0.72 seconds
Started Apr 18 01:41:02 PM PDT 24
Finished Apr 18 01:41:03 PM PDT 24
Peak memory 183296 kb
Host smart-d45c411b-5004-4a4a-92ee-fbc9b6f3471f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048229720 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.3048229720
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.1753663902
Short name T266
Test name
Test status
Simulation time 187443716612 ps
CPU time 45 seconds
Started Apr 18 01:41:02 PM PDT 24
Finished Apr 18 01:41:47 PM PDT 24
Peak memory 193692 kb
Host smart-dfd88c2d-f2b6-4ad2-9418-3c8c6601c22a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753663902 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_
all.1753663902
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_jump.3589411988
Short name T252
Test name
Test status
Simulation time 523402313 ps
CPU time 0.73 seconds
Started Apr 18 01:41:03 PM PDT 24
Finished Apr 18 01:41:04 PM PDT 24
Peak memory 183312 kb
Host smart-07716d67-185a-49a0-8d80-6ad57bde37c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589411988 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.3589411988
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.3392269958
Short name T117
Test name
Test status
Simulation time 34629177507 ps
CPU time 50.65 seconds
Started Apr 18 01:41:04 PM PDT 24
Finished Apr 18 01:41:55 PM PDT 24
Peak memory 183264 kb
Host smart-fa8dc666-6e58-4043-9a97-6c0dc1ef0995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392269958 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.3392269958
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.677606958
Short name T196
Test name
Test status
Simulation time 444609016 ps
CPU time 1.2 seconds
Started Apr 18 01:41:04 PM PDT 24
Finished Apr 18 01:41:05 PM PDT 24
Peak memory 183300 kb
Host smart-2b9d0107-a38f-42d6-b78e-82e3b2309204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677606958 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.677606958
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.1271006843
Short name T120
Test name
Test status
Simulation time 114765955913 ps
CPU time 60.55 seconds
Started Apr 18 01:41:03 PM PDT 24
Finished Apr 18 01:42:04 PM PDT 24
Peak memory 191564 kb
Host smart-11b81224-f4a0-44e5-b8b9-64638b94e58f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271006843 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_
all.1271006843
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.298478697
Short name T85
Test name
Test status
Simulation time 487095139881 ps
CPU time 981.3 seconds
Started Apr 18 01:41:02 PM PDT 24
Finished Apr 18 01:57:23 PM PDT 24
Peak memory 202812 kb
Host smart-3c3fb82d-0a0a-4e9d-b12e-abc8537154d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298478697 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.298478697
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.aon_timer_jump.3388431516
Short name T24
Test name
Test status
Simulation time 418549671 ps
CPU time 1.28 seconds
Started Apr 18 01:41:05 PM PDT 24
Finished Apr 18 01:41:06 PM PDT 24
Peak memory 183312 kb
Host smart-4ab842b4-dcf4-425d-9147-983ed41b4b98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388431516 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.3388431516
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.1686334191
Short name T146
Test name
Test status
Simulation time 16548030228 ps
CPU time 3.48 seconds
Started Apr 18 01:41:05 PM PDT 24
Finished Apr 18 01:41:08 PM PDT 24
Peak memory 183332 kb
Host smart-1e507418-a2bd-4081-8ac1-181b225943d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686334191 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.1686334191
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.2030968798
Short name T267
Test name
Test status
Simulation time 372649482 ps
CPU time 0.67 seconds
Started Apr 18 01:41:06 PM PDT 24
Finished Apr 18 01:41:07 PM PDT 24
Peak memory 183308 kb
Host smart-7b0cd75e-2bb4-4291-9b27-4917274b609c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030968798 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.2030968798
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.2369622552
Short name T264
Test name
Test status
Simulation time 35768222917 ps
CPU time 23.89 seconds
Started Apr 18 01:41:02 PM PDT 24
Finished Apr 18 01:41:26 PM PDT 24
Peak memory 193796 kb
Host smart-4b8e9f2b-ac64-4301-b36f-c1f3c802c9ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369622552 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_
all.2369622552
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.1409603147
Short name T207
Test name
Test status
Simulation time 17599172377 ps
CPU time 139.95 seconds
Started Apr 18 01:41:03 PM PDT 24
Finished Apr 18 01:43:23 PM PDT 24
Peak memory 198272 kb
Host smart-941c9735-3db6-47bb-99cf-39c4daca4de1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409603147 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.1409603147
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.aon_timer_jump.3754400347
Short name T190
Test name
Test status
Simulation time 461029077 ps
CPU time 1.27 seconds
Started Apr 18 01:41:03 PM PDT 24
Finished Apr 18 01:41:04 PM PDT 24
Peak memory 183304 kb
Host smart-e766c14c-6036-496b-b4e6-f25711e87277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754400347 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.3754400347
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.2059508943
Short name T219
Test name
Test status
Simulation time 34514196739 ps
CPU time 22.46 seconds
Started Apr 18 01:41:06 PM PDT 24
Finished Apr 18 01:41:29 PM PDT 24
Peak memory 183368 kb
Host smart-6ff8428e-03e8-4727-abb0-9380a3e762fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059508943 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.2059508943
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.1568189810
Short name T209
Test name
Test status
Simulation time 526633427 ps
CPU time 0.72 seconds
Started Apr 18 01:41:03 PM PDT 24
Finished Apr 18 01:41:04 PM PDT 24
Peak memory 183296 kb
Host smart-700badf9-7bef-4c32-a2b2-2bee03fdca19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568189810 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.1568189810
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.1265692702
Short name T118
Test name
Test status
Simulation time 166591094690 ps
CPU time 27.02 seconds
Started Apr 18 01:41:07 PM PDT 24
Finished Apr 18 01:41:34 PM PDT 24
Peak memory 183392 kb
Host smart-717068e5-630d-46cc-845b-a0267d10682f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265692702 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_
all.1265692702
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_jump.468684304
Short name T204
Test name
Test status
Simulation time 390494130 ps
CPU time 1.13 seconds
Started Apr 18 01:41:08 PM PDT 24
Finished Apr 18 01:41:09 PM PDT 24
Peak memory 183244 kb
Host smart-c05c9118-c2cf-4c75-89f3-168080d961a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468684304 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.468684304
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.3736542281
Short name T128
Test name
Test status
Simulation time 10660047390 ps
CPU time 15.56 seconds
Started Apr 18 01:41:10 PM PDT 24
Finished Apr 18 01:41:26 PM PDT 24
Peak memory 183332 kb
Host smart-d8c27343-7559-44fb-8e23-a08ffeaa9822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736542281 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.3736542281
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.2637299673
Short name T108
Test name
Test status
Simulation time 424161792 ps
CPU time 0.83 seconds
Started Apr 18 01:41:10 PM PDT 24
Finished Apr 18 01:41:11 PM PDT 24
Peak memory 183308 kb
Host smart-3bbabfae-6a21-4649-b70d-1b9b0ce4d234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637299673 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.2637299673
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.3506326909
Short name T188
Test name
Test status
Simulation time 5461532843 ps
CPU time 2.93 seconds
Started Apr 18 01:41:07 PM PDT 24
Finished Apr 18 01:41:11 PM PDT 24
Peak memory 195292 kb
Host smart-2a4a099e-2322-4e8c-bf6b-1314062a58d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506326909 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_
all.3506326909
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_jump.560807334
Short name T127
Test name
Test status
Simulation time 349230896 ps
CPU time 1.09 seconds
Started Apr 18 01:41:06 PM PDT 24
Finished Apr 18 01:41:07 PM PDT 24
Peak memory 183296 kb
Host smart-bd013ef9-ef19-440d-bab2-9fdcfe9d83a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560807334 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.560807334
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.2458951603
Short name T121
Test name
Test status
Simulation time 18241883430 ps
CPU time 6.14 seconds
Started Apr 18 01:41:06 PM PDT 24
Finished Apr 18 01:41:13 PM PDT 24
Peak memory 183288 kb
Host smart-f0339bf5-e7ca-4599-a48b-5d5f2698478f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458951603 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.2458951603
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.3133578130
Short name T224
Test name
Test status
Simulation time 485439042 ps
CPU time 0.9 seconds
Started Apr 18 01:41:06 PM PDT 24
Finished Apr 18 01:41:07 PM PDT 24
Peak memory 183284 kb
Host smart-13055794-a8f3-43c2-9350-5d0ff5af2728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133578130 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.3133578130
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.1484873253
Short name T202
Test name
Test status
Simulation time 166182595013 ps
CPU time 14.22 seconds
Started Apr 18 01:41:09 PM PDT 24
Finished Apr 18 01:41:23 PM PDT 24
Peak memory 192868 kb
Host smart-1f83782a-f55e-4ece-8abc-5241c2440519
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484873253 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_
all.1484873253
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_jump.91112917
Short name T113
Test name
Test status
Simulation time 400514725 ps
CPU time 0.84 seconds
Started Apr 18 01:41:08 PM PDT 24
Finished Apr 18 01:41:10 PM PDT 24
Peak memory 183340 kb
Host smart-65982144-8985-48d8-b850-d6b19ae3a4ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91112917 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.91112917
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.2594611441
Short name T208
Test name
Test status
Simulation time 24933916925 ps
CPU time 10.3 seconds
Started Apr 18 01:41:07 PM PDT 24
Finished Apr 18 01:41:18 PM PDT 24
Peak memory 183360 kb
Host smart-a7282a13-f748-4fde-8bb7-0842e16aa249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594611441 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.2594611441
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.415168952
Short name T171
Test name
Test status
Simulation time 418839474 ps
CPU time 0.66 seconds
Started Apr 18 01:41:09 PM PDT 24
Finished Apr 18 01:41:10 PM PDT 24
Peak memory 183296 kb
Host smart-48e96038-6384-42ac-8f0b-93bfee2f0802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415168952 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.415168952
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.1879257435
Short name T116
Test name
Test status
Simulation time 173918873366 ps
CPU time 231.36 seconds
Started Apr 18 01:41:12 PM PDT 24
Finished Apr 18 01:45:04 PM PDT 24
Peak memory 193668 kb
Host smart-c4b8120c-aecf-40c8-b868-6a83aafe497a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879257435 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_
all.1879257435
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_jump.2647559692
Short name T32
Test name
Test status
Simulation time 464650924 ps
CPU time 0.85 seconds
Started Apr 18 01:40:16 PM PDT 24
Finished Apr 18 01:40:17 PM PDT 24
Peak memory 183272 kb
Host smart-e1e29a9b-b48e-45cf-8d00-747f2506438b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647559692 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.2647559692
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.2808362031
Short name T126
Test name
Test status
Simulation time 19075918205 ps
CPU time 28.67 seconds
Started Apr 18 01:40:17 PM PDT 24
Finished Apr 18 01:40:46 PM PDT 24
Peak memory 183340 kb
Host smart-db0ad08b-6841-497e-94d5-a427fd623585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808362031 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.2808362031
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.3249971189
Short name T5
Test name
Test status
Simulation time 424406108 ps
CPU time 0.87 seconds
Started Apr 18 01:40:17 PM PDT 24
Finished Apr 18 01:40:18 PM PDT 24
Peak memory 183280 kb
Host smart-c860f7f9-f146-4447-8fbd-80796dd739f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249971189 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.3249971189
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.2045072641
Short name T230
Test name
Test status
Simulation time 147884870947 ps
CPU time 198.1 seconds
Started Apr 18 01:40:20 PM PDT 24
Finished Apr 18 01:43:39 PM PDT 24
Peak memory 194092 kb
Host smart-1fde6194-8971-4445-b95e-327cd5b72303
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045072641 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_a
ll.2045072641
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.3779708061
Short name T87
Test name
Test status
Simulation time 103767528298 ps
CPU time 728.75 seconds
Started Apr 18 01:40:19 PM PDT 24
Finished Apr 18 01:52:28 PM PDT 24
Peak memory 199564 kb
Host smart-b8a3364f-a6fc-4438-8544-987c226762d0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779708061 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.3779708061
Directory /workspace/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.aon_timer_jump.367903414
Short name T53
Test name
Test status
Simulation time 373021172 ps
CPU time 1.08 seconds
Started Apr 18 01:40:18 PM PDT 24
Finished Apr 18 01:40:20 PM PDT 24
Peak memory 183304 kb
Host smart-91b1d76c-9694-4daf-a913-67cc3c4b4489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367903414 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.367903414
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.1327545800
Short name T131
Test name
Test status
Simulation time 21696718235 ps
CPU time 10.1 seconds
Started Apr 18 01:40:22 PM PDT 24
Finished Apr 18 01:40:32 PM PDT 24
Peak memory 183316 kb
Host smart-9650156b-ce92-46d4-ab24-c0cff745a0c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327545800 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.1327545800
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.2745727255
Short name T221
Test name
Test status
Simulation time 403538657 ps
CPU time 1.13 seconds
Started Apr 18 01:40:15 PM PDT 24
Finished Apr 18 01:40:17 PM PDT 24
Peak memory 183288 kb
Host smart-7303e285-a390-4047-b9c2-26512abfd822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745727255 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.2745727255
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.466947260
Short name T132
Test name
Test status
Simulation time 208254031903 ps
CPU time 177.8 seconds
Started Apr 18 01:40:21 PM PDT 24
Finished Apr 18 01:43:19 PM PDT 24
Peak memory 183372 kb
Host smart-eb0987b4-bb46-4313-bab7-c34a173a1523
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466947260 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_al
l.466947260
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_jump.1783790637
Short name T56
Test name
Test status
Simulation time 519251965 ps
CPU time 1.06 seconds
Started Apr 18 01:40:15 PM PDT 24
Finished Apr 18 01:40:17 PM PDT 24
Peak memory 183312 kb
Host smart-ad78d309-ab88-470d-9535-01b107dca993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783790637 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.1783790637
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.4210674050
Short name T33
Test name
Test status
Simulation time 18272029667 ps
CPU time 28.77 seconds
Started Apr 18 01:40:20 PM PDT 24
Finished Apr 18 01:40:49 PM PDT 24
Peak memory 183360 kb
Host smart-7b4ae885-5e77-4624-beb1-557b4ade0923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210674050 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.4210674050
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.1775659780
Short name T238
Test name
Test status
Simulation time 419585676 ps
CPU time 0.82 seconds
Started Apr 18 01:40:18 PM PDT 24
Finished Apr 18 01:40:20 PM PDT 24
Peak memory 183304 kb
Host smart-d37ad7c7-b406-456b-aad8-3c7cbe7fc6a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775659780 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.1775659780
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.1499103907
Short name T141
Test name
Test status
Simulation time 75628231217 ps
CPU time 107.56 seconds
Started Apr 18 01:40:21 PM PDT 24
Finished Apr 18 01:42:09 PM PDT 24
Peak memory 193672 kb
Host smart-2339dba2-f9c1-4092-b3cf-5b4fb2da1d99
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499103907 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_a
ll.1499103907
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.4080085105
Short name T166
Test name
Test status
Simulation time 233045269697 ps
CPU time 662.89 seconds
Started Apr 18 01:40:19 PM PDT 24
Finished Apr 18 01:51:22 PM PDT 24
Peak memory 200748 kb
Host smart-a6cce21a-eb59-40ba-a86d-d06d5a3fd583
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080085105 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.4080085105
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.aon_timer_jump.3802851202
Short name T186
Test name
Test status
Simulation time 566282356 ps
CPU time 1.38 seconds
Started Apr 18 01:40:20 PM PDT 24
Finished Apr 18 01:40:22 PM PDT 24
Peak memory 183208 kb
Host smart-3e255291-0c4a-4951-8bec-7734357b36f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802851202 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.3802851202
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.2568497088
Short name T11
Test name
Test status
Simulation time 49350199968 ps
CPU time 32.36 seconds
Started Apr 18 01:40:19 PM PDT 24
Finished Apr 18 01:40:52 PM PDT 24
Peak memory 183104 kb
Host smart-1c954a1b-86f9-49c6-930a-580be6bea0b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568497088 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.2568497088
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.1035396285
Short name T254
Test name
Test status
Simulation time 568877041 ps
CPU time 0.72 seconds
Started Apr 18 01:40:19 PM PDT 24
Finished Apr 18 01:40:20 PM PDT 24
Peak memory 183288 kb
Host smart-e425e19f-98ba-423c-9307-60468531c492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035396285 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.1035396285
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.3677790763
Short name T12
Test name
Test status
Simulation time 68218378405 ps
CPU time 104.58 seconds
Started Apr 18 01:40:17 PM PDT 24
Finished Apr 18 01:42:03 PM PDT 24
Peak memory 183304 kb
Host smart-58cbc7dc-497f-47fa-91a2-025cb3826aae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677790763 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_a
ll.3677790763
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.2228820804
Short name T46
Test name
Test status
Simulation time 25407576132 ps
CPU time 48.71 seconds
Started Apr 18 01:40:27 PM PDT 24
Finished Apr 18 01:41:16 PM PDT 24
Peak memory 198332 kb
Host smart-e0a105a5-c8f2-4711-a04e-7cf69d9ff9f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228820804 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.2228820804
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.aon_timer_jump.2521215665
Short name T143
Test name
Test status
Simulation time 437590765 ps
CPU time 1.23 seconds
Started Apr 18 01:40:18 PM PDT 24
Finished Apr 18 01:40:20 PM PDT 24
Peak memory 183312 kb
Host smart-1d325ebe-5677-4ea8-9149-6cbca498a798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521215665 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.2521215665
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.1157639997
Short name T249
Test name
Test status
Simulation time 598081165 ps
CPU time 0.76 seconds
Started Apr 18 01:40:20 PM PDT 24
Finished Apr 18 01:40:22 PM PDT 24
Peak memory 183284 kb
Host smart-c0bf5473-d32a-4850-91ee-1de29c833073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157639997 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.1157639997
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.2667766674
Short name T10
Test name
Test status
Simulation time 445922888 ps
CPU time 0.67 seconds
Started Apr 18 01:40:19 PM PDT 24
Finished Apr 18 01:40:21 PM PDT 24
Peak memory 183288 kb
Host smart-714acd74-fd10-484e-a3c1-cb70bf1f1868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667766674 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.2667766674
Directory /workspace/9.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.2078616906
Short name T251
Test name
Test status
Simulation time 62210909799 ps
CPU time 108.4 seconds
Started Apr 18 01:40:22 PM PDT 24
Finished Apr 18 01:42:11 PM PDT 24
Peak memory 183320 kb
Host smart-e20e67aa-447a-4cae-b2b9-af95624e90bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078616906 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_a
ll.2078616906
Directory /workspace/9.aon_timer_stress_all/latest
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