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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
92.98 99.25 93.67 100.00 98.40 99.51 67.06


Total test records in report: 417
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T64 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.1851201380 Apr 23 01:19:52 PM PDT 24 Apr 23 01:19:53 PM PDT 24 1185656846 ps
T282 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.3682167006 Apr 23 01:20:00 PM PDT 24 Apr 23 01:20:02 PM PDT 24 366572985 ps
T283 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.2964323361 Apr 23 01:19:45 PM PDT 24 Apr 23 01:19:47 PM PDT 24 570899904 ps
T65 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.2756757041 Apr 23 01:19:28 PM PDT 24 Apr 23 01:19:33 PM PDT 24 2635343629 ps
T36 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.1525333839 Apr 23 01:19:44 PM PDT 24 Apr 23 01:19:52 PM PDT 24 4442442908 ps
T284 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.2547066007 Apr 23 01:20:13 PM PDT 24 Apr 23 01:20:14 PM PDT 24 314830484 ps
T285 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.316793461 Apr 23 01:19:57 PM PDT 24 Apr 23 01:19:59 PM PDT 24 329966125 ps
T286 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.3684718283 Apr 23 01:20:05 PM PDT 24 Apr 23 01:20:06 PM PDT 24 339777196 ps
T66 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.1208151617 Apr 23 01:19:46 PM PDT 24 Apr 23 01:19:47 PM PDT 24 306512587 ps
T50 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.3464704407 Apr 23 01:20:07 PM PDT 24 Apr 23 01:20:08 PM PDT 24 326834801 ps
T287 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.2551566734 Apr 23 01:19:30 PM PDT 24 Apr 23 01:19:32 PM PDT 24 471367622 ps
T288 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.1155914542 Apr 23 01:19:24 PM PDT 24 Apr 23 01:19:26 PM PDT 24 431691263 ps
T289 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.1977773722 Apr 23 01:20:00 PM PDT 24 Apr 23 01:20:01 PM PDT 24 507309588 ps
T290 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.2707786984 Apr 23 01:18:46 PM PDT 24 Apr 23 01:18:47 PM PDT 24 429205946 ps
T67 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.2343183363 Apr 23 01:19:17 PM PDT 24 Apr 23 01:19:19 PM PDT 24 2595242767 ps
T291 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.3010959641 Apr 23 01:20:01 PM PDT 24 Apr 23 01:20:02 PM PDT 24 377126929 ps
T292 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.3400839235 Apr 23 01:19:17 PM PDT 24 Apr 23 01:19:19 PM PDT 24 559117951 ps
T51 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.1147388890 Apr 23 01:19:53 PM PDT 24 Apr 23 01:19:54 PM PDT 24 539012856 ps
T52 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.4019518072 Apr 23 01:19:21 PM PDT 24 Apr 23 01:19:23 PM PDT 24 1012421998 ps
T293 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.1309056704 Apr 23 01:20:07 PM PDT 24 Apr 23 01:20:08 PM PDT 24 481301540 ps
T53 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.435874246 Apr 23 01:18:51 PM PDT 24 Apr 23 01:18:53 PM PDT 24 444600406 ps
T294 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.2847108480 Apr 23 01:19:24 PM PDT 24 Apr 23 01:19:25 PM PDT 24 280775257 ps
T295 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.3405353694 Apr 23 01:19:12 PM PDT 24 Apr 23 01:19:14 PM PDT 24 1311657143 ps
T68 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.204774005 Apr 23 01:19:31 PM PDT 24 Apr 23 01:19:36 PM PDT 24 2826070807 ps
T296 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.2277435810 Apr 23 01:19:53 PM PDT 24 Apr 23 01:19:55 PM PDT 24 312407598 ps
T297 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.285680715 Apr 23 01:20:00 PM PDT 24 Apr 23 01:20:01 PM PDT 24 525192843 ps
T298 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.3859213522 Apr 23 01:19:31 PM PDT 24 Apr 23 01:19:34 PM PDT 24 740563858 ps
T299 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.3065536409 Apr 23 01:20:02 PM PDT 24 Apr 23 01:20:03 PM PDT 24 431928995 ps
T300 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.3798596280 Apr 23 01:19:42 PM PDT 24 Apr 23 01:19:44 PM PDT 24 482410957 ps
T301 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.1657257603 Apr 23 01:18:53 PM PDT 24 Apr 23 01:18:55 PM PDT 24 456982813 ps
T69 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.431019286 Apr 23 01:19:54 PM PDT 24 Apr 23 01:19:56 PM PDT 24 1685642910 ps
T302 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.1565382682 Apr 23 01:20:00 PM PDT 24 Apr 23 01:20:01 PM PDT 24 385445825 ps
T303 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.3065014852 Apr 23 01:18:54 PM PDT 24 Apr 23 01:18:56 PM PDT 24 559086107 ps
T97 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.87502673 Apr 23 01:18:48 PM PDT 24 Apr 23 01:18:55 PM PDT 24 14132912237 ps
T304 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.1437571251 Apr 23 01:18:45 PM PDT 24 Apr 23 01:18:46 PM PDT 24 327699009 ps
T305 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.2293637695 Apr 23 01:19:38 PM PDT 24 Apr 23 01:19:41 PM PDT 24 629960651 ps
T306 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.2659864344 Apr 23 01:20:01 PM PDT 24 Apr 23 01:20:03 PM PDT 24 490786456 ps
T307 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.3046304846 Apr 23 01:19:39 PM PDT 24 Apr 23 01:19:41 PM PDT 24 612999432 ps
T308 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.46968273 Apr 23 01:18:54 PM PDT 24 Apr 23 01:18:56 PM PDT 24 574541833 ps
T54 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.2564391145 Apr 23 01:19:30 PM PDT 24 Apr 23 01:19:31 PM PDT 24 563096095 ps
T309 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.1239262774 Apr 23 01:20:00 PM PDT 24 Apr 23 01:20:01 PM PDT 24 455908859 ps
T37 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.684597935 Apr 23 01:19:52 PM PDT 24 Apr 23 01:20:07 PM PDT 24 8340056819 ps
T70 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.1645748132 Apr 23 01:19:52 PM PDT 24 Apr 23 01:19:56 PM PDT 24 2730207574 ps
T310 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.837656395 Apr 23 01:19:14 PM PDT 24 Apr 23 01:19:15 PM PDT 24 627462959 ps
T311 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.2573166502 Apr 23 01:18:43 PM PDT 24 Apr 23 01:18:45 PM PDT 24 679316206 ps
T96 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.2027966408 Apr 23 01:19:53 PM PDT 24 Apr 23 01:19:58 PM PDT 24 8486926089 ps
T312 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.3803294040 Apr 23 01:20:00 PM PDT 24 Apr 23 01:20:01 PM PDT 24 453716008 ps
T313 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.3155188417 Apr 23 01:19:39 PM PDT 24 Apr 23 01:19:43 PM PDT 24 588021673 ps
T314 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.2647009327 Apr 23 01:20:03 PM PDT 24 Apr 23 01:20:04 PM PDT 24 317912345 ps
T315 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.1842755535 Apr 23 01:19:23 PM PDT 24 Apr 23 01:19:24 PM PDT 24 404477146 ps
T316 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.101378198 Apr 23 01:19:30 PM PDT 24 Apr 23 01:19:43 PM PDT 24 8093918776 ps
T317 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.2994334927 Apr 23 01:19:34 PM PDT 24 Apr 23 01:19:35 PM PDT 24 560532023 ps
T55 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.1825385918 Apr 23 01:19:17 PM PDT 24 Apr 23 01:19:19 PM PDT 24 369990292 ps
T318 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.1799751777 Apr 23 01:19:28 PM PDT 24 Apr 23 01:19:29 PM PDT 24 499793284 ps
T319 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.1571801420 Apr 23 01:19:38 PM PDT 24 Apr 23 01:19:40 PM PDT 24 522321449 ps
T320 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.4262253632 Apr 23 01:19:54 PM PDT 24 Apr 23 01:19:57 PM PDT 24 468491250 ps
T321 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.102369116 Apr 23 01:19:35 PM PDT 24 Apr 23 01:19:36 PM PDT 24 532306423 ps
T322 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.2079842979 Apr 23 01:19:44 PM PDT 24 Apr 23 01:19:46 PM PDT 24 363070394 ps
T323 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.1798133543 Apr 23 01:19:50 PM PDT 24 Apr 23 01:19:52 PM PDT 24 433044622 ps
T324 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.187469380 Apr 23 01:19:31 PM PDT 24 Apr 23 01:19:33 PM PDT 24 591100912 ps
T56 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.3132462269 Apr 23 01:19:46 PM PDT 24 Apr 23 01:19:47 PM PDT 24 303078352 ps
T91 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.1025138005 Apr 23 01:19:26 PM PDT 24 Apr 23 01:19:31 PM PDT 24 4276785577 ps
T325 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.4147138923 Apr 23 01:19:32 PM PDT 24 Apr 23 01:19:33 PM PDT 24 300793831 ps
T326 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.3234306673 Apr 23 01:19:29 PM PDT 24 Apr 23 01:19:30 PM PDT 24 400271365 ps
T57 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.3253169661 Apr 23 01:19:23 PM PDT 24 Apr 23 01:19:24 PM PDT 24 324212815 ps
T327 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.3185621482 Apr 23 01:19:03 PM PDT 24 Apr 23 01:19:25 PM PDT 24 13945023253 ps
T95 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.2045997138 Apr 23 01:18:57 PM PDT 24 Apr 23 01:19:12 PM PDT 24 8143818485 ps
T328 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.1204980308 Apr 23 01:19:24 PM PDT 24 Apr 23 01:19:26 PM PDT 24 501037324 ps
T329 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.589304510 Apr 23 01:18:56 PM PDT 24 Apr 23 01:18:57 PM PDT 24 370748955 ps
T71 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.465326288 Apr 23 01:18:56 PM PDT 24 Apr 23 01:18:58 PM PDT 24 1523171085 ps
T330 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.1491247325 Apr 23 01:20:15 PM PDT 24 Apr 23 01:20:17 PM PDT 24 444733021 ps
T331 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.469691054 Apr 23 01:19:52 PM PDT 24 Apr 23 01:19:53 PM PDT 24 531849088 ps
T332 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.2928617393 Apr 23 01:19:49 PM PDT 24 Apr 23 01:19:51 PM PDT 24 342462173 ps
T333 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.2155531245 Apr 23 01:19:15 PM PDT 24 Apr 23 01:19:16 PM PDT 24 462243673 ps
T334 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.2638010501 Apr 23 01:19:34 PM PDT 24 Apr 23 01:19:36 PM PDT 24 400242323 ps
T335 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.3268868904 Apr 23 01:19:04 PM PDT 24 Apr 23 01:19:06 PM PDT 24 450387559 ps
T336 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.3040052945 Apr 23 01:19:34 PM PDT 24 Apr 23 01:19:36 PM PDT 24 1498057780 ps
T337 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.2516251912 Apr 23 01:18:56 PM PDT 24 Apr 23 01:18:57 PM PDT 24 358894329 ps
T338 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.1581160539 Apr 23 01:19:23 PM PDT 24 Apr 23 01:19:25 PM PDT 24 397576715 ps
T339 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.3150339080 Apr 23 01:19:14 PM PDT 24 Apr 23 01:19:17 PM PDT 24 464640563 ps
T92 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.3269235218 Apr 23 01:19:12 PM PDT 24 Apr 23 01:19:28 PM PDT 24 8698852314 ps
T340 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.2923982404 Apr 23 01:19:04 PM PDT 24 Apr 23 01:19:06 PM PDT 24 3123281460 ps
T341 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.2391989978 Apr 23 01:19:39 PM PDT 24 Apr 23 01:19:41 PM PDT 24 517677884 ps
T342 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.358254908 Apr 23 01:18:57 PM PDT 24 Apr 23 01:19:00 PM PDT 24 556906302 ps
T58 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.1491421929 Apr 23 01:19:41 PM PDT 24 Apr 23 01:19:43 PM PDT 24 443911008 ps
T343 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.1497004398 Apr 23 01:19:49 PM PDT 24 Apr 23 01:19:57 PM PDT 24 4746135701 ps
T344 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.369293092 Apr 23 01:20:00 PM PDT 24 Apr 23 01:20:02 PM PDT 24 449062530 ps
T345 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.98141268 Apr 23 01:19:33 PM PDT 24 Apr 23 01:19:35 PM PDT 24 571291368 ps
T346 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.2865540377 Apr 23 01:20:00 PM PDT 24 Apr 23 01:20:02 PM PDT 24 484237366 ps
T347 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.2936074054 Apr 23 01:20:01 PM PDT 24 Apr 23 01:20:03 PM PDT 24 430837841 ps
T348 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.3083211646 Apr 23 01:19:21 PM PDT 24 Apr 23 01:19:23 PM PDT 24 316807849 ps
T349 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.1858123571 Apr 23 01:19:56 PM PDT 24 Apr 23 01:19:57 PM PDT 24 399707764 ps
T59 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.2923236010 Apr 23 01:19:19 PM PDT 24 Apr 23 01:19:20 PM PDT 24 315896580 ps
T350 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.4267007095 Apr 23 01:20:02 PM PDT 24 Apr 23 01:20:04 PM PDT 24 423937853 ps
T351 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.654654145 Apr 23 01:19:29 PM PDT 24 Apr 23 01:19:31 PM PDT 24 457461876 ps
T352 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.1546674706 Apr 23 01:19:59 PM PDT 24 Apr 23 01:20:00 PM PDT 24 478439703 ps
T93 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.4157770429 Apr 23 01:19:34 PM PDT 24 Apr 23 01:19:47 PM PDT 24 7986908481 ps
T353 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.1302138246 Apr 23 01:20:18 PM PDT 24 Apr 23 01:20:20 PM PDT 24 422708661 ps
T354 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.3924322116 Apr 23 01:19:23 PM PDT 24 Apr 23 01:19:25 PM PDT 24 3297134492 ps
T355 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.1596872075 Apr 23 01:19:59 PM PDT 24 Apr 23 01:20:00 PM PDT 24 527289489 ps
T356 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.2004279226 Apr 23 01:19:18 PM PDT 24 Apr 23 01:19:20 PM PDT 24 411365127 ps
T62 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.12905264 Apr 23 01:19:31 PM PDT 24 Apr 23 01:19:32 PM PDT 24 300813990 ps
T357 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.1703641689 Apr 23 01:19:14 PM PDT 24 Apr 23 01:19:17 PM PDT 24 4477271446 ps
T358 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.158125152 Apr 23 01:19:28 PM PDT 24 Apr 23 01:19:30 PM PDT 24 368922308 ps
T359 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.1444470424 Apr 23 01:19:56 PM PDT 24 Apr 23 01:19:58 PM PDT 24 480893128 ps
T360 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.637794534 Apr 23 01:19:39 PM PDT 24 Apr 23 01:19:43 PM PDT 24 1246295194 ps
T361 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.177453302 Apr 23 01:19:30 PM PDT 24 Apr 23 01:19:31 PM PDT 24 1298269241 ps
T362 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.1205067320 Apr 23 01:19:46 PM PDT 24 Apr 23 01:19:48 PM PDT 24 669694934 ps
T363 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.945736231 Apr 23 01:20:11 PM PDT 24 Apr 23 01:20:13 PM PDT 24 328129302 ps
T364 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.441914912 Apr 23 01:19:00 PM PDT 24 Apr 23 01:19:01 PM PDT 24 343823378 ps
T365 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.3155734192 Apr 23 01:19:06 PM PDT 24 Apr 23 01:19:10 PM PDT 24 404508468 ps
T366 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.4141826854 Apr 23 01:19:59 PM PDT 24 Apr 23 01:20:00 PM PDT 24 400760313 ps
T367 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.3323399236 Apr 23 01:19:03 PM PDT 24 Apr 23 01:19:05 PM PDT 24 1084145697 ps
T368 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.3504613919 Apr 23 01:19:19 PM PDT 24 Apr 23 01:19:20 PM PDT 24 427848186 ps
T369 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.517614838 Apr 23 01:19:58 PM PDT 24 Apr 23 01:19:59 PM PDT 24 428155867 ps
T94 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.854185767 Apr 23 01:19:36 PM PDT 24 Apr 23 01:19:50 PM PDT 24 8453233834 ps
T370 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.958083818 Apr 23 01:18:51 PM PDT 24 Apr 23 01:18:54 PM PDT 24 1852302650 ps
T371 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.3042448151 Apr 23 01:19:40 PM PDT 24 Apr 23 01:19:56 PM PDT 24 7816842497 ps
T372 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.291809802 Apr 23 01:19:09 PM PDT 24 Apr 23 01:19:11 PM PDT 24 362459230 ps
T373 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.3648163916 Apr 23 01:20:13 PM PDT 24 Apr 23 01:20:14 PM PDT 24 438504330 ps
T374 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.3460734459 Apr 23 01:19:19 PM PDT 24 Apr 23 01:19:20 PM PDT 24 479972854 ps
T375 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.1191511684 Apr 23 01:19:16 PM PDT 24 Apr 23 01:19:19 PM PDT 24 1021509120 ps
T376 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.3238335190 Apr 23 01:19:18 PM PDT 24 Apr 23 01:19:20 PM PDT 24 345663948 ps
T63 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.341541036 Apr 23 01:18:43 PM PDT 24 Apr 23 01:18:45 PM PDT 24 951153584 ps
T377 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.641336410 Apr 23 01:19:02 PM PDT 24 Apr 23 01:19:04 PM PDT 24 320319813 ps
T378 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.1730506249 Apr 23 01:19:03 PM PDT 24 Apr 23 01:19:04 PM PDT 24 355858193 ps
T379 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.3884571982 Apr 23 01:18:45 PM PDT 24 Apr 23 01:18:47 PM PDT 24 356985455 ps
T380 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.4229693932 Apr 23 01:18:45 PM PDT 24 Apr 23 01:18:46 PM PDT 24 305921436 ps
T381 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.955706356 Apr 23 01:19:17 PM PDT 24 Apr 23 01:19:18 PM PDT 24 322166987 ps
T382 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.3700552554 Apr 23 01:19:52 PM PDT 24 Apr 23 01:19:53 PM PDT 24 482652108 ps
T383 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.2109714543 Apr 23 01:20:02 PM PDT 24 Apr 23 01:20:03 PM PDT 24 523246013 ps
T384 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.1423289694 Apr 23 01:19:05 PM PDT 24 Apr 23 01:19:06 PM PDT 24 305566601 ps
T385 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.740953886 Apr 23 01:19:51 PM PDT 24 Apr 23 01:19:53 PM PDT 24 313116087 ps
T386 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.428741686 Apr 23 01:19:38 PM PDT 24 Apr 23 01:19:41 PM PDT 24 4306333847 ps
T387 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.1986577411 Apr 23 01:19:54 PM PDT 24 Apr 23 01:19:56 PM PDT 24 959922079 ps
T60 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.3973511336 Apr 23 01:19:13 PM PDT 24 Apr 23 01:20:04 PM PDT 24 12681603387 ps
T388 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.1435334834 Apr 23 01:19:28 PM PDT 24 Apr 23 01:19:31 PM PDT 24 410788368 ps
T389 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.2798441540 Apr 23 01:19:30 PM PDT 24 Apr 23 01:19:45 PM PDT 24 8555210353 ps
T390 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.2779414431 Apr 23 01:18:54 PM PDT 24 Apr 23 01:18:55 PM PDT 24 796218581 ps
T391 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.656572164 Apr 23 01:19:00 PM PDT 24 Apr 23 01:19:04 PM PDT 24 7727848153 ps
T392 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.64242711 Apr 23 01:20:03 PM PDT 24 Apr 23 01:20:04 PM PDT 24 403256673 ps
T393 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.242475001 Apr 23 01:20:01 PM PDT 24 Apr 23 01:20:03 PM PDT 24 526103953 ps
T394 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.3067395852 Apr 23 01:19:46 PM PDT 24 Apr 23 01:19:47 PM PDT 24 383169865 ps
T395 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.1326437746 Apr 23 01:20:15 PM PDT 24 Apr 23 01:20:17 PM PDT 24 504293362 ps
T61 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.684062644 Apr 23 01:19:26 PM PDT 24 Apr 23 01:19:28 PM PDT 24 491964926 ps
T396 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.409377130 Apr 23 01:19:47 PM PDT 24 Apr 23 01:19:49 PM PDT 24 506884209 ps
T397 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.2108597801 Apr 23 01:19:41 PM PDT 24 Apr 23 01:19:43 PM PDT 24 494824451 ps
T398 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.1532152661 Apr 23 01:18:54 PM PDT 24 Apr 23 01:19:31 PM PDT 24 13479012942 ps
T399 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.1914110584 Apr 23 01:18:53 PM PDT 24 Apr 23 01:18:54 PM PDT 24 810737979 ps
T400 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.1055042925 Apr 23 01:19:12 PM PDT 24 Apr 23 01:19:14 PM PDT 24 397019800 ps
T401 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.1921568678 Apr 23 01:19:45 PM PDT 24 Apr 23 01:19:49 PM PDT 24 2310993696 ps
T402 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.64010914 Apr 23 01:18:54 PM PDT 24 Apr 23 01:18:56 PM PDT 24 615786081 ps
T403 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.3023844267 Apr 23 01:19:24 PM PDT 24 Apr 23 01:19:26 PM PDT 24 521145629 ps
T404 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.2361007942 Apr 23 01:20:04 PM PDT 24 Apr 23 01:20:05 PM PDT 24 300903606 ps
T405 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.4002173832 Apr 23 01:18:45 PM PDT 24 Apr 23 01:18:53 PM PDT 24 8092549108 ps
T406 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.3152443343 Apr 23 01:19:31 PM PDT 24 Apr 23 01:19:36 PM PDT 24 8108501318 ps
T407 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.727450484 Apr 23 01:19:39 PM PDT 24 Apr 23 01:19:41 PM PDT 24 2251466607 ps
T408 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.1590549666 Apr 23 01:19:49 PM PDT 24 Apr 23 01:19:51 PM PDT 24 1711734237 ps
T409 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.975158948 Apr 23 01:19:07 PM PDT 24 Apr 23 01:19:09 PM PDT 24 455772588 ps
T410 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.2236186195 Apr 23 01:19:23 PM PDT 24 Apr 23 01:19:28 PM PDT 24 2503260367 ps
T411 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.3241717455 Apr 23 01:19:49 PM PDT 24 Apr 23 01:19:52 PM PDT 24 416476589 ps
T412 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.1084193771 Apr 23 01:19:48 PM PDT 24 Apr 23 01:19:52 PM PDT 24 2740959412 ps
T413 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.1984555461 Apr 23 01:20:05 PM PDT 24 Apr 23 01:20:07 PM PDT 24 375820428 ps
T414 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.966540586 Apr 23 01:19:19 PM PDT 24 Apr 23 01:19:25 PM PDT 24 7115460001 ps
T415 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.1072292101 Apr 23 01:19:51 PM PDT 24 Apr 23 01:19:56 PM PDT 24 4046476483 ps
T416 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.1952686576 Apr 23 01:19:21 PM PDT 24 Apr 23 01:19:29 PM PDT 24 8125238437 ps
T417 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.491326069 Apr 23 01:19:27 PM PDT 24 Apr 23 01:19:28 PM PDT 24 590195145 ps

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.115202184
Short name T1
Test name
Test status
Simulation time 118112212899 ps
CPU time 360.78 seconds
Started Apr 23 02:14:14 PM PDT 24
Finished Apr 23 02:20:15 PM PDT 24
Peak memory 198328 kb
Host smart-8dafb272-03d1-4747-be53-d81c42845b36
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115202184 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.115202184
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.1843957359
Short name T35
Test name
Test status
Simulation time 7827230096 ps
CPU time 4.49 seconds
Started Apr 23 01:19:22 PM PDT 24
Finished Apr 23 01:19:27 PM PDT 24
Peak memory 198228 kb
Host smart-deaf53e3-f6a6-43a6-9c19-e49d6315f7fd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843957359 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl
_intg_err.1843957359
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.1884549600
Short name T39
Test name
Test status
Simulation time 97531737179 ps
CPU time 313.67 seconds
Started Apr 23 02:14:03 PM PDT 24
Finished Apr 23 02:19:17 PM PDT 24
Peak memory 198348 kb
Host smart-2eada06f-e4dc-473d-aa1c-6c98c6a684c3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884549600 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.1884549600
Directory /workspace/9.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.429420899
Short name T11
Test name
Test status
Simulation time 141599218774 ps
CPU time 218.6 seconds
Started Apr 23 02:13:49 PM PDT 24
Finished Apr 23 02:17:28 PM PDT 24
Peak memory 193720 kb
Host smart-6dc03d5e-0539-49cf-86fa-1c76b0dc9256
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429420899 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_al
l.429420899
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.2564391145
Short name T54
Test name
Test status
Simulation time 563096095 ps
CPU time 1.03 seconds
Started Apr 23 01:19:30 PM PDT 24
Finished Apr 23 01:19:31 PM PDT 24
Peak memory 193220 kb
Host smart-15ba385e-8ae8-4d76-9102-da1a4dfc06bc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564391145 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.2564391145
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.3814691613
Short name T17
Test name
Test status
Simulation time 3915141179 ps
CPU time 6.81 seconds
Started Apr 23 02:13:55 PM PDT 24
Finished Apr 23 02:14:02 PM PDT 24
Peak memory 214732 kb
Host smart-a82da495-b0b5-4e58-9d0c-3bdb02511641
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814691613 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.3814691613
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.3844306938
Short name T82
Test name
Test status
Simulation time 77982806586 ps
CPU time 154.63 seconds
Started Apr 23 02:14:05 PM PDT 24
Finished Apr 23 02:16:41 PM PDT 24
Peak memory 198248 kb
Host smart-4a0525a2-7f92-4fd8-bdd4-def9a0139fde
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844306938 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.3844306938
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.947102950
Short name T136
Test name
Test status
Simulation time 84894219672 ps
CPU time 109.69 seconds
Started Apr 23 02:14:37 PM PDT 24
Finished Apr 23 02:16:28 PM PDT 24
Peak memory 198332 kb
Host smart-671917b8-9df8-47e4-98c7-5101c0a4671b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947102950 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.947102950
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.1208151617
Short name T66
Test name
Test status
Simulation time 306512587 ps
CPU time 1.12 seconds
Started Apr 23 01:19:46 PM PDT 24
Finished Apr 23 01:19:47 PM PDT 24
Peak memory 192180 kb
Host smart-905c8119-5feb-4dd7-a85e-8733dff24b71
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208151617 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.1208151617
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.3152443343
Short name T406
Test name
Test status
Simulation time 8108501318 ps
CPU time 4.03 seconds
Started Apr 23 01:19:31 PM PDT 24
Finished Apr 23 01:19:36 PM PDT 24
Peak memory 198116 kb
Host smart-6d25ad03-1f54-4dff-850c-69cb329e93a8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152443343 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_t
l_intg_err.3152443343
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.105848540
Short name T40
Test name
Test status
Simulation time 84688402245 ps
CPU time 407.26 seconds
Started Apr 23 02:14:12 PM PDT 24
Finished Apr 23 02:21:00 PM PDT 24
Peak memory 198316 kb
Host smart-e6ff2558-c99f-456a-b913-cfc73b88b3e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105848540 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.105848540
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.435874246
Short name T53
Test name
Test status
Simulation time 444600406 ps
CPU time 1.26 seconds
Started Apr 23 01:18:51 PM PDT 24
Finished Apr 23 01:18:53 PM PDT 24
Peak memory 183812 kb
Host smart-5e1a6223-5577-46ef-bad1-1f00c1b78d54
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435874246 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_al
iasing.435874246
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.87502673
Short name T97
Test name
Test status
Simulation time 14132912237 ps
CPU time 6.69 seconds
Started Apr 23 01:18:48 PM PDT 24
Finished Apr 23 01:18:55 PM PDT 24
Peak memory 192392 kb
Host smart-c183242a-386f-435d-af43-c8d4a0ca40f9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87502673 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_bit
_bash.87502673
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.341541036
Short name T63
Test name
Test status
Simulation time 951153584 ps
CPU time 1.44 seconds
Started Apr 23 01:18:43 PM PDT 24
Finished Apr 23 01:18:45 PM PDT 24
Peak memory 193352 kb
Host smart-0c4a5f82-f8a4-43fa-b6fa-1a8917c2992f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341541036 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_hw
_reset.341541036
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.64010914
Short name T402
Test name
Test status
Simulation time 615786081 ps
CPU time 1.61 seconds
Started Apr 23 01:18:54 PM PDT 24
Finished Apr 23 01:18:56 PM PDT 24
Peak memory 196096 kb
Host smart-f3a85df8-cb4c-44f8-b4e2-3015ea5464b4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64010914 -assert nopostproc +UVM_TESTNAME=a
on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.64010914
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.3884571982
Short name T379
Test name
Test status
Simulation time 356985455 ps
CPU time 1.13 seconds
Started Apr 23 01:18:45 PM PDT 24
Finished Apr 23 01:18:47 PM PDT 24
Peak memory 193184 kb
Host smart-152075ea-338c-49f7-a45f-f30b160893e4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884571982 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.3884571982
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.2707786984
Short name T290
Test name
Test status
Simulation time 429205946 ps
CPU time 0.68 seconds
Started Apr 23 01:18:46 PM PDT 24
Finished Apr 23 01:18:47 PM PDT 24
Peak memory 183884 kb
Host smart-48824b0e-3e94-458d-8e56-7890b7e70460
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707786984 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.2707786984
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.4229693932
Short name T380
Test name
Test status
Simulation time 305921436 ps
CPU time 0.61 seconds
Started Apr 23 01:18:45 PM PDT 24
Finished Apr 23 01:18:46 PM PDT 24
Peak memory 183732 kb
Host smart-d8e99362-6af6-4359-8821-efd4d40ec248
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229693932 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_t
imer_mem_partial_access.4229693932
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.1437571251
Short name T304
Test name
Test status
Simulation time 327699009 ps
CPU time 0.64 seconds
Started Apr 23 01:18:45 PM PDT 24
Finished Apr 23 01:18:46 PM PDT 24
Peak memory 183776 kb
Host smart-27b5d5aa-a5df-43ab-83ae-cc35f9b34d1d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437571251 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_w
alk.1437571251
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.958083818
Short name T370
Test name
Test status
Simulation time 1852302650 ps
CPU time 1.91 seconds
Started Apr 23 01:18:51 PM PDT 24
Finished Apr 23 01:18:54 PM PDT 24
Peak memory 194772 kb
Host smart-876aded5-5a85-40f1-ad2d-0695355ef5f0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958083818 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_
timer_same_csr_outstanding.958083818
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.2573166502
Short name T311
Test name
Test status
Simulation time 679316206 ps
CPU time 1.95 seconds
Started Apr 23 01:18:43 PM PDT 24
Finished Apr 23 01:18:45 PM PDT 24
Peak memory 198744 kb
Host smart-1567316e-b5e0-4c09-b01e-438dcfc059e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573166502 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.2573166502
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.4002173832
Short name T405
Test name
Test status
Simulation time 8092549108 ps
CPU time 7.6 seconds
Started Apr 23 01:18:45 PM PDT 24
Finished Apr 23 01:18:53 PM PDT 24
Peak memory 198144 kb
Host smart-74711245-b979-4e5d-b4fc-ccfa80c08b9d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002173832 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl
_intg_err.4002173832
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.2779414431
Short name T390
Test name
Test status
Simulation time 796218581 ps
CPU time 0.99 seconds
Started Apr 23 01:18:54 PM PDT 24
Finished Apr 23 01:18:55 PM PDT 24
Peak memory 183916 kb
Host smart-37160438-c527-48a5-a6a1-97b8675ec24a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779414431 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_a
liasing.2779414431
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.1532152661
Short name T398
Test name
Test status
Simulation time 13479012942 ps
CPU time 35.91 seconds
Started Apr 23 01:18:54 PM PDT 24
Finished Apr 23 01:19:31 PM PDT 24
Peak memory 192388 kb
Host smart-93f04fa4-8148-4062-8904-9811ba700ebe
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532152661 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_b
it_bash.1532152661
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.1914110584
Short name T399
Test name
Test status
Simulation time 810737979 ps
CPU time 0.91 seconds
Started Apr 23 01:18:53 PM PDT 24
Finished Apr 23 01:18:54 PM PDT 24
Peak memory 183996 kb
Host smart-ca53f891-e8f5-42fc-a183-0a76d35994fd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914110584 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_h
w_reset.1914110584
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.1430231025
Short name T32
Test name
Test status
Simulation time 324602759 ps
CPU time 1.13 seconds
Started Apr 23 01:18:58 PM PDT 24
Finished Apr 23 01:18:59 PM PDT 24
Peak memory 195944 kb
Host smart-73ceb493-45ed-475b-8729-45cdbf65ee71
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430231025 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.1430231025
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.3065014852
Short name T303
Test name
Test status
Simulation time 559086107 ps
CPU time 0.74 seconds
Started Apr 23 01:18:54 PM PDT 24
Finished Apr 23 01:18:56 PM PDT 24
Peak memory 193068 kb
Host smart-cd7580c4-e5a9-4a33-9e8e-e312d5d91be6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065014852 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.3065014852
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.1657257603
Short name T301
Test name
Test status
Simulation time 456982813 ps
CPU time 1.12 seconds
Started Apr 23 01:18:53 PM PDT 24
Finished Apr 23 01:18:55 PM PDT 24
Peak memory 183908 kb
Host smart-88e25b55-b289-4319-a922-cfa0b329ff66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657257603 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.1657257603
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.46968273
Short name T308
Test name
Test status
Simulation time 574541833 ps
CPU time 0.55 seconds
Started Apr 23 01:18:54 PM PDT 24
Finished Apr 23 01:18:56 PM PDT 24
Peak memory 183752 kb
Host smart-d0229a88-b9bc-4869-9307-45f3524b2344
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46968273 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_
timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_tim
er_mem_partial_access.46968273
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.589304510
Short name T329
Test name
Test status
Simulation time 370748955 ps
CPU time 0.96 seconds
Started Apr 23 01:18:56 PM PDT 24
Finished Apr 23 01:18:57 PM PDT 24
Peak memory 183748 kb
Host smart-c0feb927-3e9f-44ef-84ee-04c49808cf7b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589304510 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_wa
lk.589304510
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.465326288
Short name T71
Test name
Test status
Simulation time 1523171085 ps
CPU time 1.3 seconds
Started Apr 23 01:18:56 PM PDT 24
Finished Apr 23 01:18:58 PM PDT 24
Peak memory 183968 kb
Host smart-20a5036a-a173-480f-ba2b-388c3f00dba0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465326288 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_
timer_same_csr_outstanding.465326288
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.641336410
Short name T377
Test name
Test status
Simulation time 320319813 ps
CPU time 1.42 seconds
Started Apr 23 01:19:02 PM PDT 24
Finished Apr 23 01:19:04 PM PDT 24
Peak memory 198836 kb
Host smart-f2ccddc8-c619-4f21-96c3-8adf413fe0c9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641336410 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.641336410
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.2045997138
Short name T95
Test name
Test status
Simulation time 8143818485 ps
CPU time 14.59 seconds
Started Apr 23 01:18:57 PM PDT 24
Finished Apr 23 01:19:12 PM PDT 24
Peak memory 198088 kb
Host smart-b8f14598-86cd-48f7-b8f9-bb46c30c71eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045997138 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl
_intg_err.2045997138
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.2638010501
Short name T334
Test name
Test status
Simulation time 400242323 ps
CPU time 1.24 seconds
Started Apr 23 01:19:34 PM PDT 24
Finished Apr 23 01:19:36 PM PDT 24
Peak memory 195396 kb
Host smart-4757cb1e-bc99-4b6d-958c-32f8f1815e58
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638010501 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.2638010501
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.4147138923
Short name T325
Test name
Test status
Simulation time 300793831 ps
CPU time 0.94 seconds
Started Apr 23 01:19:32 PM PDT 24
Finished Apr 23 01:19:33 PM PDT 24
Peak memory 183880 kb
Host smart-a4c92fbc-fb8b-4a49-bda4-85479a1664f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147138923 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.4147138923
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.177453302
Short name T361
Test name
Test status
Simulation time 1298269241 ps
CPU time 1.15 seconds
Started Apr 23 01:19:30 PM PDT 24
Finished Apr 23 01:19:31 PM PDT 24
Peak memory 184020 kb
Host smart-2e507532-a65b-43a7-bd12-8160f7b0766d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177453302 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon
_timer_same_csr_outstanding.177453302
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.2551566734
Short name T287
Test name
Test status
Simulation time 471367622 ps
CPU time 1.18 seconds
Started Apr 23 01:19:30 PM PDT 24
Finished Apr 23 01:19:32 PM PDT 24
Peak memory 198524 kb
Host smart-d956f917-c595-488e-9c76-3c01a8317144
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551566734 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.2551566734
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.2994334927
Short name T317
Test name
Test status
Simulation time 560532023 ps
CPU time 0.95 seconds
Started Apr 23 01:19:34 PM PDT 24
Finished Apr 23 01:19:35 PM PDT 24
Peak memory 195600 kb
Host smart-e750d8e5-8e3c-4710-9caf-4bc0c4b0d9f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994334927 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.2994334927
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.98141268
Short name T345
Test name
Test status
Simulation time 571291368 ps
CPU time 0.73 seconds
Started Apr 23 01:19:33 PM PDT 24
Finished Apr 23 01:19:35 PM PDT 24
Peak memory 193084 kb
Host smart-5bb43f81-67a7-4bc1-b3c6-f71d62691d8c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98141268 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.98141268
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.1571801420
Short name T319
Test name
Test status
Simulation time 522321449 ps
CPU time 0.72 seconds
Started Apr 23 01:19:38 PM PDT 24
Finished Apr 23 01:19:40 PM PDT 24
Peak memory 183820 kb
Host smart-d2cd8b52-1ae3-4393-b788-649c65bca506
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571801420 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.1571801420
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.3040052945
Short name T336
Test name
Test status
Simulation time 1498057780 ps
CPU time 1.67 seconds
Started Apr 23 01:19:34 PM PDT 24
Finished Apr 23 01:19:36 PM PDT 24
Peak memory 193536 kb
Host smart-096ca6e2-b5b8-4e36-bbcf-eb0f1cba32e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040052945 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.ao
n_timer_same_csr_outstanding.3040052945
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.3859213522
Short name T298
Test name
Test status
Simulation time 740563858 ps
CPU time 1.94 seconds
Started Apr 23 01:19:31 PM PDT 24
Finished Apr 23 01:19:34 PM PDT 24
Peak memory 198824 kb
Host smart-ff0ba1ce-23bc-4846-ae73-4990bd69344a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859213522 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.3859213522
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.854185767
Short name T94
Test name
Test status
Simulation time 8453233834 ps
CPU time 13.61 seconds
Started Apr 23 01:19:36 PM PDT 24
Finished Apr 23 01:19:50 PM PDT 24
Peak memory 198264 kb
Host smart-55bbf8db-6e82-4f24-8dea-d10a17715dc0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854185767 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl
_intg_err.854185767
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.2079842979
Short name T322
Test name
Test status
Simulation time 363070394 ps
CPU time 1.15 seconds
Started Apr 23 01:19:44 PM PDT 24
Finished Apr 23 01:19:46 PM PDT 24
Peak memory 195380 kb
Host smart-ceddbe77-ae18-4019-a698-6c7947165d22
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079842979 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.2079842979
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.1491421929
Short name T58
Test name
Test status
Simulation time 443911008 ps
CPU time 0.9 seconds
Started Apr 23 01:19:41 PM PDT 24
Finished Apr 23 01:19:43 PM PDT 24
Peak memory 193280 kb
Host smart-c7e05066-7531-4653-8a29-f51dec37cf00
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491421929 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.1491421929
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.1253469243
Short name T281
Test name
Test status
Simulation time 407580598 ps
CPU time 0.8 seconds
Started Apr 23 01:19:39 PM PDT 24
Finished Apr 23 01:19:40 PM PDT 24
Peak memory 183760 kb
Host smart-e8a89905-22f0-405c-b948-394df5e8288f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253469243 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.1253469243
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.727450484
Short name T407
Test name
Test status
Simulation time 2251466607 ps
CPU time 1.67 seconds
Started Apr 23 01:19:39 PM PDT 24
Finished Apr 23 01:19:41 PM PDT 24
Peak memory 192216 kb
Host smart-7afac4a4-7d08-499c-9410-b4962d0ebff0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727450484 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon
_timer_same_csr_outstanding.727450484
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.3155188417
Short name T313
Test name
Test status
Simulation time 588021673 ps
CPU time 2.41 seconds
Started Apr 23 01:19:39 PM PDT 24
Finished Apr 23 01:19:43 PM PDT 24
Peak memory 198864 kb
Host smart-5a3c2417-228b-4ad3-8300-743ae36c5e68
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155188417 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.3155188417
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.4157770429
Short name T93
Test name
Test status
Simulation time 7986908481 ps
CPU time 13.06 seconds
Started Apr 23 01:19:34 PM PDT 24
Finished Apr 23 01:19:47 PM PDT 24
Peak memory 198120 kb
Host smart-0d442e73-8f70-4fc6-8172-b268f260b910
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157770429 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_t
l_intg_err.4157770429
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.3046304846
Short name T307
Test name
Test status
Simulation time 612999432 ps
CPU time 0.89 seconds
Started Apr 23 01:19:39 PM PDT 24
Finished Apr 23 01:19:41 PM PDT 24
Peak memory 196480 kb
Host smart-d5bd46e4-781d-48d2-a512-66e8d4456ab9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046304846 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.3046304846
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.2108597801
Short name T397
Test name
Test status
Simulation time 494824451 ps
CPU time 0.77 seconds
Started Apr 23 01:19:41 PM PDT 24
Finished Apr 23 01:19:43 PM PDT 24
Peak memory 183868 kb
Host smart-789c0898-fd7c-4480-aeb8-649b5eefda96
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108597801 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.2108597801
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.2391989978
Short name T341
Test name
Test status
Simulation time 517677884 ps
CPU time 0.69 seconds
Started Apr 23 01:19:39 PM PDT 24
Finished Apr 23 01:19:41 PM PDT 24
Peak memory 183816 kb
Host smart-35b1c022-2327-48f1-903f-1fbc85b6cb5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391989978 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.2391989978
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.637794534
Short name T360
Test name
Test status
Simulation time 1246295194 ps
CPU time 3.37 seconds
Started Apr 23 01:19:39 PM PDT 24
Finished Apr 23 01:19:43 PM PDT 24
Peak memory 183960 kb
Host smart-c46b7817-452d-4008-ac94-6717fdc85e2e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637794534 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon
_timer_same_csr_outstanding.637794534
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.2293637695
Short name T305
Test name
Test status
Simulation time 629960651 ps
CPU time 2.49 seconds
Started Apr 23 01:19:38 PM PDT 24
Finished Apr 23 01:19:41 PM PDT 24
Peak memory 198780 kb
Host smart-feb7ca48-d9ad-483b-bbc3-ce2cff1ccaff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293637695 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.2293637695
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.428741686
Short name T386
Test name
Test status
Simulation time 4306333847 ps
CPU time 2.7 seconds
Started Apr 23 01:19:38 PM PDT 24
Finished Apr 23 01:19:41 PM PDT 24
Peak memory 197828 kb
Host smart-b4cf22a4-1cad-4bc4-935f-cf90f8e60645
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428741686 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl
_intg_err.428741686
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.409377130
Short name T396
Test name
Test status
Simulation time 506884209 ps
CPU time 1.48 seconds
Started Apr 23 01:19:47 PM PDT 24
Finished Apr 23 01:19:49 PM PDT 24
Peak memory 196180 kb
Host smart-2cf66c4e-0d87-4c55-99b0-9e12ea66367f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409377130 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.409377130
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.3132462269
Short name T56
Test name
Test status
Simulation time 303078352 ps
CPU time 1.07 seconds
Started Apr 23 01:19:46 PM PDT 24
Finished Apr 23 01:19:47 PM PDT 24
Peak memory 193364 kb
Host smart-b3f37739-bd97-45c4-b9e8-0c7471292617
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132462269 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.3132462269
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.3798596280
Short name T300
Test name
Test status
Simulation time 482410957 ps
CPU time 0.61 seconds
Started Apr 23 01:19:42 PM PDT 24
Finished Apr 23 01:19:44 PM PDT 24
Peak memory 183880 kb
Host smart-f3915145-0b13-4321-b046-4e12c0aff3fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798596280 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.3798596280
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.1590549666
Short name T408
Test name
Test status
Simulation time 1711734237 ps
CPU time 1.21 seconds
Started Apr 23 01:19:49 PM PDT 24
Finished Apr 23 01:19:51 PM PDT 24
Peak memory 193476 kb
Host smart-ffcd1acc-5f18-430b-a89e-f756819b4e39
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590549666 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao
n_timer_same_csr_outstanding.1590549666
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.2964323361
Short name T283
Test name
Test status
Simulation time 570899904 ps
CPU time 2.09 seconds
Started Apr 23 01:19:45 PM PDT 24
Finished Apr 23 01:19:47 PM PDT 24
Peak memory 198760 kb
Host smart-47494a11-480f-42e5-841a-8337b1a4d21c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964323361 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.2964323361
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.3042448151
Short name T371
Test name
Test status
Simulation time 7816842497 ps
CPU time 14.94 seconds
Started Apr 23 01:19:40 PM PDT 24
Finished Apr 23 01:19:56 PM PDT 24
Peak memory 198160 kb
Host smart-4a5ccfcd-9208-4e75-a69a-09a80cb00b2a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042448151 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_t
l_intg_err.3042448151
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.469691054
Short name T331
Test name
Test status
Simulation time 531849088 ps
CPU time 0.86 seconds
Started Apr 23 01:19:52 PM PDT 24
Finished Apr 23 01:19:53 PM PDT 24
Peak memory 196276 kb
Host smart-63373925-6e92-4c12-81ee-76fa0205173c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469691054 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.469691054
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.3067395852
Short name T394
Test name
Test status
Simulation time 383169865 ps
CPU time 0.6 seconds
Started Apr 23 01:19:46 PM PDT 24
Finished Apr 23 01:19:47 PM PDT 24
Peak memory 183812 kb
Host smart-59c87327-9f51-4ca3-ac4b-11a56dc054d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067395852 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.3067395852
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.1921568678
Short name T401
Test name
Test status
Simulation time 2310993696 ps
CPU time 3.88 seconds
Started Apr 23 01:19:45 PM PDT 24
Finished Apr 23 01:19:49 PM PDT 24
Peak memory 194740 kb
Host smart-e67c8ef7-7b51-428f-8967-7abcb5e923dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921568678 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.ao
n_timer_same_csr_outstanding.1921568678
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.1205067320
Short name T362
Test name
Test status
Simulation time 669694934 ps
CPU time 2.17 seconds
Started Apr 23 01:19:46 PM PDT 24
Finished Apr 23 01:19:48 PM PDT 24
Peak memory 198768 kb
Host smart-55033ef7-8c4f-4a86-a189-c434f2386e53
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205067320 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.1205067320
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.1525333839
Short name T36
Test name
Test status
Simulation time 4442442908 ps
CPU time 7.53 seconds
Started Apr 23 01:19:44 PM PDT 24
Finished Apr 23 01:19:52 PM PDT 24
Peak memory 197852 kb
Host smart-2b289554-c0e8-4fad-8ec8-e93473e6cc1b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525333839 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_t
l_intg_err.1525333839
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.2928617393
Short name T332
Test name
Test status
Simulation time 342462173 ps
CPU time 1.18 seconds
Started Apr 23 01:19:49 PM PDT 24
Finished Apr 23 01:19:51 PM PDT 24
Peak memory 195416 kb
Host smart-b32c2b46-f417-4ad2-820e-0f4546c43586
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928617393 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.2928617393
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.1147388890
Short name T51
Test name
Test status
Simulation time 539012856 ps
CPU time 0.66 seconds
Started Apr 23 01:19:53 PM PDT 24
Finished Apr 23 01:19:54 PM PDT 24
Peak memory 193236 kb
Host smart-ead142ae-656f-43c3-bbd6-3315d47a4bea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147388890 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.1147388890
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.740953886
Short name T385
Test name
Test status
Simulation time 313116087 ps
CPU time 0.96 seconds
Started Apr 23 01:19:51 PM PDT 24
Finished Apr 23 01:19:53 PM PDT 24
Peak memory 183756 kb
Host smart-aa9509bd-62a8-48fe-ade2-2bd85fb13c81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740953886 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.740953886
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.1084193771
Short name T412
Test name
Test status
Simulation time 2740959412 ps
CPU time 3.83 seconds
Started Apr 23 01:19:48 PM PDT 24
Finished Apr 23 01:19:52 PM PDT 24
Peak memory 192320 kb
Host smart-13a20a02-47e8-4993-8a71-9b5f95d3bc75
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084193771 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.ao
n_timer_same_csr_outstanding.1084193771
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.3241717455
Short name T411
Test name
Test status
Simulation time 416476589 ps
CPU time 2.27 seconds
Started Apr 23 01:19:49 PM PDT 24
Finished Apr 23 01:19:52 PM PDT 24
Peak memory 198784 kb
Host smart-2ceb090a-d392-4426-8b6b-44584ce0a092
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241717455 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.3241717455
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.1497004398
Short name T343
Test name
Test status
Simulation time 4746135701 ps
CPU time 7.94 seconds
Started Apr 23 01:19:49 PM PDT 24
Finished Apr 23 01:19:57 PM PDT 24
Peak memory 197916 kb
Host smart-1798ae2b-4d59-4e97-b8bb-c8f0809652ac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497004398 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_t
l_intg_err.1497004398
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.1309056704
Short name T293
Test name
Test status
Simulation time 481301540 ps
CPU time 0.86 seconds
Started Apr 23 01:20:07 PM PDT 24
Finished Apr 23 01:20:08 PM PDT 24
Peak memory 197256 kb
Host smart-2b5cb1ec-23a6-433e-8145-5342b7d7bb01
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309056704 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.1309056704
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.3464704407
Short name T50
Test name
Test status
Simulation time 326834801 ps
CPU time 0.75 seconds
Started Apr 23 01:20:07 PM PDT 24
Finished Apr 23 01:20:08 PM PDT 24
Peak memory 184244 kb
Host smart-e50eb13d-d282-4205-8d4a-a87f97003c60
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464704407 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.3464704407
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.2277435810
Short name T296
Test name
Test status
Simulation time 312407598 ps
CPU time 1 seconds
Started Apr 23 01:19:53 PM PDT 24
Finished Apr 23 01:19:55 PM PDT 24
Peak memory 183836 kb
Host smart-f9694faa-dec2-4912-a179-8db1d4c44fe8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277435810 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.2277435810
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.1645748132
Short name T70
Test name
Test status
Simulation time 2730207574 ps
CPU time 4.23 seconds
Started Apr 23 01:19:52 PM PDT 24
Finished Apr 23 01:19:56 PM PDT 24
Peak memory 184024 kb
Host smart-5c272693-6a11-40a8-af7e-a459d1ff2c40
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645748132 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.ao
n_timer_same_csr_outstanding.1645748132
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.1798133543
Short name T323
Test name
Test status
Simulation time 433044622 ps
CPU time 2.06 seconds
Started Apr 23 01:19:50 PM PDT 24
Finished Apr 23 01:19:52 PM PDT 24
Peak memory 198732 kb
Host smart-7a360143-8a35-4a79-884f-975f37fbd1c3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798133543 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.1798133543
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.1072292101
Short name T415
Test name
Test status
Simulation time 4046476483 ps
CPU time 3.89 seconds
Started Apr 23 01:19:51 PM PDT 24
Finished Apr 23 01:19:56 PM PDT 24
Peak memory 197884 kb
Host smart-1e535f31-0af4-4ef3-9a63-153e20ebc23b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072292101 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_t
l_intg_err.1072292101
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.4267007095
Short name T350
Test name
Test status
Simulation time 423937853 ps
CPU time 1.06 seconds
Started Apr 23 01:20:02 PM PDT 24
Finished Apr 23 01:20:04 PM PDT 24
Peak memory 197520 kb
Host smart-b68a1d16-8f1e-4694-a6fa-788cd0b9b546
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267007095 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.4267007095
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.2416448911
Short name T31
Test name
Test status
Simulation time 332163360 ps
CPU time 1.17 seconds
Started Apr 23 01:19:58 PM PDT 24
Finished Apr 23 01:20:00 PM PDT 24
Peak memory 183836 kb
Host smart-31a0e78b-d834-470f-aeb5-9e07c9ad6ea6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416448911 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.2416448911
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.3010959641
Short name T291
Test name
Test status
Simulation time 377126929 ps
CPU time 0.64 seconds
Started Apr 23 01:20:01 PM PDT 24
Finished Apr 23 01:20:02 PM PDT 24
Peak memory 183972 kb
Host smart-e38bbcee-a7a0-4e01-a6ce-cf1b082a5542
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010959641 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.3010959641
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.1851201380
Short name T64
Test name
Test status
Simulation time 1185656846 ps
CPU time 1.05 seconds
Started Apr 23 01:19:52 PM PDT 24
Finished Apr 23 01:19:53 PM PDT 24
Peak memory 193620 kb
Host smart-59dcc8f6-1486-4dbc-811b-c133db892cd2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851201380 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.ao
n_timer_same_csr_outstanding.1851201380
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.1986577411
Short name T387
Test name
Test status
Simulation time 959922079 ps
CPU time 1.9 seconds
Started Apr 23 01:19:54 PM PDT 24
Finished Apr 23 01:19:56 PM PDT 24
Peak memory 198816 kb
Host smart-cd941479-b44a-4431-acc3-2564f7e94d22
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986577411 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.1986577411
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.684597935
Short name T37
Test name
Test status
Simulation time 8340056819 ps
CPU time 14.49 seconds
Started Apr 23 01:19:52 PM PDT 24
Finished Apr 23 01:20:07 PM PDT 24
Peak memory 198092 kb
Host smart-b4db6b05-a6be-43a9-8104-c7c0c03dc9be
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684597935 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl
_intg_err.684597935
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.3700552554
Short name T382
Test name
Test status
Simulation time 482652108 ps
CPU time 0.77 seconds
Started Apr 23 01:19:52 PM PDT 24
Finished Apr 23 01:19:53 PM PDT 24
Peak memory 195804 kb
Host smart-453f4f29-7c0d-4798-a2b3-323fdad670cb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700552554 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.3700552554
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.242475001
Short name T393
Test name
Test status
Simulation time 526103953 ps
CPU time 1.38 seconds
Started Apr 23 01:20:01 PM PDT 24
Finished Apr 23 01:20:03 PM PDT 24
Peak memory 184260 kb
Host smart-3d345471-9459-42f3-929f-1a110f73e4fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242475001 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.242475001
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.369293092
Short name T344
Test name
Test status
Simulation time 449062530 ps
CPU time 1.2 seconds
Started Apr 23 01:20:00 PM PDT 24
Finished Apr 23 01:20:02 PM PDT 24
Peak memory 183972 kb
Host smart-5241507d-c83b-4f0f-81c2-28da42370ded
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369293092 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.369293092
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.431019286
Short name T69
Test name
Test status
Simulation time 1685642910 ps
CPU time 1.29 seconds
Started Apr 23 01:19:54 PM PDT 24
Finished Apr 23 01:19:56 PM PDT 24
Peak memory 193500 kb
Host smart-ea33d912-98a1-44fd-b38d-55ee99c446bf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431019286 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon
_timer_same_csr_outstanding.431019286
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.4262253632
Short name T320
Test name
Test status
Simulation time 468491250 ps
CPU time 2.06 seconds
Started Apr 23 01:19:54 PM PDT 24
Finished Apr 23 01:19:57 PM PDT 24
Peak memory 198752 kb
Host smart-b6980368-19d8-4b1e-931c-8591739e8a84
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262253632 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.4262253632
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.2027966408
Short name T96
Test name
Test status
Simulation time 8486926089 ps
CPU time 4.37 seconds
Started Apr 23 01:19:53 PM PDT 24
Finished Apr 23 01:19:58 PM PDT 24
Peak memory 198336 kb
Host smart-8abfc5ad-4077-40c4-b82f-7cd40627cc7f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027966408 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_t
l_intg_err.2027966408
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.3268868904
Short name T335
Test name
Test status
Simulation time 450387559 ps
CPU time 1.32 seconds
Started Apr 23 01:19:04 PM PDT 24
Finished Apr 23 01:19:06 PM PDT 24
Peak memory 193412 kb
Host smart-a8a5894f-37cc-44a8-9e73-b9f12de7542f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268868904 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_a
liasing.3268868904
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.3185621482
Short name T327
Test name
Test status
Simulation time 13945023253 ps
CPU time 21.69 seconds
Started Apr 23 01:19:03 PM PDT 24
Finished Apr 23 01:19:25 PM PDT 24
Peak memory 192440 kb
Host smart-1528bb86-70da-4d99-b4a0-427da44050bd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185621482 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_b
it_bash.3185621482
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.3323399236
Short name T367
Test name
Test status
Simulation time 1084145697 ps
CPU time 1.04 seconds
Started Apr 23 01:19:03 PM PDT 24
Finished Apr 23 01:19:05 PM PDT 24
Peak memory 183848 kb
Host smart-c86f7420-0914-495e-af8f-2c23d468c84d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323399236 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_h
w_reset.3323399236
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.975158948
Short name T409
Test name
Test status
Simulation time 455772588 ps
CPU time 1.37 seconds
Started Apr 23 01:19:07 PM PDT 24
Finished Apr 23 01:19:09 PM PDT 24
Peak memory 196460 kb
Host smart-7fe10550-ada2-4c91-aa65-fba00512fc6e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975158948 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.975158948
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.1730506249
Short name T378
Test name
Test status
Simulation time 355858193 ps
CPU time 0.74 seconds
Started Apr 23 01:19:03 PM PDT 24
Finished Apr 23 01:19:04 PM PDT 24
Peak memory 183832 kb
Host smart-67b98498-0baf-4603-9984-8e7650dec327
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730506249 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.1730506249
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.2516251912
Short name T337
Test name
Test status
Simulation time 358894329 ps
CPU time 0.67 seconds
Started Apr 23 01:18:56 PM PDT 24
Finished Apr 23 01:18:57 PM PDT 24
Peak memory 183820 kb
Host smart-3c382ce1-230a-48d4-9c5b-624b08c05f82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516251912 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.2516251912
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.1423289694
Short name T384
Test name
Test status
Simulation time 305566601 ps
CPU time 0.62 seconds
Started Apr 23 01:19:05 PM PDT 24
Finished Apr 23 01:19:06 PM PDT 24
Peak memory 183748 kb
Host smart-15d7f603-2b0e-4109-ac5d-61421d7364a1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423289694 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_t
imer_mem_partial_access.1423289694
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.441914912
Short name T364
Test name
Test status
Simulation time 343823378 ps
CPU time 0.77 seconds
Started Apr 23 01:19:00 PM PDT 24
Finished Apr 23 01:19:01 PM PDT 24
Peak memory 183760 kb
Host smart-71cbcd52-687b-4867-b6a2-b637987fd89b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441914912 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_wa
lk.441914912
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.2923982404
Short name T340
Test name
Test status
Simulation time 3123281460 ps
CPU time 1.75 seconds
Started Apr 23 01:19:04 PM PDT 24
Finished Apr 23 01:19:06 PM PDT 24
Peak memory 184028 kb
Host smart-97dae914-7433-4925-8f3f-4f7fa1f9f825
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923982404 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon
_timer_same_csr_outstanding.2923982404
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.358254908
Short name T342
Test name
Test status
Simulation time 556906302 ps
CPU time 2.16 seconds
Started Apr 23 01:18:57 PM PDT 24
Finished Apr 23 01:19:00 PM PDT 24
Peak memory 198776 kb
Host smart-ee24a64a-41c6-4fa9-a79e-67ce0d687007
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358254908 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.358254908
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.656572164
Short name T391
Test name
Test status
Simulation time 7727848153 ps
CPU time 3.23 seconds
Started Apr 23 01:19:00 PM PDT 24
Finished Apr 23 01:19:04 PM PDT 24
Peak memory 198236 kb
Host smart-1a602bf2-b0e2-430f-811a-6a8cbacde434
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656572164 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_
intg_err.656572164
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.2865540377
Short name T346
Test name
Test status
Simulation time 484237366 ps
CPU time 0.73 seconds
Started Apr 23 01:20:00 PM PDT 24
Finished Apr 23 01:20:02 PM PDT 24
Peak memory 183972 kb
Host smart-a1cf0908-6ef3-4398-9ddd-70ef0bcf7288
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865540377 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.2865540377
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.1858123571
Short name T349
Test name
Test status
Simulation time 399707764 ps
CPU time 1.15 seconds
Started Apr 23 01:19:56 PM PDT 24
Finished Apr 23 01:19:57 PM PDT 24
Peak memory 183820 kb
Host smart-0f6c8957-5389-47c0-8725-21259e57afb3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858123571 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.1858123571
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.316793461
Short name T285
Test name
Test status
Simulation time 329966125 ps
CPU time 1.04 seconds
Started Apr 23 01:19:57 PM PDT 24
Finished Apr 23 01:19:59 PM PDT 24
Peak memory 183876 kb
Host smart-6e35b7cd-6204-4622-8970-e2e2979deafc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316793461 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.316793461
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.1565382682
Short name T302
Test name
Test status
Simulation time 385445825 ps
CPU time 0.6 seconds
Started Apr 23 01:20:00 PM PDT 24
Finished Apr 23 01:20:01 PM PDT 24
Peak memory 183836 kb
Host smart-f382f7f1-a0b6-45df-a149-bcea31ac474b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565382682 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.1565382682
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.3682167006
Short name T282
Test name
Test status
Simulation time 366572985 ps
CPU time 0.68 seconds
Started Apr 23 01:20:00 PM PDT 24
Finished Apr 23 01:20:02 PM PDT 24
Peak memory 183908 kb
Host smart-cddd8dc4-8a6e-4f45-a8c1-cc14dc62a83d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682167006 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.3682167006
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.1444470424
Short name T359
Test name
Test status
Simulation time 480893128 ps
CPU time 1.3 seconds
Started Apr 23 01:19:56 PM PDT 24
Finished Apr 23 01:19:58 PM PDT 24
Peak memory 183832 kb
Host smart-7197e294-c785-4ad3-aa7a-b86def5abd83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444470424 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.1444470424
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.2659864344
Short name T306
Test name
Test status
Simulation time 490786456 ps
CPU time 1.27 seconds
Started Apr 23 01:20:01 PM PDT 24
Finished Apr 23 01:20:03 PM PDT 24
Peak memory 183836 kb
Host smart-a9876f3b-1373-49f1-9bcb-f56da0dcc99f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659864344 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.2659864344
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.2936074054
Short name T347
Test name
Test status
Simulation time 430837841 ps
CPU time 0.92 seconds
Started Apr 23 01:20:01 PM PDT 24
Finished Apr 23 01:20:03 PM PDT 24
Peak memory 183756 kb
Host smart-ddcbd437-09b3-48d3-956a-b06a58910ad3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936074054 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.2936074054
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.1596872075
Short name T355
Test name
Test status
Simulation time 527289489 ps
CPU time 0.75 seconds
Started Apr 23 01:19:59 PM PDT 24
Finished Apr 23 01:20:00 PM PDT 24
Peak memory 183816 kb
Host smart-45f0c382-8125-48ed-a6d9-8ddf5fc0cfb3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596872075 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.1596872075
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.4141826854
Short name T366
Test name
Test status
Simulation time 400760313 ps
CPU time 0.78 seconds
Started Apr 23 01:19:59 PM PDT 24
Finished Apr 23 01:20:00 PM PDT 24
Peak memory 183824 kb
Host smart-ceca7634-2137-4ec3-b7bf-999a6420716f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141826854 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.4141826854
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.837656395
Short name T310
Test name
Test status
Simulation time 627462959 ps
CPU time 1.12 seconds
Started Apr 23 01:19:14 PM PDT 24
Finished Apr 23 01:19:15 PM PDT 24
Peak memory 183992 kb
Host smart-1a828014-7c5c-4c88-a645-b779e463ebc4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837656395 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_al
iasing.837656395
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.3973511336
Short name T60
Test name
Test status
Simulation time 12681603387 ps
CPU time 50.7 seconds
Started Apr 23 01:19:13 PM PDT 24
Finished Apr 23 01:20:04 PM PDT 24
Peak memory 184136 kb
Host smart-2d393fbc-c596-4b1e-8a34-573fb323b1b3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973511336 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_b
it_bash.3973511336
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.3405353694
Short name T295
Test name
Test status
Simulation time 1311657143 ps
CPU time 0.87 seconds
Started Apr 23 01:19:12 PM PDT 24
Finished Apr 23 01:19:14 PM PDT 24
Peak memory 183828 kb
Host smart-21f9bc4d-03be-4104-a962-574ef21530fd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405353694 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_h
w_reset.3405353694
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.3400839235
Short name T292
Test name
Test status
Simulation time 559117951 ps
CPU time 1.48 seconds
Started Apr 23 01:19:17 PM PDT 24
Finished Apr 23 01:19:19 PM PDT 24
Peak memory 195600 kb
Host smart-e7c6a068-2303-492c-bca9-788950f248f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400839235 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.3400839235
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.291809802
Short name T372
Test name
Test status
Simulation time 362459230 ps
CPU time 1.14 seconds
Started Apr 23 01:19:09 PM PDT 24
Finished Apr 23 01:19:11 PM PDT 24
Peak memory 183928 kb
Host smart-e58e9715-2567-4c08-bcf9-c80a9a80380b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291809802 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.291809802
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.1055042925
Short name T400
Test name
Test status
Simulation time 397019800 ps
CPU time 0.81 seconds
Started Apr 23 01:19:12 PM PDT 24
Finished Apr 23 01:19:14 PM PDT 24
Peak memory 183876 kb
Host smart-b28a83c5-b695-4f8e-9346-d907f8dedfee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055042925 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.1055042925
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.2155531245
Short name T333
Test name
Test status
Simulation time 462243673 ps
CPU time 0.9 seconds
Started Apr 23 01:19:15 PM PDT 24
Finished Apr 23 01:19:16 PM PDT 24
Peak memory 183748 kb
Host smart-ac358729-cf4c-4780-8f9c-3a6bbfa44a85
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155531245 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_t
imer_mem_partial_access.2155531245
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.955706356
Short name T381
Test name
Test status
Simulation time 322166987 ps
CPU time 0.64 seconds
Started Apr 23 01:19:17 PM PDT 24
Finished Apr 23 01:19:18 PM PDT 24
Peak memory 183744 kb
Host smart-93e735ec-974e-4ed2-a075-1d837f267ac3
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955706356 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_wa
lk.955706356
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.1191511684
Short name T375
Test name
Test status
Simulation time 1021509120 ps
CPU time 2.09 seconds
Started Apr 23 01:19:16 PM PDT 24
Finished Apr 23 01:19:19 PM PDT 24
Peak memory 193336 kb
Host smart-1cf62baf-e0a8-4845-876c-52b46db1ba2d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191511684 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon
_timer_same_csr_outstanding.1191511684
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.3155734192
Short name T365
Test name
Test status
Simulation time 404508468 ps
CPU time 2.74 seconds
Started Apr 23 01:19:06 PM PDT 24
Finished Apr 23 01:19:10 PM PDT 24
Peak memory 198800 kb
Host smart-d577d5af-ff68-4d50-ac5a-cafa25df06e7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155734192 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.3155734192
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.3269235218
Short name T92
Test name
Test status
Simulation time 8698852314 ps
CPU time 15.14 seconds
Started Apr 23 01:19:12 PM PDT 24
Finished Apr 23 01:19:28 PM PDT 24
Peak memory 198268 kb
Host smart-4801835d-5b18-40e6-9d6b-aa91d9379486
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269235218 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl
_intg_err.3269235218
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.1546674706
Short name T352
Test name
Test status
Simulation time 478439703 ps
CPU time 0.89 seconds
Started Apr 23 01:19:59 PM PDT 24
Finished Apr 23 01:20:00 PM PDT 24
Peak memory 183820 kb
Host smart-f1c91569-27e7-4872-9e74-5685472a19dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546674706 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.1546674706
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.1239262774
Short name T309
Test name
Test status
Simulation time 455908859 ps
CPU time 1.06 seconds
Started Apr 23 01:20:00 PM PDT 24
Finished Apr 23 01:20:01 PM PDT 24
Peak memory 183776 kb
Host smart-a13a3d5a-55d4-44f8-8369-7620f3fe275e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239262774 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.1239262774
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.517614838
Short name T369
Test name
Test status
Simulation time 428155867 ps
CPU time 1.2 seconds
Started Apr 23 01:19:58 PM PDT 24
Finished Apr 23 01:19:59 PM PDT 24
Peak memory 183828 kb
Host smart-d9d7633e-611f-4fd0-8a83-8b15f1ee1a93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517614838 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.517614838
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.1977773722
Short name T289
Test name
Test status
Simulation time 507309588 ps
CPU time 0.73 seconds
Started Apr 23 01:20:00 PM PDT 24
Finished Apr 23 01:20:01 PM PDT 24
Peak memory 183908 kb
Host smart-50f64b43-1cdb-4d36-b3b5-e899beb9634f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977773722 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.1977773722
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.285680715
Short name T297
Test name
Test status
Simulation time 525192843 ps
CPU time 0.75 seconds
Started Apr 23 01:20:00 PM PDT 24
Finished Apr 23 01:20:01 PM PDT 24
Peak memory 183928 kb
Host smart-55b09321-d5f0-48a6-b7f3-52c66681f161
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285680715 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.285680715
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.2647009327
Short name T314
Test name
Test status
Simulation time 317912345 ps
CPU time 0.68 seconds
Started Apr 23 01:20:03 PM PDT 24
Finished Apr 23 01:20:04 PM PDT 24
Peak memory 183884 kb
Host smart-dd6a938a-1316-48a5-8cdb-d8a2845e1597
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647009327 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.2647009327
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.2547066007
Short name T284
Test name
Test status
Simulation time 314830484 ps
CPU time 1.03 seconds
Started Apr 23 01:20:13 PM PDT 24
Finished Apr 23 01:20:14 PM PDT 24
Peak memory 183808 kb
Host smart-9911a796-6a8b-4329-9cba-ed6961a82ce4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547066007 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.2547066007
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.3648163916
Short name T373
Test name
Test status
Simulation time 438504330 ps
CPU time 0.7 seconds
Started Apr 23 01:20:13 PM PDT 24
Finished Apr 23 01:20:14 PM PDT 24
Peak memory 183804 kb
Host smart-1ec9a115-4bc7-4056-a8ba-d774bea4228a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648163916 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.3648163916
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.64242711
Short name T392
Test name
Test status
Simulation time 403256673 ps
CPU time 0.71 seconds
Started Apr 23 01:20:03 PM PDT 24
Finished Apr 23 01:20:04 PM PDT 24
Peak memory 183796 kb
Host smart-aacbdd6e-aa96-46a0-958a-a4e3a6598f36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64242711 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.64242711
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.1491247325
Short name T330
Test name
Test status
Simulation time 444733021 ps
CPU time 1.21 seconds
Started Apr 23 01:20:15 PM PDT 24
Finished Apr 23 01:20:17 PM PDT 24
Peak memory 183804 kb
Host smart-c860dfd3-b955-47af-8125-5ec1c1ee5ec6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491247325 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.1491247325
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.1825385918
Short name T55
Test name
Test status
Simulation time 369990292 ps
CPU time 0.92 seconds
Started Apr 23 01:19:17 PM PDT 24
Finished Apr 23 01:19:19 PM PDT 24
Peak memory 183844 kb
Host smart-0702dcb9-ee97-4145-b84e-4613fe377639
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825385918 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_a
liasing.1825385918
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.966540586
Short name T414
Test name
Test status
Simulation time 7115460001 ps
CPU time 4.91 seconds
Started Apr 23 01:19:19 PM PDT 24
Finished Apr 23 01:19:25 PM PDT 24
Peak memory 184180 kb
Host smart-ba56b2c9-bf92-4fcb-9a2f-2e883469babc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966540586 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_bi
t_bash.966540586
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.4019518072
Short name T52
Test name
Test status
Simulation time 1012421998 ps
CPU time 1.43 seconds
Started Apr 23 01:19:21 PM PDT 24
Finished Apr 23 01:19:23 PM PDT 24
Peak memory 183872 kb
Host smart-3169909b-e3e5-4a6a-8d33-3cb5bf85e1b6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019518072 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_h
w_reset.4019518072
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.3460734459
Short name T374
Test name
Test status
Simulation time 479972854 ps
CPU time 0.97 seconds
Started Apr 23 01:19:19 PM PDT 24
Finished Apr 23 01:19:20 PM PDT 24
Peak memory 196148 kb
Host smart-fb249a39-d794-4624-ab96-3668b5e5e1bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460734459 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.3460734459
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.2923236010
Short name T59
Test name
Test status
Simulation time 315896580 ps
CPU time 0.66 seconds
Started Apr 23 01:19:19 PM PDT 24
Finished Apr 23 01:19:20 PM PDT 24
Peak memory 183820 kb
Host smart-9426848f-0d71-4209-9474-83b0bc23c710
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923236010 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.2923236010
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.3504613919
Short name T368
Test name
Test status
Simulation time 427848186 ps
CPU time 0.71 seconds
Started Apr 23 01:19:19 PM PDT 24
Finished Apr 23 01:19:20 PM PDT 24
Peak memory 183812 kb
Host smart-a53b9cd9-fcbb-409c-b934-8abbd710de32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504613919 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.3504613919
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.2847108480
Short name T294
Test name
Test status
Simulation time 280775257 ps
CPU time 0.94 seconds
Started Apr 23 01:19:24 PM PDT 24
Finished Apr 23 01:19:25 PM PDT 24
Peak memory 183760 kb
Host smart-f342c4ff-9508-4ce5-bc87-0b6bef34c18e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847108480 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_t
imer_mem_partial_access.2847108480
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.3238335190
Short name T376
Test name
Test status
Simulation time 345663948 ps
CPU time 1.05 seconds
Started Apr 23 01:19:18 PM PDT 24
Finished Apr 23 01:19:20 PM PDT 24
Peak memory 183756 kb
Host smart-9cb10727-66d7-485a-8564-fe8399b92dda
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238335190 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_w
alk.3238335190
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.2343183363
Short name T67
Test name
Test status
Simulation time 2595242767 ps
CPU time 1.73 seconds
Started Apr 23 01:19:17 PM PDT 24
Finished Apr 23 01:19:19 PM PDT 24
Peak memory 194524 kb
Host smart-05e9e9d2-b5ad-4d73-851b-9abd26ec129c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343183363 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon
_timer_same_csr_outstanding.2343183363
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.3150339080
Short name T339
Test name
Test status
Simulation time 464640563 ps
CPU time 2.02 seconds
Started Apr 23 01:19:14 PM PDT 24
Finished Apr 23 01:19:17 PM PDT 24
Peak memory 198780 kb
Host smart-abc79d96-3437-41f3-a2da-d5ff2bd9b666
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150339080 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.3150339080
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.1703641689
Short name T357
Test name
Test status
Simulation time 4477271446 ps
CPU time 2.72 seconds
Started Apr 23 01:19:14 PM PDT 24
Finished Apr 23 01:19:17 PM PDT 24
Peak memory 197456 kb
Host smart-7683f383-982a-43c9-85a3-daaddf467cef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703641689 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl
_intg_err.1703641689
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.945736231
Short name T363
Test name
Test status
Simulation time 328129302 ps
CPU time 0.76 seconds
Started Apr 23 01:20:11 PM PDT 24
Finished Apr 23 01:20:13 PM PDT 24
Peak memory 183808 kb
Host smart-05e89f07-5bb7-42aa-9ea2-062f2f725361
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945736231 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.945736231
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.1984555461
Short name T413
Test name
Test status
Simulation time 375820428 ps
CPU time 1.03 seconds
Started Apr 23 01:20:05 PM PDT 24
Finished Apr 23 01:20:07 PM PDT 24
Peak memory 183876 kb
Host smart-aa2947c3-e192-41be-b349-964a3bec8a21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984555461 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.1984555461
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.2361007942
Short name T404
Test name
Test status
Simulation time 300903606 ps
CPU time 0.65 seconds
Started Apr 23 01:20:04 PM PDT 24
Finished Apr 23 01:20:05 PM PDT 24
Peak memory 183784 kb
Host smart-b3166167-b0ab-4127-96f9-2b2122e8d8fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361007942 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.2361007942
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.3684718283
Short name T286
Test name
Test status
Simulation time 339777196 ps
CPU time 0.66 seconds
Started Apr 23 01:20:05 PM PDT 24
Finished Apr 23 01:20:06 PM PDT 24
Peak memory 183816 kb
Host smart-49cb0d10-a266-41de-aeb0-c4df5d88024d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684718283 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.3684718283
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.1326437746
Short name T395
Test name
Test status
Simulation time 504293362 ps
CPU time 0.94 seconds
Started Apr 23 01:20:15 PM PDT 24
Finished Apr 23 01:20:17 PM PDT 24
Peak memory 183692 kb
Host smart-fa5afcc5-4954-455e-8dea-755d1ac3ecf5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326437746 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.1326437746
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.2039776563
Short name T279
Test name
Test status
Simulation time 468926269 ps
CPU time 0.74 seconds
Started Apr 23 01:20:15 PM PDT 24
Finished Apr 23 01:20:17 PM PDT 24
Peak memory 183712 kb
Host smart-017a20b5-4267-484b-bb0b-c5fcab28f437
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039776563 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.2039776563
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.2109714543
Short name T383
Test name
Test status
Simulation time 523246013 ps
CPU time 0.77 seconds
Started Apr 23 01:20:02 PM PDT 24
Finished Apr 23 01:20:03 PM PDT 24
Peak memory 183832 kb
Host smart-970ce002-b1f4-4dcc-bdae-618f8853c2c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109714543 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.2109714543
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.3803294040
Short name T312
Test name
Test status
Simulation time 453716008 ps
CPU time 0.87 seconds
Started Apr 23 01:20:00 PM PDT 24
Finished Apr 23 01:20:01 PM PDT 24
Peak memory 183836 kb
Host smart-c0635f88-b6f2-486f-9a4b-78ab92c99ac3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803294040 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.3803294040
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.3065536409
Short name T299
Test name
Test status
Simulation time 431928995 ps
CPU time 0.67 seconds
Started Apr 23 01:20:02 PM PDT 24
Finished Apr 23 01:20:03 PM PDT 24
Peak memory 183836 kb
Host smart-a09c9fc4-e9fb-4214-bdc5-a745cb17403c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065536409 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.3065536409
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.1302138246
Short name T353
Test name
Test status
Simulation time 422708661 ps
CPU time 0.78 seconds
Started Apr 23 01:20:18 PM PDT 24
Finished Apr 23 01:20:20 PM PDT 24
Peak memory 183804 kb
Host smart-54e3c005-6ec9-4db1-9aa8-9b84eefe7588
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302138246 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.1302138246
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.1842755535
Short name T315
Test name
Test status
Simulation time 404477146 ps
CPU time 0.85 seconds
Started Apr 23 01:19:23 PM PDT 24
Finished Apr 23 01:19:24 PM PDT 24
Peak memory 195296 kb
Host smart-b78f84e9-5243-49f2-b3d9-ad09c9ecf646
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842755535 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.1842755535
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.3023844267
Short name T403
Test name
Test status
Simulation time 521145629 ps
CPU time 1.08 seconds
Started Apr 23 01:19:24 PM PDT 24
Finished Apr 23 01:19:26 PM PDT 24
Peak memory 183976 kb
Host smart-8007c590-5b01-4fa1-bab0-bafb0a1d27cf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023844267 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.3023844267
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.1155914542
Short name T288
Test name
Test status
Simulation time 431691263 ps
CPU time 1.16 seconds
Started Apr 23 01:19:24 PM PDT 24
Finished Apr 23 01:19:26 PM PDT 24
Peak memory 183784 kb
Host smart-7d696b89-ac30-4c17-a42d-11c9ff63ccc9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155914542 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.1155914542
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.3924322116
Short name T354
Test name
Test status
Simulation time 3297134492 ps
CPU time 2.07 seconds
Started Apr 23 01:19:23 PM PDT 24
Finished Apr 23 01:19:25 PM PDT 24
Peak memory 195220 kb
Host smart-ad3ef2d2-45b3-45d6-a276-398f8eba4139
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924322116 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon
_timer_same_csr_outstanding.3924322116
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.2004279226
Short name T356
Test name
Test status
Simulation time 411365127 ps
CPU time 1.23 seconds
Started Apr 23 01:19:18 PM PDT 24
Finished Apr 23 01:19:20 PM PDT 24
Peak memory 198852 kb
Host smart-a638d65f-1da1-4b0f-b4e3-38489adff4c3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004279226 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.2004279226
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.1952686576
Short name T416
Test name
Test status
Simulation time 8125238437 ps
CPU time 7.49 seconds
Started Apr 23 01:19:21 PM PDT 24
Finished Apr 23 01:19:29 PM PDT 24
Peak memory 198052 kb
Host smart-09a2bc61-7f63-49a9-8e00-fa2f7465486e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952686576 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl
_intg_err.1952686576
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.1581160539
Short name T338
Test name
Test status
Simulation time 397576715 ps
CPU time 1.13 seconds
Started Apr 23 01:19:23 PM PDT 24
Finished Apr 23 01:19:25 PM PDT 24
Peak memory 195760 kb
Host smart-98f2e4cc-ad3e-4763-b0c7-cd293bcb019f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581160539 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.1581160539
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.3253169661
Short name T57
Test name
Test status
Simulation time 324212815 ps
CPU time 0.84 seconds
Started Apr 23 01:19:23 PM PDT 24
Finished Apr 23 01:19:24 PM PDT 24
Peak memory 193208 kb
Host smart-24a4d71a-0a25-4a8d-92d6-b229f489e53c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253169661 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.3253169661
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.2484221079
Short name T280
Test name
Test status
Simulation time 299992447 ps
CPU time 0.89 seconds
Started Apr 23 01:19:25 PM PDT 24
Finished Apr 23 01:19:27 PM PDT 24
Peak memory 183816 kb
Host smart-ba3ed3ff-8aa3-43aa-9ea1-3807e8bd7cfa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484221079 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.2484221079
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.2236186195
Short name T410
Test name
Test status
Simulation time 2503260367 ps
CPU time 3.8 seconds
Started Apr 23 01:19:23 PM PDT 24
Finished Apr 23 01:19:28 PM PDT 24
Peak memory 194392 kb
Host smart-8b87cc38-33d4-4045-8879-13f7a6002ff4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236186195 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon
_timer_same_csr_outstanding.2236186195
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.1204980308
Short name T328
Test name
Test status
Simulation time 501037324 ps
CPU time 1.68 seconds
Started Apr 23 01:19:24 PM PDT 24
Finished Apr 23 01:19:26 PM PDT 24
Peak memory 197884 kb
Host smart-2b4aef8c-aedf-4bce-ba8b-c9a68bed355f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204980308 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.1204980308
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.491326069
Short name T417
Test name
Test status
Simulation time 590195145 ps
CPU time 0.95 seconds
Started Apr 23 01:19:27 PM PDT 24
Finished Apr 23 01:19:28 PM PDT 24
Peak memory 197116 kb
Host smart-07e18e64-335f-4900-8ea9-796bd6d6b9f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491326069 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.491326069
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.684062644
Short name T61
Test name
Test status
Simulation time 491964926 ps
CPU time 0.75 seconds
Started Apr 23 01:19:26 PM PDT 24
Finished Apr 23 01:19:28 PM PDT 24
Peak memory 183896 kb
Host smart-8754a168-35d2-4dc6-9b3c-a2da6e5abe8c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684062644 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.684062644
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.1799751777
Short name T318
Test name
Test status
Simulation time 499793284 ps
CPU time 0.7 seconds
Started Apr 23 01:19:28 PM PDT 24
Finished Apr 23 01:19:29 PM PDT 24
Peak memory 183880 kb
Host smart-092eafef-d84e-47d6-928d-4d5bdf30ebf3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799751777 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.1799751777
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.1559500216
Short name T33
Test name
Test status
Simulation time 1410790616 ps
CPU time 1.02 seconds
Started Apr 23 01:19:27 PM PDT 24
Finished Apr 23 01:19:29 PM PDT 24
Peak memory 193564 kb
Host smart-bad55ffc-4fa6-468b-a95c-5bffea959b85
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559500216 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon
_timer_same_csr_outstanding.1559500216
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.3083211646
Short name T348
Test name
Test status
Simulation time 316807849 ps
CPU time 1.66 seconds
Started Apr 23 01:19:21 PM PDT 24
Finished Apr 23 01:19:23 PM PDT 24
Peak memory 198788 kb
Host smart-16ef0372-0989-4f05-b575-c5a439e7620f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083211646 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.3083211646
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.2798441540
Short name T389
Test name
Test status
Simulation time 8555210353 ps
CPU time 14.59 seconds
Started Apr 23 01:19:30 PM PDT 24
Finished Apr 23 01:19:45 PM PDT 24
Peak memory 198160 kb
Host smart-be8f413d-f700-48ae-a99c-b2f692caba54
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798441540 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl
_intg_err.2798441540
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.2144363602
Short name T34
Test name
Test status
Simulation time 441519794 ps
CPU time 0.96 seconds
Started Apr 23 01:19:27 PM PDT 24
Finished Apr 23 01:19:29 PM PDT 24
Peak memory 195380 kb
Host smart-15ca347d-dd4b-4508-a168-3e01a2f805a9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144363602 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.2144363602
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.3234306673
Short name T326
Test name
Test status
Simulation time 400271365 ps
CPU time 0.73 seconds
Started Apr 23 01:19:29 PM PDT 24
Finished Apr 23 01:19:30 PM PDT 24
Peak memory 193272 kb
Host smart-c5073517-6109-4d3b-bd3f-b5523e02cbc7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234306673 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.3234306673
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.654654145
Short name T351
Test name
Test status
Simulation time 457461876 ps
CPU time 1.17 seconds
Started Apr 23 01:19:29 PM PDT 24
Finished Apr 23 01:19:31 PM PDT 24
Peak memory 183840 kb
Host smart-b436f6a6-9102-40f6-9418-b5c029334b28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654654145 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.654654145
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.2756757041
Short name T65
Test name
Test status
Simulation time 2635343629 ps
CPU time 4.01 seconds
Started Apr 23 01:19:28 PM PDT 24
Finished Apr 23 01:19:33 PM PDT 24
Peak memory 194960 kb
Host smart-22a57b47-daf6-4ff5-9fec-5c0b3decbb40
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756757041 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon
_timer_same_csr_outstanding.2756757041
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.187469380
Short name T324
Test name
Test status
Simulation time 591100912 ps
CPU time 1.74 seconds
Started Apr 23 01:19:31 PM PDT 24
Finished Apr 23 01:19:33 PM PDT 24
Peak memory 198768 kb
Host smart-54cff0da-d414-49bf-af87-cd8dad383f2c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187469380 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.187469380
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.1025138005
Short name T91
Test name
Test status
Simulation time 4276785577 ps
CPU time 4.89 seconds
Started Apr 23 01:19:26 PM PDT 24
Finished Apr 23 01:19:31 PM PDT 24
Peak memory 197696 kb
Host smart-1028e0a2-89ce-42cd-ac7d-0d423b4805a3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025138005 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl
_intg_err.1025138005
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.102369116
Short name T321
Test name
Test status
Simulation time 532306423 ps
CPU time 1.04 seconds
Started Apr 23 01:19:35 PM PDT 24
Finished Apr 23 01:19:36 PM PDT 24
Peak memory 195676 kb
Host smart-c43109fe-9cf0-4cd3-8699-cf21e25c0a85
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102369116 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.102369116
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.12905264
Short name T62
Test name
Test status
Simulation time 300813990 ps
CPU time 0.79 seconds
Started Apr 23 01:19:31 PM PDT 24
Finished Apr 23 01:19:32 PM PDT 24
Peak memory 193208 kb
Host smart-c8be122a-551d-4754-97cc-808bf0c3bed7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12905264 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.12905264
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.158125152
Short name T358
Test name
Test status
Simulation time 368922308 ps
CPU time 0.68 seconds
Started Apr 23 01:19:28 PM PDT 24
Finished Apr 23 01:19:30 PM PDT 24
Peak memory 183840 kb
Host smart-d5370c1e-59d6-41f3-89f4-6f9a89dd1146
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158125152 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.158125152
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.204774005
Short name T68
Test name
Test status
Simulation time 2826070807 ps
CPU time 4.46 seconds
Started Apr 23 01:19:31 PM PDT 24
Finished Apr 23 01:19:36 PM PDT 24
Peak memory 194724 kb
Host smart-87dfa8ed-9091-43c0-910d-41498e2d547d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204774005 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_
timer_same_csr_outstanding.204774005
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.1435334834
Short name T388
Test name
Test status
Simulation time 410788368 ps
CPU time 2.39 seconds
Started Apr 23 01:19:28 PM PDT 24
Finished Apr 23 01:19:31 PM PDT 24
Peak memory 198732 kb
Host smart-368a8943-b540-4c24-bb5b-702cd4cb5a98
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435334834 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.1435334834
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.101378198
Short name T316
Test name
Test status
Simulation time 8093918776 ps
CPU time 12.81 seconds
Started Apr 23 01:19:30 PM PDT 24
Finished Apr 23 01:19:43 PM PDT 24
Peak memory 198236 kb
Host smart-4cbd6c50-4fea-4613-add7-78f8953992a8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101378198 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_
intg_err.101378198
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_jump.938472692
Short name T24
Test name
Test status
Simulation time 459729227 ps
CPU time 0.73 seconds
Started Apr 23 02:13:48 PM PDT 24
Finished Apr 23 02:13:49 PM PDT 24
Peak memory 183296 kb
Host smart-c4598b86-276a-4817-8001-a28d46b08cc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938472692 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.938472692
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.1235991456
Short name T160
Test name
Test status
Simulation time 8227361171 ps
CPU time 3.54 seconds
Started Apr 23 02:13:53 PM PDT 24
Finished Apr 23 02:13:57 PM PDT 24
Peak memory 183372 kb
Host smart-63b8cce3-6f55-4f0d-8593-05d3b0a9eac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235991456 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.1235991456
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.2028216742
Short name T15
Test name
Test status
Simulation time 4327495667 ps
CPU time 6.42 seconds
Started Apr 23 02:13:51 PM PDT 24
Finished Apr 23 02:13:57 PM PDT 24
Peak memory 215136 kb
Host smart-1eeb16c0-25d2-4e3a-9bd3-3fe603df34a9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028216742 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.2028216742
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.2859823278
Short name T276
Test name
Test status
Simulation time 552349053 ps
CPU time 1.37 seconds
Started Apr 23 02:13:46 PM PDT 24
Finished Apr 23 02:13:47 PM PDT 24
Peak memory 183268 kb
Host smart-d3c52954-d2b4-4203-a79f-2ea300cb9b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859823278 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.2859823278
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.2441942945
Short name T25
Test name
Test status
Simulation time 170582983483 ps
CPU time 69.05 seconds
Started Apr 23 02:13:49 PM PDT 24
Finished Apr 23 02:14:59 PM PDT 24
Peak memory 183280 kb
Host smart-b52083f6-dd54-47c5-aea9-4cf87bb1b3da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441942945 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_a
ll.2441942945
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_jump.2508502307
Short name T76
Test name
Test status
Simulation time 484427697 ps
CPU time 1.35 seconds
Started Apr 23 02:13:49 PM PDT 24
Finished Apr 23 02:13:51 PM PDT 24
Peak memory 183244 kb
Host smart-e6e57421-83b1-4fc4-8a1f-aa5716293c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508502307 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.2508502307
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.2165733924
Short name T213
Test name
Test status
Simulation time 36582969347 ps
CPU time 30.78 seconds
Started Apr 23 02:13:52 PM PDT 24
Finished Apr 23 02:14:23 PM PDT 24
Peak memory 183372 kb
Host smart-c329add0-f58a-42f2-8136-a29b3174cb26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165733924 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.2165733924
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.2391242435
Short name T113
Test name
Test status
Simulation time 395422426 ps
CPU time 0.67 seconds
Started Apr 23 02:13:53 PM PDT 24
Finished Apr 23 02:13:54 PM PDT 24
Peak memory 183276 kb
Host smart-f2f9bbee-e4cd-45e1-b82a-78fc59c42a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391242435 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.2391242435
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_jump.2258551929
Short name T278
Test name
Test status
Simulation time 431180320 ps
CPU time 1.17 seconds
Started Apr 23 02:14:06 PM PDT 24
Finished Apr 23 02:14:07 PM PDT 24
Peak memory 183228 kb
Host smart-bf76c1c1-83b2-4e58-9e6e-af02a02d86fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258551929 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.2258551929
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.2458057815
Short name T8
Test name
Test status
Simulation time 36615522748 ps
CPU time 56.82 seconds
Started Apr 23 02:14:02 PM PDT 24
Finished Apr 23 02:14:59 PM PDT 24
Peak memory 183344 kb
Host smart-3f7f073f-ce1a-4834-a6c8-228712aecfc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458057815 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.2458057815
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.3790249525
Short name T175
Test name
Test status
Simulation time 534494452 ps
CPU time 0.94 seconds
Started Apr 23 02:14:01 PM PDT 24
Finished Apr 23 02:14:03 PM PDT 24
Peak memory 183212 kb
Host smart-1037ac0b-022e-4879-8edd-477bedcb7b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790249525 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.3790249525
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.3022090161
Short name T163
Test name
Test status
Simulation time 302398985699 ps
CPU time 271.74 seconds
Started Apr 23 02:14:06 PM PDT 24
Finished Apr 23 02:18:38 PM PDT 24
Peak memory 183308 kb
Host smart-d37a77e9-d7c6-48ee-8d1d-5409d4797d27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022090161 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_
all.3022090161
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_jump.4234465303
Short name T2
Test name
Test status
Simulation time 463208163 ps
CPU time 0.74 seconds
Started Apr 23 02:14:08 PM PDT 24
Finished Apr 23 02:14:10 PM PDT 24
Peak memory 183264 kb
Host smart-5db684cc-84c4-4050-8b47-ce6d12a8864f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234465303 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.4234465303
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.1995678793
Short name T116
Test name
Test status
Simulation time 11577224360 ps
CPU time 18.65 seconds
Started Apr 23 02:14:05 PM PDT 24
Finished Apr 23 02:14:25 PM PDT 24
Peak memory 183332 kb
Host smart-50652206-3f67-4787-84d6-c64fa064180a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995678793 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.1995678793
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.3175628241
Short name T114
Test name
Test status
Simulation time 397590637 ps
CPU time 0.68 seconds
Started Apr 23 02:14:06 PM PDT 24
Finished Apr 23 02:14:07 PM PDT 24
Peak memory 183272 kb
Host smart-c662971d-529e-4d9a-bcc3-7d15beb81676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175628241 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.3175628241
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.967818177
Short name T147
Test name
Test status
Simulation time 95693250719 ps
CPU time 148.34 seconds
Started Apr 23 02:14:03 PM PDT 24
Finished Apr 23 02:16:32 PM PDT 24
Peak memory 191488 kb
Host smart-c584f428-ac6e-4ae8-9480-c034f215724c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967818177 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_a
ll.967818177
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.1623207249
Short name T216
Test name
Test status
Simulation time 104717969840 ps
CPU time 739.08 seconds
Started Apr 23 02:14:06 PM PDT 24
Finished Apr 23 02:26:25 PM PDT 24
Peak memory 199908 kb
Host smart-3dc7ab5b-2e29-4cf4-b207-9a997009dacb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623207249 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand_reset.1623207249
Directory /workspace/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.aon_timer_jump.2149857569
Short name T173
Test name
Test status
Simulation time 480227123 ps
CPU time 1.2 seconds
Started Apr 23 02:14:09 PM PDT 24
Finished Apr 23 02:14:10 PM PDT 24
Peak memory 183300 kb
Host smart-345fe4b3-36dd-48d5-9af7-74737eca4e9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149857569 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.2149857569
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.2439427291
Short name T237
Test name
Test status
Simulation time 10289723219 ps
CPU time 14.26 seconds
Started Apr 23 02:14:04 PM PDT 24
Finished Apr 23 02:14:19 PM PDT 24
Peak memory 183364 kb
Host smart-06d5e45f-ab11-4c95-a9fd-0b0e892e4421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439427291 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.2439427291
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.3326768137
Short name T115
Test name
Test status
Simulation time 430451821 ps
CPU time 0.84 seconds
Started Apr 23 02:14:04 PM PDT 24
Finished Apr 23 02:14:05 PM PDT 24
Peak memory 183300 kb
Host smart-dff3129f-09cb-494c-8c2e-729de9ee2a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326768137 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.3326768137
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.1331891382
Short name T120
Test name
Test status
Simulation time 243684278324 ps
CPU time 40.45 seconds
Started Apr 23 02:14:09 PM PDT 24
Finished Apr 23 02:14:50 PM PDT 24
Peak memory 183516 kb
Host smart-ef0e8511-af43-4222-b009-38c62dd782a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331891382 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_
all.1331891382
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.1597931752
Short name T77
Test name
Test status
Simulation time 18740711812 ps
CPU time 129.35 seconds
Started Apr 23 02:14:09 PM PDT 24
Finished Apr 23 02:16:19 PM PDT 24
Peak memory 198276 kb
Host smart-9291e540-ff31-4ba7-8f67-c1f27a3cbd5e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597931752 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.1597931752
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_jump.2061675012
Short name T156
Test name
Test status
Simulation time 446574847 ps
CPU time 1.28 seconds
Started Apr 23 02:14:10 PM PDT 24
Finished Apr 23 02:14:12 PM PDT 24
Peak memory 183268 kb
Host smart-456f8a4c-8c6c-4920-9b1e-16c0bbcd9c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061675012 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.2061675012
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.1198184012
Short name T165
Test name
Test status
Simulation time 11019657909 ps
CPU time 18.77 seconds
Started Apr 23 02:14:10 PM PDT 24
Finished Apr 23 02:14:30 PM PDT 24
Peak memory 183372 kb
Host smart-29a9ddf8-91c2-4e54-befe-bed456f0739c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198184012 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.1198184012
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.2635809932
Short name T238
Test name
Test status
Simulation time 450922493 ps
CPU time 1.23 seconds
Started Apr 23 02:14:10 PM PDT 24
Finished Apr 23 02:14:12 PM PDT 24
Peak memory 183308 kb
Host smart-0370000a-6b2b-4663-ad48-29d4d4ffd32c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635809932 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.2635809932
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.3098004664
Short name T266
Test name
Test status
Simulation time 144974419311 ps
CPU time 241.94 seconds
Started Apr 23 02:14:08 PM PDT 24
Finished Apr 23 02:18:11 PM PDT 24
Peak memory 183248 kb
Host smart-d5a02632-0b2e-4bbe-b08d-cf501d7d1cd7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098004664 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_
all.3098004664
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.3274187662
Short name T12
Test name
Test status
Simulation time 43016294312 ps
CPU time 352.03 seconds
Started Apr 23 02:14:09 PM PDT 24
Finished Apr 23 02:20:01 PM PDT 24
Peak memory 198216 kb
Host smart-5677ad34-b41d-44f6-86fb-2b76b10f46fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274187662 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.3274187662
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.aon_timer_jump.3192909398
Short name T28
Test name
Test status
Simulation time 575006844 ps
CPU time 0.73 seconds
Started Apr 23 02:14:08 PM PDT 24
Finished Apr 23 02:14:09 PM PDT 24
Peak memory 183324 kb
Host smart-f008140a-af7f-45ab-a6de-8737df3f2818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192909398 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.3192909398
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.1865104164
Short name T229
Test name
Test status
Simulation time 28705020480 ps
CPU time 11.44 seconds
Started Apr 23 02:14:10 PM PDT 24
Finished Apr 23 02:14:22 PM PDT 24
Peak memory 183328 kb
Host smart-13271e7a-ac46-48e4-ac5d-438abc9a4e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865104164 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.1865104164
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.3292999060
Short name T142
Test name
Test status
Simulation time 387080605 ps
CPU time 0.62 seconds
Started Apr 23 02:14:07 PM PDT 24
Finished Apr 23 02:14:08 PM PDT 24
Peak memory 183288 kb
Host smart-8a363572-52a4-40e2-a342-b1a36acad8ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292999060 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.3292999060
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.365637596
Short name T144
Test name
Test status
Simulation time 151043789019 ps
CPU time 194.62 seconds
Started Apr 23 02:14:11 PM PDT 24
Finished Apr 23 02:17:26 PM PDT 24
Peak memory 195012 kb
Host smart-c14b226a-6f4a-4db9-8c80-07c6b2041751
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365637596 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_a
ll.365637596
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_jump.484433479
Short name T169
Test name
Test status
Simulation time 471367625 ps
CPU time 0.73 seconds
Started Apr 23 02:14:10 PM PDT 24
Finished Apr 23 02:14:11 PM PDT 24
Peak memory 183292 kb
Host smart-3fbf71ce-8fb1-44d6-9965-f4a135eb2ab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484433479 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.484433479
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.770970544
Short name T154
Test name
Test status
Simulation time 35735526621 ps
CPU time 53.61 seconds
Started Apr 23 02:14:11 PM PDT 24
Finished Apr 23 02:15:05 PM PDT 24
Peak memory 183372 kb
Host smart-d991ce7e-72f9-4672-b75d-8177582645fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770970544 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.770970544
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.3233090271
Short name T130
Test name
Test status
Simulation time 526589217 ps
CPU time 1.34 seconds
Started Apr 23 02:14:10 PM PDT 24
Finished Apr 23 02:14:12 PM PDT 24
Peak memory 183188 kb
Host smart-1c4e496c-f2a8-4bb4-b748-b74e0330c116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233090271 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.3233090271
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.2234244712
Short name T48
Test name
Test status
Simulation time 178665295968 ps
CPU time 40.35 seconds
Started Apr 23 02:14:13 PM PDT 24
Finished Apr 23 02:14:54 PM PDT 24
Peak memory 191528 kb
Host smart-a94c86cf-c06e-45a2-a0d5-627dd3c4ee0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234244712 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_
all.2234244712
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.3703459253
Short name T234
Test name
Test status
Simulation time 31033328117 ps
CPU time 114.03 seconds
Started Apr 23 02:14:14 PM PDT 24
Finished Apr 23 02:16:08 PM PDT 24
Peak memory 198232 kb
Host smart-cfa55896-1399-4986-b690-34ff866a9207
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703459253 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.3703459253
Directory /workspace/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.aon_timer_jump.2703951340
Short name T275
Test name
Test status
Simulation time 614404700 ps
CPU time 1.48 seconds
Started Apr 23 02:14:14 PM PDT 24
Finished Apr 23 02:14:16 PM PDT 24
Peak memory 183264 kb
Host smart-87f5a4d4-f9f4-4f15-97f6-07a23c79c61a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703951340 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.2703951340
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.1803614303
Short name T138
Test name
Test status
Simulation time 55717018398 ps
CPU time 13.64 seconds
Started Apr 23 02:14:14 PM PDT 24
Finished Apr 23 02:14:28 PM PDT 24
Peak memory 183308 kb
Host smart-aa72c5c7-c791-4ad9-9e00-5cd6c9ee0f5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803614303 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.1803614303
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.756631331
Short name T179
Test name
Test status
Simulation time 492356394 ps
CPU time 0.72 seconds
Started Apr 23 02:14:13 PM PDT 24
Finished Apr 23 02:14:14 PM PDT 24
Peak memory 183236 kb
Host smart-b555ab4d-639b-4761-84a5-3d0986743071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756631331 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.756631331
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.4149393176
Short name T161
Test name
Test status
Simulation time 147809804409 ps
CPU time 31.85 seconds
Started Apr 23 02:14:15 PM PDT 24
Finished Apr 23 02:14:47 PM PDT 24
Peak memory 193736 kb
Host smart-36377093-e324-45b1-bf0e-8b84412703f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149393176 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_
all.4149393176
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/17.aon_timer_jump.1914756710
Short name T103
Test name
Test status
Simulation time 536709993 ps
CPU time 0.99 seconds
Started Apr 23 02:14:14 PM PDT 24
Finished Apr 23 02:14:15 PM PDT 24
Peak memory 183312 kb
Host smart-09591264-6c2f-4b87-8a4e-9ecc2c97aa9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914756710 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.1914756710
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.4036282329
Short name T243
Test name
Test status
Simulation time 28081459835 ps
CPU time 3.84 seconds
Started Apr 23 02:14:14 PM PDT 24
Finished Apr 23 02:14:19 PM PDT 24
Peak memory 183308 kb
Host smart-c73a97dc-39d6-4af4-8d22-edcfee68c7fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036282329 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.4036282329
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.1486444047
Short name T72
Test name
Test status
Simulation time 522838799 ps
CPU time 0.76 seconds
Started Apr 23 02:14:13 PM PDT 24
Finished Apr 23 02:14:14 PM PDT 24
Peak memory 183212 kb
Host smart-cb76b793-0fa4-4d1f-8107-cba76da2d2b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486444047 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.1486444047
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.1012127759
Short name T47
Test name
Test status
Simulation time 134983363130 ps
CPU time 48.5 seconds
Started Apr 23 02:14:13 PM PDT 24
Finished Apr 23 02:15:02 PM PDT 24
Peak memory 183520 kb
Host smart-3e70c1fa-bb3c-4a51-bfc5-16e09bfd9bb9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012127759 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_
all.1012127759
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.1904351257
Short name T134
Test name
Test status
Simulation time 189275477920 ps
CPU time 177.63 seconds
Started Apr 23 02:14:14 PM PDT 24
Finished Apr 23 02:17:12 PM PDT 24
Peak memory 198280 kb
Host smart-abd0c342-51d9-4a82-adb3-e07581004c0b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904351257 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.1904351257
Directory /workspace/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.aon_timer_jump.3642038023
Short name T200
Test name
Test status
Simulation time 410416848 ps
CPU time 1.18 seconds
Started Apr 23 02:14:16 PM PDT 24
Finished Apr 23 02:14:18 PM PDT 24
Peak memory 183292 kb
Host smart-767d75e0-7807-4d99-9547-bce4ac0c9296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642038023 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.3642038023
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.2382923467
Short name T250
Test name
Test status
Simulation time 7361927125 ps
CPU time 12.82 seconds
Started Apr 23 02:14:17 PM PDT 24
Finished Apr 23 02:14:30 PM PDT 24
Peak memory 183304 kb
Host smart-63756cef-536b-49ff-8b8e-b900f42a0de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382923467 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.2382923467
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.3882880238
Short name T227
Test name
Test status
Simulation time 431334653 ps
CPU time 0.62 seconds
Started Apr 23 02:14:16 PM PDT 24
Finished Apr 23 02:14:17 PM PDT 24
Peak memory 183304 kb
Host smart-543b3c6d-3e61-4d3b-8c16-8f973db7b269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882880238 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.3882880238
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.3817117765
Short name T222
Test name
Test status
Simulation time 165783950520 ps
CPU time 99.85 seconds
Started Apr 23 02:14:16 PM PDT 24
Finished Apr 23 02:15:56 PM PDT 24
Peak memory 183352 kb
Host smart-e3e3ece6-7961-44f2-8f71-0ce686cb2a31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817117765 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_
all.3817117765
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_jump.2606830301
Short name T153
Test name
Test status
Simulation time 507735683 ps
CPU time 0.63 seconds
Started Apr 23 02:14:19 PM PDT 24
Finished Apr 23 02:14:20 PM PDT 24
Peak memory 183216 kb
Host smart-2247650f-b4c9-44a7-917b-46668cd9383a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606830301 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.2606830301
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.3561471237
Short name T145
Test name
Test status
Simulation time 32359039985 ps
CPU time 25.46 seconds
Started Apr 23 02:14:21 PM PDT 24
Finished Apr 23 02:14:47 PM PDT 24
Peak memory 183312 kb
Host smart-9bb21e17-66da-4dee-ad36-4afb5444e44f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561471237 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.3561471237
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.1165540237
Short name T211
Test name
Test status
Simulation time 380362816 ps
CPU time 1.13 seconds
Started Apr 23 02:14:18 PM PDT 24
Finished Apr 23 02:14:19 PM PDT 24
Peak memory 183248 kb
Host smart-9ce9f7c5-b107-4a27-ae4d-6f66e41652fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165540237 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.1165540237
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.460111349
Short name T272
Test name
Test status
Simulation time 73763924155 ps
CPU time 25.55 seconds
Started Apr 23 02:14:19 PM PDT 24
Finished Apr 23 02:14:46 PM PDT 24
Peak memory 183488 kb
Host smart-d9b54c65-505c-4163-8bce-dd4e9cd65d36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460111349 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_a
ll.460111349
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_jump.1009549793
Short name T107
Test name
Test status
Simulation time 460030434 ps
CPU time 0.84 seconds
Started Apr 23 02:13:53 PM PDT 24
Finished Apr 23 02:13:55 PM PDT 24
Peak memory 183224 kb
Host smart-f9d3c653-ccd2-4081-87a0-29e43a3bee31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009549793 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.1009549793
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.1385874764
Short name T190
Test name
Test status
Simulation time 33845686222 ps
CPU time 28.79 seconds
Started Apr 23 02:13:52 PM PDT 24
Finished Apr 23 02:14:22 PM PDT 24
Peak memory 183264 kb
Host smart-2d5ab0ad-43a3-4fcd-a9c8-24ca079dd4ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385874764 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.1385874764
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.89507156
Short name T16
Test name
Test status
Simulation time 7961170190 ps
CPU time 9.15 seconds
Started Apr 23 02:13:52 PM PDT 24
Finished Apr 23 02:14:02 PM PDT 24
Peak memory 215340 kb
Host smart-80855389-7ba3-4341-b1f6-ca5922e1aadc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89507156 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.89507156
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.250981874
Short name T215
Test name
Test status
Simulation time 473852318 ps
CPU time 0.65 seconds
Started Apr 23 02:13:56 PM PDT 24
Finished Apr 23 02:13:57 PM PDT 24
Peak memory 183268 kb
Host smart-962761ca-e6ea-455e-bca1-058cdbbd1270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250981874 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.250981874
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.3429718103
Short name T187
Test name
Test status
Simulation time 136500277881 ps
CPU time 110.35 seconds
Started Apr 23 02:13:56 PM PDT 24
Finished Apr 23 02:15:46 PM PDT 24
Peak memory 193748 kb
Host smart-1bc7fa85-bbc3-4af7-8bf2-bf7772aa75bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429718103 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_a
ll.3429718103
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.2984780407
Short name T10
Test name
Test status
Simulation time 44329431806 ps
CPU time 489.2 seconds
Started Apr 23 02:13:52 PM PDT 24
Finished Apr 23 02:22:02 PM PDT 24
Peak memory 198232 kb
Host smart-e4550584-d4f7-4e70-a001-48d05746b2fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984780407 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.2984780407
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.aon_timer_jump.969820002
Short name T30
Test name
Test status
Simulation time 419215767 ps
CPU time 0.67 seconds
Started Apr 23 02:14:20 PM PDT 24
Finished Apr 23 02:14:21 PM PDT 24
Peak memory 183300 kb
Host smart-77705930-7807-4dd9-9c5e-16c3f52f8dc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969820002 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.969820002
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.3620778937
Short name T225
Test name
Test status
Simulation time 52607285846 ps
CPU time 67.72 seconds
Started Apr 23 02:14:19 PM PDT 24
Finished Apr 23 02:15:27 PM PDT 24
Peak memory 183304 kb
Host smart-e50207dd-9a44-45bb-a48d-f976bb7f32ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620778937 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.3620778937
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.653555432
Short name T254
Test name
Test status
Simulation time 502465984 ps
CPU time 0.93 seconds
Started Apr 23 02:14:20 PM PDT 24
Finished Apr 23 02:14:22 PM PDT 24
Peak memory 183288 kb
Host smart-d7e827bd-514e-4f92-8926-69c2240a6fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653555432 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.653555432
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.2960127999
Short name T135
Test name
Test status
Simulation time 165341661279 ps
CPU time 253.21 seconds
Started Apr 23 02:14:22 PM PDT 24
Finished Apr 23 02:18:36 PM PDT 24
Peak memory 193152 kb
Host smart-8e319808-1c96-43b5-acd7-bd1e7996214d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960127999 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_
all.2960127999
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.4191849806
Short name T181
Test name
Test status
Simulation time 49853161495 ps
CPU time 344.78 seconds
Started Apr 23 02:14:19 PM PDT 24
Finished Apr 23 02:20:05 PM PDT 24
Peak memory 198224 kb
Host smart-b2a78649-96fd-4358-9eb5-c38befc63378
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191849806 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.4191849806
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_jump.1182680185
Short name T180
Test name
Test status
Simulation time 334378667 ps
CPU time 1.03 seconds
Started Apr 23 02:14:20 PM PDT 24
Finished Apr 23 02:14:21 PM PDT 24
Peak memory 183208 kb
Host smart-b4f3bd55-cdcc-4449-9d67-7ca9900e4499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182680185 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.1182680185
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.3433995995
Short name T121
Test name
Test status
Simulation time 19300153888 ps
CPU time 29.98 seconds
Started Apr 23 02:14:20 PM PDT 24
Finished Apr 23 02:14:51 PM PDT 24
Peak memory 183344 kb
Host smart-51f19120-b678-4667-97f1-7ce230ee6d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433995995 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.3433995995
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.1054938824
Short name T185
Test name
Test status
Simulation time 595945756 ps
CPU time 0.83 seconds
Started Apr 23 02:14:20 PM PDT 24
Finished Apr 23 02:14:21 PM PDT 24
Peak memory 183308 kb
Host smart-282fca53-23ba-446f-b323-5f0b9ef496f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054938824 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.1054938824
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.3635568432
Short name T49
Test name
Test status
Simulation time 103881203749 ps
CPU time 42.96 seconds
Started Apr 23 02:14:25 PM PDT 24
Finished Apr 23 02:15:08 PM PDT 24
Peak memory 195204 kb
Host smart-75d3b0e4-657d-4a70-b021-097872df3f48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635568432 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_
all.3635568432
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.3279770019
Short name T223
Test name
Test status
Simulation time 59439879282 ps
CPU time 122.11 seconds
Started Apr 23 02:14:21 PM PDT 24
Finished Apr 23 02:16:23 PM PDT 24
Peak memory 198348 kb
Host smart-d7b16482-1002-4ae9-a865-e008be5cecd1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279770019 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.3279770019
Directory /workspace/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.aon_timer_jump.3130653754
Short name T22
Test name
Test status
Simulation time 563304928 ps
CPU time 1.52 seconds
Started Apr 23 02:14:24 PM PDT 24
Finished Apr 23 02:14:26 PM PDT 24
Peak memory 183180 kb
Host smart-b82f2890-435d-4fe9-9aec-bdcb5e5ffb47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130653754 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.3130653754
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.1996352339
Short name T232
Test name
Test status
Simulation time 4544138353 ps
CPU time 0.96 seconds
Started Apr 23 02:14:23 PM PDT 24
Finished Apr 23 02:14:24 PM PDT 24
Peak memory 183352 kb
Host smart-b91d86db-b855-4ff8-a9e2-89f9bc082914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996352339 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.1996352339
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.297219261
Short name T174
Test name
Test status
Simulation time 380750748 ps
CPU time 1.12 seconds
Started Apr 23 02:14:25 PM PDT 24
Finished Apr 23 02:14:26 PM PDT 24
Peak memory 183256 kb
Host smart-02de4061-c761-41d3-baea-6ce5fb472ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297219261 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.297219261
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.83125299
Short name T27
Test name
Test status
Simulation time 81613646904 ps
CPU time 308.33 seconds
Started Apr 23 02:14:24 PM PDT 24
Finished Apr 23 02:19:33 PM PDT 24
Peak memory 198228 kb
Host smart-e483e147-cc7d-4b06-8942-a42c2e9d7895
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83125299 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.83125299
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.aon_timer_jump.1646177206
Short name T21
Test name
Test status
Simulation time 593897552 ps
CPU time 0.89 seconds
Started Apr 23 02:14:22 PM PDT 24
Finished Apr 23 02:14:23 PM PDT 24
Peak memory 183244 kb
Host smart-dc7a2254-6a99-47a0-9250-107d0d620edb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646177206 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.1646177206
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.3433330359
Short name T99
Test name
Test status
Simulation time 22836166988 ps
CPU time 16.44 seconds
Started Apr 23 02:14:24 PM PDT 24
Finished Apr 23 02:14:40 PM PDT 24
Peak memory 183316 kb
Host smart-5eb2cf6b-2fb9-4025-a2be-65c596313239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433330359 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.3433330359
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.338083574
Short name T262
Test name
Test status
Simulation time 530512402 ps
CPU time 0.84 seconds
Started Apr 23 02:14:24 PM PDT 24
Finished Apr 23 02:14:26 PM PDT 24
Peak memory 183272 kb
Host smart-0bcaeb6f-76c5-44fd-b2d8-2db8bcd46102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338083574 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.338083574
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.881390402
Short name T194
Test name
Test status
Simulation time 138581336286 ps
CPU time 238.9 seconds
Started Apr 23 02:14:24 PM PDT 24
Finished Apr 23 02:18:23 PM PDT 24
Peak memory 183432 kb
Host smart-50d07783-35c8-4688-a9d4-708c4f6731c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881390402 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_a
ll.881390402
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_jump.329738873
Short name T247
Test name
Test status
Simulation time 583700412 ps
CPU time 1.41 seconds
Started Apr 23 02:14:28 PM PDT 24
Finished Apr 23 02:14:30 PM PDT 24
Peak memory 183300 kb
Host smart-92feca7f-d9fd-4806-b0cf-2fef682f9c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329738873 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.329738873
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.564502373
Short name T183
Test name
Test status
Simulation time 31132698500 ps
CPU time 41.88 seconds
Started Apr 23 02:14:26 PM PDT 24
Finished Apr 23 02:15:08 PM PDT 24
Peak memory 183372 kb
Host smart-05597be2-cd79-4548-98d3-38a90962a83e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564502373 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.564502373
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.1292987235
Short name T260
Test name
Test status
Simulation time 384282923 ps
CPU time 1.16 seconds
Started Apr 23 02:14:24 PM PDT 24
Finished Apr 23 02:14:26 PM PDT 24
Peak memory 183212 kb
Host smart-cdc80626-f651-459f-aabe-75b05d2e9cce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292987235 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.1292987235
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.272763687
Short name T249
Test name
Test status
Simulation time 141561380951 ps
CPU time 52.76 seconds
Started Apr 23 02:14:28 PM PDT 24
Finished Apr 23 02:15:21 PM PDT 24
Peak memory 192688 kb
Host smart-a21223a7-f0bd-472d-bb63-bbf45d18cd83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272763687 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_a
ll.272763687
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.3615503551
Short name T78
Test name
Test status
Simulation time 37120341742 ps
CPU time 147.32 seconds
Started Apr 23 02:14:29 PM PDT 24
Finished Apr 23 02:16:57 PM PDT 24
Peak memory 198276 kb
Host smart-b0d95321-0cae-41e9-bd56-5aec970b57d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615503551 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand_reset.3615503551
Directory /workspace/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.aon_timer_jump.2482663944
Short name T220
Test name
Test status
Simulation time 508186945 ps
CPU time 0.67 seconds
Started Apr 23 02:14:30 PM PDT 24
Finished Apr 23 02:14:31 PM PDT 24
Peak memory 183296 kb
Host smart-10259b7f-a598-45fd-9e3b-9d8b5e198f53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482663944 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.2482663944
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.1183306648
Short name T106
Test name
Test status
Simulation time 35455076689 ps
CPU time 55.56 seconds
Started Apr 23 02:14:30 PM PDT 24
Finished Apr 23 02:15:26 PM PDT 24
Peak memory 183364 kb
Host smart-4d82443f-ef22-48c8-b868-a846ba54516c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183306648 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.1183306648
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.3000808532
Short name T202
Test name
Test status
Simulation time 559809038 ps
CPU time 1 seconds
Started Apr 23 02:14:29 PM PDT 24
Finished Apr 23 02:14:31 PM PDT 24
Peak memory 182984 kb
Host smart-ec179365-64f1-44d5-81e4-185c180813bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000808532 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.3000808532
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.981796819
Short name T149
Test name
Test status
Simulation time 57211567690 ps
CPU time 23.48 seconds
Started Apr 23 02:14:26 PM PDT 24
Finished Apr 23 02:14:50 PM PDT 24
Peak memory 183288 kb
Host smart-2ed5dbf0-73be-4564-b09a-0d9d98a3bf45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981796819 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_a
ll.981796819
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_jump.1286984556
Short name T166
Test name
Test status
Simulation time 348466726 ps
CPU time 1 seconds
Started Apr 23 02:14:28 PM PDT 24
Finished Apr 23 02:14:29 PM PDT 24
Peak memory 183260 kb
Host smart-4b5e042f-857d-4663-bf87-c0ab6b14825b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286984556 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.1286984556
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.698768333
Short name T127
Test name
Test status
Simulation time 58644595520 ps
CPU time 83.78 seconds
Started Apr 23 02:14:29 PM PDT 24
Finished Apr 23 02:15:53 PM PDT 24
Peak memory 183344 kb
Host smart-91fe3203-13c2-4021-a729-4b2a47525daf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698768333 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.698768333
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.1427211589
Short name T261
Test name
Test status
Simulation time 410395504 ps
CPU time 1.22 seconds
Started Apr 23 02:14:27 PM PDT 24
Finished Apr 23 02:14:29 PM PDT 24
Peak memory 183212 kb
Host smart-ba8ca7bb-7e84-4c3c-bfa3-efdee19e2268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427211589 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.1427211589
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.1868910821
Short name T155
Test name
Test status
Simulation time 128867797980 ps
CPU time 179.8 seconds
Started Apr 23 02:14:30 PM PDT 24
Finished Apr 23 02:17:30 PM PDT 24
Peak memory 183304 kb
Host smart-78d9c9ac-21c2-4d1c-b3a1-7d2f257dcba4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868910821 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_
all.1868910821
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.3901268041
Short name T43
Test name
Test status
Simulation time 32751369728 ps
CPU time 254.08 seconds
Started Apr 23 02:14:30 PM PDT 24
Finished Apr 23 02:18:45 PM PDT 24
Peak memory 198320 kb
Host smart-91f44fa1-6692-4a06-9394-23e330edabe5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901268041 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.3901268041
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_jump.1477097925
Short name T110
Test name
Test status
Simulation time 452890838 ps
CPU time 0.72 seconds
Started Apr 23 02:14:28 PM PDT 24
Finished Apr 23 02:14:29 PM PDT 24
Peak memory 183304 kb
Host smart-e92505f9-dc35-4288-a9ce-66b90dd2bfe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477097925 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.1477097925
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.2801930154
Short name T74
Test name
Test status
Simulation time 35631055308 ps
CPU time 28.24 seconds
Started Apr 23 02:14:27 PM PDT 24
Finished Apr 23 02:14:56 PM PDT 24
Peak memory 183276 kb
Host smart-a5698dd0-9c18-4a46-92d2-c973da065fca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801930154 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.2801930154
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.3100608405
Short name T167
Test name
Test status
Simulation time 409476387 ps
CPU time 0.87 seconds
Started Apr 23 02:14:29 PM PDT 24
Finished Apr 23 02:14:31 PM PDT 24
Peak memory 183212 kb
Host smart-4bacfee4-326d-4882-9f8b-8db39d82a073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100608405 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.3100608405
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.2386975126
Short name T105
Test name
Test status
Simulation time 27689055645 ps
CPU time 46.4 seconds
Started Apr 23 02:14:28 PM PDT 24
Finished Apr 23 02:15:15 PM PDT 24
Peak memory 183328 kb
Host smart-07bb7037-a4dd-4af7-8e50-c517a512c3f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386975126 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_
all.2386975126
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.3549697263
Short name T214
Test name
Test status
Simulation time 104864516288 ps
CPU time 226.17 seconds
Started Apr 23 02:14:29 PM PDT 24
Finished Apr 23 02:18:15 PM PDT 24
Peak memory 198248 kb
Host smart-35a9cf58-7e16-4fbd-b427-85d165652881
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549697263 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.3549697263
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_jump.970134207
Short name T271
Test name
Test status
Simulation time 393889047 ps
CPU time 1.21 seconds
Started Apr 23 02:14:30 PM PDT 24
Finished Apr 23 02:14:31 PM PDT 24
Peak memory 183296 kb
Host smart-4fa2357d-e022-41d9-be8b-2e669fdac8a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970134207 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.970134207
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.1693914661
Short name T126
Test name
Test status
Simulation time 12376490630 ps
CPU time 18.8 seconds
Started Apr 23 02:14:29 PM PDT 24
Finished Apr 23 02:14:49 PM PDT 24
Peak memory 182964 kb
Host smart-082d3038-0662-4b4a-9b06-a8d1134f679f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693914661 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.1693914661
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.2377475697
Short name T259
Test name
Test status
Simulation time 619208674 ps
CPU time 0.71 seconds
Started Apr 23 02:14:30 PM PDT 24
Finished Apr 23 02:14:32 PM PDT 24
Peak memory 183296 kb
Host smart-b0bcf019-971c-4be3-993d-b6dbbd38a474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377475697 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.2377475697
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.2812585245
Short name T177
Test name
Test status
Simulation time 18269898511 ps
CPU time 7.27 seconds
Started Apr 23 02:14:31 PM PDT 24
Finished Apr 23 02:14:39 PM PDT 24
Peak memory 183344 kb
Host smart-ccbd0f0e-52be-47cc-a166-8049c2c55aff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812585245 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_
all.2812585245
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.3002094386
Short name T240
Test name
Test status
Simulation time 42918141444 ps
CPU time 469.1 seconds
Started Apr 23 02:14:32 PM PDT 24
Finished Apr 23 02:22:22 PM PDT 24
Peak memory 198228 kb
Host smart-7ecab5c8-12c3-4f44-ad31-03f4c1ac8a0a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002094386 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.3002094386
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.aon_timer_jump.3798577354
Short name T164
Test name
Test status
Simulation time 627367153 ps
CPU time 0.61 seconds
Started Apr 23 02:14:35 PM PDT 24
Finished Apr 23 02:14:36 PM PDT 24
Peak memory 183308 kb
Host smart-12d8114a-f507-439d-9389-a124a71eb03f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798577354 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.3798577354
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.3229569285
Short name T9
Test name
Test status
Simulation time 7098263306 ps
CPU time 11.44 seconds
Started Apr 23 02:14:30 PM PDT 24
Finished Apr 23 02:14:43 PM PDT 24
Peak memory 183356 kb
Host smart-e3ca5806-2177-40de-8b6a-fffd9c88d961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229569285 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.3229569285
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.2778470746
Short name T205
Test name
Test status
Simulation time 487325711 ps
CPU time 0.62 seconds
Started Apr 23 02:14:32 PM PDT 24
Finished Apr 23 02:14:33 PM PDT 24
Peak memory 183264 kb
Host smart-28358ee8-eb37-4370-b822-c8887fc9d3bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778470746 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.2778470746
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.3533510383
Short name T18
Test name
Test status
Simulation time 95281469820 ps
CPU time 24.86 seconds
Started Apr 23 02:14:36 PM PDT 24
Finished Apr 23 02:15:01 PM PDT 24
Peak memory 183360 kb
Host smart-98b21fa0-e448-41ad-9638-638f1fe12346
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533510383 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_
all.3533510383
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.1783423140
Short name T81
Test name
Test status
Simulation time 109257721727 ps
CPU time 407.19 seconds
Started Apr 23 02:14:32 PM PDT 24
Finished Apr 23 02:21:19 PM PDT 24
Peak memory 198220 kb
Host smart-46e7e91f-f769-4e73-973c-3f2ae29a3ad3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783423140 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.1783423140
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.aon_timer_jump.503066491
Short name T140
Test name
Test status
Simulation time 399524007 ps
CPU time 0.89 seconds
Started Apr 23 02:13:57 PM PDT 24
Finished Apr 23 02:13:59 PM PDT 24
Peak memory 183200 kb
Host smart-074f6085-f31c-4b87-8a81-b236c85e4bdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503066491 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.503066491
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.2761451683
Short name T88
Test name
Test status
Simulation time 29326915632 ps
CPU time 23.23 seconds
Started Apr 23 02:13:53 PM PDT 24
Finished Apr 23 02:14:17 PM PDT 24
Peak memory 183248 kb
Host smart-aa30ab3d-f8e6-4b44-8316-fd7d5c1ae2fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761451683 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.2761451683
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.436221138
Short name T20
Test name
Test status
Simulation time 7741504383 ps
CPU time 3.64 seconds
Started Apr 23 02:13:57 PM PDT 24
Finished Apr 23 02:14:02 PM PDT 24
Peak memory 215196 kb
Host smart-0401dddf-972f-4b6a-9736-9e7af774d7b9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436221138 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.436221138
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.1688985737
Short name T100
Test name
Test status
Simulation time 597300605 ps
CPU time 0.66 seconds
Started Apr 23 02:13:54 PM PDT 24
Finished Apr 23 02:13:55 PM PDT 24
Peak memory 183252 kb
Host smart-8e69a18c-66a2-4825-a8b5-0831c78d98b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688985737 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.1688985737
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.3249439889
Short name T274
Test name
Test status
Simulation time 32718809840 ps
CPU time 48.93 seconds
Started Apr 23 02:13:53 PM PDT 24
Finished Apr 23 02:14:43 PM PDT 24
Peak memory 183296 kb
Host smart-1d174715-3864-4d9e-86b7-08731bf0023b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249439889 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_a
ll.3249439889
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.283525695
Short name T195
Test name
Test status
Simulation time 130442197259 ps
CPU time 152.81 seconds
Started Apr 23 02:13:54 PM PDT 24
Finished Apr 23 02:16:28 PM PDT 24
Peak memory 198316 kb
Host smart-79e9bcf7-196b-4909-8909-3ddddc7aa0ce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283525695 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.283525695
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_jump.2503630181
Short name T265
Test name
Test status
Simulation time 416866809 ps
CPU time 1.23 seconds
Started Apr 23 02:14:36 PM PDT 24
Finished Apr 23 02:14:38 PM PDT 24
Peak memory 183308 kb
Host smart-180bd9b4-5f07-4d86-94fe-c5a80c28db90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503630181 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.2503630181
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.3649240786
Short name T123
Test name
Test status
Simulation time 12359232641 ps
CPU time 2.52 seconds
Started Apr 23 02:14:33 PM PDT 24
Finished Apr 23 02:14:36 PM PDT 24
Peak memory 183360 kb
Host smart-e910fe09-1dbc-4791-a1ac-74198e5360ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649240786 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.3649240786
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.2338537428
Short name T125
Test name
Test status
Simulation time 417052034 ps
CPU time 1.11 seconds
Started Apr 23 02:14:34 PM PDT 24
Finished Apr 23 02:14:35 PM PDT 24
Peak memory 183308 kb
Host smart-f10a971b-5c2e-463a-b791-7f7e968c59cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338537428 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.2338537428
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.618806654
Short name T258
Test name
Test status
Simulation time 129536950729 ps
CPU time 222.76 seconds
Started Apr 23 02:14:35 PM PDT 24
Finished Apr 23 02:18:18 PM PDT 24
Peak memory 183380 kb
Host smart-54b193d5-2c89-47b6-b2ee-fff7903561af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618806654 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_a
ll.618806654
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.159851671
Short name T80
Test name
Test status
Simulation time 134120347854 ps
CPU time 230.76 seconds
Started Apr 23 02:14:30 PM PDT 24
Finished Apr 23 02:18:21 PM PDT 24
Peak memory 198236 kb
Host smart-8ac2637c-b012-4378-8e93-040d0470fc90
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159851671 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.159851671
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.aon_timer_jump.964406059
Short name T189
Test name
Test status
Simulation time 381072272 ps
CPU time 0.78 seconds
Started Apr 23 02:14:34 PM PDT 24
Finished Apr 23 02:14:35 PM PDT 24
Peak memory 183224 kb
Host smart-526b2b74-357f-4eff-9cf4-1549210cd1dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964406059 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.964406059
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.120796960
Short name T186
Test name
Test status
Simulation time 46512551252 ps
CPU time 17.59 seconds
Started Apr 23 02:14:31 PM PDT 24
Finished Apr 23 02:14:49 PM PDT 24
Peak memory 183352 kb
Host smart-2aa294d0-8544-4a32-a6e3-b7bb3f895bad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120796960 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.120796960
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.2368089821
Short name T122
Test name
Test status
Simulation time 569642804 ps
CPU time 0.62 seconds
Started Apr 23 02:14:33 PM PDT 24
Finished Apr 23 02:14:33 PM PDT 24
Peak memory 183248 kb
Host smart-d8a25e63-edfd-4730-83f0-fce0c85a1bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368089821 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.2368089821
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_jump.1984891014
Short name T270
Test name
Test status
Simulation time 446226951 ps
CPU time 0.84 seconds
Started Apr 23 02:14:36 PM PDT 24
Finished Apr 23 02:14:37 PM PDT 24
Peak memory 183304 kb
Host smart-e022f7d4-63b8-4e2a-8354-208a9c2f2628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984891014 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.1984891014
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.2653732862
Short name T6
Test name
Test status
Simulation time 16022831799 ps
CPU time 5.8 seconds
Started Apr 23 02:14:31 PM PDT 24
Finished Apr 23 02:14:37 PM PDT 24
Peak memory 183332 kb
Host smart-67a78b86-65b7-4748-8418-d2c6074d583b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653732862 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.2653732862
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.1686153004
Short name T244
Test name
Test status
Simulation time 595057687 ps
CPU time 0.73 seconds
Started Apr 23 02:14:33 PM PDT 24
Finished Apr 23 02:14:34 PM PDT 24
Peak memory 183268 kb
Host smart-1c1673fd-6142-43fb-8f0f-2258f2020dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686153004 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.1686153004
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.1805481807
Short name T108
Test name
Test status
Simulation time 19564013756 ps
CPU time 18.56 seconds
Started Apr 23 02:14:37 PM PDT 24
Finished Apr 23 02:14:56 PM PDT 24
Peak memory 194140 kb
Host smart-a5185162-355d-45c3-a85f-29333a847bbc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805481807 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_
all.1805481807
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.2630587101
Short name T208
Test name
Test status
Simulation time 76193229246 ps
CPU time 643.35 seconds
Started Apr 23 02:14:35 PM PDT 24
Finished Apr 23 02:25:19 PM PDT 24
Peak memory 198992 kb
Host smart-b1dc1d67-c4aa-4d95-97f5-44fadcd5e97b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630587101 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_reset.2630587101
Directory /workspace/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.aon_timer_jump.10373199
Short name T209
Test name
Test status
Simulation time 544672914 ps
CPU time 1.37 seconds
Started Apr 23 02:14:38 PM PDT 24
Finished Apr 23 02:14:40 PM PDT 24
Peak memory 183300 kb
Host smart-856ab836-355a-4184-8207-b70fe0870907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10373199 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.10373199
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.313108338
Short name T4
Test name
Test status
Simulation time 39525916205 ps
CPU time 11.22 seconds
Started Apr 23 02:14:35 PM PDT 24
Finished Apr 23 02:14:47 PM PDT 24
Peak memory 183304 kb
Host smart-398a4916-584e-4597-8b62-ea9602d0491a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313108338 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.313108338
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.300105689
Short name T13
Test name
Test status
Simulation time 389138045 ps
CPU time 1.07 seconds
Started Apr 23 02:14:37 PM PDT 24
Finished Apr 23 02:14:38 PM PDT 24
Peak memory 183304 kb
Host smart-f62f8d13-963b-47f2-a671-15dc638f5b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300105689 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.300105689
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.3492873278
Short name T90
Test name
Test status
Simulation time 252412960432 ps
CPU time 151.98 seconds
Started Apr 23 02:14:36 PM PDT 24
Finished Apr 23 02:17:09 PM PDT 24
Peak memory 194784 kb
Host smart-442dbb08-581f-404d-9d27-e400c027b401
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492873278 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_
all.3492873278
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_jump.371073631
Short name T198
Test name
Test status
Simulation time 486026644 ps
CPU time 1.27 seconds
Started Apr 23 02:14:38 PM PDT 24
Finished Apr 23 02:14:40 PM PDT 24
Peak memory 183248 kb
Host smart-8645c3f7-2980-436a-89da-bccbc88bffd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371073631 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.371073631
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.3243508986
Short name T101
Test name
Test status
Simulation time 33040586132 ps
CPU time 6.81 seconds
Started Apr 23 02:14:36 PM PDT 24
Finished Apr 23 02:14:44 PM PDT 24
Peak memory 183284 kb
Host smart-22834aa8-e0eb-49d4-b67e-7cf312d3a0c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243508986 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.3243508986
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.1251474131
Short name T188
Test name
Test status
Simulation time 343607962 ps
CPU time 1.08 seconds
Started Apr 23 02:14:35 PM PDT 24
Finished Apr 23 02:14:37 PM PDT 24
Peak memory 183280 kb
Host smart-ee0067cc-a574-4256-ae60-372482747caa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251474131 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.1251474131
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.469033613
Short name T159
Test name
Test status
Simulation time 24204740564 ps
CPU time 23.41 seconds
Started Apr 23 02:14:37 PM PDT 24
Finished Apr 23 02:15:01 PM PDT 24
Peak memory 194652 kb
Host smart-c0fa1b29-6a08-4ccb-a962-f5f2b6b444b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469033613 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_a
ll.469033613
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.106323580
Short name T269
Test name
Test status
Simulation time 54452971652 ps
CPU time 562.28 seconds
Started Apr 23 02:14:39 PM PDT 24
Finished Apr 23 02:24:01 PM PDT 24
Peak memory 198284 kb
Host smart-1ea5f302-14db-4bcd-82e2-ad9b1bdb3d05
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106323580 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.106323580
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.aon_timer_jump.2671316999
Short name T219
Test name
Test status
Simulation time 354831532 ps
CPU time 1.05 seconds
Started Apr 23 02:14:38 PM PDT 24
Finished Apr 23 02:14:40 PM PDT 24
Peak memory 183224 kb
Host smart-2eec4371-f1af-4c6d-9c88-8a5330483771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671316999 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.2671316999
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.4109279124
Short name T133
Test name
Test status
Simulation time 55159974212 ps
CPU time 90.08 seconds
Started Apr 23 02:14:40 PM PDT 24
Finished Apr 23 02:16:10 PM PDT 24
Peak memory 183308 kb
Host smart-43678892-7a0d-44eb-857a-de354150f11f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109279124 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.4109279124
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.393619309
Short name T221
Test name
Test status
Simulation time 500920193 ps
CPU time 1.32 seconds
Started Apr 23 02:14:38 PM PDT 24
Finished Apr 23 02:14:40 PM PDT 24
Peak memory 183288 kb
Host smart-3ad153d8-2811-438e-90cf-9d01631c28e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393619309 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.393619309
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.1624772902
Short name T29
Test name
Test status
Simulation time 154287143946 ps
CPU time 225.19 seconds
Started Apr 23 02:14:42 PM PDT 24
Finished Apr 23 02:18:28 PM PDT 24
Peak memory 194888 kb
Host smart-3befd7a8-3e67-4854-940a-8d7a3a96154c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624772902 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_
all.1624772902
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_jump.3865415003
Short name T236
Test name
Test status
Simulation time 516780969 ps
CPU time 0.73 seconds
Started Apr 23 02:14:50 PM PDT 24
Finished Apr 23 02:14:51 PM PDT 24
Peak memory 183312 kb
Host smart-b42044b5-9faa-4b5b-9048-904ae26fc670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865415003 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.3865415003
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.3741027487
Short name T228
Test name
Test status
Simulation time 8855961778 ps
CPU time 3.01 seconds
Started Apr 23 02:14:49 PM PDT 24
Finished Apr 23 02:14:53 PM PDT 24
Peak memory 183376 kb
Host smart-982c1a0d-a3a0-422f-bb47-47a30a8ea3e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741027487 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.3741027487
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.2312296928
Short name T75
Test name
Test status
Simulation time 437298907 ps
CPU time 1.08 seconds
Started Apr 23 02:14:49 PM PDT 24
Finished Apr 23 02:14:51 PM PDT 24
Peak memory 183312 kb
Host smart-9e9426f5-9b5d-4ea6-898f-2e8b00f725d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312296928 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.2312296928
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.63855800
Short name T193
Test name
Test status
Simulation time 262034748524 ps
CPU time 376.53 seconds
Started Apr 23 02:14:48 PM PDT 24
Finished Apr 23 02:21:05 PM PDT 24
Peak memory 194240 kb
Host smart-565b7c2e-df39-4af3-90b6-c1d92d392beb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63855800 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_al
l.63855800
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.1680320566
Short name T230
Test name
Test status
Simulation time 157345597641 ps
CPU time 164.34 seconds
Started Apr 23 02:14:41 PM PDT 24
Finished Apr 23 02:17:26 PM PDT 24
Peak memory 206472 kb
Host smart-c64a9421-b70b-43b0-8492-c443418739c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680320566 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.1680320566
Directory /workspace/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.aon_timer_jump.1455170362
Short name T245
Test name
Test status
Simulation time 520205998 ps
CPU time 0.73 seconds
Started Apr 23 02:14:49 PM PDT 24
Finished Apr 23 02:14:50 PM PDT 24
Peak memory 183312 kb
Host smart-88fe4a94-f6eb-402a-a336-07ca0ab7c6b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455170362 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.1455170362
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.2742940049
Short name T84
Test name
Test status
Simulation time 5801638042 ps
CPU time 8.56 seconds
Started Apr 23 02:14:42 PM PDT 24
Finished Apr 23 02:14:51 PM PDT 24
Peak memory 183296 kb
Host smart-ed3faa07-e6d9-4337-ab99-9915d66fd0e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742940049 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.2742940049
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.2470488384
Short name T204
Test name
Test status
Simulation time 408291168 ps
CPU time 1.17 seconds
Started Apr 23 02:14:40 PM PDT 24
Finished Apr 23 02:14:42 PM PDT 24
Peak memory 183284 kb
Host smart-44620519-38ef-451f-8a38-6b6813a1636f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470488384 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.2470488384
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.3748578661
Short name T182
Test name
Test status
Simulation time 71578747556 ps
CPU time 17.82 seconds
Started Apr 23 02:14:41 PM PDT 24
Finished Apr 23 02:15:00 PM PDT 24
Peak memory 195080 kb
Host smart-fa572f98-f6b0-4ff6-ae3e-438cd6e210ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748578661 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_
all.3748578661
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.238642988
Short name T226
Test name
Test status
Simulation time 207635344889 ps
CPU time 801.57 seconds
Started Apr 23 02:14:42 PM PDT 24
Finished Apr 23 02:28:04 PM PDT 24
Peak memory 201676 kb
Host smart-4104c970-1e94-4b17-82aa-b4ec5c80bd5c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238642988 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.238642988
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.aon_timer_jump.4237288008
Short name T131
Test name
Test status
Simulation time 570241071 ps
CPU time 0.71 seconds
Started Apr 23 02:14:44 PM PDT 24
Finished Apr 23 02:14:45 PM PDT 24
Peak memory 183308 kb
Host smart-5bcef766-bb4c-4098-b862-dff9382ff367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237288008 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.4237288008
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.3965751627
Short name T111
Test name
Test status
Simulation time 36202628825 ps
CPU time 61.79 seconds
Started Apr 23 02:14:49 PM PDT 24
Finished Apr 23 02:15:51 PM PDT 24
Peak memory 183376 kb
Host smart-ae857323-5d9a-4045-ae5f-8806aac2898d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965751627 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.3965751627
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.3940774016
Short name T119
Test name
Test status
Simulation time 423241272 ps
CPU time 0.69 seconds
Started Apr 23 02:14:42 PM PDT 24
Finished Apr 23 02:14:43 PM PDT 24
Peak memory 183304 kb
Host smart-c5abe42b-a866-457f-bd55-7c5b20556cd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940774016 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.3940774016
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.1525834421
Short name T253
Test name
Test status
Simulation time 165681727984 ps
CPU time 45.88 seconds
Started Apr 23 02:14:44 PM PDT 24
Finished Apr 23 02:15:30 PM PDT 24
Peak memory 194848 kb
Host smart-974d0f3d-6538-4afc-8eaf-0ad1e902e09c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525834421 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_
all.1525834421
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.2706890001
Short name T196
Test name
Test status
Simulation time 56859584956 ps
CPU time 596.81 seconds
Started Apr 23 02:14:47 PM PDT 24
Finished Apr 23 02:24:45 PM PDT 24
Peak memory 198336 kb
Host smart-1552101e-4cb5-4d4d-a885-0dd402f66e87
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706890001 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand_reset.2706890001
Directory /workspace/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.aon_timer_jump.2427282009
Short name T3
Test name
Test status
Simulation time 441699438 ps
CPU time 1.18 seconds
Started Apr 23 02:14:43 PM PDT 24
Finished Apr 23 02:14:45 PM PDT 24
Peak memory 183296 kb
Host smart-f8cd187e-fa56-4708-9331-dbd3a35caf88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427282009 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.2427282009
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.825854182
Short name T117
Test name
Test status
Simulation time 53533938251 ps
CPU time 38.28 seconds
Started Apr 23 02:14:48 PM PDT 24
Finished Apr 23 02:15:27 PM PDT 24
Peak memory 183360 kb
Host smart-314edcac-a2ad-40f4-9fd5-e20ae26b78ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825854182 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.825854182
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.1680556440
Short name T26
Test name
Test status
Simulation time 390971688 ps
CPU time 0.68 seconds
Started Apr 23 02:14:44 PM PDT 24
Finished Apr 23 02:14:45 PM PDT 24
Peak memory 183324 kb
Host smart-e8f911e6-73a0-4488-9af1-c3926879af0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680556440 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.1680556440
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.3057786145
Short name T146
Test name
Test status
Simulation time 49982433741 ps
CPU time 34.33 seconds
Started Apr 23 02:14:47 PM PDT 24
Finished Apr 23 02:15:22 PM PDT 24
Peak memory 193872 kb
Host smart-a1a3fdee-a1ba-497e-888c-ebf2478cceab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057786145 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_
all.3057786145
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.2251734324
Short name T42
Test name
Test status
Simulation time 147384624123 ps
CPU time 300.02 seconds
Started Apr 23 02:14:44 PM PDT 24
Finished Apr 23 02:19:45 PM PDT 24
Peak memory 198288 kb
Host smart-9c07247a-6648-436f-ac2c-f81adaaf04e9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251734324 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.2251734324
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_jump.273729479
Short name T128
Test name
Test status
Simulation time 669155086 ps
CPU time 0.6 seconds
Started Apr 23 02:13:52 PM PDT 24
Finished Apr 23 02:13:54 PM PDT 24
Peak memory 183216 kb
Host smart-59dcf533-be9d-41de-bbfd-b2b6cea5ffc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273729479 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.273729479
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.2092870780
Short name T212
Test name
Test status
Simulation time 35722206333 ps
CPU time 7.41 seconds
Started Apr 23 02:13:54 PM PDT 24
Finished Apr 23 02:14:02 PM PDT 24
Peak memory 183288 kb
Host smart-16a5af7f-f636-4bab-9b31-60e532b99b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092870780 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.2092870780
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.1020498596
Short name T19
Test name
Test status
Simulation time 8345472460 ps
CPU time 9.22 seconds
Started Apr 23 02:13:58 PM PDT 24
Finished Apr 23 02:14:08 PM PDT 24
Peak memory 215072 kb
Host smart-8c077fc6-64e8-41c7-a5a3-f41ff131e438
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020498596 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.1020498596
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.2424107596
Short name T172
Test name
Test status
Simulation time 476304442 ps
CPU time 1.22 seconds
Started Apr 23 02:13:58 PM PDT 24
Finished Apr 23 02:13:59 PM PDT 24
Peak memory 183232 kb
Host smart-903d6e38-a2b5-4915-b0ec-56b8f3306377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424107596 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.2424107596
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.1968088327
Short name T23
Test name
Test status
Simulation time 409626944675 ps
CPU time 335 seconds
Started Apr 23 02:13:57 PM PDT 24
Finished Apr 23 02:19:33 PM PDT 24
Peak memory 193904 kb
Host smart-9503caef-4758-48a0-a2b3-29411f9424e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968088327 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_a
ll.1968088327
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_jump.1241173440
Short name T112
Test name
Test status
Simulation time 387150539 ps
CPU time 0.8 seconds
Started Apr 23 02:14:47 PM PDT 24
Finished Apr 23 02:14:49 PM PDT 24
Peak memory 183296 kb
Host smart-13b9ae2a-dc82-466f-9212-9905e7087603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241173440 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.1241173440
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.611890798
Short name T201
Test name
Test status
Simulation time 27228840362 ps
CPU time 38.86 seconds
Started Apr 23 02:14:43 PM PDT 24
Finished Apr 23 02:15:23 PM PDT 24
Peak memory 183344 kb
Host smart-e11fdc56-23d7-467b-b7a3-2123c77014d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611890798 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.611890798
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.665715673
Short name T148
Test name
Test status
Simulation time 380457640 ps
CPU time 0.67 seconds
Started Apr 23 02:14:45 PM PDT 24
Finished Apr 23 02:14:46 PM PDT 24
Peak memory 183300 kb
Host smart-d6cd34ed-b456-4e41-bffe-989860d0374b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665715673 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.665715673
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.3878296074
Short name T150
Test name
Test status
Simulation time 297061792863 ps
CPU time 115.15 seconds
Started Apr 23 02:14:47 PM PDT 24
Finished Apr 23 02:16:42 PM PDT 24
Peak memory 183372 kb
Host smart-49d88291-eaed-48f2-bc48-5708f52d4fd0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878296074 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_
all.3878296074
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_jump.324971835
Short name T176
Test name
Test status
Simulation time 547339114 ps
CPU time 1.3 seconds
Started Apr 23 02:14:46 PM PDT 24
Finished Apr 23 02:14:48 PM PDT 24
Peak memory 183308 kb
Host smart-1ad073ef-39d4-468e-ae9c-5e62cde77821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324971835 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.324971835
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.674509923
Short name T109
Test name
Test status
Simulation time 39062387959 ps
CPU time 15.1 seconds
Started Apr 23 02:14:47 PM PDT 24
Finished Apr 23 02:15:03 PM PDT 24
Peak memory 183356 kb
Host smart-154b03a0-1486-42aa-8f2b-502c5276058c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674509923 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.674509923
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.1075868055
Short name T252
Test name
Test status
Simulation time 443185883 ps
CPU time 0.89 seconds
Started Apr 23 02:14:55 PM PDT 24
Finished Apr 23 02:14:56 PM PDT 24
Peak memory 183316 kb
Host smart-4f29d1b2-f51b-4ad9-84e8-572025d191c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075868055 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.1075868055
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.209483172
Short name T210
Test name
Test status
Simulation time 123256412927 ps
CPU time 198.89 seconds
Started Apr 23 02:14:48 PM PDT 24
Finished Apr 23 02:18:08 PM PDT 24
Peak memory 183312 kb
Host smart-4b0f5eac-6de5-49a1-989a-512ffedfcfcb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209483172 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_a
ll.209483172
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.2358863987
Short name T86
Test name
Test status
Simulation time 41249241624 ps
CPU time 314 seconds
Started Apr 23 02:14:47 PM PDT 24
Finished Apr 23 02:20:01 PM PDT 24
Peak memory 198228 kb
Host smart-372f11e6-5efa-4eb4-8b2c-d066aecf5c83
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358863987 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.2358863987
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.aon_timer_jump.3116801453
Short name T139
Test name
Test status
Simulation time 354509002 ps
CPU time 0.86 seconds
Started Apr 23 02:14:49 PM PDT 24
Finished Apr 23 02:14:51 PM PDT 24
Peak memory 183312 kb
Host smart-3b4862de-7b11-4ea1-ab89-a1e665357e0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116801453 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.3116801453
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.7713326
Short name T158
Test name
Test status
Simulation time 59778617377 ps
CPU time 23.38 seconds
Started Apr 23 02:14:49 PM PDT 24
Finished Apr 23 02:15:12 PM PDT 24
Peak memory 183348 kb
Host smart-f5dcd35d-1c47-4a3e-baef-54d899e2c2fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7713326 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.7713326
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.2069106645
Short name T137
Test name
Test status
Simulation time 515698853 ps
CPU time 0.62 seconds
Started Apr 23 02:14:49 PM PDT 24
Finished Apr 23 02:14:50 PM PDT 24
Peak memory 183272 kb
Host smart-475f388c-ba39-4d46-8e6d-d8aba30170f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069106645 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.2069106645
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.507026092
Short name T218
Test name
Test status
Simulation time 187128842141 ps
CPU time 150.5 seconds
Started Apr 23 02:14:51 PM PDT 24
Finished Apr 23 02:17:22 PM PDT 24
Peak memory 193452 kb
Host smart-8be8e6c3-6e13-4384-8494-0c5d735fcdc3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507026092 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_a
ll.507026092
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.1439305387
Short name T224
Test name
Test status
Simulation time 94087388955 ps
CPU time 247.63 seconds
Started Apr 23 02:14:50 PM PDT 24
Finished Apr 23 02:18:58 PM PDT 24
Peak memory 198256 kb
Host smart-7f90fc6c-888c-4bd3-a5ea-21e420b14868
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439305387 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.1439305387
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.aon_timer_jump.2296004343
Short name T239
Test name
Test status
Simulation time 403491792 ps
CPU time 0.63 seconds
Started Apr 23 02:14:48 PM PDT 24
Finished Apr 23 02:14:49 PM PDT 24
Peak memory 183392 kb
Host smart-c8b7564c-1c7c-431a-874b-a9761d258f58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296004343 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.2296004343
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.2542402219
Short name T157
Test name
Test status
Simulation time 19299182496 ps
CPU time 26.09 seconds
Started Apr 23 02:14:49 PM PDT 24
Finished Apr 23 02:15:16 PM PDT 24
Peak memory 183304 kb
Host smart-7744a50e-0b90-4800-8de4-f0bde858defc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542402219 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.2542402219
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.1285641021
Short name T102
Test name
Test status
Simulation time 360900325 ps
CPU time 0.69 seconds
Started Apr 23 02:14:49 PM PDT 24
Finished Apr 23 02:14:50 PM PDT 24
Peak memory 183304 kb
Host smart-f3e89f7a-b0b8-42e7-9277-3b41ec76c9dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285641021 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.1285641021
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.1950241084
Short name T171
Test name
Test status
Simulation time 97963893250 ps
CPU time 41.28 seconds
Started Apr 23 02:14:51 PM PDT 24
Finished Apr 23 02:15:33 PM PDT 24
Peak memory 193756 kb
Host smart-b1744a91-1b96-47f0-91fa-8d45d8c73838
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950241084 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_
all.1950241084
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.440476614
Short name T83
Test name
Test status
Simulation time 144461502221 ps
CPU time 203.49 seconds
Started Apr 23 02:14:49 PM PDT 24
Finished Apr 23 02:18:13 PM PDT 24
Peak memory 198344 kb
Host smart-3b1e5c28-99ef-476c-8d4b-79ca82d4abe1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440476614 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.440476614
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.aon_timer_jump.3907443548
Short name T124
Test name
Test status
Simulation time 424012252 ps
CPU time 0.7 seconds
Started Apr 23 02:14:54 PM PDT 24
Finished Apr 23 02:14:55 PM PDT 24
Peak memory 183296 kb
Host smart-ac806ffb-7813-4345-bd8e-b8b0fe4890f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907443548 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.3907443548
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.2707038335
Short name T207
Test name
Test status
Simulation time 42524417174 ps
CPU time 15.93 seconds
Started Apr 23 02:14:52 PM PDT 24
Finished Apr 23 02:15:08 PM PDT 24
Peak memory 183332 kb
Host smart-3a982329-5da4-43a3-8999-df530d7689a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707038335 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.2707038335
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.3091016595
Short name T246
Test name
Test status
Simulation time 591419350 ps
CPU time 1.44 seconds
Started Apr 23 02:14:51 PM PDT 24
Finished Apr 23 02:14:53 PM PDT 24
Peak memory 183272 kb
Host smart-d41b4fb6-eaf7-4d4c-ba29-b09e3033017c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091016595 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.3091016595
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.927425890
Short name T241
Test name
Test status
Simulation time 320568959795 ps
CPU time 62.68 seconds
Started Apr 23 02:14:52 PM PDT 24
Finished Apr 23 02:15:55 PM PDT 24
Peak memory 191528 kb
Host smart-d4295baf-e135-4c78-a458-97eaafe623a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927425890 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_a
ll.927425890
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.1657936775
Short name T263
Test name
Test status
Simulation time 88276781049 ps
CPU time 158.6 seconds
Started Apr 23 02:14:51 PM PDT 24
Finished Apr 23 02:17:30 PM PDT 24
Peak memory 198360 kb
Host smart-57106df8-402d-43cb-a819-cc1716ecd9b0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657936775 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.1657936775
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.aon_timer_jump.663872897
Short name T14
Test name
Test status
Simulation time 556465494 ps
CPU time 0.7 seconds
Started Apr 23 02:14:52 PM PDT 24
Finished Apr 23 02:14:53 PM PDT 24
Peak memory 183304 kb
Host smart-294bb6b0-8db4-433f-88ae-1cf0f4cc03f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663872897 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.663872897
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.316466610
Short name T46
Test name
Test status
Simulation time 19236897731 ps
CPU time 26.81 seconds
Started Apr 23 02:14:52 PM PDT 24
Finished Apr 23 02:15:20 PM PDT 24
Peak memory 183372 kb
Host smart-fcc413db-d880-4d9e-840d-494754b8abc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316466610 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.316466610
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.2701874626
Short name T206
Test name
Test status
Simulation time 593261767 ps
CPU time 1.42 seconds
Started Apr 23 02:14:50 PM PDT 24
Finished Apr 23 02:14:52 PM PDT 24
Peak memory 183304 kb
Host smart-f0d282c6-8fc6-4968-8f33-6c8df738def5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701874626 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.2701874626
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.1638118023
Short name T255
Test name
Test status
Simulation time 237738916163 ps
CPU time 387.74 seconds
Started Apr 23 02:14:52 PM PDT 24
Finished Apr 23 02:21:20 PM PDT 24
Peak memory 193648 kb
Host smart-c20ed058-99a6-40d2-bffd-0caba110d34a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638118023 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_
all.1638118023
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.1885267967
Short name T5
Test name
Test status
Simulation time 315601664835 ps
CPU time 598.45 seconds
Started Apr 23 02:14:53 PM PDT 24
Finished Apr 23 02:24:52 PM PDT 24
Peak memory 198952 kb
Host smart-971ae49b-ee6d-4d58-8bc4-d0a086b3d7d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885267967 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.1885267967
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.aon_timer_jump.21160195
Short name T152
Test name
Test status
Simulation time 557549805 ps
CPU time 0.73 seconds
Started Apr 23 02:14:55 PM PDT 24
Finished Apr 23 02:14:56 PM PDT 24
Peak memory 183292 kb
Host smart-3d2ed696-47a1-4ac5-a060-b4ce831240e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21160195 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.21160195
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.3908055087
Short name T87
Test name
Test status
Simulation time 26333289697 ps
CPU time 10.6 seconds
Started Apr 23 02:14:54 PM PDT 24
Finished Apr 23 02:15:05 PM PDT 24
Peak memory 183308 kb
Host smart-db882296-cb8d-4a25-8a93-de9b1e11118a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908055087 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.3908055087
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.692207463
Short name T98
Test name
Test status
Simulation time 528966808 ps
CPU time 0.61 seconds
Started Apr 23 02:14:56 PM PDT 24
Finished Apr 23 02:14:57 PM PDT 24
Peak memory 183304 kb
Host smart-dacbbbb8-9d4a-42f3-9995-1715c45c4d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692207463 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.692207463
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.3580988500
Short name T268
Test name
Test status
Simulation time 105769405024 ps
CPU time 141.83 seconds
Started Apr 23 02:14:58 PM PDT 24
Finished Apr 23 02:17:20 PM PDT 24
Peak memory 194096 kb
Host smart-52352408-5bbb-4e10-8e23-75970c3ddd96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580988500 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_
all.3580988500
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.3271995705
Short name T38
Test name
Test status
Simulation time 117053061185 ps
CPU time 562.09 seconds
Started Apr 23 02:14:55 PM PDT 24
Finished Apr 23 02:24:18 PM PDT 24
Peak memory 198760 kb
Host smart-7a374980-a811-4b28-86b8-c5ac3e9556b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271995705 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.3271995705
Directory /workspace/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.aon_timer_jump.41170107
Short name T192
Test name
Test status
Simulation time 494504185 ps
CPU time 0.72 seconds
Started Apr 23 02:14:59 PM PDT 24
Finished Apr 23 02:15:01 PM PDT 24
Peak memory 183280 kb
Host smart-706dc4c8-8b7d-41bd-951c-8b2c7535320e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41170107 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.41170107
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.610112084
Short name T170
Test name
Test status
Simulation time 13351754359 ps
CPU time 17.84 seconds
Started Apr 23 02:14:56 PM PDT 24
Finished Apr 23 02:15:15 PM PDT 24
Peak memory 183308 kb
Host smart-dd7a796b-a330-4bd7-a250-b7eea70cd5b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610112084 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.610112084
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.34465070
Short name T235
Test name
Test status
Simulation time 512790220 ps
CPU time 1.27 seconds
Started Apr 23 02:14:55 PM PDT 24
Finished Apr 23 02:14:56 PM PDT 24
Peak memory 183308 kb
Host smart-34b067af-6561-40ce-9d32-604a09b3e230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34465070 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.34465070
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.818497136
Short name T73
Test name
Test status
Simulation time 106957579116 ps
CPU time 160.12 seconds
Started Apr 23 02:14:57 PM PDT 24
Finished Apr 23 02:17:37 PM PDT 24
Peak memory 183348 kb
Host smart-47a26996-c760-4b55-88c1-0ed4cd85e818
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818497136 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_a
ll.818497136
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.1489167475
Short name T151
Test name
Test status
Simulation time 44126934573 ps
CPU time 180.49 seconds
Started Apr 23 02:14:56 PM PDT 24
Finished Apr 23 02:17:57 PM PDT 24
Peak memory 198272 kb
Host smart-3b10ee83-9c0d-453f-8412-4324cdd7d9b0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489167475 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.1489167475
Directory /workspace/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_jump.4103680295
Short name T132
Test name
Test status
Simulation time 559804314 ps
CPU time 1.43 seconds
Started Apr 23 02:15:03 PM PDT 24
Finished Apr 23 02:15:05 PM PDT 24
Peak memory 183228 kb
Host smart-2e878077-f193-495b-956b-0d2593e4db39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103680295 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.4103680295
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.3992099770
Short name T264
Test name
Test status
Simulation time 8552731791 ps
CPU time 4.63 seconds
Started Apr 23 02:14:59 PM PDT 24
Finished Apr 23 02:15:04 PM PDT 24
Peak memory 183364 kb
Host smart-02452f8c-d5b7-4580-88b4-2713a4883372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992099770 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.3992099770
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.2472367394
Short name T256
Test name
Test status
Simulation time 584430338 ps
CPU time 1.4 seconds
Started Apr 23 02:14:59 PM PDT 24
Finished Apr 23 02:15:01 PM PDT 24
Peak memory 183256 kb
Host smart-025b2e72-46ca-459a-9d26-8bc68d09268d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472367394 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.2472367394
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.793697221
Short name T203
Test name
Test status
Simulation time 217213532555 ps
CPU time 34.61 seconds
Started Apr 23 02:15:03 PM PDT 24
Finished Apr 23 02:15:38 PM PDT 24
Peak memory 183288 kb
Host smart-910609af-6884-4a47-9dd7-dbf336d4623d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793697221 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_a
ll.793697221
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.4258749851
Short name T41
Test name
Test status
Simulation time 25108178525 ps
CPU time 283.81 seconds
Started Apr 23 02:15:00 PM PDT 24
Finished Apr 23 02:19:45 PM PDT 24
Peak memory 198252 kb
Host smart-71252fc5-d2fc-4528-8f8c-de89555d66f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258749851 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.4258749851
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.aon_timer_jump.1534298955
Short name T277
Test name
Test status
Simulation time 389473373 ps
CPU time 0.86 seconds
Started Apr 23 02:15:00 PM PDT 24
Finished Apr 23 02:15:02 PM PDT 24
Peak memory 183184 kb
Host smart-7cc554c8-119f-4b40-ade5-e10ba011ed36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534298955 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.1534298955
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.2182191593
Short name T168
Test name
Test status
Simulation time 3748138801 ps
CPU time 3.63 seconds
Started Apr 23 02:15:01 PM PDT 24
Finished Apr 23 02:15:06 PM PDT 24
Peak memory 183256 kb
Host smart-f2eb527f-6505-4736-803a-30dfdfbc153f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182191593 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.2182191593
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.184468468
Short name T129
Test name
Test status
Simulation time 541117779 ps
CPU time 1.25 seconds
Started Apr 23 02:15:00 PM PDT 24
Finished Apr 23 02:15:02 PM PDT 24
Peak memory 183300 kb
Host smart-24c472de-2f94-4c72-8b57-9f164ba63e8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184468468 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.184468468
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.3698268378
Short name T191
Test name
Test status
Simulation time 157456383441 ps
CPU time 111.51 seconds
Started Apr 23 02:15:02 PM PDT 24
Finished Apr 23 02:16:54 PM PDT 24
Peak memory 183272 kb
Host smart-e75a9105-45dd-4c74-9681-42ae7165b472
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698268378 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_
all.3698268378
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.1718883163
Short name T85
Test name
Test status
Simulation time 176654601335 ps
CPU time 790.62 seconds
Started Apr 23 02:15:02 PM PDT 24
Finished Apr 23 02:28:13 PM PDT 24
Peak memory 201264 kb
Host smart-5df1dad7-781c-4a51-88e7-42abbf9b5a6f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718883163 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.1718883163
Directory /workspace/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.aon_timer_jump.2519521006
Short name T233
Test name
Test status
Simulation time 502262471 ps
CPU time 1.25 seconds
Started Apr 23 02:13:57 PM PDT 24
Finished Apr 23 02:13:58 PM PDT 24
Peak memory 183268 kb
Host smart-bc122b29-a2a9-4ac9-80b7-9d230f9108b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519521006 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.2519521006
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.1123948489
Short name T45
Test name
Test status
Simulation time 2517897756 ps
CPU time 3.95 seconds
Started Apr 23 02:13:59 PM PDT 24
Finished Apr 23 02:14:04 PM PDT 24
Peak memory 183384 kb
Host smart-28f783c8-ab2a-48f2-83a9-f0fd93bfed29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123948489 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.1123948489
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.2765647335
Short name T178
Test name
Test status
Simulation time 425704232 ps
CPU time 0.65 seconds
Started Apr 23 02:13:55 PM PDT 24
Finished Apr 23 02:13:56 PM PDT 24
Peak memory 183240 kb
Host smart-4fbb2e7e-1df8-4d64-b281-db17673c9671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765647335 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.2765647335
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.2213751601
Short name T7
Test name
Test status
Simulation time 190369460261 ps
CPU time 268.14 seconds
Started Apr 23 02:13:56 PM PDT 24
Finished Apr 23 02:18:24 PM PDT 24
Peak memory 183280 kb
Host smart-4e5cdd5e-2718-4152-98d8-5ffcc2a7ea70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213751601 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_a
ll.2213751601
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.1356615393
Short name T231
Test name
Test status
Simulation time 726712515449 ps
CPU time 638.24 seconds
Started Apr 23 02:13:56 PM PDT 24
Finished Apr 23 02:24:35 PM PDT 24
Peak memory 207696 kb
Host smart-18d89053-a9ba-401a-bd4a-d1d255b9325d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356615393 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.1356615393
Directory /workspace/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.aon_timer_jump.937885712
Short name T118
Test name
Test status
Simulation time 404704181 ps
CPU time 0.71 seconds
Started Apr 23 02:13:58 PM PDT 24
Finished Apr 23 02:13:59 PM PDT 24
Peak memory 183296 kb
Host smart-f6c6632b-1643-4cdc-9e13-ba116424a4be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937885712 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.937885712
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.1852219970
Short name T44
Test name
Test status
Simulation time 39248908011 ps
CPU time 16.47 seconds
Started Apr 23 02:13:56 PM PDT 24
Finished Apr 23 02:14:13 PM PDT 24
Peak memory 183452 kb
Host smart-123ebab5-cdf0-4cbe-98a5-3def70f08521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852219970 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.1852219970
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.2717976058
Short name T251
Test name
Test status
Simulation time 515607554 ps
CPU time 0.98 seconds
Started Apr 23 02:13:57 PM PDT 24
Finished Apr 23 02:13:58 PM PDT 24
Peak memory 183220 kb
Host smart-b150cc16-dcb8-4343-b8eb-d915a5f06dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717976058 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.2717976058
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.3916960129
Short name T143
Test name
Test status
Simulation time 373831064507 ps
CPU time 142.99 seconds
Started Apr 23 02:13:58 PM PDT 24
Finished Apr 23 02:16:22 PM PDT 24
Peak memory 192688 kb
Host smart-033715c4-aeed-4b25-8a84-dafce19a52bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916960129 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_a
ll.3916960129
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.1277483261
Short name T89
Test name
Test status
Simulation time 46898825390 ps
CPU time 106.01 seconds
Started Apr 23 02:13:57 PM PDT 24
Finished Apr 23 02:15:44 PM PDT 24
Peak memory 198344 kb
Host smart-7bfc6977-cc0d-41f3-bac4-5685a9289d44
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277483261 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.1277483261
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.aon_timer_jump.3918714559
Short name T273
Test name
Test status
Simulation time 481795063 ps
CPU time 0.78 seconds
Started Apr 23 02:13:58 PM PDT 24
Finished Apr 23 02:14:00 PM PDT 24
Peak memory 183196 kb
Host smart-97c562f5-2b3b-4663-b749-a14dbec658bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918714559 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.3918714559
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.3324965120
Short name T217
Test name
Test status
Simulation time 6569086632 ps
CPU time 9.22 seconds
Started Apr 23 02:13:59 PM PDT 24
Finished Apr 23 02:14:09 PM PDT 24
Peak memory 183348 kb
Host smart-1e51348e-4256-49e4-9326-4a1a219c5c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324965120 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.3324965120
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.416538012
Short name T257
Test name
Test status
Simulation time 458714879 ps
CPU time 0.8 seconds
Started Apr 23 02:13:57 PM PDT 24
Finished Apr 23 02:13:58 PM PDT 24
Peak memory 183272 kb
Host smart-ea8427a8-39d7-43a8-bfb3-d6bd32f0e324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416538012 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.416538012
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.941246326
Short name T141
Test name
Test status
Simulation time 182423868552 ps
CPU time 262.91 seconds
Started Apr 23 02:13:59 PM PDT 24
Finished Apr 23 02:18:22 PM PDT 24
Peak memory 183376 kb
Host smart-64d55298-7576-405f-b69b-ea39015a6e64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941246326 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_al
l.941246326
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_jump.2894327834
Short name T267
Test name
Test status
Simulation time 353221200 ps
CPU time 0.91 seconds
Started Apr 23 02:14:00 PM PDT 24
Finished Apr 23 02:14:01 PM PDT 24
Peak memory 183264 kb
Host smart-d779791a-f810-41e1-84ca-9c66956af6db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894327834 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.2894327834
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.1275283603
Short name T104
Test name
Test status
Simulation time 2009663193 ps
CPU time 1.31 seconds
Started Apr 23 02:13:58 PM PDT 24
Finished Apr 23 02:14:00 PM PDT 24
Peak memory 183284 kb
Host smart-2d84a3be-fe68-4a5a-821a-6998fda723ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275283603 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.1275283603
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.1708130095
Short name T197
Test name
Test status
Simulation time 388552072 ps
CPU time 0.63 seconds
Started Apr 23 02:14:01 PM PDT 24
Finished Apr 23 02:14:02 PM PDT 24
Peak memory 183160 kb
Host smart-aafaf72d-659c-4cbb-aca0-79be4b70115c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708130095 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.1708130095
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.993221811
Short name T162
Test name
Test status
Simulation time 154401690032 ps
CPU time 200.73 seconds
Started Apr 23 02:13:59 PM PDT 24
Finished Apr 23 02:17:20 PM PDT 24
Peak memory 194872 kb
Host smart-3de6b8c2-76f4-4d36-99f8-1088ce9e835b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993221811 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_al
l.993221811
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.853357839
Short name T79
Test name
Test status
Simulation time 175752158192 ps
CPU time 113.5 seconds
Started Apr 23 02:13:59 PM PDT 24
Finished Apr 23 02:15:53 PM PDT 24
Peak memory 213756 kb
Host smart-89f978cf-5a99-4c10-a404-74594b948a5b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853357839 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.853357839
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.aon_timer_jump.2626019161
Short name T248
Test name
Test status
Simulation time 632948291 ps
CPU time 0.66 seconds
Started Apr 23 02:14:02 PM PDT 24
Finished Apr 23 02:14:03 PM PDT 24
Peak memory 183340 kb
Host smart-c6e51152-75e0-49b5-9fe1-a2bbc427adb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626019161 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.2626019161
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.2191124472
Short name T199
Test name
Test status
Simulation time 30915518663 ps
CPU time 12.1 seconds
Started Apr 23 02:14:05 PM PDT 24
Finished Apr 23 02:14:18 PM PDT 24
Peak memory 183304 kb
Host smart-acc963e9-04fe-424b-b9bb-327fdc82b8f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191124472 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.2191124472
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.3527145794
Short name T184
Test name
Test status
Simulation time 398536457 ps
CPU time 0.66 seconds
Started Apr 23 02:14:05 PM PDT 24
Finished Apr 23 02:14:06 PM PDT 24
Peak memory 183232 kb
Host smart-f9d1432d-8dbf-4e79-9d5f-48e25c35c4bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527145794 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.3527145794
Directory /workspace/9.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.67072673
Short name T242
Test name
Test status
Simulation time 68640413999 ps
CPU time 27.85 seconds
Started Apr 23 02:14:02 PM PDT 24
Finished Apr 23 02:14:30 PM PDT 24
Peak memory 183368 kb
Host smart-3e60a04a-e339-4b9f-b490-6567c4fc5835
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67072673 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all
.67072673
Directory /workspace/9.aon_timer_stress_all/latest
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