Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
92.98 99.25 93.67 100.00 98.40 99.51 67.06


Total test records in report: 420
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T31 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.1905170888 Apr 25 12:46:45 PM PDT 24 Apr 25 12:46:48 PM PDT 24 335641473 ps
T283 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.2467038142 Apr 25 12:46:44 PM PDT 24 Apr 25 12:46:49 PM PDT 24 497930105 ps
T34 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.611694371 Apr 25 12:46:51 PM PDT 24 Apr 25 12:46:55 PM PDT 24 1572845390 ps
T284 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.1789231210 Apr 25 12:47:01 PM PDT 24 Apr 25 12:47:04 PM PDT 24 307035232 ps
T35 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.1253592707 Apr 25 12:46:38 PM PDT 24 Apr 25 12:46:52 PM PDT 24 8641270725 ps
T285 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.803980442 Apr 25 12:46:59 PM PDT 24 Apr 25 12:47:01 PM PDT 24 468321352 ps
T87 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.3235258925 Apr 25 12:46:46 PM PDT 24 Apr 25 12:46:49 PM PDT 24 625619127 ps
T36 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.820705555 Apr 25 12:46:55 PM PDT 24 Apr 25 12:47:01 PM PDT 24 8612584905 ps
T72 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.2916529417 Apr 25 12:46:51 PM PDT 24 Apr 25 12:46:54 PM PDT 24 2498475396 ps
T286 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.3492993988 Apr 25 12:46:51 PM PDT 24 Apr 25 12:46:53 PM PDT 24 566200233 ps
T49 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.3368031981 Apr 25 12:46:43 PM PDT 24 Apr 25 12:46:46 PM PDT 24 507917031 ps
T73 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.3217751530 Apr 25 12:46:44 PM PDT 24 Apr 25 12:46:48 PM PDT 24 527080297 ps
T287 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.2812385627 Apr 25 12:47:00 PM PDT 24 Apr 25 12:47:01 PM PDT 24 413026585 ps
T288 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.2973658267 Apr 25 12:46:59 PM PDT 24 Apr 25 12:47:01 PM PDT 24 481224955 ps
T289 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.2200892406 Apr 25 12:46:33 PM PDT 24 Apr 25 12:46:46 PM PDT 24 7006580679 ps
T290 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.3219664798 Apr 25 12:47:04 PM PDT 24 Apr 25 12:47:06 PM PDT 24 482024487 ps
T291 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.2990523028 Apr 25 12:47:03 PM PDT 24 Apr 25 12:47:05 PM PDT 24 494561105 ps
T50 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.2207741948 Apr 25 12:46:46 PM PDT 24 Apr 25 12:46:49 PM PDT 24 338607082 ps
T292 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.1386550783 Apr 25 12:46:35 PM PDT 24 Apr 25 12:46:37 PM PDT 24 375017945 ps
T37 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.491293186 Apr 25 12:46:39 PM PDT 24 Apr 25 12:46:54 PM PDT 24 8574063483 ps
T293 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.1174685643 Apr 25 12:46:54 PM PDT 24 Apr 25 12:46:56 PM PDT 24 736904254 ps
T294 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.2062284306 Apr 25 12:46:38 PM PDT 24 Apr 25 12:46:41 PM PDT 24 382013357 ps
T295 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.2193206250 Apr 25 12:47:01 PM PDT 24 Apr 25 12:47:03 PM PDT 24 348074995 ps
T296 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.2461173403 Apr 25 12:46:49 PM PDT 24 Apr 25 12:46:52 PM PDT 24 472294693 ps
T104 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.3958160249 Apr 25 12:46:43 PM PDT 24 Apr 25 12:46:50 PM PDT 24 4437536826 ps
T297 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.109736343 Apr 25 12:46:42 PM PDT 24 Apr 25 12:46:45 PM PDT 24 386089676 ps
T298 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.496620658 Apr 25 12:46:47 PM PDT 24 Apr 25 12:46:50 PM PDT 24 675636763 ps
T299 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.3376974099 Apr 25 12:46:45 PM PDT 24 Apr 25 12:46:48 PM PDT 24 273337655 ps
T51 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.4242087600 Apr 25 12:46:42 PM PDT 24 Apr 25 12:46:46 PM PDT 24 639458358 ps
T300 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.1533739080 Apr 25 12:46:45 PM PDT 24 Apr 25 12:46:49 PM PDT 24 363035146 ps
T301 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.2841816013 Apr 25 12:47:07 PM PDT 24 Apr 25 12:47:10 PM PDT 24 419891388 ps
T302 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.4228802670 Apr 25 12:46:53 PM PDT 24 Apr 25 12:46:55 PM PDT 24 412384702 ps
T303 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.2272957796 Apr 25 12:46:53 PM PDT 24 Apr 25 12:46:55 PM PDT 24 407980991 ps
T304 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.1249008101 Apr 25 12:46:57 PM PDT 24 Apr 25 12:47:00 PM PDT 24 454240959 ps
T305 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.2892375554 Apr 25 12:46:38 PM PDT 24 Apr 25 12:46:41 PM PDT 24 517964706 ps
T306 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.1983003224 Apr 25 12:46:54 PM PDT 24 Apr 25 12:46:56 PM PDT 24 1146559789 ps
T307 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.1816989053 Apr 25 12:46:43 PM PDT 24 Apr 25 12:46:46 PM PDT 24 386670083 ps
T52 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.3248260984 Apr 25 12:46:38 PM PDT 24 Apr 25 12:47:10 PM PDT 24 13864294459 ps
T308 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.1103565545 Apr 25 12:46:41 PM PDT 24 Apr 25 12:46:44 PM PDT 24 264073067 ps
T309 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.863022197 Apr 25 12:46:52 PM PDT 24 Apr 25 12:46:54 PM PDT 24 575832017 ps
T53 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.3986230883 Apr 25 12:46:51 PM PDT 24 Apr 25 12:46:52 PM PDT 24 345208045 ps
T310 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.3153934892 Apr 25 12:47:04 PM PDT 24 Apr 25 12:47:06 PM PDT 24 579444828 ps
T311 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.2183226048 Apr 25 12:46:39 PM PDT 24 Apr 25 12:46:41 PM PDT 24 320400610 ps
T312 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.218844674 Apr 25 12:47:03 PM PDT 24 Apr 25 12:47:04 PM PDT 24 370186266 ps
T313 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.925086716 Apr 25 12:46:32 PM PDT 24 Apr 25 12:46:35 PM PDT 24 422184880 ps
T314 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.3326874718 Apr 25 12:46:43 PM PDT 24 Apr 25 12:46:46 PM PDT 24 575914911 ps
T315 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.185821913 Apr 25 12:46:58 PM PDT 24 Apr 25 12:47:00 PM PDT 24 4424270152 ps
T316 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.2892143706 Apr 25 12:46:55 PM PDT 24 Apr 25 12:46:58 PM PDT 24 510072438 ps
T317 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.1638022196 Apr 25 12:46:34 PM PDT 24 Apr 25 12:46:36 PM PDT 24 310763998 ps
T106 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.1447523095 Apr 25 12:46:46 PM PDT 24 Apr 25 12:46:54 PM PDT 24 7923363614 ps
T318 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.1859726060 Apr 25 12:46:57 PM PDT 24 Apr 25 12:47:00 PM PDT 24 555605628 ps
T319 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.718094343 Apr 25 12:47:07 PM PDT 24 Apr 25 12:47:10 PM PDT 24 462542760 ps
T320 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.3822182705 Apr 25 12:46:53 PM PDT 24 Apr 25 12:46:56 PM PDT 24 539654787 ps
T74 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.955347091 Apr 25 12:46:55 PM PDT 24 Apr 25 12:47:00 PM PDT 24 2252164338 ps
T75 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.1680624400 Apr 25 12:46:53 PM PDT 24 Apr 25 12:46:55 PM PDT 24 550116674 ps
T321 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.2960973988 Apr 25 12:46:45 PM PDT 24 Apr 25 12:46:48 PM PDT 24 416552358 ps
T76 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.955943775 Apr 25 12:46:42 PM PDT 24 Apr 25 12:46:45 PM PDT 24 1385081492 ps
T322 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.374157718 Apr 25 12:46:34 PM PDT 24 Apr 25 12:46:36 PM PDT 24 392504426 ps
T323 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.3008123837 Apr 25 12:47:01 PM PDT 24 Apr 25 12:47:03 PM PDT 24 494814583 ps
T324 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.1999061033 Apr 25 12:46:41 PM PDT 24 Apr 25 12:46:43 PM PDT 24 504004315 ps
T325 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.3460741563 Apr 25 12:46:44 PM PDT 24 Apr 25 12:46:47 PM PDT 24 368821344 ps
T77 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.1360144377 Apr 25 12:46:43 PM PDT 24 Apr 25 12:46:46 PM PDT 24 2426670416 ps
T78 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.2894544961 Apr 25 12:46:54 PM PDT 24 Apr 25 12:46:57 PM PDT 24 2422212879 ps
T326 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.2272452415 Apr 25 12:46:42 PM PDT 24 Apr 25 12:46:46 PM PDT 24 1270419916 ps
T327 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.2387910273 Apr 25 12:46:46 PM PDT 24 Apr 25 12:46:49 PM PDT 24 501381793 ps
T328 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.730020673 Apr 25 12:47:06 PM PDT 24 Apr 25 12:47:08 PM PDT 24 447857958 ps
T329 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.3262214714 Apr 25 12:46:47 PM PDT 24 Apr 25 12:46:50 PM PDT 24 480828896 ps
T330 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.126220961 Apr 25 12:46:55 PM PDT 24 Apr 25 12:46:58 PM PDT 24 769350869 ps
T331 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.330465802 Apr 25 12:46:38 PM PDT 24 Apr 25 12:46:41 PM PDT 24 1154080278 ps
T332 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.3756562962 Apr 25 12:46:59 PM PDT 24 Apr 25 12:47:00 PM PDT 24 406255395 ps
T333 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.2052054737 Apr 25 12:46:53 PM PDT 24 Apr 25 12:46:55 PM PDT 24 402563658 ps
T334 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.2325316558 Apr 25 12:46:50 PM PDT 24 Apr 25 12:46:53 PM PDT 24 506176550 ps
T335 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.1807165694 Apr 25 12:46:46 PM PDT 24 Apr 25 12:46:52 PM PDT 24 2237961405 ps
T55 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.3500967174 Apr 25 12:46:46 PM PDT 24 Apr 25 12:46:49 PM PDT 24 608234361 ps
T107 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.974854739 Apr 25 12:46:51 PM PDT 24 Apr 25 12:47:01 PM PDT 24 4217407419 ps
T336 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.2294130484 Apr 25 12:46:58 PM PDT 24 Apr 25 12:47:00 PM PDT 24 332362112 ps
T337 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.1474708510 Apr 25 12:46:39 PM PDT 24 Apr 25 12:46:42 PM PDT 24 395372928 ps
T338 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.306258677 Apr 25 12:46:55 PM PDT 24 Apr 25 12:46:57 PM PDT 24 310864920 ps
T339 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.2707952932 Apr 25 12:46:46 PM PDT 24 Apr 25 12:46:49 PM PDT 24 533983241 ps
T340 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.3617171558 Apr 25 12:47:06 PM PDT 24 Apr 25 12:47:08 PM PDT 24 511559169 ps
T341 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.4161561295 Apr 25 12:46:55 PM PDT 24 Apr 25 12:46:57 PM PDT 24 576424417 ps
T342 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.3478084337 Apr 25 12:46:35 PM PDT 24 Apr 25 12:46:39 PM PDT 24 431751508 ps
T343 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.4193494712 Apr 25 12:46:51 PM PDT 24 Apr 25 12:46:54 PM PDT 24 1429595971 ps
T344 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.3754300332 Apr 25 12:46:49 PM PDT 24 Apr 25 12:46:58 PM PDT 24 4286953080 ps
T345 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.3675667384 Apr 25 12:46:38 PM PDT 24 Apr 25 12:46:41 PM PDT 24 626697358 ps
T346 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.418624584 Apr 25 12:46:36 PM PDT 24 Apr 25 12:46:38 PM PDT 24 507505990 ps
T108 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.2953394386 Apr 25 12:46:40 PM PDT 24 Apr 25 12:46:45 PM PDT 24 4414379099 ps
T347 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.3928636808 Apr 25 12:46:39 PM PDT 24 Apr 25 12:46:43 PM PDT 24 2203124188 ps
T348 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.1295399680 Apr 25 12:46:57 PM PDT 24 Apr 25 12:46:59 PM PDT 24 420693932 ps
T349 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.1865606004 Apr 25 12:47:01 PM PDT 24 Apr 25 12:47:04 PM PDT 24 503238120 ps
T350 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.3403763976 Apr 25 12:47:00 PM PDT 24 Apr 25 12:47:02 PM PDT 24 316426638 ps
T351 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.3318147812 Apr 25 12:46:42 PM PDT 24 Apr 25 12:46:45 PM PDT 24 1342205278 ps
T352 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.4054176005 Apr 25 12:46:52 PM PDT 24 Apr 25 12:46:54 PM PDT 24 1321695475 ps
T353 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.4216289048 Apr 25 12:46:55 PM PDT 24 Apr 25 12:46:58 PM PDT 24 593131394 ps
T354 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.627033584 Apr 25 12:46:50 PM PDT 24 Apr 25 12:47:03 PM PDT 24 8005331842 ps
T355 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.2352899230 Apr 25 12:46:39 PM PDT 24 Apr 25 12:46:42 PM PDT 24 703770287 ps
T356 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.4283878544 Apr 25 12:46:59 PM PDT 24 Apr 25 12:47:00 PM PDT 24 321527885 ps
T357 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.3077676320 Apr 25 12:46:41 PM PDT 24 Apr 25 12:46:45 PM PDT 24 837421498 ps
T358 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.4261159792 Apr 25 12:46:57 PM PDT 24 Apr 25 12:47:02 PM PDT 24 4100213854 ps
T359 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.3868672360 Apr 25 12:46:43 PM PDT 24 Apr 25 12:46:46 PM PDT 24 419117626 ps
T360 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.3619266837 Apr 25 12:46:51 PM PDT 24 Apr 25 12:46:53 PM PDT 24 451471399 ps
T361 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.1635921664 Apr 25 12:46:51 PM PDT 24 Apr 25 12:46:52 PM PDT 24 307152661 ps
T61 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.3522175329 Apr 25 12:46:54 PM PDT 24 Apr 25 12:46:57 PM PDT 24 338308042 ps
T362 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.52820660 Apr 25 12:46:49 PM PDT 24 Apr 25 12:46:53 PM PDT 24 431750571 ps
T363 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.1888378297 Apr 25 12:46:45 PM PDT 24 Apr 25 12:46:49 PM PDT 24 305168764 ps
T364 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.4141616915 Apr 25 12:46:50 PM PDT 24 Apr 25 12:46:51 PM PDT 24 342963869 ps
T365 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.2372220455 Apr 25 12:47:06 PM PDT 24 Apr 25 12:47:08 PM PDT 24 310550366 ps
T366 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.1845508797 Apr 25 12:46:57 PM PDT 24 Apr 25 12:46:59 PM PDT 24 531475556 ps
T367 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.2189158751 Apr 25 12:46:59 PM PDT 24 Apr 25 12:47:03 PM PDT 24 972918627 ps
T368 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.27252742 Apr 25 12:46:42 PM PDT 24 Apr 25 12:46:45 PM PDT 24 1303723794 ps
T56 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.4036807426 Apr 25 12:46:38 PM PDT 24 Apr 25 12:46:41 PM PDT 24 395683674 ps
T369 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.1890934012 Apr 25 12:46:55 PM PDT 24 Apr 25 12:46:58 PM PDT 24 453649238 ps
T370 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.158578004 Apr 25 12:46:36 PM PDT 24 Apr 25 12:46:46 PM PDT 24 7155169765 ps
T371 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.4000723534 Apr 25 12:46:36 PM PDT 24 Apr 25 12:46:39 PM PDT 24 503025616 ps
T372 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.11881480 Apr 25 12:46:43 PM PDT 24 Apr 25 12:46:46 PM PDT 24 351548514 ps
T373 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.2553485498 Apr 25 12:46:42 PM PDT 24 Apr 25 12:46:47 PM PDT 24 8168846538 ps
T374 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.1409330474 Apr 25 12:47:03 PM PDT 24 Apr 25 12:47:05 PM PDT 24 419858967 ps
T71 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.1019835206 Apr 25 12:46:55 PM PDT 24 Apr 25 12:46:57 PM PDT 24 462708329 ps
T375 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.1648373811 Apr 25 12:46:42 PM PDT 24 Apr 25 12:46:45 PM PDT 24 526867148 ps
T376 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.3692728244 Apr 25 12:46:51 PM PDT 24 Apr 25 12:46:54 PM PDT 24 471827414 ps
T377 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.1850739211 Apr 25 12:46:39 PM PDT 24 Apr 25 12:46:43 PM PDT 24 481146482 ps
T378 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.143693122 Apr 25 12:46:54 PM PDT 24 Apr 25 12:46:57 PM PDT 24 1175535800 ps
T379 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.2270887482 Apr 25 12:47:00 PM PDT 24 Apr 25 12:47:02 PM PDT 24 422506257 ps
T380 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.557777690 Apr 25 12:46:45 PM PDT 24 Apr 25 12:46:49 PM PDT 24 1099087687 ps
T381 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.609793162 Apr 25 12:46:55 PM PDT 24 Apr 25 12:46:57 PM PDT 24 328802802 ps
T382 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.2837647758 Apr 25 12:46:35 PM PDT 24 Apr 25 12:46:43 PM PDT 24 7756216287 ps
T383 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.3948085195 Apr 25 12:46:59 PM PDT 24 Apr 25 12:47:02 PM PDT 24 472840270 ps
T384 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.3246461183 Apr 25 12:47:02 PM PDT 24 Apr 25 12:47:05 PM PDT 24 3073202737 ps
T385 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.2203098009 Apr 25 12:46:37 PM PDT 24 Apr 25 12:46:39 PM PDT 24 396555935 ps
T386 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.749255922 Apr 25 12:46:42 PM PDT 24 Apr 25 12:46:45 PM PDT 24 1203607164 ps
T387 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.4281440290 Apr 25 12:46:55 PM PDT 24 Apr 25 12:46:58 PM PDT 24 490923412 ps
T388 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.3000874101 Apr 25 12:46:42 PM PDT 24 Apr 25 12:46:47 PM PDT 24 574462607 ps
T389 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.2449964281 Apr 25 12:46:48 PM PDT 24 Apr 25 12:46:51 PM PDT 24 354937923 ps
T390 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.2590186482 Apr 25 12:46:49 PM PDT 24 Apr 25 12:46:52 PM PDT 24 4476248546 ps
T391 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.3165957759 Apr 25 12:46:36 PM PDT 24 Apr 25 12:46:38 PM PDT 24 637354101 ps
T392 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.4247108702 Apr 25 12:46:51 PM PDT 24 Apr 25 12:46:53 PM PDT 24 347223565 ps
T393 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.620092274 Apr 25 12:46:55 PM PDT 24 Apr 25 12:47:10 PM PDT 24 8103964585 ps
T394 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.2655786712 Apr 25 12:46:59 PM PDT 24 Apr 25 12:47:01 PM PDT 24 349828548 ps
T395 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.2605681688 Apr 25 12:46:46 PM PDT 24 Apr 25 12:46:49 PM PDT 24 2159834160 ps
T396 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.2567874143 Apr 25 12:46:52 PM PDT 24 Apr 25 12:46:55 PM PDT 24 360624717 ps
T397 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.4206924285 Apr 25 12:46:49 PM PDT 24 Apr 25 12:47:02 PM PDT 24 7938634450 ps
T398 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.658166023 Apr 25 12:47:03 PM PDT 24 Apr 25 12:47:05 PM PDT 24 302023948 ps
T105 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.3542762830 Apr 25 12:46:42 PM PDT 24 Apr 25 12:46:50 PM PDT 24 4714455289 ps
T399 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.2664136494 Apr 25 12:47:01 PM PDT 24 Apr 25 12:47:04 PM PDT 24 285700812 ps
T400 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.3899235587 Apr 25 12:46:54 PM PDT 24 Apr 25 12:47:02 PM PDT 24 4294719493 ps
T57 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.95687148 Apr 25 12:46:38 PM PDT 24 Apr 25 12:46:41 PM PDT 24 307476833 ps
T401 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.2308607837 Apr 25 12:46:55 PM PDT 24 Apr 25 12:47:04 PM PDT 24 4039956871 ps
T58 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.1999355167 Apr 25 12:46:46 PM PDT 24 Apr 25 12:47:04 PM PDT 24 10774048528 ps
T402 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.167611128 Apr 25 12:47:01 PM PDT 24 Apr 25 12:47:03 PM PDT 24 460055466 ps
T403 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.1667840082 Apr 25 12:46:43 PM PDT 24 Apr 25 12:46:47 PM PDT 24 753932339 ps
T59 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.598801858 Apr 25 12:46:55 PM PDT 24 Apr 25 12:46:58 PM PDT 24 447214020 ps
T404 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.1044894146 Apr 25 12:46:37 PM PDT 24 Apr 25 12:46:40 PM PDT 24 698553117 ps
T405 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.1498537259 Apr 25 12:46:37 PM PDT 24 Apr 25 12:46:40 PM PDT 24 1802019811 ps
T406 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.3533375438 Apr 25 12:46:57 PM PDT 24 Apr 25 12:46:59 PM PDT 24 389796444 ps
T407 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.1381296455 Apr 25 12:46:37 PM PDT 24 Apr 25 12:46:39 PM PDT 24 1431384394 ps
T408 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.261895261 Apr 25 12:46:40 PM PDT 24 Apr 25 12:46:42 PM PDT 24 546659203 ps
T409 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.2500664990 Apr 25 12:47:04 PM PDT 24 Apr 25 12:47:07 PM PDT 24 316262302 ps
T60 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.2725571672 Apr 25 12:46:40 PM PDT 24 Apr 25 12:46:43 PM PDT 24 595208221 ps
T410 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.3526558369 Apr 25 12:47:00 PM PDT 24 Apr 25 12:47:03 PM PDT 24 304208572 ps
T411 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.2262809227 Apr 25 12:46:53 PM PDT 24 Apr 25 12:46:55 PM PDT 24 604944159 ps
T412 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.567380392 Apr 25 12:46:38 PM PDT 24 Apr 25 12:46:40 PM PDT 24 514964074 ps
T413 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.2986944165 Apr 25 12:46:53 PM PDT 24 Apr 25 12:46:55 PM PDT 24 522830312 ps
T414 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.4198577481 Apr 25 12:46:44 PM PDT 24 Apr 25 12:46:47 PM PDT 24 473123088 ps
T415 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.1649641238 Apr 25 12:46:38 PM PDT 24 Apr 25 12:46:40 PM PDT 24 313058988 ps
T416 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.2410027349 Apr 25 12:47:08 PM PDT 24 Apr 25 12:47:10 PM PDT 24 3024656472 ps
T417 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.2839756506 Apr 25 12:47:04 PM PDT 24 Apr 25 12:47:06 PM PDT 24 511413265 ps
T418 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.2470292185 Apr 25 12:46:42 PM PDT 24 Apr 25 12:46:44 PM PDT 24 610422921 ps
T54 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.3913981118 Apr 25 12:46:37 PM PDT 24 Apr 25 12:46:39 PM PDT 24 386286326 ps
T419 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.928718175 Apr 25 12:46:50 PM PDT 24 Apr 25 12:46:52 PM PDT 24 461730063 ps
T420 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.2325571002 Apr 25 12:47:06 PM PDT 24 Apr 25 12:47:19 PM PDT 24 7543162920 ps

Test location /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.2297852644
Short name T2
Test name
Test status
Simulation time 173599524581 ps
CPU time 465.09 seconds
Started Apr 25 12:46:36 PM PDT 24
Finished Apr 25 12:54:23 PM PDT 24
Peak memory 198532 kb
Host smart-254217f3-b92a-41e2-9972-08d74c31fbb2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297852644 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.2297852644
Directory /workspace/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.2370522910
Short name T7
Test name
Test status
Simulation time 34980010465 ps
CPU time 55.35 seconds
Started Apr 25 12:46:32 PM PDT 24
Finished Apr 25 12:47:29 PM PDT 24
Peak memory 191792 kb
Host smart-27bf2126-f97a-4c4d-a424-3245e26fb809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370522910 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.2370522910
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.820705555
Short name T36
Test name
Test status
Simulation time 8612584905 ps
CPU time 4.04 seconds
Started Apr 25 12:46:55 PM PDT 24
Finished Apr 25 12:47:01 PM PDT 24
Peak memory 197844 kb
Host smart-3fbc511f-eea4-42f0-bc9d-8b70a59c300f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820705555 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl
_intg_err.820705555
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.295559995
Short name T83
Test name
Test status
Simulation time 41502512096 ps
CPU time 177.73 seconds
Started Apr 25 12:45:59 PM PDT 24
Finished Apr 25 12:48:58 PM PDT 24
Peak memory 198380 kb
Host smart-68ca3574-d271-4c1f-a2e6-5d61a7dc7601
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295559995 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.295559995
Directory /workspace/9.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.3076672828
Short name T25
Test name
Test status
Simulation time 481968301313 ps
CPU time 1062.47 seconds
Started Apr 25 12:46:07 PM PDT 24
Finished Apr 25 01:03:51 PM PDT 24
Peak memory 204840 kb
Host smart-ccf3b743-68a7-45ca-a1e8-48e6934b27cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076672828 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.3076672828
Directory /workspace/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.3986230883
Short name T53
Test name
Test status
Simulation time 345208045 ps
CPU time 1.12 seconds
Started Apr 25 12:46:51 PM PDT 24
Finished Apr 25 12:46:52 PM PDT 24
Peak memory 183556 kb
Host smart-4bbf0cb0-33d9-4a91-a667-8bf8af68050e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986230883 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.3986230883
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.3952241131
Short name T16
Test name
Test status
Simulation time 3750494704 ps
CPU time 2.39 seconds
Started Apr 25 12:45:57 PM PDT 24
Finished Apr 25 12:46:01 PM PDT 24
Peak memory 214916 kb
Host smart-fd6f535d-d877-41c4-bfde-d499fd448ddb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952241131 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.3952241131
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.3747134948
Short name T12
Test name
Test status
Simulation time 385770229234 ps
CPU time 336.94 seconds
Started Apr 25 12:46:07 PM PDT 24
Finished Apr 25 12:51:45 PM PDT 24
Peak memory 194788 kb
Host smart-1ee9dc39-1b53-4bb8-a379-b5def373423b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747134948 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_
all.3747134948
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.1253592707
Short name T35
Test name
Test status
Simulation time 8641270725 ps
CPU time 12.83 seconds
Started Apr 25 12:46:38 PM PDT 24
Finished Apr 25 12:46:52 PM PDT 24
Peak memory 197836 kb
Host smart-2c060947-0bc1-45e0-99eb-2d5c2f0e9f95
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253592707 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl
_intg_err.1253592707
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.1036275237
Short name T164
Test name
Test status
Simulation time 43467613892 ps
CPU time 356.52 seconds
Started Apr 25 12:45:56 PM PDT 24
Finished Apr 25 12:51:54 PM PDT 24
Peak memory 198480 kb
Host smart-ea284ca5-652e-46be-a304-3684322e801c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036275237 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.1036275237
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.1044894146
Short name T404
Test name
Test status
Simulation time 698553117 ps
CPU time 1.91 seconds
Started Apr 25 12:46:37 PM PDT 24
Finished Apr 25 12:46:40 PM PDT 24
Peak memory 183668 kb
Host smart-347003d6-e890-4cd6-b120-e0747881fbc5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044894146 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_a
liasing.1044894146
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.2200892406
Short name T289
Test name
Test status
Simulation time 7006580679 ps
CPU time 10.93 seconds
Started Apr 25 12:46:33 PM PDT 24
Finished Apr 25 12:46:46 PM PDT 24
Peak memory 192040 kb
Host smart-fc6ad0c7-bdb0-403d-9c3f-b76a1dbf2ed4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200892406 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_b
it_bash.2200892406
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.330465802
Short name T331
Test name
Test status
Simulation time 1154080278 ps
CPU time 1.34 seconds
Started Apr 25 12:46:38 PM PDT 24
Finished Apr 25 12:46:41 PM PDT 24
Peak memory 183720 kb
Host smart-1b8c0801-054d-4abe-b5be-a41fac7b3b9f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330465802 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_hw
_reset.330465802
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.2892375554
Short name T305
Test name
Test status
Simulation time 517964706 ps
CPU time 0.86 seconds
Started Apr 25 12:46:38 PM PDT 24
Finished Apr 25 12:46:41 PM PDT 24
Peak memory 195784 kb
Host smart-ad7b733e-d52c-4722-a165-420d3d7fc00c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892375554 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.2892375554
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.3913981118
Short name T54
Test name
Test status
Simulation time 386286326 ps
CPU time 0.81 seconds
Started Apr 25 12:46:37 PM PDT 24
Finished Apr 25 12:46:39 PM PDT 24
Peak memory 193056 kb
Host smart-94892a7e-3229-4598-a404-44a0c1073600
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913981118 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.3913981118
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.925086716
Short name T313
Test name
Test status
Simulation time 422184880 ps
CPU time 0.86 seconds
Started Apr 25 12:46:32 PM PDT 24
Finished Apr 25 12:46:35 PM PDT 24
Peak memory 183560 kb
Host smart-f5ea71fd-83cd-48ac-8d12-acd7f00aa45a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925086716 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.925086716
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.346884992
Short name T282
Test name
Test status
Simulation time 409199920 ps
CPU time 0.57 seconds
Started Apr 25 12:46:38 PM PDT 24
Finished Apr 25 12:46:41 PM PDT 24
Peak memory 183504 kb
Host smart-5e39095f-f388-46b6-8d0e-cdc42468c9e8
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346884992 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_ti
mer_mem_partial_access.346884992
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.1638022196
Short name T317
Test name
Test status
Simulation time 310763998 ps
CPU time 0.92 seconds
Started Apr 25 12:46:34 PM PDT 24
Finished Apr 25 12:46:36 PM PDT 24
Peak memory 183564 kb
Host smart-f5534882-dd2e-4441-a7c3-f58ed1eb8903
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638022196 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_w
alk.1638022196
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.1498537259
Short name T405
Test name
Test status
Simulation time 1802019811 ps
CPU time 1.71 seconds
Started Apr 25 12:46:37 PM PDT 24
Finished Apr 25 12:46:40 PM PDT 24
Peak memory 193440 kb
Host smart-ffb4ebb7-ed14-4875-a89a-85b38edcf7bf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498537259 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon
_timer_same_csr_outstanding.1498537259
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.374157718
Short name T322
Test name
Test status
Simulation time 392504426 ps
CPU time 1.04 seconds
Started Apr 25 12:46:34 PM PDT 24
Finished Apr 25 12:46:36 PM PDT 24
Peak memory 198128 kb
Host smart-0bdf6813-0175-4bb5-b7cb-0dcdab1dc8ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374157718 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.374157718
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.2837647758
Short name T382
Test name
Test status
Simulation time 7756216287 ps
CPU time 7.67 seconds
Started Apr 25 12:46:35 PM PDT 24
Finished Apr 25 12:46:43 PM PDT 24
Peak memory 197852 kb
Host smart-415fd004-8a73-4d66-85a6-0d110c99b4d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837647758 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl
_intg_err.2837647758
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.2725571672
Short name T60
Test name
Test status
Simulation time 595208221 ps
CPU time 1.06 seconds
Started Apr 25 12:46:40 PM PDT 24
Finished Apr 25 12:46:43 PM PDT 24
Peak memory 183616 kb
Host smart-f6f008ae-17b9-4a62-b6c2-3d096030b4f6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725571672 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_a
liasing.2725571672
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.158578004
Short name T370
Test name
Test status
Simulation time 7155169765 ps
CPU time 8.53 seconds
Started Apr 25 12:46:36 PM PDT 24
Finished Apr 25 12:46:46 PM PDT 24
Peak memory 195844 kb
Host smart-a0db6a10-3874-43b9-a60a-41831db03b9f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158578004 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_bi
t_bash.158578004
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.1381296455
Short name T407
Test name
Test status
Simulation time 1431384394 ps
CPU time 0.68 seconds
Started Apr 25 12:46:37 PM PDT 24
Finished Apr 25 12:46:39 PM PDT 24
Peak memory 193056 kb
Host smart-bf687038-2fd3-4502-b843-5d64f0651896
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381296455 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_h
w_reset.1381296455
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.3675667384
Short name T345
Test name
Test status
Simulation time 626697358 ps
CPU time 1.13 seconds
Started Apr 25 12:46:38 PM PDT 24
Finished Apr 25 12:46:41 PM PDT 24
Peak memory 195692 kb
Host smart-7df3f008-b913-4477-9092-7c8715122b42
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675667384 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.3675667384
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.4036807426
Short name T56
Test name
Test status
Simulation time 395683674 ps
CPU time 0.82 seconds
Started Apr 25 12:46:38 PM PDT 24
Finished Apr 25 12:46:41 PM PDT 24
Peak memory 183676 kb
Host smart-1377a147-a6a4-4943-83b2-54be40cc9783
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036807426 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.4036807426
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.2062284306
Short name T294
Test name
Test status
Simulation time 382013357 ps
CPU time 1.1 seconds
Started Apr 25 12:46:38 PM PDT 24
Finished Apr 25 12:46:41 PM PDT 24
Peak memory 183580 kb
Host smart-bc613a3f-876f-401a-a38e-0a8dda6d7551
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062284306 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.2062284306
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.2183226048
Short name T311
Test name
Test status
Simulation time 320400610 ps
CPU time 0.61 seconds
Started Apr 25 12:46:39 PM PDT 24
Finished Apr 25 12:46:41 PM PDT 24
Peak memory 183408 kb
Host smart-6401f0e7-3df7-4cca-bbb3-bbcd85fc5019
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183226048 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_t
imer_mem_partial_access.2183226048
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.567380392
Short name T412
Test name
Test status
Simulation time 514964074 ps
CPU time 0.54 seconds
Started Apr 25 12:46:38 PM PDT 24
Finished Apr 25 12:46:40 PM PDT 24
Peak memory 183580 kb
Host smart-96837fcd-f294-40a5-bda7-76fc41a622ff
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567380392 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_wa
lk.567380392
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.3928636808
Short name T347
Test name
Test status
Simulation time 2203124188 ps
CPU time 2.33 seconds
Started Apr 25 12:46:39 PM PDT 24
Finished Apr 25 12:46:43 PM PDT 24
Peak memory 194704 kb
Host smart-d8595371-b345-4db3-a271-42245cb96639
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928636808 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon
_timer_same_csr_outstanding.3928636808
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.1850739211
Short name T377
Test name
Test status
Simulation time 481146482 ps
CPU time 2.25 seconds
Started Apr 25 12:46:39 PM PDT 24
Finished Apr 25 12:46:43 PM PDT 24
Peak memory 198468 kb
Host smart-9fbb2748-30e0-4812-a834-cdcd4b407335
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850739211 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.1850739211
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.2953394386
Short name T108
Test name
Test status
Simulation time 4414379099 ps
CPU time 4.03 seconds
Started Apr 25 12:46:40 PM PDT 24
Finished Apr 25 12:46:45 PM PDT 24
Peak memory 197508 kb
Host smart-cf4a2c46-31a6-4f6b-94a0-91d2fddb9d60
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953394386 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl
_intg_err.2953394386
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.3262214714
Short name T329
Test name
Test status
Simulation time 480828896 ps
CPU time 1.18 seconds
Started Apr 25 12:46:47 PM PDT 24
Finished Apr 25 12:46:50 PM PDT 24
Peak memory 195716 kb
Host smart-72f8153b-a41b-4763-b411-3d431e3836e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262214714 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.3262214714
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.3522175329
Short name T61
Test name
Test status
Simulation time 338308042 ps
CPU time 0.69 seconds
Started Apr 25 12:46:54 PM PDT 24
Finished Apr 25 12:46:57 PM PDT 24
Peak memory 193012 kb
Host smart-29163e33-f678-40f4-abec-d200f66ea8d5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522175329 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.3522175329
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.4228802670
Short name T302
Test name
Test status
Simulation time 412384702 ps
CPU time 1.24 seconds
Started Apr 25 12:46:53 PM PDT 24
Finished Apr 25 12:46:55 PM PDT 24
Peak memory 183576 kb
Host smart-68704cf4-9ffa-49cf-9500-b5a138baa914
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228802670 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.4228802670
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.4054176005
Short name T352
Test name
Test status
Simulation time 1321695475 ps
CPU time 1.09 seconds
Started Apr 25 12:46:52 PM PDT 24
Finished Apr 25 12:46:54 PM PDT 24
Peak memory 193184 kb
Host smart-fcf1d402-c27a-4349-af6c-e0b5836eacc8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054176005 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.ao
n_timer_same_csr_outstanding.4054176005
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.126220961
Short name T330
Test name
Test status
Simulation time 769350869 ps
CPU time 1.73 seconds
Started Apr 25 12:46:55 PM PDT 24
Finished Apr 25 12:46:58 PM PDT 24
Peak memory 198376 kb
Host smart-6fb66548-85cd-4230-83b0-857068ad95f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126220961 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.126220961
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.974854739
Short name T107
Test name
Test status
Simulation time 4217407419 ps
CPU time 7.88 seconds
Started Apr 25 12:46:51 PM PDT 24
Finished Apr 25 12:47:01 PM PDT 24
Peak memory 197652 kb
Host smart-b6ab05d3-dea3-4ca5-8fbf-f23cad4c61f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974854739 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl
_intg_err.974854739
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.2262809227
Short name T411
Test name
Test status
Simulation time 604944159 ps
CPU time 0.87 seconds
Started Apr 25 12:46:53 PM PDT 24
Finished Apr 25 12:46:55 PM PDT 24
Peak memory 196284 kb
Host smart-ca78be02-9e79-4c5a-918c-c0d74db3df36
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262809227 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.2262809227
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.863022197
Short name T309
Test name
Test status
Simulation time 575832017 ps
CPU time 0.79 seconds
Started Apr 25 12:46:52 PM PDT 24
Finished Apr 25 12:46:54 PM PDT 24
Peak memory 192904 kb
Host smart-f176b510-7ebc-4f3f-9eb3-0f6d44e32ba1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863022197 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.863022197
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.3756562962
Short name T332
Test name
Test status
Simulation time 406255395 ps
CPU time 0.58 seconds
Started Apr 25 12:46:59 PM PDT 24
Finished Apr 25 12:47:00 PM PDT 24
Peak memory 183564 kb
Host smart-086b68b6-da0e-4451-8f86-a17df7e6ff04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756562962 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.3756562962
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.611694371
Short name T34
Test name
Test status
Simulation time 1572845390 ps
CPU time 3.72 seconds
Started Apr 25 12:46:51 PM PDT 24
Finished Apr 25 12:46:55 PM PDT 24
Peak memory 193220 kb
Host smart-814e07fd-2e75-410d-89a6-56148df91842
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611694371 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon
_timer_same_csr_outstanding.611694371
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.1174685643
Short name T293
Test name
Test status
Simulation time 736904254 ps
CPU time 1.35 seconds
Started Apr 25 12:46:54 PM PDT 24
Finished Apr 25 12:46:56 PM PDT 24
Peak memory 198468 kb
Host smart-95ef634d-5b78-47d9-aee0-3b105c881b2b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174685643 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.1174685643
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.3899235587
Short name T400
Test name
Test status
Simulation time 4294719493 ps
CPU time 6.86 seconds
Started Apr 25 12:46:54 PM PDT 24
Finished Apr 25 12:47:02 PM PDT 24
Peak memory 197588 kb
Host smart-8556156f-26c8-4257-a484-0391be965e2b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899235587 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_t
l_intg_err.3899235587
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.2415102682
Short name T29
Test name
Test status
Simulation time 514180643 ps
CPU time 0.98 seconds
Started Apr 25 12:46:53 PM PDT 24
Finished Apr 25 12:46:55 PM PDT 24
Peak memory 195740 kb
Host smart-e2541b72-58e3-45ac-83d5-4b14dd12ba9c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415102682 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.2415102682
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.2449964281
Short name T389
Test name
Test status
Simulation time 354937923 ps
CPU time 0.82 seconds
Started Apr 25 12:46:48 PM PDT 24
Finished Apr 25 12:46:51 PM PDT 24
Peak memory 183568 kb
Host smart-6b34c307-e3d4-4cb7-8892-e20c3df1f742
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449964281 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.2449964281
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.955347091
Short name T74
Test name
Test status
Simulation time 2252164338 ps
CPU time 3.35 seconds
Started Apr 25 12:46:55 PM PDT 24
Finished Apr 25 12:47:00 PM PDT 24
Peak memory 183836 kb
Host smart-fadcd45c-6ffe-4e64-8b9c-927481f694d4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955347091 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon
_timer_same_csr_outstanding.955347091
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.4281440290
Short name T387
Test name
Test status
Simulation time 490923412 ps
CPU time 1.33 seconds
Started Apr 25 12:46:55 PM PDT 24
Finished Apr 25 12:46:58 PM PDT 24
Peak memory 198344 kb
Host smart-e50d8fe3-d868-4f4a-b947-574cce71849b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281440290 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.4281440290
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.2325571002
Short name T420
Test name
Test status
Simulation time 7543162920 ps
CPU time 12.3 seconds
Started Apr 25 12:47:06 PM PDT 24
Finished Apr 25 12:47:19 PM PDT 24
Peak memory 197964 kb
Host smart-327173e7-7d13-4d4b-86fe-0d094f735fca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325571002 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_t
l_intg_err.2325571002
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.3619266837
Short name T360
Test name
Test status
Simulation time 451471399 ps
CPU time 0.99 seconds
Started Apr 25 12:46:51 PM PDT 24
Finished Apr 25 12:46:53 PM PDT 24
Peak memory 195716 kb
Host smart-bce5c26f-0c9d-4dad-a9ac-6a1ca0d4d2d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619266837 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.3619266837
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.3858862573
Short name T30
Test name
Test status
Simulation time 398235428 ps
CPU time 0.86 seconds
Started Apr 25 12:46:51 PM PDT 24
Finished Apr 25 12:46:54 PM PDT 24
Peak memory 183640 kb
Host smart-4ed3deae-ab00-4d8f-9371-f725f06751c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858862573 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.3858862573
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.4247108702
Short name T392
Test name
Test status
Simulation time 347223565 ps
CPU time 0.64 seconds
Started Apr 25 12:46:51 PM PDT 24
Finished Apr 25 12:46:53 PM PDT 24
Peak memory 183556 kb
Host smart-3bc85875-cfc7-4a98-afdc-02cb87a14d2b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247108702 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.4247108702
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.143693122
Short name T378
Test name
Test status
Simulation time 1175535800 ps
CPU time 1.15 seconds
Started Apr 25 12:46:54 PM PDT 24
Finished Apr 25 12:46:57 PM PDT 24
Peak memory 193160 kb
Host smart-ed1a8594-eff2-4c72-af26-3f2daedabc04
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143693122 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon
_timer_same_csr_outstanding.143693122
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.52820660
Short name T362
Test name
Test status
Simulation time 431750571 ps
CPU time 2.4 seconds
Started Apr 25 12:46:49 PM PDT 24
Finished Apr 25 12:46:53 PM PDT 24
Peak memory 198448 kb
Host smart-20325201-aacd-4e3c-9210-dcebe25ea575
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52820660 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.52820660
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.3822182705
Short name T320
Test name
Test status
Simulation time 539654787 ps
CPU time 1.12 seconds
Started Apr 25 12:46:53 PM PDT 24
Finished Apr 25 12:46:56 PM PDT 24
Peak memory 198232 kb
Host smart-cabc3b03-8ab2-4c22-a26d-959c08742584
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822182705 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.3822182705
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.598801858
Short name T59
Test name
Test status
Simulation time 447214020 ps
CPU time 1.09 seconds
Started Apr 25 12:46:55 PM PDT 24
Finished Apr 25 12:46:58 PM PDT 24
Peak memory 183636 kb
Host smart-3853b802-6f75-4635-8da4-7e55b6c8c7e0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598801858 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.598801858
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.4161561295
Short name T341
Test name
Test status
Simulation time 576424417 ps
CPU time 0.6 seconds
Started Apr 25 12:46:55 PM PDT 24
Finished Apr 25 12:46:57 PM PDT 24
Peak memory 183552 kb
Host smart-3d76d35c-374f-4fb1-8ae0-80fcd62eeefa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161561295 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.4161561295
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.4193494712
Short name T343
Test name
Test status
Simulation time 1429595971 ps
CPU time 1.07 seconds
Started Apr 25 12:46:51 PM PDT 24
Finished Apr 25 12:46:54 PM PDT 24
Peak memory 193224 kb
Host smart-2155f591-0a5b-4e23-80b5-a72611bc5f9f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193494712 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao
n_timer_same_csr_outstanding.4193494712
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.2325316558
Short name T334
Test name
Test status
Simulation time 506176550 ps
CPU time 2.37 seconds
Started Apr 25 12:46:50 PM PDT 24
Finished Apr 25 12:46:53 PM PDT 24
Peak memory 198448 kb
Host smart-0c712863-ef54-4936-9c5c-194a3a2dc46d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325316558 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.2325316558
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.2308607837
Short name T401
Test name
Test status
Simulation time 4039956871 ps
CPU time 6.87 seconds
Started Apr 25 12:46:55 PM PDT 24
Finished Apr 25 12:47:04 PM PDT 24
Peak memory 196056 kb
Host smart-304a3d56-7a8d-4556-b31c-2acb99c94c11
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308607837 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_t
l_intg_err.2308607837
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.3692728244
Short name T376
Test name
Test status
Simulation time 471827414 ps
CPU time 1 seconds
Started Apr 25 12:46:51 PM PDT 24
Finished Apr 25 12:46:54 PM PDT 24
Peak memory 198140 kb
Host smart-d972fe84-2b98-4247-a19d-9c6c9282edb7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692728244 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.3692728244
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.928718175
Short name T419
Test name
Test status
Simulation time 461730063 ps
CPU time 0.75 seconds
Started Apr 25 12:46:50 PM PDT 24
Finished Apr 25 12:46:52 PM PDT 24
Peak memory 192944 kb
Host smart-4eecc12f-10ee-491e-a428-10f3ac2e6425
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928718175 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.928718175
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.2655786712
Short name T394
Test name
Test status
Simulation time 349828548 ps
CPU time 0.78 seconds
Started Apr 25 12:46:59 PM PDT 24
Finished Apr 25 12:47:01 PM PDT 24
Peak memory 183520 kb
Host smart-8435c8c4-90fb-4f2c-b1de-1eded86283f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655786712 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.2655786712
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.2916529417
Short name T72
Test name
Test status
Simulation time 2498475396 ps
CPU time 1.72 seconds
Started Apr 25 12:46:51 PM PDT 24
Finished Apr 25 12:46:54 PM PDT 24
Peak memory 194336 kb
Host smart-4ff1bb17-dc67-43ca-908b-635961bd53fb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916529417 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.ao
n_timer_same_csr_outstanding.2916529417
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.1859726060
Short name T318
Test name
Test status
Simulation time 555605628 ps
CPU time 1.52 seconds
Started Apr 25 12:46:57 PM PDT 24
Finished Apr 25 12:47:00 PM PDT 24
Peak memory 198368 kb
Host smart-3ae62539-0820-4ca3-985b-925d3ccf243a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859726060 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.1859726060
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.3754300332
Short name T344
Test name
Test status
Simulation time 4286953080 ps
CPU time 7.27 seconds
Started Apr 25 12:46:49 PM PDT 24
Finished Apr 25 12:46:58 PM PDT 24
Peak memory 197308 kb
Host smart-68f13e43-37f2-4c42-b5ba-7faf4a3bf561
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754300332 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_t
l_intg_err.3754300332
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.1845508797
Short name T366
Test name
Test status
Simulation time 531475556 ps
CPU time 0.98 seconds
Started Apr 25 12:46:57 PM PDT 24
Finished Apr 25 12:46:59 PM PDT 24
Peak memory 195056 kb
Host smart-bb93682f-5848-432d-9bdf-516646bef5d0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845508797 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.1845508797
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.306258677
Short name T338
Test name
Test status
Simulation time 310864920 ps
CPU time 0.65 seconds
Started Apr 25 12:46:55 PM PDT 24
Finished Apr 25 12:46:57 PM PDT 24
Peak memory 192960 kb
Host smart-e5892910-a894-48a9-bc35-b937297993b2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306258677 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.306258677
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.1635921664
Short name T361
Test name
Test status
Simulation time 307152661 ps
CPU time 0.69 seconds
Started Apr 25 12:46:51 PM PDT 24
Finished Apr 25 12:46:52 PM PDT 24
Peak memory 183576 kb
Host smart-5301877a-ade5-4c40-a611-5252b39d1fa8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635921664 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.1635921664
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.2894544961
Short name T78
Test name
Test status
Simulation time 2422212879 ps
CPU time 1.52 seconds
Started Apr 25 12:46:54 PM PDT 24
Finished Apr 25 12:46:57 PM PDT 24
Peak memory 191868 kb
Host smart-2bc53d85-232f-4af1-928b-04b3e120bf22
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894544961 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.ao
n_timer_same_csr_outstanding.2894544961
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.2461173403
Short name T296
Test name
Test status
Simulation time 472294693 ps
CPU time 2.35 seconds
Started Apr 25 12:46:49 PM PDT 24
Finished Apr 25 12:46:52 PM PDT 24
Peak memory 198384 kb
Host smart-8f6926e7-859c-46fe-8165-ec8bd47e6e6a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461173403 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.2461173403
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.2590186482
Short name T390
Test name
Test status
Simulation time 4476248546 ps
CPU time 2.33 seconds
Started Apr 25 12:46:49 PM PDT 24
Finished Apr 25 12:46:52 PM PDT 24
Peak memory 196456 kb
Host smart-50e6a1dd-0387-48b7-816a-ed41e362f4e2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590186482 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_t
l_intg_err.2590186482
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.718094343
Short name T319
Test name
Test status
Simulation time 462542760 ps
CPU time 0.89 seconds
Started Apr 25 12:47:07 PM PDT 24
Finished Apr 25 12:47:10 PM PDT 24
Peak memory 196668 kb
Host smart-6c9393ef-c98c-47ea-b29a-ce0010b2082c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718094343 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.718094343
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.1019835206
Short name T71
Test name
Test status
Simulation time 462708329 ps
CPU time 0.76 seconds
Started Apr 25 12:46:55 PM PDT 24
Finished Apr 25 12:46:57 PM PDT 24
Peak memory 183796 kb
Host smart-24609c4c-f8d1-44ea-96b6-59964bd9f3ff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019835206 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.1019835206
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.1295399680
Short name T348
Test name
Test status
Simulation time 420693932 ps
CPU time 0.96 seconds
Started Apr 25 12:46:57 PM PDT 24
Finished Apr 25 12:46:59 PM PDT 24
Peak memory 183564 kb
Host smart-4c09f5ef-423a-40b5-b5e4-43480f4af756
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295399680 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.1295399680
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.2410027349
Short name T416
Test name
Test status
Simulation time 3024656472 ps
CPU time 0.91 seconds
Started Apr 25 12:47:08 PM PDT 24
Finished Apr 25 12:47:10 PM PDT 24
Peak memory 191936 kb
Host smart-ddebc842-b661-424b-bee9-26fd8a31a0fd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410027349 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.ao
n_timer_same_csr_outstanding.2410027349
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.4216289048
Short name T353
Test name
Test status
Simulation time 593131394 ps
CPU time 1.33 seconds
Started Apr 25 12:46:55 PM PDT 24
Finished Apr 25 12:46:58 PM PDT 24
Peak memory 198440 kb
Host smart-6dae3f72-461d-419f-911d-616377b67b64
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216289048 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.4216289048
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.185821913
Short name T315
Test name
Test status
Simulation time 4424270152 ps
CPU time 1.71 seconds
Started Apr 25 12:46:58 PM PDT 24
Finished Apr 25 12:47:00 PM PDT 24
Peak memory 197580 kb
Host smart-0a985a62-82f3-4177-8f20-03986f6d1d83
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185821913 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl
_intg_err.185821913
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.3153934892
Short name T310
Test name
Test status
Simulation time 579444828 ps
CPU time 0.96 seconds
Started Apr 25 12:47:04 PM PDT 24
Finished Apr 25 12:47:06 PM PDT 24
Peak memory 197008 kb
Host smart-986d2bc1-ad55-4f6a-a836-25067224bbca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153934892 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.3153934892
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.1680624400
Short name T75
Test name
Test status
Simulation time 550116674 ps
CPU time 0.76 seconds
Started Apr 25 12:46:53 PM PDT 24
Finished Apr 25 12:46:55 PM PDT 24
Peak memory 183544 kb
Host smart-123bf0c4-9c1f-43c7-995b-9ce3a2354846
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680624400 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.1680624400
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.2272957796
Short name T303
Test name
Test status
Simulation time 407980991 ps
CPU time 0.77 seconds
Started Apr 25 12:46:53 PM PDT 24
Finished Apr 25 12:46:55 PM PDT 24
Peak memory 183460 kb
Host smart-fa1e63c6-e5ef-4294-92f3-46709cf456f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272957796 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.2272957796
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.2189158751
Short name T367
Test name
Test status
Simulation time 972918627 ps
CPU time 2.59 seconds
Started Apr 25 12:46:59 PM PDT 24
Finished Apr 25 12:47:03 PM PDT 24
Peak memory 193212 kb
Host smart-82057816-5188-43cb-8980-661d0c63bfca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189158751 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.ao
n_timer_same_csr_outstanding.2189158751
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.1249008101
Short name T304
Test name
Test status
Simulation time 454240959 ps
CPU time 2.08 seconds
Started Apr 25 12:46:57 PM PDT 24
Finished Apr 25 12:47:00 PM PDT 24
Peak memory 198376 kb
Host smart-20f955b0-4a48-40b0-a9a0-07ce27c20514
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249008101 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.1249008101
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.620092274
Short name T393
Test name
Test status
Simulation time 8103964585 ps
CPU time 13.48 seconds
Started Apr 25 12:46:55 PM PDT 24
Finished Apr 25 12:47:10 PM PDT 24
Peak memory 198000 kb
Host smart-2c4e6be5-7c60-4a4e-a667-83f824b071ad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620092274 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl
_intg_err.620092274
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.1983003224
Short name T306
Test name
Test status
Simulation time 1146559789 ps
CPU time 1.53 seconds
Started Apr 25 12:46:54 PM PDT 24
Finished Apr 25 12:46:56 PM PDT 24
Peak memory 198368 kb
Host smart-a59867d1-2c5e-4316-bbba-ee9c0e1e83ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983003224 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.1983003224
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.1890934012
Short name T369
Test name
Test status
Simulation time 453649238 ps
CPU time 0.87 seconds
Started Apr 25 12:46:55 PM PDT 24
Finished Apr 25 12:46:58 PM PDT 24
Peak memory 193040 kb
Host smart-e66ac188-1d4b-4841-a24f-f18b40a2a695
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890934012 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.1890934012
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.2270887482
Short name T379
Test name
Test status
Simulation time 422506257 ps
CPU time 0.63 seconds
Started Apr 25 12:47:00 PM PDT 24
Finished Apr 25 12:47:02 PM PDT 24
Peak memory 183468 kb
Host smart-4f30ec1e-1392-4aee-88f3-72806f075a7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270887482 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.2270887482
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.3246461183
Short name T384
Test name
Test status
Simulation time 3073202737 ps
CPU time 1.83 seconds
Started Apr 25 12:47:02 PM PDT 24
Finished Apr 25 12:47:05 PM PDT 24
Peak memory 194704 kb
Host smart-a6565213-cebd-41ea-a8c9-b54776e6877c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246461183 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao
n_timer_same_csr_outstanding.3246461183
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.2567874143
Short name T396
Test name
Test status
Simulation time 360624717 ps
CPU time 1.66 seconds
Started Apr 25 12:46:52 PM PDT 24
Finished Apr 25 12:46:55 PM PDT 24
Peak memory 198456 kb
Host smart-d5bbd687-0e40-4c6c-912d-7ede7b4503bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567874143 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.2567874143
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.4261159792
Short name T358
Test name
Test status
Simulation time 4100213854 ps
CPU time 3.74 seconds
Started Apr 25 12:46:57 PM PDT 24
Finished Apr 25 12:47:02 PM PDT 24
Peak memory 197316 kb
Host smart-428590eb-a4fd-4559-83c8-f1b7d23ab664
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261159792 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_t
l_intg_err.4261159792
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.2470292185
Short name T418
Test name
Test status
Simulation time 610422921 ps
CPU time 0.79 seconds
Started Apr 25 12:46:42 PM PDT 24
Finished Apr 25 12:46:44 PM PDT 24
Peak memory 193148 kb
Host smart-fd2113cf-fa96-4fd5-b1e6-20ca4ffcc465
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470292185 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_a
liasing.2470292185
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.3248260984
Short name T52
Test name
Test status
Simulation time 13864294459 ps
CPU time 30.66 seconds
Started Apr 25 12:46:38 PM PDT 24
Finished Apr 25 12:47:10 PM PDT 24
Peak memory 192152 kb
Host smart-14643abc-3f9d-4a0b-80a7-d32959b43f92
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248260984 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_b
it_bash.3248260984
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.3165957759
Short name T391
Test name
Test status
Simulation time 637354101 ps
CPU time 1.46 seconds
Started Apr 25 12:46:36 PM PDT 24
Finished Apr 25 12:46:38 PM PDT 24
Peak memory 183620 kb
Host smart-d0aa84bf-6609-45f5-bcc8-54edc1ea9cb1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165957759 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_h
w_reset.3165957759
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.2203098009
Short name T385
Test name
Test status
Simulation time 396555935 ps
CPU time 1.12 seconds
Started Apr 25 12:46:37 PM PDT 24
Finished Apr 25 12:46:39 PM PDT 24
Peak memory 195628 kb
Host smart-c6ac4a5a-3e3e-4c39-894c-208cadd3e8e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203098009 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.2203098009
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.95687148
Short name T57
Test name
Test status
Simulation time 307476833 ps
CPU time 1.02 seconds
Started Apr 25 12:46:38 PM PDT 24
Finished Apr 25 12:46:41 PM PDT 24
Peak memory 183740 kb
Host smart-5fec0386-04dc-476f-bf2c-43eb361340bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95687148 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.95687148
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.1474708510
Short name T337
Test name
Test status
Simulation time 395372928 ps
CPU time 0.64 seconds
Started Apr 25 12:46:39 PM PDT 24
Finished Apr 25 12:46:42 PM PDT 24
Peak memory 183540 kb
Host smart-41cefc15-9973-4d28-b65c-00ee7e9a4438
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474708510 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.1474708510
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.418624584
Short name T346
Test name
Test status
Simulation time 507505990 ps
CPU time 1.12 seconds
Started Apr 25 12:46:36 PM PDT 24
Finished Apr 25 12:46:38 PM PDT 24
Peak memory 183468 kb
Host smart-e47cc782-ce60-41b7-97e2-2d66074b83d7
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418624584 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_ti
mer_mem_partial_access.418624584
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.1649641238
Short name T415
Test name
Test status
Simulation time 313058988 ps
CPU time 0.71 seconds
Started Apr 25 12:46:38 PM PDT 24
Finished Apr 25 12:46:40 PM PDT 24
Peak memory 183568 kb
Host smart-e67fcb67-f72c-4c13-b2d7-cdcbec52728e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649641238 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_w
alk.1649641238
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.1360144377
Short name T77
Test name
Test status
Simulation time 2426670416 ps
CPU time 1.36 seconds
Started Apr 25 12:46:43 PM PDT 24
Finished Apr 25 12:46:46 PM PDT 24
Peak memory 194304 kb
Host smart-e6d6a139-cbb2-4e42-803c-8e8a2199c71d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360144377 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon
_timer_same_csr_outstanding.1360144377
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.3478084337
Short name T342
Test name
Test status
Simulation time 431751508 ps
CPU time 2.53 seconds
Started Apr 25 12:46:35 PM PDT 24
Finished Apr 25 12:46:39 PM PDT 24
Peak memory 198404 kb
Host smart-f1056b9c-c8cd-4607-afd1-bf5d4bc30bfe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478084337 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.3478084337
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.2294130484
Short name T336
Test name
Test status
Simulation time 332362112 ps
CPU time 1.03 seconds
Started Apr 25 12:46:58 PM PDT 24
Finished Apr 25 12:47:00 PM PDT 24
Peak memory 183440 kb
Host smart-2fc84ed0-59a5-413d-81e5-63c7d5b2a710
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294130484 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.2294130484
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.4283878544
Short name T356
Test name
Test status
Simulation time 321527885 ps
CPU time 0.65 seconds
Started Apr 25 12:46:59 PM PDT 24
Finished Apr 25 12:47:00 PM PDT 24
Peak memory 183548 kb
Host smart-844ca8ae-35a2-4826-8b46-049cde7916ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283878544 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.4283878544
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.2986944165
Short name T413
Test name
Test status
Simulation time 522830312 ps
CPU time 0.74 seconds
Started Apr 25 12:46:53 PM PDT 24
Finished Apr 25 12:46:55 PM PDT 24
Peak memory 183576 kb
Host smart-667c8150-461c-442e-bbf4-37e3fe56d367
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986944165 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.2986944165
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.609793162
Short name T381
Test name
Test status
Simulation time 328802802 ps
CPU time 0.83 seconds
Started Apr 25 12:46:55 PM PDT 24
Finished Apr 25 12:46:57 PM PDT 24
Peak memory 183544 kb
Host smart-4390c37b-4e79-48cb-abb3-8d7651b058f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609793162 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.609793162
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.3533375438
Short name T406
Test name
Test status
Simulation time 389796444 ps
CPU time 1.08 seconds
Started Apr 25 12:46:57 PM PDT 24
Finished Apr 25 12:46:59 PM PDT 24
Peak memory 183436 kb
Host smart-e9cc83a8-aee8-43fb-ac53-fbce225f34b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533375438 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.3533375438
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.2973658267
Short name T288
Test name
Test status
Simulation time 481224955 ps
CPU time 0.56 seconds
Started Apr 25 12:46:59 PM PDT 24
Finished Apr 25 12:47:01 PM PDT 24
Peak memory 183552 kb
Host smart-7590ea07-d4f1-4d49-b263-3ab207d5dd15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973658267 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.2973658267
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.2990523028
Short name T291
Test name
Test status
Simulation time 494561105 ps
CPU time 0.64 seconds
Started Apr 25 12:47:03 PM PDT 24
Finished Apr 25 12:47:05 PM PDT 24
Peak memory 183464 kb
Host smart-4afbd389-6945-40d9-ae36-1a55d7399c23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990523028 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.2990523028
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.803980442
Short name T285
Test name
Test status
Simulation time 468321352 ps
CPU time 1.28 seconds
Started Apr 25 12:46:59 PM PDT 24
Finished Apr 25 12:47:01 PM PDT 24
Peak memory 183552 kb
Host smart-c5b44c75-a66b-4eef-88c8-864b876d63c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803980442 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.803980442
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.2892143706
Short name T316
Test name
Test status
Simulation time 510072438 ps
CPU time 1.34 seconds
Started Apr 25 12:46:55 PM PDT 24
Finished Apr 25 12:46:58 PM PDT 24
Peak memory 183524 kb
Host smart-760ecb40-a9fb-41f6-93af-a6e1a04e9bc3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892143706 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.2892143706
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.3219664798
Short name T290
Test name
Test status
Simulation time 482024487 ps
CPU time 0.68 seconds
Started Apr 25 12:47:04 PM PDT 24
Finished Apr 25 12:47:06 PM PDT 24
Peak memory 183556 kb
Host smart-8ca96e96-0938-4f20-bb0f-e5f813227732
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219664798 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.3219664798
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.3368031981
Short name T49
Test name
Test status
Simulation time 507917031 ps
CPU time 1.07 seconds
Started Apr 25 12:46:43 PM PDT 24
Finished Apr 25 12:46:46 PM PDT 24
Peak memory 183700 kb
Host smart-e4df33da-b676-4be9-ac7d-213883ada730
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368031981 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_a
liasing.3368031981
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.1999355167
Short name T58
Test name
Test status
Simulation time 10774048528 ps
CPU time 16.2 seconds
Started Apr 25 12:46:46 PM PDT 24
Finished Apr 25 12:47:04 PM PDT 24
Peak memory 192052 kb
Host smart-0b35d14b-7a4f-42b2-82e8-f2fcac89754b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999355167 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_b
it_bash.1999355167
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.2352899230
Short name T355
Test name
Test status
Simulation time 703770287 ps
CPU time 1.09 seconds
Started Apr 25 12:46:39 PM PDT 24
Finished Apr 25 12:46:42 PM PDT 24
Peak memory 183616 kb
Host smart-699c53c5-7ff5-437a-8732-3bb747edf1f8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352899230 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_h
w_reset.2352899230
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.3326874718
Short name T314
Test name
Test status
Simulation time 575914911 ps
CPU time 1.54 seconds
Started Apr 25 12:46:43 PM PDT 24
Finished Apr 25 12:46:46 PM PDT 24
Peak memory 195972 kb
Host smart-ef018883-5952-43e8-9179-9073ca762a36
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326874718 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.3326874718
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.2207741948
Short name T50
Test name
Test status
Simulation time 338607082 ps
CPU time 1.03 seconds
Started Apr 25 12:46:46 PM PDT 24
Finished Apr 25 12:46:49 PM PDT 24
Peak memory 192064 kb
Host smart-07e8debd-9228-40d5-bc03-915cee075202
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207741948 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.2207741948
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.4000723534
Short name T371
Test name
Test status
Simulation time 503025616 ps
CPU time 1.38 seconds
Started Apr 25 12:46:36 PM PDT 24
Finished Apr 25 12:46:39 PM PDT 24
Peak memory 183576 kb
Host smart-8f5ed408-fda7-4781-9a2c-b120a8c1e31a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000723534 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.4000723534
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.11881480
Short name T372
Test name
Test status
Simulation time 351548514 ps
CPU time 1.06 seconds
Started Apr 25 12:46:43 PM PDT 24
Finished Apr 25 12:46:46 PM PDT 24
Peak memory 183464 kb
Host smart-fab6bd92-b425-4b92-a5bc-1d417cae2051
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11881480 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_
timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_tim
er_mem_partial_access.11881480
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.1386550783
Short name T292
Test name
Test status
Simulation time 375017945 ps
CPU time 0.97 seconds
Started Apr 25 12:46:35 PM PDT 24
Finished Apr 25 12:46:37 PM PDT 24
Peak memory 183412 kb
Host smart-b4fe3e71-3518-4584-98de-a6a3ddca1e84
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386550783 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_w
alk.1386550783
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.749255922
Short name T386
Test name
Test status
Simulation time 1203607164 ps
CPU time 1.4 seconds
Started Apr 25 12:46:42 PM PDT 24
Finished Apr 25 12:46:45 PM PDT 24
Peak memory 193216 kb
Host smart-504b1481-bf80-4b05-a1b9-6f14a99cac4a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749255922 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_
timer_same_csr_outstanding.749255922
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.1667840082
Short name T403
Test name
Test status
Simulation time 753932339 ps
CPU time 1.86 seconds
Started Apr 25 12:46:43 PM PDT 24
Finished Apr 25 12:46:47 PM PDT 24
Peak memory 198464 kb
Host smart-bd8644f0-c5eb-4ac1-9342-999d3563a828
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667840082 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.1667840082
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.491293186
Short name T37
Test name
Test status
Simulation time 8574063483 ps
CPU time 12.76 seconds
Started Apr 25 12:46:39 PM PDT 24
Finished Apr 25 12:46:54 PM PDT 24
Peak memory 197692 kb
Host smart-90e49c25-cde7-4cff-92d6-f989167df255
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491293186 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_
intg_err.491293186
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.2372220455
Short name T365
Test name
Test status
Simulation time 310550366 ps
CPU time 0.79 seconds
Started Apr 25 12:47:06 PM PDT 24
Finished Apr 25 12:47:08 PM PDT 24
Peak memory 183520 kb
Host smart-1c69f60b-5b93-475a-8789-3e4a21740112
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372220455 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.2372220455
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.2052054737
Short name T333
Test name
Test status
Simulation time 402563658 ps
CPU time 0.62 seconds
Started Apr 25 12:46:53 PM PDT 24
Finished Apr 25 12:46:55 PM PDT 24
Peak memory 183456 kb
Host smart-3fd5fb46-9315-4b6f-b9d8-bfa29bf029cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052054737 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.2052054737
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.1409330474
Short name T374
Test name
Test status
Simulation time 419858967 ps
CPU time 0.87 seconds
Started Apr 25 12:47:03 PM PDT 24
Finished Apr 25 12:47:05 PM PDT 24
Peak memory 183552 kb
Host smart-5eb48683-652b-4ab7-8693-bd20bcd5a484
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409330474 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.1409330474
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.3008123837
Short name T323
Test name
Test status
Simulation time 494814583 ps
CPU time 0.62 seconds
Started Apr 25 12:47:01 PM PDT 24
Finished Apr 25 12:47:03 PM PDT 24
Peak memory 183552 kb
Host smart-3c3f3776-e93d-42b9-a6cd-022adc4b0092
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008123837 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.3008123837
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.3526558369
Short name T410
Test name
Test status
Simulation time 304208572 ps
CPU time 0.73 seconds
Started Apr 25 12:47:00 PM PDT 24
Finished Apr 25 12:47:03 PM PDT 24
Peak memory 183564 kb
Host smart-eeb6160b-fa85-4a30-a37a-a69b9ccf01c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526558369 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.3526558369
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.1865606004
Short name T349
Test name
Test status
Simulation time 503238120 ps
CPU time 1.2 seconds
Started Apr 25 12:47:01 PM PDT 24
Finished Apr 25 12:47:04 PM PDT 24
Peak memory 183532 kb
Host smart-c595b6bd-0347-4ef6-b6e3-6ea917c8e246
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865606004 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.1865606004
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.2193206250
Short name T295
Test name
Test status
Simulation time 348074995 ps
CPU time 0.71 seconds
Started Apr 25 12:47:01 PM PDT 24
Finished Apr 25 12:47:03 PM PDT 24
Peak memory 183576 kb
Host smart-6a601127-6d91-44cc-8c60-91499e5f823c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193206250 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.2193206250
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.3948085195
Short name T383
Test name
Test status
Simulation time 472840270 ps
CPU time 1.27 seconds
Started Apr 25 12:46:59 PM PDT 24
Finished Apr 25 12:47:02 PM PDT 24
Peak memory 183564 kb
Host smart-c491c0c8-510a-487b-9b83-5c6f9ec5c9c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948085195 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.3948085195
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.2812385627
Short name T287
Test name
Test status
Simulation time 413026585 ps
CPU time 0.67 seconds
Started Apr 25 12:47:00 PM PDT 24
Finished Apr 25 12:47:01 PM PDT 24
Peak memory 183540 kb
Host smart-e8f21eeb-b081-4885-ae62-b5e993d05f34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812385627 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.2812385627
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.218844674
Short name T312
Test name
Test status
Simulation time 370186266 ps
CPU time 0.65 seconds
Started Apr 25 12:47:03 PM PDT 24
Finished Apr 25 12:47:04 PM PDT 24
Peak memory 183496 kb
Host smart-4b311423-1239-4e1a-afac-12c6cc1e6b0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218844674 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.218844674
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.3500967174
Short name T55
Test name
Test status
Simulation time 608234361 ps
CPU time 1.05 seconds
Started Apr 25 12:46:46 PM PDT 24
Finished Apr 25 12:46:49 PM PDT 24
Peak memory 191908 kb
Host smart-2b15e8fc-56e6-4729-b7c5-94b681c82462
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500967174 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_a
liasing.3500967174
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.4242087600
Short name T51
Test name
Test status
Simulation time 639458358 ps
CPU time 2.42 seconds
Started Apr 25 12:46:42 PM PDT 24
Finished Apr 25 12:46:46 PM PDT 24
Peak memory 192108 kb
Host smart-50b61f35-96f5-4d35-a0d9-6bd37e507804
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242087600 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_b
it_bash.4242087600
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.2760662182
Short name T38
Test name
Test status
Simulation time 548622736 ps
CPU time 1.29 seconds
Started Apr 25 12:46:45 PM PDT 24
Finished Apr 25 12:46:48 PM PDT 24
Peak memory 183656 kb
Host smart-f66be93c-6f04-4006-ad9d-708e1e819f1b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760662182 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_h
w_reset.2760662182
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.1533739080
Short name T300
Test name
Test status
Simulation time 363035146 ps
CPU time 1.24 seconds
Started Apr 25 12:46:45 PM PDT 24
Finished Apr 25 12:46:49 PM PDT 24
Peak memory 196100 kb
Host smart-c0e941dc-6f07-4567-88f1-4704fef1d25b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533739080 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.1533739080
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.261895261
Short name T408
Test name
Test status
Simulation time 546659203 ps
CPU time 0.87 seconds
Started Apr 25 12:46:40 PM PDT 24
Finished Apr 25 12:46:42 PM PDT 24
Peak memory 183808 kb
Host smart-fc0a3404-f8e2-41bb-9409-f3b3b643324a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261895261 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.261895261
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.2267189991
Short name T281
Test name
Test status
Simulation time 348741893 ps
CPU time 0.7 seconds
Started Apr 25 12:46:43 PM PDT 24
Finished Apr 25 12:46:46 PM PDT 24
Peak memory 183476 kb
Host smart-50c9076d-872a-413e-9cf4-43dd8e86e7fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267189991 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.2267189991
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.1103565545
Short name T308
Test name
Test status
Simulation time 264073067 ps
CPU time 0.87 seconds
Started Apr 25 12:46:41 PM PDT 24
Finished Apr 25 12:46:44 PM PDT 24
Peak memory 183400 kb
Host smart-ddd4d7b5-6e42-46d8-be1c-2266c3ffed76
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103565545 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_t
imer_mem_partial_access.1103565545
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.4198577481
Short name T414
Test name
Test status
Simulation time 473123088 ps
CPU time 1.31 seconds
Started Apr 25 12:46:44 PM PDT 24
Finished Apr 25 12:46:47 PM PDT 24
Peak memory 183456 kb
Host smart-6925520c-a146-4cdb-a035-59838b450f81
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198577481 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_w
alk.4198577481
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.2272452415
Short name T326
Test name
Test status
Simulation time 1270419916 ps
CPU time 1.41 seconds
Started Apr 25 12:46:42 PM PDT 24
Finished Apr 25 12:46:46 PM PDT 24
Peak memory 193044 kb
Host smart-922a3fc2-c866-474f-b7c8-66a9fc96ae17
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272452415 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon
_timer_same_csr_outstanding.2272452415
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.3318147812
Short name T351
Test name
Test status
Simulation time 1342205278 ps
CPU time 1.33 seconds
Started Apr 25 12:46:42 PM PDT 24
Finished Apr 25 12:46:45 PM PDT 24
Peak memory 198524 kb
Host smart-2ed1dc8d-461d-46ae-b43c-8429c068d011
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318147812 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.3318147812
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.3958160249
Short name T104
Test name
Test status
Simulation time 4437536826 ps
CPU time 4.52 seconds
Started Apr 25 12:46:43 PM PDT 24
Finished Apr 25 12:46:50 PM PDT 24
Peak memory 196472 kb
Host smart-22f07f7c-e764-4393-b018-069a6f4f444c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958160249 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl
_intg_err.3958160249
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.3403763976
Short name T350
Test name
Test status
Simulation time 316426638 ps
CPU time 1.04 seconds
Started Apr 25 12:47:00 PM PDT 24
Finished Apr 25 12:47:02 PM PDT 24
Peak memory 183552 kb
Host smart-fede97ad-708c-47b2-9be8-e370cf09ddf3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403763976 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.3403763976
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.2664136494
Short name T399
Test name
Test status
Simulation time 285700812 ps
CPU time 0.97 seconds
Started Apr 25 12:47:01 PM PDT 24
Finished Apr 25 12:47:04 PM PDT 24
Peak memory 183560 kb
Host smart-4217fea5-0ad5-4f77-bec2-404ca421c31f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664136494 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.2664136494
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.2500664990
Short name T409
Test name
Test status
Simulation time 316262302 ps
CPU time 0.75 seconds
Started Apr 25 12:47:04 PM PDT 24
Finished Apr 25 12:47:07 PM PDT 24
Peak memory 183560 kb
Host smart-f2773c50-6e02-41ef-8141-d064add946f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500664990 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.2500664990
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.167611128
Short name T402
Test name
Test status
Simulation time 460055466 ps
CPU time 0.71 seconds
Started Apr 25 12:47:01 PM PDT 24
Finished Apr 25 12:47:03 PM PDT 24
Peak memory 183516 kb
Host smart-6e5e19fe-1fa4-4467-a7f3-996ffc08824d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167611128 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.167611128
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.730020673
Short name T328
Test name
Test status
Simulation time 447857958 ps
CPU time 0.74 seconds
Started Apr 25 12:47:06 PM PDT 24
Finished Apr 25 12:47:08 PM PDT 24
Peak memory 183552 kb
Host smart-9e002374-eda3-4cd0-aed9-2946ef05888b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730020673 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.730020673
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.3617171558
Short name T340
Test name
Test status
Simulation time 511559169 ps
CPU time 1.18 seconds
Started Apr 25 12:47:06 PM PDT 24
Finished Apr 25 12:47:08 PM PDT 24
Peak memory 183452 kb
Host smart-7c170063-69cb-45ce-bdef-af5576d8f5d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617171558 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.3617171558
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.2841816013
Short name T301
Test name
Test status
Simulation time 419891388 ps
CPU time 1.13 seconds
Started Apr 25 12:47:07 PM PDT 24
Finished Apr 25 12:47:10 PM PDT 24
Peak memory 183568 kb
Host smart-b550aa5a-1696-4a42-ba8c-4a9311f1eab9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841816013 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.2841816013
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.2839756506
Short name T417
Test name
Test status
Simulation time 511413265 ps
CPU time 0.92 seconds
Started Apr 25 12:47:04 PM PDT 24
Finished Apr 25 12:47:06 PM PDT 24
Peak memory 183564 kb
Host smart-b04912e1-7b6d-4fdb-a602-6da279dd8303
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839756506 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.2839756506
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.1789231210
Short name T284
Test name
Test status
Simulation time 307035232 ps
CPU time 1.01 seconds
Started Apr 25 12:47:01 PM PDT 24
Finished Apr 25 12:47:04 PM PDT 24
Peak memory 183556 kb
Host smart-1811326f-f7ee-4542-a180-8c0120168f5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789231210 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.1789231210
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.658166023
Short name T398
Test name
Test status
Simulation time 302023948 ps
CPU time 0.68 seconds
Started Apr 25 12:47:03 PM PDT 24
Finished Apr 25 12:47:05 PM PDT 24
Peak memory 183460 kb
Host smart-e64c87b0-9bc0-414c-85fd-da43809a9007
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658166023 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.658166023
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.3492993988
Short name T286
Test name
Test status
Simulation time 566200233 ps
CPU time 1.44 seconds
Started Apr 25 12:46:51 PM PDT 24
Finished Apr 25 12:46:53 PM PDT 24
Peak memory 195748 kb
Host smart-f2c99ffe-cf43-4adc-bc01-99a38d6dd00d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492993988 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.3492993988
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.1648373811
Short name T375
Test name
Test status
Simulation time 526867148 ps
CPU time 0.88 seconds
Started Apr 25 12:46:42 PM PDT 24
Finished Apr 25 12:46:45 PM PDT 24
Peak memory 193096 kb
Host smart-5aaf01d5-36ef-4d46-ae20-e8f989131f00
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648373811 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.1648373811
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.3376974099
Short name T299
Test name
Test status
Simulation time 273337655 ps
CPU time 0.99 seconds
Started Apr 25 12:46:45 PM PDT 24
Finished Apr 25 12:46:48 PM PDT 24
Peak memory 183560 kb
Host smart-9daa5da3-edb4-405e-8f21-b921b7676e8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376974099 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.3376974099
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.27252742
Short name T368
Test name
Test status
Simulation time 1303723794 ps
CPU time 1.02 seconds
Started Apr 25 12:46:42 PM PDT 24
Finished Apr 25 12:46:45 PM PDT 24
Peak memory 193164 kb
Host smart-31cdcc77-9211-41c6-8168-fa28a75dbb3d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27252742 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_t
imer_same_csr_outstanding.27252742
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.3077676320
Short name T357
Test name
Test status
Simulation time 837421498 ps
CPU time 2.12 seconds
Started Apr 25 12:46:41 PM PDT 24
Finished Apr 25 12:46:45 PM PDT 24
Peak memory 198472 kb
Host smart-7dde2cda-7554-4801-81e9-6e74b9db8604
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077676320 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.3077676320
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.3542762830
Short name T105
Test name
Test status
Simulation time 4714455289 ps
CPU time 5.8 seconds
Started Apr 25 12:46:42 PM PDT 24
Finished Apr 25 12:46:50 PM PDT 24
Peak memory 197532 kb
Host smart-3f7f4987-415f-4dfb-a4de-fab70cd7d2bf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542762830 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl
_intg_err.3542762830
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.3235258925
Short name T87
Test name
Test status
Simulation time 625619127 ps
CPU time 1.13 seconds
Started Apr 25 12:46:46 PM PDT 24
Finished Apr 25 12:46:49 PM PDT 24
Peak memory 195908 kb
Host smart-d679e7db-b5bf-4d6c-a2cc-487af4446dea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235258925 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.3235258925
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.3217751530
Short name T73
Test name
Test status
Simulation time 527080297 ps
CPU time 1.27 seconds
Started Apr 25 12:46:44 PM PDT 24
Finished Apr 25 12:46:48 PM PDT 24
Peak memory 183752 kb
Host smart-41b5c34f-aa2c-4b7e-8091-c5261b62e419
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217751530 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.3217751530
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.1999061033
Short name T324
Test name
Test status
Simulation time 504004315 ps
CPU time 0.7 seconds
Started Apr 25 12:46:41 PM PDT 24
Finished Apr 25 12:46:43 PM PDT 24
Peak memory 183504 kb
Host smart-1782d93f-0eec-4a1f-b802-9f68208c05e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999061033 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.1999061033
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.955943775
Short name T76
Test name
Test status
Simulation time 1385081492 ps
CPU time 1.05 seconds
Started Apr 25 12:46:42 PM PDT 24
Finished Apr 25 12:46:45 PM PDT 24
Peak memory 183612 kb
Host smart-1acd64da-4716-4205-9cb9-d3d3b5e76161
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955943775 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_
timer_same_csr_outstanding.955943775
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.1888378297
Short name T363
Test name
Test status
Simulation time 305168764 ps
CPU time 1.76 seconds
Started Apr 25 12:46:45 PM PDT 24
Finished Apr 25 12:46:49 PM PDT 24
Peak memory 198424 kb
Host smart-8936e42a-0b43-4a94-ac36-48057d4303b3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888378297 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.1888378297
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.2553485498
Short name T373
Test name
Test status
Simulation time 8168846538 ps
CPU time 3.47 seconds
Started Apr 25 12:46:42 PM PDT 24
Finished Apr 25 12:46:47 PM PDT 24
Peak memory 197716 kb
Host smart-4c83f550-0edf-444f-8707-1ac5fb1d2697
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553485498 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl
_intg_err.2553485498
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.1905170888
Short name T31
Test name
Test status
Simulation time 335641473 ps
CPU time 0.89 seconds
Started Apr 25 12:46:45 PM PDT 24
Finished Apr 25 12:46:48 PM PDT 24
Peak memory 195332 kb
Host smart-248fd99b-36ce-4294-a30c-0a085ce566c4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905170888 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.1905170888
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.4141616915
Short name T364
Test name
Test status
Simulation time 342963869 ps
CPU time 0.75 seconds
Started Apr 25 12:46:50 PM PDT 24
Finished Apr 25 12:46:51 PM PDT 24
Peak memory 183536 kb
Host smart-4d449d57-6820-4004-8216-6a859581ab1b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141616915 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.4141616915
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.109736343
Short name T297
Test name
Test status
Simulation time 386089676 ps
CPU time 0.73 seconds
Started Apr 25 12:46:42 PM PDT 24
Finished Apr 25 12:46:45 PM PDT 24
Peak memory 183564 kb
Host smart-1850abfb-794f-4503-b699-fc93678afc93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109736343 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.109736343
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.557777690
Short name T380
Test name
Test status
Simulation time 1099087687 ps
CPU time 2.01 seconds
Started Apr 25 12:46:45 PM PDT 24
Finished Apr 25 12:46:49 PM PDT 24
Peak memory 183664 kb
Host smart-7cfce363-ed4a-414b-a5df-5b2f70f1c1bc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557777690 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_
timer_same_csr_outstanding.557777690
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.3000874101
Short name T388
Test name
Test status
Simulation time 574462607 ps
CPU time 2.02 seconds
Started Apr 25 12:46:42 PM PDT 24
Finished Apr 25 12:46:47 PM PDT 24
Peak memory 198488 kb
Host smart-2f1a1450-58a4-4734-a0e0-c7c0dfc9670a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000874101 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.3000874101
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.627033584
Short name T354
Test name
Test status
Simulation time 8005331842 ps
CPU time 12.11 seconds
Started Apr 25 12:46:50 PM PDT 24
Finished Apr 25 12:47:03 PM PDT 24
Peak memory 197944 kb
Host smart-17a5dba8-8fbd-4100-9e05-e78ba47b1684
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627033584 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_
intg_err.627033584
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.3868672360
Short name T359
Test name
Test status
Simulation time 419117626 ps
CPU time 0.95 seconds
Started Apr 25 12:46:43 PM PDT 24
Finished Apr 25 12:46:46 PM PDT 24
Peak memory 198056 kb
Host smart-df1513d2-63ef-4312-877e-6adb37b76b95
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868672360 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.3868672360
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.2387910273
Short name T327
Test name
Test status
Simulation time 501381793 ps
CPU time 1.52 seconds
Started Apr 25 12:46:46 PM PDT 24
Finished Apr 25 12:46:49 PM PDT 24
Peak memory 183948 kb
Host smart-bb75515c-f20c-422d-ab6d-b1f96dd96173
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387910273 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.2387910273
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.2707952932
Short name T339
Test name
Test status
Simulation time 533983241 ps
CPU time 0.69 seconds
Started Apr 25 12:46:46 PM PDT 24
Finished Apr 25 12:46:49 PM PDT 24
Peak memory 183476 kb
Host smart-2d250107-bedd-4aaf-96ee-5af86ff17d56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707952932 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.2707952932
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.2605681688
Short name T395
Test name
Test status
Simulation time 2159834160 ps
CPU time 0.99 seconds
Started Apr 25 12:46:46 PM PDT 24
Finished Apr 25 12:46:49 PM PDT 24
Peak memory 194716 kb
Host smart-59bc93e8-c27e-42e3-8e57-e5753b3e8194
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605681688 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon
_timer_same_csr_outstanding.2605681688
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.2960973988
Short name T321
Test name
Test status
Simulation time 416552358 ps
CPU time 1.81 seconds
Started Apr 25 12:46:45 PM PDT 24
Finished Apr 25 12:46:48 PM PDT 24
Peak memory 198344 kb
Host smart-90260e7c-17bd-41a1-9eea-30cd376fee45
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960973988 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.2960973988
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.1447523095
Short name T106
Test name
Test status
Simulation time 7923363614 ps
CPU time 6.39 seconds
Started Apr 25 12:46:46 PM PDT 24
Finished Apr 25 12:46:54 PM PDT 24
Peak memory 197876 kb
Host smart-12c93033-59ed-4426-bcb5-668cb29df534
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447523095 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl
_intg_err.1447523095
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.496620658
Short name T298
Test name
Test status
Simulation time 675636763 ps
CPU time 0.96 seconds
Started Apr 25 12:46:47 PM PDT 24
Finished Apr 25 12:46:50 PM PDT 24
Peak memory 197488 kb
Host smart-ad7ddc6d-b06b-4a53-b1bc-6ef85e1f9d0a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496620658 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.496620658
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.1816989053
Short name T307
Test name
Test status
Simulation time 386670083 ps
CPU time 1.08 seconds
Started Apr 25 12:46:43 PM PDT 24
Finished Apr 25 12:46:46 PM PDT 24
Peak memory 183548 kb
Host smart-388e7ce1-bf0a-4624-8f80-e6f313faea82
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816989053 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.1816989053
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.3460741563
Short name T325
Test name
Test status
Simulation time 368821344 ps
CPU time 0.8 seconds
Started Apr 25 12:46:44 PM PDT 24
Finished Apr 25 12:46:47 PM PDT 24
Peak memory 183560 kb
Host smart-715dd107-54dc-427f-84eb-8f72fb809979
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460741563 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.3460741563
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.1807165694
Short name T335
Test name
Test status
Simulation time 2237961405 ps
CPU time 3.75 seconds
Started Apr 25 12:46:46 PM PDT 24
Finished Apr 25 12:46:52 PM PDT 24
Peak memory 194572 kb
Host smart-53af7fa8-d4b3-4e8e-aa0e-85500c2e5737
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807165694 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon
_timer_same_csr_outstanding.1807165694
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.2467038142
Short name T283
Test name
Test status
Simulation time 497930105 ps
CPU time 2.82 seconds
Started Apr 25 12:46:44 PM PDT 24
Finished Apr 25 12:46:49 PM PDT 24
Peak memory 198448 kb
Host smart-1ab76539-f740-4b24-be78-e32d2c0cc90a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467038142 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.2467038142
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.4206924285
Short name T397
Test name
Test status
Simulation time 7938634450 ps
CPU time 12.04 seconds
Started Apr 25 12:46:49 PM PDT 24
Finished Apr 25 12:47:02 PM PDT 24
Peak memory 197876 kb
Host smart-91b09e5e-d51e-498c-a608-bfec2b84f730
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206924285 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl
_intg_err.4206924285
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_jump.103204754
Short name T62
Test name
Test status
Simulation time 391295934 ps
CPU time 0.89 seconds
Started Apr 25 12:45:58 PM PDT 24
Finished Apr 25 12:46:00 PM PDT 24
Peak memory 183472 kb
Host smart-a28897c2-c48f-46ce-a364-377bcfa1d2a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103204754 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.103204754
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.1552492593
Short name T237
Test name
Test status
Simulation time 40892426696 ps
CPU time 69.22 seconds
Started Apr 25 12:45:46 PM PDT 24
Finished Apr 25 12:46:56 PM PDT 24
Peak memory 191724 kb
Host smart-665c4260-f369-44ac-86d1-d825c58c00b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552492593 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.1552492593
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.3958392466
Short name T136
Test name
Test status
Simulation time 556428891 ps
CPU time 0.96 seconds
Started Apr 25 12:45:45 PM PDT 24
Finished Apr 25 12:45:46 PM PDT 24
Peak memory 183492 kb
Host smart-1563cc25-5ab6-4d35-89fe-42ec962259ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958392466 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.3958392466
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.744562412
Short name T221
Test name
Test status
Simulation time 23682351269 ps
CPU time 10.79 seconds
Started Apr 25 12:45:52 PM PDT 24
Finished Apr 25 12:46:03 PM PDT 24
Peak memory 193924 kb
Host smart-ef599397-e24a-4163-8409-61453c300dd1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744562412 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_al
l.744562412
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_jump.3912179090
Short name T140
Test name
Test status
Simulation time 424074748 ps
CPU time 1.18 seconds
Started Apr 25 12:45:56 PM PDT 24
Finished Apr 25 12:45:58 PM PDT 24
Peak memory 183492 kb
Host smart-891ebea0-7669-485b-91e7-82531ff945e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912179090 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.3912179090
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.1280689577
Short name T195
Test name
Test status
Simulation time 37590031317 ps
CPU time 15.22 seconds
Started Apr 25 12:45:52 PM PDT 24
Finished Apr 25 12:46:08 PM PDT 24
Peak memory 183616 kb
Host smart-14675331-09cb-46fd-b61b-3d70b97cbd27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280689577 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.1280689577
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.642757233
Short name T19
Test name
Test status
Simulation time 4370817677 ps
CPU time 1.61 seconds
Started Apr 25 12:45:53 PM PDT 24
Finished Apr 25 12:45:55 PM PDT 24
Peak memory 215088 kb
Host smart-c663db8f-dd4f-4dfd-b263-bfac1e6141af
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642757233 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.642757233
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.581699583
Short name T218
Test name
Test status
Simulation time 571264260 ps
CPU time 0.72 seconds
Started Apr 25 12:45:57 PM PDT 24
Finished Apr 25 12:45:59 PM PDT 24
Peak memory 183564 kb
Host smart-66bc5ffa-424f-4d94-8ac4-c6853b7bced6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581699583 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.581699583
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.681873656
Short name T244
Test name
Test status
Simulation time 60127083234 ps
CPU time 90.5 seconds
Started Apr 25 12:45:52 PM PDT 24
Finished Apr 25 12:47:23 PM PDT 24
Peak memory 183612 kb
Host smart-16af013b-c6db-4178-b19f-2b4011b78054
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681873656 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_al
l.681873656
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.4062192174
Short name T176
Test name
Test status
Simulation time 247043024906 ps
CPU time 676.07 seconds
Started Apr 25 12:45:52 PM PDT 24
Finished Apr 25 12:57:09 PM PDT 24
Peak memory 214328 kb
Host smart-6cab4752-964e-4ce1-9fc1-74a78c0806bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062192174 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.4062192174
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.aon_timer_jump.2309527765
Short name T254
Test name
Test status
Simulation time 526650831 ps
CPU time 0.78 seconds
Started Apr 25 12:45:58 PM PDT 24
Finished Apr 25 12:46:00 PM PDT 24
Peak memory 183460 kb
Host smart-053c5c94-90b3-471b-9635-06819085bbf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309527765 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.2309527765
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.3844141415
Short name T70
Test name
Test status
Simulation time 10553213163 ps
CPU time 18.91 seconds
Started Apr 25 12:46:12 PM PDT 24
Finished Apr 25 12:46:32 PM PDT 24
Peak memory 191828 kb
Host smart-62231096-ff92-4aad-acb0-66909c2bc839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844141415 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.3844141415
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.4006959310
Short name T4
Test name
Test status
Simulation time 457291439 ps
CPU time 1.15 seconds
Started Apr 25 12:46:00 PM PDT 24
Finished Apr 25 12:46:02 PM PDT 24
Peak memory 183412 kb
Host smart-0a13cfd4-1d85-4e6a-b69b-518c1373ea1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006959310 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.4006959310
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.182994884
Short name T184
Test name
Test status
Simulation time 17757748816 ps
CPU time 141.25 seconds
Started Apr 25 12:45:57 PM PDT 24
Finished Apr 25 12:48:20 PM PDT 24
Peak memory 198528 kb
Host smart-187b6645-5884-4cfd-a11f-db4b2697d4cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182994884 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.182994884
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.aon_timer_jump.912906401
Short name T231
Test name
Test status
Simulation time 421866076 ps
CPU time 0.64 seconds
Started Apr 25 12:46:05 PM PDT 24
Finished Apr 25 12:46:07 PM PDT 24
Peak memory 183564 kb
Host smart-b5c0cc2c-18ed-4c2a-a71e-506d01f44c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912906401 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.912906401
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.3004080078
Short name T264
Test name
Test status
Simulation time 15173988387 ps
CPU time 26.15 seconds
Started Apr 25 12:46:03 PM PDT 24
Finished Apr 25 12:46:31 PM PDT 24
Peak memory 183520 kb
Host smart-fcc03d3d-eb28-4752-a49d-bcbfce4e8558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004080078 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.3004080078
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.3273268777
Short name T132
Test name
Test status
Simulation time 442394926 ps
CPU time 0.72 seconds
Started Apr 25 12:46:00 PM PDT 24
Finished Apr 25 12:46:02 PM PDT 24
Peak memory 183560 kb
Host smart-2dbd7043-da17-47e0-abd6-941e82935bdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273268777 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.3273268777
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.3862229944
Short name T91
Test name
Test status
Simulation time 4262022463 ps
CPU time 7.92 seconds
Started Apr 25 12:46:09 PM PDT 24
Finished Apr 25 12:46:18 PM PDT 24
Peak memory 183524 kb
Host smart-d56d5897-3298-4776-b18a-6bbd6236aa39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862229944 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_
all.3862229944
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.3113878736
Short name T92
Test name
Test status
Simulation time 151921539626 ps
CPU time 396.49 seconds
Started Apr 25 12:46:06 PM PDT 24
Finished Apr 25 12:52:44 PM PDT 24
Peak memory 198480 kb
Host smart-af988e1d-66b5-455b-9545-a07e967d16e9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113878736 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand_reset.3113878736
Directory /workspace/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.aon_timer_jump.567387113
Short name T190
Test name
Test status
Simulation time 504907522 ps
CPU time 1.44 seconds
Started Apr 25 12:46:11 PM PDT 24
Finished Apr 25 12:46:13 PM PDT 24
Peak memory 183464 kb
Host smart-483a0309-6198-4f2f-acf2-e69c8fb58cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567387113 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.567387113
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.4032245189
Short name T124
Test name
Test status
Simulation time 31413498543 ps
CPU time 53.93 seconds
Started Apr 25 12:46:04 PM PDT 24
Finished Apr 25 12:46:59 PM PDT 24
Peak memory 191664 kb
Host smart-a1dcce66-ba7d-423e-8fee-46ddcda9d217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032245189 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.4032245189
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.984424851
Short name T258
Test name
Test status
Simulation time 429102837 ps
CPU time 0.68 seconds
Started Apr 25 12:46:06 PM PDT 24
Finished Apr 25 12:46:09 PM PDT 24
Peak memory 183552 kb
Host smart-9fee07bf-213f-40ea-baf6-6ae24d96c696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984424851 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.984424851
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.1213372535
Short name T166
Test name
Test status
Simulation time 183759595014 ps
CPU time 248.05 seconds
Started Apr 25 12:46:04 PM PDT 24
Finished Apr 25 12:50:13 PM PDT 24
Peak memory 191724 kb
Host smart-638ad985-1ac6-4fe4-bf44-db60601cb39b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213372535 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_
all.1213372535
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/13.aon_timer_jump.3752640541
Short name T241
Test name
Test status
Simulation time 345436613 ps
CPU time 1.12 seconds
Started Apr 25 12:46:05 PM PDT 24
Finished Apr 25 12:46:08 PM PDT 24
Peak memory 183548 kb
Host smart-e8ba9e62-c35b-44a9-a3d8-6bf5d205caa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752640541 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.3752640541
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.498703808
Short name T134
Test name
Test status
Simulation time 48585689743 ps
CPU time 18.87 seconds
Started Apr 25 12:46:08 PM PDT 24
Finished Apr 25 12:46:28 PM PDT 24
Peak memory 183560 kb
Host smart-4c0dd365-0338-4e5c-8f55-73d5bf27990b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498703808 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.498703808
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.1623288604
Short name T269
Test name
Test status
Simulation time 415917826 ps
CPU time 1.23 seconds
Started Apr 25 12:46:05 PM PDT 24
Finished Apr 25 12:46:08 PM PDT 24
Peak memory 183576 kb
Host smart-60f5a844-764e-4274-b077-3f2802eda592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623288604 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.1623288604
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.417862980
Short name T225
Test name
Test status
Simulation time 65851403743 ps
CPU time 29.78 seconds
Started Apr 25 12:46:08 PM PDT 24
Finished Apr 25 12:46:40 PM PDT 24
Peak memory 194376 kb
Host smart-1a191526-fcb2-417c-b64f-5e4fe009547a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417862980 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_a
ll.417862980
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.1909349964
Short name T97
Test name
Test status
Simulation time 36129722503 ps
CPU time 138.87 seconds
Started Apr 25 12:46:09 PM PDT 24
Finished Apr 25 12:48:30 PM PDT 24
Peak memory 198472 kb
Host smart-2e525523-6ce9-4fe9-941a-f97e45032828
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909349964 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.1909349964
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.aon_timer_jump.4012684554
Short name T191
Test name
Test status
Simulation time 590562759 ps
CPU time 1.07 seconds
Started Apr 25 12:46:04 PM PDT 24
Finished Apr 25 12:46:06 PM PDT 24
Peak memory 183568 kb
Host smart-04006742-c78f-4a8b-a574-f91639427959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012684554 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.4012684554
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.3629976639
Short name T259
Test name
Test status
Simulation time 15449151859 ps
CPU time 27.28 seconds
Started Apr 25 12:46:07 PM PDT 24
Finished Apr 25 12:46:36 PM PDT 24
Peak memory 183480 kb
Host smart-4fd28b25-64fb-48b1-8360-b6be8ebd0c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629976639 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.3629976639
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.1720106531
Short name T248
Test name
Test status
Simulation time 373489776 ps
CPU time 1.06 seconds
Started Apr 25 12:46:08 PM PDT 24
Finished Apr 25 12:46:11 PM PDT 24
Peak memory 183436 kb
Host smart-dce0a983-2d96-4fce-b488-7d0a486de558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720106531 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.1720106531
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.651955790
Short name T185
Test name
Test status
Simulation time 51682333187 ps
CPU time 10.98 seconds
Started Apr 25 12:46:11 PM PDT 24
Finished Apr 25 12:46:24 PM PDT 24
Peak memory 183560 kb
Host smart-9e32a11d-3b7b-4831-ae3d-ab3875c66251
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651955790 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_a
ll.651955790
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.467694010
Short name T183
Test name
Test status
Simulation time 33813810013 ps
CPU time 328.77 seconds
Started Apr 25 12:46:05 PM PDT 24
Finished Apr 25 12:51:35 PM PDT 24
Peak memory 198372 kb
Host smart-63664c31-a416-429e-a113-00ada06ad59b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467694010 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.467694010
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.aon_timer_jump.2024646086
Short name T119
Test name
Test status
Simulation time 454907130 ps
CPU time 0.71 seconds
Started Apr 25 12:46:04 PM PDT 24
Finished Apr 25 12:46:06 PM PDT 24
Peak memory 183456 kb
Host smart-193b935c-9669-488f-8e84-11d5dc810cd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024646086 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.2024646086
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.3062487229
Short name T155
Test name
Test status
Simulation time 5144800608 ps
CPU time 4.25 seconds
Started Apr 25 12:46:08 PM PDT 24
Finished Apr 25 12:46:14 PM PDT 24
Peak memory 191768 kb
Host smart-cc5aaedd-c6a1-449e-9c82-18cafae173ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062487229 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.3062487229
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.1881888845
Short name T252
Test name
Test status
Simulation time 420667087 ps
CPU time 1.15 seconds
Started Apr 25 12:46:08 PM PDT 24
Finished Apr 25 12:46:11 PM PDT 24
Peak memory 183516 kb
Host smart-68c46f55-0ebf-4548-b7bc-3fd48230c4a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881888845 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.1881888845
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.299411400
Short name T130
Test name
Test status
Simulation time 271497859834 ps
CPU time 448.23 seconds
Started Apr 25 12:46:08 PM PDT 24
Finished Apr 25 12:53:38 PM PDT 24
Peak memory 193108 kb
Host smart-f25c033a-c636-475a-a252-997492fd81f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299411400 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_a
ll.299411400
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.3273017123
Short name T39
Test name
Test status
Simulation time 21617794659 ps
CPU time 170.32 seconds
Started Apr 25 12:46:06 PM PDT 24
Finished Apr 25 12:48:58 PM PDT 24
Peak memory 198528 kb
Host smart-b17ebc25-4ebe-4ea8-ba31-4315f8e615b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273017123 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.3273017123
Directory /workspace/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.aon_timer_jump.3523704505
Short name T277
Test name
Test status
Simulation time 487825934 ps
CPU time 0.94 seconds
Started Apr 25 12:46:06 PM PDT 24
Finished Apr 25 12:46:09 PM PDT 24
Peak memory 183552 kb
Host smart-243acf94-f8f9-4f14-9fd9-c98e9817f779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523704505 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.3523704505
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.1743423791
Short name T243
Test name
Test status
Simulation time 14824212467 ps
CPU time 25.57 seconds
Started Apr 25 12:46:04 PM PDT 24
Finished Apr 25 12:46:31 PM PDT 24
Peak memory 191816 kb
Host smart-fd83b4bd-fa10-4a67-be1c-e206de290fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743423791 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.1743423791
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.1061917299
Short name T28
Test name
Test status
Simulation time 492783085 ps
CPU time 1.17 seconds
Started Apr 25 12:46:06 PM PDT 24
Finished Apr 25 12:46:09 PM PDT 24
Peak memory 183536 kb
Host smart-e8a35073-6d62-41b0-8b13-aac96a9429e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061917299 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.1061917299
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_jump.604933524
Short name T167
Test name
Test status
Simulation time 539646743 ps
CPU time 0.67 seconds
Started Apr 25 12:46:09 PM PDT 24
Finished Apr 25 12:46:12 PM PDT 24
Peak memory 183524 kb
Host smart-37bce6d1-0540-4690-80c1-81578cd6d95d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604933524 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.604933524
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.3676471426
Short name T265
Test name
Test status
Simulation time 4325333763 ps
CPU time 6.67 seconds
Started Apr 25 12:46:03 PM PDT 24
Finished Apr 25 12:46:11 PM PDT 24
Peak memory 183572 kb
Host smart-2e11c92e-9846-4c9f-8e08-33848f6c616b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676471426 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.3676471426
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.604815126
Short name T22
Test name
Test status
Simulation time 503359051 ps
CPU time 0.77 seconds
Started Apr 25 12:46:09 PM PDT 24
Finished Apr 25 12:46:12 PM PDT 24
Peak memory 183540 kb
Host smart-3c27879c-045f-4610-8d5b-11f07e1f8a9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604815126 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.604815126
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.2031802524
Short name T174
Test name
Test status
Simulation time 78222180413 ps
CPU time 26.99 seconds
Started Apr 25 12:46:09 PM PDT 24
Finished Apr 25 12:46:38 PM PDT 24
Peak memory 183560 kb
Host smart-96cd0106-7187-47e3-a283-062bb7890681
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031802524 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_
all.2031802524
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.4136456359
Short name T5
Test name
Test status
Simulation time 31864922454 ps
CPU time 261.96 seconds
Started Apr 25 12:46:07 PM PDT 24
Finished Apr 25 12:50:31 PM PDT 24
Peak memory 198300 kb
Host smart-93d0dde2-15ec-476b-adbb-359520abc70e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136456359 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.4136456359
Directory /workspace/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.aon_timer_jump.2917846075
Short name T135
Test name
Test status
Simulation time 579979018 ps
CPU time 1.03 seconds
Started Apr 25 12:46:07 PM PDT 24
Finished Apr 25 12:46:10 PM PDT 24
Peak memory 183564 kb
Host smart-2bb2203d-7e40-489b-9757-8ee2b9ff7835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917846075 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.2917846075
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.466185860
Short name T200
Test name
Test status
Simulation time 20373018959 ps
CPU time 15.77 seconds
Started Apr 25 12:46:09 PM PDT 24
Finished Apr 25 12:46:27 PM PDT 24
Peak memory 183520 kb
Host smart-e7d11114-c28e-4f05-a18d-599eccda4f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466185860 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.466185860
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.3986090496
Short name T88
Test name
Test status
Simulation time 452952350 ps
CPU time 0.68 seconds
Started Apr 25 12:46:07 PM PDT 24
Finished Apr 25 12:46:09 PM PDT 24
Peak memory 183436 kb
Host smart-44f9802d-8ea8-473a-a9f7-bd95d524e696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986090496 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.3986090496
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.2496145262
Short name T141
Test name
Test status
Simulation time 345329146796 ps
CPU time 337.53 seconds
Started Apr 25 12:46:01 PM PDT 24
Finished Apr 25 12:51:40 PM PDT 24
Peak memory 193908 kb
Host smart-3b886b55-8f89-4fb4-8ac0-24319bdb10ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496145262 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_
all.2496145262
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_jump.3545714703
Short name T123
Test name
Test status
Simulation time 453666855 ps
CPU time 1.27 seconds
Started Apr 25 12:46:07 PM PDT 24
Finished Apr 25 12:46:10 PM PDT 24
Peak memory 183456 kb
Host smart-6a0f6647-784e-4d8f-bcc9-f99ff5d9c12f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545714703 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.3545714703
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.1744264389
Short name T160
Test name
Test status
Simulation time 27826084233 ps
CPU time 45.26 seconds
Started Apr 25 12:46:07 PM PDT 24
Finished Apr 25 12:46:54 PM PDT 24
Peak memory 183532 kb
Host smart-9adedd47-71af-4e42-b145-55ff92a54c70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744264389 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.1744264389
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.3936070194
Short name T158
Test name
Test status
Simulation time 555508073 ps
CPU time 1.3 seconds
Started Apr 25 12:46:16 PM PDT 24
Finished Apr 25 12:46:18 PM PDT 24
Peak memory 183528 kb
Host smart-65931405-5a9b-4583-b47f-7ada11c0a444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936070194 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.3936070194
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.3206173698
Short name T261
Test name
Test status
Simulation time 482489826810 ps
CPU time 771.25 seconds
Started Apr 25 12:46:09 PM PDT 24
Finished Apr 25 12:59:02 PM PDT 24
Peak memory 193964 kb
Host smart-780d3df1-9225-40ce-8ab4-b587d71a4b4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206173698 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_
all.3206173698
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.1501382392
Short name T80
Test name
Test status
Simulation time 106171964765 ps
CPU time 232.05 seconds
Started Apr 25 12:46:07 PM PDT 24
Finished Apr 25 12:50:01 PM PDT 24
Peak memory 198448 kb
Host smart-f49bbc01-d9f9-4e55-854f-837ce4b66f85
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501382392 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.1501382392
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_jump.1351842734
Short name T133
Test name
Test status
Simulation time 444548409 ps
CPU time 0.74 seconds
Started Apr 25 12:45:52 PM PDT 24
Finished Apr 25 12:45:54 PM PDT 24
Peak memory 183508 kb
Host smart-79de384a-8c92-438f-b635-1e84b75b3d7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351842734 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.1351842734
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.726349333
Short name T114
Test name
Test status
Simulation time 2915498360 ps
CPU time 2.8 seconds
Started Apr 25 12:45:52 PM PDT 24
Finished Apr 25 12:45:56 PM PDT 24
Peak memory 183612 kb
Host smart-03689f5b-4eaf-4ccc-8c8c-470343761b70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726349333 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.726349333
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.3710387508
Short name T20
Test name
Test status
Simulation time 4361804481 ps
CPU time 2.36 seconds
Started Apr 25 12:45:52 PM PDT 24
Finished Apr 25 12:45:55 PM PDT 24
Peak memory 215128 kb
Host smart-5d6cac92-d193-4577-b8f5-505bf764ec17
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710387508 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.3710387508
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.583207694
Short name T112
Test name
Test status
Simulation time 577654768 ps
CPU time 0.63 seconds
Started Apr 25 12:45:53 PM PDT 24
Finished Apr 25 12:45:55 PM PDT 24
Peak memory 183500 kb
Host smart-8eff89b9-234f-497f-9f78-1dba32c55103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583207694 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.583207694
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.2164477127
Short name T177
Test name
Test status
Simulation time 71161324769 ps
CPU time 26.74 seconds
Started Apr 25 12:45:51 PM PDT 24
Finished Apr 25 12:46:18 PM PDT 24
Peak memory 193788 kb
Host smart-f5c125b2-3deb-40c0-9055-355bb1907383
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164477127 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_a
ll.2164477127
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.2035336375
Short name T48
Test name
Test status
Simulation time 126425731136 ps
CPU time 504.75 seconds
Started Apr 25 12:45:54 PM PDT 24
Finished Apr 25 12:54:20 PM PDT 24
Peak memory 198664 kb
Host smart-9c41c6eb-0477-447d-b308-310362a10ef6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035336375 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.2035336375
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.aon_timer_jump.1611059698
Short name T115
Test name
Test status
Simulation time 479722373 ps
CPU time 0.8 seconds
Started Apr 25 12:46:09 PM PDT 24
Finished Apr 25 12:46:11 PM PDT 24
Peak memory 183388 kb
Host smart-f579fe8d-e304-41d3-b3e2-91941d5fa390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611059698 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.1611059698
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.4183647243
Short name T206
Test name
Test status
Simulation time 8127650918 ps
CPU time 3.65 seconds
Started Apr 25 12:46:18 PM PDT 24
Finished Apr 25 12:46:24 PM PDT 24
Peak memory 183596 kb
Host smart-94313ed3-5a0a-48bf-b54d-a2e3d95cb207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183647243 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.4183647243
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.4129814180
Short name T255
Test name
Test status
Simulation time 489165973 ps
CPU time 0.91 seconds
Started Apr 25 12:46:10 PM PDT 24
Finished Apr 25 12:46:12 PM PDT 24
Peak memory 183468 kb
Host smart-5a07558d-5e7b-4b03-8442-93dea72434cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129814180 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.4129814180
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.183457060
Short name T188
Test name
Test status
Simulation time 128913211433 ps
CPU time 198.77 seconds
Started Apr 25 12:46:18 PM PDT 24
Finished Apr 25 12:49:39 PM PDT 24
Peak memory 183388 kb
Host smart-00d9bd10-da01-4f52-a5af-06b6b76cf7a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183457060 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_a
ll.183457060
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.2055813713
Short name T42
Test name
Test status
Simulation time 377806489428 ps
CPU time 190.34 seconds
Started Apr 25 12:46:09 PM PDT 24
Finished Apr 25 12:49:21 PM PDT 24
Peak memory 198480 kb
Host smart-d38e5aad-579e-462a-94a6-2e68d7ff015e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055813713 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.2055813713
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_jump.2235081726
Short name T95
Test name
Test status
Simulation time 348703556 ps
CPU time 1.09 seconds
Started Apr 25 12:46:10 PM PDT 24
Finished Apr 25 12:46:13 PM PDT 24
Peak memory 183552 kb
Host smart-f21f4183-2780-4214-8b65-03e435ccd592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235081726 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.2235081726
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.455992420
Short name T14
Test name
Test status
Simulation time 36675679365 ps
CPU time 12.72 seconds
Started Apr 25 12:46:09 PM PDT 24
Finished Apr 25 12:46:23 PM PDT 24
Peak memory 183504 kb
Host smart-f9a0739f-1744-4064-994f-e5fb9a77aee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455992420 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.455992420
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.2822200891
Short name T137
Test name
Test status
Simulation time 490767580 ps
CPU time 0.88 seconds
Started Apr 25 12:46:19 PM PDT 24
Finished Apr 25 12:46:22 PM PDT 24
Peak memory 183548 kb
Host smart-28bf1f1b-8708-4f3f-8bca-30a29aacbaef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822200891 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.2822200891
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.3928809000
Short name T223
Test name
Test status
Simulation time 215984348083 ps
CPU time 365.65 seconds
Started Apr 25 12:46:12 PM PDT 24
Finished Apr 25 12:52:19 PM PDT 24
Peak memory 183584 kb
Host smart-a34b4f77-73f1-4d6b-ad1d-0f27ff938d81
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928809000 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_
all.3928809000
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_jump.4001814539
Short name T181
Test name
Test status
Simulation time 395197372 ps
CPU time 0.9 seconds
Started Apr 25 12:46:18 PM PDT 24
Finished Apr 25 12:46:21 PM PDT 24
Peak memory 183348 kb
Host smart-2bc3d071-ed67-4e71-ba61-99bb8dfe935c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001814539 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.4001814539
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.943021720
Short name T171
Test name
Test status
Simulation time 35739809973 ps
CPU time 7.46 seconds
Started Apr 25 12:46:19 PM PDT 24
Finished Apr 25 12:46:29 PM PDT 24
Peak memory 183600 kb
Host smart-d459abf7-26f2-487a-bf1b-3aedd5d2df3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943021720 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.943021720
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.3053085290
Short name T224
Test name
Test status
Simulation time 537640701 ps
CPU time 0.7 seconds
Started Apr 25 12:46:09 PM PDT 24
Finished Apr 25 12:46:11 PM PDT 24
Peak memory 183504 kb
Host smart-1737ad7b-e130-4231-b42d-c099dd581329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053085290 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.3053085290
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.2212820558
Short name T246
Test name
Test status
Simulation time 129193313285 ps
CPU time 12.02 seconds
Started Apr 25 12:46:08 PM PDT 24
Finished Apr 25 12:46:22 PM PDT 24
Peak memory 183764 kb
Host smart-d2dc8d3a-0304-4905-aadf-72391e4e2506
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212820558 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_
all.2212820558
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.779212743
Short name T32
Test name
Test status
Simulation time 25111357375 ps
CPU time 196.44 seconds
Started Apr 25 12:46:18 PM PDT 24
Finished Apr 25 12:49:37 PM PDT 24
Peak memory 198476 kb
Host smart-39fcc6a8-2768-46db-a8c1-fe3de4c6bc65
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779212743 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.779212743
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.aon_timer_jump.982728271
Short name T227
Test name
Test status
Simulation time 619662853 ps
CPU time 0.77 seconds
Started Apr 25 12:46:21 PM PDT 24
Finished Apr 25 12:46:23 PM PDT 24
Peak memory 183464 kb
Host smart-6597d883-f4a9-4ab1-a61b-4e6f458d3c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982728271 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.982728271
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.1891901570
Short name T109
Test name
Test status
Simulation time 45751861045 ps
CPU time 17.92 seconds
Started Apr 25 12:46:21 PM PDT 24
Finished Apr 25 12:46:41 PM PDT 24
Peak memory 191728 kb
Host smart-c53e75da-a5f4-42a8-a83d-d760348d1c04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891901570 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.1891901570
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.544309974
Short name T229
Test name
Test status
Simulation time 574002543 ps
CPU time 0.89 seconds
Started Apr 25 12:46:17 PM PDT 24
Finished Apr 25 12:46:20 PM PDT 24
Peak memory 183564 kb
Host smart-75041f60-7638-4b67-880d-0355b59c5f21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544309974 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.544309974
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.2728095834
Short name T199
Test name
Test status
Simulation time 107011898641 ps
CPU time 46.81 seconds
Started Apr 25 12:46:19 PM PDT 24
Finished Apr 25 12:47:07 PM PDT 24
Peak memory 183572 kb
Host smart-308b2376-27ee-4372-af81-c8fdd2a9a89b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728095834 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_
all.2728095834
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.1342196941
Short name T86
Test name
Test status
Simulation time 44927189681 ps
CPU time 276.53 seconds
Started Apr 25 12:46:19 PM PDT 24
Finished Apr 25 12:50:58 PM PDT 24
Peak memory 198444 kb
Host smart-5d3025bc-d4ea-401d-a9f6-8c3e75886b30
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342196941 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.1342196941
Directory /workspace/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.aon_timer_jump.2195260962
Short name T211
Test name
Test status
Simulation time 394349498 ps
CPU time 1.07 seconds
Started Apr 25 12:46:25 PM PDT 24
Finished Apr 25 12:46:28 PM PDT 24
Peak memory 183436 kb
Host smart-ee7aa3bc-96df-4a67-84ff-2c725088da9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195260962 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.2195260962
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.3836161390
Short name T127
Test name
Test status
Simulation time 51030198649 ps
CPU time 84.07 seconds
Started Apr 25 12:46:19 PM PDT 24
Finished Apr 25 12:47:45 PM PDT 24
Peak memory 183492 kb
Host smart-8529bf64-b787-41df-b639-9e63701bf31a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836161390 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.3836161390
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.800149207
Short name T13
Test name
Test status
Simulation time 543390391 ps
CPU time 0.81 seconds
Started Apr 25 12:46:17 PM PDT 24
Finished Apr 25 12:46:19 PM PDT 24
Peak memory 183576 kb
Host smart-83514571-2cd5-463e-8971-9a0167de5f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800149207 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.800149207
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.3329279653
Short name T213
Test name
Test status
Simulation time 111950324320 ps
CPU time 114.1 seconds
Started Apr 25 12:46:16 PM PDT 24
Finished Apr 25 12:48:11 PM PDT 24
Peak memory 193964 kb
Host smart-6b8fe75e-0bc7-4379-a271-1e21c3be0445
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329279653 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_
all.3329279653
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.2829248775
Short name T268
Test name
Test status
Simulation time 80557053693 ps
CPU time 224.06 seconds
Started Apr 25 12:46:19 PM PDT 24
Finished Apr 25 12:50:05 PM PDT 24
Peak memory 198396 kb
Host smart-c71da0cf-0dea-414f-bfea-84dc8eca2f0b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829248775 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand_reset.2829248775
Directory /workspace/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.aon_timer_jump.3240917622
Short name T126
Test name
Test status
Simulation time 485935152 ps
CPU time 1.31 seconds
Started Apr 25 12:46:17 PM PDT 24
Finished Apr 25 12:46:21 PM PDT 24
Peak memory 183452 kb
Host smart-c615efca-32a0-4eb9-b382-958df22f911e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240917622 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.3240917622
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.1004985755
Short name T122
Test name
Test status
Simulation time 5585825292 ps
CPU time 2.81 seconds
Started Apr 25 12:46:18 PM PDT 24
Finished Apr 25 12:46:23 PM PDT 24
Peak memory 183588 kb
Host smart-0e436089-d258-47ed-b1a8-d09871bbf5e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004985755 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.1004985755
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.825383067
Short name T139
Test name
Test status
Simulation time 459768107 ps
CPU time 1.2 seconds
Started Apr 25 12:46:16 PM PDT 24
Finished Apr 25 12:46:19 PM PDT 24
Peak memory 183428 kb
Host smart-958db79f-4de5-4995-942c-ddbd48d7b945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825383067 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.825383067
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.1127718518
Short name T85
Test name
Test status
Simulation time 39822678595 ps
CPU time 145.68 seconds
Started Apr 25 12:46:17 PM PDT 24
Finished Apr 25 12:48:44 PM PDT 24
Peak memory 198560 kb
Host smart-f506d19a-dc02-45a3-bac9-95aea05327be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127718518 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.1127718518
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.aon_timer_jump.4071556828
Short name T187
Test name
Test status
Simulation time 515102679 ps
CPU time 0.99 seconds
Started Apr 25 12:46:18 PM PDT 24
Finished Apr 25 12:46:21 PM PDT 24
Peak memory 183568 kb
Host smart-3458ed41-d5af-41e2-a57f-fc2a20e5cac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071556828 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.4071556828
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.984571991
Short name T154
Test name
Test status
Simulation time 53253108302 ps
CPU time 21.44 seconds
Started Apr 25 12:46:17 PM PDT 24
Finished Apr 25 12:46:40 PM PDT 24
Peak memory 183612 kb
Host smart-e2da145b-6219-4992-94dd-fd184e9bb8c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984571991 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.984571991
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.3945677500
Short name T196
Test name
Test status
Simulation time 363267530 ps
CPU time 0.83 seconds
Started Apr 25 12:46:19 PM PDT 24
Finished Apr 25 12:46:22 PM PDT 24
Peak memory 183416 kb
Host smart-64be5526-45da-4968-a52f-e39068ce935d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945677500 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.3945677500
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.179166146
Short name T173
Test name
Test status
Simulation time 173084235602 ps
CPU time 67.52 seconds
Started Apr 25 12:46:17 PM PDT 24
Finished Apr 25 12:47:26 PM PDT 24
Peak memory 183492 kb
Host smart-a48ac68e-9c0b-4689-85da-1192c38c436c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179166146 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_a
ll.179166146
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.1491282260
Short name T81
Test name
Test status
Simulation time 59563927474 ps
CPU time 573.98 seconds
Started Apr 25 12:46:18 PM PDT 24
Finished Apr 25 12:55:54 PM PDT 24
Peak memory 198448 kb
Host smart-a97317a1-6962-4633-bf94-c1bf0df66bee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491282260 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.1491282260
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_jump.3238976845
Short name T23
Test name
Test status
Simulation time 483682498 ps
CPU time 1.31 seconds
Started Apr 25 12:46:15 PM PDT 24
Finished Apr 25 12:46:17 PM PDT 24
Peak memory 183552 kb
Host smart-367d5440-82a4-4155-8fa1-50285cdb5ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238976845 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.3238976845
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.3310761218
Short name T147
Test name
Test status
Simulation time 35446924153 ps
CPU time 59.64 seconds
Started Apr 25 12:46:15 PM PDT 24
Finished Apr 25 12:47:15 PM PDT 24
Peak memory 191672 kb
Host smart-d07ef801-8fda-4047-8ba2-f6b0224412bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310761218 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.3310761218
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.666264633
Short name T129
Test name
Test status
Simulation time 468477955 ps
CPU time 0.94 seconds
Started Apr 25 12:46:16 PM PDT 24
Finished Apr 25 12:46:18 PM PDT 24
Peak memory 183572 kb
Host smart-ba5685e9-a3c2-4bae-96c3-7264c23ae1f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666264633 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.666264633
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.2337987857
Short name T146
Test name
Test status
Simulation time 315665279769 ps
CPU time 130.99 seconds
Started Apr 25 12:46:26 PM PDT 24
Finished Apr 25 12:48:40 PM PDT 24
Peak memory 183612 kb
Host smart-c644fcf4-98dd-4b29-b21f-8da8947f9f8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337987857 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_
all.2337987857
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.2243760936
Short name T238
Test name
Test status
Simulation time 16579756792 ps
CPU time 172.5 seconds
Started Apr 25 12:46:23 PM PDT 24
Finished Apr 25 12:49:18 PM PDT 24
Peak memory 198472 kb
Host smart-236bbeb7-a607-4957-889b-d003a67d18f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243760936 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.2243760936
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_jump.2334070967
Short name T148
Test name
Test status
Simulation time 637478045 ps
CPU time 0.8 seconds
Started Apr 25 12:46:28 PM PDT 24
Finished Apr 25 12:46:31 PM PDT 24
Peak memory 183408 kb
Host smart-e32960fb-8af3-44d6-9b13-1e99ef8d843d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334070967 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.2334070967
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.1120478135
Short name T43
Test name
Test status
Simulation time 24627456016 ps
CPU time 19.29 seconds
Started Apr 25 12:46:28 PM PDT 24
Finished Apr 25 12:46:49 PM PDT 24
Peak memory 183600 kb
Host smart-fa8f7720-8591-4cb3-b3d0-9d2165dc1230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120478135 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.1120478135
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.3489211737
Short name T242
Test name
Test status
Simulation time 435236722 ps
CPU time 1.14 seconds
Started Apr 25 12:46:24 PM PDT 24
Finished Apr 25 12:46:27 PM PDT 24
Peak memory 183496 kb
Host smart-a6b4dc6f-f782-4549-bd4c-376ae24819b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489211737 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.3489211737
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.1051588945
Short name T64
Test name
Test status
Simulation time 88334673694 ps
CPU time 148.33 seconds
Started Apr 25 12:46:26 PM PDT 24
Finished Apr 25 12:48:57 PM PDT 24
Peak memory 195084 kb
Host smart-07099ace-1ada-40af-b622-56d7f0087cc8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051588945 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_
all.1051588945
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.2525960545
Short name T161
Test name
Test status
Simulation time 37465219798 ps
CPU time 415.29 seconds
Started Apr 25 12:46:25 PM PDT 24
Finished Apr 25 12:53:23 PM PDT 24
Peak memory 198504 kb
Host smart-6ab59db2-a8f8-4229-9ec9-209c50aa4e83
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525960545 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.2525960545
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.aon_timer_jump.811382563
Short name T96
Test name
Test status
Simulation time 579807776 ps
CPU time 1.56 seconds
Started Apr 25 12:46:24 PM PDT 24
Finished Apr 25 12:46:28 PM PDT 24
Peak memory 183456 kb
Host smart-d537f56b-d1ff-4014-9963-83988b9a1982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811382563 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.811382563
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.1921673776
Short name T235
Test name
Test status
Simulation time 40732308217 ps
CPU time 15.35 seconds
Started Apr 25 12:46:28 PM PDT 24
Finished Apr 25 12:46:45 PM PDT 24
Peak memory 183560 kb
Host smart-def804f7-2425-4971-aa54-6f76d7fc6873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921673776 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.1921673776
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.2503899002
Short name T116
Test name
Test status
Simulation time 452368517 ps
CPU time 0.72 seconds
Started Apr 25 12:46:22 PM PDT 24
Finished Apr 25 12:46:24 PM PDT 24
Peak memory 183428 kb
Host smart-c6ef4439-cabd-4e8d-b1b2-2dba0f6fffcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503899002 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.2503899002
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.2173495789
Short name T194
Test name
Test status
Simulation time 162551073889 ps
CPU time 264.8 seconds
Started Apr 25 12:46:25 PM PDT 24
Finished Apr 25 12:50:52 PM PDT 24
Peak memory 183640 kb
Host smart-1f25814c-3a53-41e5-842b-d0b8c6f83ae8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173495789 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_
all.2173495789
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_jump.1184784653
Short name T153
Test name
Test status
Simulation time 435172367 ps
CPU time 0.7 seconds
Started Apr 25 12:45:54 PM PDT 24
Finished Apr 25 12:45:55 PM PDT 24
Peak memory 183524 kb
Host smart-507fc1b0-2f3e-49da-898b-99b35d5cbfd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184784653 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.1184784653
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.1854705856
Short name T198
Test name
Test status
Simulation time 6018032728 ps
CPU time 2.82 seconds
Started Apr 25 12:45:53 PM PDT 24
Finished Apr 25 12:45:57 PM PDT 24
Peak memory 183564 kb
Host smart-af809e4e-1e32-4227-be73-5fd62676a879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854705856 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.1854705856
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.3805452824
Short name T15
Test name
Test status
Simulation time 4315410610 ps
CPU time 3.63 seconds
Started Apr 25 12:45:52 PM PDT 24
Finished Apr 25 12:45:56 PM PDT 24
Peak memory 215124 kb
Host smart-34e2e889-20f7-43cb-8988-273e787cac4f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805452824 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.3805452824
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.2811481156
Short name T11
Test name
Test status
Simulation time 557943662 ps
CPU time 0.79 seconds
Started Apr 25 12:45:54 PM PDT 24
Finished Apr 25 12:45:56 PM PDT 24
Peak memory 183476 kb
Host smart-f69524a2-0ee3-418a-a596-e7b385a574dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811481156 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.2811481156
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.2428050715
Short name T175
Test name
Test status
Simulation time 225298012737 ps
CPU time 95.81 seconds
Started Apr 25 12:45:52 PM PDT 24
Finished Apr 25 12:47:29 PM PDT 24
Peak memory 193320 kb
Host smart-e3912e02-0280-40d7-be9a-44b39d860fc5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428050715 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_a
ll.2428050715
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.1065185778
Short name T1
Test name
Test status
Simulation time 77619205246 ps
CPU time 411.82 seconds
Started Apr 25 12:45:50 PM PDT 24
Finished Apr 25 12:52:42 PM PDT 24
Peak memory 198552 kb
Host smart-e964676f-637a-4d43-acac-ead7388d446a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065185778 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.1065185778
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_jump.2943755203
Short name T94
Test name
Test status
Simulation time 372189707 ps
CPU time 0.68 seconds
Started Apr 25 12:46:28 PM PDT 24
Finished Apr 25 12:46:30 PM PDT 24
Peak memory 183568 kb
Host smart-58b3eace-8848-451a-8f8c-512680583afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943755203 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.2943755203
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.859269486
Short name T128
Test name
Test status
Simulation time 32734644014 ps
CPU time 53.22 seconds
Started Apr 25 12:46:28 PM PDT 24
Finished Apr 25 12:47:23 PM PDT 24
Peak memory 191816 kb
Host smart-26a8613b-b325-4fe5-8b9f-5b164eb84683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859269486 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.859269486
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.1388502193
Short name T270
Test name
Test status
Simulation time 441201488 ps
CPU time 0.75 seconds
Started Apr 25 12:46:25 PM PDT 24
Finished Apr 25 12:46:28 PM PDT 24
Peak memory 183484 kb
Host smart-2a114420-dfb1-4ddd-a16b-5df06b90378e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388502193 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.1388502193
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.1091647040
Short name T27
Test name
Test status
Simulation time 327710581138 ps
CPU time 503.55 seconds
Started Apr 25 12:46:26 PM PDT 24
Finished Apr 25 12:54:52 PM PDT 24
Peak memory 195168 kb
Host smart-3f2361bc-cf2b-4772-b9c8-b9d0eb1bd8d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091647040 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_
all.1091647040
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.2736548711
Short name T40
Test name
Test status
Simulation time 12628049440 ps
CPU time 142.02 seconds
Started Apr 25 12:46:25 PM PDT 24
Finished Apr 25 12:48:49 PM PDT 24
Peak memory 198420 kb
Host smart-8245d3f8-f9ad-4ee0-9945-fd96d8375df4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736548711 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.2736548711
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.aon_timer_jump.481096407
Short name T118
Test name
Test status
Simulation time 416179679 ps
CPU time 0.68 seconds
Started Apr 25 12:46:32 PM PDT 24
Finished Apr 25 12:46:34 PM PDT 24
Peak memory 183496 kb
Host smart-9bf94817-df8b-4e64-99fa-16661de25e8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481096407 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.481096407
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.1078198101
Short name T240
Test name
Test status
Simulation time 42211284075 ps
CPU time 25.06 seconds
Started Apr 25 12:46:21 PM PDT 24
Finished Apr 25 12:46:48 PM PDT 24
Peak memory 183604 kb
Host smart-500e18a7-313b-4dfe-9340-931cc92c4ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078198101 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.1078198101
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.2850510119
Short name T178
Test name
Test status
Simulation time 582013044 ps
CPU time 1.07 seconds
Started Apr 25 12:46:30 PM PDT 24
Finished Apr 25 12:46:33 PM PDT 24
Peak memory 183508 kb
Host smart-5acd8ef9-014f-4249-989a-c155ce01578a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850510119 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.2850510119
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.3174972050
Short name T145
Test name
Test status
Simulation time 69585158555 ps
CPU time 100.6 seconds
Started Apr 25 12:46:24 PM PDT 24
Finished Apr 25 12:48:07 PM PDT 24
Peak memory 194924 kb
Host smart-a643a032-4889-4faa-a9a1-5e05db458e72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174972050 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_
all.3174972050
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.109006058
Short name T249
Test name
Test status
Simulation time 135458137033 ps
CPU time 364.72 seconds
Started Apr 25 12:46:22 PM PDT 24
Finished Apr 25 12:52:29 PM PDT 24
Peak memory 198420 kb
Host smart-9cf4bcd4-af7e-45a7-a8a1-6beb3754f7d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109006058 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.109006058
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.aon_timer_jump.651535090
Short name T131
Test name
Test status
Simulation time 586473066 ps
CPU time 1.34 seconds
Started Apr 25 12:46:22 PM PDT 24
Finished Apr 25 12:46:25 PM PDT 24
Peak memory 183552 kb
Host smart-3c84af84-5691-49c6-9c4b-b4e16db9622a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651535090 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.651535090
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.3062459711
Short name T66
Test name
Test status
Simulation time 22135657125 ps
CPU time 30.65 seconds
Started Apr 25 12:46:21 PM PDT 24
Finished Apr 25 12:46:54 PM PDT 24
Peak memory 183576 kb
Host smart-a460828d-dbbb-4c7e-98c6-5b5a11bb2ce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062459711 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.3062459711
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.4070484790
Short name T117
Test name
Test status
Simulation time 469786515 ps
CPU time 1.44 seconds
Started Apr 25 12:46:22 PM PDT 24
Finished Apr 25 12:46:25 PM PDT 24
Peak memory 183524 kb
Host smart-8643c106-2809-4386-8661-3ea072238389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070484790 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.4070484790
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.78009263
Short name T207
Test name
Test status
Simulation time 126991128695 ps
CPU time 86.51 seconds
Started Apr 25 12:46:24 PM PDT 24
Finished Apr 25 12:47:52 PM PDT 24
Peak memory 183524 kb
Host smart-a0c6d779-45c5-4e3b-bc41-0a7cf07144b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78009263 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_al
l.78009263
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_jump.3097993413
Short name T152
Test name
Test status
Simulation time 600993610 ps
CPU time 0.8 seconds
Started Apr 25 12:46:25 PM PDT 24
Finished Apr 25 12:46:28 PM PDT 24
Peak memory 183412 kb
Host smart-1b1badeb-059b-459f-b66a-67d803b1a34a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097993413 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.3097993413
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.1713279966
Short name T280
Test name
Test status
Simulation time 17765592649 ps
CPU time 8.1 seconds
Started Apr 25 12:46:23 PM PDT 24
Finished Apr 25 12:46:33 PM PDT 24
Peak memory 183592 kb
Host smart-a1661eff-061b-4f50-8d69-491021f5f2d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713279966 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.1713279966
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.1113298390
Short name T262
Test name
Test status
Simulation time 358616945 ps
CPU time 0.68 seconds
Started Apr 25 12:46:21 PM PDT 24
Finished Apr 25 12:46:24 PM PDT 24
Peak memory 183496 kb
Host smart-ca6e0aa4-2d1a-4c4e-a5d1-68b23fcd167e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113298390 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.1113298390
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.1568158981
Short name T21
Test name
Test status
Simulation time 45132434819 ps
CPU time 19.64 seconds
Started Apr 25 12:46:26 PM PDT 24
Finished Apr 25 12:46:48 PM PDT 24
Peak memory 183632 kb
Host smart-11e47132-fe1b-47d4-ba5f-b511602ec296
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568158981 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_
all.1568158981
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.2322750017
Short name T157
Test name
Test status
Simulation time 81678081077 ps
CPU time 158.62 seconds
Started Apr 25 12:46:24 PM PDT 24
Finished Apr 25 12:49:05 PM PDT 24
Peak memory 198396 kb
Host smart-b7094952-0544-4588-95af-4f5d9c33421e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322750017 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.2322750017
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.aon_timer_jump.3987538963
Short name T250
Test name
Test status
Simulation time 443675193 ps
CPU time 1.36 seconds
Started Apr 25 12:46:22 PM PDT 24
Finished Apr 25 12:46:25 PM PDT 24
Peak memory 183440 kb
Host smart-a5275e14-bbb5-466a-bf7e-5e2f4ef986c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987538963 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.3987538963
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.3426637834
Short name T212
Test name
Test status
Simulation time 23085051728 ps
CPU time 19.7 seconds
Started Apr 25 12:46:24 PM PDT 24
Finished Apr 25 12:46:46 PM PDT 24
Peak memory 183580 kb
Host smart-c0460386-13e3-4a6d-af5e-d009b01b6878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426637834 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.3426637834
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.1459689620
Short name T239
Test name
Test status
Simulation time 401759584 ps
CPU time 1.14 seconds
Started Apr 25 12:46:25 PM PDT 24
Finished Apr 25 12:46:28 PM PDT 24
Peak memory 183576 kb
Host smart-c9f27bf7-25fc-494f-812a-106881dcf9d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459689620 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.1459689620
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.879401846
Short name T103
Test name
Test status
Simulation time 175863162305 ps
CPU time 63.63 seconds
Started Apr 25 12:46:26 PM PDT 24
Finished Apr 25 12:47:32 PM PDT 24
Peak memory 195216 kb
Host smart-9d6e0990-127b-4c84-8680-0fa8fbf60a1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879401846 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_a
ll.879401846
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.1418556018
Short name T46
Test name
Test status
Simulation time 371697460440 ps
CPU time 479.79 seconds
Started Apr 25 12:46:24 PM PDT 24
Finished Apr 25 12:54:26 PM PDT 24
Peak memory 214188 kb
Host smart-3cc85747-36c3-4388-9fba-c7d3cc318aca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418556018 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.1418556018
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.aon_timer_jump.2510723377
Short name T220
Test name
Test status
Simulation time 493780932 ps
CPU time 0.75 seconds
Started Apr 25 12:46:26 PM PDT 24
Finished Apr 25 12:46:29 PM PDT 24
Peak memory 183532 kb
Host smart-7faae401-e0c5-4635-aaa8-503e49d034f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510723377 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.2510723377
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.1075394677
Short name T10
Test name
Test status
Simulation time 21213432105 ps
CPU time 6.8 seconds
Started Apr 25 12:46:25 PM PDT 24
Finished Apr 25 12:46:34 PM PDT 24
Peak memory 183456 kb
Host smart-ee90e5e6-1dba-4891-af99-8c871c71d683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075394677 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.1075394677
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.2913711637
Short name T111
Test name
Test status
Simulation time 378996470 ps
CPU time 0.64 seconds
Started Apr 25 12:46:28 PM PDT 24
Finished Apr 25 12:46:30 PM PDT 24
Peak memory 183476 kb
Host smart-e5dcd067-3d3b-42da-aace-9f8e7bd8a99d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913711637 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.2913711637
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.2691382112
Short name T274
Test name
Test status
Simulation time 61629039229 ps
CPU time 18.24 seconds
Started Apr 25 12:46:25 PM PDT 24
Finished Apr 25 12:46:46 PM PDT 24
Peak memory 194124 kb
Host smart-0d90a741-2f82-42d1-b905-11966f8a9445
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691382112 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_
all.2691382112
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.3238107077
Short name T47
Test name
Test status
Simulation time 56919744716 ps
CPU time 242.54 seconds
Started Apr 25 12:46:26 PM PDT 24
Finished Apr 25 12:50:31 PM PDT 24
Peak memory 198444 kb
Host smart-ab9908dc-8b8a-4283-afc5-b52e793244cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238107077 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.3238107077
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.aon_timer_jump.1215413014
Short name T110
Test name
Test status
Simulation time 640388170 ps
CPU time 0.81 seconds
Started Apr 25 12:46:24 PM PDT 24
Finished Apr 25 12:46:27 PM PDT 24
Peak memory 183524 kb
Host smart-e9874896-92e9-422e-8d8d-156977384944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215413014 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.1215413014
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.1322690327
Short name T201
Test name
Test status
Simulation time 1295690962 ps
CPU time 2.5 seconds
Started Apr 25 12:46:25 PM PDT 24
Finished Apr 25 12:46:30 PM PDT 24
Peak memory 183524 kb
Host smart-6259646d-6c79-4d10-8776-00b1c6cdf77d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322690327 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.1322690327
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.83998843
Short name T90
Test name
Test status
Simulation time 507903791 ps
CPU time 0.67 seconds
Started Apr 25 12:46:24 PM PDT 24
Finished Apr 25 12:46:27 PM PDT 24
Peak memory 183456 kb
Host smart-4a9278d4-c2a9-4247-931b-8f8e31210ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83998843 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.83998843
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.1052813877
Short name T209
Test name
Test status
Simulation time 86352907989 ps
CPU time 18.12 seconds
Started Apr 25 12:46:28 PM PDT 24
Finished Apr 25 12:46:48 PM PDT 24
Peak memory 183632 kb
Host smart-14294356-68df-42a8-943b-398e70275c66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052813877 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_
all.1052813877
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.1674301188
Short name T8
Test name
Test status
Simulation time 58748784945 ps
CPU time 299.05 seconds
Started Apr 25 12:46:27 PM PDT 24
Finished Apr 25 12:51:28 PM PDT 24
Peak memory 198552 kb
Host smart-d30c0a8c-8fdc-4836-afca-6845a85900d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674301188 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.1674301188
Directory /workspace/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.aon_timer_jump.931781720
Short name T67
Test name
Test status
Simulation time 547198822 ps
CPU time 0.64 seconds
Started Apr 25 12:46:24 PM PDT 24
Finished Apr 25 12:46:27 PM PDT 24
Peak memory 183456 kb
Host smart-6190c75a-7b95-4341-a6c4-b97d492eb361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931781720 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.931781720
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.2572131700
Short name T247
Test name
Test status
Simulation time 54007762113 ps
CPU time 36.07 seconds
Started Apr 25 12:46:24 PM PDT 24
Finished Apr 25 12:47:02 PM PDT 24
Peak memory 183588 kb
Host smart-9db5ec76-1c9f-4e15-a94e-bf09aa68654a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572131700 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.2572131700
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.317308016
Short name T179
Test name
Test status
Simulation time 538206490 ps
CPU time 1.43 seconds
Started Apr 25 12:46:25 PM PDT 24
Finished Apr 25 12:46:29 PM PDT 24
Peak memory 183480 kb
Host smart-f5fe34a7-f41f-4330-830e-d43f17c717fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317308016 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.317308016
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.1678872857
Short name T156
Test name
Test status
Simulation time 95059151792 ps
CPU time 69.77 seconds
Started Apr 25 12:46:27 PM PDT 24
Finished Apr 25 12:47:39 PM PDT 24
Peak memory 193600 kb
Host smart-a74c0f55-2e63-4a7b-b74c-1a9942730fc7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678872857 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_
all.1678872857
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.1203784281
Short name T214
Test name
Test status
Simulation time 73275628027 ps
CPU time 169.37 seconds
Started Apr 25 12:46:24 PM PDT 24
Finished Apr 25 12:49:16 PM PDT 24
Peak memory 198388 kb
Host smart-031f77df-2d29-4e5c-b405-0b607e303bec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203784281 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.1203784281
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.aon_timer_jump.1532704479
Short name T168
Test name
Test status
Simulation time 604953589 ps
CPU time 0.68 seconds
Started Apr 25 12:46:24 PM PDT 24
Finished Apr 25 12:46:26 PM PDT 24
Peak memory 183532 kb
Host smart-dd0cfbaf-b7e7-4178-bf8e-e3649175f1b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532704479 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.1532704479
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.2471417269
Short name T44
Test name
Test status
Simulation time 40668322295 ps
CPU time 30.73 seconds
Started Apr 25 12:46:24 PM PDT 24
Finished Apr 25 12:46:57 PM PDT 24
Peak memory 183548 kb
Host smart-a24065da-210c-4d59-b348-b8ae5d1c93a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471417269 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.2471417269
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.765227731
Short name T210
Test name
Test status
Simulation time 528978015 ps
CPU time 1.29 seconds
Started Apr 25 12:46:30 PM PDT 24
Finished Apr 25 12:46:33 PM PDT 24
Peak memory 183500 kb
Host smart-c1eb330f-3020-40d6-8f4e-2dc0f15fdcac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765227731 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.765227731
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.2444493188
Short name T182
Test name
Test status
Simulation time 182194200888 ps
CPU time 41.74 seconds
Started Apr 25 12:46:26 PM PDT 24
Finished Apr 25 12:47:10 PM PDT 24
Peak memory 194500 kb
Host smart-8a400006-85e0-41e7-a9e6-a73f9b83a048
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444493188 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_
all.2444493188
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.2293592600
Short name T82
Test name
Test status
Simulation time 119721949092 ps
CPU time 169.67 seconds
Started Apr 25 12:46:30 PM PDT 24
Finished Apr 25 12:49:22 PM PDT 24
Peak memory 206684 kb
Host smart-b76e6f62-8a5a-45cc-9c93-f31737cb73b9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293592600 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand_reset.2293592600
Directory /workspace/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.aon_timer_jump.4127872956
Short name T193
Test name
Test status
Simulation time 519456084 ps
CPU time 0.85 seconds
Started Apr 25 12:46:28 PM PDT 24
Finished Apr 25 12:46:31 PM PDT 24
Peak memory 183464 kb
Host smart-e3a71564-814a-4e32-94e1-fcfdb3e3265e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127872956 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.4127872956
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.1327138346
Short name T163
Test name
Test status
Simulation time 3427923109 ps
CPU time 3.44 seconds
Started Apr 25 12:46:30 PM PDT 24
Finished Apr 25 12:46:35 PM PDT 24
Peak memory 183628 kb
Host smart-531f52b6-d8e9-48b6-8132-e025009dfdba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327138346 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.1327138346
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.668126602
Short name T279
Test name
Test status
Simulation time 530708318 ps
CPU time 0.66 seconds
Started Apr 25 12:46:30 PM PDT 24
Finished Apr 25 12:46:33 PM PDT 24
Peak memory 183576 kb
Host smart-7b18fa4c-6c7c-4860-ab9e-77aeed8447a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668126602 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.668126602
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.1703418515
Short name T170
Test name
Test status
Simulation time 20792703213 ps
CPU time 33.94 seconds
Started Apr 25 12:46:30 PM PDT 24
Finished Apr 25 12:47:06 PM PDT 24
Peak memory 195168 kb
Host smart-a336580c-c770-45ae-8cd0-41ae8f1f777f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703418515 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_
all.1703418515
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.3867026606
Short name T204
Test name
Test status
Simulation time 64969660121 ps
CPU time 192.85 seconds
Started Apr 25 12:46:29 PM PDT 24
Finished Apr 25 12:49:44 PM PDT 24
Peak memory 198448 kb
Host smart-21f9e8a1-53e5-4237-8de9-176731f34a77
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867026606 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.3867026606
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_jump.710854376
Short name T205
Test name
Test status
Simulation time 603498280 ps
CPU time 0.97 seconds
Started Apr 25 12:45:55 PM PDT 24
Finished Apr 25 12:45:57 PM PDT 24
Peak memory 183492 kb
Host smart-909d7001-36c5-4315-80a2-74f6653f301c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710854376 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.710854376
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.4292969795
Short name T236
Test name
Test status
Simulation time 3026295549 ps
CPU time 2.79 seconds
Started Apr 25 12:45:53 PM PDT 24
Finished Apr 25 12:45:57 PM PDT 24
Peak memory 183492 kb
Host smart-04fc04fb-3c24-4240-9f2a-7ff57a218c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292969795 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.4292969795
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.3692906102
Short name T17
Test name
Test status
Simulation time 8078084823 ps
CPU time 13.46 seconds
Started Apr 25 12:45:58 PM PDT 24
Finished Apr 25 12:46:12 PM PDT 24
Peak memory 215244 kb
Host smart-c71e3bca-0dc4-4f8f-b493-1afe9f594942
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692906102 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.3692906102
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.3461622352
Short name T149
Test name
Test status
Simulation time 347090336 ps
CPU time 1.14 seconds
Started Apr 25 12:45:52 PM PDT 24
Finished Apr 25 12:45:54 PM PDT 24
Peak memory 183548 kb
Host smart-e8d86542-0ba7-4e96-b37a-fd15bc12ec30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461622352 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.3461622352
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.987053110
Short name T208
Test name
Test status
Simulation time 264701849225 ps
CPU time 218.57 seconds
Started Apr 25 12:46:05 PM PDT 24
Finished Apr 25 12:49:45 PM PDT 24
Peak memory 194148 kb
Host smart-80059e91-7f0c-40d4-9cdf-365d065fc471
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987053110 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_al
l.987053110
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_jump.1299366429
Short name T219
Test name
Test status
Simulation time 436867067 ps
CPU time 1.35 seconds
Started Apr 25 12:46:33 PM PDT 24
Finished Apr 25 12:46:36 PM PDT 24
Peak memory 183476 kb
Host smart-a62a20ba-2048-4179-b35e-9bff1db7046b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299366429 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.1299366429
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.1286345245
Short name T202
Test name
Test status
Simulation time 22643802977 ps
CPU time 15.66 seconds
Started Apr 25 12:46:29 PM PDT 24
Finished Apr 25 12:46:47 PM PDT 24
Peak memory 183620 kb
Host smart-4e441a48-6fa5-46e4-a588-703c9e8ead47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286345245 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.1286345245
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.520558208
Short name T125
Test name
Test status
Simulation time 568798692 ps
CPU time 1.01 seconds
Started Apr 25 12:46:34 PM PDT 24
Finished Apr 25 12:46:36 PM PDT 24
Peak memory 183568 kb
Host smart-5c591fa9-decb-4ae1-a8fc-01ed568839ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520558208 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.520558208
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.3312583657
Short name T98
Test name
Test status
Simulation time 52131662074 ps
CPU time 11.44 seconds
Started Apr 25 12:46:33 PM PDT 24
Finished Apr 25 12:46:46 PM PDT 24
Peak memory 183516 kb
Host smart-211b200f-52e0-4b1b-a46c-f7f7d269f29a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312583657 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_
all.3312583657
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.796440027
Short name T41
Test name
Test status
Simulation time 40938254341 ps
CPU time 458.46 seconds
Started Apr 25 12:46:31 PM PDT 24
Finished Apr 25 12:54:11 PM PDT 24
Peak memory 198524 kb
Host smart-a74d8903-16c9-4ce7-910a-1e923a5a984d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796440027 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.796440027
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.aon_timer_jump.1506489672
Short name T189
Test name
Test status
Simulation time 381293603 ps
CPU time 0.97 seconds
Started Apr 25 12:46:31 PM PDT 24
Finished Apr 25 12:46:33 PM PDT 24
Peak memory 183536 kb
Host smart-8d75da27-5a92-4778-b54a-768c47f98b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506489672 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.1506489672
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.1574559046
Short name T273
Test name
Test status
Simulation time 53877742422 ps
CPU time 41.82 seconds
Started Apr 25 12:46:31 PM PDT 24
Finished Apr 25 12:47:14 PM PDT 24
Peak memory 183588 kb
Host smart-bdf9c09d-579c-495a-b618-8da29afcfc11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574559046 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.1574559046
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.3073245706
Short name T278
Test name
Test status
Simulation time 597338510 ps
CPU time 0.6 seconds
Started Apr 25 12:46:28 PM PDT 24
Finished Apr 25 12:46:31 PM PDT 24
Peak memory 183496 kb
Host smart-369bd991-b3c8-465c-97dd-61cc632f3d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073245706 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.3073245706
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.3308237219
Short name T3
Test name
Test status
Simulation time 118629936923 ps
CPU time 102.13 seconds
Started Apr 25 12:46:28 PM PDT 24
Finished Apr 25 12:48:12 PM PDT 24
Peak memory 194856 kb
Host smart-63169574-dfb0-4bda-9186-f2c2acff42d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308237219 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_
all.3308237219
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.102414932
Short name T121
Test name
Test status
Simulation time 69744345281 ps
CPU time 715.52 seconds
Started Apr 25 12:46:30 PM PDT 24
Finished Apr 25 12:58:27 PM PDT 24
Peak memory 208620 kb
Host smart-3e9cac76-db47-4f61-868d-4126e2da18cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102414932 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.102414932
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.aon_timer_jump.2858162659
Short name T233
Test name
Test status
Simulation time 536661770 ps
CPU time 0.77 seconds
Started Apr 25 12:46:30 PM PDT 24
Finished Apr 25 12:46:33 PM PDT 24
Peak memory 183432 kb
Host smart-37a78353-bdc9-4b9f-8404-5e9b5e7eba60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858162659 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.2858162659
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.1597549526
Short name T102
Test name
Test status
Simulation time 26448215249 ps
CPU time 16.92 seconds
Started Apr 25 12:46:30 PM PDT 24
Finished Apr 25 12:46:49 PM PDT 24
Peak memory 191720 kb
Host smart-ec6f73de-c696-4f5c-a945-5ebfa0f36cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597549526 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.1597549526
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.2715911125
Short name T257
Test name
Test status
Simulation time 570772360 ps
CPU time 0.76 seconds
Started Apr 25 12:46:32 PM PDT 24
Finished Apr 25 12:46:34 PM PDT 24
Peak memory 183576 kb
Host smart-2a4ec6f1-b3b9-4bd7-b9c0-99d1a9a4a9a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715911125 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.2715911125
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.2184336311
Short name T18
Test name
Test status
Simulation time 150280969856 ps
CPU time 191.32 seconds
Started Apr 25 12:46:33 PM PDT 24
Finished Apr 25 12:49:46 PM PDT 24
Peak memory 191732 kb
Host smart-0321f87f-72c8-41bc-a71c-7ea6ce213310
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184336311 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_
all.2184336311
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.3999333594
Short name T143
Test name
Test status
Simulation time 41822900218 ps
CPU time 431.48 seconds
Started Apr 25 12:46:33 PM PDT 24
Finished Apr 25 12:53:46 PM PDT 24
Peak memory 198440 kb
Host smart-652e9027-8b8c-4396-8f08-4e22f53bd2c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999333594 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.3999333594
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.aon_timer_jump.3187024105
Short name T215
Test name
Test status
Simulation time 452632452 ps
CPU time 1.09 seconds
Started Apr 25 12:46:30 PM PDT 24
Finished Apr 25 12:46:33 PM PDT 24
Peak memory 183456 kb
Host smart-13adae04-827a-42ff-84db-db4055369300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187024105 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.3187024105
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.2942207951
Short name T144
Test name
Test status
Simulation time 47430530626 ps
CPU time 9.86 seconds
Started Apr 25 12:46:30 PM PDT 24
Finished Apr 25 12:46:42 PM PDT 24
Peak memory 183564 kb
Host smart-e7248da2-e20a-4914-972e-a29d54aae004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942207951 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.2942207951
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.1954052321
Short name T267
Test name
Test status
Simulation time 430323571 ps
CPU time 1.13 seconds
Started Apr 25 12:46:33 PM PDT 24
Finished Apr 25 12:46:36 PM PDT 24
Peak memory 183548 kb
Host smart-f8c70f2a-e77b-4485-926d-a9b10f62b88d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954052321 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.1954052321
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.3653264993
Short name T228
Test name
Test status
Simulation time 193197258295 ps
CPU time 33.16 seconds
Started Apr 25 12:46:29 PM PDT 24
Finished Apr 25 12:47:04 PM PDT 24
Peak memory 195132 kb
Host smart-0ca5dcec-e23c-46d2-a315-3b670ced5754
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653264993 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_
all.3653264993
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.2050839920
Short name T266
Test name
Test status
Simulation time 44836553151 ps
CPU time 477.89 seconds
Started Apr 25 12:46:33 PM PDT 24
Finished Apr 25 12:54:33 PM PDT 24
Peak memory 198420 kb
Host smart-d29bf150-e985-4d66-aa41-81590d9da558
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050839920 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.2050839920
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.aon_timer_jump.2390921889
Short name T253
Test name
Test status
Simulation time 398115898 ps
CPU time 1.06 seconds
Started Apr 25 12:46:47 PM PDT 24
Finished Apr 25 12:46:50 PM PDT 24
Peak memory 183500 kb
Host smart-998d1ca7-2670-45cc-bb20-0dc16ee54288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390921889 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.2390921889
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.2332991872
Short name T272
Test name
Test status
Simulation time 25144390414 ps
CPU time 39.97 seconds
Started Apr 25 12:46:30 PM PDT 24
Finished Apr 25 12:47:12 PM PDT 24
Peak memory 183496 kb
Host smart-f8884066-7385-4833-9777-036b036197ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332991872 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.2332991872
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.1980836335
Short name T256
Test name
Test status
Simulation time 596347179 ps
CPU time 0.76 seconds
Started Apr 25 12:46:30 PM PDT 24
Finished Apr 25 12:46:32 PM PDT 24
Peak memory 183560 kb
Host smart-7ead85f4-b57c-4afc-b4c2-d6a05bcd5057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980836335 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.1980836335
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.1475379279
Short name T217
Test name
Test status
Simulation time 384637391160 ps
CPU time 552.24 seconds
Started Apr 25 12:46:29 PM PDT 24
Finished Apr 25 12:55:44 PM PDT 24
Peak memory 194456 kb
Host smart-7bce38f5-f44a-4cb7-b0a3-dbdc9baa4a32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475379279 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_
all.1475379279
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.148883192
Short name T45
Test name
Test status
Simulation time 29830076853 ps
CPU time 316.69 seconds
Started Apr 25 12:46:32 PM PDT 24
Finished Apr 25 12:51:51 PM PDT 24
Peak memory 198504 kb
Host smart-dd92aad7-a463-4446-9924-fa27ad9dec0c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148883192 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.148883192
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.aon_timer_jump.140946638
Short name T172
Test name
Test status
Simulation time 464199415 ps
CPU time 0.6 seconds
Started Apr 25 12:46:33 PM PDT 24
Finished Apr 25 12:46:35 PM PDT 24
Peak memory 183532 kb
Host smart-687cdeb0-ab7e-4c18-9937-212f764c1ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140946638 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.140946638
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.728314112
Short name T9
Test name
Test status
Simulation time 573105342 ps
CPU time 0.75 seconds
Started Apr 25 12:46:33 PM PDT 24
Finished Apr 25 12:46:35 PM PDT 24
Peak memory 183452 kb
Host smart-f581b4fa-ff4c-4f11-ab18-78616f7938d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728314112 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.728314112
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.3561013207
Short name T142
Test name
Test status
Simulation time 203493257251 ps
CPU time 573.07 seconds
Started Apr 25 12:46:29 PM PDT 24
Finished Apr 25 12:56:04 PM PDT 24
Peak memory 199960 kb
Host smart-7e318e00-0bf8-4356-b0c6-448547ce305b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561013207 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.3561013207
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.aon_timer_jump.4109170502
Short name T260
Test name
Test status
Simulation time 522789178 ps
CPU time 1.16 seconds
Started Apr 25 12:46:33 PM PDT 24
Finished Apr 25 12:46:36 PM PDT 24
Peak memory 183536 kb
Host smart-f758d0e9-9107-4bd3-b482-8b044c4266c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109170502 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.4109170502
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.2513976103
Short name T275
Test name
Test status
Simulation time 51030795244 ps
CPU time 36.31 seconds
Started Apr 25 12:46:34 PM PDT 24
Finished Apr 25 12:47:12 PM PDT 24
Peak memory 183516 kb
Host smart-84e2cac0-f10c-42a1-a0b8-79c6c9e01541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513976103 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.2513976103
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.2157478643
Short name T65
Test name
Test status
Simulation time 423229215 ps
CPU time 0.7 seconds
Started Apr 25 12:46:28 PM PDT 24
Finished Apr 25 12:46:31 PM PDT 24
Peak memory 183536 kb
Host smart-82d3bf5b-ced5-4c47-8bb4-6138af1fbec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157478643 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.2157478643
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.349806481
Short name T222
Test name
Test status
Simulation time 243993368469 ps
CPU time 156.61 seconds
Started Apr 25 12:46:35 PM PDT 24
Finished Apr 25 12:49:13 PM PDT 24
Peak memory 194320 kb
Host smart-5abcea29-42cf-4908-a524-e5c185ded4ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349806481 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_a
ll.349806481
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.3669899504
Short name T100
Test name
Test status
Simulation time 11053173092 ps
CPU time 83.61 seconds
Started Apr 25 12:46:38 PM PDT 24
Finished Apr 25 12:48:03 PM PDT 24
Peak memory 198472 kb
Host smart-d020a361-bcd2-4c3d-b8a5-41485b1bac07
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669899504 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.3669899504
Directory /workspace/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.aon_timer_jump.1741313195
Short name T89
Test name
Test status
Simulation time 453146517 ps
CPU time 0.69 seconds
Started Apr 25 12:46:33 PM PDT 24
Finished Apr 25 12:46:35 PM PDT 24
Peak memory 183468 kb
Host smart-43e9e697-b621-4be2-bf4a-6b93d22cdee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741313195 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.1741313195
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.2203569117
Short name T203
Test name
Test status
Simulation time 10329903971 ps
CPU time 10.38 seconds
Started Apr 25 12:46:36 PM PDT 24
Finished Apr 25 12:46:48 PM PDT 24
Peak memory 183520 kb
Host smart-9961736b-e056-4e53-b41c-1ad41998ed37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203569117 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.2203569117
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.348972943
Short name T230
Test name
Test status
Simulation time 559773995 ps
CPU time 1.03 seconds
Started Apr 25 12:46:39 PM PDT 24
Finished Apr 25 12:46:41 PM PDT 24
Peak memory 183572 kb
Host smart-fb9f8f73-68ab-43e4-aa0e-90f6ebcda97a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348972943 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.348972943
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.3056720648
Short name T197
Test name
Test status
Simulation time 129191917066 ps
CPU time 38.76 seconds
Started Apr 25 12:46:40 PM PDT 24
Finished Apr 25 12:47:20 PM PDT 24
Peak memory 195388 kb
Host smart-346533f5-07b0-4e5f-8890-217efc957de5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056720648 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_
all.3056720648
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.757254497
Short name T79
Test name
Test status
Simulation time 43524914444 ps
CPU time 341.09 seconds
Started Apr 25 12:46:36 PM PDT 24
Finished Apr 25 12:52:19 PM PDT 24
Peak memory 198528 kb
Host smart-f980e9b6-5254-4d2e-962c-f872a0a9537a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757254497 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.757254497
Directory /workspace/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_jump.1915941639
Short name T186
Test name
Test status
Simulation time 474444777 ps
CPU time 1.26 seconds
Started Apr 25 12:46:34 PM PDT 24
Finished Apr 25 12:46:36 PM PDT 24
Peak memory 183440 kb
Host smart-c0be681e-4297-4dba-9e47-996fc5414667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915941639 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.1915941639
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.4174010061
Short name T93
Test name
Test status
Simulation time 53751387683 ps
CPU time 83.17 seconds
Started Apr 25 12:46:36 PM PDT 24
Finished Apr 25 12:48:01 PM PDT 24
Peak memory 191832 kb
Host smart-111ee312-e1e8-4d40-95cc-04e9fec84b52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174010061 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.4174010061
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.1791117877
Short name T251
Test name
Test status
Simulation time 446075006 ps
CPU time 0.76 seconds
Started Apr 25 12:46:35 PM PDT 24
Finished Apr 25 12:46:36 PM PDT 24
Peak memory 183516 kb
Host smart-0e9c5634-f561-473d-8d8c-040059b94ef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791117877 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.1791117877
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.2144364569
Short name T68
Test name
Test status
Simulation time 135987562854 ps
CPU time 28.31 seconds
Started Apr 25 12:46:38 PM PDT 24
Finished Apr 25 12:47:08 PM PDT 24
Peak memory 183532 kb
Host smart-05b9ee9c-6f66-4327-8621-2ad359e2f488
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144364569 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_
all.2144364569
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.328267293
Short name T276
Test name
Test status
Simulation time 24853824897 ps
CPU time 270.78 seconds
Started Apr 25 12:46:51 PM PDT 24
Finished Apr 25 12:51:23 PM PDT 24
Peak memory 198504 kb
Host smart-f9925975-c91b-4b4c-88c8-0594f824581d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328267293 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.328267293
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.aon_timer_jump.1072238032
Short name T245
Test name
Test status
Simulation time 559338894 ps
CPU time 0.96 seconds
Started Apr 25 12:46:37 PM PDT 24
Finished Apr 25 12:46:39 PM PDT 24
Peak memory 183456 kb
Host smart-88ac6628-8f01-4faf-b76d-ae5a21dfe20e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072238032 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.1072238032
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.4019823978
Short name T99
Test name
Test status
Simulation time 18505816773 ps
CPU time 7.42 seconds
Started Apr 25 12:46:34 PM PDT 24
Finished Apr 25 12:46:42 PM PDT 24
Peak memory 191768 kb
Host smart-ca9943f5-c5d1-41b7-ba89-b287dca3d3e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019823978 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.4019823978
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.2030697876
Short name T192
Test name
Test status
Simulation time 370157329 ps
CPU time 1.14 seconds
Started Apr 25 12:46:33 PM PDT 24
Finished Apr 25 12:46:36 PM PDT 24
Peak memory 183560 kb
Host smart-d56187d9-2c85-433c-b3b5-b91f964d6b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030697876 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.2030697876
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.1410881605
Short name T232
Test name
Test status
Simulation time 453679443322 ps
CPU time 322.51 seconds
Started Apr 25 12:46:34 PM PDT 24
Finished Apr 25 12:51:57 PM PDT 24
Peak memory 191760 kb
Host smart-6d1899fb-7e03-4bf5-a115-61b5b33c8ca5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410881605 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_
all.1410881605
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_jump.4245919401
Short name T150
Test name
Test status
Simulation time 624247433 ps
CPU time 0.85 seconds
Started Apr 25 12:45:59 PM PDT 24
Finished Apr 25 12:46:01 PM PDT 24
Peak memory 183444 kb
Host smart-c7bf7175-1d97-4b5b-882c-446d3ba8770c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245919401 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.4245919401
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.2097613711
Short name T180
Test name
Test status
Simulation time 28497158298 ps
CPU time 9.25 seconds
Started Apr 25 12:45:59 PM PDT 24
Finished Apr 25 12:46:09 PM PDT 24
Peak memory 183508 kb
Host smart-0afd2375-c9ca-4768-802f-561887c267b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097613711 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.2097613711
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.2809129916
Short name T165
Test name
Test status
Simulation time 589526145 ps
CPU time 1.18 seconds
Started Apr 25 12:46:03 PM PDT 24
Finished Apr 25 12:46:05 PM PDT 24
Peak memory 183524 kb
Host smart-54a33032-9705-47a6-95cf-284a96d93c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809129916 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.2809129916
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.1454556308
Short name T169
Test name
Test status
Simulation time 91231383199 ps
CPU time 143.57 seconds
Started Apr 25 12:46:00 PM PDT 24
Finished Apr 25 12:48:26 PM PDT 24
Peak memory 183604 kb
Host smart-b50daa93-c5e5-4413-b7e6-9cab25478ef8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454556308 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_a
ll.1454556308
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.25404777
Short name T69
Test name
Test status
Simulation time 38380083665 ps
CPU time 271.89 seconds
Started Apr 25 12:46:06 PM PDT 24
Finished Apr 25 12:50:40 PM PDT 24
Peak memory 198376 kb
Host smart-e25fba10-357b-4370-a61f-3bb86dcc83b6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25404777 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.25404777
Directory /workspace/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.aon_timer_jump.2169479736
Short name T113
Test name
Test status
Simulation time 489957771 ps
CPU time 0.88 seconds
Started Apr 25 12:46:05 PM PDT 24
Finished Apr 25 12:46:07 PM PDT 24
Peak memory 183492 kb
Host smart-e560b8f6-b6fa-4943-8f00-92ebc45b39dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169479736 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.2169479736
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.2089698970
Short name T162
Test name
Test status
Simulation time 5061459944 ps
CPU time 3.07 seconds
Started Apr 25 12:46:03 PM PDT 24
Finished Apr 25 12:46:07 PM PDT 24
Peak memory 183504 kb
Host smart-dec73233-3db2-4c8f-bd3f-45283d07d3d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089698970 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.2089698970
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.2742947523
Short name T6
Test name
Test status
Simulation time 375421241 ps
CPU time 1.08 seconds
Started Apr 25 12:46:01 PM PDT 24
Finished Apr 25 12:46:04 PM PDT 24
Peak memory 183568 kb
Host smart-0e02bf9a-561f-4930-887c-dad4ac6d6c12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742947523 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.2742947523
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.1121027014
Short name T271
Test name
Test status
Simulation time 157596735082 ps
CPU time 226.16 seconds
Started Apr 25 12:46:02 PM PDT 24
Finished Apr 25 12:49:49 PM PDT 24
Peak memory 194980 kb
Host smart-0f695167-593c-4664-b382-61c81e316722
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121027014 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_a
ll.1121027014
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.3495111510
Short name T84
Test name
Test status
Simulation time 373931764706 ps
CPU time 514.7 seconds
Started Apr 25 12:45:59 PM PDT 24
Finished Apr 25 12:54:35 PM PDT 24
Peak memory 198516 kb
Host smart-916fe994-b2f3-4588-a69b-601532d8a03c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495111510 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.3495111510
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.aon_timer_jump.3554514490
Short name T234
Test name
Test status
Simulation time 471336056 ps
CPU time 1.23 seconds
Started Apr 25 12:45:56 PM PDT 24
Finished Apr 25 12:45:58 PM PDT 24
Peak memory 183548 kb
Host smart-3131968a-bb81-4de4-ba98-18176bbcc858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554514490 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.3554514490
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.959654282
Short name T226
Test name
Test status
Simulation time 54483097351 ps
CPU time 36.27 seconds
Started Apr 25 12:46:03 PM PDT 24
Finished Apr 25 12:46:40 PM PDT 24
Peak memory 183504 kb
Host smart-ea149ea8-4113-4c75-83de-702b452b10b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959654282 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.959654282
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.2349620262
Short name T159
Test name
Test status
Simulation time 346554702 ps
CPU time 0.93 seconds
Started Apr 25 12:46:04 PM PDT 24
Finished Apr 25 12:46:06 PM PDT 24
Peak memory 183408 kb
Host smart-0523c93f-cb1b-4518-b046-ac0ebd7270e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349620262 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.2349620262
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.3149353988
Short name T63
Test name
Test status
Simulation time 51894576377 ps
CPU time 40.26 seconds
Started Apr 25 12:46:01 PM PDT 24
Finished Apr 25 12:46:43 PM PDT 24
Peak memory 183596 kb
Host smart-e62f8c8d-0813-47c0-b414-84dbab7ac270
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149353988 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_a
ll.3149353988
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.2166924335
Short name T101
Test name
Test status
Simulation time 33970763429 ps
CPU time 285.63 seconds
Started Apr 25 12:46:05 PM PDT 24
Finished Apr 25 12:50:52 PM PDT 24
Peak memory 198444 kb
Host smart-3401297c-44af-4878-9764-6db5b8613a79
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166924335 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.2166924335
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.aon_timer_jump.764667044
Short name T216
Test name
Test status
Simulation time 571493064 ps
CPU time 1.5 seconds
Started Apr 25 12:46:01 PM PDT 24
Finished Apr 25 12:46:04 PM PDT 24
Peak memory 183576 kb
Host smart-692619af-99cd-4906-b37f-0e827976a474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764667044 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.764667044
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.2410948751
Short name T24
Test name
Test status
Simulation time 44814001786 ps
CPU time 16.13 seconds
Started Apr 25 12:45:57 PM PDT 24
Finished Apr 25 12:46:14 PM PDT 24
Peak memory 191804 kb
Host smart-2ff35e2d-1ddc-4dfa-a8b5-88de6af5b47f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410948751 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.2410948751
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.2160245866
Short name T263
Test name
Test status
Simulation time 581631429 ps
CPU time 1.47 seconds
Started Apr 25 12:46:03 PM PDT 24
Finished Apr 25 12:46:05 PM PDT 24
Peak memory 183568 kb
Host smart-f4afdb1b-b81a-41fd-a20f-9ec128f73e8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160245866 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.2160245866
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.562847175
Short name T138
Test name
Test status
Simulation time 84335452461 ps
CPU time 32.1 seconds
Started Apr 25 12:46:02 PM PDT 24
Finished Apr 25 12:46:35 PM PDT 24
Peak memory 183484 kb
Host smart-be673ccd-630e-412c-84e4-a23b04bc809d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562847175 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_al
l.562847175
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_jump.3185194209
Short name T33
Test name
Test status
Simulation time 379728936 ps
CPU time 1.08 seconds
Started Apr 25 12:46:01 PM PDT 24
Finished Apr 25 12:46:04 PM PDT 24
Peak memory 183544 kb
Host smart-2b5a0135-b576-440d-9c28-4c8f98eccd78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185194209 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.3185194209
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.492525190
Short name T26
Test name
Test status
Simulation time 15508388986 ps
CPU time 7.72 seconds
Started Apr 25 12:46:05 PM PDT 24
Finished Apr 25 12:46:14 PM PDT 24
Peak memory 191832 kb
Host smart-1d7eb25d-0df0-4e8e-806d-85f75b34093b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492525190 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.492525190
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.2858233809
Short name T151
Test name
Test status
Simulation time 470451687 ps
CPU time 1.27 seconds
Started Apr 25 12:46:03 PM PDT 24
Finished Apr 25 12:46:06 PM PDT 24
Peak memory 183560 kb
Host smart-b910bf28-05e4-4ec3-873b-29267acc717c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858233809 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.2858233809
Directory /workspace/9.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.102308842
Short name T120
Test name
Test status
Simulation time 203826261974 ps
CPU time 169.85 seconds
Started Apr 25 12:46:02 PM PDT 24
Finished Apr 25 12:48:53 PM PDT 24
Peak memory 183552 kb
Host smart-f9bdab0a-f47f-49b7-9d59-990276895e40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102308842 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_al
l.102308842
Directory /workspace/9.aon_timer_stress_all/latest
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