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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
92.98 99.25 93.67 100.00 98.40 99.51 67.06


Total test records in report: 416
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html
T277 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.1570415296 Apr 28 02:16:39 PM PDT 24 Apr 28 02:16:41 PM PDT 24 347429534 ps
T100 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.744556782 Apr 28 02:16:36 PM PDT 24 Apr 28 02:16:38 PM PDT 24 421810740 ps
T278 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.3923883148 Apr 28 02:16:20 PM PDT 24 Apr 28 02:16:21 PM PDT 24 352464054 ps
T83 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.2302448672 Apr 28 02:16:34 PM PDT 24 Apr 28 02:16:36 PM PDT 24 440215481 ps
T36 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.438164373 Apr 28 02:16:29 PM PDT 24 Apr 28 02:16:32 PM PDT 24 4497642311 ps
T279 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.3352505823 Apr 28 02:16:34 PM PDT 24 Apr 28 02:16:37 PM PDT 24 499482153 ps
T280 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.3455631082 Apr 28 02:16:23 PM PDT 24 Apr 28 02:16:25 PM PDT 24 445153758 ps
T76 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.3396211789 Apr 28 02:16:28 PM PDT 24 Apr 28 02:16:31 PM PDT 24 1384763116 ps
T281 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.3308566845 Apr 28 02:16:28 PM PDT 24 Apr 28 02:16:29 PM PDT 24 543837876 ps
T37 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.2067031793 Apr 28 02:16:29 PM PDT 24 Apr 28 02:16:45 PM PDT 24 8957763490 ps
T77 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.556451453 Apr 28 02:16:33 PM PDT 24 Apr 28 02:16:34 PM PDT 24 450277092 ps
T98 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.4001923448 Apr 28 02:16:24 PM PDT 24 Apr 28 02:16:29 PM PDT 24 4383573072 ps
T282 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.290837596 Apr 28 02:16:33 PM PDT 24 Apr 28 02:16:34 PM PDT 24 353837533 ps
T283 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.3366778080 Apr 28 02:16:38 PM PDT 24 Apr 28 02:16:41 PM PDT 24 390359356 ps
T284 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.3044994951 Apr 28 02:16:22 PM PDT 24 Apr 28 02:16:24 PM PDT 24 716282877 ps
T285 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.507521617 Apr 28 02:16:13 PM PDT 24 Apr 28 02:16:15 PM PDT 24 739005998 ps
T286 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.412232045 Apr 28 02:16:28 PM PDT 24 Apr 28 02:16:30 PM PDT 24 356776174 ps
T78 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.2235209455 Apr 28 02:16:17 PM PDT 24 Apr 28 02:16:22 PM PDT 24 1795322293 ps
T287 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.1917811191 Apr 28 02:16:24 PM PDT 24 Apr 28 02:16:36 PM PDT 24 7092223322 ps
T79 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.365392260 Apr 28 02:16:14 PM PDT 24 Apr 28 02:16:20 PM PDT 24 2055125823 ps
T288 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.3905957681 Apr 28 02:16:39 PM PDT 24 Apr 28 02:16:41 PM PDT 24 421594086 ps
T289 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.1960563709 Apr 28 02:16:28 PM PDT 24 Apr 28 02:16:29 PM PDT 24 473133572 ps
T53 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.2393252201 Apr 28 02:16:15 PM PDT 24 Apr 28 02:16:17 PM PDT 24 420185164 ps
T290 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.1807683970 Apr 28 02:16:16 PM PDT 24 Apr 28 02:16:18 PM PDT 24 573345883 ps
T291 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.2406960734 Apr 28 02:16:24 PM PDT 24 Apr 28 02:16:27 PM PDT 24 436934009 ps
T292 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.382990469 Apr 28 02:16:12 PM PDT 24 Apr 28 02:16:14 PM PDT 24 501934677 ps
T293 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.1550051127 Apr 28 02:16:24 PM PDT 24 Apr 28 02:16:28 PM PDT 24 7781370045 ps
T54 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.1848432734 Apr 28 02:16:33 PM PDT 24 Apr 28 02:16:34 PM PDT 24 318791390 ps
T99 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.1222048454 Apr 28 02:16:31 PM PDT 24 Apr 28 02:16:46 PM PDT 24 8141139248 ps
T294 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.1108442836 Apr 28 02:16:33 PM PDT 24 Apr 28 02:16:35 PM PDT 24 515648746 ps
T55 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.1428020829 Apr 28 02:16:34 PM PDT 24 Apr 28 02:16:37 PM PDT 24 490946389 ps
T295 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.3285960538 Apr 28 02:16:17 PM PDT 24 Apr 28 02:16:19 PM PDT 24 473971953 ps
T296 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.2100944825 Apr 28 02:16:27 PM PDT 24 Apr 28 02:16:31 PM PDT 24 425054530 ps
T297 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.439942071 Apr 28 02:16:13 PM PDT 24 Apr 28 02:16:15 PM PDT 24 322246147 ps
T80 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.1563421421 Apr 28 02:16:14 PM PDT 24 Apr 28 02:16:16 PM PDT 24 832371126 ps
T298 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.115314414 Apr 28 02:16:18 PM PDT 24 Apr 28 02:16:19 PM PDT 24 650622278 ps
T299 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.2045606833 Apr 28 02:16:34 PM PDT 24 Apr 28 02:16:36 PM PDT 24 363306126 ps
T300 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.2041589358 Apr 28 02:16:24 PM PDT 24 Apr 28 02:16:27 PM PDT 24 440467227 ps
T301 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.769931663 Apr 28 02:16:25 PM PDT 24 Apr 28 02:16:30 PM PDT 24 8748138949 ps
T302 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.117925537 Apr 28 02:16:13 PM PDT 24 Apr 28 02:16:16 PM PDT 24 4735926599 ps
T56 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.4172947048 Apr 28 02:16:12 PM PDT 24 Apr 28 02:16:13 PM PDT 24 499448748 ps
T303 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.591400947 Apr 28 02:16:34 PM PDT 24 Apr 28 02:16:36 PM PDT 24 383769027 ps
T304 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.2809496299 Apr 28 02:16:15 PM PDT 24 Apr 28 02:16:17 PM PDT 24 409249363 ps
T305 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.1020238612 Apr 28 02:16:08 PM PDT 24 Apr 28 02:16:15 PM PDT 24 7121608730 ps
T306 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.2047130231 Apr 28 02:16:15 PM PDT 24 Apr 28 02:16:30 PM PDT 24 8135941825 ps
T307 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.2789113475 Apr 28 02:16:31 PM PDT 24 Apr 28 02:16:33 PM PDT 24 447882619 ps
T308 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.2838162659 Apr 28 02:16:25 PM PDT 24 Apr 28 02:16:28 PM PDT 24 1474635065 ps
T57 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.2461177980 Apr 28 02:16:24 PM PDT 24 Apr 28 02:16:25 PM PDT 24 473925496 ps
T309 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.3008675044 Apr 28 02:16:40 PM PDT 24 Apr 28 02:16:42 PM PDT 24 382787429 ps
T310 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.4014474601 Apr 28 02:16:29 PM PDT 24 Apr 28 02:16:31 PM PDT 24 446695429 ps
T311 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.1155443606 Apr 28 02:16:16 PM PDT 24 Apr 28 02:16:18 PM PDT 24 331023483 ps
T312 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.2878195144 Apr 28 02:16:41 PM PDT 24 Apr 28 02:16:43 PM PDT 24 420432962 ps
T313 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.2023858925 Apr 28 02:16:13 PM PDT 24 Apr 28 02:16:20 PM PDT 24 7833223820 ps
T58 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.3686928562 Apr 28 02:16:23 PM PDT 24 Apr 28 02:16:25 PM PDT 24 391938051 ps
T314 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.2373490227 Apr 28 02:16:19 PM PDT 24 Apr 28 02:16:21 PM PDT 24 432364108 ps
T315 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.1332096807 Apr 28 02:16:32 PM PDT 24 Apr 28 02:16:34 PM PDT 24 3075466693 ps
T316 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.2568469732 Apr 28 02:16:09 PM PDT 24 Apr 28 02:16:10 PM PDT 24 626533431 ps
T317 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.224864990 Apr 28 02:16:33 PM PDT 24 Apr 28 02:16:35 PM PDT 24 424752539 ps
T318 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.4035831659 Apr 28 02:16:09 PM PDT 24 Apr 28 02:16:14 PM PDT 24 8079549475 ps
T319 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.1757779447 Apr 28 02:16:32 PM PDT 24 Apr 28 02:16:34 PM PDT 24 397264050 ps
T320 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.1108712129 Apr 28 02:16:22 PM PDT 24 Apr 28 02:16:28 PM PDT 24 9453870987 ps
T321 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.947556757 Apr 28 02:16:34 PM PDT 24 Apr 28 02:16:35 PM PDT 24 375551386 ps
T322 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.564212898 Apr 28 02:16:35 PM PDT 24 Apr 28 02:16:38 PM PDT 24 574775634 ps
T323 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.3558248582 Apr 28 02:16:32 PM PDT 24 Apr 28 02:16:35 PM PDT 24 1770099774 ps
T324 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.4090835162 Apr 28 02:16:36 PM PDT 24 Apr 28 02:16:38 PM PDT 24 501473731 ps
T325 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.1331695155 Apr 28 02:16:12 PM PDT 24 Apr 28 02:16:14 PM PDT 24 624485646 ps
T97 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.486501339 Apr 28 02:16:31 PM PDT 24 Apr 28 02:16:36 PM PDT 24 8474725916 ps
T59 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.3344872558 Apr 28 02:16:09 PM PDT 24 Apr 28 02:16:11 PM PDT 24 660434270 ps
T326 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.672298496 Apr 28 02:16:14 PM PDT 24 Apr 28 02:16:16 PM PDT 24 359039030 ps
T327 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.215568474 Apr 28 02:16:31 PM PDT 24 Apr 28 02:16:33 PM PDT 24 425640124 ps
T328 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.1649942626 Apr 28 02:16:39 PM PDT 24 Apr 28 02:16:41 PM PDT 24 284690424 ps
T62 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.1687357297 Apr 28 02:16:14 PM PDT 24 Apr 28 02:16:16 PM PDT 24 458850139 ps
T329 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.176400649 Apr 28 02:16:31 PM PDT 24 Apr 28 02:16:34 PM PDT 24 1184495081 ps
T330 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.2915046221 Apr 28 02:16:09 PM PDT 24 Apr 28 02:16:10 PM PDT 24 349329774 ps
T63 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.686695348 Apr 28 02:16:29 PM PDT 24 Apr 28 02:16:31 PM PDT 24 497314214 ps
T331 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.2660464156 Apr 28 02:16:29 PM PDT 24 Apr 28 02:16:31 PM PDT 24 285947786 ps
T332 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.3856552552 Apr 28 02:16:22 PM PDT 24 Apr 28 02:16:24 PM PDT 24 2114441856 ps
T333 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.4042498451 Apr 28 02:16:27 PM PDT 24 Apr 28 02:16:29 PM PDT 24 360134561 ps
T334 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.3598114121 Apr 28 02:16:20 PM PDT 24 Apr 28 02:16:22 PM PDT 24 419842633 ps
T335 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.2483028651 Apr 28 02:16:33 PM PDT 24 Apr 28 02:16:34 PM PDT 24 334078380 ps
T336 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.1578746237 Apr 28 02:16:28 PM PDT 24 Apr 28 02:16:30 PM PDT 24 573976143 ps
T337 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.1088369871 Apr 28 02:16:09 PM PDT 24 Apr 28 02:16:10 PM PDT 24 335581716 ps
T338 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.2453709371 Apr 28 02:16:28 PM PDT 24 Apr 28 02:16:31 PM PDT 24 623953527 ps
T339 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.2916638495 Apr 28 02:16:32 PM PDT 24 Apr 28 02:16:33 PM PDT 24 473871186 ps
T340 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.4019364463 Apr 28 02:16:39 PM PDT 24 Apr 28 02:16:41 PM PDT 24 297945169 ps
T341 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.3043950149 Apr 28 02:16:28 PM PDT 24 Apr 28 02:16:33 PM PDT 24 8280493315 ps
T342 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.2661196654 Apr 28 02:16:35 PM PDT 24 Apr 28 02:16:37 PM PDT 24 2718338026 ps
T343 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.3923945817 Apr 28 02:16:21 PM PDT 24 Apr 28 02:16:23 PM PDT 24 538390424 ps
T344 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.706527457 Apr 28 02:16:15 PM PDT 24 Apr 28 02:16:17 PM PDT 24 597055785 ps
T345 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.602241383 Apr 28 02:16:14 PM PDT 24 Apr 28 02:16:35 PM PDT 24 13988455931 ps
T346 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.2517042073 Apr 28 02:16:25 PM PDT 24 Apr 28 02:16:27 PM PDT 24 359486993 ps
T347 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.1996061072 Apr 28 02:16:25 PM PDT 24 Apr 28 02:16:27 PM PDT 24 323056522 ps
T348 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.2769925454 Apr 28 02:16:24 PM PDT 24 Apr 28 02:16:26 PM PDT 24 528923775 ps
T349 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.3533473596 Apr 28 02:16:09 PM PDT 24 Apr 28 02:16:11 PM PDT 24 4229811806 ps
T350 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.744743751 Apr 28 02:16:35 PM PDT 24 Apr 28 02:16:37 PM PDT 24 391222058 ps
T351 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.634829417 Apr 28 02:16:38 PM PDT 24 Apr 28 02:16:40 PM PDT 24 295391034 ps
T352 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.1707719525 Apr 28 02:16:16 PM PDT 24 Apr 28 02:16:18 PM PDT 24 512384964 ps
T353 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.2968518825 Apr 28 02:16:47 PM PDT 24 Apr 28 02:16:49 PM PDT 24 532194835 ps
T354 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.2844117899 Apr 28 02:16:26 PM PDT 24 Apr 28 02:16:29 PM PDT 24 570437560 ps
T355 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.449153099 Apr 28 02:16:23 PM PDT 24 Apr 28 02:16:25 PM PDT 24 477569751 ps
T356 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.4021845529 Apr 28 02:16:26 PM PDT 24 Apr 28 02:16:28 PM PDT 24 708340288 ps
T357 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.705093875 Apr 28 02:16:32 PM PDT 24 Apr 28 02:16:33 PM PDT 24 286179432 ps
T358 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.1343796501 Apr 28 02:16:21 PM PDT 24 Apr 28 02:16:30 PM PDT 24 3431355435 ps
T359 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.1345432934 Apr 28 02:16:35 PM PDT 24 Apr 28 02:16:37 PM PDT 24 364478185 ps
T360 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.3726427006 Apr 28 02:16:40 PM PDT 24 Apr 28 02:16:41 PM PDT 24 560641931 ps
T361 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.2394481009 Apr 28 02:16:24 PM PDT 24 Apr 28 02:16:26 PM PDT 24 383455517 ps
T362 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.485757519 Apr 28 02:16:28 PM PDT 24 Apr 28 02:16:30 PM PDT 24 356635825 ps
T363 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.249919626 Apr 28 02:16:39 PM PDT 24 Apr 28 02:16:41 PM PDT 24 411136218 ps
T364 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.403249973 Apr 28 02:16:25 PM PDT 24 Apr 28 02:16:26 PM PDT 24 384083108 ps
T60 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.2613063172 Apr 28 02:16:28 PM PDT 24 Apr 28 02:16:30 PM PDT 24 537736617 ps
T365 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.7483498 Apr 28 02:16:22 PM PDT 24 Apr 28 02:16:24 PM PDT 24 1068222431 ps
T366 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.3152757310 Apr 28 02:16:40 PM PDT 24 Apr 28 02:16:41 PM PDT 24 531101488 ps
T367 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.2132494348 Apr 28 02:16:28 PM PDT 24 Apr 28 02:16:31 PM PDT 24 1243790406 ps
T368 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.3548896482 Apr 28 02:16:27 PM PDT 24 Apr 28 02:16:30 PM PDT 24 1357616121 ps
T369 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.84826789 Apr 28 02:16:23 PM PDT 24 Apr 28 02:16:27 PM PDT 24 1134547141 ps
T370 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.2387321166 Apr 28 02:16:15 PM PDT 24 Apr 28 02:16:22 PM PDT 24 4070631812 ps
T371 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.2315190786 Apr 28 02:16:37 PM PDT 24 Apr 28 02:16:39 PM PDT 24 481007009 ps
T372 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.2354039845 Apr 28 02:16:38 PM PDT 24 Apr 28 02:16:40 PM PDT 24 867175072 ps
T75 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.3051554074 Apr 28 02:16:32 PM PDT 24 Apr 28 02:16:34 PM PDT 24 439215008 ps
T373 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.2719869700 Apr 28 02:16:19 PM PDT 24 Apr 28 02:16:21 PM PDT 24 526865419 ps
T374 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.245142359 Apr 28 02:16:27 PM PDT 24 Apr 28 02:16:30 PM PDT 24 504062718 ps
T375 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.3550870371 Apr 28 02:16:30 PM PDT 24 Apr 28 02:16:33 PM PDT 24 333405185 ps
T376 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.1668763831 Apr 28 02:16:19 PM PDT 24 Apr 28 02:16:21 PM PDT 24 509183444 ps
T377 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.214838895 Apr 28 02:16:35 PM PDT 24 Apr 28 02:16:37 PM PDT 24 358005029 ps
T378 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.1773484499 Apr 28 02:16:17 PM PDT 24 Apr 28 02:16:19 PM PDT 24 442487364 ps
T379 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.3664165578 Apr 28 02:16:21 PM PDT 24 Apr 28 02:16:23 PM PDT 24 648233596 ps
T380 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.496271350 Apr 28 02:16:24 PM PDT 24 Apr 28 02:16:26 PM PDT 24 357066646 ps
T381 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.1037861474 Apr 28 02:16:15 PM PDT 24 Apr 28 02:16:17 PM PDT 24 542024527 ps
T382 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.2117300278 Apr 28 02:16:13 PM PDT 24 Apr 28 02:16:15 PM PDT 24 2519769191 ps
T383 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.2140626544 Apr 28 02:16:17 PM PDT 24 Apr 28 02:16:24 PM PDT 24 7736618591 ps
T384 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.2858024448 Apr 28 02:16:30 PM PDT 24 Apr 28 02:16:32 PM PDT 24 345320463 ps
T385 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.353661053 Apr 28 02:16:28 PM PDT 24 Apr 28 02:16:29 PM PDT 24 352292179 ps
T386 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.4095765590 Apr 28 02:16:13 PM PDT 24 Apr 28 02:16:16 PM PDT 24 4676609924 ps
T387 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.2429242400 Apr 28 02:16:24 PM PDT 24 Apr 28 02:16:26 PM PDT 24 442901243 ps
T388 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.833018098 Apr 28 02:16:44 PM PDT 24 Apr 28 02:16:46 PM PDT 24 451173243 ps
T389 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.1795047821 Apr 28 02:16:20 PM PDT 24 Apr 28 02:16:24 PM PDT 24 2692898646 ps
T61 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.512447666 Apr 28 02:16:14 PM PDT 24 Apr 28 02:16:16 PM PDT 24 503545893 ps
T390 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.3782128554 Apr 28 02:16:14 PM PDT 24 Apr 28 02:16:15 PM PDT 24 394001371 ps
T391 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.1492803254 Apr 28 02:16:23 PM PDT 24 Apr 28 02:16:25 PM PDT 24 705769364 ps
T64 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.3374081374 Apr 28 02:16:14 PM PDT 24 Apr 28 02:16:26 PM PDT 24 7107631372 ps
T392 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.3926446447 Apr 28 02:16:15 PM PDT 24 Apr 28 02:16:17 PM PDT 24 395043582 ps
T393 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.3713204024 Apr 28 02:16:35 PM PDT 24 Apr 28 02:16:37 PM PDT 24 560953182 ps
T394 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.1417960364 Apr 28 02:16:13 PM PDT 24 Apr 28 02:16:15 PM PDT 24 511711136 ps
T395 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.1275573280 Apr 28 02:16:33 PM PDT 24 Apr 28 02:16:37 PM PDT 24 2091621821 ps
T396 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.894780702 Apr 28 02:16:15 PM PDT 24 Apr 28 02:16:16 PM PDT 24 517267286 ps
T397 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.3913012535 Apr 28 02:16:21 PM PDT 24 Apr 28 02:16:46 PM PDT 24 13939424566 ps
T398 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.1460021862 Apr 28 02:16:18 PM PDT 24 Apr 28 02:16:19 PM PDT 24 1212295274 ps
T399 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.215449429 Apr 28 02:16:27 PM PDT 24 Apr 28 02:16:31 PM PDT 24 4592698605 ps
T400 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.781252616 Apr 28 02:16:29 PM PDT 24 Apr 28 02:16:31 PM PDT 24 467465252 ps
T401 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.947906212 Apr 28 02:16:22 PM PDT 24 Apr 28 02:16:28 PM PDT 24 8655815309 ps
T402 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.2832502622 Apr 28 02:16:36 PM PDT 24 Apr 28 02:16:39 PM PDT 24 365159565 ps
T403 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.343226020 Apr 28 02:16:19 PM PDT 24 Apr 28 02:16:21 PM PDT 24 580796542 ps
T404 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.3931496175 Apr 28 02:16:19 PM PDT 24 Apr 28 02:16:20 PM PDT 24 487100639 ps
T405 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.3071448930 Apr 28 02:16:25 PM PDT 24 Apr 28 02:16:27 PM PDT 24 580912741 ps
T406 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.3803270922 Apr 28 02:16:19 PM PDT 24 Apr 28 02:16:21 PM PDT 24 543836092 ps
T407 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.2859061365 Apr 28 02:16:33 PM PDT 24 Apr 28 02:16:36 PM PDT 24 337704621 ps
T408 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.1891475817 Apr 28 02:16:20 PM PDT 24 Apr 28 02:16:22 PM PDT 24 570076173 ps
T65 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.1340314435 Apr 28 02:16:19 PM PDT 24 Apr 28 02:16:21 PM PDT 24 508459029 ps
T409 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.497036596 Apr 28 02:16:38 PM PDT 24 Apr 28 02:16:40 PM PDT 24 447121347 ps
T410 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.419008984 Apr 28 02:16:19 PM PDT 24 Apr 28 02:16:20 PM PDT 24 414482594 ps
T411 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.3407147168 Apr 28 02:16:11 PM PDT 24 Apr 28 02:16:12 PM PDT 24 1069307274 ps
T412 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.2513888277 Apr 28 02:16:21 PM PDT 24 Apr 28 02:16:24 PM PDT 24 2364952241 ps
T413 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.818927562 Apr 28 02:16:29 PM PDT 24 Apr 28 02:16:31 PM PDT 24 316297552 ps
T414 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.1060519154 Apr 28 02:16:02 PM PDT 24 Apr 28 02:16:03 PM PDT 24 604502327 ps
T415 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.701325527 Apr 28 02:16:10 PM PDT 24 Apr 28 02:16:12 PM PDT 24 441677292 ps
T416 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.2620495195 Apr 28 02:16:30 PM PDT 24 Apr 28 02:16:32 PM PDT 24 400140100 ps

Test location /workspace/coverage/default/46.aon_timer_stress_all.3714732656
Short name T4
Test name
Test status
Simulation time 105214895622 ps
CPU time 44.42 seconds
Started Apr 28 02:16:10 PM PDT 24
Finished Apr 28 02:16:55 PM PDT 24
Peak memory 183592 kb
Host smart-1a283ec5-2572-4f85-bf70-f852695cbcdd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714732656 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_
all.3714732656
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.4188640992
Short name T14
Test name
Test status
Simulation time 143766453082 ps
CPU time 335.45 seconds
Started Apr 28 02:15:42 PM PDT 24
Finished Apr 28 02:21:20 PM PDT 24
Peak memory 198464 kb
Host smart-03bc82fc-d263-4fb9-a2ec-5a0680f61533
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188640992 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.4188640992
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.2440005490
Short name T33
Test name
Test status
Simulation time 8072483496 ps
CPU time 2.72 seconds
Started Apr 28 02:16:27 PM PDT 24
Finished Apr 28 02:16:30 PM PDT 24
Peak memory 197692 kb
Host smart-282cca32-cc8f-4ef5-b0f3-d90640e65c90
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440005490 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_t
l_intg_err.2440005490
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.4158138477
Short name T43
Test name
Test status
Simulation time 433324987521 ps
CPU time 1005.04 seconds
Started Apr 28 02:15:41 PM PDT 24
Finished Apr 28 02:32:28 PM PDT 24
Peak memory 203860 kb
Host smart-9f0a13c5-6b63-4311-b98a-09f688b5654e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158138477 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.4158138477
Directory /workspace/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.95014885
Short name T20
Test name
Test status
Simulation time 7212604639 ps
CPU time 11.11 seconds
Started Apr 28 02:15:42 PM PDT 24
Finished Apr 28 02:15:55 PM PDT 24
Peak memory 215288 kb
Host smart-4fd268b3-cfcd-4ac8-bff8-d10724e49f07
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95014885 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.95014885
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.3375952109
Short name T40
Test name
Test status
Simulation time 138404272758 ps
CPU time 270.43 seconds
Started Apr 28 02:15:52 PM PDT 24
Finished Apr 28 02:20:25 PM PDT 24
Peak memory 198484 kb
Host smart-bb2de719-81e2-4419-8587-69b2642afde1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375952109 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_reset.3375952109
Directory /workspace/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.512447666
Short name T61
Test name
Test status
Simulation time 503545893 ps
CPU time 0.92 seconds
Started Apr 28 02:16:14 PM PDT 24
Finished Apr 28 02:16:16 PM PDT 24
Peak memory 193872 kb
Host smart-ab1d2c88-3e75-4b63-8ac6-341640c553a0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512447666 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_al
iasing.512447666
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.365392260
Short name T79
Test name
Test status
Simulation time 2055125823 ps
CPU time 5.8 seconds
Started Apr 28 02:16:14 PM PDT 24
Finished Apr 28 02:16:20 PM PDT 24
Peak memory 183736 kb
Host smart-1b44ffc5-edc1-4a06-85a4-e0c3a44f1491
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365392260 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_
timer_same_csr_outstanding.365392260
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.4035831659
Short name T318
Test name
Test status
Simulation time 8079549475 ps
CPU time 4.45 seconds
Started Apr 28 02:16:09 PM PDT 24
Finished Apr 28 02:16:14 PM PDT 24
Peak memory 198028 kb
Host smart-08138665-bba8-4d81-a23b-1f80032fe368
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035831659 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl
_intg_err.4035831659
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.3344541790
Short name T2
Test name
Test status
Simulation time 469345786 ps
CPU time 0.91 seconds
Started Apr 28 02:15:32 PM PDT 24
Finished Apr 28 02:15:34 PM PDT 24
Peak memory 183576 kb
Host smart-75266098-2cd9-4a0e-a705-bed32250bbd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344541790 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.3344541790
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.3278937146
Short name T92
Test name
Test status
Simulation time 254898345273 ps
CPU time 183.95 seconds
Started Apr 28 02:15:43 PM PDT 24
Finished Apr 28 02:18:50 PM PDT 24
Peak memory 191672 kb
Host smart-25bf3a4c-fe28-4a27-bca6-825f57a0f0d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278937146 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_
all.3278937146
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.3803270922
Short name T406
Test name
Test status
Simulation time 543836092 ps
CPU time 1.84 seconds
Started Apr 28 02:16:19 PM PDT 24
Finished Apr 28 02:16:21 PM PDT 24
Peak memory 183712 kb
Host smart-2e11bb8a-1046-43ed-af1c-911122c13cdc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803270922 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_a
liasing.3803270922
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.1020238612
Short name T305
Test name
Test status
Simulation time 7121608730 ps
CPU time 6.67 seconds
Started Apr 28 02:16:08 PM PDT 24
Finished Apr 28 02:16:15 PM PDT 24
Peak memory 192140 kb
Host smart-68b3d321-1f37-4f13-b87c-4e6d0967499a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020238612 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_b
it_bash.1020238612
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.1460021862
Short name T398
Test name
Test status
Simulation time 1212295274 ps
CPU time 0.84 seconds
Started Apr 28 02:16:18 PM PDT 24
Finished Apr 28 02:16:19 PM PDT 24
Peak memory 183684 kb
Host smart-aa71a69a-e45a-4ca0-b4de-e5325c7740eb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460021862 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_h
w_reset.1460021862
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.1773484499
Short name T378
Test name
Test status
Simulation time 442487364 ps
CPU time 1.3 seconds
Started Apr 28 02:16:17 PM PDT 24
Finished Apr 28 02:16:19 PM PDT 24
Peak memory 196028 kb
Host smart-991ea9a6-a29c-486f-899d-a33ba0ac8189
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773484499 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.1773484499
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.2373490227
Short name T314
Test name
Test status
Simulation time 432364108 ps
CPU time 1.15 seconds
Started Apr 28 02:16:19 PM PDT 24
Finished Apr 28 02:16:21 PM PDT 24
Peak memory 183616 kb
Host smart-4b55501a-7bb5-4d67-8509-7ec5614f86a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373490227 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.2373490227
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.353661053
Short name T385
Test name
Test status
Simulation time 352292179 ps
CPU time 0.65 seconds
Started Apr 28 02:16:28 PM PDT 24
Finished Apr 28 02:16:29 PM PDT 24
Peak memory 183540 kb
Host smart-b973f429-4c75-4d2e-bcc4-b825082a0ec6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353661053 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.353661053
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.3931496175
Short name T404
Test name
Test status
Simulation time 487100639 ps
CPU time 0.59 seconds
Started Apr 28 02:16:19 PM PDT 24
Finished Apr 28 02:16:20 PM PDT 24
Peak memory 183516 kb
Host smart-c3f5a134-bbdc-4035-9b7a-a7347c1d9810
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931496175 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_t
imer_mem_partial_access.3931496175
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.3926446447
Short name T392
Test name
Test status
Simulation time 395043582 ps
CPU time 0.57 seconds
Started Apr 28 02:16:15 PM PDT 24
Finished Apr 28 02:16:17 PM PDT 24
Peak memory 183564 kb
Host smart-edf5dc88-0070-46ef-814a-2bd15a3e6a36
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926446447 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_w
alk.3926446447
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.507521617
Short name T285
Test name
Test status
Simulation time 739005998 ps
CPU time 1.89 seconds
Started Apr 28 02:16:13 PM PDT 24
Finished Apr 28 02:16:15 PM PDT 24
Peak memory 198488 kb
Host smart-dbf07f78-0c84-42ab-83e3-94e5d2e3597d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507521617 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.507521617
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.3913012535
Short name T397
Test name
Test status
Simulation time 13939424566 ps
CPU time 24.29 seconds
Started Apr 28 02:16:21 PM PDT 24
Finished Apr 28 02:16:46 PM PDT 24
Peak memory 195644 kb
Host smart-4d686510-7577-4465-98b1-24ff81120524
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913012535 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_b
it_bash.3913012535
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.3344872558
Short name T59
Test name
Test status
Simulation time 660434270 ps
CPU time 1.5 seconds
Started Apr 28 02:16:09 PM PDT 24
Finished Apr 28 02:16:11 PM PDT 24
Peak memory 183672 kb
Host smart-d328c330-26b5-44cd-959a-e25dabaccf7e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344872558 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_h
w_reset.3344872558
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.1037861474
Short name T381
Test name
Test status
Simulation time 542024527 ps
CPU time 1.34 seconds
Started Apr 28 02:16:15 PM PDT 24
Finished Apr 28 02:16:17 PM PDT 24
Peak memory 195000 kb
Host smart-56e1e6a5-179c-4447-9698-161982b34159
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037861474 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.1037861474
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.1340314435
Short name T65
Test name
Test status
Simulation time 508459029 ps
CPU time 0.99 seconds
Started Apr 28 02:16:19 PM PDT 24
Finished Apr 28 02:16:21 PM PDT 24
Peak memory 183648 kb
Host smart-90f90427-a02a-41c3-9db5-b7f4986215c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340314435 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.1340314435
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.1060519154
Short name T414
Test name
Test status
Simulation time 604502327 ps
CPU time 0.58 seconds
Started Apr 28 02:16:02 PM PDT 24
Finished Apr 28 02:16:03 PM PDT 24
Peak memory 183572 kb
Host smart-b33c5527-73da-44b2-8371-729234620d9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060519154 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.1060519154
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.2915046221
Short name T330
Test name
Test status
Simulation time 349329774 ps
CPU time 0.64 seconds
Started Apr 28 02:16:09 PM PDT 24
Finished Apr 28 02:16:10 PM PDT 24
Peak memory 183548 kb
Host smart-715e4b82-9aa4-4daf-a1fd-f9c80131b80e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915046221 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_t
imer_mem_partial_access.2915046221
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.1992574280
Short name T274
Test name
Test status
Simulation time 502973045 ps
CPU time 1.26 seconds
Started Apr 28 02:16:12 PM PDT 24
Finished Apr 28 02:16:13 PM PDT 24
Peak memory 183544 kb
Host smart-42797d03-c420-456e-9226-17231696b74f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992574280 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_w
alk.1992574280
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.1563421421
Short name T80
Test name
Test status
Simulation time 832371126 ps
CPU time 2.02 seconds
Started Apr 28 02:16:14 PM PDT 24
Finished Apr 28 02:16:16 PM PDT 24
Peak memory 193148 kb
Host smart-552f3668-0f0d-465f-9700-2bb5a5554c21
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563421421 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon
_timer_same_csr_outstanding.1563421421
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.1331695155
Short name T325
Test name
Test status
Simulation time 624485646 ps
CPU time 1.3 seconds
Started Apr 28 02:16:12 PM PDT 24
Finished Apr 28 02:16:14 PM PDT 24
Peak memory 198368 kb
Host smart-c899cb1e-8f3a-4476-ae95-4df664bd948f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331695155 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.1331695155
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.3533473596
Short name T349
Test name
Test status
Simulation time 4229811806 ps
CPU time 1.81 seconds
Started Apr 28 02:16:09 PM PDT 24
Finished Apr 28 02:16:11 PM PDT 24
Peak memory 197360 kb
Host smart-2e1a23f5-e42d-456a-b426-ec082cdcd0ef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533473596 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl
_intg_err.3533473596
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.485757519
Short name T362
Test name
Test status
Simulation time 356635825 ps
CPU time 1.16 seconds
Started Apr 28 02:16:28 PM PDT 24
Finished Apr 28 02:16:30 PM PDT 24
Peak memory 195528 kb
Host smart-c4b54e02-a94b-41b0-a793-5aecbcd07042
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485757519 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.485757519
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.496271350
Short name T380
Test name
Test status
Simulation time 357066646 ps
CPU time 1.1 seconds
Started Apr 28 02:16:24 PM PDT 24
Finished Apr 28 02:16:26 PM PDT 24
Peak memory 183660 kb
Host smart-d566bf94-4a9b-42dd-b4ce-c4d04f99de83
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496271350 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.496271350
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.818927562
Short name T413
Test name
Test status
Simulation time 316297552 ps
CPU time 1.01 seconds
Started Apr 28 02:16:29 PM PDT 24
Finished Apr 28 02:16:31 PM PDT 24
Peak memory 183568 kb
Host smart-a61cfa1b-f9e8-47dd-91f0-bc6f6ecde5b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818927562 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.818927562
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.3396211789
Short name T76
Test name
Test status
Simulation time 1384763116 ps
CPU time 2.03 seconds
Started Apr 28 02:16:28 PM PDT 24
Finished Apr 28 02:16:31 PM PDT 24
Peak memory 193172 kb
Host smart-f669f4fc-5dfb-497a-aeee-200da164768a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396211789 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.ao
n_timer_same_csr_outstanding.3396211789
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.4042498451
Short name T333
Test name
Test status
Simulation time 360134561 ps
CPU time 1.41 seconds
Started Apr 28 02:16:27 PM PDT 24
Finished Apr 28 02:16:29 PM PDT 24
Peak memory 198496 kb
Host smart-2772e67a-d271-4be8-8ea0-6c015dfae313
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042498451 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.4042498451
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.3071448930
Short name T405
Test name
Test status
Simulation time 580912741 ps
CPU time 1.14 seconds
Started Apr 28 02:16:25 PM PDT 24
Finished Apr 28 02:16:27 PM PDT 24
Peak memory 195844 kb
Host smart-b9c18a34-6ba5-4e0c-8266-11788bb26836
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071448930 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.3071448930
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.3686928562
Short name T58
Test name
Test status
Simulation time 391938051 ps
CPU time 0.84 seconds
Started Apr 28 02:16:23 PM PDT 24
Finished Apr 28 02:16:25 PM PDT 24
Peak memory 192836 kb
Host smart-9ffa74bf-b15b-401e-bc88-a1bbd457d260
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686928562 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.3686928562
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.1960563709
Short name T289
Test name
Test status
Simulation time 473133572 ps
CPU time 0.76 seconds
Started Apr 28 02:16:28 PM PDT 24
Finished Apr 28 02:16:29 PM PDT 24
Peak memory 183572 kb
Host smart-54c04d6e-a5bd-4bf7-a91f-d3df8896366b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960563709 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.1960563709
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.1343796501
Short name T358
Test name
Test status
Simulation time 3431355435 ps
CPU time 9.01 seconds
Started Apr 28 02:16:21 PM PDT 24
Finished Apr 28 02:16:30 PM PDT 24
Peak memory 194784 kb
Host smart-8c88e579-dc6b-4286-a466-3a8129e5967e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343796501 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.ao
n_timer_same_csr_outstanding.1343796501
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.2844117899
Short name T354
Test name
Test status
Simulation time 570437560 ps
CPU time 2.3 seconds
Started Apr 28 02:16:26 PM PDT 24
Finished Apr 28 02:16:29 PM PDT 24
Peak memory 198488 kb
Host smart-6019c180-3a3c-4185-9d04-c3ffded59483
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844117899 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.2844117899
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.1550051127
Short name T293
Test name
Test status
Simulation time 7781370045 ps
CPU time 3.28 seconds
Started Apr 28 02:16:24 PM PDT 24
Finished Apr 28 02:16:28 PM PDT 24
Peak memory 197968 kb
Host smart-095264aa-4955-468c-a465-7987d20322ac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550051127 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_t
l_intg_err.1550051127
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.4090835162
Short name T324
Test name
Test status
Simulation time 501473731 ps
CPU time 1.36 seconds
Started Apr 28 02:16:36 PM PDT 24
Finished Apr 28 02:16:38 PM PDT 24
Peak memory 195716 kb
Host smart-14386f74-e649-41d8-bf7d-c14388d1f7b2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090835162 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.4090835162
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.2461177980
Short name T57
Test name
Test status
Simulation time 473925496 ps
CPU time 0.99 seconds
Started Apr 28 02:16:24 PM PDT 24
Finished Apr 28 02:16:25 PM PDT 24
Peak memory 193048 kb
Host smart-e4a15844-99df-46f3-9016-c76631eba80f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461177980 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.2461177980
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.705093875
Short name T357
Test name
Test status
Simulation time 286179432 ps
CPU time 0.97 seconds
Started Apr 28 02:16:32 PM PDT 24
Finished Apr 28 02:16:33 PM PDT 24
Peak memory 183416 kb
Host smart-31d7a872-6982-4179-9504-99f01eb833ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705093875 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.705093875
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.1795047821
Short name T389
Test name
Test status
Simulation time 2692898646 ps
CPU time 3.16 seconds
Started Apr 28 02:16:20 PM PDT 24
Finished Apr 28 02:16:24 PM PDT 24
Peak memory 194712 kb
Host smart-e69b3df8-2349-4169-86c1-d76254a34c01
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795047821 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.ao
n_timer_same_csr_outstanding.1795047821
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.3550870371
Short name T375
Test name
Test status
Simulation time 333405185 ps
CPU time 2.43 seconds
Started Apr 28 02:16:30 PM PDT 24
Finished Apr 28 02:16:33 PM PDT 24
Peak memory 198448 kb
Host smart-39aa05ef-e536-4f49-b598-5444abde13c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550870371 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.3550870371
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.2067031793
Short name T37
Test name
Test status
Simulation time 8957763490 ps
CPU time 15.26 seconds
Started Apr 28 02:16:29 PM PDT 24
Finished Apr 28 02:16:45 PM PDT 24
Peak memory 197972 kb
Host smart-d9281886-fe46-47c6-b879-d7ef5f8c7dd3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067031793 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_t
l_intg_err.2067031793
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.1833407028
Short name T35
Test name
Test status
Simulation time 692533343 ps
CPU time 0.91 seconds
Started Apr 28 02:16:37 PM PDT 24
Finished Apr 28 02:16:39 PM PDT 24
Peak memory 198284 kb
Host smart-c8286f4d-d0d4-4b0e-ac79-eed7f4846e95
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833407028 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.1833407028
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.3051554074
Short name T75
Test name
Test status
Simulation time 439215008 ps
CPU time 1.15 seconds
Started Apr 28 02:16:32 PM PDT 24
Finished Apr 28 02:16:34 PM PDT 24
Peak memory 183664 kb
Host smart-905c0212-9174-477d-a7a0-678a03e2677a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051554074 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.3051554074
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.1996061072
Short name T347
Test name
Test status
Simulation time 323056522 ps
CPU time 1.02 seconds
Started Apr 28 02:16:25 PM PDT 24
Finished Apr 28 02:16:27 PM PDT 24
Peak memory 183508 kb
Host smart-cf2eb02f-1ae7-4fdf-ae88-9e44cc18d629
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996061072 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.1996061072
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.3558248582
Short name T323
Test name
Test status
Simulation time 1770099774 ps
CPU time 1.98 seconds
Started Apr 28 02:16:32 PM PDT 24
Finished Apr 28 02:16:35 PM PDT 24
Peak memory 194336 kb
Host smart-c93303db-f940-42b4-b5bf-a8c2830742fd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558248582 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.ao
n_timer_same_csr_outstanding.3558248582
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.2769925454
Short name T348
Test name
Test status
Simulation time 528923775 ps
CPU time 1.92 seconds
Started Apr 28 02:16:24 PM PDT 24
Finished Apr 28 02:16:26 PM PDT 24
Peak memory 198484 kb
Host smart-cca68aff-f4c3-43f4-b974-875ac56df627
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769925454 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.2769925454
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.1108712129
Short name T320
Test name
Test status
Simulation time 9453870987 ps
CPU time 4.5 seconds
Started Apr 28 02:16:22 PM PDT 24
Finished Apr 28 02:16:28 PM PDT 24
Peak memory 198024 kb
Host smart-ae45a61c-80aa-4acb-921e-c715124401cd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108712129 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_t
l_intg_err.1108712129
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.833018098
Short name T388
Test name
Test status
Simulation time 451173243 ps
CPU time 1.43 seconds
Started Apr 28 02:16:44 PM PDT 24
Finished Apr 28 02:16:46 PM PDT 24
Peak memory 195732 kb
Host smart-961a0dc5-aa74-4107-adbb-e9acfd445040
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833018098 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.833018098
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.556451453
Short name T77
Test name
Test status
Simulation time 450277092 ps
CPU time 0.8 seconds
Started Apr 28 02:16:33 PM PDT 24
Finished Apr 28 02:16:34 PM PDT 24
Peak memory 192936 kb
Host smart-f451ffe3-c9a8-471c-b688-d4a7359ab835
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556451453 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.556451453
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.1345432934
Short name T359
Test name
Test status
Simulation time 364478185 ps
CPU time 0.72 seconds
Started Apr 28 02:16:35 PM PDT 24
Finished Apr 28 02:16:37 PM PDT 24
Peak memory 183420 kb
Host smart-e3c0bdff-fc09-4cbe-8240-03fecfb6dd45
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345432934 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.1345432934
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.2838162659
Short name T308
Test name
Test status
Simulation time 1474635065 ps
CPU time 2.35 seconds
Started Apr 28 02:16:25 PM PDT 24
Finished Apr 28 02:16:28 PM PDT 24
Peak memory 192812 kb
Host smart-88191c39-6b8d-4689-a802-dbdf9903f477
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838162659 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao
n_timer_same_csr_outstanding.2838162659
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.2354039845
Short name T372
Test name
Test status
Simulation time 867175072 ps
CPU time 1.26 seconds
Started Apr 28 02:16:38 PM PDT 24
Finished Apr 28 02:16:40 PM PDT 24
Peak memory 198444 kb
Host smart-082e7fb1-6135-4609-a4bd-f91d19079e0a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354039845 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.2354039845
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.4001923448
Short name T98
Test name
Test status
Simulation time 4383573072 ps
CPU time 3.87 seconds
Started Apr 28 02:16:24 PM PDT 24
Finished Apr 28 02:16:29 PM PDT 24
Peak memory 197288 kb
Host smart-a9b5a3a4-579b-4ff6-8f6f-455b4609cc04
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001923448 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_t
l_intg_err.4001923448
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.2517042073
Short name T346
Test name
Test status
Simulation time 359486993 ps
CPU time 0.9 seconds
Started Apr 28 02:16:25 PM PDT 24
Finished Apr 28 02:16:27 PM PDT 24
Peak memory 194584 kb
Host smart-24805cf6-c21b-4f91-aee1-62cebe588186
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517042073 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.2517042073
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.2613063172
Short name T60
Test name
Test status
Simulation time 537736617 ps
CPU time 0.93 seconds
Started Apr 28 02:16:28 PM PDT 24
Finished Apr 28 02:16:30 PM PDT 24
Peak memory 192960 kb
Host smart-c6f55a1a-38e3-4e8e-b95a-ce0249071331
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613063172 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.2613063172
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.290837596
Short name T282
Test name
Test status
Simulation time 353837533 ps
CPU time 0.93 seconds
Started Apr 28 02:16:33 PM PDT 24
Finished Apr 28 02:16:34 PM PDT 24
Peak memory 183512 kb
Host smart-0d5965e9-36a9-481f-b83a-896e9b1ad87f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290837596 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.290837596
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.1454907372
Short name T34
Test name
Test status
Simulation time 2374229775 ps
CPU time 4.11 seconds
Started Apr 28 02:16:27 PM PDT 24
Finished Apr 28 02:16:31 PM PDT 24
Peak memory 194280 kb
Host smart-0332e1b8-3766-4a2e-a309-be8315749806
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454907372 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.ao
n_timer_same_csr_outstanding.1454907372
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.2041589358
Short name T300
Test name
Test status
Simulation time 440467227 ps
CPU time 1.71 seconds
Started Apr 28 02:16:24 PM PDT 24
Finished Apr 28 02:16:27 PM PDT 24
Peak memory 198284 kb
Host smart-e59a9669-cf85-49bb-ae7d-2863f52e1d23
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041589358 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.2041589358
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.3043950149
Short name T341
Test name
Test status
Simulation time 8280493315 ps
CPU time 4.41 seconds
Started Apr 28 02:16:28 PM PDT 24
Finished Apr 28 02:16:33 PM PDT 24
Peak memory 197824 kb
Host smart-8d9a42bb-5ffe-4cd0-87a8-eaf149892f9b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043950149 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_t
l_intg_err.3043950149
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.403249973
Short name T364
Test name
Test status
Simulation time 384083108 ps
CPU time 1.09 seconds
Started Apr 28 02:16:25 PM PDT 24
Finished Apr 28 02:16:26 PM PDT 24
Peak memory 195792 kb
Host smart-52ce8b70-4b2e-4512-9efc-ec37ed16ba33
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403249973 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.403249973
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.1848432734
Short name T54
Test name
Test status
Simulation time 318791390 ps
CPU time 1.03 seconds
Started Apr 28 02:16:33 PM PDT 24
Finished Apr 28 02:16:34 PM PDT 24
Peak memory 183772 kb
Host smart-7db56faa-6312-4a6f-a2e1-78fb0d248432
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848432734 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.1848432734
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.1108442836
Short name T294
Test name
Test status
Simulation time 515648746 ps
CPU time 1.38 seconds
Started Apr 28 02:16:33 PM PDT 24
Finished Apr 28 02:16:35 PM PDT 24
Peak memory 183560 kb
Host smart-096ea367-30b1-4c8a-a53c-4f05a415ddf0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108442836 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.1108442836
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.2661196654
Short name T342
Test name
Test status
Simulation time 2718338026 ps
CPU time 0.95 seconds
Started Apr 28 02:16:35 PM PDT 24
Finished Apr 28 02:16:37 PM PDT 24
Peak memory 183772 kb
Host smart-2e6de82a-18c5-410f-a9bd-20346ccee0de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661196654 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.ao
n_timer_same_csr_outstanding.2661196654
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.564212898
Short name T322
Test name
Test status
Simulation time 574775634 ps
CPU time 1.55 seconds
Started Apr 28 02:16:35 PM PDT 24
Finished Apr 28 02:16:38 PM PDT 24
Peak memory 198480 kb
Host smart-550c6f41-74b3-4082-8cde-37d31c52d4da
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564212898 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.564212898
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.215449429
Short name T399
Test name
Test status
Simulation time 4592698605 ps
CPU time 4.18 seconds
Started Apr 28 02:16:27 PM PDT 24
Finished Apr 28 02:16:31 PM PDT 24
Peak memory 197268 kb
Host smart-949ff046-b3eb-4854-a2bf-dca8493c4e26
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215449429 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl
_intg_err.215449429
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.744556782
Short name T100
Test name
Test status
Simulation time 421810740 ps
CPU time 0.8 seconds
Started Apr 28 02:16:36 PM PDT 24
Finished Apr 28 02:16:38 PM PDT 24
Peak memory 195496 kb
Host smart-7067d568-c23f-483f-8410-c5735642fcab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744556782 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.744556782
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.2916638495
Short name T339
Test name
Test status
Simulation time 473871186 ps
CPU time 0.92 seconds
Started Apr 28 02:16:32 PM PDT 24
Finished Apr 28 02:16:33 PM PDT 24
Peak memory 183652 kb
Host smart-22332c0f-243a-4940-895b-9a7e95466656
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916638495 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.2916638495
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.2483028651
Short name T335
Test name
Test status
Simulation time 334078380 ps
CPU time 1.01 seconds
Started Apr 28 02:16:33 PM PDT 24
Finished Apr 28 02:16:34 PM PDT 24
Peak memory 183500 kb
Host smart-869c9825-4cca-4f5e-ba95-06b9011ddbc8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483028651 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.2483028651
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.1275573280
Short name T395
Test name
Test status
Simulation time 2091621821 ps
CPU time 3.8 seconds
Started Apr 28 02:16:33 PM PDT 24
Finished Apr 28 02:16:37 PM PDT 24
Peak memory 194256 kb
Host smart-3a8500da-1001-44da-9e14-716900305d22
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275573280 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.ao
n_timer_same_csr_outstanding.1275573280
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.2100944825
Short name T296
Test name
Test status
Simulation time 425054530 ps
CPU time 2.42 seconds
Started Apr 28 02:16:27 PM PDT 24
Finished Apr 28 02:16:31 PM PDT 24
Peak memory 198432 kb
Host smart-afb3699a-911d-4beb-8ea4-464d8cd940d0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100944825 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.2100944825
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.1222048454
Short name T99
Test name
Test status
Simulation time 8141139248 ps
CPU time 14.7 seconds
Started Apr 28 02:16:31 PM PDT 24
Finished Apr 28 02:16:46 PM PDT 24
Peak memory 197972 kb
Host smart-bfef4f72-0a0c-4151-b350-fa3979384b0f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222048454 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_t
l_intg_err.1222048454
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.4021845529
Short name T356
Test name
Test status
Simulation time 708340288 ps
CPU time 0.92 seconds
Started Apr 28 02:16:26 PM PDT 24
Finished Apr 28 02:16:28 PM PDT 24
Peak memory 197196 kb
Host smart-b1127e25-5c68-415b-8843-519ac4fea775
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021845529 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.4021845529
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.1428020829
Short name T55
Test name
Test status
Simulation time 490946389 ps
CPU time 0.97 seconds
Started Apr 28 02:16:34 PM PDT 24
Finished Apr 28 02:16:37 PM PDT 24
Peak memory 193032 kb
Host smart-284e71bd-a157-4034-a37e-d53037195338
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428020829 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.1428020829
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.634829417
Short name T351
Test name
Test status
Simulation time 295391034 ps
CPU time 0.91 seconds
Started Apr 28 02:16:38 PM PDT 24
Finished Apr 28 02:16:40 PM PDT 24
Peak memory 183424 kb
Host smart-c60222f5-af37-4545-8f9d-bf5b4012d21f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634829417 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.634829417
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.3548896482
Short name T368
Test name
Test status
Simulation time 1357616121 ps
CPU time 1.54 seconds
Started Apr 28 02:16:27 PM PDT 24
Finished Apr 28 02:16:30 PM PDT 24
Peak memory 183596 kb
Host smart-ca953304-d39b-40e2-9801-f72ba23abc0b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548896482 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.ao
n_timer_same_csr_outstanding.3548896482
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.1578746237
Short name T336
Test name
Test status
Simulation time 573976143 ps
CPU time 1.15 seconds
Started Apr 28 02:16:28 PM PDT 24
Finished Apr 28 02:16:30 PM PDT 24
Peak memory 198376 kb
Host smart-83b51698-d44c-4036-ace2-f4860ba4493a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578746237 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.1578746237
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.486501339
Short name T97
Test name
Test status
Simulation time 8474725916 ps
CPU time 4.18 seconds
Started Apr 28 02:16:31 PM PDT 24
Finished Apr 28 02:16:36 PM PDT 24
Peak memory 197632 kb
Host smart-792f02ff-d02d-43e2-831b-8295d35ab0b7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486501339 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl
_intg_err.486501339
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.3008675044
Short name T309
Test name
Test status
Simulation time 382787429 ps
CPU time 0.88 seconds
Started Apr 28 02:16:40 PM PDT 24
Finished Apr 28 02:16:42 PM PDT 24
Peak memory 197064 kb
Host smart-bbbf3949-6cb1-4ed5-b066-c51028add8f1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008675044 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.3008675044
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.2302448672
Short name T83
Test name
Test status
Simulation time 440215481 ps
CPU time 1.23 seconds
Started Apr 28 02:16:34 PM PDT 24
Finished Apr 28 02:16:36 PM PDT 24
Peak memory 192944 kb
Host smart-965774e3-98c3-437e-b31f-f2f9a6a1ee7d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302448672 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.2302448672
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.3352505823
Short name T279
Test name
Test status
Simulation time 499482153 ps
CPU time 1.29 seconds
Started Apr 28 02:16:34 PM PDT 24
Finished Apr 28 02:16:37 PM PDT 24
Peak memory 183572 kb
Host smart-94235e74-00cc-4057-9797-da13cf5d3c06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352505823 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.3352505823
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.2132494348
Short name T367
Test name
Test status
Simulation time 1243790406 ps
CPU time 2.06 seconds
Started Apr 28 02:16:28 PM PDT 24
Finished Apr 28 02:16:31 PM PDT 24
Peak memory 183660 kb
Host smart-c57b0072-10a5-417e-bbba-a5a52563fa3c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132494348 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao
n_timer_same_csr_outstanding.2132494348
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.2453709371
Short name T338
Test name
Test status
Simulation time 623953527 ps
CPU time 1.9 seconds
Started Apr 28 02:16:28 PM PDT 24
Finished Apr 28 02:16:31 PM PDT 24
Peak memory 198444 kb
Host smart-b7a52a76-86c0-4bd0-9cda-dd2be389babd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453709371 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.2453709371
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.438164373
Short name T36
Test name
Test status
Simulation time 4497642311 ps
CPU time 2.59 seconds
Started Apr 28 02:16:29 PM PDT 24
Finished Apr 28 02:16:32 PM PDT 24
Peak memory 197144 kb
Host smart-15aac2e7-bcaa-4a21-8936-b880f642382e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438164373 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl
_intg_err.438164373
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.3664165578
Short name T379
Test name
Test status
Simulation time 648233596 ps
CPU time 1.09 seconds
Started Apr 28 02:16:21 PM PDT 24
Finished Apr 28 02:16:23 PM PDT 24
Peak memory 194224 kb
Host smart-329b58e2-ccc5-4219-b953-38f74b2f6c26
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664165578 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_a
liasing.3664165578
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.3374081374
Short name T64
Test name
Test status
Simulation time 7107631372 ps
CPU time 10.67 seconds
Started Apr 28 02:16:14 PM PDT 24
Finished Apr 28 02:16:26 PM PDT 24
Peak memory 192176 kb
Host smart-a29e61f3-09d7-4624-93de-e9909de0843d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374081374 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_b
it_bash.3374081374
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.3407147168
Short name T411
Test name
Test status
Simulation time 1069307274 ps
CPU time 0.9 seconds
Started Apr 28 02:16:11 PM PDT 24
Finished Apr 28 02:16:12 PM PDT 24
Peak memory 183776 kb
Host smart-b202cd19-a715-4058-85ca-31483bbb2b4e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407147168 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_h
w_reset.3407147168
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.2568469732
Short name T316
Test name
Test status
Simulation time 626533431 ps
CPU time 0.75 seconds
Started Apr 28 02:16:09 PM PDT 24
Finished Apr 28 02:16:10 PM PDT 24
Peak memory 195564 kb
Host smart-36eeaf2e-7567-4ef5-92c9-96e1b1ae468d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568469732 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.2568469732
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.744743751
Short name T350
Test name
Test status
Simulation time 391222058 ps
CPU time 0.91 seconds
Started Apr 28 02:16:35 PM PDT 24
Finished Apr 28 02:16:37 PM PDT 24
Peak memory 183940 kb
Host smart-e401707a-fd56-4022-84c5-11cb6205d94a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744743751 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.744743751
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.1417960364
Short name T394
Test name
Test status
Simulation time 511711136 ps
CPU time 0.68 seconds
Started Apr 28 02:16:13 PM PDT 24
Finished Apr 28 02:16:15 PM PDT 24
Peak memory 183588 kb
Host smart-4875f527-d0c5-40db-bf9f-36167dbe61ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417960364 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.1417960364
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.1088369871
Short name T337
Test name
Test status
Simulation time 335581716 ps
CPU time 0.76 seconds
Started Apr 28 02:16:09 PM PDT 24
Finished Apr 28 02:16:10 PM PDT 24
Peak memory 183512 kb
Host smart-408d09e8-0230-4dcf-93cb-8461dc9ac75b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088369871 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_t
imer_mem_partial_access.1088369871
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.382990469
Short name T292
Test name
Test status
Simulation time 501934677 ps
CPU time 0.92 seconds
Started Apr 28 02:16:12 PM PDT 24
Finished Apr 28 02:16:14 PM PDT 24
Peak memory 183576 kb
Host smart-a3a256c1-8e00-42c3-9b8e-5ab3adbd169c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382990469 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_wa
lk.382990469
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.3109310668
Short name T32
Test name
Test status
Simulation time 1145740371 ps
CPU time 1.07 seconds
Started Apr 28 02:16:10 PM PDT 24
Finished Apr 28 02:16:12 PM PDT 24
Peak memory 183732 kb
Host smart-10202988-b5cd-4f1f-a24e-da0db4b076b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109310668 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon
_timer_same_csr_outstanding.3109310668
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.3923945817
Short name T343
Test name
Test status
Simulation time 538390424 ps
CPU time 1.41 seconds
Started Apr 28 02:16:21 PM PDT 24
Finished Apr 28 02:16:23 PM PDT 24
Peak memory 198468 kb
Host smart-028f9060-6c86-4be2-9d15-da06e3cdd872
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923945817 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.3923945817
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.2140626544
Short name T383
Test name
Test status
Simulation time 7736618591 ps
CPU time 6.36 seconds
Started Apr 28 02:16:17 PM PDT 24
Finished Apr 28 02:16:24 PM PDT 24
Peak memory 197876 kb
Host smart-a11365ce-90fd-4310-bfe7-5ac5190fa3ea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140626544 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl
_intg_err.2140626544
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.214838895
Short name T377
Test name
Test status
Simulation time 358005029 ps
CPU time 0.65 seconds
Started Apr 28 02:16:35 PM PDT 24
Finished Apr 28 02:16:37 PM PDT 24
Peak memory 183516 kb
Host smart-a2000fcc-1862-4995-a244-d38e030bf3e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214838895 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.214838895
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.2045606833
Short name T299
Test name
Test status
Simulation time 363306126 ps
CPU time 1 seconds
Started Apr 28 02:16:34 PM PDT 24
Finished Apr 28 02:16:36 PM PDT 24
Peak memory 183488 kb
Host smart-64db58d3-c43d-41a4-8667-d4c9c52503c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045606833 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.2045606833
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.2789113475
Short name T307
Test name
Test status
Simulation time 447882619 ps
CPU time 1.19 seconds
Started Apr 28 02:16:31 PM PDT 24
Finished Apr 28 02:16:33 PM PDT 24
Peak memory 183504 kb
Host smart-be1f4846-4bb5-4d83-9bbd-488a0817e1dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789113475 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.2789113475
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.3152757310
Short name T366
Test name
Test status
Simulation time 531101488 ps
CPU time 0.63 seconds
Started Apr 28 02:16:40 PM PDT 24
Finished Apr 28 02:16:41 PM PDT 24
Peak memory 183568 kb
Host smart-138791c0-10e8-4357-917a-3add6723121e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152757310 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.3152757310
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.3713204024
Short name T393
Test name
Test status
Simulation time 560953182 ps
CPU time 0.62 seconds
Started Apr 28 02:16:35 PM PDT 24
Finished Apr 28 02:16:37 PM PDT 24
Peak memory 183536 kb
Host smart-bbd101d2-32f0-4075-82b9-df9ddfa49062
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713204024 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.3713204024
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.3308566845
Short name T281
Test name
Test status
Simulation time 543837876 ps
CPU time 0.7 seconds
Started Apr 28 02:16:28 PM PDT 24
Finished Apr 28 02:16:29 PM PDT 24
Peak memory 183520 kb
Host smart-3b056908-472c-4451-802e-a73545394515
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308566845 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.3308566845
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.2858024448
Short name T384
Test name
Test status
Simulation time 345320463 ps
CPU time 1.05 seconds
Started Apr 28 02:16:30 PM PDT 24
Finished Apr 28 02:16:32 PM PDT 24
Peak memory 183448 kb
Host smart-f8b75e6d-99f6-404b-ae45-c919b2a92841
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858024448 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.2858024448
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.3726427006
Short name T360
Test name
Test status
Simulation time 560641931 ps
CPU time 0.64 seconds
Started Apr 28 02:16:40 PM PDT 24
Finished Apr 28 02:16:41 PM PDT 24
Peak memory 183572 kb
Host smart-6a92877e-fb52-4180-944d-1742e3c2b6fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726427006 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.3726427006
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.1304769734
Short name T273
Test name
Test status
Simulation time 469665034 ps
CPU time 0.75 seconds
Started Apr 28 02:16:33 PM PDT 24
Finished Apr 28 02:16:35 PM PDT 24
Peak memory 183512 kb
Host smart-ed557455-9a09-4cb4-9d13-5d1a4892aa7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304769734 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.1304769734
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.215568474
Short name T327
Test name
Test status
Simulation time 425640124 ps
CPU time 1.15 seconds
Started Apr 28 02:16:31 PM PDT 24
Finished Apr 28 02:16:33 PM PDT 24
Peak memory 183572 kb
Host smart-36bda672-57b8-4250-a6c1-43ba824d0271
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215568474 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.215568474
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.701325527
Short name T415
Test name
Test status
Simulation time 441677292 ps
CPU time 0.83 seconds
Started Apr 28 02:16:10 PM PDT 24
Finished Apr 28 02:16:12 PM PDT 24
Peak memory 183600 kb
Host smart-8c541102-5a69-4f69-9e07-1a4a0094f12c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701325527 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_al
iasing.701325527
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.1917811191
Short name T287
Test name
Test status
Simulation time 7092223322 ps
CPU time 11.18 seconds
Started Apr 28 02:16:24 PM PDT 24
Finished Apr 28 02:16:36 PM PDT 24
Peak memory 192048 kb
Host smart-e9631704-e664-4ccc-9e99-7ecd7c3fe6cf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917811191 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_b
it_bash.1917811191
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.7483498
Short name T365
Test name
Test status
Simulation time 1068222431 ps
CPU time 1.44 seconds
Started Apr 28 02:16:22 PM PDT 24
Finished Apr 28 02:16:24 PM PDT 24
Peak memory 183648 kb
Host smart-3593e618-83e8-4295-a589-5b1f2956c767
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7483498 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_hw_r
eset.7483498
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.439942071
Short name T297
Test name
Test status
Simulation time 322246147 ps
CPU time 1.09 seconds
Started Apr 28 02:16:13 PM PDT 24
Finished Apr 28 02:16:15 PM PDT 24
Peak memory 195800 kb
Host smart-707d3141-4f56-47c3-a763-cb3bc3cf8f21
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439942071 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.439942071
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.4172947048
Short name T56
Test name
Test status
Simulation time 499448748 ps
CPU time 1.31 seconds
Started Apr 28 02:16:12 PM PDT 24
Finished Apr 28 02:16:13 PM PDT 24
Peak memory 192924 kb
Host smart-16feb9b8-fc04-4e95-afe0-2e7e2f272df4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172947048 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.4172947048
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.3782128554
Short name T390
Test name
Test status
Simulation time 394001371 ps
CPU time 0.66 seconds
Started Apr 28 02:16:14 PM PDT 24
Finished Apr 28 02:16:15 PM PDT 24
Peak memory 183540 kb
Host smart-2ae5f52f-a914-4a51-b179-fc0172744522
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782128554 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.3782128554
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.419008984
Short name T410
Test name
Test status
Simulation time 414482594 ps
CPU time 0.68 seconds
Started Apr 28 02:16:19 PM PDT 24
Finished Apr 28 02:16:20 PM PDT 24
Peak memory 183504 kb
Host smart-1bc724da-b4af-409f-9626-eccbdd672f74
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419008984 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_ti
mer_mem_partial_access.419008984
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.3285960538
Short name T295
Test name
Test status
Simulation time 473971953 ps
CPU time 0.98 seconds
Started Apr 28 02:16:17 PM PDT 24
Finished Apr 28 02:16:19 PM PDT 24
Peak memory 183568 kb
Host smart-f70709ed-cbd2-44f2-ad51-79698ce13f51
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285960538 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_w
alk.3285960538
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.1332096807
Short name T315
Test name
Test status
Simulation time 3075466693 ps
CPU time 1.7 seconds
Started Apr 28 02:16:32 PM PDT 24
Finished Apr 28 02:16:34 PM PDT 24
Peak memory 194644 kb
Host smart-dd65aee2-2b7e-403e-963e-0b560cedd2b8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332096807 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon
_timer_same_csr_outstanding.1332096807
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.3455631082
Short name T280
Test name
Test status
Simulation time 445153758 ps
CPU time 1.59 seconds
Started Apr 28 02:16:23 PM PDT 24
Finished Apr 28 02:16:25 PM PDT 24
Peak memory 198476 kb
Host smart-072f3e37-cd3f-4751-9ffd-958facfb7379
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455631082 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.3455631082
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.947906212
Short name T401
Test name
Test status
Simulation time 8655815309 ps
CPU time 4.81 seconds
Started Apr 28 02:16:22 PM PDT 24
Finished Apr 28 02:16:28 PM PDT 24
Peak memory 197896 kb
Host smart-f3d374dd-658e-4259-a34b-9484d4c78ee5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947906212 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_
intg_err.947906212
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.224864990
Short name T317
Test name
Test status
Simulation time 424752539 ps
CPU time 1.17 seconds
Started Apr 28 02:16:33 PM PDT 24
Finished Apr 28 02:16:35 PM PDT 24
Peak memory 183472 kb
Host smart-031d91a2-c444-46a1-99f0-18f357537b26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224864990 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.224864990
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.2968518825
Short name T353
Test name
Test status
Simulation time 532194835 ps
CPU time 0.75 seconds
Started Apr 28 02:16:47 PM PDT 24
Finished Apr 28 02:16:49 PM PDT 24
Peak memory 183568 kb
Host smart-7203caa7-56e8-4133-92bd-9e017b9c1070
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968518825 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.2968518825
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.1757779447
Short name T319
Test name
Test status
Simulation time 397264050 ps
CPU time 1.08 seconds
Started Apr 28 02:16:32 PM PDT 24
Finished Apr 28 02:16:34 PM PDT 24
Peak memory 183496 kb
Host smart-d472672c-c826-4e33-bcc8-4168cc9ceaec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757779447 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.1757779447
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.2660464156
Short name T331
Test name
Test status
Simulation time 285947786 ps
CPU time 1.15 seconds
Started Apr 28 02:16:29 PM PDT 24
Finished Apr 28 02:16:31 PM PDT 24
Peak memory 183528 kb
Host smart-d5f1ed04-3b32-4c03-af87-a845dbaf9a41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660464156 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.2660464156
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.249919626
Short name T363
Test name
Test status
Simulation time 411136218 ps
CPU time 0.86 seconds
Started Apr 28 02:16:39 PM PDT 24
Finished Apr 28 02:16:41 PM PDT 24
Peak memory 183564 kb
Host smart-c02809c5-85e5-4e22-b067-c69f18975ea1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249919626 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.249919626
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.4014474601
Short name T310
Test name
Test status
Simulation time 446695429 ps
CPU time 0.83 seconds
Started Apr 28 02:16:29 PM PDT 24
Finished Apr 28 02:16:31 PM PDT 24
Peak memory 183540 kb
Host smart-779af88a-a247-496b-946f-4e646de18296
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014474601 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.4014474601
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.1649942626
Short name T328
Test name
Test status
Simulation time 284690424 ps
CPU time 0.98 seconds
Started Apr 28 02:16:39 PM PDT 24
Finished Apr 28 02:16:41 PM PDT 24
Peak memory 183572 kb
Host smart-f983fab2-29f9-43cd-afbd-69c8810ac693
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649942626 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.1649942626
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.3811457064
Short name T276
Test name
Test status
Simulation time 335073158 ps
CPU time 0.73 seconds
Started Apr 28 02:16:36 PM PDT 24
Finished Apr 28 02:16:38 PM PDT 24
Peak memory 183568 kb
Host smart-cbc827c6-5cf1-49e8-881a-8027237dd541
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811457064 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.3811457064
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.497036596
Short name T409
Test name
Test status
Simulation time 447121347 ps
CPU time 0.74 seconds
Started Apr 28 02:16:38 PM PDT 24
Finished Apr 28 02:16:40 PM PDT 24
Peak memory 183588 kb
Host smart-c37cb56c-cc17-4d4e-a4d0-ad60c35c8c71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497036596 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.497036596
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.781252616
Short name T400
Test name
Test status
Simulation time 467465252 ps
CPU time 1.2 seconds
Started Apr 28 02:16:29 PM PDT 24
Finished Apr 28 02:16:31 PM PDT 24
Peak memory 183536 kb
Host smart-71e9ead3-3a5e-4116-a224-7973ac614dc7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781252616 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.781252616
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.115314414
Short name T298
Test name
Test status
Simulation time 650622278 ps
CPU time 1.04 seconds
Started Apr 28 02:16:18 PM PDT 24
Finished Apr 28 02:16:19 PM PDT 24
Peak memory 194248 kb
Host smart-b7dd6eee-99d8-4e50-a456-276e5b7085a8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115314414 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_al
iasing.115314414
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.602241383
Short name T345
Test name
Test status
Simulation time 13988455931 ps
CPU time 20.23 seconds
Started Apr 28 02:16:14 PM PDT 24
Finished Apr 28 02:16:35 PM PDT 24
Peak memory 192028 kb
Host smart-ded87ee8-a25a-4a63-ad6c-46f3ddc2d3d7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602241383 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_bi
t_bash.602241383
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.343226020
Short name T403
Test name
Test status
Simulation time 580796542 ps
CPU time 0.76 seconds
Started Apr 28 02:16:19 PM PDT 24
Finished Apr 28 02:16:21 PM PDT 24
Peak memory 183652 kb
Host smart-abddd421-edd2-4772-8f4f-20a54d514d8f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343226020 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_hw
_reset.343226020
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.2809496299
Short name T304
Test name
Test status
Simulation time 409249363 ps
CPU time 1.24 seconds
Started Apr 28 02:16:15 PM PDT 24
Finished Apr 28 02:16:17 PM PDT 24
Peak memory 195776 kb
Host smart-3a12984d-21ae-406e-8c8c-dc88b1d20765
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809496299 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.2809496299
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.1687357297
Short name T62
Test name
Test status
Simulation time 458850139 ps
CPU time 0.84 seconds
Started Apr 28 02:16:14 PM PDT 24
Finished Apr 28 02:16:16 PM PDT 24
Peak memory 183872 kb
Host smart-66e16d18-3ea9-4bb1-9906-3a49628c300e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687357297 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.1687357297
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.894780702
Short name T396
Test name
Test status
Simulation time 517267286 ps
CPU time 0.61 seconds
Started Apr 28 02:16:15 PM PDT 24
Finished Apr 28 02:16:16 PM PDT 24
Peak memory 183576 kb
Host smart-77ddc0da-11f3-44cb-a4a8-bf517827bc59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894780702 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.894780702
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.1155443606
Short name T311
Test name
Test status
Simulation time 331023483 ps
CPU time 0.65 seconds
Started Apr 28 02:16:16 PM PDT 24
Finished Apr 28 02:16:18 PM PDT 24
Peak memory 183572 kb
Host smart-e3d4c826-8bba-4a2a-bb7e-6199054bad83
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155443606 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_t
imer_mem_partial_access.1155443606
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.672298496
Short name T326
Test name
Test status
Simulation time 359039030 ps
CPU time 1.05 seconds
Started Apr 28 02:16:14 PM PDT 24
Finished Apr 28 02:16:16 PM PDT 24
Peak memory 183536 kb
Host smart-ad8a4fe3-8851-40a7-b5eb-ca97a50f006f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672298496 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_wa
lk.672298496
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.2513888277
Short name T412
Test name
Test status
Simulation time 2364952241 ps
CPU time 3.15 seconds
Started Apr 28 02:16:21 PM PDT 24
Finished Apr 28 02:16:24 PM PDT 24
Peak memory 183888 kb
Host smart-bfdb6dda-d0ea-4f75-80cc-6a5363a94642
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513888277 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon
_timer_same_csr_outstanding.2513888277
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.3044994951
Short name T284
Test name
Test status
Simulation time 716282877 ps
CPU time 1.45 seconds
Started Apr 28 02:16:22 PM PDT 24
Finished Apr 28 02:16:24 PM PDT 24
Peak memory 198372 kb
Host smart-571f295f-a51d-4423-9c20-c92dafdde11e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044994951 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.3044994951
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.117925537
Short name T302
Test name
Test status
Simulation time 4735926599 ps
CPU time 2.5 seconds
Started Apr 28 02:16:13 PM PDT 24
Finished Apr 28 02:16:16 PM PDT 24
Peak memory 196440 kb
Host smart-c3c4da26-1876-4352-8c53-71268f20d1b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117925537 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_
intg_err.117925537
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.947556757
Short name T321
Test name
Test status
Simulation time 375551386 ps
CPU time 0.66 seconds
Started Apr 28 02:16:34 PM PDT 24
Finished Apr 28 02:16:35 PM PDT 24
Peak memory 183520 kb
Host smart-a7589e9c-b808-43e7-b403-bbb57bf77c91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947556757 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.947556757
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.3905957681
Short name T288
Test name
Test status
Simulation time 421594086 ps
CPU time 0.67 seconds
Started Apr 28 02:16:39 PM PDT 24
Finished Apr 28 02:16:41 PM PDT 24
Peak memory 183572 kb
Host smart-2b76bf21-3c5a-416c-8609-923efe60d008
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905957681 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.3905957681
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.1570415296
Short name T277
Test name
Test status
Simulation time 347429534 ps
CPU time 0.65 seconds
Started Apr 28 02:16:39 PM PDT 24
Finished Apr 28 02:16:41 PM PDT 24
Peak memory 183576 kb
Host smart-da573012-2c7e-48d2-ae48-241c6b956841
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570415296 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.1570415296
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.591400947
Short name T303
Test name
Test status
Simulation time 383769027 ps
CPU time 0.61 seconds
Started Apr 28 02:16:34 PM PDT 24
Finished Apr 28 02:16:36 PM PDT 24
Peak memory 183568 kb
Host smart-acfe138d-f888-4197-81ed-373e463771a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591400947 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.591400947
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.3366778080
Short name T283
Test name
Test status
Simulation time 390359356 ps
CPU time 1 seconds
Started Apr 28 02:16:38 PM PDT 24
Finished Apr 28 02:16:41 PM PDT 24
Peak memory 183572 kb
Host smart-e33d5663-5583-4178-8d58-7d4085fb54de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366778080 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.3366778080
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.2832502622
Short name T402
Test name
Test status
Simulation time 365159565 ps
CPU time 1.08 seconds
Started Apr 28 02:16:36 PM PDT 24
Finished Apr 28 02:16:39 PM PDT 24
Peak memory 183568 kb
Host smart-41726660-0e3b-4e03-9c8a-2d447525a44e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832502622 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.2832502622
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.4019364463
Short name T340
Test name
Test status
Simulation time 297945169 ps
CPU time 0.77 seconds
Started Apr 28 02:16:39 PM PDT 24
Finished Apr 28 02:16:41 PM PDT 24
Peak memory 183568 kb
Host smart-e054b048-daa3-4c7f-8451-3fa898db74a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019364463 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.4019364463
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.140725269
Short name T272
Test name
Test status
Simulation time 410304519 ps
CPU time 0.63 seconds
Started Apr 28 02:16:39 PM PDT 24
Finished Apr 28 02:16:40 PM PDT 24
Peak memory 183568 kb
Host smart-41a7c66e-c43f-427f-8952-771c23ad3189
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140725269 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.140725269
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.2878195144
Short name T312
Test name
Test status
Simulation time 420432962 ps
CPU time 1.2 seconds
Started Apr 28 02:16:41 PM PDT 24
Finished Apr 28 02:16:43 PM PDT 24
Peak memory 183572 kb
Host smart-88fb8d9c-b52a-4c74-84d9-4816f5fa839b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878195144 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.2878195144
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.412232045
Short name T286
Test name
Test status
Simulation time 356776174 ps
CPU time 0.68 seconds
Started Apr 28 02:16:28 PM PDT 24
Finished Apr 28 02:16:30 PM PDT 24
Peak memory 183612 kb
Host smart-8bf9b47b-85ab-4cbd-a777-f9db3c82e406
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412232045 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.412232045
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.2315190786
Short name T371
Test name
Test status
Simulation time 481007009 ps
CPU time 0.95 seconds
Started Apr 28 02:16:37 PM PDT 24
Finished Apr 28 02:16:39 PM PDT 24
Peak memory 195180 kb
Host smart-792fb21b-8bcd-46b0-a431-0225a4301dcb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315190786 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.2315190786
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.1707719525
Short name T352
Test name
Test status
Simulation time 512384964 ps
CPU time 1.37 seconds
Started Apr 28 02:16:16 PM PDT 24
Finished Apr 28 02:16:18 PM PDT 24
Peak memory 192952 kb
Host smart-77fad813-6e46-4ecb-9d7d-1e8242c5436d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707719525 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.1707719525
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.3923883148
Short name T278
Test name
Test status
Simulation time 352464054 ps
CPU time 0.65 seconds
Started Apr 28 02:16:20 PM PDT 24
Finished Apr 28 02:16:21 PM PDT 24
Peak memory 183572 kb
Host smart-b51d3dc1-c58e-4f07-8fe1-43e6fc4c2db1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923883148 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.3923883148
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.3856552552
Short name T332
Test name
Test status
Simulation time 2114441856 ps
CPU time 1.12 seconds
Started Apr 28 02:16:22 PM PDT 24
Finished Apr 28 02:16:24 PM PDT 24
Peak memory 194208 kb
Host smart-09b54b54-0c37-4590-86c6-bb2717f49d04
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856552552 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon
_timer_same_csr_outstanding.3856552552
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.2719869700
Short name T373
Test name
Test status
Simulation time 526865419 ps
CPU time 1.84 seconds
Started Apr 28 02:16:19 PM PDT 24
Finished Apr 28 02:16:21 PM PDT 24
Peak memory 198488 kb
Host smart-87b07cdc-ed4d-436b-b27e-4926f4ce73ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719869700 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.2719869700
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.4095765590
Short name T386
Test name
Test status
Simulation time 4676609924 ps
CPU time 2.04 seconds
Started Apr 28 02:16:13 PM PDT 24
Finished Apr 28 02:16:16 PM PDT 24
Peak memory 196524 kb
Host smart-a256110f-0772-41ef-893a-76e7224ba1bb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095765590 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl
_intg_err.4095765590
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.706527457
Short name T344
Test name
Test status
Simulation time 597055785 ps
CPU time 1.26 seconds
Started Apr 28 02:16:15 PM PDT 24
Finished Apr 28 02:16:17 PM PDT 24
Peak memory 195988 kb
Host smart-01fd59a1-50a8-4ee9-a8db-f2620051303e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706527457 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.706527457
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.2394481009
Short name T361
Test name
Test status
Simulation time 383455517 ps
CPU time 0.75 seconds
Started Apr 28 02:16:24 PM PDT 24
Finished Apr 28 02:16:26 PM PDT 24
Peak memory 193124 kb
Host smart-fe407fb6-57f6-4d43-ad5b-16cd4f4cd180
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394481009 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.2394481009
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.1626750308
Short name T275
Test name
Test status
Simulation time 418654471 ps
CPU time 1.21 seconds
Started Apr 28 02:16:19 PM PDT 24
Finished Apr 28 02:16:21 PM PDT 24
Peak memory 183552 kb
Host smart-03962d5f-5bbd-4b20-af84-1a7f3e9885b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626750308 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.1626750308
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.84826789
Short name T369
Test name
Test status
Simulation time 1134547141 ps
CPU time 3.11 seconds
Started Apr 28 02:16:23 PM PDT 24
Finished Apr 28 02:16:27 PM PDT 24
Peak memory 183892 kb
Host smart-00d084dd-2a75-4a72-9d4d-53d8514a284c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84826789 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_t
imer_same_csr_outstanding.84826789
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.2859061365
Short name T407
Test name
Test status
Simulation time 337704621 ps
CPU time 1.58 seconds
Started Apr 28 02:16:33 PM PDT 24
Finished Apr 28 02:16:36 PM PDT 24
Peak memory 198508 kb
Host smart-f403ce33-3819-47fe-b00b-17f7705c2451
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859061365 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.2859061365
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.2023858925
Short name T313
Test name
Test status
Simulation time 7833223820 ps
CPU time 6.67 seconds
Started Apr 28 02:16:13 PM PDT 24
Finished Apr 28 02:16:20 PM PDT 24
Peak memory 197696 kb
Host smart-078e8538-9143-454c-8c8d-d0c6a365ed1d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023858925 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl
_intg_err.2023858925
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.1807683970
Short name T290
Test name
Test status
Simulation time 573345883 ps
CPU time 0.76 seconds
Started Apr 28 02:16:16 PM PDT 24
Finished Apr 28 02:16:18 PM PDT 24
Peak memory 195568 kb
Host smart-169b3cc3-f968-4978-8027-a8ad2603cbac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807683970 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.1807683970
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.2393252201
Short name T53
Test name
Test status
Simulation time 420185164 ps
CPU time 1.34 seconds
Started Apr 28 02:16:15 PM PDT 24
Finished Apr 28 02:16:17 PM PDT 24
Peak memory 183672 kb
Host smart-cc070fc4-f515-483e-96c9-632ee5537b40
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393252201 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.2393252201
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.3598114121
Short name T334
Test name
Test status
Simulation time 419842633 ps
CPU time 1.22 seconds
Started Apr 28 02:16:20 PM PDT 24
Finished Apr 28 02:16:22 PM PDT 24
Peak memory 183576 kb
Host smart-fb25ed49-ce42-4fe2-ab74-2919c4ce0404
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598114121 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.3598114121
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.176400649
Short name T329
Test name
Test status
Simulation time 1184495081 ps
CPU time 2.26 seconds
Started Apr 28 02:16:31 PM PDT 24
Finished Apr 28 02:16:34 PM PDT 24
Peak memory 193244 kb
Host smart-f1fbc0b9-8df5-4591-879a-00b706de0103
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176400649 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_
timer_same_csr_outstanding.176400649
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.245142359
Short name T374
Test name
Test status
Simulation time 504062718 ps
CPU time 2.06 seconds
Started Apr 28 02:16:27 PM PDT 24
Finished Apr 28 02:16:30 PM PDT 24
Peak memory 198484 kb
Host smart-53106614-5c83-459e-8462-5292b86714c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245142359 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.245142359
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.769931663
Short name T301
Test name
Test status
Simulation time 8748138949 ps
CPU time 4.83 seconds
Started Apr 28 02:16:25 PM PDT 24
Finished Apr 28 02:16:30 PM PDT 24
Peak memory 197900 kb
Host smart-e509ffba-2e4b-45d1-932e-525ebae116f9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769931663 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_
intg_err.769931663
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.2406960734
Short name T291
Test name
Test status
Simulation time 436934009 ps
CPU time 1.31 seconds
Started Apr 28 02:16:24 PM PDT 24
Finished Apr 28 02:16:27 PM PDT 24
Peak memory 195368 kb
Host smart-47cb4b71-07e4-4f23-ad51-9b1d22026f27
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406960734 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.2406960734
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.686695348
Short name T63
Test name
Test status
Simulation time 497314214 ps
CPU time 1.02 seconds
Started Apr 28 02:16:29 PM PDT 24
Finished Apr 28 02:16:31 PM PDT 24
Peak memory 192960 kb
Host smart-33ef6842-0b31-473e-98a2-1faea3cd3812
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686695348 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.686695348
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.2429242400
Short name T387
Test name
Test status
Simulation time 442901243 ps
CPU time 0.69 seconds
Started Apr 28 02:16:24 PM PDT 24
Finished Apr 28 02:16:26 PM PDT 24
Peak memory 183520 kb
Host smart-a1446fc8-2905-4234-ac01-55c60b062542
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429242400 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.2429242400
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.2117300278
Short name T382
Test name
Test status
Simulation time 2519769191 ps
CPU time 2.17 seconds
Started Apr 28 02:16:13 PM PDT 24
Finished Apr 28 02:16:15 PM PDT 24
Peak memory 183828 kb
Host smart-d65b1719-fca4-4469-9e7c-5c9852651ab6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117300278 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon
_timer_same_csr_outstanding.2117300278
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.1891475817
Short name T408
Test name
Test status
Simulation time 570076173 ps
CPU time 1.2 seconds
Started Apr 28 02:16:20 PM PDT 24
Finished Apr 28 02:16:22 PM PDT 24
Peak memory 198252 kb
Host smart-8838524f-4fad-4aa2-a544-c71447954a7a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891475817 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.1891475817
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.2047130231
Short name T306
Test name
Test status
Simulation time 8135941825 ps
CPU time 13.98 seconds
Started Apr 28 02:16:15 PM PDT 24
Finished Apr 28 02:16:30 PM PDT 24
Peak memory 197896 kb
Host smart-c0efecd1-8ffe-406c-8f9e-c3a4e182c04c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047130231 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl
_intg_err.2047130231
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.1668763831
Short name T376
Test name
Test status
Simulation time 509183444 ps
CPU time 1.32 seconds
Started Apr 28 02:16:19 PM PDT 24
Finished Apr 28 02:16:21 PM PDT 24
Peak memory 196184 kb
Host smart-fc6bd0a4-b394-4a07-8077-d41aef82e4a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668763831 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.1668763831
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.2620495195
Short name T416
Test name
Test status
Simulation time 400140100 ps
CPU time 0.71 seconds
Started Apr 28 02:16:30 PM PDT 24
Finished Apr 28 02:16:32 PM PDT 24
Peak memory 192736 kb
Host smart-099be1a9-9417-4d42-bce8-60250e1bcc65
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620495195 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.2620495195
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.449153099
Short name T355
Test name
Test status
Simulation time 477569751 ps
CPU time 1.25 seconds
Started Apr 28 02:16:23 PM PDT 24
Finished Apr 28 02:16:25 PM PDT 24
Peak memory 183572 kb
Host smart-4a4c7d1d-7d4e-4426-a080-87d7731cd770
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449153099 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.449153099
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.2235209455
Short name T78
Test name
Test status
Simulation time 1795322293 ps
CPU time 5.09 seconds
Started Apr 28 02:16:17 PM PDT 24
Finished Apr 28 02:16:22 PM PDT 24
Peak memory 193128 kb
Host smart-43aa1cee-0435-4602-ada6-0d1ed93d7598
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235209455 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon
_timer_same_csr_outstanding.2235209455
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.1492803254
Short name T391
Test name
Test status
Simulation time 705769364 ps
CPU time 1.8 seconds
Started Apr 28 02:16:23 PM PDT 24
Finished Apr 28 02:16:25 PM PDT 24
Peak memory 198496 kb
Host smart-f1505a9b-956b-4eaf-8573-374a2bc2d3e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492803254 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.1492803254
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.2387321166
Short name T370
Test name
Test status
Simulation time 4070631812 ps
CPU time 6.25 seconds
Started Apr 28 02:16:15 PM PDT 24
Finished Apr 28 02:16:22 PM PDT 24
Peak memory 197500 kb
Host smart-0dded103-2a4c-4b46-8cf1-7b108db731cf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387321166 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl
_intg_err.2387321166
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_jump.2149154051
Short name T238
Test name
Test status
Simulation time 547125660 ps
CPU time 0.9 seconds
Started Apr 28 02:15:30 PM PDT 24
Finished Apr 28 02:15:31 PM PDT 24
Peak memory 183564 kb
Host smart-9a4d4402-1ff1-449a-933a-952c41dc066f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149154051 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.2149154051
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.3269298576
Short name T125
Test name
Test status
Simulation time 14972177492 ps
CPU time 22.22 seconds
Started Apr 28 02:15:33 PM PDT 24
Finished Apr 28 02:15:56 PM PDT 24
Peak memory 183640 kb
Host smart-eca9b75c-2915-48a6-be94-ec055a0cab47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269298576 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.3269298576
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.3649205257
Short name T227
Test name
Test status
Simulation time 118211543284 ps
CPU time 23.5 seconds
Started Apr 28 02:15:42 PM PDT 24
Finished Apr 28 02:16:08 PM PDT 24
Peak memory 194804 kb
Host smart-a7768fe2-aacd-4dcd-9dcc-b311f978254f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649205257 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_a
ll.3649205257
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_jump.2370170925
Short name T236
Test name
Test status
Simulation time 609798700 ps
CPU time 0.61 seconds
Started Apr 28 02:15:38 PM PDT 24
Finished Apr 28 02:15:40 PM PDT 24
Peak memory 183496 kb
Host smart-4b144ff4-2f54-4e96-a945-cee5f4184a9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370170925 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.2370170925
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.3033624947
Short name T21
Test name
Test status
Simulation time 30647369264 ps
CPU time 12.44 seconds
Started Apr 28 02:15:39 PM PDT 24
Finished Apr 28 02:15:52 PM PDT 24
Peak memory 183608 kb
Host smart-7c72486b-2952-4b9f-88a7-80bc4a8a7c52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033624947 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.3033624947
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.3544368449
Short name T18
Test name
Test status
Simulation time 4771467251 ps
CPU time 1.09 seconds
Started Apr 28 02:15:41 PM PDT 24
Finished Apr 28 02:15:44 PM PDT 24
Peak memory 215084 kb
Host smart-e2e6cd88-2db5-4b45-a5dc-bfcb1c100c56
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544368449 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.3544368449
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.1680078577
Short name T163
Test name
Test status
Simulation time 482509567 ps
CPU time 0.74 seconds
Started Apr 28 02:15:40 PM PDT 24
Finished Apr 28 02:15:42 PM PDT 24
Peak memory 183536 kb
Host smart-409b208e-a944-4ed0-a26b-84024329c85d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680078577 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.1680078577
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.4113566959
Short name T189
Test name
Test status
Simulation time 75369762901 ps
CPU time 27.61 seconds
Started Apr 28 02:15:30 PM PDT 24
Finished Apr 28 02:15:58 PM PDT 24
Peak memory 195200 kb
Host smart-d778f1aa-13f5-4473-a6fc-f7cbce5541f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113566959 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_a
ll.4113566959
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.4282342448
Short name T211
Test name
Test status
Simulation time 34288619582 ps
CPU time 195.64 seconds
Started Apr 28 02:15:43 PM PDT 24
Finished Apr 28 02:19:02 PM PDT 24
Peak memory 198572 kb
Host smart-7f4b1809-d1ff-4056-ad49-ee632f07faa0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282342448 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.4282342448
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.aon_timer_jump.3593355158
Short name T103
Test name
Test status
Simulation time 572376885 ps
CPU time 1.44 seconds
Started Apr 28 02:15:42 PM PDT 24
Finished Apr 28 02:15:47 PM PDT 24
Peak memory 183512 kb
Host smart-9b20a821-88e0-493b-8c0a-fae59fc22847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593355158 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.3593355158
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.3565098524
Short name T161
Test name
Test status
Simulation time 39648469038 ps
CPU time 16.76 seconds
Started Apr 28 02:15:44 PM PDT 24
Finished Apr 28 02:16:04 PM PDT 24
Peak memory 183624 kb
Host smart-e3b05a24-6fce-4ae5-b686-b9752c5d7b1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565098524 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.3565098524
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.477037578
Short name T105
Test name
Test status
Simulation time 514814355 ps
CPU time 0.77 seconds
Started Apr 28 02:15:44 PM PDT 24
Finished Apr 28 02:15:48 PM PDT 24
Peak memory 183500 kb
Host smart-486371aa-7df2-4928-b7e9-352e6b4fe015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477037578 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.477037578
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.539360859
Short name T169
Test name
Test status
Simulation time 6408940568 ps
CPU time 5.58 seconds
Started Apr 28 02:15:39 PM PDT 24
Finished Apr 28 02:15:45 PM PDT 24
Peak memory 183528 kb
Host smart-bd3151c9-2287-497a-8025-3db52097d6ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539360859 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_a
ll.539360859
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.612022794
Short name T85
Test name
Test status
Simulation time 69704717724 ps
CPU time 259.11 seconds
Started Apr 28 02:15:50 PM PDT 24
Finished Apr 28 02:20:12 PM PDT 24
Peak memory 198384 kb
Host smart-fb36c66f-d151-48be-ac03-768d13219542
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612022794 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.612022794
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.aon_timer_jump.588636546
Short name T117
Test name
Test status
Simulation time 559490203 ps
CPU time 1.49 seconds
Started Apr 28 02:15:32 PM PDT 24
Finished Apr 28 02:15:35 PM PDT 24
Peak memory 183560 kb
Host smart-bc89f07a-2a0e-4e0e-abe2-a41d993a2f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588636546 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.588636546
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.911564808
Short name T251
Test name
Test status
Simulation time 7676189545 ps
CPU time 12.2 seconds
Started Apr 28 02:15:39 PM PDT 24
Finished Apr 28 02:15:52 PM PDT 24
Peak memory 183572 kb
Host smart-031678ae-de0d-4031-b9cc-0fd7c15887c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911564808 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.911564808
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.185133547
Short name T259
Test name
Test status
Simulation time 391187674 ps
CPU time 1.19 seconds
Started Apr 28 02:15:43 PM PDT 24
Finished Apr 28 02:15:48 PM PDT 24
Peak memory 183568 kb
Host smart-9abcf64f-a973-482d-8fa2-319559ff5128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185133547 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.185133547
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_jump.3374935533
Short name T253
Test name
Test status
Simulation time 465543628 ps
CPU time 0.76 seconds
Started Apr 28 02:15:50 PM PDT 24
Finished Apr 28 02:15:54 PM PDT 24
Peak memory 183380 kb
Host smart-1cf8c861-8346-4576-bb61-1ec8b92c6d6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374935533 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.3374935533
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.1742878185
Short name T222
Test name
Test status
Simulation time 5008357555 ps
CPU time 2.63 seconds
Started Apr 28 02:15:49 PM PDT 24
Finished Apr 28 02:15:55 PM PDT 24
Peak memory 183448 kb
Host smart-35db5239-4f81-4394-9b8c-1631c8b17496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742878185 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.1742878185
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.3592783038
Short name T112
Test name
Test status
Simulation time 499634955 ps
CPU time 1.49 seconds
Started Apr 28 02:15:37 PM PDT 24
Finished Apr 28 02:15:39 PM PDT 24
Peak memory 183560 kb
Host smart-2422b7eb-066c-417c-95f1-2a69d41369f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592783038 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.3592783038
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_jump.354052955
Short name T159
Test name
Test status
Simulation time 535301886 ps
CPU time 1.34 seconds
Started Apr 28 02:15:48 PM PDT 24
Finished Apr 28 02:15:53 PM PDT 24
Peak memory 183568 kb
Host smart-5a3bb260-306a-4d64-9116-e774378b0c7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354052955 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.354052955
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.724551184
Short name T221
Test name
Test status
Simulation time 39986816971 ps
CPU time 33.12 seconds
Started Apr 28 02:15:40 PM PDT 24
Finished Apr 28 02:16:14 PM PDT 24
Peak memory 191812 kb
Host smart-c41c85eb-63ba-4a19-94ae-cc708c353c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724551184 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.724551184
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.1757788371
Short name T244
Test name
Test status
Simulation time 355940824 ps
CPU time 1.06 seconds
Started Apr 28 02:15:44 PM PDT 24
Finished Apr 28 02:15:49 PM PDT 24
Peak memory 183560 kb
Host smart-768ba97f-37ce-425e-8dc6-f54f9ef171c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757788371 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.1757788371
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.53626721
Short name T223
Test name
Test status
Simulation time 171601557796 ps
CPU time 278.56 seconds
Started Apr 28 02:15:45 PM PDT 24
Finished Apr 28 02:20:27 PM PDT 24
Peak memory 195180 kb
Host smart-8965cd84-af43-4bb1-9c1e-8d41bc359bdc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53626721 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_al
l.53626721
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.2832790862
Short name T229
Test name
Test status
Simulation time 140791224293 ps
CPU time 168.83 seconds
Started Apr 28 02:15:43 PM PDT 24
Finished Apr 28 02:18:36 PM PDT 24
Peak memory 198532 kb
Host smart-e146d9f1-cf9d-4f11-8c0c-a9b9d53f291a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832790862 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.2832790862
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.aon_timer_jump.492994330
Short name T106
Test name
Test status
Simulation time 531971746 ps
CPU time 0.91 seconds
Started Apr 28 02:15:42 PM PDT 24
Finished Apr 28 02:15:45 PM PDT 24
Peak memory 183520 kb
Host smart-4462d4f5-3dc3-41b4-b47e-17db083e50a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492994330 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.492994330
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.1255896423
Short name T10
Test name
Test status
Simulation time 52954563791 ps
CPU time 78.41 seconds
Started Apr 28 02:15:40 PM PDT 24
Finished Apr 28 02:17:00 PM PDT 24
Peak memory 183588 kb
Host smart-678726af-adfc-4d0d-98c1-ff78600f9438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255896423 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.1255896423
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.3588251914
Short name T173
Test name
Test status
Simulation time 570159947 ps
CPU time 0.97 seconds
Started Apr 28 02:15:46 PM PDT 24
Finished Apr 28 02:15:55 PM PDT 24
Peak memory 183572 kb
Host smart-e8ca6496-8691-4db1-8cae-e3ec1c7ea18f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588251914 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.3588251914
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.3638955277
Short name T218
Test name
Test status
Simulation time 203390030831 ps
CPU time 36.93 seconds
Started Apr 28 02:15:44 PM PDT 24
Finished Apr 28 02:16:25 PM PDT 24
Peak memory 195132 kb
Host smart-9b06441a-2dc2-4506-9df2-e2237cd0896e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638955277 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_
all.3638955277
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.750297357
Short name T154
Test name
Test status
Simulation time 70708603349 ps
CPU time 514.52 seconds
Started Apr 28 02:15:48 PM PDT 24
Finished Apr 28 02:24:26 PM PDT 24
Peak memory 198512 kb
Host smart-60728828-3e7e-4383-a52c-2f7d2d4eaa62
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750297357 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.750297357
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.aon_timer_jump.1606531577
Short name T129
Test name
Test status
Simulation time 376682919 ps
CPU time 1.11 seconds
Started Apr 28 02:15:51 PM PDT 24
Finished Apr 28 02:15:55 PM PDT 24
Peak memory 183568 kb
Host smart-5c742e10-7810-4e55-8352-95589b3d4df8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606531577 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.1606531577
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.1436389085
Short name T94
Test name
Test status
Simulation time 42510875740 ps
CPU time 60.57 seconds
Started Apr 28 02:15:44 PM PDT 24
Finished Apr 28 02:16:48 PM PDT 24
Peak memory 183616 kb
Host smart-154b71d7-1cd6-4aa4-a42a-493925bc93a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436389085 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.1436389085
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.2149029101
Short name T175
Test name
Test status
Simulation time 378337897 ps
CPU time 0.78 seconds
Started Apr 28 02:15:44 PM PDT 24
Finished Apr 28 02:15:48 PM PDT 24
Peak memory 183524 kb
Host smart-b9af5361-7d1e-4244-bc5c-9b96b9c22fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149029101 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.2149029101
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.1004303718
Short name T48
Test name
Test status
Simulation time 155028103674 ps
CPU time 29.77 seconds
Started Apr 28 02:15:42 PM PDT 24
Finished Apr 28 02:16:15 PM PDT 24
Peak memory 194368 kb
Host smart-8b086265-fd9e-465c-926f-a7ecf90e381e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004303718 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_
all.1004303718
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.21104695
Short name T207
Test name
Test status
Simulation time 35261346562 ps
CPU time 379.52 seconds
Started Apr 28 02:15:44 PM PDT 24
Finished Apr 28 02:22:07 PM PDT 24
Peak memory 198496 kb
Host smart-30d61d15-f7ba-4761-ac07-44004d0917fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21104695 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.21104695
Directory /workspace/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.aon_timer_jump.3415876590
Short name T217
Test name
Test status
Simulation time 419436344 ps
CPU time 0.87 seconds
Started Apr 28 02:15:40 PM PDT 24
Finished Apr 28 02:15:42 PM PDT 24
Peak memory 183576 kb
Host smart-f9f83b36-def7-48e0-8c50-f43221a3fc2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415876590 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.3415876590
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.3421929751
Short name T126
Test name
Test status
Simulation time 20869122606 ps
CPU time 22.58 seconds
Started Apr 28 02:15:45 PM PDT 24
Finished Apr 28 02:16:11 PM PDT 24
Peak memory 183624 kb
Host smart-77b9addf-034e-49ff-b251-8ffee71bcf27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421929751 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.3421929751
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.3630938684
Short name T220
Test name
Test status
Simulation time 388213262 ps
CPU time 0.83 seconds
Started Apr 28 02:15:48 PM PDT 24
Finished Apr 28 02:15:52 PM PDT 24
Peak memory 183580 kb
Host smart-9b3cb803-a21b-40f6-8243-43ef9288f56e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630938684 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.3630938684
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.3917510189
Short name T265
Test name
Test status
Simulation time 4781307172 ps
CPU time 2.44 seconds
Started Apr 28 02:15:45 PM PDT 24
Finished Apr 28 02:15:51 PM PDT 24
Peak memory 183632 kb
Host smart-22530e9e-e259-4f18-a3a8-806bcaef10a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917510189 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_
all.3917510189
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.1252395394
Short name T42
Test name
Test status
Simulation time 98258428771 ps
CPU time 219.24 seconds
Started Apr 28 02:15:45 PM PDT 24
Finished Apr 28 02:19:28 PM PDT 24
Peak memory 198484 kb
Host smart-60e2cab4-8a7c-436a-846c-505ad716c384
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252395394 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.1252395394
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.aon_timer_jump.2785495044
Short name T44
Test name
Test status
Simulation time 573721610 ps
CPU time 0.75 seconds
Started Apr 28 02:15:45 PM PDT 24
Finished Apr 28 02:15:49 PM PDT 24
Peak memory 183536 kb
Host smart-496e7263-f486-4722-ac68-1e5149ae4c8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785495044 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.2785495044
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.163086317
Short name T178
Test name
Test status
Simulation time 50715941266 ps
CPU time 80.5 seconds
Started Apr 28 02:15:43 PM PDT 24
Finished Apr 28 02:17:07 PM PDT 24
Peak memory 183596 kb
Host smart-6bc91aff-8559-439b-8cd0-a58a27f162a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163086317 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.163086317
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.2418991575
Short name T224
Test name
Test status
Simulation time 579043060 ps
CPU time 0.73 seconds
Started Apr 28 02:15:46 PM PDT 24
Finished Apr 28 02:15:50 PM PDT 24
Peak memory 183452 kb
Host smart-0a6097e0-700f-4521-823c-934d45a27a64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418991575 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.2418991575
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.1246031775
Short name T181
Test name
Test status
Simulation time 577321613197 ps
CPU time 892.54 seconds
Started Apr 28 02:15:40 PM PDT 24
Finished Apr 28 02:30:34 PM PDT 24
Peak memory 195224 kb
Host smart-5c7d25bd-530c-48f4-bb50-85248ce443fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246031775 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_
all.1246031775
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_jump.28743971
Short name T140
Test name
Test status
Simulation time 368926450 ps
CPU time 1.11 seconds
Started Apr 28 02:15:49 PM PDT 24
Finished Apr 28 02:15:57 PM PDT 24
Peak memory 183584 kb
Host smart-09a476cf-16d9-4a92-8228-a2c178e1b89a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28743971 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.28743971
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.2118254491
Short name T255
Test name
Test status
Simulation time 35020183685 ps
CPU time 53.76 seconds
Started Apr 28 02:15:51 PM PDT 24
Finished Apr 28 02:16:48 PM PDT 24
Peak memory 191868 kb
Host smart-1e510d49-3f56-4e3f-a9dc-c49183e2f1aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118254491 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.2118254491
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.3659751315
Short name T144
Test name
Test status
Simulation time 477538467 ps
CPU time 0.63 seconds
Started Apr 28 02:15:46 PM PDT 24
Finished Apr 28 02:15:50 PM PDT 24
Peak memory 183448 kb
Host smart-e487c399-b885-4cf3-b95a-c696997f20fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659751315 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.3659751315
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.2479206117
Short name T270
Test name
Test status
Simulation time 60174815844 ps
CPU time 47.14 seconds
Started Apr 28 02:15:48 PM PDT 24
Finished Apr 28 02:16:39 PM PDT 24
Peak memory 194692 kb
Host smart-888effc8-61f9-4fdb-849e-e8d28e4db31b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479206117 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_
all.2479206117
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.140229148
Short name T86
Test name
Test status
Simulation time 34427049835 ps
CPU time 276.59 seconds
Started Apr 28 02:15:46 PM PDT 24
Finished Apr 28 02:20:26 PM PDT 24
Peak memory 198436 kb
Host smart-7287e390-a732-4f33-92f6-173ea41d0f8d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140229148 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.140229148
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.aon_timer_jump.136274887
Short name T204
Test name
Test status
Simulation time 532275078 ps
CPU time 0.99 seconds
Started Apr 28 02:15:46 PM PDT 24
Finished Apr 28 02:15:51 PM PDT 24
Peak memory 183512 kb
Host smart-f6e96fab-8b0f-4647-b1e5-485768798457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136274887 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.136274887
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.2013111850
Short name T102
Test name
Test status
Simulation time 7741781024 ps
CPU time 6.19 seconds
Started Apr 28 02:15:45 PM PDT 24
Finished Apr 28 02:15:54 PM PDT 24
Peak memory 183504 kb
Host smart-8fdad6b6-380b-41d8-b1f1-abf48e8c6a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013111850 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.2013111850
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.3704584324
Short name T199
Test name
Test status
Simulation time 353131663 ps
CPU time 1.07 seconds
Started Apr 28 02:15:49 PM PDT 24
Finished Apr 28 02:15:54 PM PDT 24
Peak memory 183580 kb
Host smart-45fe56d2-7cb6-46e9-9659-9fffd4a35f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704584324 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.3704584324
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.2860173672
Short name T180
Test name
Test status
Simulation time 267459713131 ps
CPU time 395.25 seconds
Started Apr 28 02:15:51 PM PDT 24
Finished Apr 28 02:22:29 PM PDT 24
Peak memory 183664 kb
Host smart-f1818c22-0c5e-4c3d-b741-2a6977b0de3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860173672 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_
all.2860173672
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.2262985565
Short name T87
Test name
Test status
Simulation time 26276660740 ps
CPU time 185.31 seconds
Started Apr 28 02:15:46 PM PDT 24
Finished Apr 28 02:18:54 PM PDT 24
Peak memory 198444 kb
Host smart-3346993c-f3e2-4227-8004-4a16ef840820
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262985565 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.2262985565
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_jump.3909308548
Short name T184
Test name
Test status
Simulation time 572775167 ps
CPU time 1.28 seconds
Started Apr 28 02:15:44 PM PDT 24
Finished Apr 28 02:15:49 PM PDT 24
Peak memory 183564 kb
Host smart-24872d60-095b-4c1a-b573-04584a106ce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909308548 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.3909308548
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.4179057968
Short name T46
Test name
Test status
Simulation time 31476907515 ps
CPU time 5.57 seconds
Started Apr 28 02:15:45 PM PDT 24
Finished Apr 28 02:15:54 PM PDT 24
Peak memory 183560 kb
Host smart-7b5da342-f1b9-44bb-80b2-373f8a01ef2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179057968 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.4179057968
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.2335104545
Short name T19
Test name
Test status
Simulation time 7389966579 ps
CPU time 11.27 seconds
Started Apr 28 02:15:30 PM PDT 24
Finished Apr 28 02:15:41 PM PDT 24
Peak memory 215216 kb
Host smart-08d4bea6-ea0e-4635-8565-940963e8ffbb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335104545 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.2335104545
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.3286001566
Short name T28
Test name
Test status
Simulation time 494994830 ps
CPU time 0.89 seconds
Started Apr 28 02:15:41 PM PDT 24
Finished Apr 28 02:15:44 PM PDT 24
Peak memory 183564 kb
Host smart-cc301f5c-affd-47c6-a5c8-9949357ec768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286001566 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.3286001566
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_jump.493697704
Short name T237
Test name
Test status
Simulation time 376631911 ps
CPU time 1.03 seconds
Started Apr 28 02:15:51 PM PDT 24
Finished Apr 28 02:15:55 PM PDT 24
Peak memory 183616 kb
Host smart-85696277-f377-42e2-a3c6-03e0dc80f9b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493697704 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.493697704
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.40104859
Short name T240
Test name
Test status
Simulation time 32912957965 ps
CPU time 9.65 seconds
Started Apr 28 02:15:51 PM PDT 24
Finished Apr 28 02:16:07 PM PDT 24
Peak memory 183624 kb
Host smart-96b4631b-6c93-420f-8749-6a649b47b00b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40104859 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.40104859
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.488049277
Short name T107
Test name
Test status
Simulation time 628679659 ps
CPU time 0.62 seconds
Started Apr 28 02:15:40 PM PDT 24
Finished Apr 28 02:15:42 PM PDT 24
Peak memory 183524 kb
Host smart-fb3c5231-982e-487d-8f2c-b5803219bf47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488049277 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.488049277
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.3193229880
Short name T1
Test name
Test status
Simulation time 12512444210 ps
CPU time 19.88 seconds
Started Apr 28 02:15:44 PM PDT 24
Finished Apr 28 02:16:08 PM PDT 24
Peak memory 183584 kb
Host smart-b3af3528-6e87-40bc-ac12-d77f26451fa2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193229880 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_
all.3193229880
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.3063572458
Short name T188
Test name
Test status
Simulation time 19525455048 ps
CPU time 167.66 seconds
Started Apr 28 02:15:43 PM PDT 24
Finished Apr 28 02:18:34 PM PDT 24
Peak memory 198432 kb
Host smart-313e3c9a-9d84-4aad-9e11-3f7de543ea2d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063572458 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.3063572458
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_jump.1468033878
Short name T157
Test name
Test status
Simulation time 447971014 ps
CPU time 1.27 seconds
Started Apr 28 02:15:49 PM PDT 24
Finished Apr 28 02:15:53 PM PDT 24
Peak memory 183524 kb
Host smart-c1029bad-a0b3-4d54-aa60-782a7df100bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468033878 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.1468033878
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.1258874182
Short name T208
Test name
Test status
Simulation time 5746658163 ps
CPU time 0.99 seconds
Started Apr 28 02:15:43 PM PDT 24
Finished Apr 28 02:15:48 PM PDT 24
Peak memory 183600 kb
Host smart-87835f15-290d-42ff-a064-992be70246f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258874182 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.1258874182
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.1562089526
Short name T109
Test name
Test status
Simulation time 524036835 ps
CPU time 0.76 seconds
Started Apr 28 02:15:44 PM PDT 24
Finished Apr 28 02:15:48 PM PDT 24
Peak memory 183464 kb
Host smart-a11140d3-b250-4cfb-9f51-9bb29c3a3572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562089526 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.1562089526
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.36550408
Short name T248
Test name
Test status
Simulation time 64700544188 ps
CPU time 12.96 seconds
Started Apr 28 02:15:52 PM PDT 24
Finished Apr 28 02:16:15 PM PDT 24
Peak memory 183660 kb
Host smart-8abf518c-db1e-4c37-ac7c-ec8518d9596f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36550408 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_al
l.36550408
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.1043094755
Short name T234
Test name
Test status
Simulation time 64893914947 ps
CPU time 117.64 seconds
Started Apr 28 02:15:44 PM PDT 24
Finished Apr 28 02:17:45 PM PDT 24
Peak memory 198464 kb
Host smart-221732fd-ec8d-47bc-b97c-4181a184f6af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043094755 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.1043094755
Directory /workspace/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.aon_timer_jump.3641180742
Short name T26
Test name
Test status
Simulation time 349073527 ps
CPU time 1.03 seconds
Started Apr 28 02:15:49 PM PDT 24
Finished Apr 28 02:15:53 PM PDT 24
Peak memory 183576 kb
Host smart-bdd76b92-3b3d-45ea-8708-60118b06c828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641180742 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.3641180742
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.2714492945
Short name T153
Test name
Test status
Simulation time 50817902990 ps
CPU time 22.95 seconds
Started Apr 28 02:15:51 PM PDT 24
Finished Apr 28 02:16:17 PM PDT 24
Peak memory 183668 kb
Host smart-48b3ab7e-21ae-4053-ab60-922615dfd70a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714492945 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.2714492945
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.2558251022
Short name T121
Test name
Test status
Simulation time 536023039 ps
CPU time 0.78 seconds
Started Apr 28 02:15:45 PM PDT 24
Finished Apr 28 02:15:49 PM PDT 24
Peak memory 183600 kb
Host smart-da4f6483-17c9-4352-be40-f237075e5028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558251022 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.2558251022
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.2119197778
Short name T174
Test name
Test status
Simulation time 517907372257 ps
CPU time 191.27 seconds
Started Apr 28 02:15:44 PM PDT 24
Finished Apr 28 02:19:00 PM PDT 24
Peak memory 183576 kb
Host smart-e8015630-d855-450b-adbe-1196616e9b99
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119197778 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_
all.2119197778
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.361434759
Short name T245
Test name
Test status
Simulation time 307557118744 ps
CPU time 856.88 seconds
Started Apr 28 02:15:48 PM PDT 24
Finished Apr 28 02:30:08 PM PDT 24
Peak memory 203536 kb
Host smart-e7b68758-93d7-45ad-89a0-16fdf900c1a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361434759 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.361434759
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.aon_timer_jump.1560922830
Short name T74
Test name
Test status
Simulation time 566176165 ps
CPU time 1.29 seconds
Started Apr 28 02:15:44 PM PDT 24
Finished Apr 28 02:15:49 PM PDT 24
Peak memory 183564 kb
Host smart-96ec8cac-ed4a-4fb5-b1ab-237421706ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560922830 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.1560922830
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.1723968434
Short name T6
Test name
Test status
Simulation time 6092674350 ps
CPU time 10.03 seconds
Started Apr 28 02:15:44 PM PDT 24
Finished Apr 28 02:15:57 PM PDT 24
Peak memory 191792 kb
Host smart-04f745ab-0399-4c98-aeb8-bb8d42beb370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723968434 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.1723968434
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.3054571740
Short name T145
Test name
Test status
Simulation time 365654363 ps
CPU time 0.66 seconds
Started Apr 28 02:15:52 PM PDT 24
Finished Apr 28 02:15:56 PM PDT 24
Peak memory 183600 kb
Host smart-47aa6426-f5d9-4935-9119-1faee74c62c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054571740 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.3054571740
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.1886548805
Short name T7
Test name
Test status
Simulation time 134949673437 ps
CPU time 214.22 seconds
Started Apr 28 02:15:44 PM PDT 24
Finished Apr 28 02:19:22 PM PDT 24
Peak memory 183640 kb
Host smart-546992c9-54b6-4e4e-a333-8a89cd7b6a2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886548805 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_
all.1886548805
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_jump.3478824241
Short name T241
Test name
Test status
Simulation time 611722526 ps
CPU time 0.73 seconds
Started Apr 28 02:15:42 PM PDT 24
Finished Apr 28 02:15:45 PM PDT 24
Peak memory 183568 kb
Host smart-2619b179-6d6e-497d-bf59-1412f368bd30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478824241 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.3478824241
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.3732210650
Short name T66
Test name
Test status
Simulation time 39298629149 ps
CPU time 14.78 seconds
Started Apr 28 02:15:52 PM PDT 24
Finished Apr 28 02:16:10 PM PDT 24
Peak memory 183624 kb
Host smart-19eaeaa9-b097-4822-8ced-397efaf20fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732210650 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.3732210650
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.3049052168
Short name T231
Test name
Test status
Simulation time 510623527 ps
CPU time 1.24 seconds
Started Apr 28 02:15:52 PM PDT 24
Finished Apr 28 02:15:56 PM PDT 24
Peak memory 183600 kb
Host smart-474a613d-6d57-4a99-9692-5c12c6484aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049052168 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.3049052168
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.3684389032
Short name T95
Test name
Test status
Simulation time 91366001897 ps
CPU time 139.71 seconds
Started Apr 28 02:15:52 PM PDT 24
Finished Apr 28 02:18:15 PM PDT 24
Peak memory 194464 kb
Host smart-d5810f46-3b2f-42ef-bb03-c3a3abbb5306
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684389032 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_
all.3684389032
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.3797556328
Short name T82
Test name
Test status
Simulation time 49837079813 ps
CPU time 453.35 seconds
Started Apr 28 02:15:44 PM PDT 24
Finished Apr 28 02:23:21 PM PDT 24
Peak memory 198496 kb
Host smart-96091105-d54c-49b1-a7da-53f00f942b15
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797556328 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand_reset.3797556328
Directory /workspace/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.aon_timer_jump.3284794909
Short name T30
Test name
Test status
Simulation time 427653982 ps
CPU time 0.71 seconds
Started Apr 28 02:15:57 PM PDT 24
Finished Apr 28 02:15:58 PM PDT 24
Peak memory 183556 kb
Host smart-45669289-d854-4bd7-8500-25cb38dba06b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284794909 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.3284794909
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.995867050
Short name T45
Test name
Test status
Simulation time 7562197152 ps
CPU time 10.21 seconds
Started Apr 28 02:15:52 PM PDT 24
Finished Apr 28 02:16:05 PM PDT 24
Peak memory 191776 kb
Host smart-89ff9512-2dc7-4f35-afc8-feb3b65f6f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995867050 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.995867050
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.736205467
Short name T243
Test name
Test status
Simulation time 459582123 ps
CPU time 0.71 seconds
Started Apr 28 02:15:51 PM PDT 24
Finished Apr 28 02:15:55 PM PDT 24
Peak memory 183528 kb
Host smart-fde57720-afe5-4f2c-a3d2-ec53c15764f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736205467 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.736205467
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.448339034
Short name T114
Test name
Test status
Simulation time 307198138975 ps
CPU time 120.04 seconds
Started Apr 28 02:15:48 PM PDT 24
Finished Apr 28 02:17:51 PM PDT 24
Peak memory 183620 kb
Host smart-e72c8cb1-7fed-41d5-9e89-539cb79a38c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448339034 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_a
ll.448339034
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.754225144
Short name T150
Test name
Test status
Simulation time 77257398891 ps
CPU time 831.31 seconds
Started Apr 28 02:15:46 PM PDT 24
Finished Apr 28 02:29:41 PM PDT 24
Peak memory 201764 kb
Host smart-31d106f1-bc06-4e50-8614-06b812fa8eab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754225144 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.754225144
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.aon_timer_jump.912383759
Short name T254
Test name
Test status
Simulation time 596635348 ps
CPU time 0.61 seconds
Started Apr 28 02:15:43 PM PDT 24
Finished Apr 28 02:15:48 PM PDT 24
Peak memory 183508 kb
Host smart-d1f4f2a3-14ea-4e81-bd2d-0cd423108381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912383759 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.912383759
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.2965063509
Short name T9
Test name
Test status
Simulation time 54433450067 ps
CPU time 85.68 seconds
Started Apr 28 02:15:48 PM PDT 24
Finished Apr 28 02:17:17 PM PDT 24
Peak memory 191716 kb
Host smart-2a255fdc-cc22-4137-9e35-f1dfcbd45b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965063509 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.2965063509
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.3846751087
Short name T183
Test name
Test status
Simulation time 463436185 ps
CPU time 1.23 seconds
Started Apr 28 02:16:10 PM PDT 24
Finished Apr 28 02:16:12 PM PDT 24
Peak memory 183600 kb
Host smart-7c3aeb2c-4549-4d76-8ae8-3231fa87fed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846751087 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.3846751087
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.3123895585
Short name T213
Test name
Test status
Simulation time 254529310672 ps
CPU time 74.67 seconds
Started Apr 28 02:15:45 PM PDT 24
Finished Apr 28 02:17:03 PM PDT 24
Peak memory 183616 kb
Host smart-7ce820a1-868e-4409-b5a9-153471cc7038
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123895585 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_
all.3123895585
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.1821075261
Short name T73
Test name
Test status
Simulation time 145139660140 ps
CPU time 401.98 seconds
Started Apr 28 02:16:08 PM PDT 24
Finished Apr 28 02:22:50 PM PDT 24
Peak memory 198452 kb
Host smart-e7d3fde0-cc56-4518-9189-381346faa883
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821075261 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.1821075261
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_jump.2530007283
Short name T262
Test name
Test status
Simulation time 588843089 ps
CPU time 0.76 seconds
Started Apr 28 02:15:49 PM PDT 24
Finished Apr 28 02:15:54 PM PDT 24
Peak memory 183508 kb
Host smart-b61d9292-7701-4f39-95e1-30f1ed4eeb21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530007283 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.2530007283
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.351229191
Short name T166
Test name
Test status
Simulation time 20907084818 ps
CPU time 14.97 seconds
Started Apr 28 02:15:49 PM PDT 24
Finished Apr 28 02:16:07 PM PDT 24
Peak memory 183620 kb
Host smart-1345bd67-017a-4580-ae17-b314cf742764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351229191 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.351229191
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.2203436311
Short name T108
Test name
Test status
Simulation time 383625298 ps
CPU time 0.84 seconds
Started Apr 28 02:15:46 PM PDT 24
Finished Apr 28 02:15:50 PM PDT 24
Peak memory 183580 kb
Host smart-af9826a8-0020-4094-a494-8b27c6963e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203436311 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.2203436311
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.3634950858
Short name T215
Test name
Test status
Simulation time 40694646645 ps
CPU time 55.2 seconds
Started Apr 28 02:15:43 PM PDT 24
Finished Apr 28 02:16:42 PM PDT 24
Peak memory 193976 kb
Host smart-f6b619a3-4ce5-4e10-86ac-0d12cba10c8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634950858 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_
all.3634950858
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.307847376
Short name T257
Test name
Test status
Simulation time 49419156485 ps
CPU time 257.84 seconds
Started Apr 28 02:15:43 PM PDT 24
Finished Apr 28 02:20:05 PM PDT 24
Peak memory 198484 kb
Host smart-c7ad6315-582a-4c93-bc05-c060a415f3ed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307847376 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.307847376
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_jump.1152123309
Short name T139
Test name
Test status
Simulation time 349749513 ps
CPU time 1.03 seconds
Started Apr 28 02:15:51 PM PDT 24
Finished Apr 28 02:15:56 PM PDT 24
Peak memory 183576 kb
Host smart-e65d3e9e-cb26-41c4-b1fa-d4471e6b33d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152123309 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.1152123309
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.2714167439
Short name T269
Test name
Test status
Simulation time 21488352067 ps
CPU time 8.76 seconds
Started Apr 28 02:15:43 PM PDT 24
Finished Apr 28 02:15:55 PM PDT 24
Peak memory 183608 kb
Host smart-8f45110f-6251-4d8a-81bf-d0fa1489b5db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714167439 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.2714167439
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.1339860223
Short name T268
Test name
Test status
Simulation time 602439762 ps
CPU time 1.49 seconds
Started Apr 28 02:15:43 PM PDT 24
Finished Apr 28 02:15:50 PM PDT 24
Peak memory 183580 kb
Host smart-7aafc919-5d7d-4f15-96d7-ed88cb312a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339860223 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.1339860223
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.24809483
Short name T155
Test name
Test status
Simulation time 161280570256 ps
CPU time 59.51 seconds
Started Apr 28 02:15:46 PM PDT 24
Finished Apr 28 02:16:48 PM PDT 24
Peak memory 183576 kb
Host smart-d899daf4-8eb6-4c12-936a-b5657821fc69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24809483 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_al
l.24809483
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.117091464
Short name T93
Test name
Test status
Simulation time 50634550449 ps
CPU time 403.84 seconds
Started Apr 28 02:15:42 PM PDT 24
Finished Apr 28 02:22:28 PM PDT 24
Peak memory 198544 kb
Host smart-df48bb89-edbb-46ee-9e6b-968e8322bfc2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117091464 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.117091464
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.aon_timer_jump.1956332794
Short name T120
Test name
Test status
Simulation time 443565747 ps
CPU time 0.7 seconds
Started Apr 28 02:15:52 PM PDT 24
Finished Apr 28 02:15:56 PM PDT 24
Peak memory 183448 kb
Host smart-7e75de10-c795-4b0e-aa46-134aecc48fcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956332794 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.1956332794
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.1155653853
Short name T27
Test name
Test status
Simulation time 49288221545 ps
CPU time 17.26 seconds
Started Apr 28 02:15:44 PM PDT 24
Finished Apr 28 02:16:05 PM PDT 24
Peak memory 183560 kb
Host smart-39d8534a-200b-4468-bd94-ce797fd72c5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155653853 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.1155653853
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.575108954
Short name T216
Test name
Test status
Simulation time 525003355 ps
CPU time 1.26 seconds
Started Apr 28 02:15:47 PM PDT 24
Finished Apr 28 02:15:52 PM PDT 24
Peak memory 183512 kb
Host smart-428be2be-3f73-4616-a42f-1dc6755375d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575108954 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.575108954
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.1411260054
Short name T219
Test name
Test status
Simulation time 370768282394 ps
CPU time 547.44 seconds
Started Apr 28 02:15:53 PM PDT 24
Finished Apr 28 02:25:03 PM PDT 24
Peak memory 195068 kb
Host smart-0b4df140-153e-4e23-adb5-f2ae99277419
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411260054 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_
all.1411260054
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.2625070694
Short name T233
Test name
Test status
Simulation time 653204174655 ps
CPU time 459.9 seconds
Started Apr 28 02:15:50 PM PDT 24
Finished Apr 28 02:23:33 PM PDT 24
Peak memory 198432 kb
Host smart-73aeee84-49b4-4f37-b412-ecc66435028c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625070694 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.2625070694
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.aon_timer_jump.2713216806
Short name T119
Test name
Test status
Simulation time 608766445 ps
CPU time 0.73 seconds
Started Apr 28 02:15:34 PM PDT 24
Finished Apr 28 02:15:35 PM PDT 24
Peak memory 183576 kb
Host smart-79fece1c-35b5-4650-a0fa-dadaf008ef0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713216806 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.2713216806
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.2617830349
Short name T136
Test name
Test status
Simulation time 25755762984 ps
CPU time 42.47 seconds
Started Apr 28 02:15:39 PM PDT 24
Finished Apr 28 02:16:23 PM PDT 24
Peak memory 183640 kb
Host smart-9ae2ccae-677b-4f38-873b-316b61b74630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617830349 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.2617830349
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.2153539437
Short name T16
Test name
Test status
Simulation time 3718746061 ps
CPU time 6.75 seconds
Started Apr 28 02:15:44 PM PDT 24
Finished Apr 28 02:15:54 PM PDT 24
Peak memory 214932 kb
Host smart-e3822a35-b2df-4d26-a909-cfe4c448f5d3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153539437 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.2153539437
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.4287440129
Short name T22
Test name
Test status
Simulation time 475811339 ps
CPU time 0.9 seconds
Started Apr 28 02:15:43 PM PDT 24
Finished Apr 28 02:15:47 PM PDT 24
Peak memory 183520 kb
Host smart-e64ea70e-f8e8-4779-bcc4-a60467f9f1f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287440129 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.4287440129
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.409470610
Short name T190
Test name
Test status
Simulation time 115096246788 ps
CPU time 88.76 seconds
Started Apr 28 02:15:44 PM PDT 24
Finished Apr 28 02:17:17 PM PDT 24
Peak memory 193328 kb
Host smart-3036e310-0918-4cca-ab0e-89df32ff0e8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409470610 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_al
l.409470610
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.313800682
Short name T41
Test name
Test status
Simulation time 11988654310 ps
CPU time 82.35 seconds
Started Apr 28 02:15:44 PM PDT 24
Finished Apr 28 02:17:11 PM PDT 24
Peak memory 198496 kb
Host smart-fde0aed6-34f3-47a7-afa7-d05b1e279cb0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313800682 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.313800682
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_jump.1390242469
Short name T209
Test name
Test status
Simulation time 667184712 ps
CPU time 0.61 seconds
Started Apr 28 02:15:53 PM PDT 24
Finished Apr 28 02:15:56 PM PDT 24
Peak memory 183512 kb
Host smart-f0876a12-fedc-480d-ae4c-3496d41a02e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390242469 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.1390242469
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.1932529134
Short name T206
Test name
Test status
Simulation time 7191951955 ps
CPU time 2.78 seconds
Started Apr 28 02:16:04 PM PDT 24
Finished Apr 28 02:16:07 PM PDT 24
Peak memory 183624 kb
Host smart-436b3bd8-4c3c-461e-96a7-2234d4ea2b1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932529134 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.1932529134
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.795590663
Short name T212
Test name
Test status
Simulation time 456289070 ps
CPU time 1.32 seconds
Started Apr 28 02:15:54 PM PDT 24
Finished Apr 28 02:15:57 PM PDT 24
Peak memory 183572 kb
Host smart-855d58b2-7b22-443d-b97f-a8676c6ae97e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795590663 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.795590663
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.2121085037
Short name T196
Test name
Test status
Simulation time 569657481235 ps
CPU time 535.6 seconds
Started Apr 28 02:15:49 PM PDT 24
Finished Apr 28 02:24:48 PM PDT 24
Peak memory 198676 kb
Host smart-c5261135-473f-4dcc-8bd2-8f63065f01d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121085037 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.2121085037
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.aon_timer_jump.2340740567
Short name T101
Test name
Test status
Simulation time 480997832 ps
CPU time 1.35 seconds
Started Apr 28 02:15:51 PM PDT 24
Finished Apr 28 02:15:56 PM PDT 24
Peak memory 183552 kb
Host smart-d3e5b377-bdac-4eaa-8a21-099ec5547a45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340740567 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.2340740567
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.3150843707
Short name T230
Test name
Test status
Simulation time 33620229341 ps
CPU time 24.78 seconds
Started Apr 28 02:15:57 PM PDT 24
Finished Apr 28 02:16:23 PM PDT 24
Peak memory 191776 kb
Host smart-48c90f29-59f2-462a-b03a-3237b9cb0f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150843707 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.3150843707
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.3497443977
Short name T23
Test name
Test status
Simulation time 475348707 ps
CPU time 0.72 seconds
Started Apr 28 02:15:55 PM PDT 24
Finished Apr 28 02:15:57 PM PDT 24
Peak memory 183540 kb
Host smart-c66d50a5-792c-4f6e-acbe-a5d9dfe3e468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497443977 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.3497443977
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.563185957
Short name T205
Test name
Test status
Simulation time 34476102150 ps
CPU time 29.08 seconds
Started Apr 28 02:15:49 PM PDT 24
Finished Apr 28 02:16:21 PM PDT 24
Peak memory 183620 kb
Host smart-324379de-7538-4eff-86d7-3c8ec0c5dd1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563185957 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_a
ll.563185957
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/32.aon_timer_jump.577302373
Short name T258
Test name
Test status
Simulation time 509845237 ps
CPU time 0.92 seconds
Started Apr 28 02:15:58 PM PDT 24
Finished Apr 28 02:15:59 PM PDT 24
Peak memory 183516 kb
Host smart-caa91393-29a9-4c7e-b19a-445edf85f6d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577302373 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.577302373
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.2825872189
Short name T116
Test name
Test status
Simulation time 12385983218 ps
CPU time 4.27 seconds
Started Apr 28 02:15:56 PM PDT 24
Finished Apr 28 02:16:01 PM PDT 24
Peak memory 191668 kb
Host smart-b4f36976-16df-4864-a122-1379aa280cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825872189 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.2825872189
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.546858424
Short name T128
Test name
Test status
Simulation time 499916051 ps
CPU time 1.27 seconds
Started Apr 28 02:15:49 PM PDT 24
Finished Apr 28 02:15:57 PM PDT 24
Peak memory 183548 kb
Host smart-150e444d-5cc7-4b3f-8813-f5149012c914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546858424 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.546858424
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.2853875696
Short name T267
Test name
Test status
Simulation time 77060080335 ps
CPU time 112 seconds
Started Apr 28 02:15:51 PM PDT 24
Finished Apr 28 02:17:46 PM PDT 24
Peak memory 194280 kb
Host smart-8a84f52e-fe08-4d15-b292-c038ce13628b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853875696 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_
all.2853875696
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_jump.1559471823
Short name T266
Test name
Test status
Simulation time 581997914 ps
CPU time 0.86 seconds
Started Apr 28 02:16:00 PM PDT 24
Finished Apr 28 02:16:01 PM PDT 24
Peak memory 183556 kb
Host smart-cc17f4a9-45f3-4b1f-bb9b-98f9452a41ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559471823 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.1559471823
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.1207426221
Short name T187
Test name
Test status
Simulation time 33707512003 ps
CPU time 50.12 seconds
Started Apr 28 02:15:57 PM PDT 24
Finished Apr 28 02:16:48 PM PDT 24
Peak memory 183580 kb
Host smart-a82d790f-cc42-4c6a-8250-abb14904b393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207426221 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.1207426221
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.2546976551
Short name T11
Test name
Test status
Simulation time 471135023 ps
CPU time 1.33 seconds
Started Apr 28 02:15:57 PM PDT 24
Finished Apr 28 02:15:59 PM PDT 24
Peak memory 183572 kb
Host smart-2a04f656-3946-4a18-ab1d-93de8a6611d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546976551 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.2546976551
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.495492511
Short name T192
Test name
Test status
Simulation time 176591537381 ps
CPU time 36.51 seconds
Started Apr 28 02:15:52 PM PDT 24
Finished Apr 28 02:16:31 PM PDT 24
Peak memory 195496 kb
Host smart-4ae83ed4-7d58-4b15-9615-25dada81a3a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495492511 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_a
ll.495492511
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.4039004645
Short name T15
Test name
Test status
Simulation time 168817866244 ps
CPU time 433.69 seconds
Started Apr 28 02:15:52 PM PDT 24
Finished Apr 28 02:23:09 PM PDT 24
Peak memory 198484 kb
Host smart-3ff3b35c-2bb0-46bf-bb95-95acf33a6548
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039004645 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.4039004645
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.aon_timer_jump.2442195049
Short name T111
Test name
Test status
Simulation time 579176839 ps
CPU time 0.98 seconds
Started Apr 28 02:16:15 PM PDT 24
Finished Apr 28 02:16:17 PM PDT 24
Peak memory 183540 kb
Host smart-45a30dcc-a21c-4db2-b708-69abbd1ba7f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442195049 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.2442195049
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.3897168744
Short name T191
Test name
Test status
Simulation time 3216262088 ps
CPU time 5.06 seconds
Started Apr 28 02:15:51 PM PDT 24
Finished Apr 28 02:16:00 PM PDT 24
Peak memory 183616 kb
Host smart-779a331d-dfb1-4f5a-a130-b8a7f8284dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897168744 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.3897168744
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.1237008097
Short name T118
Test name
Test status
Simulation time 351895672 ps
CPU time 0.65 seconds
Started Apr 28 02:15:48 PM PDT 24
Finished Apr 28 02:15:52 PM PDT 24
Peak memory 183556 kb
Host smart-e1bf3af7-4492-4c41-a7c6-152dbd26003c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237008097 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.1237008097
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.1896876715
Short name T12
Test name
Test status
Simulation time 29734128392 ps
CPU time 48.01 seconds
Started Apr 28 02:15:48 PM PDT 24
Finished Apr 28 02:16:40 PM PDT 24
Peak memory 183516 kb
Host smart-996369f3-7019-4152-b724-a3cb57eba2f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896876715 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_
all.1896876715
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.1843079276
Short name T203
Test name
Test status
Simulation time 42575783622 ps
CPU time 144.67 seconds
Started Apr 28 02:15:50 PM PDT 24
Finished Apr 28 02:18:18 PM PDT 24
Peak memory 198544 kb
Host smart-75241a2d-8b80-480c-b270-866089381993
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843079276 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.1843079276
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.aon_timer_jump.469925132
Short name T252
Test name
Test status
Simulation time 588485931 ps
CPU time 0.76 seconds
Started Apr 28 02:15:49 PM PDT 24
Finished Apr 28 02:15:53 PM PDT 24
Peak memory 183532 kb
Host smart-138a0fbc-ef26-4817-b785-3e887ad9e4f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469925132 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.469925132
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.2678916130
Short name T142
Test name
Test status
Simulation time 1853860296 ps
CPU time 3.19 seconds
Started Apr 28 02:15:51 PM PDT 24
Finished Apr 28 02:15:57 PM PDT 24
Peak memory 183448 kb
Host smart-b6743203-4442-4ac3-892b-2733486c84cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678916130 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.2678916130
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.2235044182
Short name T67
Test name
Test status
Simulation time 439519849 ps
CPU time 1.27 seconds
Started Apr 28 02:16:13 PM PDT 24
Finished Apr 28 02:16:15 PM PDT 24
Peak memory 183580 kb
Host smart-85fee23c-312d-4134-b059-26b354453510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235044182 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.2235044182
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.3956386406
Short name T146
Test name
Test status
Simulation time 226994304980 ps
CPU time 132.58 seconds
Started Apr 28 02:15:52 PM PDT 24
Finished Apr 28 02:18:08 PM PDT 24
Peak memory 191816 kb
Host smart-bae4d874-0b03-46a9-8c17-9bf46870e456
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956386406 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_
all.3956386406
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.4222906366
Short name T151
Test name
Test status
Simulation time 129439213166 ps
CPU time 800.62 seconds
Started Apr 28 02:15:52 PM PDT 24
Finished Apr 28 02:29:16 PM PDT 24
Peak memory 201468 kb
Host smart-0e6b03ae-e28a-461e-a01c-72a997130351
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222906366 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.4222906366
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.aon_timer_jump.1984095138
Short name T110
Test name
Test status
Simulation time 554363488 ps
CPU time 1.49 seconds
Started Apr 28 02:15:49 PM PDT 24
Finished Apr 28 02:15:54 PM PDT 24
Peak memory 183552 kb
Host smart-ebe5511e-805b-4492-8cd7-b6487c462ff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984095138 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.1984095138
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.3884192671
Short name T124
Test name
Test status
Simulation time 6494193478 ps
CPU time 10.62 seconds
Started Apr 28 02:15:50 PM PDT 24
Finished Apr 28 02:16:04 PM PDT 24
Peak memory 183644 kb
Host smart-8461068e-4c35-46e7-8e22-ab386e2697e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884192671 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.3884192671
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.2226636379
Short name T193
Test name
Test status
Simulation time 415188290 ps
CPU time 0.86 seconds
Started Apr 28 02:15:49 PM PDT 24
Finished Apr 28 02:15:53 PM PDT 24
Peak memory 183460 kb
Host smart-e04b88ec-4c35-49bd-aff5-9c16aff92d0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226636379 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.2226636379
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.2994528889
Short name T132
Test name
Test status
Simulation time 84255455293 ps
CPU time 133.22 seconds
Started Apr 28 02:16:11 PM PDT 24
Finished Apr 28 02:18:25 PM PDT 24
Peak memory 183628 kb
Host smart-0fa267a4-2b7d-452e-a882-b1a062f8c529
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994528889 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_
all.2994528889
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.1030445462
Short name T143
Test name
Test status
Simulation time 40664536746 ps
CPU time 407.51 seconds
Started Apr 28 02:15:54 PM PDT 24
Finished Apr 28 02:22:44 PM PDT 24
Peak memory 198560 kb
Host smart-c005548c-9ba2-40e9-855f-c2f9a7f128aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030445462 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.1030445462
Directory /workspace/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.aon_timer_jump.1848415369
Short name T156
Test name
Test status
Simulation time 400007499 ps
CPU time 0.68 seconds
Started Apr 28 02:16:00 PM PDT 24
Finished Apr 28 02:16:01 PM PDT 24
Peak memory 183464 kb
Host smart-67e0021e-10f7-43a6-9c1d-12780d834ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848415369 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.1848415369
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.3427785601
Short name T148
Test name
Test status
Simulation time 23747668953 ps
CPU time 11.48 seconds
Started Apr 28 02:15:58 PM PDT 24
Finished Apr 28 02:16:10 PM PDT 24
Peak memory 183576 kb
Host smart-819a689f-8623-4cea-ab67-e33e0e938b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427785601 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.3427785601
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.407263282
Short name T29
Test name
Test status
Simulation time 576781661 ps
CPU time 1.03 seconds
Started Apr 28 02:15:58 PM PDT 24
Finished Apr 28 02:15:59 PM PDT 24
Peak memory 183516 kb
Host smart-92716b9a-7c12-4470-8099-dff916332d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407263282 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.407263282
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.2875945278
Short name T260
Test name
Test status
Simulation time 105345542448 ps
CPU time 177.2 seconds
Started Apr 28 02:15:47 PM PDT 24
Finished Apr 28 02:18:48 PM PDT 24
Peak memory 193704 kb
Host smart-5f4557a2-c002-4890-a304-705499fb777d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875945278 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_
all.2875945278
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.3106058016
Short name T135
Test name
Test status
Simulation time 198621232132 ps
CPU time 584.7 seconds
Started Apr 28 02:15:50 PM PDT 24
Finished Apr 28 02:25:41 PM PDT 24
Peak memory 214612 kb
Host smart-b645c3b4-0803-433a-a331-f3689d424b6d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106058016 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.3106058016
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.aon_timer_jump.1513738938
Short name T115
Test name
Test status
Simulation time 481795744 ps
CPU time 1.27 seconds
Started Apr 28 02:15:49 PM PDT 24
Finished Apr 28 02:15:57 PM PDT 24
Peak memory 183520 kb
Host smart-2cd4efed-84bd-4448-b97e-ded085a8929a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513738938 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.1513738938
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.2366028664
Short name T68
Test name
Test status
Simulation time 35690872798 ps
CPU time 9.57 seconds
Started Apr 28 02:15:49 PM PDT 24
Finished Apr 28 02:16:02 PM PDT 24
Peak memory 183616 kb
Host smart-246b114f-b8e9-403f-b163-668c0c069a99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366028664 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.2366028664
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.50290437
Short name T256
Test name
Test status
Simulation time 584014900 ps
CPU time 0.75 seconds
Started Apr 28 02:15:53 PM PDT 24
Finished Apr 28 02:15:56 PM PDT 24
Peak memory 183572 kb
Host smart-56310fa0-675f-4ab4-a214-a3991221260a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50290437 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.50290437
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.704791462
Short name T160
Test name
Test status
Simulation time 81376745969 ps
CPU time 19.75 seconds
Started Apr 28 02:16:09 PM PDT 24
Finished Apr 28 02:16:29 PM PDT 24
Peak memory 193112 kb
Host smart-23bac6ee-35bb-49ac-b0e3-cfe07d129c12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704791462 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_a
ll.704791462
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_jump.1423659559
Short name T141
Test name
Test status
Simulation time 474614341 ps
CPU time 0.66 seconds
Started Apr 28 02:16:05 PM PDT 24
Finished Apr 28 02:16:05 PM PDT 24
Peak memory 183572 kb
Host smart-36299aaa-80ab-41ae-a7d5-d9b3474a502f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423659559 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.1423659559
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.899497781
Short name T147
Test name
Test status
Simulation time 15071897857 ps
CPU time 10.48 seconds
Started Apr 28 02:15:52 PM PDT 24
Finished Apr 28 02:16:05 PM PDT 24
Peak memory 183460 kb
Host smart-fdd611ef-f78e-4253-886c-d826c6830551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899497781 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.899497781
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.1773531303
Short name T149
Test name
Test status
Simulation time 419614406 ps
CPU time 1.18 seconds
Started Apr 28 02:15:49 PM PDT 24
Finished Apr 28 02:15:53 PM PDT 24
Peak memory 183544 kb
Host smart-eb551ee4-2d8b-425b-a957-62e067608b58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773531303 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.1773531303
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.1694476793
Short name T90
Test name
Test status
Simulation time 224518138440 ps
CPU time 374.1 seconds
Started Apr 28 02:15:53 PM PDT 24
Finished Apr 28 02:22:10 PM PDT 24
Peak memory 195260 kb
Host smart-a765b1d2-859c-4e0a-953d-6a6d2ed4a033
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694476793 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_
all.1694476793
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.2476108860
Short name T171
Test name
Test status
Simulation time 32445744772 ps
CPU time 242.34 seconds
Started Apr 28 02:15:53 PM PDT 24
Finished Apr 28 02:19:58 PM PDT 24
Peak memory 198524 kb
Host smart-b0ea294b-c4ab-4663-a08a-7b4b1822dc3f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476108860 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.2476108860
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_jump.2525215752
Short name T123
Test name
Test status
Simulation time 550856596 ps
CPU time 1 seconds
Started Apr 28 02:15:30 PM PDT 24
Finished Apr 28 02:15:32 PM PDT 24
Peak memory 183548 kb
Host smart-03c71f54-255c-438a-99fe-b50393e277b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525215752 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.2525215752
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.2402896918
Short name T127
Test name
Test status
Simulation time 5488731871 ps
CPU time 9.59 seconds
Started Apr 28 02:15:40 PM PDT 24
Finished Apr 28 02:15:50 PM PDT 24
Peak memory 183644 kb
Host smart-3258ef8f-a60a-4f2a-a4c1-210fc4d11cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402896918 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.2402896918
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.3385881981
Short name T17
Test name
Test status
Simulation time 7840209438 ps
CPU time 6.15 seconds
Started Apr 28 02:15:43 PM PDT 24
Finished Apr 28 02:15:52 PM PDT 24
Peak memory 215300 kb
Host smart-4bdd416f-f0b1-46c5-a58a-7485bce8c5fc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385881981 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.3385881981
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.139649655
Short name T225
Test name
Test status
Simulation time 474678593 ps
CPU time 0.71 seconds
Started Apr 28 02:15:36 PM PDT 24
Finished Apr 28 02:15:37 PM PDT 24
Peak memory 183552 kb
Host smart-6dcd2d42-e150-495c-b94c-b227a4e26649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139649655 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.139649655
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.2736933727
Short name T185
Test name
Test status
Simulation time 52946501009 ps
CPU time 21.49 seconds
Started Apr 28 02:15:39 PM PDT 24
Finished Apr 28 02:16:01 PM PDT 24
Peak memory 183620 kb
Host smart-2bd1568d-5793-4c91-bdb1-30581a126df3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736933727 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_a
ll.2736933727
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.2677083038
Short name T198
Test name
Test status
Simulation time 80812610344 ps
CPU time 690.2 seconds
Started Apr 28 02:15:46 PM PDT 24
Finished Apr 28 02:27:20 PM PDT 24
Peak memory 208784 kb
Host smart-c4bff546-a7ce-47f0-822e-36eb4c165da7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677083038 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.2677083038
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.aon_timer_jump.1015663404
Short name T186
Test name
Test status
Simulation time 582085001 ps
CPU time 0.78 seconds
Started Apr 28 02:15:54 PM PDT 24
Finished Apr 28 02:16:02 PM PDT 24
Peak memory 183516 kb
Host smart-2013553a-c525-4380-9e5e-e7c5b7a89833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015663404 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.1015663404
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.1518678284
Short name T91
Test name
Test status
Simulation time 29535003867 ps
CPU time 20.36 seconds
Started Apr 28 02:16:03 PM PDT 24
Finished Apr 28 02:16:24 PM PDT 24
Peak memory 183600 kb
Host smart-d511c8ce-1d62-4482-9b1b-718f3678c844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518678284 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.1518678284
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.1525877693
Short name T247
Test name
Test status
Simulation time 530999064 ps
CPU time 0.74 seconds
Started Apr 28 02:16:06 PM PDT 24
Finished Apr 28 02:16:07 PM PDT 24
Peak memory 183572 kb
Host smart-2fe8c3a5-2523-49c1-98ed-5cfa8345d60f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525877693 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.1525877693
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.2719191264
Short name T38
Test name
Test status
Simulation time 23783628158 ps
CPU time 80.73 seconds
Started Apr 28 02:16:00 PM PDT 24
Finished Apr 28 02:17:21 PM PDT 24
Peak memory 198484 kb
Host smart-6ce0b3a1-7f8e-4930-b356-b8964833189b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719191264 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.2719191264
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.aon_timer_jump.3971342058
Short name T182
Test name
Test status
Simulation time 585919053 ps
CPU time 0.7 seconds
Started Apr 28 02:15:57 PM PDT 24
Finished Apr 28 02:15:58 PM PDT 24
Peak memory 183408 kb
Host smart-01fa015e-555b-41ec-8f60-cef0da97ba0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971342058 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.3971342058
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.945315401
Short name T210
Test name
Test status
Simulation time 39463847009 ps
CPU time 12.74 seconds
Started Apr 28 02:15:53 PM PDT 24
Finished Apr 28 02:16:08 PM PDT 24
Peak memory 183556 kb
Host smart-049d0d08-8206-4170-8a2f-1f6a5398822b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945315401 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.945315401
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.1578757374
Short name T158
Test name
Test status
Simulation time 439746262 ps
CPU time 0.72 seconds
Started Apr 28 02:15:52 PM PDT 24
Finished Apr 28 02:15:56 PM PDT 24
Peak memory 183536 kb
Host smart-6d386509-d7ae-406a-ad3c-97646bc13451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578757374 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.1578757374
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.2476255745
Short name T232
Test name
Test status
Simulation time 340916774164 ps
CPU time 152.05 seconds
Started Apr 28 02:16:07 PM PDT 24
Finished Apr 28 02:18:40 PM PDT 24
Peak memory 195160 kb
Host smart-6a78f57c-7b07-4c19-99f5-57938b916616
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476255745 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_
all.2476255745
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.3816325175
Short name T84
Test name
Test status
Simulation time 553881793731 ps
CPU time 268.18 seconds
Started Apr 28 02:15:54 PM PDT 24
Finished Apr 28 02:20:24 PM PDT 24
Peak memory 198504 kb
Host smart-2466662e-8186-44e0-ae05-b52de993ac8e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816325175 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.3816325175
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.aon_timer_jump.2043059918
Short name T195
Test name
Test status
Simulation time 608076357 ps
CPU time 0.78 seconds
Started Apr 28 02:15:55 PM PDT 24
Finished Apr 28 02:15:57 PM PDT 24
Peak memory 183448 kb
Host smart-1901dc87-240a-42b5-8894-4591ea1de434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043059918 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.2043059918
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.1750110887
Short name T176
Test name
Test status
Simulation time 49974272167 ps
CPU time 42.23 seconds
Started Apr 28 02:15:51 PM PDT 24
Finished Apr 28 02:16:37 PM PDT 24
Peak memory 183628 kb
Host smart-98d2eb19-46f0-4d26-957d-200d1bc8cb89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750110887 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.1750110887
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.1075049095
Short name T228
Test name
Test status
Simulation time 513864198 ps
CPU time 0.75 seconds
Started Apr 28 02:16:08 PM PDT 24
Finished Apr 28 02:16:09 PM PDT 24
Peak memory 183516 kb
Host smart-8d7cfa3c-3551-41f6-81ab-0eb3a4f61441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075049095 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.1075049095
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.446187873
Short name T51
Test name
Test status
Simulation time 120528736901 ps
CPU time 600.54 seconds
Started Apr 28 02:16:10 PM PDT 24
Finished Apr 28 02:26:11 PM PDT 24
Peak memory 206728 kb
Host smart-c8efada6-4afc-45b6-adda-7caceb279967
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446187873 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.446187873
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.aon_timer_jump.4289053376
Short name T131
Test name
Test status
Simulation time 403917435 ps
CPU time 0.7 seconds
Started Apr 28 02:15:53 PM PDT 24
Finished Apr 28 02:15:56 PM PDT 24
Peak memory 183508 kb
Host smart-cfd348e6-e6c0-4107-ac4f-870da396bc07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289053376 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.4289053376
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.2827506112
Short name T239
Test name
Test status
Simulation time 59029857152 ps
CPU time 11.98 seconds
Started Apr 28 02:15:59 PM PDT 24
Finished Apr 28 02:16:12 PM PDT 24
Peak memory 183608 kb
Host smart-6b22b7f9-6ac3-497b-80c1-eb32ddc42d17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827506112 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.2827506112
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.4170929288
Short name T263
Test name
Test status
Simulation time 361729323 ps
CPU time 0.81 seconds
Started Apr 28 02:16:16 PM PDT 24
Finished Apr 28 02:16:18 PM PDT 24
Peak memory 183536 kb
Host smart-8ab8cd44-0fd2-4aa1-9bf9-5748e852864f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170929288 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.4170929288
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.2614589428
Short name T133
Test name
Test status
Simulation time 78574132659 ps
CPU time 126.72 seconds
Started Apr 28 02:16:04 PM PDT 24
Finished Apr 28 02:18:11 PM PDT 24
Peak memory 195296 kb
Host smart-8e0ff39a-6bd9-4aae-a5fe-ce3172828f11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614589428 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_
all.2614589428
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.2594088114
Short name T261
Test name
Test status
Simulation time 1049309399619 ps
CPU time 1514.78 seconds
Started Apr 28 02:15:55 PM PDT 24
Finished Apr 28 02:41:11 PM PDT 24
Peak memory 211064 kb
Host smart-0cdcbcdf-fb69-4677-bbbe-cfc05f299ed3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594088114 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.2594088114
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.aon_timer_jump.2328573836
Short name T162
Test name
Test status
Simulation time 461952777 ps
CPU time 0.95 seconds
Started Apr 28 02:16:17 PM PDT 24
Finished Apr 28 02:16:19 PM PDT 24
Peak memory 183576 kb
Host smart-7480c29e-1c8a-4128-94b6-747bca6846f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328573836 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.2328573836
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.3550538031
Short name T122
Test name
Test status
Simulation time 41940411527 ps
CPU time 32.36 seconds
Started Apr 28 02:15:54 PM PDT 24
Finished Apr 28 02:16:28 PM PDT 24
Peak memory 183632 kb
Host smart-d72c31d4-be54-4067-9766-d70552689aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550538031 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.3550538031
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.113733665
Short name T8
Test name
Test status
Simulation time 482576401 ps
CPU time 0.91 seconds
Started Apr 28 02:15:55 PM PDT 24
Finished Apr 28 02:15:57 PM PDT 24
Peak memory 183524 kb
Host smart-3c6d0459-97a5-41aa-b8bc-5f5c62c39cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113733665 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.113733665
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.340017258
Short name T113
Test name
Test status
Simulation time 110344219265 ps
CPU time 86.13 seconds
Started Apr 28 02:16:00 PM PDT 24
Finished Apr 28 02:17:27 PM PDT 24
Peak memory 183572 kb
Host smart-e3d28b3b-814b-422c-ba1e-a3631d2cc5fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340017258 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_a
ll.340017258
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.2197879733
Short name T69
Test name
Test status
Simulation time 29284313671 ps
CPU time 40.38 seconds
Started Apr 28 02:15:54 PM PDT 24
Finished Apr 28 02:16:36 PM PDT 24
Peak memory 198436 kb
Host smart-69603c8d-ef78-4b7e-980d-bceffb6faebf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197879733 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.2197879733
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.aon_timer_jump.1072953773
Short name T197
Test name
Test status
Simulation time 577655324 ps
CPU time 0.96 seconds
Started Apr 28 02:15:53 PM PDT 24
Finished Apr 28 02:15:57 PM PDT 24
Peak memory 183568 kb
Host smart-e1a68398-9cf1-466d-9f5a-9fb99f8fa897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072953773 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.1072953773
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.4185817211
Short name T3
Test name
Test status
Simulation time 21244638179 ps
CPU time 9.61 seconds
Started Apr 28 02:16:02 PM PDT 24
Finished Apr 28 02:16:12 PM PDT 24
Peak memory 191808 kb
Host smart-fc720c24-0f42-486c-8e63-de47b351dde5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185817211 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.4185817211
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.1174859383
Short name T25
Test name
Test status
Simulation time 578740423 ps
CPU time 0.76 seconds
Started Apr 28 02:16:00 PM PDT 24
Finished Apr 28 02:16:02 PM PDT 24
Peak memory 183556 kb
Host smart-3af41302-b633-4806-a32c-f9e443df9e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174859383 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.1174859383
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.3335834581
Short name T96
Test name
Test status
Simulation time 120497010729 ps
CPU time 182.03 seconds
Started Apr 28 02:15:58 PM PDT 24
Finished Apr 28 02:19:00 PM PDT 24
Peak memory 183580 kb
Host smart-3669d27c-b2d1-4ed6-b85f-6824feca8bef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335834581 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_
all.3335834581
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/46.aon_timer_jump.4167472029
Short name T137
Test name
Test status
Simulation time 463340852 ps
CPU time 1.15 seconds
Started Apr 28 02:16:10 PM PDT 24
Finished Apr 28 02:16:11 PM PDT 24
Peak memory 183448 kb
Host smart-abfea2f1-96d9-4f52-b866-e61affa64415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167472029 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.4167472029
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.2861017171
Short name T179
Test name
Test status
Simulation time 23461175712 ps
CPU time 39.24 seconds
Started Apr 28 02:15:53 PM PDT 24
Finished Apr 28 02:16:35 PM PDT 24
Peak memory 191768 kb
Host smart-69799413-e944-48af-89fa-1d7ff80cd409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861017171 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.2861017171
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.255770595
Short name T134
Test name
Test status
Simulation time 390805438 ps
CPU time 1.23 seconds
Started Apr 28 02:16:14 PM PDT 24
Finished Apr 28 02:16:16 PM PDT 24
Peak memory 183584 kb
Host smart-5b7c2fbf-6ab6-4a92-9306-705b2c301023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255770595 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.255770595
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.378786117
Short name T24
Test name
Test status
Simulation time 96465702581 ps
CPU time 196.65 seconds
Started Apr 28 02:16:10 PM PDT 24
Finished Apr 28 02:19:27 PM PDT 24
Peak memory 198560 kb
Host smart-ed63afd1-da1b-4963-ae88-83e9a2d8adf1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378786117 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.378786117
Directory /workspace/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.aon_timer_jump.1212549690
Short name T130
Test name
Test status
Simulation time 537236193 ps
CPU time 0.99 seconds
Started Apr 28 02:16:03 PM PDT 24
Finished Apr 28 02:16:04 PM PDT 24
Peak memory 183560 kb
Host smart-726b4d48-25bf-4a5d-b898-dcb0de938f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212549690 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.1212549690
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.2369815001
Short name T250
Test name
Test status
Simulation time 28534209846 ps
CPU time 11.58 seconds
Started Apr 28 02:16:06 PM PDT 24
Finished Apr 28 02:16:18 PM PDT 24
Peak memory 183576 kb
Host smart-6a7daff6-44e6-47d8-9eb0-7d64f9ad913a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369815001 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.2369815001
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.3010018338
Short name T165
Test name
Test status
Simulation time 361153287 ps
CPU time 0.72 seconds
Started Apr 28 02:16:15 PM PDT 24
Finished Apr 28 02:16:17 PM PDT 24
Peak memory 183592 kb
Host smart-1a9512c1-df15-4f81-a00f-00973ec3fde3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010018338 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.3010018338
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.2306985789
Short name T49
Test name
Test status
Simulation time 339860448139 ps
CPU time 307.97 seconds
Started Apr 28 02:16:04 PM PDT 24
Finished Apr 28 02:21:12 PM PDT 24
Peak memory 195240 kb
Host smart-5601977e-8455-47e9-9bd7-d3852d84865a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306985789 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_
all.2306985789
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.2683729425
Short name T70
Test name
Test status
Simulation time 72563983593 ps
CPU time 746.09 seconds
Started Apr 28 02:16:05 PM PDT 24
Finished Apr 28 02:28:32 PM PDT 24
Peak memory 201152 kb
Host smart-f0758a05-e150-409a-bf8b-10620c5ef4d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683729425 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.2683729425
Directory /workspace/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_jump.3106438041
Short name T235
Test name
Test status
Simulation time 614855016 ps
CPU time 0.79 seconds
Started Apr 28 02:16:15 PM PDT 24
Finished Apr 28 02:16:17 PM PDT 24
Peak memory 183448 kb
Host smart-11565679-95e7-453d-81bd-b9d08b07a4a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106438041 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.3106438041
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.2612350293
Short name T172
Test name
Test status
Simulation time 32465216367 ps
CPU time 12.59 seconds
Started Apr 28 02:16:04 PM PDT 24
Finished Apr 28 02:16:17 PM PDT 24
Peak memory 183616 kb
Host smart-add8de5c-6038-430f-b37b-3c0d5ac209a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612350293 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.2612350293
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.1436424133
Short name T168
Test name
Test status
Simulation time 580525867 ps
CPU time 1.45 seconds
Started Apr 28 02:16:19 PM PDT 24
Finished Apr 28 02:16:21 PM PDT 24
Peak memory 183572 kb
Host smart-68f27e7a-cffd-4b0f-bbe2-355d03c39bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436424133 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.1436424133
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.1322709315
Short name T89
Test name
Test status
Simulation time 184214417927 ps
CPU time 22.12 seconds
Started Apr 28 02:16:06 PM PDT 24
Finished Apr 28 02:16:28 PM PDT 24
Peak memory 191808 kb
Host smart-d648b680-2200-4745-a7ac-60fef7274b47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322709315 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_
all.1322709315
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.4216699409
Short name T39
Test name
Test status
Simulation time 78297651256 ps
CPU time 177.64 seconds
Started Apr 28 02:16:06 PM PDT 24
Finished Apr 28 02:19:04 PM PDT 24
Peak memory 198436 kb
Host smart-708a6a73-dd75-4550-8d98-2c663997a32b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216699409 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.4216699409
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.aon_timer_jump.2507669768
Short name T271
Test name
Test status
Simulation time 448827453 ps
CPU time 1.13 seconds
Started Apr 28 02:15:58 PM PDT 24
Finished Apr 28 02:16:00 PM PDT 24
Peak memory 183500 kb
Host smart-8efe04ea-2463-4516-95fc-53c8856e6ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507669768 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.2507669768
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.1415410772
Short name T264
Test name
Test status
Simulation time 3125155444 ps
CPU time 1.69 seconds
Started Apr 28 02:16:09 PM PDT 24
Finished Apr 28 02:16:11 PM PDT 24
Peak memory 183556 kb
Host smart-b46aa1ee-9b84-4d62-a865-ab9a56f7ad7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415410772 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.1415410772
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.3536431856
Short name T177
Test name
Test status
Simulation time 427236828 ps
CPU time 0.77 seconds
Started Apr 28 02:16:11 PM PDT 24
Finished Apr 28 02:16:13 PM PDT 24
Peak memory 183516 kb
Host smart-192736d9-9d03-4468-b323-6932fa5db6b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536431856 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.3536431856
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.756632306
Short name T50
Test name
Test status
Simulation time 34916692961 ps
CPU time 40.11 seconds
Started Apr 28 02:16:14 PM PDT 24
Finished Apr 28 02:16:55 PM PDT 24
Peak memory 183444 kb
Host smart-1e0a4e27-0223-4163-b9e6-f2cb9d4527c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756632306 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_a
ll.756632306
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.502667205
Short name T13
Test name
Test status
Simulation time 34093730687 ps
CPU time 264.3 seconds
Started Apr 28 02:16:05 PM PDT 24
Finished Apr 28 02:20:30 PM PDT 24
Peak memory 198492 kb
Host smart-442c64e4-44c0-43ef-8a11-3f09c1391798
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502667205 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.502667205
Directory /workspace/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.aon_timer_jump.3662125910
Short name T226
Test name
Test status
Simulation time 384879766 ps
CPU time 0.65 seconds
Started Apr 28 02:15:33 PM PDT 24
Finished Apr 28 02:15:34 PM PDT 24
Peak memory 183540 kb
Host smart-34b56cc0-5346-4bd3-9e0a-f0e606913aab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662125910 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.3662125910
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.3072094944
Short name T242
Test name
Test status
Simulation time 36971754094 ps
CPU time 58.65 seconds
Started Apr 28 02:15:31 PM PDT 24
Finished Apr 28 02:16:30 PM PDT 24
Peak memory 191776 kb
Host smart-3415e9b4-490b-40d3-a5eb-6c69271799b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072094944 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.3072094944
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.2251258876
Short name T167
Test name
Test status
Simulation time 408093949 ps
CPU time 0.59 seconds
Started Apr 28 02:15:34 PM PDT 24
Finished Apr 28 02:15:35 PM PDT 24
Peak memory 183528 kb
Host smart-e40d0be0-3b93-44c3-b12a-7f880dc8a82c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251258876 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.2251258876
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.2005320618
Short name T246
Test name
Test status
Simulation time 53962035762 ps
CPU time 91.16 seconds
Started Apr 28 02:15:38 PM PDT 24
Finished Apr 28 02:17:10 PM PDT 24
Peak memory 194292 kb
Host smart-e877b6a3-78d6-41b2-8158-b145b8d02d15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005320618 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_a
ll.2005320618
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_jump.3227807577
Short name T214
Test name
Test status
Simulation time 478756837 ps
CPU time 1.17 seconds
Started Apr 28 02:15:39 PM PDT 24
Finished Apr 28 02:15:41 PM PDT 24
Peak memory 183548 kb
Host smart-0b10371e-84ea-4d22-9e88-2d3b5fb876a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227807577 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.3227807577
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.2499817863
Short name T5
Test name
Test status
Simulation time 59864732024 ps
CPU time 91.51 seconds
Started Apr 28 02:15:32 PM PDT 24
Finished Apr 28 02:17:04 PM PDT 24
Peak memory 183644 kb
Host smart-18a1a080-30a9-4872-a265-7f84bb51cb4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499817863 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.2499817863
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.3453625445
Short name T138
Test name
Test status
Simulation time 581830605 ps
CPU time 0.82 seconds
Started Apr 28 02:15:40 PM PDT 24
Finished Apr 28 02:15:41 PM PDT 24
Peak memory 183508 kb
Host smart-bc20995d-932b-4bac-9288-b1deb8ab12cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453625445 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.3453625445
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.4103918405
Short name T88
Test name
Test status
Simulation time 168336799548 ps
CPU time 74.79 seconds
Started Apr 28 02:15:42 PM PDT 24
Finished Apr 28 02:16:58 PM PDT 24
Peak memory 194152 kb
Host smart-4253aff6-83fb-40b3-90eb-07f36177f0c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103918405 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_a
ll.4103918405
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.1049679453
Short name T52
Test name
Test status
Simulation time 190540300350 ps
CPU time 893.71 seconds
Started Apr 28 02:15:32 PM PDT 24
Finished Apr 28 02:30:26 PM PDT 24
Peak memory 204080 kb
Host smart-7a41655a-8358-45c4-8fab-e85f3e020639
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049679453 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.1049679453
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.aon_timer_jump.2208453087
Short name T164
Test name
Test status
Simulation time 671196855 ps
CPU time 0.61 seconds
Started Apr 28 02:15:44 PM PDT 24
Finished Apr 28 02:15:48 PM PDT 24
Peak memory 183508 kb
Host smart-7bed4d76-c5a2-4439-933c-68a60edcff1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208453087 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.2208453087
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.2739441757
Short name T47
Test name
Test status
Simulation time 45045160019 ps
CPU time 64.16 seconds
Started Apr 28 02:15:33 PM PDT 24
Finished Apr 28 02:16:38 PM PDT 24
Peak memory 191796 kb
Host smart-3ddbfcee-e42b-4ff8-ba19-b7053571d310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739441757 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.2739441757
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.1501049047
Short name T72
Test name
Test status
Simulation time 333610695 ps
CPU time 0.91 seconds
Started Apr 28 02:15:38 PM PDT 24
Finished Apr 28 02:15:39 PM PDT 24
Peak memory 183568 kb
Host smart-386bf18d-377f-4d6f-8b80-82644aa42c70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501049047 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.1501049047
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.3295621019
Short name T170
Test name
Test status
Simulation time 43876511718 ps
CPU time 18.99 seconds
Started Apr 28 02:15:43 PM PDT 24
Finished Apr 28 02:16:05 PM PDT 24
Peak memory 183528 kb
Host smart-18b68886-281d-4a01-ab51-68a5b2e14951
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295621019 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_a
ll.3295621019
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.3757736545
Short name T202
Test name
Test status
Simulation time 146292051528 ps
CPU time 267.57 seconds
Started Apr 28 02:15:34 PM PDT 24
Finished Apr 28 02:20:02 PM PDT 24
Peak memory 198476 kb
Host smart-51875d33-2f8d-4649-8a1e-97fab1acdeeb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757736545 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.3757736545
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.aon_timer_jump.1514873663
Short name T104
Test name
Test status
Simulation time 342284994 ps
CPU time 1.03 seconds
Started Apr 28 02:15:44 PM PDT 24
Finished Apr 28 02:15:48 PM PDT 24
Peak memory 183404 kb
Host smart-741fa1f2-a65a-4730-9cf5-a016c048cc47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514873663 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.1514873663
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.3910978400
Short name T152
Test name
Test status
Simulation time 8046913117 ps
CPU time 12.97 seconds
Started Apr 28 02:15:31 PM PDT 24
Finished Apr 28 02:15:45 PM PDT 24
Peak memory 183636 kb
Host smart-bea1bc9b-d3f7-4f7f-945c-1e3dd38cff07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910978400 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.3910978400
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.2739339323
Short name T71
Test name
Test status
Simulation time 392994500 ps
CPU time 1.12 seconds
Started Apr 28 02:15:31 PM PDT 24
Finished Apr 28 02:15:32 PM PDT 24
Peak memory 183536 kb
Host smart-c27a00da-031f-4f38-8e58-c5d9f4d0ba66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739339323 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.2739339323
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.24893344
Short name T31
Test name
Test status
Simulation time 44943911687 ps
CPU time 88.2 seconds
Started Apr 28 02:15:49 PM PDT 24
Finished Apr 28 02:17:21 PM PDT 24
Peak memory 198364 kb
Host smart-3a44be04-fc38-4f03-ae74-7008637fe1b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24893344 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.24893344
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.aon_timer_jump.1985269235
Short name T194
Test name
Test status
Simulation time 669185740 ps
CPU time 0.59 seconds
Started Apr 28 02:15:39 PM PDT 24
Finished Apr 28 02:15:41 PM PDT 24
Peak memory 183564 kb
Host smart-6bcb557b-6c27-438c-baff-e86a9857e107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985269235 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.1985269235
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.3526918390
Short name T200
Test name
Test status
Simulation time 16819344356 ps
CPU time 7.44 seconds
Started Apr 28 02:15:42 PM PDT 24
Finished Apr 28 02:15:53 PM PDT 24
Peak memory 191816 kb
Host smart-d2c21864-8803-49a6-a36f-1f3df74c0455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526918390 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.3526918390
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.962668746
Short name T201
Test name
Test status
Simulation time 428407581 ps
CPU time 1.17 seconds
Started Apr 28 02:15:44 PM PDT 24
Finished Apr 28 02:15:48 PM PDT 24
Peak memory 183556 kb
Host smart-bb0c2eb4-8045-4da0-80d6-818a37080471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962668746 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.962668746
Directory /workspace/9.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.206778297
Short name T249
Test name
Test status
Simulation time 54109434915 ps
CPU time 80.28 seconds
Started Apr 28 02:15:44 PM PDT 24
Finished Apr 28 02:17:08 PM PDT 24
Peak memory 183596 kb
Host smart-9a2db6cf-0506-407f-b016-8a6dafe15149
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206778297 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_al
l.206778297
Directory /workspace/9.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.3550852163
Short name T81
Test name
Test status
Simulation time 66096747543 ps
CPU time 654.65 seconds
Started Apr 28 02:15:42 PM PDT 24
Finished Apr 28 02:26:39 PM PDT 24
Peak memory 199808 kb
Host smart-a0852714-2af7-4a8f-95a5-ab3e982d52cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550852163 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.3550852163
Directory /workspace/9.aon_timer_stress_all_with_rand_reset/latest
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