Unified Coverage Report :: Group :: aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
24.86	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv

---

Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	173	130	43	24.86

Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
bark_thold_cp	34	32	2	5.88	100	1	1	0
bite_thold_cp	34	32	2	5.88	100	1	1	0
pause_in_sleep_cp	2	1	1	50.00	100	1	1	2
prescale_cp	34	1	33	97.06	100	1	1	0
wdog_regwen_cp	2	0	2	100.00	100	1	1	2
wkup_cause_cp	1	0	1	100.00	100	1	1	0
wkup_thold_cp	66	64	2	3.03	100	1	1	0

Summary for Variable bark_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	32	2	5.88

User Defined Bins for bark_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bark_max	0	1	1
bark[1]	0	1	1
bark[2]	0	1	1
bark[3]	0	1	1
bark[4]	0	1	1
bark[5]	0	1	1
bark[6]	0	1	1
bark[7]	0	1	1
bark[8]	0	1	1
bark[9]	0	1	1
bark[10]	0	1	1
bark[11]	0	1	1
bark[12]	0	1	1
bark[13]	0	1	1
bark[14]	0	1	1
bark[15]	0	1	1
bark[16]	0	1	1
bark[17]	0	1	1
bark[18]	0	1	1
bark[19]	0	1	1
bark[20]	0	1	1
bark[21]	0	1	1
bark[22]	0	1	1
bark[23]	0	1	1
bark[24]	0	1	1
bark[25]	0	1	1
bark[26]	0	1	1
bark[27]	0	1	1
bark[28]	0	1	1
bark[29]	0	1	1
bark[30]	0	1	1
bark[31]	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bark[0]	55820	1		T1	627		T2	14		T3	14
bark_0	4868	1		T1	35		T2	7		T3	7

---

Summary for Variable bite_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	32	2	5.88

User Defined Bins for bite_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bite_max	0	1	1
bite[1]	0	1	1
bite[2]	0	1	1
bite[3]	0	1	1
bite[4]	0	1	1
bite[5]	0	1	1
bite[6]	0	1	1
bite[7]	0	1	1
bite[8]	0	1	1
bite[9]	0	1	1
bite[10]	0	1	1
bite[11]	0	1	1
bite[12]	0	1	1
bite[13]	0	1	1
bite[14]	0	1	1
bite[15]	0	1	1
bite[16]	0	1	1
bite[17]	0	1	1
bite[18]	0	1	1
bite[19]	0	1	1
bite[20]	0	1	1
bite[21]	0	1	1
bite[22]	0	1	1
bite[23]	0	1	1
bite[24]	0	1	1
bite[25]	0	1	1
bite[26]	0	1	1
bite[27]	0	1	1
bite[28]	0	1	1
bite[29]	0	1	1
bite[30]	0	1	1
bite[31]	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bite[0]	55333	1		T1	622		T2	13		T3	13
bite_0	5355	1		T1	40		T2	8		T3	8

---

Summary for Variable pause_in_sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for pause_in_sleep_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
[auto[1]]	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	60688	1		T1	662		T2	21		T3	21

---

Summary for Variable prescale_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for prescale_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prescale_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
prescale[0]	1187	1		T13	175		T14	9		T15	58
prescale[1]	1497	1		T13	19		T15	101		T19	19
prescale[2]	1353	1		T1	19		T91	19		T42	78
prescale[3]	769	1		T15	37		T38	55		T20	19
prescale[4]	1476	1		T39	65		T40	37		T83	167
prescale[5]	839	1		T41	28		T84	2		T92	40
prescale[6]	712	1		T38	28		T93	9		T86	38
prescale[7]	985	1		T1	24		T13	24		T15	45
prescale[8]	1115	1		T13	117		T94	19		T91	19
prescale[9]	1385	1		T1	20		T39	94		T40	40
prescale[10]	1324	1		T5	19		T8	9		T38	2
prescale[11]	1025	1		T15	70		T38	2		T95	9
prescale[12]	1022	1		T42	120		T96	23		T97	94
prescale[13]	343	1		T1	18		T5	9		T15	77
prescale[14]	974	1		T13	2		T20	19		T39	63
prescale[15]	1385	1		T20	23		T91	19		T98	23
prescale[16]	1362	1		T5	46		T13	66		T15	82
prescale[17]	1091	1		T1	61		T5	47		T20	19
prescale[18]	769	1		T1	61		T40	77		T41	2
prescale[19]	1001	1		T20	37		T41	2		T42	118
prescale[20]	1216	1		T5	19		T13	2		T15	19
prescale[21]	1280	1		T1	92		T13	2		T15	73
prescale[22]	751	1		T1	2		T13	28		T15	4
prescale[23]	756	1		T1	2		T13	2		T39	38
prescale[24]	703	1		T13	81		T38	2		T99	9
prescale[25]	1051	1		T5	40		T15	67		T91	36
prescale[26]	1153	1		T15	100		T90	9		T38	92
prescale[27]	1624	1		T1	85		T15	37		T40	104
prescale[28]	1190	1		T5	42		T13	2		T15	99
prescale[29]	1038	1		T15	2		T39	145		T42	2
prescale[30]	1181	1		T5	40		T19	54		T30	9
prescale[31]	1047	1		T13	19		T15	2		T19	40
prescale_0	26084	1		T1	278		T2	21		T3	21

---

Summary for Variable wdog_regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wdog_regwen_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	47122	1		T1	487		T2	9		T3	21
auto[1]	13566	1		T1	175		T2	12		T5	59

---

Summary for Variable wkup_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for wkup_cause_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup_cause_cleared	60688	1		T1	662		T2	21		T3	21

---

Summary for Variable wkup_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	66	64	2	3.03

User Defined Bins for wkup_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
wkup_max	0	1	1
wkup[1]	0	1	1
wkup[2]	0	1	1
wkup[3]	0	1	1
wkup[4]	0	1	1
wkup[5]	0	1	1
wkup[6]	0	1	1
wkup[7]	0	1	1
wkup[8]	0	1	1
wkup[9]	0	1	1
wkup[10]	0	1	1
wkup[11]	0	1	1
wkup[12]	0	1	1
wkup[13]	0	1	1
wkup[14]	0	1	1
wkup[15]	0	1	1
wkup[16]	0	1	1
wkup[17]	0	1	1
wkup[18]	0	1	1
wkup[19]	0	1	1
wkup[20]	0	1	1
wkup[21]	0	1	1
wkup[22]	0	1	1
wkup[23]	0	1	1
wkup[24]	0	1	1
wkup[25]	0	1	1
wkup[26]	0	1	1
wkup[27]	0	1	1
wkup[28]	0	1	1
wkup[29]	0	1	1
wkup[30]	0	1	1
wkup[31]	0	1	1
wkup[32]	0	1	1
wkup[33]	0	1	1
wkup[34]	0	1	1
wkup[35]	0	1	1
wkup[36]	0	1	1
wkup[37]	0	1	1
wkup[38]	0	1	1
wkup[39]	0	1	1
wkup[40]	0	1	1
wkup[41]	0	1	1
wkup[42]	0	1	1
wkup[43]	0	1	1
wkup[44]	0	1	1
wkup[45]	0	1	1
wkup[46]	0	1	1
wkup[47]	0	1	1
wkup[48]	0	1	1
wkup[49]	0	1	1
wkup[50]	0	1	1
wkup[51]	0	1	1
wkup[52]	0	1	1
wkup[53]	0	1	1
wkup[54]	0	1	1
wkup[55]	0	1	1
wkup[56]	0	1	1
wkup[57]	0	1	1
wkup[58]	0	1	1
wkup[59]	0	1	1
wkup[60]	0	1	1
wkup[61]	0	1	1
wkup[62]	0	1	1
wkup[63]	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup[0]	56842	1		T1	637		T2	16		T3	16
wkup_0	3846	1		T1	25		T2	5		T3	5