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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
92.98 99.25 93.67 100.00 98.40 99.51 67.06


Total test records in report: 420
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T286 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.3217660107 Apr 30 02:03:36 PM PDT 24 Apr 30 02:03:37 PM PDT 24 348191417 ps
T33 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.703745930 Apr 30 02:03:10 PM PDT 24 Apr 30 02:03:11 PM PDT 24 553424272 ps
T287 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.605099479 Apr 30 02:03:01 PM PDT 24 Apr 30 02:03:04 PM PDT 24 538027388 ps
T34 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.1121480956 Apr 30 02:03:23 PM PDT 24 Apr 30 02:03:28 PM PDT 24 4738152661 ps
T35 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.4166623179 Apr 30 02:03:29 PM PDT 24 Apr 30 02:03:31 PM PDT 24 937254398 ps
T288 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.3511488102 Apr 30 02:03:37 PM PDT 24 Apr 30 02:03:39 PM PDT 24 472300634 ps
T289 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.2030185220 Apr 30 02:03:47 PM PDT 24 Apr 30 02:03:49 PM PDT 24 467727743 ps
T71 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.1099728939 Apr 30 02:03:30 PM PDT 24 Apr 30 02:03:33 PM PDT 24 2624913935 ps
T105 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.660125144 Apr 30 02:03:17 PM PDT 24 Apr 30 02:03:19 PM PDT 24 465270016 ps
T107 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.3915957160 Apr 30 02:03:30 PM PDT 24 Apr 30 02:03:32 PM PDT 24 540140986 ps
T290 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.4224411476 Apr 30 02:03:22 PM PDT 24 Apr 30 02:03:24 PM PDT 24 606409693 ps
T291 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.746844462 Apr 30 02:03:23 PM PDT 24 Apr 30 02:03:24 PM PDT 24 341827374 ps
T72 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.3531934297 Apr 30 02:03:30 PM PDT 24 Apr 30 02:03:33 PM PDT 24 2559659422 ps
T292 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.1756375189 Apr 30 02:03:07 PM PDT 24 Apr 30 02:03:09 PM PDT 24 470750183 ps
T293 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.3565190101 Apr 30 02:03:29 PM PDT 24 Apr 30 02:03:32 PM PDT 24 629034811 ps
T294 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.2650982247 Apr 30 02:03:19 PM PDT 24 Apr 30 02:03:20 PM PDT 24 392566255 ps
T295 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.1598928870 Apr 30 02:03:00 PM PDT 24 Apr 30 02:03:02 PM PDT 24 276290301 ps
T296 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.822965625 Apr 30 02:02:59 PM PDT 24 Apr 30 02:03:02 PM PDT 24 1042235247 ps
T106 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.2849429666 Apr 30 02:03:18 PM PDT 24 Apr 30 02:03:20 PM PDT 24 387931971 ps
T73 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.2101125330 Apr 30 02:03:21 PM PDT 24 Apr 30 02:03:23 PM PDT 24 412686039 ps
T297 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.3655466136 Apr 30 02:03:37 PM PDT 24 Apr 30 02:03:39 PM PDT 24 457750202 ps
T298 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.1282453561 Apr 30 02:03:29 PM PDT 24 Apr 30 02:03:33 PM PDT 24 461922963 ps
T299 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.1461470983 Apr 30 02:03:09 PM PDT 24 Apr 30 02:03:11 PM PDT 24 784384565 ps
T300 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.2627195819 Apr 30 02:03:20 PM PDT 24 Apr 30 02:03:21 PM PDT 24 465218596 ps
T36 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.3306362636 Apr 30 02:03:29 PM PDT 24 Apr 30 02:03:43 PM PDT 24 8087930279 ps
T301 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.4101155328 Apr 30 02:03:47 PM PDT 24 Apr 30 02:03:49 PM PDT 24 518944818 ps
T74 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.4231026380 Apr 30 02:03:24 PM PDT 24 Apr 30 02:03:27 PM PDT 24 1657100033 ps
T57 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.2098770250 Apr 30 02:03:17 PM PDT 24 Apr 30 02:03:18 PM PDT 24 546256435 ps
T58 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.1889355141 Apr 30 02:03:15 PM PDT 24 Apr 30 02:03:20 PM PDT 24 3396098247 ps
T302 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.2687777806 Apr 30 02:03:29 PM PDT 24 Apr 30 02:03:32 PM PDT 24 595150135 ps
T75 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.3698451703 Apr 30 02:03:07 PM PDT 24 Apr 30 02:03:12 PM PDT 24 1505291378 ps
T303 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.211642328 Apr 30 02:03:07 PM PDT 24 Apr 30 02:03:09 PM PDT 24 343055142 ps
T304 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.4166186390 Apr 30 02:03:37 PM PDT 24 Apr 30 02:03:39 PM PDT 24 423170888 ps
T76 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.2886403366 Apr 30 02:03:07 PM PDT 24 Apr 30 02:03:08 PM PDT 24 2534730150 ps
T77 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.1142941749 Apr 30 02:03:23 PM PDT 24 Apr 30 02:03:24 PM PDT 24 321027869 ps
T305 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.3703891804 Apr 30 02:03:12 PM PDT 24 Apr 30 02:03:14 PM PDT 24 396656907 ps
T37 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.1714463287 Apr 30 02:03:12 PM PDT 24 Apr 30 02:03:15 PM PDT 24 4565505517 ps
T59 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.386179069 Apr 30 02:03:10 PM PDT 24 Apr 30 02:03:13 PM PDT 24 1334429874 ps
T306 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.2383078042 Apr 30 02:03:37 PM PDT 24 Apr 30 02:03:41 PM PDT 24 761924648 ps
T60 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.1827866849 Apr 30 02:03:19 PM PDT 24 Apr 30 02:03:20 PM PDT 24 608616594 ps
T307 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.1886660180 Apr 30 02:03:19 PM PDT 24 Apr 30 02:03:20 PM PDT 24 586681898 ps
T308 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.228198831 Apr 30 02:03:20 PM PDT 24 Apr 30 02:03:21 PM PDT 24 427962039 ps
T309 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.2449072906 Apr 30 02:03:49 PM PDT 24 Apr 30 02:03:50 PM PDT 24 310775973 ps
T310 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.17570094 Apr 30 02:03:22 PM PDT 24 Apr 30 02:03:24 PM PDT 24 349286656 ps
T100 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.641251486 Apr 30 02:03:23 PM PDT 24 Apr 30 02:03:29 PM PDT 24 4404862271 ps
T61 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.2298708248 Apr 30 02:03:29 PM PDT 24 Apr 30 02:03:31 PM PDT 24 373109521 ps
T311 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.3977580245 Apr 30 02:03:18 PM PDT 24 Apr 30 02:03:21 PM PDT 24 440411318 ps
T312 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.3250147186 Apr 30 02:03:25 PM PDT 24 Apr 30 02:03:27 PM PDT 24 461602428 ps
T313 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.1135728470 Apr 30 02:03:12 PM PDT 24 Apr 30 02:03:13 PM PDT 24 316498885 ps
T314 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.2701716239 Apr 30 02:03:17 PM PDT 24 Apr 30 02:03:18 PM PDT 24 629502350 ps
T78 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.2214579640 Apr 30 02:03:25 PM PDT 24 Apr 30 02:03:27 PM PDT 24 488786434 ps
T315 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.222005993 Apr 30 02:03:18 PM PDT 24 Apr 30 02:03:20 PM PDT 24 1969265316 ps
T316 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.1215589694 Apr 30 02:03:00 PM PDT 24 Apr 30 02:03:02 PM PDT 24 389610486 ps
T317 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.562977130 Apr 30 02:03:22 PM PDT 24 Apr 30 02:03:23 PM PDT 24 334043673 ps
T62 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.2030781980 Apr 30 02:03:22 PM PDT 24 Apr 30 02:03:23 PM PDT 24 335275342 ps
T318 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.3825976854 Apr 30 02:03:06 PM PDT 24 Apr 30 02:03:25 PM PDT 24 7137001281 ps
T319 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.95680393 Apr 30 02:03:17 PM PDT 24 Apr 30 02:03:23 PM PDT 24 6895004066 ps
T320 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.1648604380 Apr 30 02:03:41 PM PDT 24 Apr 30 02:03:42 PM PDT 24 418466989 ps
T321 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.2042071512 Apr 30 02:03:22 PM PDT 24 Apr 30 02:03:24 PM PDT 24 415508863 ps
T322 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.1661508073 Apr 30 02:03:17 PM PDT 24 Apr 30 02:03:21 PM PDT 24 2655576119 ps
T323 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.2742821719 Apr 30 02:03:19 PM PDT 24 Apr 30 02:03:21 PM PDT 24 355195518 ps
T324 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.4113288063 Apr 30 02:03:16 PM PDT 24 Apr 30 02:03:18 PM PDT 24 501617358 ps
T325 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.620186026 Apr 30 02:03:16 PM PDT 24 Apr 30 02:03:18 PM PDT 24 331977037 ps
T63 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.4257272234 Apr 30 02:03:15 PM PDT 24 Apr 30 02:03:17 PM PDT 24 439073847 ps
T326 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.1517215977 Apr 30 02:03:23 PM PDT 24 Apr 30 02:03:27 PM PDT 24 2470718354 ps
T327 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.1150352476 Apr 30 02:03:18 PM PDT 24 Apr 30 02:03:19 PM PDT 24 1173443857 ps
T104 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.394993330 Apr 30 02:03:07 PM PDT 24 Apr 30 02:03:22 PM PDT 24 7886128302 ps
T328 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.613424897 Apr 30 02:03:47 PM PDT 24 Apr 30 02:03:49 PM PDT 24 273477431 ps
T329 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.1932149061 Apr 30 02:03:29 PM PDT 24 Apr 30 02:03:30 PM PDT 24 410205075 ps
T330 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.980267964 Apr 30 02:03:37 PM PDT 24 Apr 30 02:03:38 PM PDT 24 377880200 ps
T331 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.552674333 Apr 30 02:03:20 PM PDT 24 Apr 30 02:03:22 PM PDT 24 494042729 ps
T332 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.640567549 Apr 30 02:03:29 PM PDT 24 Apr 30 02:03:31 PM PDT 24 578144820 ps
T333 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.387648733 Apr 30 02:03:31 PM PDT 24 Apr 30 02:03:33 PM PDT 24 452214334 ps
T334 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.1222986232 Apr 30 02:03:08 PM PDT 24 Apr 30 02:03:15 PM PDT 24 14091806963 ps
T66 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.4018882124 Apr 30 02:03:24 PM PDT 24 Apr 30 02:03:26 PM PDT 24 453688395 ps
T335 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.577258039 Apr 30 02:03:47 PM PDT 24 Apr 30 02:03:48 PM PDT 24 447002602 ps
T336 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.4011566966 Apr 30 02:03:17 PM PDT 24 Apr 30 02:03:19 PM PDT 24 5109186383 ps
T337 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.1916849967 Apr 30 02:03:38 PM PDT 24 Apr 30 02:03:40 PM PDT 24 522640139 ps
T338 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.3861918278 Apr 30 02:03:39 PM PDT 24 Apr 30 02:03:41 PM PDT 24 381005170 ps
T339 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.3425983843 Apr 30 02:03:23 PM PDT 24 Apr 30 02:03:25 PM PDT 24 497927425 ps
T340 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.3281254042 Apr 30 02:03:30 PM PDT 24 Apr 30 02:03:33 PM PDT 24 324163191 ps
T341 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.352304680 Apr 30 02:03:22 PM PDT 24 Apr 30 02:03:26 PM PDT 24 4607639679 ps
T342 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.1642851866 Apr 30 02:03:20 PM PDT 24 Apr 30 02:03:26 PM PDT 24 2752231451 ps
T343 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.1424792381 Apr 30 02:03:07 PM PDT 24 Apr 30 02:03:09 PM PDT 24 511437906 ps
T344 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.553149823 Apr 30 02:03:19 PM PDT 24 Apr 30 02:03:21 PM PDT 24 636460796 ps
T345 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.216865858 Apr 30 02:03:39 PM PDT 24 Apr 30 02:03:41 PM PDT 24 341102338 ps
T67 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.956959670 Apr 30 02:03:09 PM PDT 24 Apr 30 02:03:10 PM PDT 24 606544994 ps
T346 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.2171768614 Apr 30 02:03:31 PM PDT 24 Apr 30 02:03:34 PM PDT 24 2996147628 ps
T347 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.220764322 Apr 30 02:03:47 PM PDT 24 Apr 30 02:03:48 PM PDT 24 320070983 ps
T101 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.2241763275 Apr 30 02:03:02 PM PDT 24 Apr 30 02:03:10 PM PDT 24 3962691024 ps
T348 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.620899915 Apr 30 02:03:37 PM PDT 24 Apr 30 02:03:39 PM PDT 24 462189992 ps
T349 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.2686981677 Apr 30 02:03:31 PM PDT 24 Apr 30 02:03:32 PM PDT 24 404401413 ps
T350 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.3260204448 Apr 30 02:03:18 PM PDT 24 Apr 30 02:03:20 PM PDT 24 450198250 ps
T351 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.1436059193 Apr 30 02:03:37 PM PDT 24 Apr 30 02:03:38 PM PDT 24 427557740 ps
T352 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.2262306499 Apr 30 02:03:02 PM PDT 24 Apr 30 02:03:03 PM PDT 24 388944909 ps
T68 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.1508691355 Apr 30 02:03:09 PM PDT 24 Apr 30 02:03:11 PM PDT 24 496051819 ps
T64 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.3070519200 Apr 30 02:03:37 PM PDT 24 Apr 30 02:03:39 PM PDT 24 298071450 ps
T353 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.2108730295 Apr 30 02:03:07 PM PDT 24 Apr 30 02:03:10 PM PDT 24 394058801 ps
T354 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.1182701 Apr 30 02:03:39 PM PDT 24 Apr 30 02:03:41 PM PDT 24 433887197 ps
T355 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.4145360306 Apr 30 02:03:17 PM PDT 24 Apr 30 02:03:23 PM PDT 24 2350903539 ps
T356 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.2561674445 Apr 30 02:03:19 PM PDT 24 Apr 30 02:03:21 PM PDT 24 569519074 ps
T357 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.2843254240 Apr 30 02:03:31 PM PDT 24 Apr 30 02:03:33 PM PDT 24 443572040 ps
T69 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.3831823327 Apr 30 02:03:07 PM PDT 24 Apr 30 02:03:09 PM PDT 24 438221856 ps
T358 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.25958690 Apr 30 02:03:14 PM PDT 24 Apr 30 02:03:17 PM PDT 24 949098342 ps
T359 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.4271903340 Apr 30 02:03:22 PM PDT 24 Apr 30 02:03:25 PM PDT 24 1223691912 ps
T360 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.1457003655 Apr 30 02:03:09 PM PDT 24 Apr 30 02:03:10 PM PDT 24 368999053 ps
T361 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.1632228580 Apr 30 02:03:12 PM PDT 24 Apr 30 02:03:14 PM PDT 24 515737428 ps
T362 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.343376050 Apr 30 02:03:25 PM PDT 24 Apr 30 02:03:27 PM PDT 24 411249298 ps
T363 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.1541279712 Apr 30 02:03:28 PM PDT 24 Apr 30 02:03:31 PM PDT 24 4657950574 ps
T364 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.589529529 Apr 30 02:03:22 PM PDT 24 Apr 30 02:03:24 PM PDT 24 566474709 ps
T365 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.1832795245 Apr 30 02:03:23 PM PDT 24 Apr 30 02:03:25 PM PDT 24 340032924 ps
T366 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.2268978674 Apr 30 02:03:21 PM PDT 24 Apr 30 02:03:23 PM PDT 24 527280234 ps
T367 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.4024415689 Apr 30 02:03:41 PM PDT 24 Apr 30 02:03:43 PM PDT 24 489928742 ps
T368 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.4222549836 Apr 30 02:03:09 PM PDT 24 Apr 30 02:03:11 PM PDT 24 577919493 ps
T369 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.3569503369 Apr 30 02:03:31 PM PDT 24 Apr 30 02:03:34 PM PDT 24 1176558135 ps
T370 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.1542392425 Apr 30 02:03:12 PM PDT 24 Apr 30 02:03:15 PM PDT 24 1309431371 ps
T371 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.1228158720 Apr 30 02:03:07 PM PDT 24 Apr 30 02:03:10 PM PDT 24 968831850 ps
T372 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.1900053152 Apr 30 02:03:37 PM PDT 24 Apr 30 02:03:41 PM PDT 24 4201332668 ps
T373 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.2069886915 Apr 30 02:03:37 PM PDT 24 Apr 30 02:03:39 PM PDT 24 388277817 ps
T374 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.4183973734 Apr 30 02:03:31 PM PDT 24 Apr 30 02:03:33 PM PDT 24 559420189 ps
T70 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.2531472007 Apr 30 02:03:17 PM PDT 24 Apr 30 02:03:18 PM PDT 24 580933189 ps
T375 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.1131348890 Apr 30 02:03:24 PM PDT 24 Apr 30 02:03:27 PM PDT 24 522482106 ps
T376 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.443106840 Apr 30 02:03:24 PM PDT 24 Apr 30 02:03:26 PM PDT 24 1123590359 ps
T377 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.4251224513 Apr 30 02:03:17 PM PDT 24 Apr 30 02:03:18 PM PDT 24 309236749 ps
T378 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.3350496975 Apr 30 02:03:25 PM PDT 24 Apr 30 02:03:28 PM PDT 24 359425499 ps
T379 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.1807559817 Apr 30 02:03:33 PM PDT 24 Apr 30 02:03:34 PM PDT 24 493304135 ps
T380 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.3461522080 Apr 30 02:03:20 PM PDT 24 Apr 30 02:03:21 PM PDT 24 322913012 ps
T381 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.2012975804 Apr 30 02:03:38 PM PDT 24 Apr 30 02:03:40 PM PDT 24 345477643 ps
T382 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.2478739797 Apr 30 02:03:24 PM PDT 24 Apr 30 02:03:26 PM PDT 24 530440607 ps
T102 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.2942172396 Apr 30 02:03:25 PM PDT 24 Apr 30 02:03:27 PM PDT 24 9202055500 ps
T383 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.3133899894 Apr 30 02:03:24 PM PDT 24 Apr 30 02:03:30 PM PDT 24 4630385126 ps
T103 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.3413914345 Apr 30 02:03:11 PM PDT 24 Apr 30 02:03:14 PM PDT 24 4105272729 ps
T384 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.3138979469 Apr 30 02:03:09 PM PDT 24 Apr 30 02:03:11 PM PDT 24 353844714 ps
T385 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.192759860 Apr 30 02:03:38 PM PDT 24 Apr 30 02:03:40 PM PDT 24 300843641 ps
T386 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.3661179128 Apr 30 02:03:12 PM PDT 24 Apr 30 02:03:35 PM PDT 24 13990049393 ps
T387 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.4082204723 Apr 30 02:03:20 PM PDT 24 Apr 30 02:03:34 PM PDT 24 8188661805 ps
T388 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.42262141 Apr 30 02:03:07 PM PDT 24 Apr 30 02:03:09 PM PDT 24 301627543 ps
T389 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.175310321 Apr 30 02:03:18 PM PDT 24 Apr 30 02:03:19 PM PDT 24 460942493 ps
T390 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.1354755508 Apr 30 02:03:39 PM PDT 24 Apr 30 02:03:41 PM PDT 24 297487083 ps
T391 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.1414962750 Apr 30 02:03:31 PM PDT 24 Apr 30 02:03:36 PM PDT 24 8610642719 ps
T392 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.2308405515 Apr 30 02:03:18 PM PDT 24 Apr 30 02:03:19 PM PDT 24 424561119 ps
T393 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.2323655710 Apr 30 02:03:31 PM PDT 24 Apr 30 02:03:32 PM PDT 24 408739396 ps
T394 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.3249099713 Apr 30 02:03:06 PM PDT 24 Apr 30 02:03:08 PM PDT 24 322521122 ps
T395 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.784246202 Apr 30 02:03:16 PM PDT 24 Apr 30 02:03:19 PM PDT 24 5045009854 ps
T396 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.3461303010 Apr 30 02:03:16 PM PDT 24 Apr 30 02:03:19 PM PDT 24 4572839151 ps
T397 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.4293875763 Apr 30 02:03:29 PM PDT 24 Apr 30 02:03:31 PM PDT 24 475946298 ps
T398 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.3635485533 Apr 30 02:03:24 PM PDT 24 Apr 30 02:03:38 PM PDT 24 8581824279 ps
T399 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.2007982151 Apr 30 02:03:28 PM PDT 24 Apr 30 02:03:30 PM PDT 24 469524531 ps
T400 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.537606463 Apr 30 02:03:22 PM PDT 24 Apr 30 02:03:25 PM PDT 24 8527031401 ps
T65 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.3353452959 Apr 30 02:03:32 PM PDT 24 Apr 30 02:03:33 PM PDT 24 296082489 ps
T401 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.2976865484 Apr 30 02:03:22 PM PDT 24 Apr 30 02:03:24 PM PDT 24 366648052 ps
T402 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.1192624483 Apr 30 02:03:08 PM PDT 24 Apr 30 02:03:09 PM PDT 24 1171921309 ps
T403 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.15046454 Apr 30 02:03:06 PM PDT 24 Apr 30 02:03:07 PM PDT 24 499148876 ps
T404 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.3069755359 Apr 30 02:03:08 PM PDT 24 Apr 30 02:03:10 PM PDT 24 745390517 ps
T405 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.595288649 Apr 30 02:03:24 PM PDT 24 Apr 30 02:03:27 PM PDT 24 666335741 ps
T406 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.4224301724 Apr 30 02:03:17 PM PDT 24 Apr 30 02:03:18 PM PDT 24 1139221582 ps
T407 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.4231830370 Apr 30 02:03:30 PM PDT 24 Apr 30 02:03:39 PM PDT 24 7970938357 ps
T408 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.557914829 Apr 30 02:03:38 PM PDT 24 Apr 30 02:03:39 PM PDT 24 428330428 ps
T409 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.1649868616 Apr 30 02:03:31 PM PDT 24 Apr 30 02:03:33 PM PDT 24 2499945124 ps
T410 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.2767068553 Apr 30 02:03:48 PM PDT 24 Apr 30 02:03:49 PM PDT 24 456674394 ps
T411 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.2555217849 Apr 30 02:03:17 PM PDT 24 Apr 30 02:03:18 PM PDT 24 409453127 ps
T412 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.1106744077 Apr 30 02:03:17 PM PDT 24 Apr 30 02:03:19 PM PDT 24 2645139688 ps
T413 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.1665663324 Apr 30 02:03:21 PM PDT 24 Apr 30 02:03:22 PM PDT 24 523573152 ps
T414 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.2427963100 Apr 30 02:03:30 PM PDT 24 Apr 30 02:03:35 PM PDT 24 2153958516 ps
T415 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.2993374125 Apr 30 02:03:39 PM PDT 24 Apr 30 02:03:40 PM PDT 24 420088936 ps
T416 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.2483566652 Apr 30 02:03:39 PM PDT 24 Apr 30 02:03:41 PM PDT 24 333883664 ps
T417 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.3157654449 Apr 30 02:03:38 PM PDT 24 Apr 30 02:03:40 PM PDT 24 415691731 ps
T418 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.3749837805 Apr 30 02:03:37 PM PDT 24 Apr 30 02:03:39 PM PDT 24 318796107 ps
T419 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.4004545106 Apr 30 02:03:24 PM PDT 24 Apr 30 02:03:31 PM PDT 24 2816970588 ps
T420 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.1079383586 Apr 30 02:03:36 PM PDT 24 Apr 30 02:03:37 PM PDT 24 429808912 ps

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.786688064
Short name T1
Test name
Test status
Simulation time 53184956990 ps
CPU time 211.39 seconds
Started Apr 30 02:02:07 PM PDT 24
Finished Apr 30 02:05:39 PM PDT 24
Peak memory 198476 kb
Host smart-f93c9541-c967-4454-ad35-d1ea7b66c83d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786688064 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.786688064
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.1627572313
Short name T15
Test name
Test status
Simulation time 148148991010 ps
CPU time 632.31 seconds
Started Apr 30 02:02:18 PM PDT 24
Finished Apr 30 02:12:51 PM PDT 24
Peak memory 199652 kb
Host smart-502c3ea6-c0f4-4855-a9d1-aa0e91923e67
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627572313 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.1627572313
Directory /workspace/9.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.1121480956
Short name T34
Test name
Test status
Simulation time 4738152661 ps
CPU time 3.8 seconds
Started Apr 30 02:03:23 PM PDT 24
Finished Apr 30 02:03:28 PM PDT 24
Peak memory 197652 kb
Host smart-5844327c-22e2-4a2a-93b6-492c42f5ccc2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121480956 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_t
l_intg_err.1121480956
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.3158530837
Short name T41
Test name
Test status
Simulation time 112181787089 ps
CPU time 1008.98 seconds
Started Apr 30 02:02:15 PM PDT 24
Finished Apr 30 02:19:04 PM PDT 24
Peak memory 204452 kb
Host smart-b152c850-1593-46ca-8049-6ce53bfd2e52
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158530837 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.3158530837
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.1043993241
Short name T5
Test name
Test status
Simulation time 443619637631 ps
CPU time 174.48 seconds
Started Apr 30 02:02:27 PM PDT 24
Finished Apr 30 02:05:22 PM PDT 24
Peak memory 195084 kb
Host smart-1e36c40d-449e-4396-a3a1-a48ef5d37268
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043993241 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_
all.1043993241
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.1401329364
Short name T21
Test name
Test status
Simulation time 3927869361 ps
CPU time 6.02 seconds
Started Apr 30 02:02:09 PM PDT 24
Finished Apr 30 02:02:15 PM PDT 24
Peak memory 214876 kb
Host smart-8ee69d3a-b2da-4bc8-95b8-30cf25edba35
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401329364 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.1401329364
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.2241763275
Short name T101
Test name
Test status
Simulation time 3962691024 ps
CPU time 6.58 seconds
Started Apr 30 02:03:02 PM PDT 24
Finished Apr 30 02:03:10 PM PDT 24
Peak memory 197480 kb
Host smart-3f09c024-d582-4762-a053-9a323d477e21
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241763275 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl
_intg_err.2241763275
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.1518864889
Short name T20
Test name
Test status
Simulation time 191340485617 ps
CPU time 143.33 seconds
Started Apr 30 02:02:44 PM PDT 24
Finished Apr 30 02:05:08 PM PDT 24
Peak memory 183664 kb
Host smart-e06ffb4e-073b-4b45-be1b-5a5058a3d23a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518864889 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_
all.1518864889
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.2298708248
Short name T61
Test name
Test status
Simulation time 373109521 ps
CPU time 1.25 seconds
Started Apr 30 02:03:29 PM PDT 24
Finished Apr 30 02:03:31 PM PDT 24
Peak memory 193120 kb
Host smart-8bdadea9-9664-46d7-b5d1-76d3a693f377
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298708248 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.2298708248
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.3143949082
Short name T157
Test name
Test status
Simulation time 25569640068 ps
CPU time 13.02 seconds
Started Apr 30 02:02:26 PM PDT 24
Finished Apr 30 02:02:40 PM PDT 24
Peak memory 198520 kb
Host smart-7024525f-6242-42d9-9f3d-a8908922c5ff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143949082 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.3143949082
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.641251486
Short name T100
Test name
Test status
Simulation time 4404862271 ps
CPU time 5.15 seconds
Started Apr 30 02:03:23 PM PDT 24
Finished Apr 30 02:03:29 PM PDT 24
Peak memory 197660 kb
Host smart-45b3c30c-5dba-486b-8e3c-96e0199f2e70
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641251486 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl
_intg_err.641251486
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.1397048000
Short name T134
Test name
Test status
Simulation time 6669354597 ps
CPU time 11.62 seconds
Started Apr 30 02:02:17 PM PDT 24
Finished Apr 30 02:02:29 PM PDT 24
Peak memory 183544 kb
Host smart-8a7bc963-51d9-4f21-b8af-2bede15cbb69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397048000 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.1397048000
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.956959670
Short name T67
Test name
Test status
Simulation time 606544994 ps
CPU time 1.01 seconds
Started Apr 30 02:03:09 PM PDT 24
Finished Apr 30 02:03:10 PM PDT 24
Peak memory 194264 kb
Host smart-34984cc4-1a9e-4b6e-ac76-66571c37ad13
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956959670 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_al
iasing.956959670
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.3825976854
Short name T318
Test name
Test status
Simulation time 7137001281 ps
CPU time 18.59 seconds
Started Apr 30 02:03:06 PM PDT 24
Finished Apr 30 02:03:25 PM PDT 24
Peak memory 192120 kb
Host smart-0f6e48c5-35fb-4f82-92c3-cd688ab9d301
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825976854 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_b
it_bash.3825976854
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.822965625
Short name T296
Test name
Test status
Simulation time 1042235247 ps
CPU time 1.98 seconds
Started Apr 30 02:02:59 PM PDT 24
Finished Apr 30 02:03:02 PM PDT 24
Peak memory 183640 kb
Host smart-35eeb058-68c8-4058-a56b-9e926ce504e4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822965625 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_hw
_reset.822965625
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.1711441414
Short name T32
Test name
Test status
Simulation time 471405156 ps
CPU time 1.4 seconds
Started Apr 30 02:03:10 PM PDT 24
Finished Apr 30 02:03:12 PM PDT 24
Peak memory 196064 kb
Host smart-5e1f7780-fd3f-4339-90dc-3da5b5e0fb07
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711441414 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.1711441414
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.3831823327
Short name T69
Test name
Test status
Simulation time 438221856 ps
CPU time 0.91 seconds
Started Apr 30 02:03:07 PM PDT 24
Finished Apr 30 02:03:09 PM PDT 24
Peak memory 192940 kb
Host smart-4a5d0995-5305-435a-a053-57234eae01c1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831823327 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.3831823327
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.1598928870
Short name T295
Test name
Test status
Simulation time 276290301 ps
CPU time 0.91 seconds
Started Apr 30 02:03:00 PM PDT 24
Finished Apr 30 02:03:02 PM PDT 24
Peak memory 183580 kb
Host smart-7e34ffa4-801a-4d21-98ac-1632252c881a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598928870 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.1598928870
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.2262306499
Short name T352
Test name
Test status
Simulation time 388944909 ps
CPU time 0.81 seconds
Started Apr 30 02:03:02 PM PDT 24
Finished Apr 30 02:03:03 PM PDT 24
Peak memory 183496 kb
Host smart-46945f8f-d3fb-473d-91c4-37740a4783f6
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262306499 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_t
imer_mem_partial_access.2262306499
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.1215589694
Short name T316
Test name
Test status
Simulation time 389610486 ps
CPU time 1.08 seconds
Started Apr 30 02:03:00 PM PDT 24
Finished Apr 30 02:03:02 PM PDT 24
Peak memory 183556 kb
Host smart-b9576e97-997d-4d19-8224-0e558fe798e5
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215589694 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_w
alk.1215589694
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.2886403366
Short name T76
Test name
Test status
Simulation time 2534730150 ps
CPU time 1.05 seconds
Started Apr 30 02:03:07 PM PDT 24
Finished Apr 30 02:03:08 PM PDT 24
Peak memory 194396 kb
Host smart-7f0192b4-8fd2-4ece-b02c-e76c448ffa53
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886403366 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon
_timer_same_csr_outstanding.2886403366
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.605099479
Short name T287
Test name
Test status
Simulation time 538027388 ps
CPU time 1.9 seconds
Started Apr 30 02:03:01 PM PDT 24
Finished Apr 30 02:03:04 PM PDT 24
Peak memory 198452 kb
Host smart-7f82dc1e-dfbe-4fb3-9977-35ca8ae9125e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605099479 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.605099479
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.3069755359
Short name T404
Test name
Test status
Simulation time 745390517 ps
CPU time 1.41 seconds
Started Apr 30 02:03:08 PM PDT 24
Finished Apr 30 02:03:10 PM PDT 24
Peak memory 194196 kb
Host smart-1663698c-b723-4a53-82d1-ee6c2be03582
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069755359 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_a
liasing.3069755359
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.1222986232
Short name T334
Test name
Test status
Simulation time 14091806963 ps
CPU time 6.57 seconds
Started Apr 30 02:03:08 PM PDT 24
Finished Apr 30 02:03:15 PM PDT 24
Peak memory 192208 kb
Host smart-75406756-6123-4b86-9920-7979a8d750ca
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222986232 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_b
it_bash.1222986232
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.386179069
Short name T59
Test name
Test status
Simulation time 1334429874 ps
CPU time 2.57 seconds
Started Apr 30 02:03:10 PM PDT 24
Finished Apr 30 02:03:13 PM PDT 24
Peak memory 183688 kb
Host smart-e5691ac2-f8c9-4814-bea8-775dbff7581c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386179069 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_hw
_reset.386179069
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.3138979469
Short name T384
Test name
Test status
Simulation time 353844714 ps
CPU time 1.12 seconds
Started Apr 30 02:03:09 PM PDT 24
Finished Apr 30 02:03:11 PM PDT 24
Peak memory 194684 kb
Host smart-16967552-2952-46af-a277-ed5a307bf899
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138979469 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.3138979469
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.1424792381
Short name T343
Test name
Test status
Simulation time 511437906 ps
CPU time 1.33 seconds
Started Apr 30 02:03:07 PM PDT 24
Finished Apr 30 02:03:09 PM PDT 24
Peak memory 183632 kb
Host smart-848cb008-ba53-42f7-a4ea-9ff741da9960
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424792381 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.1424792381
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.1135728470
Short name T313
Test name
Test status
Simulation time 316498885 ps
CPU time 0.8 seconds
Started Apr 30 02:03:12 PM PDT 24
Finished Apr 30 02:03:13 PM PDT 24
Peak memory 183584 kb
Host smart-92f3585d-7d7b-46c3-84ae-2a8e78dd2809
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135728470 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.1135728470
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.3249099713
Short name T394
Test name
Test status
Simulation time 322521122 ps
CPU time 0.57 seconds
Started Apr 30 02:03:06 PM PDT 24
Finished Apr 30 02:03:08 PM PDT 24
Peak memory 183488 kb
Host smart-f2843730-5711-4646-b80b-b59cc9857f19
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249099713 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_t
imer_mem_partial_access.3249099713
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.211642328
Short name T303
Test name
Test status
Simulation time 343055142 ps
CPU time 0.62 seconds
Started Apr 30 02:03:07 PM PDT 24
Finished Apr 30 02:03:09 PM PDT 24
Peak memory 183508 kb
Host smart-b38dbb01-aba2-42f1-a911-14b5fb4be82b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211642328 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_wa
lk.211642328
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.3698451703
Short name T75
Test name
Test status
Simulation time 1505291378 ps
CPU time 3.62 seconds
Started Apr 30 02:03:07 PM PDT 24
Finished Apr 30 02:03:12 PM PDT 24
Peak memory 183712 kb
Host smart-500cd709-700b-44c5-812b-fd70918b7ddb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698451703 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon
_timer_same_csr_outstanding.3698451703
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.2108730295
Short name T353
Test name
Test status
Simulation time 394058801 ps
CPU time 2.64 seconds
Started Apr 30 02:03:07 PM PDT 24
Finished Apr 30 02:03:10 PM PDT 24
Peak memory 198436 kb
Host smart-a1ee5169-29c8-4b94-8216-8f5ee9e6fb02
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108730295 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.2108730295
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.1714463287
Short name T37
Test name
Test status
Simulation time 4565505517 ps
CPU time 2.32 seconds
Started Apr 30 02:03:12 PM PDT 24
Finished Apr 30 02:03:15 PM PDT 24
Peak memory 197044 kb
Host smart-88698a35-3cdd-4050-9bb4-4411c2d645b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714463287 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl
_intg_err.1714463287
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.1665663324
Short name T413
Test name
Test status
Simulation time 523573152 ps
CPU time 0.98 seconds
Started Apr 30 02:03:21 PM PDT 24
Finished Apr 30 02:03:22 PM PDT 24
Peak memory 195928 kb
Host smart-cb6c7952-672a-47b0-b473-34219c0745c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665663324 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.1665663324
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.1142941749
Short name T77
Test name
Test status
Simulation time 321027869 ps
CPU time 0.72 seconds
Started Apr 30 02:03:23 PM PDT 24
Finished Apr 30 02:03:24 PM PDT 24
Peak memory 192988 kb
Host smart-b1960584-f263-4059-ba12-0a5cdf6372f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142941749 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.1142941749
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.562977130
Short name T317
Test name
Test status
Simulation time 334043673 ps
CPU time 0.96 seconds
Started Apr 30 02:03:22 PM PDT 24
Finished Apr 30 02:03:23 PM PDT 24
Peak memory 183576 kb
Host smart-6693a472-1e46-4e31-ba49-72872c787a17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562977130 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.562977130
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.1517215977
Short name T326
Test name
Test status
Simulation time 2470718354 ps
CPU time 3.78 seconds
Started Apr 30 02:03:23 PM PDT 24
Finished Apr 30 02:03:27 PM PDT 24
Peak memory 194628 kb
Host smart-e4a1f4ca-0a05-45b8-8473-ee2ca26a963e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517215977 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.ao
n_timer_same_csr_outstanding.1517215977
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.1131348890
Short name T375
Test name
Test status
Simulation time 522482106 ps
CPU time 1.98 seconds
Started Apr 30 02:03:24 PM PDT 24
Finished Apr 30 02:03:27 PM PDT 24
Peak memory 198492 kb
Host smart-bfefb361-dd98-49f4-9fe0-c05aae42bb80
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131348890 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.1131348890
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.3635485533
Short name T398
Test name
Test status
Simulation time 8581824279 ps
CPU time 13.55 seconds
Started Apr 30 02:03:24 PM PDT 24
Finished Apr 30 02:03:38 PM PDT 24
Peak memory 198060 kb
Host smart-1b7684d3-82d0-4ff5-aefe-7d5939f4e98f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635485533 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_t
l_intg_err.3635485533
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.589529529
Short name T364
Test name
Test status
Simulation time 566474709 ps
CPU time 1.05 seconds
Started Apr 30 02:03:22 PM PDT 24
Finished Apr 30 02:03:24 PM PDT 24
Peak memory 198332 kb
Host smart-402a6093-3462-487a-9c16-f28f5b328a77
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589529529 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.589529529
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.2101125330
Short name T73
Test name
Test status
Simulation time 412686039 ps
CPU time 0.9 seconds
Started Apr 30 02:03:21 PM PDT 24
Finished Apr 30 02:03:23 PM PDT 24
Peak memory 192876 kb
Host smart-c42a2641-8104-4b81-bf91-062f70233fd0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101125330 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.2101125330
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.168567095
Short name T284
Test name
Test status
Simulation time 333920856 ps
CPU time 0.61 seconds
Started Apr 30 02:03:21 PM PDT 24
Finished Apr 30 02:03:22 PM PDT 24
Peak memory 183572 kb
Host smart-a081fb4d-d9eb-487d-8da4-b85cf2e7e1bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168567095 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.168567095
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.443106840
Short name T376
Test name
Test status
Simulation time 1123590359 ps
CPU time 1.04 seconds
Started Apr 30 02:03:24 PM PDT 24
Finished Apr 30 02:03:26 PM PDT 24
Peak memory 183664 kb
Host smart-f2a48af0-bf96-4bfc-b45e-f1841bc0a88e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443106840 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon
_timer_same_csr_outstanding.443106840
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.3281254042
Short name T340
Test name
Test status
Simulation time 324163191 ps
CPU time 2.36 seconds
Started Apr 30 02:03:30 PM PDT 24
Finished Apr 30 02:03:33 PM PDT 24
Peak memory 198504 kb
Host smart-5f5a3e69-2d7c-4d79-b84d-c4b7304c666d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281254042 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.3281254042
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.343376050
Short name T362
Test name
Test status
Simulation time 411249298 ps
CPU time 0.83 seconds
Started Apr 30 02:03:25 PM PDT 24
Finished Apr 30 02:03:27 PM PDT 24
Peak memory 196420 kb
Host smart-4f8dbd3c-e9d0-49df-9fa0-4554f03b0e6b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343376050 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.343376050
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.2214579640
Short name T78
Test name
Test status
Simulation time 488786434 ps
CPU time 1.25 seconds
Started Apr 30 02:03:25 PM PDT 24
Finished Apr 30 02:03:27 PM PDT 24
Peak memory 192920 kb
Host smart-6ad22823-b28f-4540-9bda-8d0c36a5d9e4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214579640 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.2214579640
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.1932149061
Short name T329
Test name
Test status
Simulation time 410205075 ps
CPU time 0.58 seconds
Started Apr 30 02:03:29 PM PDT 24
Finished Apr 30 02:03:30 PM PDT 24
Peak memory 183560 kb
Host smart-31f62460-7097-4ed6-956d-64eedd049892
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932149061 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.1932149061
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.1649868616
Short name T409
Test name
Test status
Simulation time 2499945124 ps
CPU time 1.5 seconds
Started Apr 30 02:03:31 PM PDT 24
Finished Apr 30 02:03:33 PM PDT 24
Peak memory 183764 kb
Host smart-f9ef8a1e-faff-46ae-8ac0-bc1a45ff394a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649868616 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.ao
n_timer_same_csr_outstanding.1649868616
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.3350496975
Short name T378
Test name
Test status
Simulation time 359425499 ps
CPU time 2.59 seconds
Started Apr 30 02:03:25 PM PDT 24
Finished Apr 30 02:03:28 PM PDT 24
Peak memory 198520 kb
Host smart-4a2753f7-790a-47cb-b1b9-d707ed4bc1eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350496975 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.3350496975
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.2942172396
Short name T102
Test name
Test status
Simulation time 9202055500 ps
CPU time 1.85 seconds
Started Apr 30 02:03:25 PM PDT 24
Finished Apr 30 02:03:27 PM PDT 24
Peak memory 197816 kb
Host smart-52ce0c4b-323b-441b-a5ef-9e56dd7bf4c2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942172396 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_t
l_intg_err.2942172396
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.2042071512
Short name T321
Test name
Test status
Simulation time 415508863 ps
CPU time 0.92 seconds
Started Apr 30 02:03:22 PM PDT 24
Finished Apr 30 02:03:24 PM PDT 24
Peak memory 195276 kb
Host smart-58fbf1e2-2406-4166-ad5e-5f84fcbbd892
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042071512 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.2042071512
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.4018882124
Short name T66
Test name
Test status
Simulation time 453688395 ps
CPU time 1.18 seconds
Started Apr 30 02:03:24 PM PDT 24
Finished Apr 30 02:03:26 PM PDT 24
Peak memory 193112 kb
Host smart-423665d0-8f99-49a1-bac4-60370401dda7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018882124 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.4018882124
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.1832795245
Short name T365
Test name
Test status
Simulation time 340032924 ps
CPU time 0.6 seconds
Started Apr 30 02:03:23 PM PDT 24
Finished Apr 30 02:03:25 PM PDT 24
Peak memory 183572 kb
Host smart-86bc4080-36cc-453f-8455-70da39016ddf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832795245 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.1832795245
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.4231026380
Short name T74
Test name
Test status
Simulation time 1657100033 ps
CPU time 2 seconds
Started Apr 30 02:03:24 PM PDT 24
Finished Apr 30 02:03:27 PM PDT 24
Peak memory 193152 kb
Host smart-47ccfe68-e212-4ae2-b0d6-a7fedd4d7770
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231026380 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.ao
n_timer_same_csr_outstanding.4231026380
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.2976865484
Short name T401
Test name
Test status
Simulation time 366648052 ps
CPU time 1.79 seconds
Started Apr 30 02:03:22 PM PDT 24
Finished Apr 30 02:03:24 PM PDT 24
Peak memory 198332 kb
Host smart-1f9bb035-6185-4fd2-abb8-79451e9b4dc4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976865484 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.2976865484
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.17570094
Short name T310
Test name
Test status
Simulation time 349286656 ps
CPU time 1.26 seconds
Started Apr 30 02:03:22 PM PDT 24
Finished Apr 30 02:03:24 PM PDT 24
Peak memory 196336 kb
Host smart-d647ad84-1b4c-443a-a5e6-b1a8db26a697
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17570094 -assert nopostproc +UVM_TESTNAME=a
on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.17570094
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.2030781980
Short name T62
Test name
Test status
Simulation time 335275342 ps
CPU time 0.61 seconds
Started Apr 30 02:03:22 PM PDT 24
Finished Apr 30 02:03:23 PM PDT 24
Peak memory 183632 kb
Host smart-c7f8afc3-3388-4462-b121-0f8c94f7d4b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030781980 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.2030781980
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.2268978674
Short name T366
Test name
Test status
Simulation time 527280234 ps
CPU time 0.72 seconds
Started Apr 30 02:03:21 PM PDT 24
Finished Apr 30 02:03:23 PM PDT 24
Peak memory 183532 kb
Host smart-c2fda611-2caf-4008-8806-70ec27717e39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268978674 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.2268978674
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.4271903340
Short name T359
Test name
Test status
Simulation time 1223691912 ps
CPU time 2.17 seconds
Started Apr 30 02:03:22 PM PDT 24
Finished Apr 30 02:03:25 PM PDT 24
Peak memory 183684 kb
Host smart-18e3f3f9-c656-4495-9218-ccff32b749cc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271903340 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao
n_timer_same_csr_outstanding.4271903340
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.3425983843
Short name T339
Test name
Test status
Simulation time 497927425 ps
CPU time 2.2 seconds
Started Apr 30 02:03:23 PM PDT 24
Finished Apr 30 02:03:25 PM PDT 24
Peak memory 198456 kb
Host smart-fa1616f9-d411-4e9d-ac7f-4442da87dfc2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425983843 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.3425983843
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.537606463
Short name T400
Test name
Test status
Simulation time 8527031401 ps
CPU time 2.09 seconds
Started Apr 30 02:03:22 PM PDT 24
Finished Apr 30 02:03:25 PM PDT 24
Peak memory 197880 kb
Host smart-0dbc60ab-28e5-46b3-9858-91bf763ae595
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537606463 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl
_intg_err.537606463
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.387648733
Short name T333
Test name
Test status
Simulation time 452214334 ps
CPU time 1.53 seconds
Started Apr 30 02:03:31 PM PDT 24
Finished Apr 30 02:03:33 PM PDT 24
Peak memory 195348 kb
Host smart-be2eb829-86a7-4d86-b44c-d4fbaa124d84
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387648733 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.387648733
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.3070519200
Short name T64
Test name
Test status
Simulation time 298071450 ps
CPU time 0.95 seconds
Started Apr 30 02:03:37 PM PDT 24
Finished Apr 30 02:03:39 PM PDT 24
Peak memory 183644 kb
Host smart-43512e8f-aa81-4cb5-a8a4-77e4e67d5fd0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070519200 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.3070519200
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.3655466136
Short name T297
Test name
Test status
Simulation time 457750202 ps
CPU time 1.21 seconds
Started Apr 30 02:03:37 PM PDT 24
Finished Apr 30 02:03:39 PM PDT 24
Peak memory 183556 kb
Host smart-ed59efa5-ff68-4bad-be7b-20ef0c6a0c4c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655466136 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.3655466136
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.4166623179
Short name T35
Test name
Test status
Simulation time 937254398 ps
CPU time 1.5 seconds
Started Apr 30 02:03:29 PM PDT 24
Finished Apr 30 02:03:31 PM PDT 24
Peak memory 183756 kb
Host smart-9528e9c7-aaf6-40ec-8998-bf263c89c541
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166623179 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.ao
n_timer_same_csr_outstanding.4166623179
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.3565190101
Short name T293
Test name
Test status
Simulation time 629034811 ps
CPU time 2.49 seconds
Started Apr 30 02:03:29 PM PDT 24
Finished Apr 30 02:03:32 PM PDT 24
Peak memory 198444 kb
Host smart-cf680336-706c-4dd1-a9c6-979af78c082c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565190101 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.3565190101
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.4231830370
Short name T407
Test name
Test status
Simulation time 7970938357 ps
CPU time 7.2 seconds
Started Apr 30 02:03:30 PM PDT 24
Finished Apr 30 02:03:39 PM PDT 24
Peak memory 197932 kb
Host smart-94df0096-9566-491c-8b3a-9705b81409fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231830370 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_t
l_intg_err.4231830370
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.640567549
Short name T332
Test name
Test status
Simulation time 578144820 ps
CPU time 0.79 seconds
Started Apr 30 02:03:29 PM PDT 24
Finished Apr 30 02:03:31 PM PDT 24
Peak memory 195376 kb
Host smart-2b1418c9-4844-4497-a0d6-e36a68e7a1b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640567549 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.640567549
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.1807559817
Short name T379
Test name
Test status
Simulation time 493304135 ps
CPU time 0.98 seconds
Started Apr 30 02:03:33 PM PDT 24
Finished Apr 30 02:03:34 PM PDT 24
Peak memory 183600 kb
Host smart-3580d08e-692c-4bf6-a389-874deaa31e1d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807559817 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.1807559817
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.4166186390
Short name T304
Test name
Test status
Simulation time 423170888 ps
CPU time 0.8 seconds
Started Apr 30 02:03:37 PM PDT 24
Finished Apr 30 02:03:39 PM PDT 24
Peak memory 183560 kb
Host smart-cd5d7b49-57c4-4dc9-a7b5-206f63196944
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166186390 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.4166186390
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.2171768614
Short name T346
Test name
Test status
Simulation time 2996147628 ps
CPU time 1.83 seconds
Started Apr 30 02:03:31 PM PDT 24
Finished Apr 30 02:03:34 PM PDT 24
Peak memory 183752 kb
Host smart-2540cd9f-693c-4f6c-bf8a-5738fbcd577a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171768614 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.ao
n_timer_same_csr_outstanding.2171768614
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.1282453561
Short name T298
Test name
Test status
Simulation time 461922963 ps
CPU time 2.62 seconds
Started Apr 30 02:03:29 PM PDT 24
Finished Apr 30 02:03:33 PM PDT 24
Peak memory 198492 kb
Host smart-f5e98e18-89fe-46f3-a176-877941d2cf77
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282453561 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.1282453561
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.3306362636
Short name T36
Test name
Test status
Simulation time 8087930279 ps
CPU time 13.06 seconds
Started Apr 30 02:03:29 PM PDT 24
Finished Apr 30 02:03:43 PM PDT 24
Peak memory 197992 kb
Host smart-bac9c811-0c7e-4a89-8161-e09ce9b70057
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306362636 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_t
l_intg_err.3306362636
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.4183973734
Short name T374
Test name
Test status
Simulation time 559420189 ps
CPU time 1.33 seconds
Started Apr 30 02:03:31 PM PDT 24
Finished Apr 30 02:03:33 PM PDT 24
Peak memory 195588 kb
Host smart-2554c4d6-34c9-459f-af5b-77a1cc61160d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183973734 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.4183973734
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.2007982151
Short name T399
Test name
Test status
Simulation time 469524531 ps
CPU time 0.62 seconds
Started Apr 30 02:03:28 PM PDT 24
Finished Apr 30 02:03:30 PM PDT 24
Peak memory 183520 kb
Host smart-0f35857d-1b3f-408a-b03c-7fbf980ece72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007982151 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.2007982151
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.2427963100
Short name T414
Test name
Test status
Simulation time 2153958516 ps
CPU time 3.57 seconds
Started Apr 30 02:03:30 PM PDT 24
Finished Apr 30 02:03:35 PM PDT 24
Peak memory 194324 kb
Host smart-528ead24-3b9c-4e9a-8027-ebf5f2298343
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427963100 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.ao
n_timer_same_csr_outstanding.2427963100
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.2687777806
Short name T302
Test name
Test status
Simulation time 595150135 ps
CPU time 1.99 seconds
Started Apr 30 02:03:29 PM PDT 24
Finished Apr 30 02:03:32 PM PDT 24
Peak memory 198432 kb
Host smart-7be8b9be-33fa-4a3a-9e24-aceaf6b689ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687777806 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.2687777806
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.1541279712
Short name T363
Test name
Test status
Simulation time 4657950574 ps
CPU time 2.55 seconds
Started Apr 30 02:03:28 PM PDT 24
Finished Apr 30 02:03:31 PM PDT 24
Peak memory 197332 kb
Host smart-999658a9-346d-45d3-865d-e6b63cd2ab60
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541279712 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_t
l_intg_err.1541279712
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.4293875763
Short name T397
Test name
Test status
Simulation time 475946298 ps
CPU time 1.29 seconds
Started Apr 30 02:03:29 PM PDT 24
Finished Apr 30 02:03:31 PM PDT 24
Peak memory 195580 kb
Host smart-ab8765ce-69ca-4b42-806c-86c5f858f650
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293875763 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.4293875763
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.3353452959
Short name T65
Test name
Test status
Simulation time 296082489 ps
CPU time 0.8 seconds
Started Apr 30 02:03:32 PM PDT 24
Finished Apr 30 02:03:33 PM PDT 24
Peak memory 183868 kb
Host smart-85c8afd8-56f7-48a6-80f0-1848a78d580b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353452959 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.3353452959
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.2843254240
Short name T357
Test name
Test status
Simulation time 443572040 ps
CPU time 1.26 seconds
Started Apr 30 02:03:31 PM PDT 24
Finished Apr 30 02:03:33 PM PDT 24
Peak memory 183548 kb
Host smart-945d45f8-9404-4bd6-a8a1-65493fbed792
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843254240 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.2843254240
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.1099728939
Short name T71
Test name
Test status
Simulation time 2624913935 ps
CPU time 2.35 seconds
Started Apr 30 02:03:30 PM PDT 24
Finished Apr 30 02:03:33 PM PDT 24
Peak memory 194528 kb
Host smart-08eec34b-5828-42cb-b8c0-530bad1b123a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099728939 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.ao
n_timer_same_csr_outstanding.1099728939
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.2383078042
Short name T306
Test name
Test status
Simulation time 761924648 ps
CPU time 2 seconds
Started Apr 30 02:03:37 PM PDT 24
Finished Apr 30 02:03:41 PM PDT 24
Peak memory 198376 kb
Host smart-a5bc9179-e3e8-47e5-9b49-e56476bc5ff8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383078042 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.2383078042
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.1900053152
Short name T372
Test name
Test status
Simulation time 4201332668 ps
CPU time 2.38 seconds
Started Apr 30 02:03:37 PM PDT 24
Finished Apr 30 02:03:41 PM PDT 24
Peak memory 197592 kb
Host smart-32a7fe4d-c2b1-4fa8-bab1-2ab846abd0d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900053152 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_t
l_intg_err.1900053152
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.3915957160
Short name T107
Test name
Test status
Simulation time 540140986 ps
CPU time 1.56 seconds
Started Apr 30 02:03:30 PM PDT 24
Finished Apr 30 02:03:32 PM PDT 24
Peak memory 195776 kb
Host smart-92b10a82-1870-40b1-8489-b0e881c0849d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915957160 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.3915957160
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.2323655710
Short name T393
Test name
Test status
Simulation time 408739396 ps
CPU time 0.66 seconds
Started Apr 30 02:03:31 PM PDT 24
Finished Apr 30 02:03:32 PM PDT 24
Peak memory 192992 kb
Host smart-6d48d6cb-b833-4d7a-8fad-746cba6415ee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323655710 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.2323655710
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.2686981677
Short name T349
Test name
Test status
Simulation time 404401413 ps
CPU time 0.86 seconds
Started Apr 30 02:03:31 PM PDT 24
Finished Apr 30 02:03:32 PM PDT 24
Peak memory 183564 kb
Host smart-d8b18e8e-f79e-4fb7-a472-8a03f8eedb95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686981677 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.2686981677
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.3531934297
Short name T72
Test name
Test status
Simulation time 2559659422 ps
CPU time 2.73 seconds
Started Apr 30 02:03:30 PM PDT 24
Finished Apr 30 02:03:33 PM PDT 24
Peak memory 191968 kb
Host smart-9ddcd462-4492-4adc-8b1f-2c293f0aa714
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531934297 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao
n_timer_same_csr_outstanding.3531934297
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.3569503369
Short name T369
Test name
Test status
Simulation time 1176558135 ps
CPU time 2.52 seconds
Started Apr 30 02:03:31 PM PDT 24
Finished Apr 30 02:03:34 PM PDT 24
Peak memory 198468 kb
Host smart-3b55e74b-fd38-419e-8fb4-1ff922e11be1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569503369 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.3569503369
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.1414962750
Short name T391
Test name
Test status
Simulation time 8610642719 ps
CPU time 4.41 seconds
Started Apr 30 02:03:31 PM PDT 24
Finished Apr 30 02:03:36 PM PDT 24
Peak memory 197824 kb
Host smart-bbb70d3f-c02d-437b-827b-77b3870ca6a1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414962750 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_t
l_intg_err.1414962750
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.1508691355
Short name T68
Test name
Test status
Simulation time 496051819 ps
CPU time 1.52 seconds
Started Apr 30 02:03:09 PM PDT 24
Finished Apr 30 02:03:11 PM PDT 24
Peak memory 183624 kb
Host smart-48caba0d-90f7-4001-b5fc-45b43429a42c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508691355 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_a
liasing.1508691355
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.3661179128
Short name T386
Test name
Test status
Simulation time 13990049393 ps
CPU time 21.86 seconds
Started Apr 30 02:03:12 PM PDT 24
Finished Apr 30 02:03:35 PM PDT 24
Peak memory 192180 kb
Host smart-81220849-fa5c-4064-80cb-d19cdc66eabe
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661179128 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_b
it_bash.3661179128
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.1461470983
Short name T299
Test name
Test status
Simulation time 784384565 ps
CPU time 1.18 seconds
Started Apr 30 02:03:09 PM PDT 24
Finished Apr 30 02:03:11 PM PDT 24
Peak memory 183628 kb
Host smart-0d4d6474-d8d3-4622-89ec-af2175cb31fe
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461470983 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_h
w_reset.1461470983
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.3703891804
Short name T305
Test name
Test status
Simulation time 396656907 ps
CPU time 1.26 seconds
Started Apr 30 02:03:12 PM PDT 24
Finished Apr 30 02:03:14 PM PDT 24
Peak memory 196468 kb
Host smart-efb594ba-0d9f-4f57-ae51-504e0801eb7c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703891804 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.3703891804
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.703745930
Short name T33
Test name
Test status
Simulation time 553424272 ps
CPU time 0.76 seconds
Started Apr 30 02:03:10 PM PDT 24
Finished Apr 30 02:03:11 PM PDT 24
Peak memory 183636 kb
Host smart-114d08c1-b189-4b94-90c0-a109a7ca73cf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703745930 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.703745930
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.1632228580
Short name T361
Test name
Test status
Simulation time 515737428 ps
CPU time 1.27 seconds
Started Apr 30 02:03:12 PM PDT 24
Finished Apr 30 02:03:14 PM PDT 24
Peak memory 183552 kb
Host smart-45779781-4661-4638-bf4f-fa84e5507be2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632228580 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.1632228580
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.42262141
Short name T388
Test name
Test status
Simulation time 301627543 ps
CPU time 0.73 seconds
Started Apr 30 02:03:07 PM PDT 24
Finished Apr 30 02:03:09 PM PDT 24
Peak memory 183508 kb
Host smart-af3b9552-d138-48b4-b037-6bef58a1b510
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42262141 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_
timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_tim
er_mem_partial_access.42262141
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.15046454
Short name T403
Test name
Test status
Simulation time 499148876 ps
CPU time 0.59 seconds
Started Apr 30 02:03:06 PM PDT 24
Finished Apr 30 02:03:07 PM PDT 24
Peak memory 183584 kb
Host smart-ff7f06f4-8be2-4b96-9c4c-6db4d9b556b6
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15046454 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_wal
k.15046454
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.1542392425
Short name T370
Test name
Test status
Simulation time 1309431371 ps
CPU time 2.42 seconds
Started Apr 30 02:03:12 PM PDT 24
Finished Apr 30 02:03:15 PM PDT 24
Peak memory 193136 kb
Host smart-a4d88e54-b176-4172-a47d-0f7f19c0e8ae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542392425 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon
_timer_same_csr_outstanding.1542392425
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.1228158720
Short name T371
Test name
Test status
Simulation time 968831850 ps
CPU time 2.23 seconds
Started Apr 30 02:03:07 PM PDT 24
Finished Apr 30 02:03:10 PM PDT 24
Peak memory 198432 kb
Host smart-f7f9df72-bbb4-471c-acb2-9def6ae98ab5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228158720 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.1228158720
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.3413914345
Short name T103
Test name
Test status
Simulation time 4105272729 ps
CPU time 2.4 seconds
Started Apr 30 02:03:11 PM PDT 24
Finished Apr 30 02:03:14 PM PDT 24
Peak memory 196600 kb
Host smart-a31b5b54-f935-47eb-a6f7-d6a91903ac02
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413914345 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl
_intg_err.3413914345
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.216865858
Short name T345
Test name
Test status
Simulation time 341102338 ps
CPU time 0.67 seconds
Started Apr 30 02:03:39 PM PDT 24
Finished Apr 30 02:03:41 PM PDT 24
Peak memory 183572 kb
Host smart-b531103c-8c79-40c8-8850-03bca6d84ca3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216865858 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.216865858
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.1648604380
Short name T320
Test name
Test status
Simulation time 418466989 ps
CPU time 0.68 seconds
Started Apr 30 02:03:41 PM PDT 24
Finished Apr 30 02:03:42 PM PDT 24
Peak memory 183548 kb
Host smart-0bee243a-7163-4fe7-a646-81a2d848462e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648604380 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.1648604380
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.557914829
Short name T408
Test name
Test status
Simulation time 428330428 ps
CPU time 0.72 seconds
Started Apr 30 02:03:38 PM PDT 24
Finished Apr 30 02:03:39 PM PDT 24
Peak memory 183536 kb
Host smart-14c2a183-8191-4e8d-bf35-70e6ab964cea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557914829 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.557914829
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.1182701
Short name T354
Test name
Test status
Simulation time 433887197 ps
CPU time 1.27 seconds
Started Apr 30 02:03:39 PM PDT 24
Finished Apr 30 02:03:41 PM PDT 24
Peak memory 183576 kb
Host smart-3d8e8620-b823-4350-b6b2-f99998d51815
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182701 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.1182701
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.3157654449
Short name T417
Test name
Test status
Simulation time 415691731 ps
CPU time 0.8 seconds
Started Apr 30 02:03:38 PM PDT 24
Finished Apr 30 02:03:40 PM PDT 24
Peak memory 183532 kb
Host smart-79c5c155-27c8-4608-bc47-b1ccad1c7b85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157654449 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.3157654449
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.3861918278
Short name T338
Test name
Test status
Simulation time 381005170 ps
CPU time 1.11 seconds
Started Apr 30 02:03:39 PM PDT 24
Finished Apr 30 02:03:41 PM PDT 24
Peak memory 183548 kb
Host smart-6df63509-4acd-40f5-882b-d217f0396f4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861918278 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.3861918278
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.3749837805
Short name T418
Test name
Test status
Simulation time 318796107 ps
CPU time 0.8 seconds
Started Apr 30 02:03:37 PM PDT 24
Finished Apr 30 02:03:39 PM PDT 24
Peak memory 183572 kb
Host smart-67eee68a-df3f-4de2-ab0e-293b6b39b09c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749837805 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.3749837805
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.2483566652
Short name T416
Test name
Test status
Simulation time 333883664 ps
CPU time 0.78 seconds
Started Apr 30 02:03:39 PM PDT 24
Finished Apr 30 02:03:41 PM PDT 24
Peak memory 183544 kb
Host smart-c8597477-7a41-4724-afdd-9824abb35c62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483566652 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.2483566652
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.1916849967
Short name T337
Test name
Test status
Simulation time 522640139 ps
CPU time 0.74 seconds
Started Apr 30 02:03:38 PM PDT 24
Finished Apr 30 02:03:40 PM PDT 24
Peak memory 183536 kb
Host smart-b8ff91c0-168c-49f8-bd4f-8d4572e9c2cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916849967 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.1916849967
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.2069886915
Short name T373
Test name
Test status
Simulation time 388277817 ps
CPU time 0.75 seconds
Started Apr 30 02:03:37 PM PDT 24
Finished Apr 30 02:03:39 PM PDT 24
Peak memory 183544 kb
Host smart-5d19cad2-1b50-4da8-b9e4-9992de828658
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069886915 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.2069886915
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.4257272234
Short name T63
Test name
Test status
Simulation time 439073847 ps
CPU time 0.96 seconds
Started Apr 30 02:03:15 PM PDT 24
Finished Apr 30 02:03:17 PM PDT 24
Peak memory 193148 kb
Host smart-a94ca960-6291-4e00-8aa0-fbd4c33f7f39
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257272234 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_a
liasing.4257272234
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.1889355141
Short name T58
Test name
Test status
Simulation time 3396098247 ps
CPU time 5.22 seconds
Started Apr 30 02:03:15 PM PDT 24
Finished Apr 30 02:03:20 PM PDT 24
Peak memory 192212 kb
Host smart-0f6934c2-a0a7-4788-a90b-688b46d1256c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889355141 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_b
it_bash.1889355141
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.1192624483
Short name T402
Test name
Test status
Simulation time 1171921309 ps
CPU time 1.03 seconds
Started Apr 30 02:03:08 PM PDT 24
Finished Apr 30 02:03:09 PM PDT 24
Peak memory 193132 kb
Host smart-6adf6df6-021d-48fa-92e0-2710787a9de3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192624483 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_h
w_reset.1192624483
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.2849429666
Short name T106
Test name
Test status
Simulation time 387931971 ps
CPU time 0.73 seconds
Started Apr 30 02:03:18 PM PDT 24
Finished Apr 30 02:03:20 PM PDT 24
Peak memory 195404 kb
Host smart-86a32be7-ba2b-4a30-b0e0-ace3675abb4b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849429666 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.2849429666
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.2098770250
Short name T57
Test name
Test status
Simulation time 546256435 ps
CPU time 0.93 seconds
Started Apr 30 02:03:17 PM PDT 24
Finished Apr 30 02:03:18 PM PDT 24
Peak memory 192980 kb
Host smart-d7c4f4b0-79e7-499b-b202-b66aa31f5112
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098770250 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.2098770250
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.2585627956
Short name T282
Test name
Test status
Simulation time 365224244 ps
CPU time 1.13 seconds
Started Apr 30 02:03:12 PM PDT 24
Finished Apr 30 02:03:13 PM PDT 24
Peak memory 183576 kb
Host smart-41a83296-7ae3-4b4a-9261-72d850754bf9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585627956 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.2585627956
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.1457003655
Short name T360
Test name
Test status
Simulation time 368999053 ps
CPU time 0.53 seconds
Started Apr 30 02:03:09 PM PDT 24
Finished Apr 30 02:03:10 PM PDT 24
Peak memory 183476 kb
Host smart-7bef5975-f02e-49d3-a0fb-72087c9fcae3
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457003655 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_t
imer_mem_partial_access.1457003655
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.1756375189
Short name T292
Test name
Test status
Simulation time 470750183 ps
CPU time 0.89 seconds
Started Apr 30 02:03:07 PM PDT 24
Finished Apr 30 02:03:09 PM PDT 24
Peak memory 183548 kb
Host smart-0463fe8c-eaa0-4414-a1ca-bcd31e0dc0d4
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756375189 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_w
alk.1756375189
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.1642851866
Short name T342
Test name
Test status
Simulation time 2752231451 ps
CPU time 5.52 seconds
Started Apr 30 02:03:20 PM PDT 24
Finished Apr 30 02:03:26 PM PDT 24
Peak memory 194496 kb
Host smart-54f0d983-094a-4672-b00d-f0eb3c2bd17f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642851866 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon
_timer_same_csr_outstanding.1642851866
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.4222549836
Short name T368
Test name
Test status
Simulation time 577919493 ps
CPU time 1.58 seconds
Started Apr 30 02:03:09 PM PDT 24
Finished Apr 30 02:03:11 PM PDT 24
Peak memory 198444 kb
Host smart-128bcd2b-eb62-4ea2-8487-24020db0ea5a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222549836 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.4222549836
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.394993330
Short name T104
Test name
Test status
Simulation time 7886128302 ps
CPU time 13.98 seconds
Started Apr 30 02:03:07 PM PDT 24
Finished Apr 30 02:03:22 PM PDT 24
Peak memory 197848 kb
Host smart-d00f464e-aa77-4350-a37b-c9b4e8c4a8ae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394993330 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_
intg_err.394993330
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.1436059193
Short name T351
Test name
Test status
Simulation time 427557740 ps
CPU time 0.69 seconds
Started Apr 30 02:03:37 PM PDT 24
Finished Apr 30 02:03:38 PM PDT 24
Peak memory 183488 kb
Host smart-18bba13a-520b-4d5d-86c1-4a592c6bee45
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436059193 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.1436059193
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.1354755508
Short name T390
Test name
Test status
Simulation time 297487083 ps
CPU time 0.98 seconds
Started Apr 30 02:03:39 PM PDT 24
Finished Apr 30 02:03:41 PM PDT 24
Peak memory 183544 kb
Host smart-5fb6dac7-ac3d-4044-a8a8-d10fe820be74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354755508 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.1354755508
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.980267964
Short name T330
Test name
Test status
Simulation time 377880200 ps
CPU time 1.07 seconds
Started Apr 30 02:03:37 PM PDT 24
Finished Apr 30 02:03:38 PM PDT 24
Peak memory 183560 kb
Host smart-45ae5543-1e63-436d-8f67-93df7839adb7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980267964 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.980267964
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.192759860
Short name T385
Test name
Test status
Simulation time 300843641 ps
CPU time 0.73 seconds
Started Apr 30 02:03:38 PM PDT 24
Finished Apr 30 02:03:40 PM PDT 24
Peak memory 183572 kb
Host smart-6270c68c-07e3-408d-ab3c-5250188fd542
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192759860 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.192759860
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.4024415689
Short name T367
Test name
Test status
Simulation time 489928742 ps
CPU time 1.04 seconds
Started Apr 30 02:03:41 PM PDT 24
Finished Apr 30 02:03:43 PM PDT 24
Peak memory 183528 kb
Host smart-f57dd280-452d-46e9-8b2e-677e7e584770
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024415689 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.4024415689
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.2012975804
Short name T381
Test name
Test status
Simulation time 345477643 ps
CPU time 0.8 seconds
Started Apr 30 02:03:38 PM PDT 24
Finished Apr 30 02:03:40 PM PDT 24
Peak memory 183556 kb
Host smart-59479f31-09ff-46fb-ac4d-a68c85a52022
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012975804 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.2012975804
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.3511488102
Short name T288
Test name
Test status
Simulation time 472300634 ps
CPU time 1.15 seconds
Started Apr 30 02:03:37 PM PDT 24
Finished Apr 30 02:03:39 PM PDT 24
Peak memory 183536 kb
Host smart-1385b592-dd84-4195-9373-8367a16863fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511488102 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.3511488102
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.620899915
Short name T348
Test name
Test status
Simulation time 462189992 ps
CPU time 0.69 seconds
Started Apr 30 02:03:37 PM PDT 24
Finished Apr 30 02:03:39 PM PDT 24
Peak memory 183576 kb
Host smart-72b862c1-96ff-4ecf-8c42-e895b26c90ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620899915 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.620899915
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.1079383586
Short name T420
Test name
Test status
Simulation time 429808912 ps
CPU time 0.8 seconds
Started Apr 30 02:03:36 PM PDT 24
Finished Apr 30 02:03:37 PM PDT 24
Peak memory 183560 kb
Host smart-c5766b50-6df1-4bed-909c-6fb50c34e3b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079383586 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.1079383586
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.2993374125
Short name T415
Test name
Test status
Simulation time 420088936 ps
CPU time 0.87 seconds
Started Apr 30 02:03:39 PM PDT 24
Finished Apr 30 02:03:40 PM PDT 24
Peak memory 183572 kb
Host smart-421cda3e-b850-48b8-86e6-4af7facad88f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993374125 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.2993374125
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.553149823
Short name T344
Test name
Test status
Simulation time 636460796 ps
CPU time 1.19 seconds
Started Apr 30 02:03:19 PM PDT 24
Finished Apr 30 02:03:21 PM PDT 24
Peak memory 183648 kb
Host smart-b8fb4256-5b3b-4816-ae0f-116768443bfd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553149823 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_al
iasing.553149823
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.95680393
Short name T319
Test name
Test status
Simulation time 6895004066 ps
CPU time 5.89 seconds
Started Apr 30 02:03:17 PM PDT 24
Finished Apr 30 02:03:23 PM PDT 24
Peak memory 192156 kb
Host smart-d431f222-b6ef-4632-a787-f39ed8577db2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95680393 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_bit
_bash.95680393
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.4224301724
Short name T406
Test name
Test status
Simulation time 1139221582 ps
CPU time 0.99 seconds
Started Apr 30 02:03:17 PM PDT 24
Finished Apr 30 02:03:18 PM PDT 24
Peak memory 183700 kb
Host smart-f2954857-ba7b-4e0a-a99d-37a181664880
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224301724 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_h
w_reset.4224301724
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.2742821719
Short name T323
Test name
Test status
Simulation time 355195518 ps
CPU time 1.17 seconds
Started Apr 30 02:03:19 PM PDT 24
Finished Apr 30 02:03:21 PM PDT 24
Peak memory 195740 kb
Host smart-ef1f99bd-9877-4d04-9db1-b5d9ea1cebd8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742821719 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.2742821719
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.2308405515
Short name T392
Test name
Test status
Simulation time 424561119 ps
CPU time 0.72 seconds
Started Apr 30 02:03:18 PM PDT 24
Finished Apr 30 02:03:19 PM PDT 24
Peak memory 183600 kb
Host smart-c230d3f7-3f11-42a6-b4c1-8d2ab60d2c89
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308405515 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.2308405515
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.4251224513
Short name T377
Test name
Test status
Simulation time 309236749 ps
CPU time 0.76 seconds
Started Apr 30 02:03:17 PM PDT 24
Finished Apr 30 02:03:18 PM PDT 24
Peak memory 183556 kb
Host smart-b3e95d7a-499c-4a21-94e1-1cb444e3e349
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251224513 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.4251224513
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.3461522080
Short name T380
Test name
Test status
Simulation time 322913012 ps
CPU time 0.56 seconds
Started Apr 30 02:03:20 PM PDT 24
Finished Apr 30 02:03:21 PM PDT 24
Peak memory 183508 kb
Host smart-7566e7bb-f653-4074-adb8-ef304d926ab7
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461522080 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_t
imer_mem_partial_access.3461522080
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.2650982247
Short name T294
Test name
Test status
Simulation time 392566255 ps
CPU time 0.6 seconds
Started Apr 30 02:03:19 PM PDT 24
Finished Apr 30 02:03:20 PM PDT 24
Peak memory 183520 kb
Host smart-1543b20f-f282-46e8-bd16-f35951de28bd
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650982247 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_w
alk.2650982247
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.1106744077
Short name T412
Test name
Test status
Simulation time 2645139688 ps
CPU time 1.23 seconds
Started Apr 30 02:03:17 PM PDT 24
Finished Apr 30 02:03:19 PM PDT 24
Peak memory 194388 kb
Host smart-da4bca8b-6366-4158-b8bf-f777213c6fc2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106744077 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon
_timer_same_csr_outstanding.1106744077
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.2561674445
Short name T356
Test name
Test status
Simulation time 569519074 ps
CPU time 1.05 seconds
Started Apr 30 02:03:19 PM PDT 24
Finished Apr 30 02:03:21 PM PDT 24
Peak memory 197312 kb
Host smart-856a3d1c-216d-4ef8-9f77-ce6ceefe370f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561674445 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.2561674445
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.3133899894
Short name T383
Test name
Test status
Simulation time 4630385126 ps
CPU time 4.67 seconds
Started Apr 30 02:03:24 PM PDT 24
Finished Apr 30 02:03:30 PM PDT 24
Peak memory 197552 kb
Host smart-86fb86dc-a8ea-483d-a7cf-f7fea4e8fd4b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133899894 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl
_intg_err.3133899894
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.3217660107
Short name T286
Test name
Test status
Simulation time 348191417 ps
CPU time 1.03 seconds
Started Apr 30 02:03:36 PM PDT 24
Finished Apr 30 02:03:37 PM PDT 24
Peak memory 183580 kb
Host smart-625c2f57-1346-4135-b62a-a4be08e4cbca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217660107 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.3217660107
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.2030185220
Short name T289
Test name
Test status
Simulation time 467727743 ps
CPU time 0.73 seconds
Started Apr 30 02:03:47 PM PDT 24
Finished Apr 30 02:03:49 PM PDT 24
Peak memory 183544 kb
Host smart-c8a99cd1-0317-4682-a490-54f370672dcb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030185220 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.2030185220
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.613424897
Short name T328
Test name
Test status
Simulation time 273477431 ps
CPU time 0.88 seconds
Started Apr 30 02:03:47 PM PDT 24
Finished Apr 30 02:03:49 PM PDT 24
Peak memory 183532 kb
Host smart-b27c9758-9d4c-4bac-b9da-650e4d708b84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613424897 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.613424897
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.220764322
Short name T347
Test name
Test status
Simulation time 320070983 ps
CPU time 0.63 seconds
Started Apr 30 02:03:47 PM PDT 24
Finished Apr 30 02:03:48 PM PDT 24
Peak memory 183564 kb
Host smart-f9c8a9fc-60ce-4f66-a180-ef77f9370a7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220764322 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.220764322
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.2767068553
Short name T410
Test name
Test status
Simulation time 456674394 ps
CPU time 0.73 seconds
Started Apr 30 02:03:48 PM PDT 24
Finished Apr 30 02:03:49 PM PDT 24
Peak memory 183532 kb
Host smart-5d578f89-6f39-4012-9f65-6a73f72441e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767068553 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.2767068553
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.4101155328
Short name T301
Test name
Test status
Simulation time 518944818 ps
CPU time 1.35 seconds
Started Apr 30 02:03:47 PM PDT 24
Finished Apr 30 02:03:49 PM PDT 24
Peak memory 183548 kb
Host smart-3c7a306c-d326-4d9c-b62f-5d1e1f5916cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101155328 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.4101155328
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.64621642
Short name T283
Test name
Test status
Simulation time 543680280 ps
CPU time 0.74 seconds
Started Apr 30 02:03:48 PM PDT 24
Finished Apr 30 02:03:50 PM PDT 24
Peak memory 183548 kb
Host smart-b817cfff-8425-49a5-9fdc-fb9b91f10aa2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64621642 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.64621642
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.1343752570
Short name T285
Test name
Test status
Simulation time 349410095 ps
CPU time 1.1 seconds
Started Apr 30 02:03:47 PM PDT 24
Finished Apr 30 02:03:49 PM PDT 24
Peak memory 183564 kb
Host smart-0aa275e5-0416-4e6f-b5ae-853e2489c3ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343752570 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.1343752570
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.2449072906
Short name T309
Test name
Test status
Simulation time 310775973 ps
CPU time 0.6 seconds
Started Apr 30 02:03:49 PM PDT 24
Finished Apr 30 02:03:50 PM PDT 24
Peak memory 183512 kb
Host smart-2abd922c-54e4-4b87-9ba3-fcd04644df58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449072906 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.2449072906
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.577258039
Short name T335
Test name
Test status
Simulation time 447002602 ps
CPU time 0.79 seconds
Started Apr 30 02:03:47 PM PDT 24
Finished Apr 30 02:03:48 PM PDT 24
Peak memory 183532 kb
Host smart-830d8a9d-cdce-4939-9351-b9e230d576a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577258039 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.577258039
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.2701716239
Short name T314
Test name
Test status
Simulation time 629502350 ps
CPU time 0.94 seconds
Started Apr 30 02:03:17 PM PDT 24
Finished Apr 30 02:03:18 PM PDT 24
Peak memory 196772 kb
Host smart-8b1a80af-e653-448d-9707-bcce6f2b931d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701716239 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.2701716239
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.2531472007
Short name T70
Test name
Test status
Simulation time 580933189 ps
CPU time 0.68 seconds
Started Apr 30 02:03:17 PM PDT 24
Finished Apr 30 02:03:18 PM PDT 24
Peak memory 183908 kb
Host smart-caf14774-296a-4765-8c43-0565eeb7cb6f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531472007 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.2531472007
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.175310321
Short name T389
Test name
Test status
Simulation time 460942493 ps
CPU time 0.74 seconds
Started Apr 30 02:03:18 PM PDT 24
Finished Apr 30 02:03:19 PM PDT 24
Peak memory 183524 kb
Host smart-7db97f51-2bdf-4211-aff8-7a9d1c8a9f11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175310321 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.175310321
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.4145360306
Short name T355
Test name
Test status
Simulation time 2350903539 ps
CPU time 5.14 seconds
Started Apr 30 02:03:17 PM PDT 24
Finished Apr 30 02:03:23 PM PDT 24
Peak memory 194668 kb
Host smart-4ffbd3ca-ea4e-4c4a-a212-8adb6ef99918
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145360306 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon
_timer_same_csr_outstanding.4145360306
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.595288649
Short name T405
Test name
Test status
Simulation time 666335741 ps
CPU time 2.02 seconds
Started Apr 30 02:03:24 PM PDT 24
Finished Apr 30 02:03:27 PM PDT 24
Peak memory 198472 kb
Host smart-32a46418-be89-44db-953a-7825dc3e11b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595288649 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.595288649
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.3461303010
Short name T396
Test name
Test status
Simulation time 4572839151 ps
CPU time 2.75 seconds
Started Apr 30 02:03:16 PM PDT 24
Finished Apr 30 02:03:19 PM PDT 24
Peak memory 197452 kb
Host smart-e5b3ff1b-32ba-4330-a846-549905aa8a6c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461303010 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl
_intg_err.3461303010
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.620186026
Short name T325
Test name
Test status
Simulation time 331977037 ps
CPU time 1.07 seconds
Started Apr 30 02:03:16 PM PDT 24
Finished Apr 30 02:03:18 PM PDT 24
Peak memory 195628 kb
Host smart-fe555d3a-da62-4a5d-ab48-8724b1ef523c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620186026 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.620186026
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.1827866849
Short name T60
Test name
Test status
Simulation time 608616594 ps
CPU time 0.57 seconds
Started Apr 30 02:03:19 PM PDT 24
Finished Apr 30 02:03:20 PM PDT 24
Peak memory 183596 kb
Host smart-0c5c39f7-4143-47e3-a68d-76153616788c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827866849 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.1827866849
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.2627195819
Short name T300
Test name
Test status
Simulation time 465218596 ps
CPU time 0.59 seconds
Started Apr 30 02:03:20 PM PDT 24
Finished Apr 30 02:03:21 PM PDT 24
Peak memory 183524 kb
Host smart-ea6ab543-f89d-46d8-be1a-dbf66c194fcb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627195819 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.2627195819
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.1661508073
Short name T322
Test name
Test status
Simulation time 2655576119 ps
CPU time 3.64 seconds
Started Apr 30 02:03:17 PM PDT 24
Finished Apr 30 02:03:21 PM PDT 24
Peak memory 183812 kb
Host smart-ce9d90bf-8d64-4f0f-9a28-ea1cba5d8eb0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661508073 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon
_timer_same_csr_outstanding.1661508073
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.3260204448
Short name T350
Test name
Test status
Simulation time 450198250 ps
CPU time 1.27 seconds
Started Apr 30 02:03:18 PM PDT 24
Finished Apr 30 02:03:20 PM PDT 24
Peak memory 198416 kb
Host smart-f6efa218-b1d9-4bef-8ede-3cdfb1b1f762
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260204448 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.3260204448
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.4082204723
Short name T387
Test name
Test status
Simulation time 8188661805 ps
CPU time 13.08 seconds
Started Apr 30 02:03:20 PM PDT 24
Finished Apr 30 02:03:34 PM PDT 24
Peak memory 197816 kb
Host smart-f2d613da-ef35-4267-b76d-fc09f1b05ef0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082204723 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl
_intg_err.4082204723
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.660125144
Short name T105
Test name
Test status
Simulation time 465270016 ps
CPU time 1.04 seconds
Started Apr 30 02:03:17 PM PDT 24
Finished Apr 30 02:03:19 PM PDT 24
Peak memory 197112 kb
Host smart-5a02ee26-c08a-4f4e-9d81-36d4a537eb61
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660125144 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.660125144
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.552674333
Short name T331
Test name
Test status
Simulation time 494042729 ps
CPU time 1.28 seconds
Started Apr 30 02:03:20 PM PDT 24
Finished Apr 30 02:03:22 PM PDT 24
Peak memory 183584 kb
Host smart-b93b1a0f-1477-4d60-bf46-ce626da8dbce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552674333 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.552674333
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.4113288063
Short name T324
Test name
Test status
Simulation time 501617358 ps
CPU time 0.68 seconds
Started Apr 30 02:03:16 PM PDT 24
Finished Apr 30 02:03:18 PM PDT 24
Peak memory 183560 kb
Host smart-a1eb021b-66c9-4a87-b77c-2632903711fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113288063 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.4113288063
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.222005993
Short name T315
Test name
Test status
Simulation time 1969265316 ps
CPU time 1.04 seconds
Started Apr 30 02:03:18 PM PDT 24
Finished Apr 30 02:03:20 PM PDT 24
Peak memory 194200 kb
Host smart-4012ddf5-24b3-4f71-8271-dda919641261
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222005993 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_
timer_same_csr_outstanding.222005993
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.25958690
Short name T358
Test name
Test status
Simulation time 949098342 ps
CPU time 2.21 seconds
Started Apr 30 02:03:14 PM PDT 24
Finished Apr 30 02:03:17 PM PDT 24
Peak memory 198464 kb
Host smart-dc62cb10-c275-4a33-90d5-7f7e092e2091
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25958690 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.25958690
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.784246202
Short name T395
Test name
Test status
Simulation time 5045009854 ps
CPU time 2.02 seconds
Started Apr 30 02:03:16 PM PDT 24
Finished Apr 30 02:03:19 PM PDT 24
Peak memory 197560 kb
Host smart-30f0b400-13e5-4e12-bc1c-a997b72840d7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784246202 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_
intg_err.784246202
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.1886660180
Short name T307
Test name
Test status
Simulation time 586681898 ps
CPU time 0.97 seconds
Started Apr 30 02:03:19 PM PDT 24
Finished Apr 30 02:03:20 PM PDT 24
Peak memory 197704 kb
Host smart-9cce121c-2b0d-4bb4-bfe0-b29bfe3b8ca7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886660180 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.1886660180
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.228198831
Short name T308
Test name
Test status
Simulation time 427962039 ps
CPU time 0.68 seconds
Started Apr 30 02:03:20 PM PDT 24
Finished Apr 30 02:03:21 PM PDT 24
Peak memory 183584 kb
Host smart-d8f33bb1-4f56-4c9a-99da-2c2d6bf38a14
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228198831 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.228198831
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.2555217849
Short name T411
Test name
Test status
Simulation time 409453127 ps
CPU time 0.61 seconds
Started Apr 30 02:03:17 PM PDT 24
Finished Apr 30 02:03:18 PM PDT 24
Peak memory 183528 kb
Host smart-e1094a12-cb3e-4184-bfdf-f439fe7094cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555217849 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.2555217849
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.1150352476
Short name T327
Test name
Test status
Simulation time 1173443857 ps
CPU time 0.81 seconds
Started Apr 30 02:03:18 PM PDT 24
Finished Apr 30 02:03:19 PM PDT 24
Peak memory 183664 kb
Host smart-d91ef387-9219-4c9b-8f63-612398d22be1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150352476 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon
_timer_same_csr_outstanding.1150352476
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.3977580245
Short name T311
Test name
Test status
Simulation time 440411318 ps
CPU time 1.88 seconds
Started Apr 30 02:03:18 PM PDT 24
Finished Apr 30 02:03:21 PM PDT 24
Peak memory 198408 kb
Host smart-ab5ed958-9755-4cdb-8f8a-e7c033b61495
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977580245 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.3977580245
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.4011566966
Short name T336
Test name
Test status
Simulation time 5109186383 ps
CPU time 1.34 seconds
Started Apr 30 02:03:17 PM PDT 24
Finished Apr 30 02:03:19 PM PDT 24
Peak memory 196348 kb
Host smart-276d3e8a-6011-486b-a9fd-8cfd895a19a2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011566966 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl
_intg_err.4011566966
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.3250147186
Short name T312
Test name
Test status
Simulation time 461602428 ps
CPU time 1.32 seconds
Started Apr 30 02:03:25 PM PDT 24
Finished Apr 30 02:03:27 PM PDT 24
Peak memory 196452 kb
Host smart-f69aac74-a6bb-49d3-8c61-f189a5d8ebed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250147186 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.3250147186
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.2478739797
Short name T382
Test name
Test status
Simulation time 530440607 ps
CPU time 0.81 seconds
Started Apr 30 02:03:24 PM PDT 24
Finished Apr 30 02:03:26 PM PDT 24
Peak memory 193008 kb
Host smart-d4daa2c1-99b2-40f6-abd0-37decbfea36f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478739797 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.2478739797
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.746844462
Short name T291
Test name
Test status
Simulation time 341827374 ps
CPU time 0.66 seconds
Started Apr 30 02:03:23 PM PDT 24
Finished Apr 30 02:03:24 PM PDT 24
Peak memory 183528 kb
Host smart-84ce15d4-7931-4571-b792-17cffa733513
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746844462 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.746844462
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.4004545106
Short name T419
Test name
Test status
Simulation time 2816970588 ps
CPU time 6.3 seconds
Started Apr 30 02:03:24 PM PDT 24
Finished Apr 30 02:03:31 PM PDT 24
Peak memory 194400 kb
Host smart-8d23708d-d0ab-44a5-aed2-3eee7834e297
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004545106 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon
_timer_same_csr_outstanding.4004545106
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.4224411476
Short name T290
Test name
Test status
Simulation time 606409693 ps
CPU time 1.49 seconds
Started Apr 30 02:03:22 PM PDT 24
Finished Apr 30 02:03:24 PM PDT 24
Peak memory 198392 kb
Host smart-825cc3af-6568-477f-a88f-92e84b3d4d14
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224411476 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.4224411476
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.352304680
Short name T341
Test name
Test status
Simulation time 4607639679 ps
CPU time 2.73 seconds
Started Apr 30 02:03:22 PM PDT 24
Finished Apr 30 02:03:26 PM PDT 24
Peak memory 197556 kb
Host smart-75003fc6-9d80-4d5f-91a4-8e64c0eec8fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352304680 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_
intg_err.352304680
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_jump.1307411865
Short name T273
Test name
Test status
Simulation time 596261829 ps
CPU time 0.68 seconds
Started Apr 30 02:02:05 PM PDT 24
Finished Apr 30 02:02:06 PM PDT 24
Peak memory 183484 kb
Host smart-24ac61e2-7c7a-4ba3-9e36-d18124cfe28a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307411865 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.1307411865
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.3046973953
Short name T51
Test name
Test status
Simulation time 51889549631 ps
CPU time 63.67 seconds
Started Apr 30 02:02:08 PM PDT 24
Finished Apr 30 02:03:12 PM PDT 24
Peak memory 183632 kb
Host smart-efc02a29-434b-4f03-a317-fa3bf3832bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046973953 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.3046973953
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.2160790881
Short name T268
Test name
Test status
Simulation time 615490176 ps
CPU time 0.59 seconds
Started Apr 30 02:02:05 PM PDT 24
Finished Apr 30 02:02:06 PM PDT 24
Peak memory 183508 kb
Host smart-14100496-8d1c-476b-8285-28a6844aec10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160790881 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.2160790881
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.3533799358
Short name T261
Test name
Test status
Simulation time 109615671468 ps
CPU time 83.86 seconds
Started Apr 30 02:02:08 PM PDT 24
Finished Apr 30 02:03:32 PM PDT 24
Peak memory 195024 kb
Host smart-1fd497b3-0bc2-491c-a12a-b118911c75a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533799358 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_a
ll.3533799358
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.4021193057
Short name T241
Test name
Test status
Simulation time 257969798359 ps
CPU time 720.33 seconds
Started Apr 30 02:02:09 PM PDT 24
Finished Apr 30 02:14:09 PM PDT 24
Peak memory 201300 kb
Host smart-44a028dd-1df0-4893-8afc-259b78e29cd8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021193057 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.4021193057
Directory /workspace/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.aon_timer_jump.3363212637
Short name T48
Test name
Test status
Simulation time 445096843 ps
CPU time 0.68 seconds
Started Apr 30 02:02:09 PM PDT 24
Finished Apr 30 02:02:10 PM PDT 24
Peak memory 183564 kb
Host smart-53373248-ab29-47e8-9ce4-16fb5079c6ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363212637 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.3363212637
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.219536642
Short name T264
Test name
Test status
Simulation time 28291857903 ps
CPU time 4.49 seconds
Started Apr 30 02:02:09 PM PDT 24
Finished Apr 30 02:02:14 PM PDT 24
Peak memory 183632 kb
Host smart-da05fcb4-ca7c-4fdc-9830-8fde3eb21440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219536642 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.219536642
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.1424691333
Short name T18
Test name
Test status
Simulation time 4080536671 ps
CPU time 6.76 seconds
Started Apr 30 02:02:10 PM PDT 24
Finished Apr 30 02:02:17 PM PDT 24
Peak memory 214936 kb
Host smart-cb4d9739-6cad-4f82-a79e-8a20054a9471
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424691333 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.1424691333
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.3702217114
Short name T271
Test name
Test status
Simulation time 566657690 ps
CPU time 1.34 seconds
Started Apr 30 02:02:11 PM PDT 24
Finished Apr 30 02:02:12 PM PDT 24
Peak memory 183576 kb
Host smart-ddc30087-b782-4d3c-bcd5-8b9e5ef55700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702217114 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.3702217114
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.1041992790
Short name T98
Test name
Test status
Simulation time 24772157862 ps
CPU time 9.81 seconds
Started Apr 30 02:02:10 PM PDT 24
Finished Apr 30 02:02:20 PM PDT 24
Peak memory 194432 kb
Host smart-6052ead1-9418-4591-8eae-1ae73dd273c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041992790 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_a
ll.1041992790
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/10.aon_timer_jump.8823528
Short name T212
Test name
Test status
Simulation time 541181471 ps
CPU time 0.75 seconds
Started Apr 30 02:02:19 PM PDT 24
Finished Apr 30 02:02:20 PM PDT 24
Peak memory 183548 kb
Host smart-ba2ffdee-e1f2-457f-a33e-4bc2292cc52f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8823528 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.8823528
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.4028762562
Short name T164
Test name
Test status
Simulation time 27025081027 ps
CPU time 11.33 seconds
Started Apr 30 02:02:19 PM PDT 24
Finished Apr 30 02:02:30 PM PDT 24
Peak memory 183560 kb
Host smart-a49dc30f-fe0c-487c-a230-25314fc4997d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028762562 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.4028762562
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.2680177175
Short name T178
Test name
Test status
Simulation time 415797322 ps
CPU time 1.13 seconds
Started Apr 30 02:02:16 PM PDT 24
Finished Apr 30 02:02:17 PM PDT 24
Peak memory 183572 kb
Host smart-2fb79d5c-f8f0-42af-b500-3753e1e87461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680177175 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.2680177175
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.3931784431
Short name T266
Test name
Test status
Simulation time 193696874015 ps
CPU time 302.63 seconds
Started Apr 30 02:02:16 PM PDT 24
Finished Apr 30 02:07:19 PM PDT 24
Peak memory 183536 kb
Host smart-4ee119e1-0c3c-4893-b772-f5f448f240ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931784431 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_
all.3931784431
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.747989975
Short name T248
Test name
Test status
Simulation time 216167662283 ps
CPU time 588.09 seconds
Started Apr 30 02:02:15 PM PDT 24
Finished Apr 30 02:12:04 PM PDT 24
Peak memory 199576 kb
Host smart-22eccf82-6b95-40ff-bac5-8211b4854b8d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747989975 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.747989975
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.aon_timer_jump.2674915607
Short name T227
Test name
Test status
Simulation time 434029307 ps
CPU time 1.14 seconds
Started Apr 30 02:02:16 PM PDT 24
Finished Apr 30 02:02:18 PM PDT 24
Peak memory 183480 kb
Host smart-a808fb18-f8f2-4f5d-bfed-c573fee55f6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674915607 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.2674915607
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.4065985412
Short name T272
Test name
Test status
Simulation time 352609694 ps
CPU time 0.83 seconds
Started Apr 30 02:02:17 PM PDT 24
Finished Apr 30 02:02:18 PM PDT 24
Peak memory 183564 kb
Host smart-fbc6e087-ecaa-44b2-a90f-5bcd9606018e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065985412 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.4065985412
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.613640096
Short name T262
Test name
Test status
Simulation time 321960659747 ps
CPU time 139.51 seconds
Started Apr 30 02:02:27 PM PDT 24
Finished Apr 30 02:04:47 PM PDT 24
Peak memory 183624 kb
Host smart-3576cb9f-be8f-4765-866c-f4522e54daab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613640096 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_a
ll.613640096
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.1856143080
Short name T206
Test name
Test status
Simulation time 1261253386048 ps
CPU time 556.35 seconds
Started Apr 30 02:02:18 PM PDT 24
Finished Apr 30 02:11:35 PM PDT 24
Peak memory 199312 kb
Host smart-4319d60e-9389-405f-90f4-da738a19cd89
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856143080 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand_reset.1856143080
Directory /workspace/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.aon_timer_jump.2886165791
Short name T31
Test name
Test status
Simulation time 600869380 ps
CPU time 1.01 seconds
Started Apr 30 02:02:25 PM PDT 24
Finished Apr 30 02:02:27 PM PDT 24
Peak memory 183548 kb
Host smart-3a9b6666-250b-483d-b816-4269a0cc48ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886165791 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.2886165791
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.3963681103
Short name T233
Test name
Test status
Simulation time 27167190260 ps
CPU time 7.67 seconds
Started Apr 30 02:02:28 PM PDT 24
Finished Apr 30 02:02:36 PM PDT 24
Peak memory 191736 kb
Host smart-eb1b69a0-5d18-415c-8066-5af747ad1a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963681103 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.3963681103
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.2955317037
Short name T165
Test name
Test status
Simulation time 412935780 ps
CPU time 1.14 seconds
Started Apr 30 02:02:28 PM PDT 24
Finished Apr 30 02:02:30 PM PDT 24
Peak memory 183496 kb
Host smart-2434e3d7-1525-4847-97e6-7cdb9a42e473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955317037 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.2955317037
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_jump.704207027
Short name T200
Test name
Test status
Simulation time 490382898 ps
CPU time 0.94 seconds
Started Apr 30 02:02:28 PM PDT 24
Finished Apr 30 02:02:29 PM PDT 24
Peak memory 183484 kb
Host smart-c15ad348-df75-4459-8727-45e950b94817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704207027 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.704207027
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.2813398193
Short name T53
Test name
Test status
Simulation time 30897691077 ps
CPU time 46.12 seconds
Started Apr 30 02:02:27 PM PDT 24
Finished Apr 30 02:03:14 PM PDT 24
Peak memory 183628 kb
Host smart-6b9ad826-a32d-4263-a390-0cf59d98c93a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813398193 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.2813398193
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.3362179632
Short name T218
Test name
Test status
Simulation time 586203008 ps
CPU time 1.4 seconds
Started Apr 30 02:02:28 PM PDT 24
Finished Apr 30 02:02:30 PM PDT 24
Peak memory 183532 kb
Host smart-55191880-44ee-4609-8886-d440f318bf85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362179632 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.3362179632
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.3358769895
Short name T185
Test name
Test status
Simulation time 48517356166 ps
CPU time 419.59 seconds
Started Apr 30 02:02:28 PM PDT 24
Finished Apr 30 02:09:28 PM PDT 24
Peak memory 198532 kb
Host smart-6c5b4436-3a5c-416b-a639-5f15b8f74b7b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358769895 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.3358769895
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.aon_timer_jump.1871659677
Short name T115
Test name
Test status
Simulation time 425652287 ps
CPU time 0.93 seconds
Started Apr 30 02:02:31 PM PDT 24
Finished Apr 30 02:02:32 PM PDT 24
Peak memory 183568 kb
Host smart-4fe14b90-4aec-4da8-a467-7593e0359192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871659677 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.1871659677
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.2568021365
Short name T30
Test name
Test status
Simulation time 59495737542 ps
CPU time 23.05 seconds
Started Apr 30 02:02:27 PM PDT 24
Finished Apr 30 02:02:51 PM PDT 24
Peak memory 191832 kb
Host smart-cbaea9f9-e898-49b6-ad55-f4089a662cb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568021365 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.2568021365
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.2470446883
Short name T24
Test name
Test status
Simulation time 561390213 ps
CPU time 0.74 seconds
Started Apr 30 02:02:27 PM PDT 24
Finished Apr 30 02:02:28 PM PDT 24
Peak memory 183528 kb
Host smart-4ad16deb-c51b-406f-8005-523cb727d5ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470446883 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.2470446883
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.1037415029
Short name T246
Test name
Test status
Simulation time 438985843705 ps
CPU time 780.47 seconds
Started Apr 30 02:02:28 PM PDT 24
Finished Apr 30 02:15:29 PM PDT 24
Peak memory 195184 kb
Host smart-476eefd1-169f-4c7b-a25b-22f10211428d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037415029 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_
all.1037415029
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.1287949892
Short name T160
Test name
Test status
Simulation time 219777672268 ps
CPU time 490.71 seconds
Started Apr 30 02:02:27 PM PDT 24
Finished Apr 30 02:10:38 PM PDT 24
Peak memory 198456 kb
Host smart-bb6f805c-e733-464a-941d-eef75404cd0a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287949892 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.1287949892
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.aon_timer_jump.4132839292
Short name T122
Test name
Test status
Simulation time 470871149 ps
CPU time 0.71 seconds
Started Apr 30 02:02:25 PM PDT 24
Finished Apr 30 02:02:27 PM PDT 24
Peak memory 183548 kb
Host smart-e7526e54-2490-40d4-a125-f89923975986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132839292 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.4132839292
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.4149076061
Short name T197
Test name
Test status
Simulation time 6922472473 ps
CPU time 7.12 seconds
Started Apr 30 02:02:26 PM PDT 24
Finished Apr 30 02:02:33 PM PDT 24
Peak memory 191852 kb
Host smart-01001a64-71d1-4b1f-8933-6d148ed7037c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149076061 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.4149076061
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.2120276244
Short name T158
Test name
Test status
Simulation time 416138962 ps
CPU time 0.71 seconds
Started Apr 30 02:02:27 PM PDT 24
Finished Apr 30 02:02:28 PM PDT 24
Peak memory 183560 kb
Host smart-e5e5dad5-2246-4ca1-a121-8a01ecb729ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120276244 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.2120276244
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.3100968141
Short name T92
Test name
Test status
Simulation time 90612983220 ps
CPU time 128.74 seconds
Started Apr 30 02:02:28 PM PDT 24
Finished Apr 30 02:04:37 PM PDT 24
Peak memory 194876 kb
Host smart-bc70a0c8-4d87-4ee1-a280-769f9b766697
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100968141 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_
all.3100968141
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.809912978
Short name T42
Test name
Test status
Simulation time 30752676403 ps
CPU time 125.23 seconds
Started Apr 30 02:02:26 PM PDT 24
Finished Apr 30 02:04:32 PM PDT 24
Peak memory 198532 kb
Host smart-071f531d-ff6e-4368-911b-c1593408bb83
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809912978 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.809912978
Directory /workspace/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.aon_timer_jump.3873572827
Short name T126
Test name
Test status
Simulation time 560056673 ps
CPU time 0.68 seconds
Started Apr 30 02:02:30 PM PDT 24
Finished Apr 30 02:02:31 PM PDT 24
Peak memory 183564 kb
Host smart-11eced49-c270-4f6d-8470-efc24b2a5434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873572827 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.3873572827
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.163263699
Short name T239
Test name
Test status
Simulation time 7087234604 ps
CPU time 10.71 seconds
Started Apr 30 02:02:27 PM PDT 24
Finished Apr 30 02:02:38 PM PDT 24
Peak memory 183544 kb
Host smart-c69e5eb3-a63a-4d28-9fab-b277f1b98eb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163263699 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.163263699
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.2545865347
Short name T231
Test name
Test status
Simulation time 553717223 ps
CPU time 0.74 seconds
Started Apr 30 02:02:29 PM PDT 24
Finished Apr 30 02:02:30 PM PDT 24
Peak memory 183488 kb
Host smart-a91ebfba-a491-4f77-8edb-c76a6261469d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545865347 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.2545865347
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.637841238
Short name T119
Test name
Test status
Simulation time 307352180902 ps
CPU time 458.61 seconds
Started Apr 30 02:02:27 PM PDT 24
Finished Apr 30 02:10:06 PM PDT 24
Peak memory 194984 kb
Host smart-d4150c88-1ca5-4f80-9d9e-ffbe64dc4b75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637841238 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_a
ll.637841238
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.3272669513
Short name T97
Test name
Test status
Simulation time 88515446099 ps
CPU time 377.41 seconds
Started Apr 30 02:02:28 PM PDT 24
Finished Apr 30 02:08:46 PM PDT 24
Peak memory 206648 kb
Host smart-ba7d32c5-10da-4ad6-a1be-cee1ab40b6a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272669513 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.3272669513
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.aon_timer_jump.3921902205
Short name T215
Test name
Test status
Simulation time 371720198 ps
CPU time 1.22 seconds
Started Apr 30 02:02:25 PM PDT 24
Finished Apr 30 02:02:27 PM PDT 24
Peak memory 183496 kb
Host smart-7c542c20-60d1-4a8c-bca5-6733e108e633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921902205 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.3921902205
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.844258820
Short name T124
Test name
Test status
Simulation time 16270631711 ps
CPU time 24.3 seconds
Started Apr 30 02:02:26 PM PDT 24
Finished Apr 30 02:02:51 PM PDT 24
Peak memory 183572 kb
Host smart-0549090e-f817-436c-9e59-936d5c033041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844258820 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.844258820
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.3902573528
Short name T149
Test name
Test status
Simulation time 501246844 ps
CPU time 0.73 seconds
Started Apr 30 02:02:26 PM PDT 24
Finished Apr 30 02:02:27 PM PDT 24
Peak memory 183564 kb
Host smart-dc266165-3d37-46a1-bb6e-34aeb56a8282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902573528 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.3902573528
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.742025806
Short name T249
Test name
Test status
Simulation time 42755151703 ps
CPU time 16.26 seconds
Started Apr 30 02:02:29 PM PDT 24
Finished Apr 30 02:02:46 PM PDT 24
Peak memory 183588 kb
Host smart-bf8e5e8d-c1db-4c9b-a635-e39844df9c7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742025806 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_a
ll.742025806
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.2759847646
Short name T87
Test name
Test status
Simulation time 108006856024 ps
CPU time 432.29 seconds
Started Apr 30 02:02:28 PM PDT 24
Finished Apr 30 02:09:41 PM PDT 24
Peak memory 198532 kb
Host smart-09844067-1da7-4103-b0fb-f51fc39db662
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759847646 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.2759847646
Directory /workspace/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.aon_timer_jump.2017939215
Short name T27
Test name
Test status
Simulation time 613218658 ps
CPU time 0.78 seconds
Started Apr 30 02:02:37 PM PDT 24
Finished Apr 30 02:02:38 PM PDT 24
Peak memory 183492 kb
Host smart-3f0259ef-1c91-4b7a-b438-559219c24cf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017939215 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.2017939215
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.3363005956
Short name T214
Test name
Test status
Simulation time 24412898058 ps
CPU time 9.31 seconds
Started Apr 30 02:02:27 PM PDT 24
Finished Apr 30 02:02:37 PM PDT 24
Peak memory 191744 kb
Host smart-a9da687d-051b-4d72-8d1c-c26807d0a797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363005956 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.3363005956
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.2097317736
Short name T243
Test name
Test status
Simulation time 372346961 ps
CPU time 1.12 seconds
Started Apr 30 02:02:28 PM PDT 24
Finished Apr 30 02:02:30 PM PDT 24
Peak memory 183532 kb
Host smart-6f2b17e2-a97f-4079-8326-f6df501343d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097317736 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.2097317736
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.1563383200
Short name T240
Test name
Test status
Simulation time 298299875000 ps
CPU time 496.91 seconds
Started Apr 30 02:02:34 PM PDT 24
Finished Apr 30 02:10:51 PM PDT 24
Peak memory 191824 kb
Host smart-9ce0560d-18fe-48ef-b76f-610366da8c05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563383200 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_
all.1563383200
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.3950854229
Short name T79
Test name
Test status
Simulation time 400574926084 ps
CPU time 707.83 seconds
Started Apr 30 02:02:35 PM PDT 24
Finished Apr 30 02:14:23 PM PDT 24
Peak memory 200660 kb
Host smart-8359cf89-48f5-487b-9373-54808076b7de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950854229 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.3950854229
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.aon_timer_jump.440289007
Short name T171
Test name
Test status
Simulation time 454583347 ps
CPU time 0.73 seconds
Started Apr 30 02:02:38 PM PDT 24
Finished Apr 30 02:02:40 PM PDT 24
Peak memory 183600 kb
Host smart-2cbf92f6-40f7-42d2-93aa-23aa39df44e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440289007 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.440289007
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.3657358824
Short name T93
Test name
Test status
Simulation time 12661517574 ps
CPU time 5.6 seconds
Started Apr 30 02:02:35 PM PDT 24
Finished Apr 30 02:02:41 PM PDT 24
Peak memory 191768 kb
Host smart-73020089-99e5-4633-b5b6-e19341c85933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657358824 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.3657358824
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.2523819225
Short name T175
Test name
Test status
Simulation time 375563827 ps
CPU time 0.69 seconds
Started Apr 30 02:02:33 PM PDT 24
Finished Apr 30 02:02:34 PM PDT 24
Peak memory 183492 kb
Host smart-8df538f7-a2e4-48b3-bc51-712b8435e3c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523819225 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.2523819225
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.2747339547
Short name T130
Test name
Test status
Simulation time 172974924159 ps
CPU time 42.81 seconds
Started Apr 30 02:02:35 PM PDT 24
Finished Apr 30 02:03:18 PM PDT 24
Peak memory 193720 kb
Host smart-adb56274-f75c-411c-a847-54ab3d5c2cef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747339547 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_
all.2747339547
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.261222805
Short name T55
Test name
Test status
Simulation time 109227657686 ps
CPU time 267.16 seconds
Started Apr 30 02:02:36 PM PDT 24
Finished Apr 30 02:07:04 PM PDT 24
Peak memory 198532 kb
Host smart-223a12b2-081e-44e7-a539-ae9efdc6c280
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261222805 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.261222805
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_jump.3295542107
Short name T54
Test name
Test status
Simulation time 503034575 ps
CPU time 0.7 seconds
Started Apr 30 02:02:09 PM PDT 24
Finished Apr 30 02:02:10 PM PDT 24
Peak memory 183508 kb
Host smart-5d7b327f-bafc-40e2-9c53-a13257eed65a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295542107 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.3295542107
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.2874286321
Short name T99
Test name
Test status
Simulation time 31584648356 ps
CPU time 13.69 seconds
Started Apr 30 02:02:09 PM PDT 24
Finished Apr 30 02:02:23 PM PDT 24
Peak memory 183572 kb
Host smart-f2213adc-076b-4eb7-8b1c-8aa0531546dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874286321 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.2874286321
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.908359415
Short name T22
Test name
Test status
Simulation time 4195714851 ps
CPU time 6.95 seconds
Started Apr 30 02:02:18 PM PDT 24
Finished Apr 30 02:02:25 PM PDT 24
Peak memory 214880 kb
Host smart-e6783f44-042a-4df1-9798-fa575e8689eb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908359415 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.908359415
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.2480705357
Short name T147
Test name
Test status
Simulation time 515532398 ps
CPU time 0.94 seconds
Started Apr 30 02:02:10 PM PDT 24
Finished Apr 30 02:02:12 PM PDT 24
Peak memory 183572 kb
Host smart-1ceaa9c9-6c42-41d8-baf4-20b241de54ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480705357 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.2480705357
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.3440753967
Short name T252
Test name
Test status
Simulation time 463859198341 ps
CPU time 656.82 seconds
Started Apr 30 02:02:14 PM PDT 24
Finished Apr 30 02:13:12 PM PDT 24
Peak memory 183772 kb
Host smart-634e939f-f155-4ceb-a9b9-ae2d274be16b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440753967 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_a
ll.3440753967
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_jump.2513950424
Short name T128
Test name
Test status
Simulation time 577826595 ps
CPU time 0.6 seconds
Started Apr 30 02:02:34 PM PDT 24
Finished Apr 30 02:02:35 PM PDT 24
Peak memory 183524 kb
Host smart-bdc8cb80-21c2-4fab-8921-f83f11e5cd30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513950424 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.2513950424
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.878652760
Short name T125
Test name
Test status
Simulation time 26017914457 ps
CPU time 41.08 seconds
Started Apr 30 02:02:35 PM PDT 24
Finished Apr 30 02:03:16 PM PDT 24
Peak memory 183544 kb
Host smart-172c2efb-6803-4ec7-afd6-fa911c6a4477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878652760 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.878652760
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.2475355794
Short name T208
Test name
Test status
Simulation time 605078549 ps
CPU time 0.64 seconds
Started Apr 30 02:02:38 PM PDT 24
Finished Apr 30 02:02:39 PM PDT 24
Peak memory 183600 kb
Host smart-7e394397-2a5e-4b75-9869-277f0569dd37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475355794 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.2475355794
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.1404534385
Short name T146
Test name
Test status
Simulation time 172719317568 ps
CPU time 62.7 seconds
Started Apr 30 02:02:35 PM PDT 24
Finished Apr 30 02:03:38 PM PDT 24
Peak memory 195244 kb
Host smart-e41c0742-3097-4ee0-aa57-092c90c78ab6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404534385 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_
all.1404534385
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.2229743302
Short name T38
Test name
Test status
Simulation time 147289373249 ps
CPU time 624.35 seconds
Started Apr 30 02:02:33 PM PDT 24
Finished Apr 30 02:12:58 PM PDT 24
Peak memory 199860 kb
Host smart-7df378f3-f31e-494e-b250-0274e1b56baa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229743302 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.2229743302
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_jump.1311735867
Short name T219
Test name
Test status
Simulation time 586180877 ps
CPU time 1.05 seconds
Started Apr 30 02:02:37 PM PDT 24
Finished Apr 30 02:02:38 PM PDT 24
Peak memory 183492 kb
Host smart-f082a802-60b9-4542-aeb0-ba5db506ed8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311735867 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.1311735867
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.1858101707
Short name T172
Test name
Test status
Simulation time 18533504054 ps
CPU time 28.65 seconds
Started Apr 30 02:02:33 PM PDT 24
Finished Apr 30 02:03:02 PM PDT 24
Peak memory 183568 kb
Host smart-e7b3dcc7-8594-43d3-8434-bf55b61cd1bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858101707 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.1858101707
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.3982491193
Short name T166
Test name
Test status
Simulation time 493255204 ps
CPU time 0.64 seconds
Started Apr 30 02:02:44 PM PDT 24
Finished Apr 30 02:02:45 PM PDT 24
Peak memory 183524 kb
Host smart-ab05a9a3-9e76-48a2-a4ce-d5a6dcca6ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982491193 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.3982491193
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.4201788975
Short name T84
Test name
Test status
Simulation time 19881560883 ps
CPU time 56.7 seconds
Started Apr 30 02:02:37 PM PDT 24
Finished Apr 30 02:03:34 PM PDT 24
Peak memory 198304 kb
Host smart-28c43584-27cd-47a9-8e20-7f2e555f21d8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201788975 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.4201788975
Directory /workspace/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.aon_timer_jump.374948253
Short name T112
Test name
Test status
Simulation time 460388557 ps
CPU time 0.71 seconds
Started Apr 30 02:02:34 PM PDT 24
Finished Apr 30 02:02:36 PM PDT 24
Peak memory 183568 kb
Host smart-51226a6e-aeac-427d-8dae-5f300e06b5d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374948253 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.374948253
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.1221780203
Short name T137
Test name
Test status
Simulation time 10554819665 ps
CPU time 17.45 seconds
Started Apr 30 02:02:36 PM PDT 24
Finished Apr 30 02:02:54 PM PDT 24
Peak memory 183584 kb
Host smart-78454917-87d7-446e-9222-42280864b3d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221780203 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.1221780203
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.2485600724
Short name T155
Test name
Test status
Simulation time 478455802 ps
CPU time 1.31 seconds
Started Apr 30 02:02:40 PM PDT 24
Finished Apr 30 02:02:42 PM PDT 24
Peak memory 183556 kb
Host smart-8f8de223-0e23-4131-a95a-58a02bb3b70c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485600724 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.2485600724
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.1863907755
Short name T109
Test name
Test status
Simulation time 54334565008 ps
CPU time 20.21 seconds
Started Apr 30 02:02:44 PM PDT 24
Finished Apr 30 02:03:05 PM PDT 24
Peak memory 193920 kb
Host smart-09b05302-9968-481f-ae79-e0018c70a6af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863907755 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_
all.1863907755
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.3648205789
Short name T143
Test name
Test status
Simulation time 177169500284 ps
CPU time 723.98 seconds
Started Apr 30 02:02:34 PM PDT 24
Finished Apr 30 02:14:39 PM PDT 24
Peak memory 200980 kb
Host smart-f74159ea-f906-40ec-b30b-73cb2007adaf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648205789 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.3648205789
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.aon_timer_jump.300507789
Short name T114
Test name
Test status
Simulation time 596975131 ps
CPU time 0.63 seconds
Started Apr 30 02:02:37 PM PDT 24
Finished Apr 30 02:02:38 PM PDT 24
Peak memory 183512 kb
Host smart-f70f501e-b91d-4db6-9f22-3e2db32c4475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300507789 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.300507789
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.2111208881
Short name T117
Test name
Test status
Simulation time 23643795738 ps
CPU time 9.28 seconds
Started Apr 30 02:02:34 PM PDT 24
Finished Apr 30 02:02:44 PM PDT 24
Peak memory 183624 kb
Host smart-a5b23039-e054-4b0a-81b6-5a18e2b21ea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111208881 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.2111208881
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.1951894755
Short name T28
Test name
Test status
Simulation time 350048869 ps
CPU time 0.82 seconds
Started Apr 30 02:02:35 PM PDT 24
Finished Apr 30 02:02:36 PM PDT 24
Peak memory 183528 kb
Host smart-d68bf623-fd38-4eca-b5c5-eb61251515ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951894755 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.1951894755
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.3612227955
Short name T217
Test name
Test status
Simulation time 194820062614 ps
CPU time 295.32 seconds
Started Apr 30 02:02:36 PM PDT 24
Finished Apr 30 02:07:31 PM PDT 24
Peak memory 194360 kb
Host smart-4f172cf8-dba6-4ef6-87f9-7db66f6816ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612227955 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_
all.3612227955
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.991609569
Short name T88
Test name
Test status
Simulation time 128748778483 ps
CPU time 282.65 seconds
Started Apr 30 02:02:35 PM PDT 24
Finished Apr 30 02:07:18 PM PDT 24
Peak memory 206692 kb
Host smart-4a0e9233-1372-4940-abf5-fb8e1f6c5b22
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991609569 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.991609569
Directory /workspace/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.aon_timer_jump.640963416
Short name T3
Test name
Test status
Simulation time 409590483 ps
CPU time 0.75 seconds
Started Apr 30 02:02:36 PM PDT 24
Finished Apr 30 02:02:37 PM PDT 24
Peak memory 183516 kb
Host smart-8a4fd1d3-250e-4b8d-ac22-8e494e7be674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640963416 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.640963416
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.705374301
Short name T256
Test name
Test status
Simulation time 3531928476 ps
CPU time 1.6 seconds
Started Apr 30 02:02:33 PM PDT 24
Finished Apr 30 02:02:35 PM PDT 24
Peak memory 183624 kb
Host smart-15df6085-cc29-43dc-b8ec-85679d0f2fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705374301 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.705374301
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.251506233
Short name T108
Test name
Test status
Simulation time 516073819 ps
CPU time 0.75 seconds
Started Apr 30 02:02:35 PM PDT 24
Finished Apr 30 02:02:36 PM PDT 24
Peak memory 183576 kb
Host smart-72c0021a-e72f-4daf-b2a0-539cc4034967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251506233 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.251506233
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.525965417
Short name T81
Test name
Test status
Simulation time 85631000465 ps
CPU time 671.26 seconds
Started Apr 30 02:02:37 PM PDT 24
Finished Apr 30 02:13:49 PM PDT 24
Peak memory 199144 kb
Host smart-a4ff7351-a752-4ae3-82b5-f0b6c7010184
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525965417 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand_reset.525965417
Directory /workspace/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.aon_timer_jump.1574137326
Short name T138
Test name
Test status
Simulation time 398362799 ps
CPU time 1.1 seconds
Started Apr 30 02:02:37 PM PDT 24
Finished Apr 30 02:02:39 PM PDT 24
Peak memory 183624 kb
Host smart-4f404a1a-6ec5-45d5-9fa2-68c6c5e56284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574137326 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.1574137326
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.2618011978
Short name T229
Test name
Test status
Simulation time 5239858433 ps
CPU time 1.4 seconds
Started Apr 30 02:02:33 PM PDT 24
Finished Apr 30 02:02:35 PM PDT 24
Peak memory 191836 kb
Host smart-b320a814-b3c4-481e-b0f9-d29119a82ec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618011978 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.2618011978
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.518065011
Short name T29
Test name
Test status
Simulation time 488349716 ps
CPU time 0.89 seconds
Started Apr 30 02:02:36 PM PDT 24
Finished Apr 30 02:02:37 PM PDT 24
Peak memory 183516 kb
Host smart-4f02996f-aebe-41fa-a683-e013ff2c0694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518065011 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.518065011
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.301654490
Short name T96
Test name
Test status
Simulation time 350239278612 ps
CPU time 145.12 seconds
Started Apr 30 02:02:44 PM PDT 24
Finished Apr 30 02:05:09 PM PDT 24
Peak memory 194300 kb
Host smart-450ea571-5c07-43f0-81b9-ae6272ca5501
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301654490 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_a
ll.301654490
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.2020560622
Short name T209
Test name
Test status
Simulation time 212305513924 ps
CPU time 621.52 seconds
Started Apr 30 02:02:35 PM PDT 24
Finished Apr 30 02:12:57 PM PDT 24
Peak memory 200276 kb
Host smart-d2e8d756-c0df-48ad-ae55-5a3f23766b31
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020560622 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.2020560622
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.aon_timer_jump.2042199531
Short name T235
Test name
Test status
Simulation time 513475408 ps
CPU time 1.54 seconds
Started Apr 30 02:02:36 PM PDT 24
Finished Apr 30 02:02:38 PM PDT 24
Peak memory 183512 kb
Host smart-62f08963-51bb-4c2b-99ef-0289ed0ce3f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042199531 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.2042199531
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.2800654430
Short name T180
Test name
Test status
Simulation time 3811751695 ps
CPU time 2.05 seconds
Started Apr 30 02:02:37 PM PDT 24
Finished Apr 30 02:02:40 PM PDT 24
Peak memory 183664 kb
Host smart-d89b3b0e-23ee-46e1-a3ed-f090e3f527c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800654430 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.2800654430
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.1117314804
Short name T129
Test name
Test status
Simulation time 391990621 ps
CPU time 1.08 seconds
Started Apr 30 02:02:39 PM PDT 24
Finished Apr 30 02:02:41 PM PDT 24
Peak memory 183516 kb
Host smart-e739ed9f-e241-49b5-9226-706d58cca8d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117314804 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.1117314804
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.2230111448
Short name T167
Test name
Test status
Simulation time 20851039220 ps
CPU time 9.11 seconds
Started Apr 30 02:02:43 PM PDT 24
Finished Apr 30 02:02:53 PM PDT 24
Peak memory 183572 kb
Host smart-7a60da89-d82f-4f61-a3e8-509d20292fca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230111448 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_
all.2230111448
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/27.aon_timer_jump.2238214603
Short name T163
Test name
Test status
Simulation time 414038390 ps
CPU time 0.82 seconds
Started Apr 30 02:02:43 PM PDT 24
Finished Apr 30 02:02:44 PM PDT 24
Peak memory 183508 kb
Host smart-fdeaf61e-66fb-4f81-a7ae-e3f81b2d011b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238214603 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.2238214603
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.514433619
Short name T194
Test name
Test status
Simulation time 1692747090 ps
CPU time 3.26 seconds
Started Apr 30 02:02:44 PM PDT 24
Finished Apr 30 02:02:47 PM PDT 24
Peak memory 183552 kb
Host smart-1b3befc2-2e13-4f40-aeeb-92b6cfa65106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514433619 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.514433619
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.3072096081
Short name T174
Test name
Test status
Simulation time 504623109 ps
CPU time 0.64 seconds
Started Apr 30 02:02:41 PM PDT 24
Finished Apr 30 02:02:42 PM PDT 24
Peak memory 183564 kb
Host smart-e63687fd-33f3-480f-8ff4-cda17e03b015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072096081 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.3072096081
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.2904787130
Short name T236
Test name
Test status
Simulation time 126820604738 ps
CPU time 79.17 seconds
Started Apr 30 02:02:43 PM PDT 24
Finished Apr 30 02:04:03 PM PDT 24
Peak memory 183572 kb
Host smart-35100526-8005-4e04-8b04-dfbc4b973290
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904787130 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_
all.2904787130
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_jump.96855660
Short name T173
Test name
Test status
Simulation time 594801644 ps
CPU time 0.75 seconds
Started Apr 30 02:02:49 PM PDT 24
Finished Apr 30 02:02:50 PM PDT 24
Peak memory 183516 kb
Host smart-c9e5ad39-d91c-42c9-8c5c-62a06402dcfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96855660 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.96855660
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.1055878870
Short name T196
Test name
Test status
Simulation time 44902646196 ps
CPU time 68.72 seconds
Started Apr 30 02:02:44 PM PDT 24
Finished Apr 30 02:03:53 PM PDT 24
Peak memory 191828 kb
Host smart-81f6db08-92bc-45d4-8591-78dd31b67cb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055878870 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.1055878870
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.1448814536
Short name T139
Test name
Test status
Simulation time 367659809 ps
CPU time 0.66 seconds
Started Apr 30 02:02:45 PM PDT 24
Finished Apr 30 02:02:46 PM PDT 24
Peak memory 183488 kb
Host smart-cef708e2-2160-492d-ae03-6a7cc2937fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448814536 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.1448814536
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.1829881864
Short name T259
Test name
Test status
Simulation time 247867543087 ps
CPU time 96.02 seconds
Started Apr 30 02:02:43 PM PDT 24
Finished Apr 30 02:04:19 PM PDT 24
Peak memory 193644 kb
Host smart-8e3bb660-5cbf-4977-8530-385ce4710b37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829881864 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_
all.1829881864
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.3793479884
Short name T44
Test name
Test status
Simulation time 177192710214 ps
CPU time 605.14 seconds
Started Apr 30 02:02:43 PM PDT 24
Finished Apr 30 02:12:49 PM PDT 24
Peak memory 199636 kb
Host smart-1c40bffb-6bbc-4b65-9f35-bb259e4a7bfc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793479884 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.3793479884
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.aon_timer_jump.2163213930
Short name T52
Test name
Test status
Simulation time 542129007 ps
CPU time 1.48 seconds
Started Apr 30 02:02:55 PM PDT 24
Finished Apr 30 02:02:57 PM PDT 24
Peak memory 183536 kb
Host smart-f4296ec2-3a22-4f87-81d2-4726615b47cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163213930 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.2163213930
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.964787360
Short name T135
Test name
Test status
Simulation time 32198704104 ps
CPU time 51.55 seconds
Started Apr 30 02:02:42 PM PDT 24
Finished Apr 30 02:03:34 PM PDT 24
Peak memory 191828 kb
Host smart-fcc76a6b-e1a8-4692-ae76-c8a56e367011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964787360 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.964787360
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.520753008
Short name T111
Test name
Test status
Simulation time 334389624 ps
CPU time 0.92 seconds
Started Apr 30 02:02:43 PM PDT 24
Finished Apr 30 02:02:44 PM PDT 24
Peak memory 183576 kb
Host smart-ffb1d828-e5d6-420d-b3ab-2e6540f18d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520753008 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.520753008
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.1624249006
Short name T133
Test name
Test status
Simulation time 53508336163 ps
CPU time 308.09 seconds
Started Apr 30 02:02:53 PM PDT 24
Finished Apr 30 02:08:02 PM PDT 24
Peak memory 198424 kb
Host smart-38aff260-1f24-49db-b60b-d739b06f189b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624249006 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.1624249006
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.aon_timer_jump.3589218918
Short name T153
Test name
Test status
Simulation time 589512751 ps
CPU time 1.4 seconds
Started Apr 30 02:02:15 PM PDT 24
Finished Apr 30 02:02:17 PM PDT 24
Peak memory 183560 kb
Host smart-8b02ccd2-951e-4fc4-9ca7-c56743fc9186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589218918 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.3589218918
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.1837596710
Short name T170
Test name
Test status
Simulation time 30223297514 ps
CPU time 25.58 seconds
Started Apr 30 02:02:11 PM PDT 24
Finished Apr 30 02:02:37 PM PDT 24
Peak memory 183528 kb
Host smart-cc6a202a-e0b2-465f-8149-f735540bda42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837596710 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.1837596710
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.583795203
Short name T16
Test name
Test status
Simulation time 7988181525 ps
CPU time 5.9 seconds
Started Apr 30 02:02:09 PM PDT 24
Finished Apr 30 02:02:16 PM PDT 24
Peak memory 215232 kb
Host smart-431bd3b9-5d82-43e8-9c4c-c4d61d9d018f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583795203 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.583795203
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.647701668
Short name T192
Test name
Test status
Simulation time 502628832 ps
CPU time 1.22 seconds
Started Apr 30 02:02:09 PM PDT 24
Finished Apr 30 02:02:11 PM PDT 24
Peak memory 183520 kb
Host smart-20546715-24fb-4d41-9bea-c31d67064b17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647701668 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.647701668
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.1217443519
Short name T213
Test name
Test status
Simulation time 29053000986 ps
CPU time 12.21 seconds
Started Apr 30 02:02:10 PM PDT 24
Finished Apr 30 02:02:22 PM PDT 24
Peak memory 194172 kb
Host smart-61193d31-e2f4-4446-96ae-d1940c771b1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217443519 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_a
ll.1217443519
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.3579573305
Short name T216
Test name
Test status
Simulation time 126153786185 ps
CPU time 164.25 seconds
Started Apr 30 02:02:09 PM PDT 24
Finished Apr 30 02:04:54 PM PDT 24
Peak memory 198480 kb
Host smart-99d0456e-dee3-4def-9b20-0c41bfff7430
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579573305 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.3579573305
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_jump.2550976324
Short name T45
Test name
Test status
Simulation time 492161607 ps
CPU time 0.73 seconds
Started Apr 30 02:02:50 PM PDT 24
Finished Apr 30 02:02:51 PM PDT 24
Peak memory 183516 kb
Host smart-84edee22-2b91-45ef-b219-41130a858687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550976324 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.2550976324
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.2351956230
Short name T90
Test name
Test status
Simulation time 51127271663 ps
CPU time 35.02 seconds
Started Apr 30 02:02:43 PM PDT 24
Finished Apr 30 02:03:18 PM PDT 24
Peak memory 183628 kb
Host smart-6c1d9db4-1b02-409a-8dfc-a2acfaa80f78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351956230 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.2351956230
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.4260842523
Short name T141
Test name
Test status
Simulation time 535030737 ps
CPU time 0.95 seconds
Started Apr 30 02:02:54 PM PDT 24
Finished Apr 30 02:02:55 PM PDT 24
Peak memory 183544 kb
Host smart-2059e26b-b652-4f96-bfe2-7f12a8224544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260842523 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.4260842523
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.427139512
Short name T19
Test name
Test status
Simulation time 225301682956 ps
CPU time 146.29 seconds
Started Apr 30 02:02:54 PM PDT 24
Finished Apr 30 02:05:21 PM PDT 24
Peak memory 195552 kb
Host smart-777eb273-e727-4768-b65c-38d3b46c7d90
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427139512 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_a
ll.427139512
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.964177194
Short name T267
Test name
Test status
Simulation time 58037459965 ps
CPU time 237.64 seconds
Started Apr 30 02:02:54 PM PDT 24
Finished Apr 30 02:06:52 PM PDT 24
Peak memory 214240 kb
Host smart-a70e3816-4e0d-404c-892f-ee428c3b02c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964177194 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.964177194
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.aon_timer_jump.2209700177
Short name T47
Test name
Test status
Simulation time 400451623 ps
CPU time 1.16 seconds
Started Apr 30 02:02:43 PM PDT 24
Finished Apr 30 02:02:45 PM PDT 24
Peak memory 183564 kb
Host smart-5bb4ece7-7990-4808-a731-19c4d05bd41d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209700177 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.2209700177
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.188304823
Short name T281
Test name
Test status
Simulation time 16093583452 ps
CPU time 24.62 seconds
Started Apr 30 02:02:50 PM PDT 24
Finished Apr 30 02:03:15 PM PDT 24
Peak memory 183576 kb
Host smart-d8d29979-4171-4ca5-8fca-c70833aaf414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188304823 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.188304823
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.3399080447
Short name T110
Test name
Test status
Simulation time 364878078 ps
CPU time 0.78 seconds
Started Apr 30 02:02:42 PM PDT 24
Finished Apr 30 02:02:44 PM PDT 24
Peak memory 183516 kb
Host smart-8798a184-35fb-44fd-84f7-842c3c52d76c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399080447 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.3399080447
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.2170056968
Short name T257
Test name
Test status
Simulation time 15746645559 ps
CPU time 14.38 seconds
Started Apr 30 02:02:44 PM PDT 24
Finished Apr 30 02:02:59 PM PDT 24
Peak memory 183576 kb
Host smart-8a875d97-c7f2-4c55-b65b-0fa1c7425ee0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170056968 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_
all.2170056968
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.1770289435
Short name T142
Test name
Test status
Simulation time 84746603279 ps
CPU time 240.36 seconds
Started Apr 30 02:02:44 PM PDT 24
Finished Apr 30 02:06:45 PM PDT 24
Peak memory 198508 kb
Host smart-68d4ee33-5d92-43df-b938-1e6303a3790b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770289435 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.1770289435
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.aon_timer_jump.916859864
Short name T12
Test name
Test status
Simulation time 422702368 ps
CPU time 1.23 seconds
Started Apr 30 02:02:43 PM PDT 24
Finished Apr 30 02:02:45 PM PDT 24
Peak memory 183476 kb
Host smart-9338d716-cd80-4aca-abc5-664c424883c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916859864 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.916859864
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.2488804235
Short name T255
Test name
Test status
Simulation time 41465560342 ps
CPU time 64.46 seconds
Started Apr 30 02:02:45 PM PDT 24
Finished Apr 30 02:03:50 PM PDT 24
Peak memory 183536 kb
Host smart-5219a004-902c-40d4-bf32-5e61d6272200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488804235 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.2488804235
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.78676182
Short name T162
Test name
Test status
Simulation time 559822572 ps
CPU time 0.99 seconds
Started Apr 30 02:02:53 PM PDT 24
Finished Apr 30 02:02:55 PM PDT 24
Peak memory 183528 kb
Host smart-47e57028-c44a-4105-ae24-fa3342d9f2ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78676182 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.78676182
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.1796087651
Short name T91
Test name
Test status
Simulation time 148622686681 ps
CPU time 231.11 seconds
Started Apr 30 02:02:43 PM PDT 24
Finished Apr 30 02:06:34 PM PDT 24
Peak memory 194336 kb
Host smart-7e424656-8fa1-4439-8b78-b88894b3577b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796087651 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_
all.1796087651
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.460473159
Short name T140
Test name
Test status
Simulation time 282386776946 ps
CPU time 544.47 seconds
Started Apr 30 02:02:42 PM PDT 24
Finished Apr 30 02:11:47 PM PDT 24
Peak memory 198884 kb
Host smart-9175647a-a01b-4eae-93e8-aa14bc1ae35f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460473159 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_reset.460473159
Directory /workspace/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.aon_timer_jump.4115202646
Short name T277
Test name
Test status
Simulation time 369688798 ps
CPU time 0.69 seconds
Started Apr 30 02:02:42 PM PDT 24
Finished Apr 30 02:02:43 PM PDT 24
Peak memory 183460 kb
Host smart-ceae3dba-a505-4b1b-a679-cf25c4e06ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115202646 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.4115202646
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.2249704816
Short name T199
Test name
Test status
Simulation time 10633572605 ps
CPU time 9.33 seconds
Started Apr 30 02:02:41 PM PDT 24
Finished Apr 30 02:02:51 PM PDT 24
Peak memory 191788 kb
Host smart-01c25c9e-4079-445a-becf-c4c5bea905cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249704816 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.2249704816
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.3363157318
Short name T238
Test name
Test status
Simulation time 491244740 ps
CPU time 0.63 seconds
Started Apr 30 02:02:43 PM PDT 24
Finished Apr 30 02:02:44 PM PDT 24
Peak memory 183512 kb
Host smart-e683349b-84c3-4039-a2ee-8dc5b432f411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363157318 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.3363157318
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.3282505818
Short name T120
Test name
Test status
Simulation time 390944429692 ps
CPU time 84.55 seconds
Started Apr 30 02:02:42 PM PDT 24
Finished Apr 30 02:04:07 PM PDT 24
Peak memory 195380 kb
Host smart-74d38d09-9e8e-4f4b-9e84-2e87799a82cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282505818 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_
all.3282505818
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.1590259877
Short name T43
Test name
Test status
Simulation time 60085370619 ps
CPU time 676.05 seconds
Started Apr 30 02:02:54 PM PDT 24
Finished Apr 30 02:14:10 PM PDT 24
Peak memory 199068 kb
Host smart-75fe49e0-bef5-49b5-9f16-7096a9f9271b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590259877 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.1590259877
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.aon_timer_jump.4107112027
Short name T198
Test name
Test status
Simulation time 573835994 ps
CPU time 0.63 seconds
Started Apr 30 02:02:43 PM PDT 24
Finished Apr 30 02:02:45 PM PDT 24
Peak memory 183552 kb
Host smart-ccca7dce-57e9-4476-844a-c5056a18a199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107112027 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.4107112027
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.3734450506
Short name T49
Test name
Test status
Simulation time 15198398146 ps
CPU time 6.06 seconds
Started Apr 30 02:02:42 PM PDT 24
Finished Apr 30 02:02:49 PM PDT 24
Peak memory 191824 kb
Host smart-16cf7bc3-a988-4b2a-a3f4-4e955416b27d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734450506 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.3734450506
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.3585982039
Short name T10
Test name
Test status
Simulation time 548115177 ps
CPU time 1.43 seconds
Started Apr 30 02:02:43 PM PDT 24
Finished Apr 30 02:02:45 PM PDT 24
Peak memory 183580 kb
Host smart-eb81e6cd-7333-4d05-85a3-be3ec557c1e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585982039 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.3585982039
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.1371791075
Short name T274
Test name
Test status
Simulation time 80411400830 ps
CPU time 109.38 seconds
Started Apr 30 02:02:46 PM PDT 24
Finished Apr 30 02:04:36 PM PDT 24
Peak memory 194812 kb
Host smart-7147093b-08c0-4fc4-bfea-2dc8f6002d51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371791075 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_
all.1371791075
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.2185647293
Short name T89
Test name
Test status
Simulation time 46268103881 ps
CPU time 358.86 seconds
Started Apr 30 02:02:44 PM PDT 24
Finished Apr 30 02:08:44 PM PDT 24
Peak memory 198532 kb
Host smart-fa908ab5-bb5a-49a0-a385-2c0ba583d92d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185647293 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.2185647293
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.aon_timer_jump.828125349
Short name T148
Test name
Test status
Simulation time 625278890 ps
CPU time 0.67 seconds
Started Apr 30 02:02:55 PM PDT 24
Finished Apr 30 02:02:56 PM PDT 24
Peak memory 183536 kb
Host smart-5f35c30e-a223-46fb-9185-dfdfebb50f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828125349 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.828125349
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.3184730809
Short name T221
Test name
Test status
Simulation time 25887102497 ps
CPU time 20.93 seconds
Started Apr 30 02:02:43 PM PDT 24
Finished Apr 30 02:03:04 PM PDT 24
Peak memory 183608 kb
Host smart-555f0adf-4e1c-4b5f-b3c4-1a67cbaa5394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184730809 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.3184730809
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.353492290
Short name T177
Test name
Test status
Simulation time 388661231 ps
CPU time 0.69 seconds
Started Apr 30 02:02:45 PM PDT 24
Finished Apr 30 02:02:46 PM PDT 24
Peak memory 183476 kb
Host smart-baba8532-c784-45eb-8fe1-8e3a32574a80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353492290 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.353492290
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.1599475639
Short name T121
Test name
Test status
Simulation time 106821368360 ps
CPU time 160.77 seconds
Started Apr 30 02:02:50 PM PDT 24
Finished Apr 30 02:05:33 PM PDT 24
Peak memory 193292 kb
Host smart-e24bdc14-8efd-45ab-9c55-5b2eb1d02161
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599475639 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_
all.1599475639
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.1814672310
Short name T86
Test name
Test status
Simulation time 45256033716 ps
CPU time 164.09 seconds
Started Apr 30 02:02:50 PM PDT 24
Finished Apr 30 02:05:35 PM PDT 24
Peak memory 198504 kb
Host smart-6e61c7ec-1cbc-4c7c-a5d3-b0e00e0e22ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814672310 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.1814672310
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.aon_timer_jump.495370502
Short name T50
Test name
Test status
Simulation time 542872764 ps
CPU time 0.6 seconds
Started Apr 30 02:02:51 PM PDT 24
Finished Apr 30 02:02:53 PM PDT 24
Peak memory 183548 kb
Host smart-5683483b-a509-48a0-a13e-4bfdfba6ddf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495370502 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.495370502
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.2766400961
Short name T187
Test name
Test status
Simulation time 57596834044 ps
CPU time 48.74 seconds
Started Apr 30 02:02:51 PM PDT 24
Finished Apr 30 02:03:41 PM PDT 24
Peak memory 183632 kb
Host smart-f7033fac-e0be-4d25-b656-5c5cf00e9ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766400961 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.2766400961
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.1430745974
Short name T230
Test name
Test status
Simulation time 500021311 ps
CPU time 0.74 seconds
Started Apr 30 02:02:52 PM PDT 24
Finished Apr 30 02:02:53 PM PDT 24
Peak memory 183576 kb
Host smart-829fd064-3ac3-4cc3-b9ec-21992ac92cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430745974 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.1430745974
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.3350218207
Short name T191
Test name
Test status
Simulation time 402399542856 ps
CPU time 302.94 seconds
Started Apr 30 02:02:50 PM PDT 24
Finished Apr 30 02:07:55 PM PDT 24
Peak memory 195076 kb
Host smart-73d59751-d65a-40d2-8a41-858aa59c9ce0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350218207 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_
all.3350218207
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_jump.722485233
Short name T2
Test name
Test status
Simulation time 585909372 ps
CPU time 1.57 seconds
Started Apr 30 02:02:51 PM PDT 24
Finished Apr 30 02:02:54 PM PDT 24
Peak memory 183512 kb
Host smart-2ecf700c-8429-4ae0-9be3-826db5cc7b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722485233 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.722485233
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.4068604130
Short name T14
Test name
Test status
Simulation time 1494167060 ps
CPU time 2.61 seconds
Started Apr 30 02:02:55 PM PDT 24
Finished Apr 30 02:02:58 PM PDT 24
Peak memory 183740 kb
Host smart-f6a4d6d6-34f9-4347-9704-0e1f2e622ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068604130 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.4068604130
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.3040061176
Short name T207
Test name
Test status
Simulation time 338652629 ps
CPU time 1.03 seconds
Started Apr 30 02:02:51 PM PDT 24
Finished Apr 30 02:02:53 PM PDT 24
Peak memory 183528 kb
Host smart-25d00ab1-ed64-47b6-83f4-cdcc299af500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040061176 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.3040061176
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.1247109891
Short name T237
Test name
Test status
Simulation time 357124678948 ps
CPU time 149.42 seconds
Started Apr 30 02:02:49 PM PDT 24
Finished Apr 30 02:05:19 PM PDT 24
Peak memory 194100 kb
Host smart-760365bb-9266-490d-aa02-abde209b9a43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247109891 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_
all.1247109891
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.3111062378
Short name T13
Test name
Test status
Simulation time 89475601249 ps
CPU time 624.91 seconds
Started Apr 30 02:02:50 PM PDT 24
Finished Apr 30 02:13:17 PM PDT 24
Peak memory 200116 kb
Host smart-59ea1079-1dc9-46df-b0d2-0212a252bffe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111062378 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.3111062378
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.aon_timer_jump.3211513005
Short name T181
Test name
Test status
Simulation time 439199590 ps
CPU time 0.85 seconds
Started Apr 30 02:02:50 PM PDT 24
Finished Apr 30 02:02:52 PM PDT 24
Peak memory 183552 kb
Host smart-42969e93-49ef-472f-946c-8802fde8f945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211513005 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.3211513005
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.1274978140
Short name T169
Test name
Test status
Simulation time 38218207934 ps
CPU time 4.41 seconds
Started Apr 30 02:02:50 PM PDT 24
Finished Apr 30 02:02:56 PM PDT 24
Peak memory 183628 kb
Host smart-2ed7b451-78e7-4e42-876c-ccd16b82939d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274978140 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.1274978140
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.379829301
Short name T7
Test name
Test status
Simulation time 565947423 ps
CPU time 0.81 seconds
Started Apr 30 02:02:50 PM PDT 24
Finished Apr 30 02:02:52 PM PDT 24
Peak memory 183524 kb
Host smart-da25312f-9715-42ce-928b-529b06b64969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379829301 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.379829301
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.3915984759
Short name T186
Test name
Test status
Simulation time 439992303127 ps
CPU time 162.36 seconds
Started Apr 30 02:02:50 PM PDT 24
Finished Apr 30 02:05:33 PM PDT 24
Peak memory 194760 kb
Host smart-f05ebb58-cc70-42b6-b895-a687ff71f3a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915984759 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_
all.3915984759
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.4224913175
Short name T251
Test name
Test status
Simulation time 67459983033 ps
CPU time 496.66 seconds
Started Apr 30 02:02:52 PM PDT 24
Finished Apr 30 02:11:09 PM PDT 24
Peak memory 198484 kb
Host smart-b9c30b1c-bd19-4f20-8020-587fd93add93
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224913175 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand_reset.4224913175
Directory /workspace/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.aon_timer_jump.1010939899
Short name T210
Test name
Test status
Simulation time 596428927 ps
CPU time 0.99 seconds
Started Apr 30 02:02:51 PM PDT 24
Finished Apr 30 02:02:53 PM PDT 24
Peak memory 183528 kb
Host smart-d42dc68d-8d04-4935-9439-799a25b4f1e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010939899 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.1010939899
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.2003579813
Short name T131
Test name
Test status
Simulation time 8563047902 ps
CPU time 4.06 seconds
Started Apr 30 02:02:51 PM PDT 24
Finished Apr 30 02:02:56 PM PDT 24
Peak memory 183632 kb
Host smart-930fee00-ce3d-4fc9-aee0-8bb2e61625a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003579813 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.2003579813
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.3328679887
Short name T151
Test name
Test status
Simulation time 502855120 ps
CPU time 0.59 seconds
Started Apr 30 02:02:50 PM PDT 24
Finished Apr 30 02:02:51 PM PDT 24
Peak memory 183516 kb
Host smart-6a65a7f7-1b4a-4604-9954-2371f786bf64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328679887 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.3328679887
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.3602926172
Short name T276
Test name
Test status
Simulation time 298342098156 ps
CPU time 115.54 seconds
Started Apr 30 02:02:55 PM PDT 24
Finished Apr 30 02:04:51 PM PDT 24
Peak memory 183800 kb
Host smart-c0c6b56b-e080-437c-ba70-ddcbdd1f8fdd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602926172 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_
all.3602926172
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_jump.1735684932
Short name T184
Test name
Test status
Simulation time 590087013 ps
CPU time 0.61 seconds
Started Apr 30 02:02:19 PM PDT 24
Finished Apr 30 02:02:20 PM PDT 24
Peak memory 183540 kb
Host smart-8160b979-608d-4b25-ab42-e480861c138d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735684932 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.1735684932
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.1336758679
Short name T195
Test name
Test status
Simulation time 5264275510 ps
CPU time 2.9 seconds
Started Apr 30 02:02:13 PM PDT 24
Finished Apr 30 02:02:16 PM PDT 24
Peak memory 183552 kb
Host smart-6bfd83a6-4290-409d-b33f-077b9b78d654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336758679 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.1336758679
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.3145017669
Short name T17
Test name
Test status
Simulation time 4549564900 ps
CPU time 4.23 seconds
Started Apr 30 02:02:12 PM PDT 24
Finished Apr 30 02:02:17 PM PDT 24
Peak memory 215188 kb
Host smart-d3264378-5e55-46aa-b0f9-202869544947
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145017669 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.3145017669
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.3970858482
Short name T224
Test name
Test status
Simulation time 463065758 ps
CPU time 1.16 seconds
Started Apr 30 02:02:14 PM PDT 24
Finished Apr 30 02:02:15 PM PDT 24
Peak memory 183468 kb
Host smart-95a016d4-1cee-4792-a707-f1e25882e96d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970858482 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.3970858482
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.2961663049
Short name T258
Test name
Test status
Simulation time 50947043638 ps
CPU time 15.39 seconds
Started Apr 30 02:02:19 PM PDT 24
Finished Apr 30 02:02:35 PM PDT 24
Peak memory 194048 kb
Host smart-3216da10-a12b-4e65-aab9-fb00f96e9a51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961663049 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_a
ll.2961663049
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.2898822080
Short name T80
Test name
Test status
Simulation time 188062146467 ps
CPU time 947.27 seconds
Started Apr 30 02:02:10 PM PDT 24
Finished Apr 30 02:17:58 PM PDT 24
Peak memory 204600 kb
Host smart-56ca0215-f854-4e00-a4cd-c436faab0d90
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898822080 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.2898822080
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.aon_timer_jump.393216376
Short name T113
Test name
Test status
Simulation time 402541854 ps
CPU time 1.09 seconds
Started Apr 30 02:02:51 PM PDT 24
Finished Apr 30 02:02:53 PM PDT 24
Peak memory 183568 kb
Host smart-9b5c1f02-aec1-457f-98d0-0b8bcd453763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393216376 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.393216376
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.1668088697
Short name T190
Test name
Test status
Simulation time 57371797290 ps
CPU time 88.62 seconds
Started Apr 30 02:02:55 PM PDT 24
Finished Apr 30 02:04:24 PM PDT 24
Peak memory 183800 kb
Host smart-c0711cd5-080b-4ef9-a0ab-47347e92ba0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668088697 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.1668088697
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.1845432919
Short name T232
Test name
Test status
Simulation time 441766414 ps
CPU time 0.71 seconds
Started Apr 30 02:02:51 PM PDT 24
Finished Apr 30 02:02:53 PM PDT 24
Peak memory 183500 kb
Host smart-a61d3ae9-9287-419a-8c04-9bbe159d35c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845432919 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.1845432919
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.356517198
Short name T183
Test name
Test status
Simulation time 275079707211 ps
CPU time 100.03 seconds
Started Apr 30 02:02:49 PM PDT 24
Finished Apr 30 02:04:29 PM PDT 24
Peak memory 195256 kb
Host smart-9a353879-e679-47eb-abbe-8920cb0ef2f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356517198 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_a
ll.356517198
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.2049180182
Short name T242
Test name
Test status
Simulation time 35401259351 ps
CPU time 330.79 seconds
Started Apr 30 02:02:52 PM PDT 24
Finished Apr 30 02:08:23 PM PDT 24
Peak memory 198496 kb
Host smart-8ddffca0-38fb-439a-b012-41131b99bea0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049180182 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.2049180182
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.aon_timer_jump.478769803
Short name T201
Test name
Test status
Simulation time 461313678 ps
CPU time 0.87 seconds
Started Apr 30 02:02:59 PM PDT 24
Finished Apr 30 02:03:01 PM PDT 24
Peak memory 183532 kb
Host smart-5891b61d-be3e-4c30-9f58-624e4ffda37a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478769803 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.478769803
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.533618930
Short name T95
Test name
Test status
Simulation time 22510645667 ps
CPU time 9.01 seconds
Started Apr 30 02:02:50 PM PDT 24
Finished Apr 30 02:02:59 PM PDT 24
Peak memory 183564 kb
Host smart-fad82dc9-6921-4868-85f9-a1d3a612e657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533618930 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.533618930
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.2084413751
Short name T226
Test name
Test status
Simulation time 558044421 ps
CPU time 0.99 seconds
Started Apr 30 02:02:49 PM PDT 24
Finished Apr 30 02:02:50 PM PDT 24
Peak memory 183536 kb
Host smart-917bdae7-8b5b-41ec-bcee-ae864aa31c74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084413751 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.2084413751
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.1017429400
Short name T182
Test name
Test status
Simulation time 41708646155 ps
CPU time 34.4 seconds
Started Apr 30 02:02:49 PM PDT 24
Finished Apr 30 02:03:24 PM PDT 24
Peak memory 183572 kb
Host smart-8e65307c-edcc-45db-bba9-629247c1269a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017429400 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_
all.1017429400
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.4000876261
Short name T193
Test name
Test status
Simulation time 55733606190 ps
CPU time 271.74 seconds
Started Apr 30 02:02:51 PM PDT 24
Finished Apr 30 02:07:24 PM PDT 24
Peak memory 198512 kb
Host smart-c55a619b-48e8-4ebb-8e47-995a123b3efa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000876261 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.4000876261
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.aon_timer_jump.1170027580
Short name T123
Test name
Test status
Simulation time 511156905 ps
CPU time 1.29 seconds
Started Apr 30 02:02:52 PM PDT 24
Finished Apr 30 02:02:54 PM PDT 24
Peak memory 183564 kb
Host smart-f9d996a6-b7f4-4ac4-9dc2-d380f8b948ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170027580 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.1170027580
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.4274646776
Short name T244
Test name
Test status
Simulation time 53073515191 ps
CPU time 45.55 seconds
Started Apr 30 02:02:50 PM PDT 24
Finished Apr 30 02:03:37 PM PDT 24
Peak memory 183624 kb
Host smart-590fa6d1-c672-4862-82c4-b32732f1a054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274646776 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.4274646776
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.4092431357
Short name T254
Test name
Test status
Simulation time 459665213 ps
CPU time 0.87 seconds
Started Apr 30 02:02:50 PM PDT 24
Finished Apr 30 02:02:51 PM PDT 24
Peak memory 183552 kb
Host smart-e30bf6d5-ee03-40cb-a32d-0ddec930d090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092431357 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.4092431357
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.2831108963
Short name T260
Test name
Test status
Simulation time 481024535117 ps
CPU time 189.6 seconds
Started Apr 30 02:02:49 PM PDT 24
Finished Apr 30 02:06:00 PM PDT 24
Peak memory 183704 kb
Host smart-fd5cc03b-185d-486b-90d3-06f349553779
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831108963 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_
all.2831108963
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.3180653767
Short name T245
Test name
Test status
Simulation time 237297379865 ps
CPU time 642 seconds
Started Apr 30 02:02:49 PM PDT 24
Finished Apr 30 02:13:32 PM PDT 24
Peak memory 200696 kb
Host smart-0dfe1f7a-8223-4b58-8d7e-baad9f02770a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180653767 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.3180653767
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.aon_timer_jump.2086372720
Short name T46
Test name
Test status
Simulation time 532130327 ps
CPU time 0.63 seconds
Started Apr 30 02:02:50 PM PDT 24
Finished Apr 30 02:02:51 PM PDT 24
Peak memory 183568 kb
Host smart-71ae5b33-e007-4d80-b38a-538093f25781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086372720 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.2086372720
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.2514717916
Short name T270
Test name
Test status
Simulation time 8166854896 ps
CPU time 6.35 seconds
Started Apr 30 02:02:52 PM PDT 24
Finished Apr 30 02:02:59 PM PDT 24
Peak memory 183628 kb
Host smart-c11cf2a9-363c-4858-8fd3-97ff14e0d3c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514717916 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.2514717916
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.4220595132
Short name T4
Test name
Test status
Simulation time 409079472 ps
CPU time 1.12 seconds
Started Apr 30 02:02:50 PM PDT 24
Finished Apr 30 02:02:52 PM PDT 24
Peak memory 183556 kb
Host smart-acbb6147-5438-447c-a6d9-11b2f1fca9ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220595132 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.4220595132
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.2356349995
Short name T145
Test name
Test status
Simulation time 79717043568 ps
CPU time 15.74 seconds
Started Apr 30 02:02:50 PM PDT 24
Finished Apr 30 02:03:06 PM PDT 24
Peak memory 183612 kb
Host smart-76950c98-945e-4cc2-a23e-5cba7908ca49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356349995 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_
all.2356349995
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.3370738064
Short name T188
Test name
Test status
Simulation time 89516565710 ps
CPU time 188.19 seconds
Started Apr 30 02:02:51 PM PDT 24
Finished Apr 30 02:06:00 PM PDT 24
Peak memory 198472 kb
Host smart-8fb63cc0-7d7f-4251-9b9e-801881b206f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370738064 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.3370738064
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.aon_timer_jump.1702428423
Short name T202
Test name
Test status
Simulation time 408845380 ps
CPU time 0.66 seconds
Started Apr 30 02:02:58 PM PDT 24
Finished Apr 30 02:02:59 PM PDT 24
Peak memory 183572 kb
Host smart-bc0edc98-f97f-4946-ac78-ef543c46294c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702428423 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.1702428423
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.3466527871
Short name T203
Test name
Test status
Simulation time 15983626830 ps
CPU time 26.2 seconds
Started Apr 30 02:02:58 PM PDT 24
Finished Apr 30 02:03:25 PM PDT 24
Peak memory 191764 kb
Host smart-822323da-054e-4876-bb86-70df57cb4d50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466527871 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.3466527871
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.3823379404
Short name T161
Test name
Test status
Simulation time 384579820 ps
CPU time 1.09 seconds
Started Apr 30 02:02:58 PM PDT 24
Finished Apr 30 02:03:01 PM PDT 24
Peak memory 183564 kb
Host smart-b5e3872b-a862-4e37-bee6-ddb9f1fe0248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823379404 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.3823379404
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.1688529173
Short name T211
Test name
Test status
Simulation time 214851384444 ps
CPU time 161.55 seconds
Started Apr 30 02:02:58 PM PDT 24
Finished Apr 30 02:05:41 PM PDT 24
Peak memory 194372 kb
Host smart-ddaa3421-f586-45f7-9308-5bdead8edfad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688529173 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_
all.1688529173
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.3775193112
Short name T83
Test name
Test status
Simulation time 308064901084 ps
CPU time 576.3 seconds
Started Apr 30 02:03:00 PM PDT 24
Finished Apr 30 02:12:38 PM PDT 24
Peak memory 199192 kb
Host smart-728312ae-d7a4-467e-8499-d72d888cd4ff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775193112 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.3775193112
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.aon_timer_jump.533315358
Short name T136
Test name
Test status
Simulation time 574679691 ps
CPU time 0.6 seconds
Started Apr 30 02:03:00 PM PDT 24
Finished Apr 30 02:03:01 PM PDT 24
Peak memory 183560 kb
Host smart-3181ad8c-e2b3-4287-bcd2-6e509c3e02a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533315358 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.533315358
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.2568409319
Short name T265
Test name
Test status
Simulation time 13512968892 ps
CPU time 20.27 seconds
Started Apr 30 02:02:58 PM PDT 24
Finished Apr 30 02:03:19 PM PDT 24
Peak memory 183604 kb
Host smart-a12f27d4-e843-4851-8946-62178f9fc1f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568409319 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.2568409319
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.2109335737
Short name T132
Test name
Test status
Simulation time 567967324 ps
CPU time 0.75 seconds
Started Apr 30 02:02:58 PM PDT 24
Finished Apr 30 02:03:00 PM PDT 24
Peak memory 183536 kb
Host smart-b3cdb40f-ba6f-4e7e-b42e-8babefc6e2b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109335737 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.2109335737
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.3020249919
Short name T168
Test name
Test status
Simulation time 74628546030 ps
CPU time 107.35 seconds
Started Apr 30 02:03:00 PM PDT 24
Finished Apr 30 02:04:49 PM PDT 24
Peak memory 194344 kb
Host smart-9ba47678-d898-4a4c-a5b2-d54f420e27e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020249919 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_
all.3020249919
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.35832627
Short name T156
Test name
Test status
Simulation time 81623832335 ps
CPU time 444.89 seconds
Started Apr 30 02:02:58 PM PDT 24
Finished Apr 30 02:10:24 PM PDT 24
Peak memory 198504 kb
Host smart-93005e46-9987-47dc-ac2e-08c12e93d3de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35832627 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.35832627
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.aon_timer_jump.2619208019
Short name T118
Test name
Test status
Simulation time 579121826 ps
CPU time 0.82 seconds
Started Apr 30 02:03:00 PM PDT 24
Finished Apr 30 02:03:02 PM PDT 24
Peak memory 183544 kb
Host smart-386a6518-c62c-41a1-89ee-c833d0113ad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619208019 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.2619208019
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.2757831766
Short name T280
Test name
Test status
Simulation time 55027163499 ps
CPU time 4.88 seconds
Started Apr 30 02:02:59 PM PDT 24
Finished Apr 30 02:03:05 PM PDT 24
Peak memory 191824 kb
Host smart-6463d76d-ccb7-49d6-b841-9bfd02c2840e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757831766 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.2757831766
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.123503171
Short name T179
Test name
Test status
Simulation time 518483622 ps
CPU time 0.73 seconds
Started Apr 30 02:03:01 PM PDT 24
Finished Apr 30 02:03:03 PM PDT 24
Peak memory 183504 kb
Host smart-e2a446ae-d69e-49bb-a3b6-52a59663f763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123503171 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.123503171
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.608044010
Short name T222
Test name
Test status
Simulation time 443271877010 ps
CPU time 505.84 seconds
Started Apr 30 02:03:00 PM PDT 24
Finished Apr 30 02:11:26 PM PDT 24
Peak memory 194204 kb
Host smart-b78b0c81-337d-4a8d-8723-326b9cab06b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608044010 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_a
ll.608044010
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.860812981
Short name T40
Test name
Test status
Simulation time 299858848871 ps
CPU time 870.4 seconds
Started Apr 30 02:02:58 PM PDT 24
Finished Apr 30 02:17:29 PM PDT 24
Peak memory 203260 kb
Host smart-ca9c6921-9136-459f-8cea-b7afed49fba4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860812981 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.860812981
Directory /workspace/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.aon_timer_jump.3956649610
Short name T205
Test name
Test status
Simulation time 433813549 ps
CPU time 1.25 seconds
Started Apr 30 02:02:59 PM PDT 24
Finished Apr 30 02:03:01 PM PDT 24
Peak memory 183548 kb
Host smart-c067717c-b411-4357-88bb-78b4781a0c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956649610 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.3956649610
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.3011330000
Short name T25
Test name
Test status
Simulation time 27116636359 ps
CPU time 37.11 seconds
Started Apr 30 02:02:59 PM PDT 24
Finished Apr 30 02:03:37 PM PDT 24
Peak memory 183548 kb
Host smart-48a313de-f8e6-4fef-9735-a3c4e2b14612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011330000 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.3011330000
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.555662420
Short name T6
Test name
Test status
Simulation time 432573333 ps
CPU time 1.19 seconds
Started Apr 30 02:02:59 PM PDT 24
Finished Apr 30 02:03:01 PM PDT 24
Peak memory 183576 kb
Host smart-8b3af2f8-9134-4ad4-8b41-1bab37f2981a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555662420 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.555662420
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.304838897
Short name T278
Test name
Test status
Simulation time 79345461502 ps
CPU time 127.62 seconds
Started Apr 30 02:03:00 PM PDT 24
Finished Apr 30 02:05:08 PM PDT 24
Peak memory 183524 kb
Host smart-994b0215-5856-431e-a6cf-8202037df08e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304838897 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_a
ll.304838897
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.3346577831
Short name T82
Test name
Test status
Simulation time 90182130297 ps
CPU time 339.92 seconds
Started Apr 30 02:03:00 PM PDT 24
Finished Apr 30 02:08:41 PM PDT 24
Peak memory 198464 kb
Host smart-b709870c-b706-4745-99e5-0858d8c0660c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346577831 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.3346577831
Directory /workspace/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_jump.3309069865
Short name T225
Test name
Test status
Simulation time 455320488 ps
CPU time 0.68 seconds
Started Apr 30 02:03:01 PM PDT 24
Finished Apr 30 02:03:03 PM PDT 24
Peak memory 183512 kb
Host smart-88642da0-3d8a-4a58-aef0-da0d96747dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309069865 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.3309069865
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.1386950541
Short name T159
Test name
Test status
Simulation time 21612327601 ps
CPU time 35.5 seconds
Started Apr 30 02:03:02 PM PDT 24
Finished Apr 30 02:03:38 PM PDT 24
Peak memory 183632 kb
Host smart-d7a566f6-d6f0-4c3b-9e8c-ce42e2031c8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386950541 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.1386950541
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.2786116807
Short name T204
Test name
Test status
Simulation time 504586630 ps
CPU time 1.23 seconds
Started Apr 30 02:02:59 PM PDT 24
Finished Apr 30 02:03:01 PM PDT 24
Peak memory 183556 kb
Host smart-76465b2b-ec7a-41a9-a519-79158f6caa89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786116807 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.2786116807
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.717471231
Short name T116
Test name
Test status
Simulation time 112473117813 ps
CPU time 12.91 seconds
Started Apr 30 02:02:59 PM PDT 24
Finished Apr 30 02:03:13 PM PDT 24
Peak memory 193116 kb
Host smart-32cb69b2-a341-4414-81b1-7097451a6375
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717471231 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_a
ll.717471231
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.1620090225
Short name T269
Test name
Test status
Simulation time 165492411692 ps
CPU time 419.08 seconds
Started Apr 30 02:02:59 PM PDT 24
Finished Apr 30 02:10:00 PM PDT 24
Peak memory 198492 kb
Host smart-0df6d87e-b3f5-4684-be0f-1a5d8d580314
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620090225 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.1620090225
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.aon_timer_jump.3323510713
Short name T23
Test name
Test status
Simulation time 422912440 ps
CPU time 0.66 seconds
Started Apr 30 02:02:58 PM PDT 24
Finished Apr 30 02:03:00 PM PDT 24
Peak memory 183572 kb
Host smart-29140982-f996-421f-ba24-44c6d9a6ae90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323510713 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.3323510713
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.2995229234
Short name T247
Test name
Test status
Simulation time 60867955402 ps
CPU time 88.51 seconds
Started Apr 30 02:02:59 PM PDT 24
Finished Apr 30 02:04:29 PM PDT 24
Peak memory 191728 kb
Host smart-b0d7d1d0-99d3-4294-b418-08e78303b4f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995229234 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.2995229234
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.1490297508
Short name T154
Test name
Test status
Simulation time 353012517 ps
CPU time 0.64 seconds
Started Apr 30 02:03:03 PM PDT 24
Finished Apr 30 02:03:04 PM PDT 24
Peak memory 183540 kb
Host smart-5279051c-b857-412b-b2ba-9b056c911c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490297508 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.1490297508
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.3611081929
Short name T228
Test name
Test status
Simulation time 142347443809 ps
CPU time 56.77 seconds
Started Apr 30 02:03:02 PM PDT 24
Finished Apr 30 02:03:59 PM PDT 24
Peak memory 194940 kb
Host smart-c6fe3787-540b-4668-b56f-6ae4a755d704
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611081929 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_
all.3611081929
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_jump.2048846968
Short name T275
Test name
Test status
Simulation time 423263116 ps
CPU time 0.9 seconds
Started Apr 30 02:02:19 PM PDT 24
Finished Apr 30 02:02:20 PM PDT 24
Peak memory 183528 kb
Host smart-c465f86c-7ffd-4e6e-811b-698c4d2a8d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048846968 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.2048846968
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.3181045232
Short name T279
Test name
Test status
Simulation time 1794926472 ps
CPU time 3.38 seconds
Started Apr 30 02:02:13 PM PDT 24
Finished Apr 30 02:02:17 PM PDT 24
Peak memory 183572 kb
Host smart-2405bccb-353b-4382-bad1-668ee6ff608e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181045232 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.3181045232
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.3783741748
Short name T263
Test name
Test status
Simulation time 508853319 ps
CPU time 1.23 seconds
Started Apr 30 02:02:11 PM PDT 24
Finished Apr 30 02:02:12 PM PDT 24
Peak memory 183544 kb
Host smart-43ca86ae-fa9c-4e86-a467-47194be1a22f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783741748 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.3783741748
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.2598831160
Short name T250
Test name
Test status
Simulation time 209601505662 ps
CPU time 88.1 seconds
Started Apr 30 02:02:15 PM PDT 24
Finished Apr 30 02:03:44 PM PDT 24
Peak memory 183628 kb
Host smart-c4098655-1743-4b77-b826-b79a3734c0cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598831160 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_a
ll.2598831160
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.1554273932
Short name T39
Test name
Test status
Simulation time 75375736566 ps
CPU time 141.6 seconds
Started Apr 30 02:02:10 PM PDT 24
Finished Apr 30 02:04:32 PM PDT 24
Peak memory 198472 kb
Host smart-a0f69a4a-d4d9-4252-af00-394bb2f7fa46
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554273932 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.1554273932
Directory /workspace/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.aon_timer_jump.3711316221
Short name T26
Test name
Test status
Simulation time 615180713 ps
CPU time 1.58 seconds
Started Apr 30 02:02:12 PM PDT 24
Finished Apr 30 02:02:14 PM PDT 24
Peak memory 183564 kb
Host smart-577c8c7c-ee36-494e-ab13-10a62fc2bfcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711316221 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.3711316221
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.309674222
Short name T144
Test name
Test status
Simulation time 38160577638 ps
CPU time 19.11 seconds
Started Apr 30 02:02:09 PM PDT 24
Finished Apr 30 02:02:29 PM PDT 24
Peak memory 183592 kb
Host smart-a58bcbe5-45a7-4858-8683-afd5836542d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309674222 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.309674222
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.3424225956
Short name T11
Test name
Test status
Simulation time 475355127 ps
CPU time 0.57 seconds
Started Apr 30 02:02:18 PM PDT 24
Finished Apr 30 02:02:19 PM PDT 24
Peak memory 183544 kb
Host smart-45ae87c3-9c24-4a30-875f-48060898163f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424225956 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.3424225956
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.3993470180
Short name T127
Test name
Test status
Simulation time 92077067304 ps
CPU time 72.74 seconds
Started Apr 30 02:02:11 PM PDT 24
Finished Apr 30 02:03:25 PM PDT 24
Peak memory 183532 kb
Host smart-f58d78ef-96e5-4825-95a5-73d2fa4733f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993470180 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_a
ll.3993470180
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.4045188915
Short name T56
Test name
Test status
Simulation time 251547972713 ps
CPU time 450.61 seconds
Started Apr 30 02:02:18 PM PDT 24
Finished Apr 30 02:09:49 PM PDT 24
Peak memory 198472 kb
Host smart-a5edefbb-12af-484d-9062-9ddee00f91ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045188915 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.4045188915
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.aon_timer_jump.3180298485
Short name T234
Test name
Test status
Simulation time 562657981 ps
CPU time 0.69 seconds
Started Apr 30 02:02:14 PM PDT 24
Finished Apr 30 02:02:15 PM PDT 24
Peak memory 183532 kb
Host smart-d5cca557-0ed3-46fa-a2f5-cc921d3166c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180298485 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.3180298485
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.2330357276
Short name T189
Test name
Test status
Simulation time 23843883799 ps
CPU time 9.24 seconds
Started Apr 30 02:02:15 PM PDT 24
Finished Apr 30 02:02:25 PM PDT 24
Peak memory 183628 kb
Host smart-7828a53c-b0a7-4c92-b7b7-19a6f2ca1b13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330357276 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.2330357276
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.3511595609
Short name T176
Test name
Test status
Simulation time 461400780 ps
CPU time 0.69 seconds
Started Apr 30 02:02:12 PM PDT 24
Finished Apr 30 02:02:13 PM PDT 24
Peak memory 183576 kb
Host smart-db703305-c4f5-430d-88fd-63e16a6430a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511595609 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.3511595609
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.1397333228
Short name T85
Test name
Test status
Simulation time 70348855267 ps
CPU time 87.43 seconds
Started Apr 30 02:02:13 PM PDT 24
Finished Apr 30 02:03:41 PM PDT 24
Peak memory 198452 kb
Host smart-9a495be9-ae54-4685-b7da-7ee946af775b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397333228 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.1397333228
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.aon_timer_jump.1246465559
Short name T150
Test name
Test status
Simulation time 419963446 ps
CPU time 0.87 seconds
Started Apr 30 02:02:12 PM PDT 24
Finished Apr 30 02:02:13 PM PDT 24
Peak memory 183564 kb
Host smart-27a51624-fceb-4d40-998a-bb7b302b7a75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246465559 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.1246465559
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.822239710
Short name T8
Test name
Test status
Simulation time 19982937665 ps
CPU time 8.8 seconds
Started Apr 30 02:02:14 PM PDT 24
Finished Apr 30 02:02:24 PM PDT 24
Peak memory 191824 kb
Host smart-c846889d-8464-49ec-94e5-f63f3399e703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822239710 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.822239710
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.43470602
Short name T223
Test name
Test status
Simulation time 457544650 ps
CPU time 1.27 seconds
Started Apr 30 02:02:18 PM PDT 24
Finished Apr 30 02:02:20 PM PDT 24
Peak memory 183544 kb
Host smart-dfd07c11-6f75-41b4-b6ef-ad477723a68e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43470602 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.43470602
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.1788129475
Short name T94
Test name
Test status
Simulation time 43452129156 ps
CPU time 23.92 seconds
Started Apr 30 02:02:13 PM PDT 24
Finished Apr 30 02:02:38 PM PDT 24
Peak memory 193792 kb
Host smart-886561f9-a5a9-43ae-98fe-e71f94f1dfc0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788129475 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_a
ll.1788129475
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_jump.536968395
Short name T152
Test name
Test status
Simulation time 498278246 ps
CPU time 0.91 seconds
Started Apr 30 02:02:16 PM PDT 24
Finished Apr 30 02:02:18 PM PDT 24
Peak memory 183536 kb
Host smart-3b6535ec-31cd-4696-9c84-9a1749370fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536968395 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.536968395
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.654315549
Short name T253
Test name
Test status
Simulation time 5942317091 ps
CPU time 5.3 seconds
Started Apr 30 02:02:17 PM PDT 24
Finished Apr 30 02:02:22 PM PDT 24
Peak memory 183616 kb
Host smart-030cb4a5-598b-49b3-bbaa-0975f94c5bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654315549 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.654315549
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.568406832
Short name T9
Test name
Test status
Simulation time 402127961 ps
CPU time 0.8 seconds
Started Apr 30 02:02:12 PM PDT 24
Finished Apr 30 02:02:14 PM PDT 24
Peak memory 183564 kb
Host smart-ae199fae-0d5f-40fa-8615-0eb8ac88d205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568406832 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.568406832
Directory /workspace/9.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.1911796973
Short name T220
Test name
Test status
Simulation time 45124446169 ps
CPU time 6.14 seconds
Started Apr 30 02:02:20 PM PDT 24
Finished Apr 30 02:02:27 PM PDT 24
Peak memory 183696 kb
Host smart-398e463b-bee8-4e06-9361-105d281327e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911796973 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_a
ll.1911796973
Directory /workspace/9.aon_timer_stress_all/latest
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