Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
92.98 99.25 93.67 100.00 98.40 99.51 67.06


Total test records in report: 424
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T288 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.534808002 May 02 02:59:27 PM PDT 24 May 02 02:59:31 PM PDT 24 381907321 ps
T24 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.1561345505 May 02 02:59:03 PM PDT 24 May 02 02:59:10 PM PDT 24 7858701970 ps
T289 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.1370548988 May 02 02:58:59 PM PDT 24 May 02 02:59:01 PM PDT 24 335153498 ps
T290 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.3966341028 May 02 02:59:00 PM PDT 24 May 02 02:59:03 PM PDT 24 303893675 ps
T25 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.1120250181 May 02 02:59:15 PM PDT 24 May 02 02:59:18 PM PDT 24 512968668 ps
T26 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.3035137424 May 02 02:59:18 PM PDT 24 May 02 02:59:21 PM PDT 24 392601530 ps
T291 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.1125220407 May 02 02:59:26 PM PDT 24 May 02 02:59:29 PM PDT 24 357827853 ps
T27 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.1610314784 May 02 02:59:01 PM PDT 24 May 02 02:59:05 PM PDT 24 4258951638 ps
T292 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.4136362200 May 02 02:59:22 PM PDT 24 May 02 02:59:25 PM PDT 24 616411729 ps
T80 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.531897821 May 02 02:58:59 PM PDT 24 May 02 02:59:03 PM PDT 24 1576409580 ps
T293 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.2412151352 May 02 02:59:14 PM PDT 24 May 02 02:59:16 PM PDT 24 507557753 ps
T294 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.2167401791 May 02 02:59:26 PM PDT 24 May 02 02:59:30 PM PDT 24 483586792 ps
T295 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.3785984209 May 02 02:59:00 PM PDT 24 May 02 02:59:03 PM PDT 24 404884580 ps
T81 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.3839470808 May 02 02:59:01 PM PDT 24 May 02 02:59:04 PM PDT 24 1130638500 ps
T54 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.1319779511 May 02 02:58:56 PM PDT 24 May 02 02:58:58 PM PDT 24 529971995 ps
T28 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.3449393014 May 02 02:59:14 PM PDT 24 May 02 02:59:23 PM PDT 24 8235637175 ps
T296 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.409546529 May 02 02:59:03 PM PDT 24 May 02 02:59:07 PM PDT 24 473885615 ps
T55 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.1504862960 May 02 02:59:12 PM PDT 24 May 02 02:59:14 PM PDT 24 491125508 ps
T104 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.3094076107 May 02 02:58:56 PM PDT 24 May 02 02:59:11 PM PDT 24 8309409851 ps
T56 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.3268962993 May 02 02:59:10 PM PDT 24 May 02 02:59:12 PM PDT 24 501411965 ps
T297 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.2637724164 May 02 02:59:14 PM PDT 24 May 02 02:59:17 PM PDT 24 605777801 ps
T298 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.2485743897 May 02 02:59:01 PM PDT 24 May 02 02:59:04 PM PDT 24 290586362 ps
T299 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.2451536513 May 02 02:59:23 PM PDT 24 May 02 02:59:27 PM PDT 24 279567716 ps
T82 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.3827700860 May 02 02:59:22 PM PDT 24 May 02 02:59:26 PM PDT 24 1940619859 ps
T57 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.2557889721 May 02 02:59:00 PM PDT 24 May 02 02:59:07 PM PDT 24 11671842591 ps
T83 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.2593339963 May 02 02:59:18 PM PDT 24 May 02 02:59:20 PM PDT 24 515523175 ps
T58 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.358034781 May 02 02:58:57 PM PDT 24 May 02 02:59:15 PM PDT 24 6305646623 ps
T59 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.106183054 May 02 02:59:18 PM PDT 24 May 02 02:59:21 PM PDT 24 310849491 ps
T300 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.663691182 May 02 02:59:03 PM PDT 24 May 02 02:59:07 PM PDT 24 919969195 ps
T301 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.568966136 May 02 02:59:00 PM PDT 24 May 02 02:59:03 PM PDT 24 318202595 ps
T302 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.2961352697 May 02 02:59:04 PM PDT 24 May 02 02:59:07 PM PDT 24 395033155 ps
T105 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.4111793679 May 02 02:58:58 PM PDT 24 May 02 02:59:04 PM PDT 24 7909177542 ps
T84 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.2561177212 May 02 02:59:08 PM PDT 24 May 02 02:59:10 PM PDT 24 1262455507 ps
T71 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.3611830204 May 02 02:58:58 PM PDT 24 May 02 02:59:00 PM PDT 24 423200301 ps
T72 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.1435320940 May 02 02:59:14 PM PDT 24 May 02 02:59:17 PM PDT 24 312014656 ps
T303 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.645996378 May 02 02:59:22 PM PDT 24 May 02 02:59:25 PM PDT 24 424772568 ps
T108 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.3343921249 May 02 02:59:20 PM PDT 24 May 02 02:59:29 PM PDT 24 4024649984 ps
T85 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.1461562450 May 02 02:59:13 PM PDT 24 May 02 02:59:18 PM PDT 24 1818348356 ps
T304 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.1553892057 May 02 02:59:16 PM PDT 24 May 02 02:59:19 PM PDT 24 500738350 ps
T305 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.714132767 May 02 02:59:21 PM PDT 24 May 02 02:59:23 PM PDT 24 479079008 ps
T73 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.1771956154 May 02 02:58:58 PM PDT 24 May 02 02:59:00 PM PDT 24 433081836 ps
T306 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.3167536454 May 02 02:59:27 PM PDT 24 May 02 02:59:30 PM PDT 24 557974167 ps
T307 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.1359555680 May 02 02:58:58 PM PDT 24 May 02 02:59:02 PM PDT 24 1270954874 ps
T308 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.2573697395 May 02 02:58:57 PM PDT 24 May 02 02:58:58 PM PDT 24 310688587 ps
T309 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.39096285 May 02 02:59:18 PM PDT 24 May 02 02:59:21 PM PDT 24 564625260 ps
T86 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.3477758671 May 02 02:59:05 PM PDT 24 May 02 02:59:08 PM PDT 24 2202918927 ps
T310 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.2292532791 May 02 02:59:26 PM PDT 24 May 02 02:59:29 PM PDT 24 405417887 ps
T311 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.1268930195 May 02 02:59:13 PM PDT 24 May 02 02:59:15 PM PDT 24 455354437 ps
T312 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.746091864 May 02 02:59:00 PM PDT 24 May 02 02:59:04 PM PDT 24 370682570 ps
T87 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.3778370191 May 02 02:59:02 PM PDT 24 May 02 02:59:05 PM PDT 24 2370052357 ps
T313 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.2359704910 May 02 02:59:06 PM PDT 24 May 02 02:59:08 PM PDT 24 528081279 ps
T314 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.940501808 May 02 02:59:15 PM PDT 24 May 02 02:59:21 PM PDT 24 2735386707 ps
T315 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.4251985521 May 02 02:59:14 PM PDT 24 May 02 02:59:17 PM PDT 24 492791563 ps
T74 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.1218306048 May 02 02:59:02 PM PDT 24 May 02 02:59:09 PM PDT 24 6797682224 ps
T316 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.3903945069 May 02 02:58:59 PM PDT 24 May 02 02:59:02 PM PDT 24 376562005 ps
T317 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.3139765111 May 02 02:59:23 PM PDT 24 May 02 02:59:25 PM PDT 24 571670170 ps
T318 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.2582545467 May 02 02:58:58 PM PDT 24 May 02 02:59:00 PM PDT 24 604118560 ps
T319 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.2845323823 May 02 02:59:23 PM PDT 24 May 02 02:59:27 PM PDT 24 359367727 ps
T320 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.388736112 May 02 02:59:20 PM PDT 24 May 02 02:59:23 PM PDT 24 559665884 ps
T321 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.1647627284 May 02 02:59:07 PM PDT 24 May 02 02:59:10 PM PDT 24 403612722 ps
T322 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.1581728474 May 02 02:59:28 PM PDT 24 May 02 02:59:31 PM PDT 24 451197741 ps
T323 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.3986181389 May 02 02:58:59 PM PDT 24 May 02 02:59:01 PM PDT 24 299868414 ps
T75 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.1014483842 May 02 02:59:04 PM PDT 24 May 02 02:59:07 PM PDT 24 526094664 ps
T324 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.929221250 May 02 02:59:22 PM PDT 24 May 02 02:59:25 PM PDT 24 522873786 ps
T325 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.1047157202 May 02 02:59:04 PM PDT 24 May 02 02:59:07 PM PDT 24 539982493 ps
T326 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.2421294459 May 02 02:59:26 PM PDT 24 May 02 02:59:30 PM PDT 24 517133678 ps
T327 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.3556677093 May 02 02:58:58 PM PDT 24 May 02 02:59:01 PM PDT 24 555966505 ps
T328 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.2147765480 May 02 02:59:03 PM PDT 24 May 02 02:59:07 PM PDT 24 503935767 ps
T329 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.4162320008 May 02 02:59:02 PM PDT 24 May 02 02:59:07 PM PDT 24 1261673245 ps
T330 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.2177100898 May 02 02:59:25 PM PDT 24 May 02 02:59:28 PM PDT 24 534572721 ps
T331 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.1371174302 May 02 02:59:22 PM PDT 24 May 02 02:59:25 PM PDT 24 488256166 ps
T332 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.1533667539 May 02 02:59:20 PM PDT 24 May 02 02:59:22 PM PDT 24 1231958691 ps
T76 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.1671823511 May 02 02:58:58 PM PDT 24 May 02 02:59:01 PM PDT 24 491170298 ps
T333 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.1801998384 May 02 02:58:59 PM PDT 24 May 02 02:59:02 PM PDT 24 342774520 ps
T334 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.3053490495 May 02 02:59:00 PM PDT 24 May 02 02:59:09 PM PDT 24 7354219545 ps
T335 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.3550628603 May 02 02:59:25 PM PDT 24 May 02 02:59:29 PM PDT 24 279368551 ps
T336 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.4118447535 May 02 02:59:28 PM PDT 24 May 02 02:59:31 PM PDT 24 357292643 ps
T337 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.2247817194 May 02 02:59:24 PM PDT 24 May 02 02:59:27 PM PDT 24 469792645 ps
T338 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.4087413090 May 02 02:58:57 PM PDT 24 May 02 02:58:58 PM PDT 24 463864918 ps
T339 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.2848353401 May 02 02:59:14 PM PDT 24 May 02 02:59:16 PM PDT 24 1568100032 ps
T340 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.2098728595 May 02 02:59:20 PM PDT 24 May 02 02:59:22 PM PDT 24 296692300 ps
T341 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.3345631329 May 02 02:59:16 PM PDT 24 May 02 02:59:19 PM PDT 24 302911769 ps
T342 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.91757701 May 02 02:59:08 PM PDT 24 May 02 02:59:12 PM PDT 24 493669394 ps
T343 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.3891735606 May 02 02:59:28 PM PDT 24 May 02 02:59:31 PM PDT 24 496063436 ps
T77 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.324563660 May 02 02:59:04 PM PDT 24 May 02 02:59:07 PM PDT 24 426314634 ps
T344 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.3503833325 May 02 02:59:26 PM PDT 24 May 02 02:59:30 PM PDT 24 496246011 ps
T345 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.3651108576 May 02 02:58:57 PM PDT 24 May 02 02:59:00 PM PDT 24 425523793 ps
T346 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.3854950779 May 02 02:59:15 PM PDT 24 May 02 02:59:18 PM PDT 24 717762968 ps
T347 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.274058080 May 02 02:59:14 PM PDT 24 May 02 02:59:16 PM PDT 24 534317323 ps
T348 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.3069345154 May 02 02:59:00 PM PDT 24 May 02 02:59:06 PM PDT 24 1163985449 ps
T349 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.3465159774 May 02 02:59:25 PM PDT 24 May 02 02:59:29 PM PDT 24 389311687 ps
T106 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.2966354880 May 02 02:59:19 PM PDT 24 May 02 02:59:28 PM PDT 24 8839460526 ps
T350 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.3327325408 May 02 02:59:01 PM PDT 24 May 02 02:59:04 PM PDT 24 720078354 ps
T351 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.533539075 May 02 02:59:06 PM PDT 24 May 02 02:59:08 PM PDT 24 313169664 ps
T352 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.277052999 May 02 02:59:20 PM PDT 24 May 02 02:59:24 PM PDT 24 527565698 ps
T60 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.927244797 May 02 02:59:01 PM PDT 24 May 02 02:59:05 PM PDT 24 434962135 ps
T353 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.703111962 May 02 02:59:19 PM PDT 24 May 02 02:59:21 PM PDT 24 482047700 ps
T354 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.2753570982 May 02 02:59:02 PM PDT 24 May 02 02:59:05 PM PDT 24 426635303 ps
T355 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.2558737970 May 02 02:59:24 PM PDT 24 May 02 02:59:27 PM PDT 24 426719656 ps
T356 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.2281754525 May 02 02:58:59 PM PDT 24 May 02 02:59:02 PM PDT 24 389556654 ps
T357 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.2540132578 May 02 02:58:58 PM PDT 24 May 02 02:59:00 PM PDT 24 359764308 ps
T109 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.4102323693 May 02 02:59:22 PM PDT 24 May 02 02:59:29 PM PDT 24 8921617149 ps
T358 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.2390531549 May 02 02:59:16 PM PDT 24 May 02 02:59:20 PM PDT 24 597795125 ps
T359 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.4030194039 May 02 02:59:25 PM PDT 24 May 02 02:59:28 PM PDT 24 427565873 ps
T360 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.2063840247 May 02 02:59:23 PM PDT 24 May 02 02:59:26 PM PDT 24 434343359 ps
T361 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.210629257 May 02 02:59:01 PM PDT 24 May 02 02:59:05 PM PDT 24 367467021 ps
T362 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.3296458076 May 02 02:59:00 PM PDT 24 May 02 02:59:04 PM PDT 24 2508902769 ps
T363 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.2555104131 May 02 02:59:13 PM PDT 24 May 02 02:59:15 PM PDT 24 438002562 ps
T364 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.1867525636 May 02 02:58:59 PM PDT 24 May 02 02:59:02 PM PDT 24 307259942 ps
T365 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.669857564 May 02 02:58:59 PM PDT 24 May 02 02:59:03 PM PDT 24 400755094 ps
T366 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.3816560583 May 02 02:59:15 PM PDT 24 May 02 02:59:18 PM PDT 24 437965813 ps
T367 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.4018894447 May 02 02:59:04 PM PDT 24 May 02 02:59:07 PM PDT 24 1064723716 ps
T368 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.1828237445 May 02 02:58:59 PM PDT 24 May 02 02:59:03 PM PDT 24 1149788382 ps
T369 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.873353101 May 02 02:59:24 PM PDT 24 May 02 02:59:28 PM PDT 24 451893932 ps
T110 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.3192947347 May 02 02:59:14 PM PDT 24 May 02 02:59:19 PM PDT 24 4046542116 ps
T370 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.426964567 May 02 02:59:20 PM PDT 24 May 02 02:59:24 PM PDT 24 2734790274 ps
T371 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.1456117512 May 02 02:58:59 PM PDT 24 May 02 02:59:09 PM PDT 24 4308211121 ps
T372 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.1772267737 May 02 02:59:25 PM PDT 24 May 02 02:59:28 PM PDT 24 389448970 ps
T373 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.102097979 May 02 02:58:58 PM PDT 24 May 02 02:59:00 PM PDT 24 475073707 ps
T374 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.4115420483 May 02 02:59:15 PM PDT 24 May 02 02:59:17 PM PDT 24 398678053 ps
T375 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.1771992987 May 02 02:58:59 PM PDT 24 May 02 02:59:02 PM PDT 24 372981558 ps
T78 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.2346806637 May 02 02:59:05 PM PDT 24 May 02 02:59:07 PM PDT 24 386407437 ps
T376 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.530926123 May 02 02:59:26 PM PDT 24 May 02 02:59:30 PM PDT 24 404359104 ps
T377 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.3197296941 May 02 02:59:23 PM PDT 24 May 02 02:59:26 PM PDT 24 578416719 ps
T378 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.2248781956 May 02 02:59:14 PM PDT 24 May 02 02:59:16 PM PDT 24 536261650 ps
T379 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.1118313212 May 02 02:59:30 PM PDT 24 May 02 02:59:33 PM PDT 24 418660231 ps
T380 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.2815480738 May 02 02:59:06 PM PDT 24 May 02 02:59:08 PM PDT 24 535678340 ps
T381 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.2303287073 May 02 02:58:59 PM PDT 24 May 02 02:59:14 PM PDT 24 7088360543 ps
T382 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.3403843573 May 02 02:59:13 PM PDT 24 May 02 02:59:16 PM PDT 24 802997615 ps
T107 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.2879050179 May 02 02:59:04 PM PDT 24 May 02 02:59:19 PM PDT 24 8345559134 ps
T79 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.2059636067 May 02 02:58:58 PM PDT 24 May 02 02:59:01 PM PDT 24 813810445 ps
T383 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.753077396 May 02 02:59:02 PM PDT 24 May 02 02:59:07 PM PDT 24 409951204 ps
T384 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.1024030667 May 02 02:59:00 PM PDT 24 May 02 02:59:05 PM PDT 24 473405402 ps
T385 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.607602504 May 02 02:59:14 PM PDT 24 May 02 02:59:19 PM PDT 24 1891388476 ps
T386 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.3067060321 May 02 02:59:25 PM PDT 24 May 02 02:59:28 PM PDT 24 326986852 ps
T387 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.1427860182 May 02 02:58:59 PM PDT 24 May 02 02:59:14 PM PDT 24 8155305543 ps
T388 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.3373306278 May 02 02:59:23 PM PDT 24 May 02 02:59:39 PM PDT 24 7854625533 ps
T389 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.2005582527 May 02 02:59:08 PM PDT 24 May 02 02:59:10 PM PDT 24 410421985 ps
T390 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.3023959782 May 02 02:59:18 PM PDT 24 May 02 02:59:22 PM PDT 24 1090998239 ps
T391 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.3645844272 May 02 02:59:18 PM PDT 24 May 02 02:59:20 PM PDT 24 438538899 ps
T392 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.4114483065 May 02 02:59:23 PM PDT 24 May 02 02:59:25 PM PDT 24 329240145 ps
T393 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.537591975 May 02 02:59:20 PM PDT 24 May 02 02:59:23 PM PDT 24 497660979 ps
T394 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.61649444 May 02 02:59:10 PM PDT 24 May 02 02:59:12 PM PDT 24 1515331041 ps
T395 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.713229873 May 02 02:59:07 PM PDT 24 May 02 02:59:10 PM PDT 24 896865340 ps
T396 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.2550530168 May 02 02:58:58 PM PDT 24 May 02 02:59:00 PM PDT 24 333449717 ps
T397 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.2715183930 May 02 02:59:00 PM PDT 24 May 02 02:59:04 PM PDT 24 4670792488 ps
T398 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.3412393389 May 02 02:58:58 PM PDT 24 May 02 02:59:01 PM PDT 24 521602327 ps
T399 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.3004895747 May 02 02:59:23 PM PDT 24 May 02 02:59:26 PM PDT 24 341939006 ps
T400 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.1009116587 May 02 02:59:19 PM PDT 24 May 02 02:59:21 PM PDT 24 1173342284 ps
T401 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.112026565 May 02 02:59:23 PM PDT 24 May 02 02:59:28 PM PDT 24 4794090868 ps
T61 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.1091975500 May 02 02:59:16 PM PDT 24 May 02 02:59:19 PM PDT 24 410819717 ps
T402 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.430696484 May 02 02:59:21 PM PDT 24 May 02 02:59:23 PM PDT 24 324218128 ps
T403 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.1892167461 May 02 02:59:14 PM PDT 24 May 02 02:59:20 PM PDT 24 4264016304 ps
T404 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.3323132576 May 02 02:59:03 PM PDT 24 May 02 02:59:06 PM PDT 24 535266043 ps
T405 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.2051084253 May 02 02:59:26 PM PDT 24 May 02 02:59:29 PM PDT 24 307219401 ps
T406 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.2253475382 May 02 02:59:04 PM PDT 24 May 02 02:59:19 PM PDT 24 8960528624 ps
T407 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.1555449469 May 02 02:59:16 PM PDT 24 May 02 02:59:24 PM PDT 24 4170741177 ps
T408 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.3897858792 May 02 02:59:07 PM PDT 24 May 02 02:59:10 PM PDT 24 591347608 ps
T409 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.4038055369 May 02 02:59:18 PM PDT 24 May 02 02:59:20 PM PDT 24 341751053 ps
T410 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.1732780394 May 02 02:59:20 PM PDT 24 May 02 02:59:23 PM PDT 24 379445102 ps
T411 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.3335078479 May 02 02:59:24 PM PDT 24 May 02 02:59:27 PM PDT 24 303832863 ps
T412 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.191162799 May 02 02:59:16 PM PDT 24 May 02 02:59:19 PM PDT 24 4593316316 ps
T413 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.853334183 May 02 02:59:20 PM PDT 24 May 02 02:59:24 PM PDT 24 1355575750 ps
T414 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.244747478 May 02 02:59:24 PM PDT 24 May 02 02:59:27 PM PDT 24 341035891 ps
T415 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.440816416 May 02 02:58:58 PM PDT 24 May 02 02:59:00 PM PDT 24 479696096 ps
T416 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.2153944348 May 02 02:59:14 PM PDT 24 May 02 02:59:17 PM PDT 24 530428525 ps
T417 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.356426548 May 02 02:59:03 PM PDT 24 May 02 02:59:06 PM PDT 24 529687313 ps
T418 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.1513650028 May 02 02:59:19 PM PDT 24 May 02 02:59:21 PM PDT 24 492856863 ps
T419 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.962937925 May 02 02:59:13 PM PDT 24 May 02 02:59:15 PM PDT 24 294467506 ps
T420 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.3078545799 May 02 02:59:03 PM PDT 24 May 02 02:59:18 PM PDT 24 7643937868 ps
T421 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.1430512107 May 02 02:59:02 PM PDT 24 May 02 02:59:05 PM PDT 24 574102224 ps
T422 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.88929022 May 02 02:59:26 PM PDT 24 May 02 02:59:29 PM PDT 24 329539358 ps
T423 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.921742811 May 02 02:59:04 PM PDT 24 May 02 02:59:07 PM PDT 24 495109567 ps
T424 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.1406626187 May 02 02:59:02 PM PDT 24 May 02 02:59:05 PM PDT 24 511295178 ps

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.227558294
Short name T3
Test name
Test status
Simulation time 50103972637 ps
CPU time 362.98 seconds
Started May 02 03:54:33 PM PDT 24
Finished May 02 04:00:37 PM PDT 24
Peak memory 198488 kb
Host smart-9d6dfa90-7fdd-411b-89ef-3a6ea6566cbf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227558294 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.227558294
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.982234674
Short name T30
Test name
Test status
Simulation time 60819136272 ps
CPU time 523.84 seconds
Started May 02 03:54:08 PM PDT 24
Finished May 02 04:02:55 PM PDT 24
Peak memory 198480 kb
Host smart-edd64fb3-391c-4011-82ab-4e20e1a8cb55
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982234674 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.982234674
Directory /workspace/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.1561345505
Short name T24
Test name
Test status
Simulation time 7858701970 ps
CPU time 4.09 seconds
Started May 02 02:59:03 PM PDT 24
Finished May 02 02:59:10 PM PDT 24
Peak memory 197824 kb
Host smart-dd4f7337-4c79-4c36-a766-5a2207ca2c5c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561345505 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl
_intg_err.1561345505
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.1308001582
Short name T8
Test name
Test status
Simulation time 192628332931 ps
CPU time 112.3 seconds
Started May 02 03:54:43 PM PDT 24
Finished May 02 03:56:37 PM PDT 24
Peak memory 194448 kb
Host smart-b78ef1fd-ed8a-48fe-9ace-0173f0c4e713
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308001582 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_
all.1308001582
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.3984556086
Short name T42
Test name
Test status
Simulation time 315136607683 ps
CPU time 666.61 seconds
Started May 02 03:54:50 PM PDT 24
Finished May 02 04:06:00 PM PDT 24
Peak memory 209132 kb
Host smart-eb895790-3ea7-4190-bb30-01dd483f01f8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984556086 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.3984556086
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.1815870692
Short name T15
Test name
Test status
Simulation time 4250645229 ps
CPU time 2.04 seconds
Started May 02 03:54:18 PM PDT 24
Finished May 02 03:54:21 PM PDT 24
Peak memory 214892 kb
Host smart-bafa2b7a-9dc7-4ce9-8304-bd762e524fae
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815870692 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.1815870692
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.1435320940
Short name T72
Test name
Test status
Simulation time 312014656 ps
CPU time 1.12 seconds
Started May 02 02:59:14 PM PDT 24
Finished May 02 02:59:17 PM PDT 24
Peak memory 183820 kb
Host smart-3a74f488-ab32-4247-93bd-90f8cb9f5502
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435320940 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.1435320940
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.2933127363
Short name T31
Test name
Test status
Simulation time 112461844999 ps
CPU time 407.83 seconds
Started May 02 03:54:39 PM PDT 24
Finished May 02 04:01:29 PM PDT 24
Peak memory 198412 kb
Host smart-6186ab46-631c-4888-9176-16bae0e0c80e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933127363 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.2933127363
Directory /workspace/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.2879050179
Short name T107
Test name
Test status
Simulation time 8345559134 ps
CPU time 13.8 seconds
Started May 02 02:59:04 PM PDT 24
Finished May 02 02:59:19 PM PDT 24
Peak memory 198004 kb
Host smart-58e9c202-0cf8-4cf0-b79e-35a79ad67747
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879050179 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl
_intg_err.2879050179
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.2785140485
Short name T34
Test name
Test status
Simulation time 122549696061 ps
CPU time 262.31 seconds
Started May 02 03:54:46 PM PDT 24
Finished May 02 03:59:11 PM PDT 24
Peak memory 198416 kb
Host smart-c74012ff-1a82-45c0-a263-b497e066f6cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785140485 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.2785140485
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.3611830204
Short name T71
Test name
Test status
Simulation time 423200301 ps
CPU time 1.13 seconds
Started May 02 02:58:58 PM PDT 24
Finished May 02 02:59:00 PM PDT 24
Peak memory 183648 kb
Host smart-c518c06b-9140-4e22-86db-ed2608ac8c65
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611830204 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_a
liasing.3611830204
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.3651108576
Short name T345
Test name
Test status
Simulation time 425523793 ps
CPU time 1.16 seconds
Started May 02 02:58:57 PM PDT 24
Finished May 02 02:59:00 PM PDT 24
Peak memory 193168 kb
Host smart-036064e5-9f7e-46c0-95ce-8ccb8457adf2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651108576 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_a
liasing.3651108576
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.2303287073
Short name T381
Test name
Test status
Simulation time 7088360543 ps
CPU time 13.25 seconds
Started May 02 02:58:59 PM PDT 24
Finished May 02 02:59:14 PM PDT 24
Peak memory 192112 kb
Host smart-58fa10ef-c044-4969-8c76-10ec2254af68
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303287073 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_b
it_bash.2303287073
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.1828237445
Short name T368
Test name
Test status
Simulation time 1149788382 ps
CPU time 2.26 seconds
Started May 02 02:58:59 PM PDT 24
Finished May 02 02:59:03 PM PDT 24
Peak memory 193116 kb
Host smart-d3ae058d-522c-46ad-92da-1e12edf02db7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828237445 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_h
w_reset.1828237445
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.3903945069
Short name T316
Test name
Test status
Simulation time 376562005 ps
CPU time 1.1 seconds
Started May 02 02:58:59 PM PDT 24
Finished May 02 02:59:02 PM PDT 24
Peak memory 195148 kb
Host smart-809fefc5-569f-45ab-96b5-cebde98d23ff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903945069 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.3903945069
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.927244797
Short name T60
Test name
Test status
Simulation time 434962135 ps
CPU time 1.28 seconds
Started May 02 02:59:01 PM PDT 24
Finished May 02 02:59:05 PM PDT 24
Peak memory 192916 kb
Host smart-bcb7a420-ed21-4478-bdf7-3b2729895d12
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927244797 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.927244797
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.210629257
Short name T361
Test name
Test status
Simulation time 367467021 ps
CPU time 0.94 seconds
Started May 02 02:59:01 PM PDT 24
Finished May 02 02:59:05 PM PDT 24
Peak memory 183540 kb
Host smart-77af888a-b402-4fdc-a9f2-0f2db519fe32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210629257 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.210629257
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.2550530168
Short name T396
Test name
Test status
Simulation time 333449717 ps
CPU time 0.63 seconds
Started May 02 02:58:58 PM PDT 24
Finished May 02 02:59:00 PM PDT 24
Peak memory 183508 kb
Host smart-fead446d-d85a-42fb-8ddf-872fa1357e62
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550530168 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_t
imer_mem_partial_access.2550530168
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.2573697395
Short name T308
Test name
Test status
Simulation time 310688587 ps
CPU time 0.65 seconds
Started May 02 02:58:57 PM PDT 24
Finished May 02 02:58:58 PM PDT 24
Peak memory 183560 kb
Host smart-516577d5-eea4-4d8d-a558-64ac3af67df4
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573697395 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_w
alk.2573697395
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.531897821
Short name T80
Test name
Test status
Simulation time 1576409580 ps
CPU time 2.56 seconds
Started May 02 02:58:59 PM PDT 24
Finished May 02 02:59:03 PM PDT 24
Peak memory 193164 kb
Host smart-c9eac760-5b27-4ec6-9386-e0db25b79d75
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531897821 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_
timer_same_csr_outstanding.531897821
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.3556677093
Short name T327
Test name
Test status
Simulation time 555966505 ps
CPU time 1.72 seconds
Started May 02 02:58:58 PM PDT 24
Finished May 02 02:59:01 PM PDT 24
Peak memory 198464 kb
Host smart-32858b35-3233-4cf3-b3d3-6914fc337b19
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556677093 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.3556677093
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.1427860182
Short name T387
Test name
Test status
Simulation time 8155305543 ps
CPU time 13.81 seconds
Started May 02 02:58:59 PM PDT 24
Finished May 02 02:59:14 PM PDT 24
Peak memory 197796 kb
Host smart-c7a21e33-9417-4729-b2c4-d1c92256cee4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427860182 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl
_intg_err.1427860182
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.3053490495
Short name T334
Test name
Test status
Simulation time 7354219545 ps
CPU time 6.54 seconds
Started May 02 02:59:00 PM PDT 24
Finished May 02 02:59:09 PM PDT 24
Peak memory 192116 kb
Host smart-9fe50ccd-d27e-431f-ab3e-d2072d50e929
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053490495 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_b
it_bash.3053490495
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.1359555680
Short name T307
Test name
Test status
Simulation time 1270954874 ps
CPU time 2.36 seconds
Started May 02 02:58:58 PM PDT 24
Finished May 02 02:59:02 PM PDT 24
Peak memory 183724 kb
Host smart-8d086833-ab9f-4bcd-875e-3e99471ac528
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359555680 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_h
w_reset.1359555680
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.102097979
Short name T373
Test name
Test status
Simulation time 475073707 ps
CPU time 1.31 seconds
Started May 02 02:58:58 PM PDT 24
Finished May 02 02:59:00 PM PDT 24
Peak memory 195348 kb
Host smart-583f511e-1c10-4fdf-b948-8918109e930f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102097979 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.102097979
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.1319779511
Short name T54
Test name
Test status
Simulation time 529971995 ps
CPU time 0.64 seconds
Started May 02 02:58:56 PM PDT 24
Finished May 02 02:58:58 PM PDT 24
Peak memory 183644 kb
Host smart-3eea555a-4b93-4d84-99d1-2d716fe16bfb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319779511 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.1319779511
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.440816416
Short name T415
Test name
Test status
Simulation time 479696096 ps
CPU time 0.69 seconds
Started May 02 02:58:58 PM PDT 24
Finished May 02 02:59:00 PM PDT 24
Peak memory 183580 kb
Host smart-8bac17f0-7c87-4ccb-a4d8-afb676c9a10f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440816416 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.440816416
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.4087413090
Short name T338
Test name
Test status
Simulation time 463864918 ps
CPU time 0.74 seconds
Started May 02 02:58:57 PM PDT 24
Finished May 02 02:58:58 PM PDT 24
Peak memory 183464 kb
Host smart-332620a3-ee46-421c-a80c-316b36b59d7f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087413090 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_t
imer_mem_partial_access.4087413090
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.3986181389
Short name T323
Test name
Test status
Simulation time 299868414 ps
CPU time 0.76 seconds
Started May 02 02:58:59 PM PDT 24
Finished May 02 02:59:01 PM PDT 24
Peak memory 183552 kb
Host smart-221d9766-8bd1-4a8d-8599-5a6457403f87
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986181389 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_w
alk.3986181389
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.3296458076
Short name T362
Test name
Test status
Simulation time 2508902769 ps
CPU time 2.28 seconds
Started May 02 02:59:00 PM PDT 24
Finished May 02 02:59:04 PM PDT 24
Peak memory 194520 kb
Host smart-bf0bd4db-e482-4939-b211-70a33a4814ab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296458076 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon
_timer_same_csr_outstanding.3296458076
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.3412393389
Short name T398
Test name
Test status
Simulation time 521602327 ps
CPU time 1.6 seconds
Started May 02 02:58:58 PM PDT 24
Finished May 02 02:59:01 PM PDT 24
Peak memory 198468 kb
Host smart-7e1c8e7f-f6be-4330-8f58-aa9ce69eedc9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412393389 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.3412393389
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.2715183930
Short name T397
Test name
Test status
Simulation time 4670792488 ps
CPU time 1.24 seconds
Started May 02 02:59:00 PM PDT 24
Finished May 02 02:59:04 PM PDT 24
Peak memory 196216 kb
Host smart-f643a583-316f-4d13-b19b-af4328a9575c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715183930 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl
_intg_err.2715183930
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.2248781956
Short name T378
Test name
Test status
Simulation time 536261650 ps
CPU time 0.9 seconds
Started May 02 02:59:14 PM PDT 24
Finished May 02 02:59:16 PM PDT 24
Peak memory 195812 kb
Host smart-d90121e3-75fc-4874-a356-2c689e941278
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248781956 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.2248781956
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.2555104131
Short name T363
Test name
Test status
Simulation time 438002562 ps
CPU time 0.75 seconds
Started May 02 02:59:13 PM PDT 24
Finished May 02 02:59:15 PM PDT 24
Peak memory 183812 kb
Host smart-afdafc03-68d0-4db6-897e-bb5d46c77fd6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555104131 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.2555104131
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.1268930195
Short name T311
Test name
Test status
Simulation time 455354437 ps
CPU time 0.73 seconds
Started May 02 02:59:13 PM PDT 24
Finished May 02 02:59:15 PM PDT 24
Peak memory 183560 kb
Host smart-a3eb62da-03bb-45ee-bbee-38fa36c67a2b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268930195 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.1268930195
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.607602504
Short name T385
Test name
Test status
Simulation time 1891388476 ps
CPU time 3.82 seconds
Started May 02 02:59:14 PM PDT 24
Finished May 02 02:59:19 PM PDT 24
Peak memory 193192 kb
Host smart-e07f3a38-297e-40b0-99e1-69991445bbff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607602504 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon
_timer_same_csr_outstanding.607602504
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.3403843573
Short name T382
Test name
Test status
Simulation time 802997615 ps
CPU time 1.78 seconds
Started May 02 02:59:13 PM PDT 24
Finished May 02 02:59:16 PM PDT 24
Peak memory 198500 kb
Host smart-efccc5f2-743e-4cf9-b2ad-8783b6c54166
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403843573 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.3403843573
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.191162799
Short name T412
Test name
Test status
Simulation time 4593316316 ps
CPU time 2.33 seconds
Started May 02 02:59:16 PM PDT 24
Finished May 02 02:59:19 PM PDT 24
Peak memory 197620 kb
Host smart-b1342db5-032c-42ab-a5ed-92a9d889f6d8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191162799 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl
_intg_err.191162799
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.1120250181
Short name T25
Test name
Test status
Simulation time 512968668 ps
CPU time 1.37 seconds
Started May 02 02:59:15 PM PDT 24
Finished May 02 02:59:18 PM PDT 24
Peak memory 195264 kb
Host smart-df3040fc-8347-41a4-b8f2-2bd1c15836af
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120250181 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.1120250181
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.1504862960
Short name T55
Test name
Test status
Simulation time 491125508 ps
CPU time 1.29 seconds
Started May 02 02:59:12 PM PDT 24
Finished May 02 02:59:14 PM PDT 24
Peak memory 183636 kb
Host smart-07438b75-dff2-460f-9dac-9231d16bce3b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504862960 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.1504862960
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.4115420483
Short name T374
Test name
Test status
Simulation time 398678053 ps
CPU time 1.21 seconds
Started May 02 02:59:15 PM PDT 24
Finished May 02 02:59:17 PM PDT 24
Peak memory 183508 kb
Host smart-08d14c6a-d9cb-4520-98b4-75364d1354f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115420483 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.4115420483
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.1461562450
Short name T85
Test name
Test status
Simulation time 1818348356 ps
CPU time 5.05 seconds
Started May 02 02:59:13 PM PDT 24
Finished May 02 02:59:18 PM PDT 24
Peak memory 194852 kb
Host smart-c9a7a378-1fe0-44f6-b2a2-68e7c6b6f2da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461562450 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.ao
n_timer_same_csr_outstanding.1461562450
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.3816560583
Short name T366
Test name
Test status
Simulation time 437965813 ps
CPU time 2 seconds
Started May 02 02:59:15 PM PDT 24
Finished May 02 02:59:18 PM PDT 24
Peak memory 198440 kb
Host smart-e7269404-b00b-4e27-960e-1248afb52619
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816560583 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.3816560583
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.1892167461
Short name T403
Test name
Test status
Simulation time 4264016304 ps
CPU time 5.5 seconds
Started May 02 02:59:14 PM PDT 24
Finished May 02 02:59:20 PM PDT 24
Peak memory 197600 kb
Host smart-65008a91-a290-40f4-9df9-6bf8803ccbca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892167461 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_t
l_intg_err.1892167461
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.274058080
Short name T347
Test name
Test status
Simulation time 534317323 ps
CPU time 0.99 seconds
Started May 02 02:59:14 PM PDT 24
Finished May 02 02:59:16 PM PDT 24
Peak memory 194648 kb
Host smart-b0b12189-bff0-4ba7-a1a0-7f3225e9c933
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274058080 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.274058080
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.962937925
Short name T419
Test name
Test status
Simulation time 294467506 ps
CPU time 0.73 seconds
Started May 02 02:59:13 PM PDT 24
Finished May 02 02:59:15 PM PDT 24
Peak memory 183560 kb
Host smart-54005ab0-e57c-4744-9c7a-44ddb7c3b74b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962937925 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.962937925
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.940501808
Short name T314
Test name
Test status
Simulation time 2735386707 ps
CPU time 4.6 seconds
Started May 02 02:59:15 PM PDT 24
Finished May 02 02:59:21 PM PDT 24
Peak memory 183756 kb
Host smart-ab71c513-2c44-4e67-89b9-98e4517bf912
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940501808 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon
_timer_same_csr_outstanding.940501808
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.3854950779
Short name T346
Test name
Test status
Simulation time 717762968 ps
CPU time 1.85 seconds
Started May 02 02:59:15 PM PDT 24
Finished May 02 02:59:18 PM PDT 24
Peak memory 198396 kb
Host smart-2a7a64d5-97c9-454a-8d22-0145b409c6e6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854950779 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.3854950779
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.1555449469
Short name T407
Test name
Test status
Simulation time 4170741177 ps
CPU time 6.57 seconds
Started May 02 02:59:16 PM PDT 24
Finished May 02 02:59:24 PM PDT 24
Peak memory 197660 kb
Host smart-da9c4e23-3fad-4f5d-b411-a5da2302369f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555449469 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_t
l_intg_err.1555449469
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.2637724164
Short name T297
Test name
Test status
Simulation time 605777801 ps
CPU time 1.52 seconds
Started May 02 02:59:14 PM PDT 24
Finished May 02 02:59:17 PM PDT 24
Peak memory 196280 kb
Host smart-79a5e2fa-1577-4448-84c1-53dbb3e254ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637724164 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.2637724164
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.1091975500
Short name T61
Test name
Test status
Simulation time 410819717 ps
CPU time 1.1 seconds
Started May 02 02:59:16 PM PDT 24
Finished May 02 02:59:19 PM PDT 24
Peak memory 183568 kb
Host smart-a8cbaacc-3346-43a8-81e4-03a6bc1815a9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091975500 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.1091975500
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.2412151352
Short name T293
Test name
Test status
Simulation time 507557753 ps
CPU time 0.57 seconds
Started May 02 02:59:14 PM PDT 24
Finished May 02 02:59:16 PM PDT 24
Peak memory 183536 kb
Host smart-d097db98-6bb2-4189-9c84-db42d2b04d0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412151352 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.2412151352
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.2848353401
Short name T339
Test name
Test status
Simulation time 1568100032 ps
CPU time 0.83 seconds
Started May 02 02:59:14 PM PDT 24
Finished May 02 02:59:16 PM PDT 24
Peak memory 193180 kb
Host smart-2494d50a-6cce-47e7-9f46-bf09a5ecd1b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848353401 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.ao
n_timer_same_csr_outstanding.2848353401
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.2390531549
Short name T358
Test name
Test status
Simulation time 597795125 ps
CPU time 2.73 seconds
Started May 02 02:59:16 PM PDT 24
Finished May 02 02:59:20 PM PDT 24
Peak memory 198436 kb
Host smart-21d66c02-22b5-4d05-a595-0da4b313d29f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390531549 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.2390531549
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.3449393014
Short name T28
Test name
Test status
Simulation time 8235637175 ps
CPU time 7.11 seconds
Started May 02 02:59:14 PM PDT 24
Finished May 02 02:59:23 PM PDT 24
Peak memory 197968 kb
Host smart-0ee19980-adb8-4270-aeca-d4329066c99f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449393014 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_t
l_intg_err.3449393014
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.1553892057
Short name T304
Test name
Test status
Simulation time 500738350 ps
CPU time 0.92 seconds
Started May 02 02:59:16 PM PDT 24
Finished May 02 02:59:19 PM PDT 24
Peak memory 197508 kb
Host smart-ffcd6bcd-0111-4896-a9ed-0204b0de9178
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553892057 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.1553892057
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.106183054
Short name T59
Test name
Test status
Simulation time 310849491 ps
CPU time 0.79 seconds
Started May 02 02:59:18 PM PDT 24
Finished May 02 02:59:21 PM PDT 24
Peak memory 192932 kb
Host smart-a1f929d0-441f-4001-a6e8-15512e02bd0d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106183054 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.106183054
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.3645844272
Short name T391
Test name
Test status
Simulation time 438538899 ps
CPU time 0.67 seconds
Started May 02 02:59:18 PM PDT 24
Finished May 02 02:59:20 PM PDT 24
Peak memory 183564 kb
Host smart-f82e5cc8-d832-4fb1-8df9-cfb8ba1b282a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645844272 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.3645844272
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.3827700860
Short name T82
Test name
Test status
Simulation time 1940619859 ps
CPU time 2.28 seconds
Started May 02 02:59:22 PM PDT 24
Finished May 02 02:59:26 PM PDT 24
Peak memory 194236 kb
Host smart-4efbcecd-7886-4451-9442-dda3eaeb4767
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827700860 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao
n_timer_same_csr_outstanding.3827700860
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.4251985521
Short name T315
Test name
Test status
Simulation time 492791563 ps
CPU time 1.89 seconds
Started May 02 02:59:14 PM PDT 24
Finished May 02 02:59:17 PM PDT 24
Peak memory 198456 kb
Host smart-a4dd4b16-360e-4d3f-a1a3-20f9397aee13
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251985521 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.4251985521
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.3192947347
Short name T110
Test name
Test status
Simulation time 4046542116 ps
CPU time 3.49 seconds
Started May 02 02:59:14 PM PDT 24
Finished May 02 02:59:19 PM PDT 24
Peak memory 197504 kb
Host smart-3ba64a2c-e8ce-410e-99d5-d9769ef65741
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192947347 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_t
l_intg_err.3192947347
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.3139765111
Short name T317
Test name
Test status
Simulation time 571670170 ps
CPU time 1 seconds
Started May 02 02:59:23 PM PDT 24
Finished May 02 02:59:25 PM PDT 24
Peak memory 195636 kb
Host smart-4ff0bf2d-ca8d-4c93-afd0-31f7139d3387
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139765111 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.3139765111
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.703111962
Short name T353
Test name
Test status
Simulation time 482047700 ps
CPU time 0.69 seconds
Started May 02 02:59:19 PM PDT 24
Finished May 02 02:59:21 PM PDT 24
Peak memory 183664 kb
Host smart-86cb7b8e-ddae-4f7e-b425-8a6625662e00
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703111962 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.703111962
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.430696484
Short name T402
Test name
Test status
Simulation time 324218128 ps
CPU time 0.65 seconds
Started May 02 02:59:21 PM PDT 24
Finished May 02 02:59:23 PM PDT 24
Peak memory 183592 kb
Host smart-06ffbe4c-548a-47d9-a6de-d34b5b0ad3a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430696484 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.430696484
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.1009116587
Short name T400
Test name
Test status
Simulation time 1173342284 ps
CPU time 0.95 seconds
Started May 02 02:59:19 PM PDT 24
Finished May 02 02:59:21 PM PDT 24
Peak memory 192924 kb
Host smart-74dadc9b-22cd-4065-92ea-bc3780d9be0e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009116587 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.ao
n_timer_same_csr_outstanding.1009116587
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.3465159774
Short name T349
Test name
Test status
Simulation time 389311687 ps
CPU time 1.51 seconds
Started May 02 02:59:25 PM PDT 24
Finished May 02 02:59:29 PM PDT 24
Peak memory 198536 kb
Host smart-038822af-4542-4682-a676-2c8a0586e0ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465159774 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.3465159774
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.2966354880
Short name T106
Test name
Test status
Simulation time 8839460526 ps
CPU time 7.59 seconds
Started May 02 02:59:19 PM PDT 24
Finished May 02 02:59:28 PM PDT 24
Peak memory 197796 kb
Host smart-ce1edc36-8250-44d5-8906-31cb9ad1dbc3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966354880 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_t
l_intg_err.2966354880
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.537591975
Short name T393
Test name
Test status
Simulation time 497660979 ps
CPU time 1.19 seconds
Started May 02 02:59:20 PM PDT 24
Finished May 02 02:59:23 PM PDT 24
Peak memory 198320 kb
Host smart-57ff5810-a072-455e-9885-a597581f47fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537591975 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.537591975
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.2593339963
Short name T83
Test name
Test status
Simulation time 515523175 ps
CPU time 0.74 seconds
Started May 02 02:59:18 PM PDT 24
Finished May 02 02:59:20 PM PDT 24
Peak memory 183640 kb
Host smart-74a7a2aa-f8f4-40d3-bebe-76243cffde4d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593339963 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.2593339963
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.1513650028
Short name T418
Test name
Test status
Simulation time 492856863 ps
CPU time 0.86 seconds
Started May 02 02:59:19 PM PDT 24
Finished May 02 02:59:21 PM PDT 24
Peak memory 183324 kb
Host smart-2df7d653-aac4-4ed0-af7b-0cc74a1c1ef7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513650028 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.1513650028
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.3023959782
Short name T390
Test name
Test status
Simulation time 1090998239 ps
CPU time 2.09 seconds
Started May 02 02:59:18 PM PDT 24
Finished May 02 02:59:22 PM PDT 24
Peak memory 183724 kb
Host smart-f534169f-e359-4d0b-90f7-ea45b0b6b85c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023959782 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.ao
n_timer_same_csr_outstanding.3023959782
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.388736112
Short name T320
Test name
Test status
Simulation time 559665884 ps
CPU time 1.74 seconds
Started May 02 02:59:20 PM PDT 24
Finished May 02 02:59:23 PM PDT 24
Peak memory 198420 kb
Host smart-26a6dfb9-4600-47ab-9077-7748bac784b8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388736112 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.388736112
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.4102323693
Short name T109
Test name
Test status
Simulation time 8921617149 ps
CPU time 4.48 seconds
Started May 02 02:59:22 PM PDT 24
Finished May 02 02:59:29 PM PDT 24
Peak memory 197824 kb
Host smart-985ee6a1-ff99-4d15-b677-0007735832b2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102323693 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_t
l_intg_err.4102323693
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.4136362200
Short name T292
Test name
Test status
Simulation time 616411729 ps
CPU time 1.14 seconds
Started May 02 02:59:22 PM PDT 24
Finished May 02 02:59:25 PM PDT 24
Peak memory 198356 kb
Host smart-9d4631a3-be15-4ded-a3bd-c8a102bd67ce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136362200 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.4136362200
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.3035137424
Short name T26
Test name
Test status
Simulation time 392601530 ps
CPU time 1.25 seconds
Started May 02 02:59:18 PM PDT 24
Finished May 02 02:59:21 PM PDT 24
Peak memory 193008 kb
Host smart-8b03cc90-02c9-4258-afb4-48380cffa45a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035137424 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.3035137424
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.4038055369
Short name T409
Test name
Test status
Simulation time 341751053 ps
CPU time 0.65 seconds
Started May 02 02:59:18 PM PDT 24
Finished May 02 02:59:20 PM PDT 24
Peak memory 183548 kb
Host smart-e139aa69-9672-4c5f-bffd-a41334059383
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038055369 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.4038055369
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.853334183
Short name T413
Test name
Test status
Simulation time 1355575750 ps
CPU time 2.59 seconds
Started May 02 02:59:20 PM PDT 24
Finished May 02 02:59:24 PM PDT 24
Peak memory 183616 kb
Host smart-ece33df8-120e-44f8-9f07-5ff78ae2d372
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853334183 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon
_timer_same_csr_outstanding.853334183
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.3197296941
Short name T377
Test name
Test status
Simulation time 578416719 ps
CPU time 1.44 seconds
Started May 02 02:59:23 PM PDT 24
Finished May 02 02:59:26 PM PDT 24
Peak memory 198452 kb
Host smart-b2d78b1e-822f-4099-8e05-b23c553b3a13
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197296941 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.3197296941
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.112026565
Short name T401
Test name
Test status
Simulation time 4794090868 ps
CPU time 2.23 seconds
Started May 02 02:59:23 PM PDT 24
Finished May 02 02:59:28 PM PDT 24
Peak memory 196128 kb
Host smart-47cb3554-8ef6-4bb2-b428-4c3bce5d721c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112026565 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl
_intg_err.112026565
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.929221250
Short name T324
Test name
Test status
Simulation time 522873786 ps
CPU time 1.25 seconds
Started May 02 02:59:22 PM PDT 24
Finished May 02 02:59:25 PM PDT 24
Peak memory 198528 kb
Host smart-47626659-7e59-4883-a363-f726304c6f13
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929221250 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.929221250
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.645996378
Short name T303
Test name
Test status
Simulation time 424772568 ps
CPU time 1.26 seconds
Started May 02 02:59:22 PM PDT 24
Finished May 02 02:59:25 PM PDT 24
Peak memory 183636 kb
Host smart-89f49320-b154-4fc3-bade-941b765e068f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645996378 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.645996378
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.3345631329
Short name T341
Test name
Test status
Simulation time 302911769 ps
CPU time 1 seconds
Started May 02 02:59:16 PM PDT 24
Finished May 02 02:59:19 PM PDT 24
Peak memory 183560 kb
Host smart-d0780502-0847-41e5-bfec-2cbaa54af474
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345631329 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.3345631329
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.426964567
Short name T370
Test name
Test status
Simulation time 2734790274 ps
CPU time 2.63 seconds
Started May 02 02:59:20 PM PDT 24
Finished May 02 02:59:24 PM PDT 24
Peak memory 183876 kb
Host smart-4223bddb-fcab-4890-b555-e2814d518e2c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426964567 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon
_timer_same_csr_outstanding.426964567
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.277052999
Short name T352
Test name
Test status
Simulation time 527565698 ps
CPU time 2.07 seconds
Started May 02 02:59:20 PM PDT 24
Finished May 02 02:59:24 PM PDT 24
Peak memory 198480 kb
Host smart-fad631e6-16eb-45a1-b1b4-a562cf4fff07
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277052999 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.277052999
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.3373306278
Short name T388
Test name
Test status
Simulation time 7854625533 ps
CPU time 13.61 seconds
Started May 02 02:59:23 PM PDT 24
Finished May 02 02:59:39 PM PDT 24
Peak memory 197916 kb
Host smart-feb44916-7678-4d57-a171-f05dfeddd5bb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373306278 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_t
l_intg_err.3373306278
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.39096285
Short name T309
Test name
Test status
Simulation time 564625260 ps
CPU time 0.94 seconds
Started May 02 02:59:18 PM PDT 24
Finished May 02 02:59:21 PM PDT 24
Peak memory 198324 kb
Host smart-d2a65542-01a5-44e5-b5fb-e9ffa1ed792c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39096285 -assert nopostproc +UVM_TESTNAME=a
on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.39096285
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.1732780394
Short name T410
Test name
Test status
Simulation time 379445102 ps
CPU time 0.94 seconds
Started May 02 02:59:20 PM PDT 24
Finished May 02 02:59:23 PM PDT 24
Peak memory 192988 kb
Host smart-582315d9-10ef-48c0-b0b1-7ba6d029736b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732780394 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.1732780394
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.2098728595
Short name T340
Test name
Test status
Simulation time 296692300 ps
CPU time 0.91 seconds
Started May 02 02:59:20 PM PDT 24
Finished May 02 02:59:22 PM PDT 24
Peak memory 183548 kb
Host smart-ddf5e004-8b53-4149-87b8-2645af852b9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098728595 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.2098728595
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.1533667539
Short name T332
Test name
Test status
Simulation time 1231958691 ps
CPU time 0.74 seconds
Started May 02 02:59:20 PM PDT 24
Finished May 02 02:59:22 PM PDT 24
Peak memory 183784 kb
Host smart-e9228d7b-72a0-4b1b-98e3-867630858504
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533667539 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao
n_timer_same_csr_outstanding.1533667539
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.2845323823
Short name T319
Test name
Test status
Simulation time 359367727 ps
CPU time 1.59 seconds
Started May 02 02:59:23 PM PDT 24
Finished May 02 02:59:27 PM PDT 24
Peak memory 198528 kb
Host smart-85570372-c674-4b93-9b5d-9a1ab85cb152
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845323823 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.2845323823
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.3343921249
Short name T108
Test name
Test status
Simulation time 4024649984 ps
CPU time 7.37 seconds
Started May 02 02:59:20 PM PDT 24
Finished May 02 02:59:29 PM PDT 24
Peak memory 196340 kb
Host smart-7392c30f-43e4-474e-b566-70b26d9e9418
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343921249 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_t
l_intg_err.3343921249
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.669857564
Short name T365
Test name
Test status
Simulation time 400755094 ps
CPU time 1.34 seconds
Started May 02 02:58:59 PM PDT 24
Finished May 02 02:59:03 PM PDT 24
Peak memory 183664 kb
Host smart-370b9e2d-acac-4c5a-993a-51c98ec77ec0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669857564 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_al
iasing.669857564
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.1218306048
Short name T74
Test name
Test status
Simulation time 6797682224 ps
CPU time 4.97 seconds
Started May 02 02:59:02 PM PDT 24
Finished May 02 02:59:09 PM PDT 24
Peak memory 192108 kb
Host smart-9000e52f-2521-4bd9-ae29-0b0a67fdc5c6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218306048 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_b
it_bash.1218306048
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.663691182
Short name T300
Test name
Test status
Simulation time 919969195 ps
CPU time 2 seconds
Started May 02 02:59:03 PM PDT 24
Finished May 02 02:59:07 PM PDT 24
Peak memory 183592 kb
Host smart-1bbdfa66-4688-44cc-83c1-298ec4bde03f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663691182 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_hw
_reset.663691182
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.3323132576
Short name T404
Test name
Test status
Simulation time 535266043 ps
CPU time 0.92 seconds
Started May 02 02:59:03 PM PDT 24
Finished May 02 02:59:06 PM PDT 24
Peak memory 196160 kb
Host smart-02f35d8b-b4a2-4f7a-8198-0ba7f97ae646
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323132576 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.3323132576
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.1771956154
Short name T73
Test name
Test status
Simulation time 433081836 ps
CPU time 1.17 seconds
Started May 02 02:58:58 PM PDT 24
Finished May 02 02:59:00 PM PDT 24
Peak memory 183668 kb
Host smart-ef199aee-9957-460d-a4f2-ced8c10cd4af
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771956154 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.1771956154
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.2753570982
Short name T354
Test name
Test status
Simulation time 426635303 ps
CPU time 0.73 seconds
Started May 02 02:59:02 PM PDT 24
Finished May 02 02:59:05 PM PDT 24
Peak memory 183544 kb
Host smart-b5d13124-0b24-4851-8ee3-7def2f5de452
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753570982 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.2753570982
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.568966136
Short name T301
Test name
Test status
Simulation time 318202595 ps
CPU time 0.65 seconds
Started May 02 02:59:00 PM PDT 24
Finished May 02 02:59:03 PM PDT 24
Peak memory 183524 kb
Host smart-d725fd80-14d5-457d-a581-22c6e4459fdf
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568966136 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_ti
mer_mem_partial_access.568966136
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.2281754525
Short name T356
Test name
Test status
Simulation time 389556654 ps
CPU time 1.1 seconds
Started May 02 02:58:59 PM PDT 24
Finished May 02 02:59:02 PM PDT 24
Peak memory 183552 kb
Host smart-2fdfeaea-eb92-4b65-9913-9fd759d2ed78
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281754525 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_w
alk.2281754525
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.4162320008
Short name T329
Test name
Test status
Simulation time 1261673245 ps
CPU time 2.93 seconds
Started May 02 02:59:02 PM PDT 24
Finished May 02 02:59:07 PM PDT 24
Peak memory 193256 kb
Host smart-70c96879-45e1-4624-b53f-cecc11749ee0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162320008 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon
_timer_same_csr_outstanding.4162320008
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.1024030667
Short name T384
Test name
Test status
Simulation time 473405402 ps
CPU time 2.03 seconds
Started May 02 02:59:00 PM PDT 24
Finished May 02 02:59:05 PM PDT 24
Peak memory 198248 kb
Host smart-04ffed27-caee-4f1f-af6d-b9468b69ab85
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024030667 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.1024030667
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.4111793679
Short name T105
Test name
Test status
Simulation time 7909177542 ps
CPU time 4.36 seconds
Started May 02 02:58:58 PM PDT 24
Finished May 02 02:59:04 PM PDT 24
Peak memory 197916 kb
Host smart-eebd74d6-7d94-433c-abe9-b8c2cc0af7aa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111793679 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl
_intg_err.4111793679
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.714132767
Short name T305
Test name
Test status
Simulation time 479079008 ps
CPU time 0.92 seconds
Started May 02 02:59:21 PM PDT 24
Finished May 02 02:59:23 PM PDT 24
Peak memory 183544 kb
Host smart-90502ebe-2b4e-45a2-850c-03e16d0eebe2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714132767 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.714132767
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.3004895747
Short name T399
Test name
Test status
Simulation time 341939006 ps
CPU time 0.66 seconds
Started May 02 02:59:23 PM PDT 24
Finished May 02 02:59:26 PM PDT 24
Peak memory 183640 kb
Host smart-ee35b604-c5a0-471d-9b09-59406081ca3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004895747 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.3004895747
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.1371174302
Short name T331
Test name
Test status
Simulation time 488256166 ps
CPU time 0.58 seconds
Started May 02 02:59:22 PM PDT 24
Finished May 02 02:59:25 PM PDT 24
Peak memory 183540 kb
Host smart-2637079c-fde7-4ea0-ab29-4fa810dcef91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371174302 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.1371174302
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.2421294459
Short name T326
Test name
Test status
Simulation time 517133678 ps
CPU time 0.69 seconds
Started May 02 02:59:26 PM PDT 24
Finished May 02 02:59:30 PM PDT 24
Peak memory 183536 kb
Host smart-cf19a79b-bd00-4886-9815-a992a2746fca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421294459 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.2421294459
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.1125220407
Short name T291
Test name
Test status
Simulation time 357827853 ps
CPU time 1.14 seconds
Started May 02 02:59:26 PM PDT 24
Finished May 02 02:59:29 PM PDT 24
Peak memory 183588 kb
Host smart-2340d9df-47bd-4359-8433-16b08af0c059
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125220407 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.1125220407
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.2063840247
Short name T360
Test name
Test status
Simulation time 434343359 ps
CPU time 0.7 seconds
Started May 02 02:59:23 PM PDT 24
Finished May 02 02:59:26 PM PDT 24
Peak memory 183532 kb
Host smart-49d58b3e-30c7-44af-874c-115fc1d8e238
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063840247 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.2063840247
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.3335078479
Short name T411
Test name
Test status
Simulation time 303832863 ps
CPU time 0.75 seconds
Started May 02 02:59:24 PM PDT 24
Finished May 02 02:59:27 PM PDT 24
Peak memory 183548 kb
Host smart-f912c89b-ce76-45c4-a075-0034770f6ec9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335078479 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.3335078479
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.2451536513
Short name T299
Test name
Test status
Simulation time 279567716 ps
CPU time 1 seconds
Started May 02 02:59:23 PM PDT 24
Finished May 02 02:59:27 PM PDT 24
Peak memory 183560 kb
Host smart-45750427-447f-462e-ae03-2bd0c7e891c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451536513 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.2451536513
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.4114483065
Short name T392
Test name
Test status
Simulation time 329240145 ps
CPU time 0.64 seconds
Started May 02 02:59:23 PM PDT 24
Finished May 02 02:59:25 PM PDT 24
Peak memory 183540 kb
Host smart-8338b9fe-a8e2-4af7-8422-2ed496c9a7e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114483065 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.4114483065
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.1581728474
Short name T322
Test name
Test status
Simulation time 451197741 ps
CPU time 1.12 seconds
Started May 02 02:59:28 PM PDT 24
Finished May 02 02:59:31 PM PDT 24
Peak memory 183580 kb
Host smart-7dd83db1-6ed1-4bde-8925-af6889be3d78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581728474 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.1581728474
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.1671823511
Short name T76
Test name
Test status
Simulation time 491170298 ps
CPU time 1.21 seconds
Started May 02 02:58:58 PM PDT 24
Finished May 02 02:59:01 PM PDT 24
Peak memory 183660 kb
Host smart-7293e44c-2195-46ca-b135-2e56f603a3e4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671823511 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_a
liasing.1671823511
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.358034781
Short name T58
Test name
Test status
Simulation time 6305646623 ps
CPU time 17.88 seconds
Started May 02 02:58:57 PM PDT 24
Finished May 02 02:59:15 PM PDT 24
Peak memory 195764 kb
Host smart-dda98b48-78ea-475a-af89-a6fa7f0057f7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358034781 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_bi
t_bash.358034781
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.2059636067
Short name T79
Test name
Test status
Simulation time 813810445 ps
CPU time 1.74 seconds
Started May 02 02:58:58 PM PDT 24
Finished May 02 02:59:01 PM PDT 24
Peak memory 183648 kb
Host smart-65408694-9f72-4af8-a018-7408ef52347d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059636067 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_h
w_reset.2059636067
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.1430512107
Short name T421
Test name
Test status
Simulation time 574102224 ps
CPU time 1.02 seconds
Started May 02 02:59:02 PM PDT 24
Finished May 02 02:59:05 PM PDT 24
Peak memory 195192 kb
Host smart-86340703-f588-4857-84f9-baa98d3329f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430512107 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.1430512107
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.1801998384
Short name T333
Test name
Test status
Simulation time 342774520 ps
CPU time 0.99 seconds
Started May 02 02:58:59 PM PDT 24
Finished May 02 02:59:02 PM PDT 24
Peak memory 183632 kb
Host smart-292e426f-5e60-459b-a03f-7dbc1b19dc51
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801998384 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.1801998384
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.2540132578
Short name T357
Test name
Test status
Simulation time 359764308 ps
CPU time 0.71 seconds
Started May 02 02:58:58 PM PDT 24
Finished May 02 02:59:00 PM PDT 24
Peak memory 183544 kb
Host smart-6c5c7072-9e9a-4ad8-89ed-baec25119896
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540132578 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.2540132578
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.1771992987
Short name T375
Test name
Test status
Simulation time 372981558 ps
CPU time 0.69 seconds
Started May 02 02:58:59 PM PDT 24
Finished May 02 02:59:02 PM PDT 24
Peak memory 183484 kb
Host smart-a270368e-1ec1-45e7-abb0-c2d48f4bb4af
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771992987 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_t
imer_mem_partial_access.1771992987
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.3785984209
Short name T295
Test name
Test status
Simulation time 404884580 ps
CPU time 0.64 seconds
Started May 02 02:59:00 PM PDT 24
Finished May 02 02:59:03 PM PDT 24
Peak memory 183528 kb
Host smart-a4feafc1-b089-49aa-9d0b-d7ee76350ac8
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785984209 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_w
alk.3785984209
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.3839470808
Short name T81
Test name
Test status
Simulation time 1130638500 ps
CPU time 0.96 seconds
Started May 02 02:59:01 PM PDT 24
Finished May 02 02:59:04 PM PDT 24
Peak memory 183708 kb
Host smart-ca8fa869-0ca1-4ed0-8885-623ecac37f20
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839470808 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon
_timer_same_csr_outstanding.3839470808
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.2582545467
Short name T318
Test name
Test status
Simulation time 604118560 ps
CPU time 1.53 seconds
Started May 02 02:58:58 PM PDT 24
Finished May 02 02:59:00 PM PDT 24
Peak memory 198508 kb
Host smart-6c999111-27c2-4ad3-a583-af07050b8b38
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582545467 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.2582545467
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.1456117512
Short name T371
Test name
Test status
Simulation time 4308211121 ps
CPU time 7.91 seconds
Started May 02 02:58:59 PM PDT 24
Finished May 02 02:59:09 PM PDT 24
Peak memory 197456 kb
Host smart-c8c292d4-7c30-47a7-841b-c5f37990858e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456117512 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl
_intg_err.1456117512
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.1772267737
Short name T372
Test name
Test status
Simulation time 389448970 ps
CPU time 0.68 seconds
Started May 02 02:59:25 PM PDT 24
Finished May 02 02:59:28 PM PDT 24
Peak memory 183572 kb
Host smart-4342324b-832b-45b0-b979-dd13bf331700
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772267737 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.1772267737
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.3067060321
Short name T386
Test name
Test status
Simulation time 326986852 ps
CPU time 1.08 seconds
Started May 02 02:59:25 PM PDT 24
Finished May 02 02:59:28 PM PDT 24
Peak memory 183576 kb
Host smart-30168df1-d3a8-4b07-9764-87c7d0d84756
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067060321 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.3067060321
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.3550628603
Short name T335
Test name
Test status
Simulation time 279368551 ps
CPU time 0.67 seconds
Started May 02 02:59:25 PM PDT 24
Finished May 02 02:59:29 PM PDT 24
Peak memory 183564 kb
Host smart-dc234cf4-8191-4f96-b0a0-a09e305867c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550628603 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.3550628603
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.244747478
Short name T414
Test name
Test status
Simulation time 341035891 ps
CPU time 1.05 seconds
Started May 02 02:59:24 PM PDT 24
Finished May 02 02:59:27 PM PDT 24
Peak memory 183572 kb
Host smart-3739036f-443e-4941-aa60-5afd44cb4860
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244747478 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.244747478
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.3891735606
Short name T343
Test name
Test status
Simulation time 496063436 ps
CPU time 1.23 seconds
Started May 02 02:59:28 PM PDT 24
Finished May 02 02:59:31 PM PDT 24
Peak memory 183428 kb
Host smart-8762e6f1-e608-45e6-ae86-e538deb99afa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891735606 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.3891735606
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.2167401791
Short name T294
Test name
Test status
Simulation time 483586792 ps
CPU time 1.31 seconds
Started May 02 02:59:26 PM PDT 24
Finished May 02 02:59:30 PM PDT 24
Peak memory 183508 kb
Host smart-4ec2305b-de72-47de-846c-2eac779748c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167401791 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.2167401791
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.534808002
Short name T288
Test name
Test status
Simulation time 381907321 ps
CPU time 1.16 seconds
Started May 02 02:59:27 PM PDT 24
Finished May 02 02:59:31 PM PDT 24
Peak memory 183540 kb
Host smart-9a51aa5e-d28e-4855-80c2-4e6c3db6c3f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534808002 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.534808002
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.3503833325
Short name T344
Test name
Test status
Simulation time 496246011 ps
CPU time 0.75 seconds
Started May 02 02:59:26 PM PDT 24
Finished May 02 02:59:30 PM PDT 24
Peak memory 183544 kb
Host smart-a72658cd-d42a-4ddb-b8bb-7094e12d8751
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503833325 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.3503833325
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.88929022
Short name T422
Test name
Test status
Simulation time 329539358 ps
CPU time 0.69 seconds
Started May 02 02:59:26 PM PDT 24
Finished May 02 02:59:29 PM PDT 24
Peak memory 183560 kb
Host smart-1e441fd4-874e-40fa-94d2-1e31c6dac615
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88929022 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.88929022
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.4030194039
Short name T359
Test name
Test status
Simulation time 427565873 ps
CPU time 0.69 seconds
Started May 02 02:59:25 PM PDT 24
Finished May 02 02:59:28 PM PDT 24
Peak memory 183576 kb
Host smart-4541e3e3-b2d2-407e-bba9-8d93dfe2b883
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030194039 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.4030194039
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.3268962993
Short name T56
Test name
Test status
Simulation time 501411965 ps
CPU time 0.83 seconds
Started May 02 02:59:10 PM PDT 24
Finished May 02 02:59:12 PM PDT 24
Peak memory 183684 kb
Host smart-b38c20cd-ad97-46b3-bd95-36c74569f6f2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268962993 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_a
liasing.3268962993
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.2557889721
Short name T57
Test name
Test status
Simulation time 11671842591 ps
CPU time 5 seconds
Started May 02 02:59:00 PM PDT 24
Finished May 02 02:59:07 PM PDT 24
Peak memory 192136 kb
Host smart-a7ca41c0-bcfa-45fa-8a6c-1256b089c502
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557889721 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_b
it_bash.2557889721
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.3327325408
Short name T350
Test name
Test status
Simulation time 720078354 ps
CPU time 0.97 seconds
Started May 02 02:59:01 PM PDT 24
Finished May 02 02:59:04 PM PDT 24
Peak memory 183720 kb
Host smart-488c79c8-1b13-4b58-8de2-164d0c71b9e9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327325408 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_h
w_reset.3327325408
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.356426548
Short name T417
Test name
Test status
Simulation time 529687313 ps
CPU time 0.79 seconds
Started May 02 02:59:03 PM PDT 24
Finished May 02 02:59:06 PM PDT 24
Peak memory 195420 kb
Host smart-0ed6d218-b2c6-43d2-a64f-493b5cdcce23
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356426548 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.356426548
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.533539075
Short name T351
Test name
Test status
Simulation time 313169664 ps
CPU time 0.77 seconds
Started May 02 02:59:06 PM PDT 24
Finished May 02 02:59:08 PM PDT 24
Peak memory 183668 kb
Host smart-e9f3ba86-b960-467a-9d9d-a59633e10104
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533539075 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.533539075
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.1370548988
Short name T289
Test name
Test status
Simulation time 335153498 ps
CPU time 1.04 seconds
Started May 02 02:58:59 PM PDT 24
Finished May 02 02:59:01 PM PDT 24
Peak memory 183544 kb
Host smart-0b419d9d-ed9f-4a04-a31b-21c63e58b184
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370548988 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.1370548988
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.3966341028
Short name T290
Test name
Test status
Simulation time 303893675 ps
CPU time 0.91 seconds
Started May 02 02:59:00 PM PDT 24
Finished May 02 02:59:03 PM PDT 24
Peak memory 183520 kb
Host smart-e3ff44e4-c13f-4eba-929a-5e635dd1d1d5
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966341028 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_t
imer_mem_partial_access.3966341028
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.1406626187
Short name T424
Test name
Test status
Simulation time 511295178 ps
CPU time 0.6 seconds
Started May 02 02:59:02 PM PDT 24
Finished May 02 02:59:05 PM PDT 24
Peak memory 183520 kb
Host smart-8c889f68-f895-4ea1-9886-d499f82df0d1
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406626187 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_w
alk.1406626187
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.3069345154
Short name T348
Test name
Test status
Simulation time 1163985449 ps
CPU time 3.31 seconds
Started May 02 02:59:00 PM PDT 24
Finished May 02 02:59:06 PM PDT 24
Peak memory 193132 kb
Host smart-4d6722a3-79d1-4bf3-83d0-8c390aac317d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069345154 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon
_timer_same_csr_outstanding.3069345154
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.746091864
Short name T312
Test name
Test status
Simulation time 370682570 ps
CPU time 1.73 seconds
Started May 02 02:59:00 PM PDT 24
Finished May 02 02:59:04 PM PDT 24
Peak memory 198484 kb
Host smart-511032bd-c1a9-4e46-bdcc-df87f8723854
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746091864 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.746091864
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.3094076107
Short name T104
Test name
Test status
Simulation time 8309409851 ps
CPU time 14.03 seconds
Started May 02 02:58:56 PM PDT 24
Finished May 02 02:59:11 PM PDT 24
Peak memory 197916 kb
Host smart-743c6813-acdb-4de9-a877-f797704b68ae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094076107 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl
_intg_err.3094076107
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.3167536454
Short name T306
Test name
Test status
Simulation time 557974167 ps
CPU time 0.61 seconds
Started May 02 02:59:27 PM PDT 24
Finished May 02 02:59:30 PM PDT 24
Peak memory 183540 kb
Host smart-c3bde858-ce21-4739-b99e-44bcb12fe69b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167536454 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.3167536454
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.2177100898
Short name T330
Test name
Test status
Simulation time 534572721 ps
CPU time 0.77 seconds
Started May 02 02:59:25 PM PDT 24
Finished May 02 02:59:28 PM PDT 24
Peak memory 183556 kb
Host smart-b9d45403-e81a-466a-b95d-8afad4f5151f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177100898 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.2177100898
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.2558737970
Short name T355
Test name
Test status
Simulation time 426719656 ps
CPU time 1.25 seconds
Started May 02 02:59:24 PM PDT 24
Finished May 02 02:59:27 PM PDT 24
Peak memory 183548 kb
Host smart-b4a2bc4d-4505-43f8-bdc4-2a1afb4e07d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558737970 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.2558737970
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.2292532791
Short name T310
Test name
Test status
Simulation time 405417887 ps
CPU time 0.97 seconds
Started May 02 02:59:26 PM PDT 24
Finished May 02 02:59:29 PM PDT 24
Peak memory 183556 kb
Host smart-53715be4-ad2d-48bf-963f-42e4a97a9760
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292532791 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.2292532791
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.2051084253
Short name T405
Test name
Test status
Simulation time 307219401 ps
CPU time 0.65 seconds
Started May 02 02:59:26 PM PDT 24
Finished May 02 02:59:29 PM PDT 24
Peak memory 183500 kb
Host smart-116da1a3-60e9-4912-a381-192b3520c88e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051084253 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.2051084253
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.2247817194
Short name T337
Test name
Test status
Simulation time 469792645 ps
CPU time 0.64 seconds
Started May 02 02:59:24 PM PDT 24
Finished May 02 02:59:27 PM PDT 24
Peak memory 183548 kb
Host smart-4d74ecc2-6fc3-4546-b85d-99592cf29c75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247817194 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.2247817194
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.1118313212
Short name T379
Test name
Test status
Simulation time 418660231 ps
CPU time 0.59 seconds
Started May 02 02:59:30 PM PDT 24
Finished May 02 02:59:33 PM PDT 24
Peak memory 183532 kb
Host smart-fffd7035-acc6-4188-9079-3d1cb969e840
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118313212 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.1118313212
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.4118447535
Short name T336
Test name
Test status
Simulation time 357292643 ps
CPU time 0.66 seconds
Started May 02 02:59:28 PM PDT 24
Finished May 02 02:59:31 PM PDT 24
Peak memory 183448 kb
Host smart-dede52ad-47f0-4d61-8cae-71c80fd6a62c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118447535 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.4118447535
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.873353101
Short name T369
Test name
Test status
Simulation time 451893932 ps
CPU time 1.26 seconds
Started May 02 02:59:24 PM PDT 24
Finished May 02 02:59:28 PM PDT 24
Peak memory 183548 kb
Host smart-df41f8f4-7351-441a-871a-592527fa12ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873353101 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.873353101
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.530926123
Short name T376
Test name
Test status
Simulation time 404359104 ps
CPU time 1.21 seconds
Started May 02 02:59:26 PM PDT 24
Finished May 02 02:59:30 PM PDT 24
Peak memory 183512 kb
Host smart-755ea5cf-919c-429f-964f-d66fd01c3f6f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530926123 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.530926123
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.921742811
Short name T423
Test name
Test status
Simulation time 495109567 ps
CPU time 0.89 seconds
Started May 02 02:59:04 PM PDT 24
Finished May 02 02:59:07 PM PDT 24
Peak memory 195148 kb
Host smart-6bf845c9-e8d4-469e-9512-9ef39b73a064
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921742811 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.921742811
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.2346806637
Short name T78
Test name
Test status
Simulation time 386407437 ps
CPU time 0.88 seconds
Started May 02 02:59:05 PM PDT 24
Finished May 02 02:59:07 PM PDT 24
Peak memory 192912 kb
Host smart-a84ee63d-5eb7-4a19-872d-ce1a7548c896
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346806637 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.2346806637
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.2815480738
Short name T380
Test name
Test status
Simulation time 535678340 ps
CPU time 0.71 seconds
Started May 02 02:59:06 PM PDT 24
Finished May 02 02:59:08 PM PDT 24
Peak memory 183588 kb
Host smart-a6f8e08b-4d4a-4b41-92be-c19fe567e10d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815480738 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.2815480738
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.2561177212
Short name T84
Test name
Test status
Simulation time 1262455507 ps
CPU time 1.09 seconds
Started May 02 02:59:08 PM PDT 24
Finished May 02 02:59:10 PM PDT 24
Peak memory 183756 kb
Host smart-6c3525eb-8fb7-436c-9e91-7d80c54b4558
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561177212 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon
_timer_same_csr_outstanding.2561177212
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.2147765480
Short name T328
Test name
Test status
Simulation time 503935767 ps
CPU time 1.98 seconds
Started May 02 02:59:03 PM PDT 24
Finished May 02 02:59:07 PM PDT 24
Peak memory 198516 kb
Host smart-6375eea6-5d37-4a4b-8973-0f82bf4710a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147765480 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.2147765480
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.3078545799
Short name T420
Test name
Test status
Simulation time 7643937868 ps
CPU time 13.33 seconds
Started May 02 02:59:03 PM PDT 24
Finished May 02 02:59:18 PM PDT 24
Peak memory 197884 kb
Host smart-7970c6b0-8693-4ece-8662-36bc9b87615a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078545799 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl
_intg_err.3078545799
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.713229873
Short name T395
Test name
Test status
Simulation time 896865340 ps
CPU time 0.93 seconds
Started May 02 02:59:07 PM PDT 24
Finished May 02 02:59:10 PM PDT 24
Peak memory 198252 kb
Host smart-3f57645b-84b8-477d-afd9-3fc56accbd6c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713229873 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.713229873
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.324563660
Short name T77
Test name
Test status
Simulation time 426314634 ps
CPU time 1.2 seconds
Started May 02 02:59:04 PM PDT 24
Finished May 02 02:59:07 PM PDT 24
Peak memory 183652 kb
Host smart-dc71a395-f1db-4ede-9c21-e4778ee3fd5a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324563660 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.324563660
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.2005582527
Short name T389
Test name
Test status
Simulation time 410421985 ps
CPU time 0.73 seconds
Started May 02 02:59:08 PM PDT 24
Finished May 02 02:59:10 PM PDT 24
Peak memory 183556 kb
Host smart-ad04c4b0-c853-4ee4-85a0-5d8a4ec26026
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005582527 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.2005582527
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.4018894447
Short name T367
Test name
Test status
Simulation time 1064723716 ps
CPU time 0.87 seconds
Started May 02 02:59:04 PM PDT 24
Finished May 02 02:59:07 PM PDT 24
Peak memory 193316 kb
Host smart-13d8710e-efe9-42ee-a4fb-642711b42385
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018894447 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon
_timer_same_csr_outstanding.4018894447
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.753077396
Short name T383
Test name
Test status
Simulation time 409951204 ps
CPU time 2.75 seconds
Started May 02 02:59:02 PM PDT 24
Finished May 02 02:59:07 PM PDT 24
Peak memory 198416 kb
Host smart-e22d4350-7939-47ef-b462-62a2e236aa3f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753077396 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.753077396
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.1647627284
Short name T321
Test name
Test status
Simulation time 403612722 ps
CPU time 0.96 seconds
Started May 02 02:59:07 PM PDT 24
Finished May 02 02:59:10 PM PDT 24
Peak memory 195812 kb
Host smart-d8d42949-fe3e-49b9-9890-0727c6554f61
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647627284 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.1647627284
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.1047157202
Short name T325
Test name
Test status
Simulation time 539982493 ps
CPU time 1.3 seconds
Started May 02 02:59:04 PM PDT 24
Finished May 02 02:59:07 PM PDT 24
Peak memory 183824 kb
Host smart-ed129f69-37e0-424f-97e5-cdcad3c14c90
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047157202 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.1047157202
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.2961352697
Short name T302
Test name
Test status
Simulation time 395033155 ps
CPU time 0.81 seconds
Started May 02 02:59:04 PM PDT 24
Finished May 02 02:59:07 PM PDT 24
Peak memory 183548 kb
Host smart-c935ea03-17a7-4e91-b35c-2350f6c9ae3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961352697 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.2961352697
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.3778370191
Short name T87
Test name
Test status
Simulation time 2370052357 ps
CPU time 1.08 seconds
Started May 02 02:59:02 PM PDT 24
Finished May 02 02:59:05 PM PDT 24
Peak memory 194656 kb
Host smart-49492a8f-b963-4e25-b109-635216253de0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778370191 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon
_timer_same_csr_outstanding.3778370191
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.91757701
Short name T342
Test name
Test status
Simulation time 493669394 ps
CPU time 2.63 seconds
Started May 02 02:59:08 PM PDT 24
Finished May 02 02:59:12 PM PDT 24
Peak memory 198468 kb
Host smart-65a5eece-2ea9-48f1-b172-33919230bcd8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91757701 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.91757701
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.1610314784
Short name T27
Test name
Test status
Simulation time 4258951638 ps
CPU time 1.86 seconds
Started May 02 02:59:01 PM PDT 24
Finished May 02 02:59:05 PM PDT 24
Peak memory 197304 kb
Host smart-b2caeac1-4136-456f-8a5b-f9065ae07941
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610314784 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl
_intg_err.1610314784
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.3897858792
Short name T408
Test name
Test status
Simulation time 591347608 ps
CPU time 1.11 seconds
Started May 02 02:59:07 PM PDT 24
Finished May 02 02:59:10 PM PDT 24
Peak memory 196100 kb
Host smart-617b519e-5ca9-4096-bf37-269670073168
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897858792 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.3897858792
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.1014483842
Short name T75
Test name
Test status
Simulation time 526094664 ps
CPU time 1.01 seconds
Started May 02 02:59:04 PM PDT 24
Finished May 02 02:59:07 PM PDT 24
Peak memory 193024 kb
Host smart-b3e449e7-4f3b-414c-bbca-d96e3073328e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014483842 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.1014483842
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.2485743897
Short name T298
Test name
Test status
Simulation time 290586362 ps
CPU time 0.62 seconds
Started May 02 02:59:01 PM PDT 24
Finished May 02 02:59:04 PM PDT 24
Peak memory 183496 kb
Host smart-c1b914dc-1c71-4c79-a2dc-4adf63f95286
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485743897 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.2485743897
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.3477758671
Short name T86
Test name
Test status
Simulation time 2202918927 ps
CPU time 1.55 seconds
Started May 02 02:59:05 PM PDT 24
Finished May 02 02:59:08 PM PDT 24
Peak memory 194368 kb
Host smart-fcbb7334-8056-4e45-8d7e-d1194851eec2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477758671 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon
_timer_same_csr_outstanding.3477758671
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.2203220954
Short name T287
Test name
Test status
Simulation time 514569077 ps
CPU time 1.54 seconds
Started May 02 02:59:02 PM PDT 24
Finished May 02 02:59:06 PM PDT 24
Peak memory 198356 kb
Host smart-8356772a-563c-41f6-864c-d666d3e337cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203220954 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.2203220954
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.2153944348
Short name T416
Test name
Test status
Simulation time 530428525 ps
CPU time 1.38 seconds
Started May 02 02:59:14 PM PDT 24
Finished May 02 02:59:17 PM PDT 24
Peak memory 195844 kb
Host smart-01134f84-4602-4373-a86f-bb71623e7c78
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153944348 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.2153944348
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.2359704910
Short name T313
Test name
Test status
Simulation time 528081279 ps
CPU time 0.91 seconds
Started May 02 02:59:06 PM PDT 24
Finished May 02 02:59:08 PM PDT 24
Peak memory 183672 kb
Host smart-fda2f3e5-8d73-497b-ad55-c2b967102f14
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359704910 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.2359704910
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.1867525636
Short name T364
Test name
Test status
Simulation time 307259942 ps
CPU time 0.99 seconds
Started May 02 02:58:59 PM PDT 24
Finished May 02 02:59:02 PM PDT 24
Peak memory 183552 kb
Host smart-d9777b39-c4e2-43f1-887f-f6e75ba92421
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867525636 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.1867525636
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.61649444
Short name T394
Test name
Test status
Simulation time 1515331041 ps
CPU time 0.98 seconds
Started May 02 02:59:10 PM PDT 24
Finished May 02 02:59:12 PM PDT 24
Peak memory 191888 kb
Host smart-cc722682-9fbc-43fb-a746-050d4dc8acbf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61649444 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_t
imer_same_csr_outstanding.61649444
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.409546529
Short name T296
Test name
Test status
Simulation time 473885615 ps
CPU time 2.2 seconds
Started May 02 02:59:03 PM PDT 24
Finished May 02 02:59:07 PM PDT 24
Peak memory 198504 kb
Host smart-b3aafbbf-d607-40d3-9857-b5fe6ef63a5a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409546529 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.409546529
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.2253475382
Short name T406
Test name
Test status
Simulation time 8960528624 ps
CPU time 13.26 seconds
Started May 02 02:59:04 PM PDT 24
Finished May 02 02:59:19 PM PDT 24
Peak memory 197668 kb
Host smart-3d8be08b-2332-4dd7-a018-c7b5c580662c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253475382 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl
_intg_err.2253475382
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_jump.975957234
Short name T230
Test name
Test status
Simulation time 550446566 ps
CPU time 1.39 seconds
Started May 02 03:54:33 PM PDT 24
Finished May 02 03:54:35 PM PDT 24
Peak memory 183588 kb
Host smart-c791964a-c4f3-48ac-8154-eb7fc2606f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975957234 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.975957234
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.4038794493
Short name T178
Test name
Test status
Simulation time 45777179725 ps
CPU time 6.82 seconds
Started May 02 03:54:06 PM PDT 24
Finished May 02 03:54:16 PM PDT 24
Peak memory 183612 kb
Host smart-2b839afe-bae5-418e-b028-52a0625034ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038794493 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.4038794493
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.3328357963
Short name T19
Test name
Test status
Simulation time 4108858564 ps
CPU time 6.97 seconds
Started May 02 03:54:04 PM PDT 24
Finished May 02 03:54:15 PM PDT 24
Peak memory 214840 kb
Host smart-ef9efad5-ac8e-46d8-bf19-0e2ea1ded637
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328357963 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.3328357963
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.1174099070
Short name T130
Test name
Test status
Simulation time 430392276 ps
CPU time 1.24 seconds
Started May 02 03:54:06 PM PDT 24
Finished May 02 03:54:11 PM PDT 24
Peak memory 183556 kb
Host smart-ef87e4a2-0cae-4042-ad8a-5c2c66a73632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174099070 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.1174099070
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.988582862
Short name T250
Test name
Test status
Simulation time 135607520203 ps
CPU time 48.63 seconds
Started May 02 03:54:07 PM PDT 24
Finished May 02 03:54:59 PM PDT 24
Peak memory 193928 kb
Host smart-f6864fbf-c387-465d-aec2-aef66187019c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988582862 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_al
l.988582862
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.1888598652
Short name T14
Test name
Test status
Simulation time 432598410555 ps
CPU time 603.37 seconds
Started May 02 03:54:22 PM PDT 24
Finished May 02 04:04:26 PM PDT 24
Peak memory 199260 kb
Host smart-b1ee8837-56f6-42c6-b431-35d0c3ab8e78
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888598652 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.1888598652
Directory /workspace/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.aon_timer_jump.1664744206
Short name T228
Test name
Test status
Simulation time 407547418 ps
CPU time 0.91 seconds
Started May 02 03:54:08 PM PDT 24
Finished May 02 03:54:12 PM PDT 24
Peak memory 183552 kb
Host smart-544b4717-2a0d-4cca-8fda-34e43b5aa9b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664744206 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.1664744206
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.512681220
Short name T253
Test name
Test status
Simulation time 23859651704 ps
CPU time 33.75 seconds
Started May 02 03:54:04 PM PDT 24
Finished May 02 03:54:42 PM PDT 24
Peak memory 183608 kb
Host smart-4ce257f8-8661-4bc4-bfc5-2ae484d809cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512681220 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.512681220
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.3007955596
Short name T255
Test name
Test status
Simulation time 385748284 ps
CPU time 0.82 seconds
Started May 02 03:54:25 PM PDT 24
Finished May 02 03:54:27 PM PDT 24
Peak memory 183560 kb
Host smart-cc5047d7-d843-42c0-8712-904b65430db9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007955596 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.3007955596
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.198316835
Short name T97
Test name
Test status
Simulation time 48970707331 ps
CPU time 130.75 seconds
Started May 02 03:54:30 PM PDT 24
Finished May 02 03:56:41 PM PDT 24
Peak memory 198556 kb
Host smart-86940add-6888-467e-95b4-a653b5d41a17
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198316835 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.198316835
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.aon_timer_jump.3865286176
Short name T128
Test name
Test status
Simulation time 526502017 ps
CPU time 1.32 seconds
Started May 02 03:54:12 PM PDT 24
Finished May 02 03:54:15 PM PDT 24
Peak memory 183536 kb
Host smart-586382ef-1ecc-4eb6-ade1-fb6033b285ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865286176 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.3865286176
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.3536294130
Short name T4
Test name
Test status
Simulation time 15904379106 ps
CPU time 2.54 seconds
Started May 02 03:54:14 PM PDT 24
Finished May 02 03:54:17 PM PDT 24
Peak memory 191808 kb
Host smart-28fc58df-0e87-418d-842e-9efcf52b49b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536294130 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.3536294130
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.1916367852
Short name T211
Test name
Test status
Simulation time 551350539 ps
CPU time 1.31 seconds
Started May 02 03:54:38 PM PDT 24
Finished May 02 03:54:40 PM PDT 24
Peak memory 183580 kb
Host smart-fc789b8f-3336-47bb-b150-0f7f9a354ddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916367852 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.1916367852
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.3541053918
Short name T208
Test name
Test status
Simulation time 178139189396 ps
CPU time 68.15 seconds
Started May 02 03:54:21 PM PDT 24
Finished May 02 03:55:30 PM PDT 24
Peak memory 194968 kb
Host smart-5c561bd9-5f65-451c-a5c3-73e22d868616
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541053918 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_
all.3541053918
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_jump.2232445558
Short name T169
Test name
Test status
Simulation time 406141641 ps
CPU time 0.9 seconds
Started May 02 03:54:33 PM PDT 24
Finished May 02 03:54:35 PM PDT 24
Peak memory 183524 kb
Host smart-8b913649-3cca-45c3-8146-bb737da0b7e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232445558 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.2232445558
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.461827101
Short name T213
Test name
Test status
Simulation time 35083369179 ps
CPU time 23.62 seconds
Started May 02 03:54:29 PM PDT 24
Finished May 02 03:54:54 PM PDT 24
Peak memory 183584 kb
Host smart-c20d93e6-3701-485a-b957-ad905ac8c1aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461827101 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.461827101
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.1884942591
Short name T114
Test name
Test status
Simulation time 479841850 ps
CPU time 0.67 seconds
Started May 02 03:54:16 PM PDT 24
Finished May 02 03:54:17 PM PDT 24
Peak memory 183544 kb
Host smart-2bf043bb-7372-40aa-b3f5-c44c5d9bcd9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884942591 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.1884942591
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.2635449234
Short name T283
Test name
Test status
Simulation time 334602922677 ps
CPU time 494.81 seconds
Started May 02 03:54:19 PM PDT 24
Finished May 02 04:02:34 PM PDT 24
Peak memory 195516 kb
Host smart-7d7b57cf-0efd-40ce-989c-76aac2092057
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635449234 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_
all.2635449234
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_jump.621306889
Short name T20
Test name
Test status
Simulation time 519632308 ps
CPU time 0.74 seconds
Started May 02 03:54:33 PM PDT 24
Finished May 02 03:54:35 PM PDT 24
Peak memory 183540 kb
Host smart-1cf003ee-420d-4531-be28-c646e94a1943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621306889 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.621306889
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.2236130780
Short name T125
Test name
Test status
Simulation time 49552540591 ps
CPU time 39.21 seconds
Started May 02 03:54:39 PM PDT 24
Finished May 02 03:55:20 PM PDT 24
Peak memory 183592 kb
Host smart-9651bcf2-c211-4d59-9cc4-cd75acdc3990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236130780 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.2236130780
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.3613020035
Short name T260
Test name
Test status
Simulation time 466457802 ps
CPU time 0.67 seconds
Started May 02 03:54:39 PM PDT 24
Finished May 02 03:54:41 PM PDT 24
Peak memory 183584 kb
Host smart-8a18ada6-9ba7-43a2-92c8-e2a13d518d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613020035 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.3613020035
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.2134470798
Short name T22
Test name
Test status
Simulation time 104488935770 ps
CPU time 137.7 seconds
Started May 02 03:54:34 PM PDT 24
Finished May 02 03:56:53 PM PDT 24
Peak memory 183560 kb
Host smart-c876376d-d3fd-41ba-8168-ba8deb91c619
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134470798 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_
all.2134470798
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.2096095806
Short name T95
Test name
Test status
Simulation time 156144166975 ps
CPU time 161.37 seconds
Started May 02 03:54:39 PM PDT 24
Finished May 02 03:57:21 PM PDT 24
Peak memory 198548 kb
Host smart-a2849ed0-c786-414a-a3fe-240ebb32a0db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096095806 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.2096095806
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_jump.275422683
Short name T224
Test name
Test status
Simulation time 493388050 ps
CPU time 0.77 seconds
Started May 02 03:54:31 PM PDT 24
Finished May 02 03:54:33 PM PDT 24
Peak memory 183540 kb
Host smart-dac60ade-8f22-4d00-9e76-bcec59b80b01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275422683 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.275422683
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.2294428297
Short name T68
Test name
Test status
Simulation time 3998858572 ps
CPU time 7.14 seconds
Started May 02 03:54:45 PM PDT 24
Finished May 02 03:54:54 PM PDT 24
Peak memory 183592 kb
Host smart-ae7395b9-1d30-4d32-b7f8-dbf3b73aeaa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294428297 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.2294428297
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.1778917912
Short name T171
Test name
Test status
Simulation time 432431913 ps
CPU time 0.7 seconds
Started May 02 03:54:32 PM PDT 24
Finished May 02 03:54:34 PM PDT 24
Peak memory 183500 kb
Host smart-845865d7-87f3-4c33-ad09-4963d88ab102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778917912 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.1778917912
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.3869317285
Short name T198
Test name
Test status
Simulation time 438686916119 ps
CPU time 148.2 seconds
Started May 02 03:54:25 PM PDT 24
Finished May 02 03:56:54 PM PDT 24
Peak memory 194344 kb
Host smart-fd70ad02-475e-43af-bf8f-f9206779bff5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869317285 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_
all.3869317285
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.2011308556
Short name T175
Test name
Test status
Simulation time 52516789842 ps
CPU time 520.92 seconds
Started May 02 03:54:41 PM PDT 24
Finished May 02 04:03:23 PM PDT 24
Peak memory 198488 kb
Host smart-0c260dce-27d8-4936-9f85-6d7cb5cab032
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011308556 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.2011308556
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.aon_timer_jump.3120690377
Short name T112
Test name
Test status
Simulation time 515725027 ps
CPU time 1.25 seconds
Started May 02 03:54:36 PM PDT 24
Finished May 02 03:54:38 PM PDT 24
Peak memory 183516 kb
Host smart-fdfc668d-fe55-4036-b374-ab17603386e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120690377 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.3120690377
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.1978182399
Short name T210
Test name
Test status
Simulation time 55980794114 ps
CPU time 88.37 seconds
Started May 02 03:54:38 PM PDT 24
Finished May 02 03:56:07 PM PDT 24
Peak memory 183600 kb
Host smart-ada4890f-4c35-4c2e-ae19-058e9f985d74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978182399 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.1978182399
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.912252488
Short name T256
Test name
Test status
Simulation time 455081225 ps
CPU time 1.23 seconds
Started May 02 03:54:33 PM PDT 24
Finished May 02 03:54:36 PM PDT 24
Peak memory 183536 kb
Host smart-45ea6cd6-3438-472a-95ca-bb9f4e4b4e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912252488 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.912252488
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.813298691
Short name T139
Test name
Test status
Simulation time 101049497088 ps
CPU time 16.42 seconds
Started May 02 03:54:25 PM PDT 24
Finished May 02 03:54:42 PM PDT 24
Peak memory 183576 kb
Host smart-2ee4de35-494a-46a2-a0ae-f0f12d1f819a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813298691 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_a
ll.813298691
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.1380176755
Short name T180
Test name
Test status
Simulation time 201274637095 ps
CPU time 390.62 seconds
Started May 02 03:54:37 PM PDT 24
Finished May 02 04:01:08 PM PDT 24
Peak memory 198472 kb
Host smart-0e175d17-625d-4e02-a285-630020bbc18e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380176755 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.1380176755
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.aon_timer_jump.699161382
Short name T141
Test name
Test status
Simulation time 414839367 ps
CPU time 1.18 seconds
Started May 02 03:54:40 PM PDT 24
Finished May 02 03:54:42 PM PDT 24
Peak memory 183564 kb
Host smart-b101b757-be28-4573-a412-cffebdcf2b73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699161382 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.699161382
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.584745491
Short name T9
Test name
Test status
Simulation time 24865753173 ps
CPU time 8.81 seconds
Started May 02 03:54:33 PM PDT 24
Finished May 02 03:54:42 PM PDT 24
Peak memory 183624 kb
Host smart-946a8bb9-9482-42c0-b5d9-9f17bbadfdcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584745491 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.584745491
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.1464706197
Short name T44
Test name
Test status
Simulation time 589823438 ps
CPU time 0.73 seconds
Started May 02 03:54:24 PM PDT 24
Finished May 02 03:54:26 PM PDT 24
Peak memory 183608 kb
Host smart-b8ea5fa2-84a4-4f61-af39-36cdab8f3938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464706197 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.1464706197
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.615740663
Short name T278
Test name
Test status
Simulation time 231666890318 ps
CPU time 197.9 seconds
Started May 02 03:54:23 PM PDT 24
Finished May 02 03:57:42 PM PDT 24
Peak memory 195336 kb
Host smart-38cb1b98-9152-4ac1-a231-d399af6d16e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615740663 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_a
ll.615740663
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.477681834
Short name T32
Test name
Test status
Simulation time 86675924380 ps
CPU time 166.75 seconds
Started May 02 03:54:41 PM PDT 24
Finished May 02 03:57:30 PM PDT 24
Peak memory 198552 kb
Host smart-f4c02319-19f8-423f-8c46-0069ad60e400
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477681834 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.477681834
Directory /workspace/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.aon_timer_jump.1606303008
Short name T197
Test name
Test status
Simulation time 416589795 ps
CPU time 0.91 seconds
Started May 02 03:54:36 PM PDT 24
Finished May 02 03:54:38 PM PDT 24
Peak memory 183548 kb
Host smart-9597f072-37a8-4e45-a102-03397100b407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606303008 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.1606303008
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.1994509397
Short name T65
Test name
Test status
Simulation time 17447432989 ps
CPU time 6.88 seconds
Started May 02 03:54:34 PM PDT 24
Finished May 02 03:54:42 PM PDT 24
Peak memory 183636 kb
Host smart-80ea12a6-b6e5-4170-b581-0c8690cf08e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994509397 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.1994509397
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.1581200756
Short name T272
Test name
Test status
Simulation time 555499758 ps
CPU time 0.65 seconds
Started May 02 03:54:32 PM PDT 24
Finished May 02 03:54:33 PM PDT 24
Peak memory 183524 kb
Host smart-a3605c06-dea6-4545-995d-2c31e856636f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581200756 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.1581200756
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.3809706977
Short name T203
Test name
Test status
Simulation time 23699663787 ps
CPU time 4 seconds
Started May 02 03:54:39 PM PDT 24
Finished May 02 03:54:44 PM PDT 24
Peak memory 194160 kb
Host smart-e51ac94c-6e5c-4749-99a4-02675a8a2635
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809706977 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_
all.3809706977
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.3935324072
Short name T93
Test name
Test status
Simulation time 70457427186 ps
CPU time 732.86 seconds
Started May 02 03:54:43 PM PDT 24
Finished May 02 04:06:59 PM PDT 24
Peak memory 200404 kb
Host smart-6c5b3afa-55f1-4507-9581-ee2b1d00f07b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935324072 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.3935324072
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.aon_timer_jump.2160085989
Short name T207
Test name
Test status
Simulation time 484736771 ps
CPU time 0.76 seconds
Started May 02 03:54:42 PM PDT 24
Finished May 02 03:54:44 PM PDT 24
Peak memory 183552 kb
Host smart-3a3e2251-3bf7-4ebe-b1c6-485852a0f274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160085989 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.2160085989
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.1938909070
Short name T188
Test name
Test status
Simulation time 17728382078 ps
CPU time 31.76 seconds
Started May 02 03:54:43 PM PDT 24
Finished May 02 03:55:17 PM PDT 24
Peak memory 183632 kb
Host smart-8b50b783-fb0f-4893-8f6a-91fb34fd5a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938909070 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.1938909070
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.1471558645
Short name T66
Test name
Test status
Simulation time 612956319 ps
CPU time 1.6 seconds
Started May 02 03:54:41 PM PDT 24
Finished May 02 03:54:44 PM PDT 24
Peak memory 183568 kb
Host smart-f1a8ce27-9da0-4341-bbf7-6100d0308f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471558645 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.1471558645
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.3647776915
Short name T276
Test name
Test status
Simulation time 65997127398 ps
CPU time 7.41 seconds
Started May 02 03:54:41 PM PDT 24
Finished May 02 03:54:50 PM PDT 24
Peak memory 195064 kb
Host smart-ccc70538-797d-4f59-a7d2-a992f869bc7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647776915 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_
all.3647776915
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_jump.4111943075
Short name T285
Test name
Test status
Simulation time 572075799 ps
CPU time 0.7 seconds
Started May 02 03:54:45 PM PDT 24
Finished May 02 03:54:48 PM PDT 24
Peak memory 183560 kb
Host smart-4da9c4f1-94ba-4dee-ac97-f055cbf62e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111943075 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.4111943075
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.3599582445
Short name T118
Test name
Test status
Simulation time 24618655913 ps
CPU time 32.34 seconds
Started May 02 03:54:43 PM PDT 24
Finished May 02 03:55:18 PM PDT 24
Peak memory 183604 kb
Host smart-22fec04e-46bf-460f-91ed-eafe02cbce35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599582445 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.3599582445
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.4116739717
Short name T163
Test name
Test status
Simulation time 486570886 ps
CPU time 0.81 seconds
Started May 02 03:54:55 PM PDT 24
Finished May 02 03:54:58 PM PDT 24
Peak memory 183608 kb
Host smart-61c137f1-ebdc-43a4-a689-3dc842523364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116739717 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.4116739717
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.2762062600
Short name T166
Test name
Test status
Simulation time 152567633292 ps
CPU time 233.56 seconds
Started May 02 03:54:40 PM PDT 24
Finished May 02 03:58:35 PM PDT 24
Peak memory 183604 kb
Host smart-b385b4d4-5c2c-4be1-8ffc-be9027113d64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762062600 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_
all.2762062600
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.1926555520
Short name T185
Test name
Test status
Simulation time 14046573219 ps
CPU time 150.05 seconds
Started May 02 03:54:42 PM PDT 24
Finished May 02 03:57:14 PM PDT 24
Peak memory 198532 kb
Host smart-51ba77e0-91d9-4405-afb7-1bdfb47213f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926555520 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.1926555520
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.aon_timer_jump.2308879143
Short name T267
Test name
Test status
Simulation time 466415532 ps
CPU time 1.33 seconds
Started May 02 03:54:43 PM PDT 24
Finished May 02 03:54:47 PM PDT 24
Peak memory 183572 kb
Host smart-23f0b7eb-01e9-4b05-af76-477abec58bac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308879143 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.2308879143
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.401417412
Short name T154
Test name
Test status
Simulation time 48166005489 ps
CPU time 75.99 seconds
Started May 02 03:54:39 PM PDT 24
Finished May 02 03:55:56 PM PDT 24
Peak memory 183608 kb
Host smart-117c422c-d50c-4b11-a10a-23cb52f976f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401417412 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.401417412
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.1556049258
Short name T237
Test name
Test status
Simulation time 453513632 ps
CPU time 1.22 seconds
Started May 02 03:54:35 PM PDT 24
Finished May 02 03:54:37 PM PDT 24
Peak memory 183560 kb
Host smart-f1ce918c-7107-4695-a447-85d75650f8a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556049258 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.1556049258
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.572555855
Short name T143
Test name
Test status
Simulation time 95499829061 ps
CPU time 18.22 seconds
Started May 02 03:54:46 PM PDT 24
Finished May 02 03:55:07 PM PDT 24
Peak memory 195292 kb
Host smart-f51e6b4f-6702-47d1-b067-1e26993b56d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572555855 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_a
ll.572555855
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.3494907071
Short name T23
Test name
Test status
Simulation time 69031838773 ps
CPU time 606.95 seconds
Started May 02 03:54:43 PM PDT 24
Finished May 02 04:04:53 PM PDT 24
Peak memory 198456 kb
Host smart-b44ea871-98ad-4220-8c32-881e7b1a7103
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494907071 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.3494907071
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_jump.2021610655
Short name T212
Test name
Test status
Simulation time 552185822 ps
CPU time 0.73 seconds
Started May 02 03:54:34 PM PDT 24
Finished May 02 03:54:36 PM PDT 24
Peak memory 183568 kb
Host smart-1228ea05-a30d-46c4-845c-537ad0e35326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021610655 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.2021610655
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.4032878766
Short name T277
Test name
Test status
Simulation time 36173101418 ps
CPU time 57.28 seconds
Started May 02 03:54:32 PM PDT 24
Finished May 02 03:55:31 PM PDT 24
Peak memory 183616 kb
Host smart-bbcfd85d-8f0c-4154-9ef2-2507d9097427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032878766 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.4032878766
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.870932734
Short name T18
Test name
Test status
Simulation time 8291189572 ps
CPU time 14.28 seconds
Started May 02 03:54:07 PM PDT 24
Finished May 02 03:54:25 PM PDT 24
Peak memory 215620 kb
Host smart-93fd332c-17a1-4785-bcf7-1345804e5eb4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870932734 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.870932734
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.2113259433
Short name T217
Test name
Test status
Simulation time 386680768 ps
CPU time 0.69 seconds
Started May 02 03:54:33 PM PDT 24
Finished May 02 03:54:34 PM PDT 24
Peak memory 183564 kb
Host smart-13e8e63d-7ad8-4ad1-880d-39c06987c0a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113259433 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.2113259433
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.3177450588
Short name T231
Test name
Test status
Simulation time 13142007861 ps
CPU time 22.75 seconds
Started May 02 03:54:09 PM PDT 24
Finished May 02 03:54:35 PM PDT 24
Peak memory 193864 kb
Host smart-87b15542-6341-4951-83f0-abe83b08235e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177450588 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_a
ll.3177450588
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_jump.1547935273
Short name T282
Test name
Test status
Simulation time 460726731 ps
CPU time 1.39 seconds
Started May 02 03:54:41 PM PDT 24
Finished May 02 03:54:44 PM PDT 24
Peak memory 183560 kb
Host smart-014d9759-ac5a-470e-a362-735d0463e80c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547935273 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.1547935273
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.3168066396
Short name T259
Test name
Test status
Simulation time 58080306209 ps
CPU time 21.51 seconds
Started May 02 03:54:32 PM PDT 24
Finished May 02 03:54:54 PM PDT 24
Peak memory 183632 kb
Host smart-8394e476-6088-436c-bab1-97330459d7b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168066396 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.3168066396
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.1267629653
Short name T2
Test name
Test status
Simulation time 474222055 ps
CPU time 0.6 seconds
Started May 02 03:54:46 PM PDT 24
Finished May 02 03:54:48 PM PDT 24
Peak memory 183564 kb
Host smart-6b594e34-d745-425b-9b8d-c9605d1a7b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267629653 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.1267629653
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.2930392007
Short name T172
Test name
Test status
Simulation time 138041106409 ps
CPU time 105.98 seconds
Started May 02 03:54:42 PM PDT 24
Finished May 02 03:56:30 PM PDT 24
Peak memory 195516 kb
Host smart-af1ead3e-8961-4a97-8a1b-578e335e7e57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930392007 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_
all.2930392007
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/21.aon_timer_jump.3727756006
Short name T200
Test name
Test status
Simulation time 545438169 ps
CPU time 1.33 seconds
Started May 02 03:54:40 PM PDT 24
Finished May 02 03:54:42 PM PDT 24
Peak memory 183524 kb
Host smart-3359e837-f7f4-41e8-a700-79f33be749d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727756006 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.3727756006
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.919570115
Short name T159
Test name
Test status
Simulation time 14670166492 ps
CPU time 10.37 seconds
Started May 02 03:54:40 PM PDT 24
Finished May 02 03:54:52 PM PDT 24
Peak memory 191824 kb
Host smart-57df5a66-85b8-4d3f-87ff-0ba1ed8de2b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919570115 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.919570115
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.2678682323
Short name T89
Test name
Test status
Simulation time 614699197 ps
CPU time 0.67 seconds
Started May 02 03:54:36 PM PDT 24
Finished May 02 03:54:37 PM PDT 24
Peak memory 183580 kb
Host smart-5f2a3142-8881-44fe-b347-0013d38e10a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678682323 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.2678682323
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.203727316
Short name T227
Test name
Test status
Simulation time 47127754817 ps
CPU time 18.43 seconds
Started May 02 03:54:41 PM PDT 24
Finished May 02 03:55:01 PM PDT 24
Peak memory 183628 kb
Host smart-6558d80f-39d1-4bca-a306-b205573a40d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203727316 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_a
ll.203727316
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.2782712810
Short name T194
Test name
Test status
Simulation time 265118165950 ps
CPU time 589.51 seconds
Started May 02 03:54:34 PM PDT 24
Finished May 02 04:04:24 PM PDT 24
Peak memory 206688 kb
Host smart-dd31b922-efb4-44af-abd2-7c6f84a31030
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782712810 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.2782712810
Directory /workspace/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.aon_timer_jump.1751554651
Short name T62
Test name
Test status
Simulation time 556260274 ps
CPU time 0.77 seconds
Started May 02 03:54:43 PM PDT 24
Finished May 02 03:54:46 PM PDT 24
Peak memory 183520 kb
Host smart-d643289f-3c6e-4e65-94f2-dee96a1eea7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751554651 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.1751554651
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.575519693
Short name T120
Test name
Test status
Simulation time 36655887468 ps
CPU time 27.85 seconds
Started May 02 03:54:43 PM PDT 24
Finished May 02 03:55:14 PM PDT 24
Peak memory 191772 kb
Host smart-a52d941e-dbb1-4361-9c1f-4cd93679bf4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575519693 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.575519693
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.2646670963
Short name T162
Test name
Test status
Simulation time 581808412 ps
CPU time 0.99 seconds
Started May 02 03:54:34 PM PDT 24
Finished May 02 03:54:36 PM PDT 24
Peak memory 183568 kb
Host smart-21baff6e-b23e-458c-9d65-f1bdf14ebeb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646670963 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.2646670963
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.466971814
Short name T235
Test name
Test status
Simulation time 460257753331 ps
CPU time 180.24 seconds
Started May 02 03:54:32 PM PDT 24
Finished May 02 03:57:33 PM PDT 24
Peak memory 194296 kb
Host smart-86451870-4061-44a2-bbaa-d73c0d0afcd7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466971814 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_a
ll.466971814
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.747809732
Short name T98
Test name
Test status
Simulation time 216786572122 ps
CPU time 165.66 seconds
Started May 02 03:54:40 PM PDT 24
Finished May 02 03:57:27 PM PDT 24
Peak memory 198496 kb
Host smart-f1e4da65-cd6d-470b-9eb2-db3222aa0cfe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747809732 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.747809732
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.aon_timer_jump.3138770854
Short name T240
Test name
Test status
Simulation time 351950915 ps
CPU time 1.08 seconds
Started May 02 03:54:36 PM PDT 24
Finished May 02 03:54:38 PM PDT 24
Peak memory 183544 kb
Host smart-6bcade4f-f87f-4649-ac5c-f4919c858f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138770854 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.3138770854
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.1042653091
Short name T151
Test name
Test status
Simulation time 20704377829 ps
CPU time 28.89 seconds
Started May 02 03:54:38 PM PDT 24
Finished May 02 03:55:08 PM PDT 24
Peak memory 191832 kb
Host smart-a17b796c-4003-4dca-b3c2-c7c0a86ed272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042653091 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.1042653091
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.4230333185
Short name T204
Test name
Test status
Simulation time 544421350 ps
CPU time 1.48 seconds
Started May 02 03:54:43 PM PDT 24
Finished May 02 03:54:47 PM PDT 24
Peak memory 183560 kb
Host smart-3ea4c53e-1a5c-49d7-918a-822ab08a6c2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230333185 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.4230333185
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.512251413
Short name T132
Test name
Test status
Simulation time 103965793328 ps
CPU time 151.91 seconds
Started May 02 03:54:43 PM PDT 24
Finished May 02 03:57:17 PM PDT 24
Peak memory 194224 kb
Host smart-c58a493d-e3e5-46bd-a641-b34ffec9dc6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512251413 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_a
ll.512251413
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.325426431
Short name T91
Test name
Test status
Simulation time 24515432352 ps
CPU time 169.03 seconds
Started May 02 03:54:48 PM PDT 24
Finished May 02 03:57:41 PM PDT 24
Peak memory 198548 kb
Host smart-f0822451-e5de-49e2-9da0-22ea48c3eb03
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325426431 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.325426431
Directory /workspace/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.aon_timer_jump.3285319786
Short name T49
Test name
Test status
Simulation time 454503349 ps
CPU time 1.17 seconds
Started May 02 03:54:45 PM PDT 24
Finished May 02 03:54:48 PM PDT 24
Peak memory 183572 kb
Host smart-4f7089aa-179c-46cc-a371-c0cb96ab8a95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285319786 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.3285319786
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.1790343682
Short name T144
Test name
Test status
Simulation time 28351103684 ps
CPU time 10.86 seconds
Started May 02 03:54:45 PM PDT 24
Finished May 02 03:54:58 PM PDT 24
Peak memory 183620 kb
Host smart-aac12823-bb2a-4591-a74e-66784ea055e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790343682 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.1790343682
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.3345608378
Short name T167
Test name
Test status
Simulation time 543357509 ps
CPU time 0.67 seconds
Started May 02 03:54:48 PM PDT 24
Finished May 02 03:54:51 PM PDT 24
Peak memory 183564 kb
Host smart-45d80564-102b-4ac1-8af5-e4e21b6aa0e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345608378 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.3345608378
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.3894957869
Short name T238
Test name
Test status
Simulation time 152757111468 ps
CPU time 12.06 seconds
Started May 02 03:54:44 PM PDT 24
Finished May 02 03:54:58 PM PDT 24
Peak memory 195476 kb
Host smart-3b1df30d-e9e6-44eb-aaca-05555d981d14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894957869 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_
all.3894957869
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.1505588479
Short name T152
Test name
Test status
Simulation time 63515974193 ps
CPU time 695.06 seconds
Started May 02 03:54:35 PM PDT 24
Finished May 02 04:06:11 PM PDT 24
Peak memory 199356 kb
Host smart-8bc55ebf-bbce-46c1-bfeb-d88a2eaddd3f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505588479 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand_reset.1505588479
Directory /workspace/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.aon_timer_jump.2178302252
Short name T246
Test name
Test status
Simulation time 420045927 ps
CPU time 1.19 seconds
Started May 02 03:54:44 PM PDT 24
Finished May 02 03:54:47 PM PDT 24
Peak memory 183552 kb
Host smart-8a6772b8-9d81-4ab2-bbfb-8bd65333724d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178302252 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.2178302252
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.1790110660
Short name T183
Test name
Test status
Simulation time 59473231432 ps
CPU time 97.52 seconds
Started May 02 03:54:50 PM PDT 24
Finished May 02 03:56:30 PM PDT 24
Peak memory 183632 kb
Host smart-19f58341-aa16-4279-bd5e-4a90c0dd1a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790110660 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.1790110660
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.240291087
Short name T134
Test name
Test status
Simulation time 406395487 ps
CPU time 0.69 seconds
Started May 02 03:54:46 PM PDT 24
Finished May 02 03:54:49 PM PDT 24
Peak memory 183568 kb
Host smart-f61ee237-bbf0-4331-a75a-1a19031aba50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240291087 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.240291087
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.3122381348
Short name T254
Test name
Test status
Simulation time 56008927874 ps
CPU time 20.44 seconds
Started May 02 03:54:43 PM PDT 24
Finished May 02 03:55:06 PM PDT 24
Peak memory 183616 kb
Host smart-38d6bb21-7242-4652-afbb-ebee5f63efac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122381348 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_
all.3122381348
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.275942315
Short name T52
Test name
Test status
Simulation time 76730567709 ps
CPU time 764.56 seconds
Started May 02 03:54:39 PM PDT 24
Finished May 02 04:07:25 PM PDT 24
Peak memory 200840 kb
Host smart-31385d4c-bf35-4a92-89fc-5259c91e9091
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275942315 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.275942315
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.aon_timer_jump.466745832
Short name T116
Test name
Test status
Simulation time 573893472 ps
CPU time 1.48 seconds
Started May 02 03:54:34 PM PDT 24
Finished May 02 03:54:36 PM PDT 24
Peak memory 183552 kb
Host smart-704d8648-0179-404f-859a-9694e40bba2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466745832 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.466745832
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.725389382
Short name T232
Test name
Test status
Simulation time 34589229138 ps
CPU time 11.62 seconds
Started May 02 03:54:52 PM PDT 24
Finished May 02 03:55:07 PM PDT 24
Peak memory 191824 kb
Host smart-7968922a-30bf-4b63-8513-d3553e5c53e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725389382 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.725389382
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.1287207208
Short name T177
Test name
Test status
Simulation time 411697513 ps
CPU time 0.65 seconds
Started May 02 03:54:49 PM PDT 24
Finished May 02 03:54:52 PM PDT 24
Peak memory 183552 kb
Host smart-ef89e500-6431-4428-985e-f7e981f0d033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287207208 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.1287207208
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.790513595
Short name T37
Test name
Test status
Simulation time 110639602263 ps
CPU time 94.78 seconds
Started May 02 03:54:42 PM PDT 24
Finished May 02 03:56:19 PM PDT 24
Peak memory 195536 kb
Host smart-42928402-7721-4a54-ad29-af6bfbaa72ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790513595 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_a
ll.790513595
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.1241942147
Short name T53
Test name
Test status
Simulation time 105188899737 ps
CPU time 267.62 seconds
Started May 02 03:54:41 PM PDT 24
Finished May 02 03:59:11 PM PDT 24
Peak memory 198448 kb
Host smart-02983d2e-88ca-4af4-9dc2-9347574bd868
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241942147 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.1241942147
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_jump.1769682174
Short name T148
Test name
Test status
Simulation time 380092041 ps
CPU time 1.13 seconds
Started May 02 03:54:41 PM PDT 24
Finished May 02 03:54:44 PM PDT 24
Peak memory 183544 kb
Host smart-c03757db-1740-47a9-93d8-7a4ba2e43238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769682174 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.1769682174
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.852447769
Short name T249
Test name
Test status
Simulation time 4172315213 ps
CPU time 1.08 seconds
Started May 02 03:54:41 PM PDT 24
Finished May 02 03:54:43 PM PDT 24
Peak memory 183616 kb
Host smart-9134c6ba-b3a9-4361-9776-d5c7c8602c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852447769 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.852447769
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.749220171
Short name T168
Test name
Test status
Simulation time 562229759 ps
CPU time 1 seconds
Started May 02 03:54:48 PM PDT 24
Finished May 02 03:54:52 PM PDT 24
Peak memory 183536 kb
Host smart-69bdfe64-79a6-433d-b5ec-23ebf1c9706f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749220171 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.749220171
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.162561750
Short name T131
Test name
Test status
Simulation time 38054056632 ps
CPU time 12.49 seconds
Started May 02 03:54:47 PM PDT 24
Finished May 02 03:55:03 PM PDT 24
Peak memory 183556 kb
Host smart-e75e8e84-7e9f-4a59-bd20-41297e1b54f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162561750 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_a
ll.162561750
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.1150469505
Short name T138
Test name
Test status
Simulation time 135771274016 ps
CPU time 594.08 seconds
Started May 02 03:54:51 PM PDT 24
Finished May 02 04:04:48 PM PDT 24
Peak memory 199272 kb
Host smart-fa58a27c-f673-4d88-b921-7be6426939ff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150469505 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.1150469505
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_jump.464228046
Short name T155
Test name
Test status
Simulation time 393305193 ps
CPU time 1.16 seconds
Started May 02 03:54:42 PM PDT 24
Finished May 02 03:54:45 PM PDT 24
Peak memory 183532 kb
Host smart-50d23445-d86e-470d-b9d3-b29bae15c906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464228046 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.464228046
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.601119553
Short name T35
Test name
Test status
Simulation time 33559591651 ps
CPU time 13.49 seconds
Started May 02 03:54:41 PM PDT 24
Finished May 02 03:54:55 PM PDT 24
Peak memory 183604 kb
Host smart-fa160e95-0469-4fa3-9c1d-718cd27bedd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601119553 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.601119553
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.101113916
Short name T262
Test name
Test status
Simulation time 350009178 ps
CPU time 0.67 seconds
Started May 02 03:54:49 PM PDT 24
Finished May 02 03:54:52 PM PDT 24
Peak memory 183516 kb
Host smart-c78167f3-aed6-49ac-b86f-f40af7829f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101113916 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.101113916
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.2556900678
Short name T135
Test name
Test status
Simulation time 77911440947 ps
CPU time 29.09 seconds
Started May 02 03:54:58 PM PDT 24
Finished May 02 03:55:29 PM PDT 24
Peak memory 183752 kb
Host smart-bbe7bee2-03a4-4f60-9dd8-843e135f157c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556900678 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_
all.2556900678
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.2803591018
Short name T251
Test name
Test status
Simulation time 117021378030 ps
CPU time 308.08 seconds
Started May 02 03:54:48 PM PDT 24
Finished May 02 03:59:59 PM PDT 24
Peak memory 198456 kb
Host smart-b0328cb1-ca4f-49cf-83a0-413005f72c8e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803591018 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.2803591018
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.aon_timer_jump.3604245429
Short name T173
Test name
Test status
Simulation time 584346237 ps
CPU time 0.75 seconds
Started May 02 03:54:47 PM PDT 24
Finished May 02 03:54:51 PM PDT 24
Peak memory 183484 kb
Host smart-59b9a579-9a69-49a2-a58f-9bd579d4d91f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604245429 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.3604245429
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.3465707668
Short name T191
Test name
Test status
Simulation time 17597917756 ps
CPU time 15.25 seconds
Started May 02 03:54:38 PM PDT 24
Finished May 02 03:54:54 PM PDT 24
Peak memory 183564 kb
Host smart-3de23287-b3d4-40c9-baf8-df8e2dc168f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465707668 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.3465707668
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.2998213429
Short name T123
Test name
Test status
Simulation time 373958472 ps
CPU time 1.12 seconds
Started May 02 03:54:40 PM PDT 24
Finished May 02 03:54:43 PM PDT 24
Peak memory 183552 kb
Host smart-beaaa41d-f020-44b7-b38c-e2238e2438c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998213429 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.2998213429
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.2706376728
Short name T223
Test name
Test status
Simulation time 305292127319 ps
CPU time 243.23 seconds
Started May 02 03:54:58 PM PDT 24
Finished May 02 03:59:04 PM PDT 24
Peak memory 195292 kb
Host smart-480d7f04-72f1-4a5b-80e6-36e01d4c1d7b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706376728 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_
all.2706376728
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.37659320
Short name T92
Test name
Test status
Simulation time 90163454798 ps
CPU time 346.71 seconds
Started May 02 03:54:42 PM PDT 24
Finished May 02 04:00:31 PM PDT 24
Peak memory 198460 kb
Host smart-4f87e57e-60ac-4360-8d1d-bf2be1177252
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37659320 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.37659320
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.aon_timer_jump.1688323553
Short name T153
Test name
Test status
Simulation time 423079737 ps
CPU time 0.95 seconds
Started May 02 03:54:30 PM PDT 24
Finished May 02 03:54:32 PM PDT 24
Peak memory 183568 kb
Host smart-c27b3fe8-9a79-4e89-a224-96379e3aa631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688323553 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.1688323553
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.3936816476
Short name T13
Test name
Test status
Simulation time 11055817467 ps
CPU time 18.9 seconds
Started May 02 03:54:31 PM PDT 24
Finished May 02 03:54:51 PM PDT 24
Peak memory 191832 kb
Host smart-5f82e1f0-643e-4b73-9025-bd982581f1d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936816476 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.3936816476
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.1023236981
Short name T16
Test name
Test status
Simulation time 4281298333 ps
CPU time 7.73 seconds
Started May 02 03:54:03 PM PDT 24
Finished May 02 03:54:15 PM PDT 24
Peak memory 214820 kb
Host smart-3f00d4b2-96fa-4db4-8b19-60f8472842ba
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023236981 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.1023236981
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.3472555434
Short name T222
Test name
Test status
Simulation time 346631169 ps
CPU time 1.13 seconds
Started May 02 03:54:08 PM PDT 24
Finished May 02 03:54:12 PM PDT 24
Peak memory 183524 kb
Host smart-7c55b746-482c-4794-bb7d-65c8d16f9e14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472555434 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.3472555434
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.1479375701
Short name T165
Test name
Test status
Simulation time 80888678051 ps
CPU time 66.72 seconds
Started May 02 03:54:08 PM PDT 24
Finished May 02 03:55:18 PM PDT 24
Peak memory 183716 kb
Host smart-87ab488c-e758-44be-bc6d-48a55ff911ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479375701 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_a
ll.1479375701
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.1570013870
Short name T245
Test name
Test status
Simulation time 658251912323 ps
CPU time 625.24 seconds
Started May 02 03:54:06 PM PDT 24
Finished May 02 04:04:35 PM PDT 24
Peak memory 200100 kb
Host smart-93d48e11-d312-4643-a8f0-ccb9ddc81194
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570013870 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.1570013870
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_jump.1495546943
Short name T247
Test name
Test status
Simulation time 541134249 ps
CPU time 0.76 seconds
Started May 02 03:54:42 PM PDT 24
Finished May 02 03:54:45 PM PDT 24
Peak memory 183524 kb
Host smart-57002551-0e1a-41f5-96bd-f6d6a49bd621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495546943 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.1495546943
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.4272432461
Short name T70
Test name
Test status
Simulation time 21699249211 ps
CPU time 6.73 seconds
Started May 02 03:54:42 PM PDT 24
Finished May 02 03:54:50 PM PDT 24
Peak memory 183644 kb
Host smart-3bba5dd9-ec0e-41ab-90db-af2ac3964c53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272432461 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.4272432461
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.3248442303
Short name T268
Test name
Test status
Simulation time 377770152 ps
CPU time 0.71 seconds
Started May 02 03:54:50 PM PDT 24
Finished May 02 03:54:54 PM PDT 24
Peak memory 183564 kb
Host smart-b57e8da5-c6a6-4a1b-9f13-c007f4432cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248442303 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.3248442303
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.2722188126
Short name T140
Test name
Test status
Simulation time 28366112897 ps
CPU time 12.29 seconds
Started May 02 03:54:48 PM PDT 24
Finished May 02 03:55:04 PM PDT 24
Peak memory 183624 kb
Host smart-5f457417-ca47-4b4b-b495-588d5a23a30e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722188126 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_
all.2722188126
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.4275095087
Short name T145
Test name
Test status
Simulation time 3593178724 ps
CPU time 32.45 seconds
Started May 02 03:54:42 PM PDT 24
Finished May 02 03:55:17 PM PDT 24
Peak memory 198548 kb
Host smart-d71de7df-59f6-4eb3-8725-baea6f9d617a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275095087 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.4275095087
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.aon_timer_jump.3039417933
Short name T220
Test name
Test status
Simulation time 495931949 ps
CPU time 0.74 seconds
Started May 02 03:54:42 PM PDT 24
Finished May 02 03:54:45 PM PDT 24
Peak memory 183560 kb
Host smart-7af53626-7982-472b-ad3f-cdd46cc17fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039417933 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.3039417933
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.2688721508
Short name T270
Test name
Test status
Simulation time 15347517122 ps
CPU time 5.54 seconds
Started May 02 03:54:43 PM PDT 24
Finished May 02 03:54:51 PM PDT 24
Peak memory 191788 kb
Host smart-0bdf9111-824d-41ed-9659-83f36614d2da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688721508 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.2688721508
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.2177121289
Short name T146
Test name
Test status
Simulation time 417713684 ps
CPU time 0.65 seconds
Started May 02 03:54:48 PM PDT 24
Finished May 02 03:54:52 PM PDT 24
Peak memory 183568 kb
Host smart-64232451-1df3-4621-84d0-0367ed761224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177121289 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.2177121289
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.995068142
Short name T182
Test name
Test status
Simulation time 22000945494 ps
CPU time 33.5 seconds
Started May 02 03:54:45 PM PDT 24
Finished May 02 03:55:20 PM PDT 24
Peak memory 183592 kb
Host smart-16977089-2fe5-4e8b-9bb4-c04f1996fc18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995068142 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_a
ll.995068142
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.335679964
Short name T33
Test name
Test status
Simulation time 22514969720 ps
CPU time 95.86 seconds
Started May 02 03:54:42 PM PDT 24
Finished May 02 03:56:21 PM PDT 24
Peak memory 198452 kb
Host smart-12718759-bf89-4c6f-aced-887a25073bf6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335679964 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.335679964
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.aon_timer_jump.4067683159
Short name T63
Test name
Test status
Simulation time 381568794 ps
CPU time 1.03 seconds
Started May 02 03:54:43 PM PDT 24
Finished May 02 03:54:47 PM PDT 24
Peak memory 183544 kb
Host smart-217799bb-42d8-4a3c-a508-1c02e07a14a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067683159 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.4067683159
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.3427884135
Short name T90
Test name
Test status
Simulation time 24709494912 ps
CPU time 37.16 seconds
Started May 02 03:54:41 PM PDT 24
Finished May 02 03:55:20 PM PDT 24
Peak memory 183588 kb
Host smart-d737530d-a2de-4daf-bff9-95bf8caf8a61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427884135 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.3427884135
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.2790839278
Short name T133
Test name
Test status
Simulation time 370451711 ps
CPU time 0.7 seconds
Started May 02 03:54:51 PM PDT 24
Finished May 02 03:54:55 PM PDT 24
Peak memory 183552 kb
Host smart-8cf6f1e5-7783-493e-a7a5-b0721376ea48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790839278 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.2790839278
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.3450368338
Short name T192
Test name
Test status
Simulation time 58971998774 ps
CPU time 92.82 seconds
Started May 02 03:54:48 PM PDT 24
Finished May 02 03:56:24 PM PDT 24
Peak memory 183680 kb
Host smart-44c0435e-8d89-420d-a848-a552ae1a950a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450368338 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_
all.3450368338
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.2708881346
Short name T12
Test name
Test status
Simulation time 52436473950 ps
CPU time 141.8 seconds
Started May 02 03:54:44 PM PDT 24
Finished May 02 03:57:08 PM PDT 24
Peak memory 198500 kb
Host smart-bf7fc4bb-8fc7-4a46-ac93-9c3b3e902bcd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708881346 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_reset.2708881346
Directory /workspace/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.aon_timer_jump.1194559342
Short name T147
Test name
Test status
Simulation time 597178280 ps
CPU time 0.79 seconds
Started May 02 03:54:50 PM PDT 24
Finished May 02 03:54:53 PM PDT 24
Peak memory 183564 kb
Host smart-c710a3b6-894c-4e20-9b5f-c9a04f1ea024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194559342 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.1194559342
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.1593891306
Short name T279
Test name
Test status
Simulation time 50057504573 ps
CPU time 60.7 seconds
Started May 02 03:54:43 PM PDT 24
Finished May 02 03:55:46 PM PDT 24
Peak memory 191844 kb
Host smart-e4cd736e-8e1c-4673-8955-a08290ca416f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593891306 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.1593891306
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.775055442
Short name T209
Test name
Test status
Simulation time 459682591 ps
CPU time 0.73 seconds
Started May 02 03:54:42 PM PDT 24
Finished May 02 03:54:45 PM PDT 24
Peak memory 183540 kb
Host smart-f4845d2e-d97f-485f-86be-54f8b995dcb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775055442 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.775055442
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.3296863452
Short name T99
Test name
Test status
Simulation time 43489122084 ps
CPU time 230.5 seconds
Started May 02 03:54:43 PM PDT 24
Finished May 02 03:58:35 PM PDT 24
Peak memory 198536 kb
Host smart-d363d576-d34c-4b3f-89b0-7881d595a6f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296863452 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.3296863452
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.aon_timer_jump.3779532538
Short name T122
Test name
Test status
Simulation time 365703258 ps
CPU time 1.1 seconds
Started May 02 03:54:45 PM PDT 24
Finished May 02 03:54:48 PM PDT 24
Peak memory 183532 kb
Host smart-58c6b7b6-3d3b-4ecf-9269-2028b1a20a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779532538 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.3779532538
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.15054001
Short name T6
Test name
Test status
Simulation time 6588180376 ps
CPU time 3.01 seconds
Started May 02 03:54:43 PM PDT 24
Finished May 02 03:54:49 PM PDT 24
Peak memory 183604 kb
Host smart-4791e6e8-a0a4-4235-bede-1b340c5878c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15054001 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.15054001
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.4178804789
Short name T46
Test name
Test status
Simulation time 365794473 ps
CPU time 0.81 seconds
Started May 02 03:54:45 PM PDT 24
Finished May 02 03:54:48 PM PDT 24
Peak memory 183580 kb
Host smart-143d286b-e529-44d4-9d59-90c6209c57bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178804789 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.4178804789
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.2618714995
Short name T121
Test name
Test status
Simulation time 145821141482 ps
CPU time 55.67 seconds
Started May 02 03:54:46 PM PDT 24
Finished May 02 03:55:45 PM PDT 24
Peak memory 192996 kb
Host smart-3a3eac4f-4687-4a24-bda0-e4b4fd690cfc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618714995 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_
all.2618714995
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.1235974380
Short name T218
Test name
Test status
Simulation time 27411726790 ps
CPU time 287.07 seconds
Started May 02 03:54:48 PM PDT 24
Finished May 02 03:59:38 PM PDT 24
Peak memory 198480 kb
Host smart-26c6b3dc-d291-4641-9be7-91099a2cda33
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235974380 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.1235974380
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.aon_timer_jump.2606245042
Short name T129
Test name
Test status
Simulation time 469209099 ps
CPU time 0.94 seconds
Started May 02 03:54:45 PM PDT 24
Finished May 02 03:54:48 PM PDT 24
Peak memory 183560 kb
Host smart-bdc960b3-6a4c-4244-82e2-7142b5983514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606245042 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.2606245042
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.332330850
Short name T102
Test name
Test status
Simulation time 28402517281 ps
CPU time 5.74 seconds
Started May 02 03:54:46 PM PDT 24
Finished May 02 03:54:54 PM PDT 24
Peak memory 191824 kb
Host smart-6bfcb718-76ab-4c04-bbc7-ad59428f2251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332330850 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.332330850
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.2446383580
Short name T43
Test name
Test status
Simulation time 349113939 ps
CPU time 0.8 seconds
Started May 02 03:54:37 PM PDT 24
Finished May 02 03:54:38 PM PDT 24
Peak memory 183548 kb
Host smart-c6fb48b7-f4d2-414c-919d-43b53497b1a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446383580 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.2446383580
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.2174817833
Short name T266
Test name
Test status
Simulation time 167981508394 ps
CPU time 121.93 seconds
Started May 02 03:54:40 PM PDT 24
Finished May 02 03:56:44 PM PDT 24
Peak memory 183608 kb
Host smart-a7aa630b-856f-4393-aea0-16cef4e3ba7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174817833 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_
all.2174817833
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.3610761182
Short name T226
Test name
Test status
Simulation time 149446890141 ps
CPU time 453.02 seconds
Started May 02 03:54:47 PM PDT 24
Finished May 02 04:02:23 PM PDT 24
Peak memory 198516 kb
Host smart-0ed35d0f-aab2-4cfd-ae0e-074aaedbf211
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610761182 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.3610761182
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.aon_timer_jump.3292608327
Short name T243
Test name
Test status
Simulation time 621157570 ps
CPU time 0.82 seconds
Started May 02 03:54:49 PM PDT 24
Finished May 02 03:54:58 PM PDT 24
Peak memory 183564 kb
Host smart-b42386aa-5336-4161-b206-e3f917b09e34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292608327 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.3292608327
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.2180075824
Short name T5
Test name
Test status
Simulation time 33403469437 ps
CPU time 5.47 seconds
Started May 02 03:54:46 PM PDT 24
Finished May 02 03:54:54 PM PDT 24
Peak memory 191816 kb
Host smart-dfdb1679-8dd3-4f10-8ca6-601d28a9a4f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180075824 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.2180075824
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.65164830
Short name T275
Test name
Test status
Simulation time 558925518 ps
CPU time 0.57 seconds
Started May 02 03:54:49 PM PDT 24
Finished May 02 03:54:53 PM PDT 24
Peak memory 183528 kb
Host smart-080fbe40-c7c1-4fc6-b6fd-5d92266f8f0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65164830 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.65164830
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.3797690732
Short name T127
Test name
Test status
Simulation time 91340784296 ps
CPU time 156.97 seconds
Started May 02 03:54:47 PM PDT 24
Finished May 02 03:57:27 PM PDT 24
Peak memory 183604 kb
Host smart-2538f15a-0980-4dba-9355-efb99820be1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797690732 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_
all.3797690732
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_jump.3592031767
Short name T170
Test name
Test status
Simulation time 611020509 ps
CPU time 1.41 seconds
Started May 02 03:54:54 PM PDT 24
Finished May 02 03:54:57 PM PDT 24
Peak memory 183540 kb
Host smart-7cb0f1d8-2bce-443f-b64b-e9f54df29e20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592031767 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.3592031767
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.1719369065
Short name T201
Test name
Test status
Simulation time 40627513781 ps
CPU time 28.49 seconds
Started May 02 03:54:47 PM PDT 24
Finished May 02 03:55:18 PM PDT 24
Peak memory 191860 kb
Host smart-9b3c7cec-0c56-4006-95fb-dfb3a9e98562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719369065 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.1719369065
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.992370049
Short name T233
Test name
Test status
Simulation time 358323777 ps
CPU time 0.72 seconds
Started May 02 03:54:51 PM PDT 24
Finished May 02 03:54:55 PM PDT 24
Peak memory 183552 kb
Host smart-5f9a4f31-b31c-4641-a689-ceddf1854eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992370049 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.992370049
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.2019136573
Short name T274
Test name
Test status
Simulation time 85257274458 ps
CPU time 135.74 seconds
Started May 02 03:54:46 PM PDT 24
Finished May 02 03:57:05 PM PDT 24
Peak memory 183604 kb
Host smart-72dade17-cf17-47ac-ac1b-7c88a9ee0e52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019136573 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_
all.2019136573
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.3897100211
Short name T94
Test name
Test status
Simulation time 197292402938 ps
CPU time 362.93 seconds
Started May 02 03:54:49 PM PDT 24
Finished May 02 04:00:54 PM PDT 24
Peak memory 198572 kb
Host smart-9fa583f7-b5eb-48c7-a50e-7702b0650a6d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897100211 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.3897100211
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.aon_timer_jump.2376961771
Short name T187
Test name
Test status
Simulation time 440539347 ps
CPU time 0.68 seconds
Started May 02 03:54:45 PM PDT 24
Finished May 02 03:54:47 PM PDT 24
Peak memory 183552 kb
Host smart-ad6e6e1c-d9b0-4b97-a102-2cc9ff1b2778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376961771 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.2376961771
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.565459552
Short name T219
Test name
Test status
Simulation time 30302129692 ps
CPU time 9.32 seconds
Started May 02 03:54:43 PM PDT 24
Finished May 02 03:54:55 PM PDT 24
Peak memory 183620 kb
Host smart-ff1a6627-e1d3-4a4a-907f-d3fb46bd0312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565459552 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.565459552
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.1360237459
Short name T186
Test name
Test status
Simulation time 409783991 ps
CPU time 0.7 seconds
Started May 02 03:54:45 PM PDT 24
Finished May 02 03:54:47 PM PDT 24
Peak memory 183544 kb
Host smart-ea85e59a-7556-472b-9fba-92383c977cc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360237459 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.1360237459
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.751971913
Short name T273
Test name
Test status
Simulation time 145951878346 ps
CPU time 222.3 seconds
Started May 02 03:54:46 PM PDT 24
Finished May 02 03:58:31 PM PDT 24
Peak memory 195444 kb
Host smart-8b7c2b35-71a0-4c43-b183-9224a63f7332
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751971913 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_a
ll.751971913
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.1012321539
Short name T101
Test name
Test status
Simulation time 17031969087 ps
CPU time 71.78 seconds
Started May 02 03:54:45 PM PDT 24
Finished May 02 03:55:59 PM PDT 24
Peak memory 198524 kb
Host smart-92c421ce-2fdd-4df6-8bf1-861db32b810f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012321539 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand_reset.1012321539
Directory /workspace/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.aon_timer_jump.17859752
Short name T193
Test name
Test status
Simulation time 478694898 ps
CPU time 0.71 seconds
Started May 02 03:54:44 PM PDT 24
Finished May 02 03:54:47 PM PDT 24
Peak memory 183560 kb
Host smart-e94c3ba0-60ec-46c9-a367-f041c3f60571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17859752 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.17859752
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.3560532120
Short name T117
Test name
Test status
Simulation time 19092939369 ps
CPU time 15.75 seconds
Started May 02 03:54:43 PM PDT 24
Finished May 02 03:55:01 PM PDT 24
Peak memory 183636 kb
Host smart-1dfe9678-1e99-4f5f-bcb6-4ddddd38f6c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560532120 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.3560532120
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.3409407527
Short name T242
Test name
Test status
Simulation time 405516203 ps
CPU time 0.86 seconds
Started May 02 03:54:41 PM PDT 24
Finished May 02 03:54:43 PM PDT 24
Peak memory 183564 kb
Host smart-8072cc30-e0a4-49fb-a23b-17c8a3af8ab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409407527 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.3409407527
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.3294394383
Short name T136
Test name
Test status
Simulation time 129055726962 ps
CPU time 91.63 seconds
Started May 02 03:54:55 PM PDT 24
Finished May 02 03:56:29 PM PDT 24
Peak memory 183608 kb
Host smart-f35f7051-ea00-470b-8401-433661951925
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294394383 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_
all.3294394383
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_jump.2952325743
Short name T40
Test name
Test status
Simulation time 447587796 ps
CPU time 0.92 seconds
Started May 02 03:54:32 PM PDT 24
Finished May 02 03:54:34 PM PDT 24
Peak memory 183552 kb
Host smart-2edacac5-b5f9-4b70-8937-9bf7b761d9c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952325743 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.2952325743
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.2424208775
Short name T157
Test name
Test status
Simulation time 22316964759 ps
CPU time 32.83 seconds
Started May 02 03:54:08 PM PDT 24
Finished May 02 03:54:44 PM PDT 24
Peak memory 183572 kb
Host smart-cf0eb803-44ee-4c88-8991-d544f51f0219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424208775 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.2424208775
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.902330809
Short name T11
Test name
Test status
Simulation time 7900562961 ps
CPU time 6.55 seconds
Started May 02 03:54:08 PM PDT 24
Finished May 02 03:54:18 PM PDT 24
Peak memory 215512 kb
Host smart-4e569570-7441-412e-8b12-06805277385e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902330809 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.902330809
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.3668374301
Short name T111
Test name
Test status
Simulation time 523110917 ps
CPU time 1.41 seconds
Started May 02 03:54:07 PM PDT 24
Finished May 02 03:54:12 PM PDT 24
Peak memory 183536 kb
Host smart-343411b0-fbf2-4f85-9263-1d7b967be634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668374301 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.3668374301
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.4193390940
Short name T264
Test name
Test status
Simulation time 88998603833 ps
CPU time 145.78 seconds
Started May 02 03:54:31 PM PDT 24
Finished May 02 03:56:58 PM PDT 24
Peak memory 183596 kb
Host smart-10ef2914-e93d-47aa-b53b-7b7720a9316e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193390940 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_a
ll.4193390940
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_jump.515725614
Short name T1
Test name
Test status
Simulation time 409490627 ps
CPU time 0.71 seconds
Started May 02 03:54:43 PM PDT 24
Finished May 02 03:54:46 PM PDT 24
Peak memory 183576 kb
Host smart-0162ac03-e19a-4e54-97ed-a8b59e91c95c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515725614 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.515725614
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.4127936904
Short name T236
Test name
Test status
Simulation time 26622603957 ps
CPU time 43.13 seconds
Started May 02 03:54:52 PM PDT 24
Finished May 02 03:55:38 PM PDT 24
Peak memory 183620 kb
Host smart-74f05233-b3f8-47ec-8cdf-7294b5b934e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127936904 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.4127936904
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.2155952166
Short name T149
Test name
Test status
Simulation time 561923746 ps
CPU time 1.44 seconds
Started May 02 03:54:44 PM PDT 24
Finished May 02 03:54:48 PM PDT 24
Peak memory 183564 kb
Host smart-bc6cf9c8-7c94-49c5-8897-b25d6938c345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155952166 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.2155952166
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.1349573912
Short name T241
Test name
Test status
Simulation time 109805898930 ps
CPU time 158.8 seconds
Started May 02 03:54:47 PM PDT 24
Finished May 02 03:57:29 PM PDT 24
Peak memory 194076 kb
Host smart-e61d37da-208a-484c-a45a-9d016fd42c0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349573912 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_
all.1349573912
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.1875315117
Short name T284
Test name
Test status
Simulation time 93819404597 ps
CPU time 1044.49 seconds
Started May 02 03:54:57 PM PDT 24
Finished May 02 04:12:23 PM PDT 24
Peak memory 205324 kb
Host smart-fb53fa7f-cf3f-4322-9914-a23e0bdb740a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875315117 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.1875315117
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.aon_timer_jump.1726286009
Short name T47
Test name
Test status
Simulation time 383729684 ps
CPU time 0.7 seconds
Started May 02 03:54:46 PM PDT 24
Finished May 02 03:54:49 PM PDT 24
Peak memory 183448 kb
Host smart-040899b9-7388-4d33-89aa-a3b86d37be1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726286009 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.1726286009
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.3471349268
Short name T215
Test name
Test status
Simulation time 31654352991 ps
CPU time 50.76 seconds
Started May 02 03:54:55 PM PDT 24
Finished May 02 03:55:48 PM PDT 24
Peak memory 191820 kb
Host smart-1416656f-e522-43f6-b442-98dd86436b7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471349268 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.3471349268
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.686544512
Short name T119
Test name
Test status
Simulation time 405605588 ps
CPU time 0.85 seconds
Started May 02 03:54:46 PM PDT 24
Finished May 02 03:54:50 PM PDT 24
Peak memory 183560 kb
Host smart-df5d03c2-c5c5-42a9-9a10-06e4cd1d5515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686544512 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.686544512
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.429762964
Short name T225
Test name
Test status
Simulation time 170703596795 ps
CPU time 40.74 seconds
Started May 02 03:54:43 PM PDT 24
Finished May 02 03:55:26 PM PDT 24
Peak memory 195512 kb
Host smart-aa7b9717-3b67-4dba-bd3c-901035ab8857
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429762964 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_a
ll.429762964
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.1555007021
Short name T181
Test name
Test status
Simulation time 128712059609 ps
CPU time 219.66 seconds
Started May 02 03:54:57 PM PDT 24
Finished May 02 03:58:38 PM PDT 24
Peak memory 198488 kb
Host smart-545aa992-3ed2-40c2-a3e6-8b6aca378f42
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555007021 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.1555007021
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.aon_timer_jump.2246730933
Short name T263
Test name
Test status
Simulation time 430829619 ps
CPU time 1.11 seconds
Started May 02 03:54:44 PM PDT 24
Finished May 02 03:54:48 PM PDT 24
Peak memory 183548 kb
Host smart-92fa85f3-b8d4-49ae-b68a-c0939ab52d42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246730933 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.2246730933
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.401501769
Short name T36
Test name
Test status
Simulation time 13951780160 ps
CPU time 6.34 seconds
Started May 02 03:54:51 PM PDT 24
Finished May 02 03:55:00 PM PDT 24
Peak memory 183616 kb
Host smart-c09adce2-44af-47fd-9766-aa79f223e537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401501769 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.401501769
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.4278415262
Short name T124
Test name
Test status
Simulation time 569840735 ps
CPU time 1.38 seconds
Started May 02 03:54:44 PM PDT 24
Finished May 02 03:54:47 PM PDT 24
Peak memory 183556 kb
Host smart-68cd7a64-4d39-46ac-a6e7-1bc3927ff476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278415262 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.4278415262
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.4182309166
Short name T234
Test name
Test status
Simulation time 252066812138 ps
CPU time 424 seconds
Started May 02 03:54:43 PM PDT 24
Finished May 02 04:01:49 PM PDT 24
Peak memory 194296 kb
Host smart-56e985ae-ecf6-42e2-abe9-b51f10c5b9e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182309166 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_
all.4182309166
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.2279620479
Short name T50
Test name
Test status
Simulation time 145110928737 ps
CPU time 300.76 seconds
Started May 02 03:55:15 PM PDT 24
Finished May 02 04:00:18 PM PDT 24
Peak memory 198544 kb
Host smart-ea380e2b-2409-4845-844d-3b6e32ff19e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279620479 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.2279620479
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.aon_timer_jump.524500834
Short name T179
Test name
Test status
Simulation time 451357442 ps
CPU time 0.74 seconds
Started May 02 03:54:50 PM PDT 24
Finished May 02 03:54:54 PM PDT 24
Peak memory 183528 kb
Host smart-28ec2f10-6f5a-4e62-b464-b3dc291aa0da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524500834 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.524500834
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.2596191599
Short name T161
Test name
Test status
Simulation time 36788592687 ps
CPU time 14.55 seconds
Started May 02 03:54:54 PM PDT 24
Finished May 02 03:55:11 PM PDT 24
Peak memory 183616 kb
Host smart-e16ccd60-1e6f-4afb-a8c6-ba0c8cc27a6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596191599 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.2596191599
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.3230192050
Short name T199
Test name
Test status
Simulation time 501244903 ps
CPU time 0.73 seconds
Started May 02 03:54:43 PM PDT 24
Finished May 02 03:54:46 PM PDT 24
Peak memory 183532 kb
Host smart-4c96694d-f6b6-4f1d-a8ad-13978b0dc4a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230192050 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.3230192050
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.298302505
Short name T10
Test name
Test status
Simulation time 102975747038 ps
CPU time 37.57 seconds
Started May 02 03:54:56 PM PDT 24
Finished May 02 03:55:36 PM PDT 24
Peak memory 183752 kb
Host smart-eac550b6-bc40-4989-a65e-0de5555d3b60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298302505 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_a
ll.298302505
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.4219506018
Short name T150
Test name
Test status
Simulation time 19977811545 ps
CPU time 218.77 seconds
Started May 02 03:54:50 PM PDT 24
Finished May 02 03:58:31 PM PDT 24
Peak memory 198492 kb
Host smart-61ecd495-9698-4da2-bf29-87ca14440443
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219506018 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.4219506018
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.aon_timer_jump.1047728446
Short name T261
Test name
Test status
Simulation time 498610671 ps
CPU time 0.59 seconds
Started May 02 03:54:46 PM PDT 24
Finished May 02 03:54:49 PM PDT 24
Peak memory 183536 kb
Host smart-4a7c35f8-73af-4f15-a538-0d04c3767482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047728446 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.1047728446
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.2919883893
Short name T103
Test name
Test status
Simulation time 31840171382 ps
CPU time 49.63 seconds
Started May 02 03:54:46 PM PDT 24
Finished May 02 03:55:38 PM PDT 24
Peak memory 183604 kb
Host smart-fda42f47-d1ad-46ab-a947-49bfdab6fe74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919883893 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.2919883893
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.1649741493
Short name T7
Test name
Test status
Simulation time 392399129 ps
CPU time 1.14 seconds
Started May 02 03:55:01 PM PDT 24
Finished May 02 03:55:04 PM PDT 24
Peak memory 183560 kb
Host smart-f4f927f1-6f27-4d9c-ab98-599cc7652d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649741493 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.1649741493
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.1848683838
Short name T156
Test name
Test status
Simulation time 35194864427 ps
CPU time 12.93 seconds
Started May 02 03:54:47 PM PDT 24
Finished May 02 03:55:03 PM PDT 24
Peak memory 194244 kb
Host smart-dd04353c-5c7b-4b19-acae-c4138bdc85b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848683838 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_
all.1848683838
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_jump.3176169475
Short name T195
Test name
Test status
Simulation time 389285531 ps
CPU time 1.08 seconds
Started May 02 03:54:48 PM PDT 24
Finished May 02 03:54:52 PM PDT 24
Peak memory 183548 kb
Host smart-20250c38-6c89-40ca-8e06-be85e45cd3b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176169475 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.3176169475
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.3926820571
Short name T205
Test name
Test status
Simulation time 23317715684 ps
CPU time 16.38 seconds
Started May 02 03:54:52 PM PDT 24
Finished May 02 03:55:12 PM PDT 24
Peak memory 183552 kb
Host smart-88e7dd7f-3a12-461f-b18d-049ed4211f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926820571 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.3926820571
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.3471006790
Short name T88
Test name
Test status
Simulation time 555604001 ps
CPU time 1.41 seconds
Started May 02 03:54:58 PM PDT 24
Finished May 02 03:55:01 PM PDT 24
Peak memory 183572 kb
Host smart-2c952a78-a2e8-482d-b8c1-6c5b5bef958c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471006790 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.3471006790
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.2893738808
Short name T239
Test name
Test status
Simulation time 49130298737 ps
CPU time 77.57 seconds
Started May 02 03:54:55 PM PDT 24
Finished May 02 03:56:15 PM PDT 24
Peak memory 183644 kb
Host smart-9469c251-4b84-493f-a848-7208943f03a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893738808 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_
all.2893738808
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.3777445466
Short name T269
Test name
Test status
Simulation time 49072732024 ps
CPU time 290.89 seconds
Started May 02 03:54:59 PM PDT 24
Finished May 02 03:59:52 PM PDT 24
Peak memory 198428 kb
Host smart-a2b15b52-c680-4b1e-bbfd-b0ad46a1f8b2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777445466 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.3777445466
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.aon_timer_jump.2438379960
Short name T115
Test name
Test status
Simulation time 437747821 ps
CPU time 1.21 seconds
Started May 02 03:54:47 PM PDT 24
Finished May 02 03:54:51 PM PDT 24
Peak memory 183536 kb
Host smart-e9c1276b-4d33-4ae7-afb5-8a945be5d6c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438379960 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.2438379960
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.2698106888
Short name T158
Test name
Test status
Simulation time 4958301822 ps
CPU time 1.9 seconds
Started May 02 03:54:46 PM PDT 24
Finished May 02 03:54:51 PM PDT 24
Peak memory 183600 kb
Host smart-1892825a-a3ee-4e81-a4ac-3e22d99c70a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698106888 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.2698106888
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.4146448058
Short name T184
Test name
Test status
Simulation time 368897575 ps
CPU time 0.64 seconds
Started May 02 03:54:51 PM PDT 24
Finished May 02 03:54:54 PM PDT 24
Peak memory 183500 kb
Host smart-e06bd418-7873-490b-ba26-a75546140a6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146448058 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.4146448058
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.2497889193
Short name T41
Test name
Test status
Simulation time 99978059571 ps
CPU time 115.62 seconds
Started May 02 03:54:44 PM PDT 24
Finished May 02 03:56:42 PM PDT 24
Peak memory 193044 kb
Host smart-8dcba463-0321-4ade-be28-c5f50289199c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497889193 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_
all.2497889193
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.2390992217
Short name T280
Test name
Test status
Simulation time 445492498614 ps
CPU time 739.03 seconds
Started May 02 03:54:52 PM PDT 24
Finished May 02 04:07:14 PM PDT 24
Peak memory 201712 kb
Host smart-6c565819-934f-4112-ba64-61dbd66b6a2d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390992217 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.2390992217
Directory /workspace/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.aon_timer_jump.1837700095
Short name T126
Test name
Test status
Simulation time 385355091 ps
CPU time 0.71 seconds
Started May 02 03:55:00 PM PDT 24
Finished May 02 03:55:03 PM PDT 24
Peak memory 183548 kb
Host smart-aa392830-5d88-481e-bb91-258be3ca6dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837700095 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.1837700095
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.3314479083
Short name T176
Test name
Test status
Simulation time 41036439290 ps
CPU time 8.5 seconds
Started May 02 03:54:53 PM PDT 24
Finished May 02 03:55:04 PM PDT 24
Peak memory 191804 kb
Host smart-42518b5a-0f05-41a9-86d2-f61ee03af062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314479083 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.3314479083
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.2453124540
Short name T21
Test name
Test status
Simulation time 537747174 ps
CPU time 0.9 seconds
Started May 02 03:54:42 PM PDT 24
Finished May 02 03:54:45 PM PDT 24
Peak memory 183528 kb
Host smart-d44e3557-1c9c-4da9-8ca5-37f50273da14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453124540 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.2453124540
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.3032258752
Short name T17
Test name
Test status
Simulation time 268842513580 ps
CPU time 132.16 seconds
Started May 02 03:54:56 PM PDT 24
Finished May 02 03:57:10 PM PDT 24
Peak memory 183632 kb
Host smart-8116195d-afd1-410e-b171-f70aea0f499a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032258752 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_
all.3032258752
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.2917263001
Short name T45
Test name
Test status
Simulation time 76904681870 ps
CPU time 170.62 seconds
Started May 02 03:54:48 PM PDT 24
Finished May 02 03:57:42 PM PDT 24
Peak memory 198496 kb
Host smart-e08a38ff-287d-4214-acec-1a51fb44a348
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917263001 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.2917263001
Directory /workspace/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_jump.1271668663
Short name T221
Test name
Test status
Simulation time 333912146 ps
CPU time 1.12 seconds
Started May 02 03:54:59 PM PDT 24
Finished May 02 03:55:03 PM PDT 24
Peak memory 183564 kb
Host smart-fa2b8788-4a15-4328-ad1d-d1faa7df5345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271668663 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.1271668663
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.1128420499
Short name T190
Test name
Test status
Simulation time 9079015594 ps
CPU time 3.33 seconds
Started May 02 03:54:49 PM PDT 24
Finished May 02 03:54:56 PM PDT 24
Peak memory 183648 kb
Host smart-948ffed8-1786-4efc-8b1c-8569368a67f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128420499 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.1128420499
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.3496979750
Short name T196
Test name
Test status
Simulation time 457376931 ps
CPU time 1.28 seconds
Started May 02 03:54:47 PM PDT 24
Finished May 02 03:54:51 PM PDT 24
Peak memory 183596 kb
Host smart-2d18dd71-33f3-426f-9352-8611c3770cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496979750 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.3496979750
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.3141911058
Short name T286
Test name
Test status
Simulation time 137141058332 ps
CPU time 200.79 seconds
Started May 02 03:54:57 PM PDT 24
Finished May 02 03:58:20 PM PDT 24
Peak memory 195476 kb
Host smart-bdcab094-0834-41ed-89f6-327568ecb298
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141911058 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_
all.3141911058
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.2575176363
Short name T229
Test name
Test status
Simulation time 285989423879 ps
CPU time 509.53 seconds
Started May 02 03:54:52 PM PDT 24
Finished May 02 04:03:25 PM PDT 24
Peak memory 198488 kb
Host smart-c5d8c006-1cb0-4ffc-b923-bc62e7bbbaab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575176363 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.2575176363
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.aon_timer_jump.2002122026
Short name T38
Test name
Test status
Simulation time 560864975 ps
CPU time 0.95 seconds
Started May 02 03:55:00 PM PDT 24
Finished May 02 03:55:03 PM PDT 24
Peak memory 183480 kb
Host smart-83ecb284-d21a-47f2-b955-39b9818de694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002122026 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.2002122026
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.1374218868
Short name T281
Test name
Test status
Simulation time 1974816126 ps
CPU time 1.31 seconds
Started May 02 03:54:54 PM PDT 24
Finished May 02 03:54:58 PM PDT 24
Peak memory 183556 kb
Host smart-d5812440-31b7-4d79-b235-0176dfce074d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374218868 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.1374218868
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.4085870174
Short name T64
Test name
Test status
Simulation time 378973933 ps
CPU time 0.72 seconds
Started May 02 03:54:51 PM PDT 24
Finished May 02 03:54:55 PM PDT 24
Peak memory 183560 kb
Host smart-d2c36bb0-a8f6-42c9-9e31-de41471c044f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085870174 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.4085870174
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.3343000403
Short name T216
Test name
Test status
Simulation time 213814999614 ps
CPU time 68 seconds
Started May 02 03:54:49 PM PDT 24
Finished May 02 03:56:00 PM PDT 24
Peak memory 195396 kb
Host smart-c01e69e5-529b-4ca5-8e56-dd926b1eaede
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343000403 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_
all.3343000403
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.1643069903
Short name T248
Test name
Test status
Simulation time 163102004470 ps
CPU time 948 seconds
Started May 02 03:54:48 PM PDT 24
Finished May 02 04:10:39 PM PDT 24
Peak memory 204104 kb
Host smart-0683ff6d-7974-48fc-9d18-a3a9cc6c4e63
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643069903 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.1643069903
Directory /workspace/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.aon_timer_jump.1977960260
Short name T258
Test name
Test status
Simulation time 492981363 ps
CPU time 1.04 seconds
Started May 02 03:54:07 PM PDT 24
Finished May 02 03:54:11 PM PDT 24
Peak memory 183572 kb
Host smart-bf2c8a4e-b189-4992-97bf-b28a8112bbf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977960260 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.1977960260
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.3732248273
Short name T137
Test name
Test status
Simulation time 59869874097 ps
CPU time 13.41 seconds
Started May 02 03:54:07 PM PDT 24
Finished May 02 03:54:24 PM PDT 24
Peak memory 183640 kb
Host smart-d5c061ad-ebba-4c29-acea-02ec7676dd47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732248273 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.3732248273
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.948093383
Short name T51
Test name
Test status
Simulation time 610309307 ps
CPU time 0.75 seconds
Started May 02 03:54:33 PM PDT 24
Finished May 02 03:54:34 PM PDT 24
Peak memory 183552 kb
Host smart-79cd0115-9cf1-43d4-b580-e7699eb6d5c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948093383 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.948093383
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.2655542560
Short name T67
Test name
Test status
Simulation time 271411043862 ps
CPU time 295.65 seconds
Started May 02 03:54:39 PM PDT 24
Finished May 02 03:59:35 PM PDT 24
Peak memory 194796 kb
Host smart-7002ef9d-ca41-46fc-97ae-4a3894325020
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655542560 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_a
ll.2655542560
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_jump.4049697594
Short name T69
Test name
Test status
Simulation time 574128030 ps
CPU time 0.77 seconds
Started May 02 03:54:31 PM PDT 24
Finished May 02 03:54:33 PM PDT 24
Peak memory 183528 kb
Host smart-2d717c7f-7f29-4964-b402-8a1078ac5c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049697594 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.4049697594
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.2946801151
Short name T174
Test name
Test status
Simulation time 24807290442 ps
CPU time 37.89 seconds
Started May 02 03:54:09 PM PDT 24
Finished May 02 03:54:50 PM PDT 24
Peak memory 183620 kb
Host smart-4e972e4d-7570-4822-b62e-7b9a0316269e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946801151 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.2946801151
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.1990969018
Short name T206
Test name
Test status
Simulation time 415565954 ps
CPU time 0.74 seconds
Started May 02 03:54:30 PM PDT 24
Finished May 02 03:54:31 PM PDT 24
Peak memory 183544 kb
Host smart-f293d923-84df-4ae5-b43d-7965107cd6b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990969018 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.1990969018
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.910749981
Short name T164
Test name
Test status
Simulation time 123236292509 ps
CPU time 193.1 seconds
Started May 02 03:54:08 PM PDT 24
Finished May 02 03:57:24 PM PDT 24
Peak memory 195124 kb
Host smart-a1bc56bf-ab87-4aaf-bcb9-0dcb5c88f9ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910749981 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_al
l.910749981
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.2579733871
Short name T29
Test name
Test status
Simulation time 35108133323 ps
CPU time 140.53 seconds
Started May 02 03:54:31 PM PDT 24
Finished May 02 03:56:52 PM PDT 24
Peak memory 198476 kb
Host smart-048e5d48-60fd-4211-b862-07317cd7ec34
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579733871 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.2579733871
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.aon_timer_jump.784605081
Short name T214
Test name
Test status
Simulation time 541041692 ps
CPU time 1.44 seconds
Started May 02 03:54:06 PM PDT 24
Finished May 02 03:54:11 PM PDT 24
Peak memory 183532 kb
Host smart-5710710a-eabc-40c3-9e00-fc6235ef32b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784605081 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.784605081
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.1870767362
Short name T257
Test name
Test status
Simulation time 40449946691 ps
CPU time 16.63 seconds
Started May 02 03:54:09 PM PDT 24
Finished May 02 03:54:29 PM PDT 24
Peak memory 191804 kb
Host smart-1cf9f83b-85bb-4c02-9389-4760488171a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870767362 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.1870767362
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.492124737
Short name T265
Test name
Test status
Simulation time 454024627 ps
CPU time 0.72 seconds
Started May 02 03:54:09 PM PDT 24
Finished May 02 03:54:13 PM PDT 24
Peak memory 183556 kb
Host smart-3a32c8c2-fdee-44d0-8a6a-b83d18eb1e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492124737 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.492124737
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.1463512470
Short name T160
Test name
Test status
Simulation time 97858061148 ps
CPU time 138.95 seconds
Started May 02 03:54:40 PM PDT 24
Finished May 02 03:57:00 PM PDT 24
Peak memory 183752 kb
Host smart-1a1aef22-f911-40c6-bb90-0b9c224b2766
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463512470 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_a
ll.1463512470
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.787611843
Short name T142
Test name
Test status
Simulation time 91564605129 ps
CPU time 782.11 seconds
Started May 02 03:54:32 PM PDT 24
Finished May 02 04:07:35 PM PDT 24
Peak memory 201260 kb
Host smart-2b2b726b-c89b-4056-b19d-99a99555f807
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787611843 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.787611843
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.aon_timer_jump.1409524152
Short name T39
Test name
Test status
Simulation time 498589593 ps
CPU time 1.18 seconds
Started May 02 03:54:11 PM PDT 24
Finished May 02 03:54:14 PM PDT 24
Peak memory 183540 kb
Host smart-cca4e3cc-eeee-407b-9b59-01640157b671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409524152 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.1409524152
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.2478079373
Short name T244
Test name
Test status
Simulation time 18728335661 ps
CPU time 8.52 seconds
Started May 02 03:54:27 PM PDT 24
Finished May 02 03:54:36 PM PDT 24
Peak memory 183640 kb
Host smart-c9e03029-3d3d-408e-ba19-f0f6a6c559a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478079373 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.2478079373
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.1582660280
Short name T202
Test name
Test status
Simulation time 456449354 ps
CPU time 0.63 seconds
Started May 02 03:54:42 PM PDT 24
Finished May 02 03:54:45 PM PDT 24
Peak memory 183556 kb
Host smart-caaf58f1-9419-4ac2-afdc-a4d77666ef8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582660280 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.1582660280
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.179187537
Short name T48
Test name
Test status
Simulation time 39417820594 ps
CPU time 14.1 seconds
Started May 02 03:54:30 PM PDT 24
Finished May 02 03:54:45 PM PDT 24
Peak memory 183656 kb
Host smart-69f00d6a-f600-4efc-bdab-f049d27daacb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179187537 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_al
l.179187537
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.482015789
Short name T96
Test name
Test status
Simulation time 123330608155 ps
CPU time 479.16 seconds
Started May 02 03:54:27 PM PDT 24
Finished May 02 04:02:27 PM PDT 24
Peak memory 198408 kb
Host smart-102efda1-dea5-4999-aafe-fd15531c3391
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482015789 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.482015789
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.aon_timer_jump.204348391
Short name T189
Test name
Test status
Simulation time 453260123 ps
CPU time 0.77 seconds
Started May 02 03:54:11 PM PDT 24
Finished May 02 03:54:14 PM PDT 24
Peak memory 183532 kb
Host smart-62616af5-1c90-46be-a826-713e69b2d842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204348391 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.204348391
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.2334410936
Short name T252
Test name
Test status
Simulation time 35908254755 ps
CPU time 7.51 seconds
Started May 02 03:54:37 PM PDT 24
Finished May 02 03:54:45 PM PDT 24
Peak memory 183592 kb
Host smart-98c28aeb-6808-4680-92e7-f8e43f1454f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334410936 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.2334410936
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.1144708344
Short name T113
Test name
Test status
Simulation time 572144435 ps
CPU time 0.7 seconds
Started May 02 03:54:14 PM PDT 24
Finished May 02 03:54:16 PM PDT 24
Peak memory 183556 kb
Host smart-adc76ee4-b8dd-4447-b086-f6760847e8d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144708344 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.1144708344
Directory /workspace/9.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.1304462305
Short name T271
Test name
Test status
Simulation time 12975132750 ps
CPU time 23.22 seconds
Started May 02 03:54:28 PM PDT 24
Finished May 02 03:54:52 PM PDT 24
Peak memory 183596 kb
Host smart-47d67d09-944b-45b0-8d63-1e5f8e0de5dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304462305 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_a
ll.1304462305
Directory /workspace/9.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.3222665360
Short name T100
Test name
Test status
Simulation time 12659365026 ps
CPU time 87.44 seconds
Started May 02 03:54:12 PM PDT 24
Finished May 02 03:55:41 PM PDT 24
Peak memory 198540 kb
Host smart-da94fc5a-47d9-40fe-9d34-7159d3293bcb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222665360 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.3222665360
Directory /workspace/9.aon_timer_stress_all_with_rand_reset/latest
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