Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
92.98 99.25 93.67 100.00 98.40 99.51 67.06


Total test records in report: 420
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T72 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.1526834826 May 05 01:22:20 PM PDT 24 May 05 01:22:22 PM PDT 24 904737880 ps
T98 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.703509369 May 05 01:22:01 PM PDT 24 May 05 01:22:02 PM PDT 24 418139340 ps
T279 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.899127267 May 05 01:21:51 PM PDT 24 May 05 01:21:53 PM PDT 24 871127907 ps
T36 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.103689635 May 05 01:22:26 PM PDT 24 May 05 01:22:31 PM PDT 24 8574908961 ps
T48 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.2440175110 May 05 01:21:49 PM PDT 24 May 05 01:21:55 PM PDT 24 7626558079 ps
T37 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.4293114696 May 05 01:21:50 PM PDT 24 May 05 01:21:57 PM PDT 24 7766890479 ps
T73 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.1707773942 May 05 01:22:23 PM PDT 24 May 05 01:22:24 PM PDT 24 433714291 ps
T38 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.1346031831 May 05 01:22:15 PM PDT 24 May 05 01:22:23 PM PDT 24 8442875806 ps
T280 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.469604400 May 05 01:22:34 PM PDT 24 May 05 01:22:36 PM PDT 24 509938241 ps
T74 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.3790845388 May 05 01:22:12 PM PDT 24 May 05 01:22:14 PM PDT 24 1242488630 ps
T281 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.471010984 May 05 01:21:50 PM PDT 24 May 05 01:21:52 PM PDT 24 273015215 ps
T282 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.657425993 May 05 01:21:56 PM PDT 24 May 05 01:21:58 PM PDT 24 478442875 ps
T283 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.963763836 May 05 01:22:33 PM PDT 24 May 05 01:22:34 PM PDT 24 354387539 ps
T49 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.2083895035 May 05 01:22:15 PM PDT 24 May 05 01:22:17 PM PDT 24 324187708 ps
T284 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.3762545477 May 05 01:21:50 PM PDT 24 May 05 01:21:51 PM PDT 24 390242219 ps
T285 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.1421373749 May 05 01:21:57 PM PDT 24 May 05 01:21:58 PM PDT 24 410838126 ps
T75 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.3727572188 May 05 01:22:10 PM PDT 24 May 05 01:22:15 PM PDT 24 2360440572 ps
T286 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.1675655597 May 05 01:21:57 PM PDT 24 May 05 01:21:58 PM PDT 24 536073830 ps
T287 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.4041875719 May 05 01:22:00 PM PDT 24 May 05 01:22:02 PM PDT 24 308783318 ps
T50 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.2015716624 May 05 01:22:24 PM PDT 24 May 05 01:22:25 PM PDT 24 405097806 ps
T288 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.1919666835 May 05 01:21:47 PM PDT 24 May 05 01:21:48 PM PDT 24 344311922 ps
T51 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.2153229181 May 05 01:21:57 PM PDT 24 May 05 01:21:58 PM PDT 24 575921169 ps
T289 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.2563236877 May 05 01:21:55 PM PDT 24 May 05 01:21:57 PM PDT 24 743125385 ps
T97 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.3903966183 May 05 01:22:05 PM PDT 24 May 05 01:22:16 PM PDT 24 8064583726 ps
T52 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.1536767683 May 05 01:22:00 PM PDT 24 May 05 01:22:18 PM PDT 24 12046795760 ps
T290 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.2712400313 May 05 01:22:37 PM PDT 24 May 05 01:22:38 PM PDT 24 393382162 ps
T53 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.2779604675 May 05 01:21:47 PM PDT 24 May 05 01:21:49 PM PDT 24 552279960 ps
T54 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.1376254884 May 05 01:22:25 PM PDT 24 May 05 01:22:26 PM PDT 24 730687951 ps
T291 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.284941291 May 05 01:22:25 PM PDT 24 May 05 01:22:27 PM PDT 24 722363513 ps
T292 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.4210723741 May 05 01:22:00 PM PDT 24 May 05 01:22:14 PM PDT 24 8086841210 ps
T293 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.937128476 May 05 01:22:33 PM PDT 24 May 05 01:22:34 PM PDT 24 504738947 ps
T294 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.2873396044 May 05 01:22:31 PM PDT 24 May 05 01:22:32 PM PDT 24 298992186 ps
T295 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.3164260248 May 05 01:21:55 PM PDT 24 May 05 01:21:56 PM PDT 24 579418463 ps
T296 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.3549427522 May 05 01:22:30 PM PDT 24 May 05 01:22:33 PM PDT 24 452599407 ps
T297 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.1884558478 May 05 01:22:34 PM PDT 24 May 05 01:22:35 PM PDT 24 357349580 ps
T298 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.3658024658 May 05 01:22:31 PM PDT 24 May 05 01:22:32 PM PDT 24 429258042 ps
T299 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.4228242522 May 05 01:22:33 PM PDT 24 May 05 01:22:34 PM PDT 24 460804941 ps
T300 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.2232946297 May 05 01:22:20 PM PDT 24 May 05 01:22:23 PM PDT 24 992997264 ps
T301 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.2911755756 May 05 01:22:27 PM PDT 24 May 05 01:22:28 PM PDT 24 543420108 ps
T76 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.2683629510 May 05 01:21:56 PM PDT 24 May 05 01:22:01 PM PDT 24 2561119401 ps
T302 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.55010636 May 05 01:22:22 PM PDT 24 May 05 01:22:24 PM PDT 24 502877792 ps
T303 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.3259187561 May 05 01:21:54 PM PDT 24 May 05 01:21:59 PM PDT 24 7067523806 ps
T304 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.178578401 May 05 01:22:01 PM PDT 24 May 05 01:22:02 PM PDT 24 395572959 ps
T305 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.2664937248 May 05 01:22:22 PM PDT 24 May 05 01:22:23 PM PDT 24 429226529 ps
T77 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.943041896 May 05 01:21:55 PM PDT 24 May 05 01:21:57 PM PDT 24 2239887135 ps
T306 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.1099352590 May 05 01:22:21 PM PDT 24 May 05 01:22:22 PM PDT 24 375690791 ps
T307 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.505625838 May 05 01:22:20 PM PDT 24 May 05 01:22:23 PM PDT 24 4827197366 ps
T57 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.2356792122 May 05 01:21:59 PM PDT 24 May 05 01:22:03 PM PDT 24 4313947701 ps
T308 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.167665496 May 05 01:21:51 PM PDT 24 May 05 01:21:53 PM PDT 24 4719538559 ps
T309 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.1053514613 May 05 01:22:35 PM PDT 24 May 05 01:22:36 PM PDT 24 406963611 ps
T310 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.324890725 May 05 01:22:20 PM PDT 24 May 05 01:22:22 PM PDT 24 467675997 ps
T58 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.1299692856 May 05 01:22:04 PM PDT 24 May 05 01:22:05 PM PDT 24 384957875 ps
T311 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.2947700626 May 05 01:22:11 PM PDT 24 May 05 01:22:14 PM PDT 24 9115056553 ps
T312 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.2543953905 May 05 01:22:36 PM PDT 24 May 05 01:22:38 PM PDT 24 298415155 ps
T313 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.4159882019 May 05 01:22:21 PM PDT 24 May 05 01:22:22 PM PDT 24 517386647 ps
T314 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.1524511 May 05 01:22:36 PM PDT 24 May 05 01:22:37 PM PDT 24 275450328 ps
T315 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.1997027789 May 05 01:22:28 PM PDT 24 May 05 01:22:29 PM PDT 24 280614822 ps
T316 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.1300389062 May 05 01:22:00 PM PDT 24 May 05 01:22:01 PM PDT 24 492309688 ps
T78 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.3108591339 May 05 01:22:11 PM PDT 24 May 05 01:22:12 PM PDT 24 544091452 ps
T317 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.3756248034 May 05 01:22:24 PM PDT 24 May 05 01:22:25 PM PDT 24 495026684 ps
T79 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.1814460514 May 05 01:22:28 PM PDT 24 May 05 01:22:32 PM PDT 24 1482652702 ps
T318 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.3414447969 May 05 01:22:36 PM PDT 24 May 05 01:22:37 PM PDT 24 445462183 ps
T319 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.3515893666 May 05 01:22:24 PM PDT 24 May 05 01:22:26 PM PDT 24 288552244 ps
T320 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.1237278164 May 05 01:22:04 PM PDT 24 May 05 01:22:06 PM PDT 24 429834925 ps
T321 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.1154881606 May 05 01:22:10 PM PDT 24 May 05 01:22:12 PM PDT 24 322676405 ps
T322 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.4278136991 May 05 01:22:31 PM PDT 24 May 05 01:22:33 PM PDT 24 332305707 ps
T323 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.168399668 May 05 01:22:28 PM PDT 24 May 05 01:22:29 PM PDT 24 546311578 ps
T324 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.1566354798 May 05 01:22:33 PM PDT 24 May 05 01:22:35 PM PDT 24 298881625 ps
T325 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.3235242344 May 05 01:21:57 PM PDT 24 May 05 01:21:59 PM PDT 24 439473948 ps
T326 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.4197273630 May 05 01:21:46 PM PDT 24 May 05 01:21:48 PM PDT 24 561340943 ps
T327 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.325592849 May 05 01:22:35 PM PDT 24 May 05 01:22:36 PM PDT 24 413631010 ps
T328 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.221743909 May 05 01:21:47 PM PDT 24 May 05 01:21:49 PM PDT 24 2372297052 ps
T329 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.177282545 May 05 01:22:11 PM PDT 24 May 05 01:22:23 PM PDT 24 7356534223 ps
T330 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.181563851 May 05 01:22:34 PM PDT 24 May 05 01:22:35 PM PDT 24 503654742 ps
T331 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.788083500 May 05 01:22:16 PM PDT 24 May 05 01:22:20 PM PDT 24 3004355114 ps
T332 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.1924375162 May 05 01:22:33 PM PDT 24 May 05 01:22:34 PM PDT 24 350730764 ps
T333 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.2335022094 May 05 01:22:27 PM PDT 24 May 05 01:22:28 PM PDT 24 675191014 ps
T334 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.403712715 May 05 01:21:55 PM PDT 24 May 05 01:22:00 PM PDT 24 8183035722 ps
T335 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.1149345227 May 05 01:22:11 PM PDT 24 May 05 01:22:12 PM PDT 24 273130218 ps
T336 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.925840256 May 05 01:22:31 PM PDT 24 May 05 01:22:33 PM PDT 24 1483639044 ps
T337 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.780295202 May 05 01:22:26 PM PDT 24 May 05 01:22:28 PM PDT 24 525432880 ps
T59 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.1450697371 May 05 01:21:46 PM PDT 24 May 05 01:21:51 PM PDT 24 7911804036 ps
T338 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.1557515616 May 05 01:22:30 PM PDT 24 May 05 01:22:34 PM PDT 24 8541286128 ps
T339 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.1784548892 May 05 01:21:48 PM PDT 24 May 05 01:21:50 PM PDT 24 1105968617 ps
T340 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.2360412230 May 05 01:22:15 PM PDT 24 May 05 01:22:19 PM PDT 24 2895713658 ps
T341 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.3307969347 May 05 01:22:37 PM PDT 24 May 05 01:22:38 PM PDT 24 362166672 ps
T71 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.3141743790 May 05 01:22:04 PM PDT 24 May 05 01:22:05 PM PDT 24 403918960 ps
T342 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.2112427439 May 05 01:22:18 PM PDT 24 May 05 01:22:20 PM PDT 24 549175446 ps
T343 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.2538785509 May 05 01:21:48 PM PDT 24 May 05 01:22:01 PM PDT 24 7983406810 ps
T344 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.3355738813 May 05 01:21:59 PM PDT 24 May 05 01:22:00 PM PDT 24 540747689 ps
T345 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.1553376262 May 05 01:22:00 PM PDT 24 May 05 01:22:01 PM PDT 24 340788095 ps
T346 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.2470090502 May 05 01:22:02 PM PDT 24 May 05 01:22:03 PM PDT 24 525196201 ps
T55 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.2440146052 May 05 01:22:00 PM PDT 24 May 05 01:22:03 PM PDT 24 1144971780 ps
T347 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.3135913100 May 05 01:22:30 PM PDT 24 May 05 01:22:31 PM PDT 24 1594771126 ps
T348 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.2857505273 May 05 01:22:01 PM PDT 24 May 05 01:22:06 PM PDT 24 8800513194 ps
T349 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.1324251845 May 05 01:22:23 PM PDT 24 May 05 01:22:25 PM PDT 24 1195972101 ps
T56 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.2442589049 May 05 01:22:16 PM PDT 24 May 05 01:22:17 PM PDT 24 353344389 ps
T350 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.3753988510 May 05 01:22:32 PM PDT 24 May 05 01:22:33 PM PDT 24 468569897 ps
T351 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.3704478171 May 05 01:22:20 PM PDT 24 May 05 01:22:22 PM PDT 24 455007609 ps
T60 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.2383210487 May 05 01:22:30 PM PDT 24 May 05 01:22:31 PM PDT 24 320277174 ps
T352 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.1990297394 May 05 01:22:12 PM PDT 24 May 05 01:22:14 PM PDT 24 273549754 ps
T353 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.3566522186 May 05 01:21:46 PM PDT 24 May 05 01:21:48 PM PDT 24 432074669 ps
T61 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.1927237852 May 05 01:21:55 PM PDT 24 May 05 01:21:56 PM PDT 24 633176494 ps
T354 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.2462270041 May 05 01:22:06 PM PDT 24 May 05 01:22:07 PM PDT 24 399964735 ps
T355 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.1249104218 May 05 01:22:17 PM PDT 24 May 05 01:22:19 PM PDT 24 350011118 ps
T356 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.33745621 May 05 01:22:20 PM PDT 24 May 05 01:22:22 PM PDT 24 484904292 ps
T357 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.2029327722 May 05 01:21:53 PM PDT 24 May 05 01:21:53 PM PDT 24 345879445 ps
T358 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.3595577860 May 05 01:22:26 PM PDT 24 May 05 01:22:28 PM PDT 24 381161742 ps
T359 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.3711918080 May 05 01:22:24 PM PDT 24 May 05 01:22:25 PM PDT 24 530975140 ps
T360 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.2901180315 May 05 01:21:51 PM PDT 24 May 05 01:21:52 PM PDT 24 389063592 ps
T361 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.3802598944 May 05 01:21:49 PM PDT 24 May 05 01:21:53 PM PDT 24 1971872050 ps
T362 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.3553012237 May 05 01:22:30 PM PDT 24 May 05 01:22:32 PM PDT 24 474306818 ps
T363 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.1604262589 May 05 01:22:00 PM PDT 24 May 05 01:22:02 PM PDT 24 288862830 ps
T364 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.2870331810 May 05 01:22:11 PM PDT 24 May 05 01:22:13 PM PDT 24 506080111 ps
T365 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.2142289100 May 05 01:22:24 PM PDT 24 May 05 01:22:32 PM PDT 24 7513351675 ps
T366 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.3015825005 May 05 01:22:31 PM PDT 24 May 05 01:22:45 PM PDT 24 7873773321 ps
T367 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.3556212342 May 05 01:21:55 PM PDT 24 May 05 01:21:57 PM PDT 24 422190049 ps
T368 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.850466600 May 05 01:21:51 PM PDT 24 May 05 01:21:53 PM PDT 24 606297613 ps
T369 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.824508106 May 05 01:22:02 PM PDT 24 May 05 01:22:03 PM PDT 24 360535434 ps
T370 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.2794501901 May 05 01:21:47 PM PDT 24 May 05 01:21:48 PM PDT 24 332909911 ps
T371 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.976333069 May 05 01:22:25 PM PDT 24 May 05 01:22:26 PM PDT 24 297082998 ps
T372 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.2396527209 May 05 01:22:14 PM PDT 24 May 05 01:22:17 PM PDT 24 411786308 ps
T373 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.3298596836 May 05 01:22:35 PM PDT 24 May 05 01:22:36 PM PDT 24 517068886 ps
T374 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.538697181 May 05 01:22:30 PM PDT 24 May 05 01:22:31 PM PDT 24 417690435 ps
T375 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.1643255669 May 05 01:21:48 PM PDT 24 May 05 01:21:50 PM PDT 24 369506200 ps
T376 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.135570592 May 05 01:22:12 PM PDT 24 May 05 01:22:13 PM PDT 24 558015442 ps
T377 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.1169694715 May 05 01:22:32 PM PDT 24 May 05 01:22:35 PM PDT 24 351244714 ps
T378 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.1912539210 May 05 01:22:19 PM PDT 24 May 05 01:22:21 PM PDT 24 540126047 ps
T379 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.1895907565 May 05 01:22:04 PM PDT 24 May 05 01:22:07 PM PDT 24 421359780 ps
T380 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.198261520 May 05 01:21:49 PM PDT 24 May 05 01:21:50 PM PDT 24 465816327 ps
T381 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.1729096909 May 05 01:21:57 PM PDT 24 May 05 01:21:59 PM PDT 24 486560516 ps
T382 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.1792697260 May 05 01:22:32 PM PDT 24 May 05 01:22:34 PM PDT 24 452813837 ps
T383 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.2329569092 May 05 01:22:34 PM PDT 24 May 05 01:22:35 PM PDT 24 505566140 ps
T384 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.2214329555 May 05 01:22:30 PM PDT 24 May 05 01:22:31 PM PDT 24 276436052 ps
T385 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.3271672195 May 05 01:21:46 PM PDT 24 May 05 01:21:47 PM PDT 24 420438684 ps
T386 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.3090329382 May 05 01:22:10 PM PDT 24 May 05 01:22:13 PM PDT 24 354549521 ps
T387 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.1817895398 May 05 01:22:20 PM PDT 24 May 05 01:22:23 PM PDT 24 518130924 ps
T388 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.614662575 May 05 01:21:50 PM PDT 24 May 05 01:21:51 PM PDT 24 326878636 ps
T389 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.2313408620 May 05 01:21:54 PM PDT 24 May 05 01:21:56 PM PDT 24 1253469179 ps
T390 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.3499578265 May 05 01:21:49 PM PDT 24 May 05 01:21:51 PM PDT 24 354359192 ps
T391 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.2086937486 May 05 01:22:27 PM PDT 24 May 05 01:22:31 PM PDT 24 4163474097 ps
T392 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.1579418251 May 05 01:22:19 PM PDT 24 May 05 01:22:21 PM PDT 24 1550101376 ps
T393 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.3799580100 May 05 01:21:59 PM PDT 24 May 05 01:22:03 PM PDT 24 1826381329 ps
T394 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.1505443784 May 05 01:22:29 PM PDT 24 May 05 01:22:31 PM PDT 24 565350937 ps
T395 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.988397372 May 05 01:22:35 PM PDT 24 May 05 01:22:37 PM PDT 24 427422474 ps
T396 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.1404069471 May 05 01:22:20 PM PDT 24 May 05 01:22:22 PM PDT 24 533977415 ps
T397 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.760266780 May 05 01:22:25 PM PDT 24 May 05 01:22:26 PM PDT 24 963542643 ps
T398 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.2253056719 May 05 01:22:27 PM PDT 24 May 05 01:22:32 PM PDT 24 2796350571 ps
T399 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.589678930 May 05 01:21:46 PM PDT 24 May 05 01:21:47 PM PDT 24 412690869 ps
T400 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.3077242964 May 05 01:22:20 PM PDT 24 May 05 01:22:22 PM PDT 24 1590701883 ps
T401 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.1204642553 May 05 01:22:27 PM PDT 24 May 05 01:22:30 PM PDT 24 389137849 ps
T402 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.3630606164 May 05 01:22:26 PM PDT 24 May 05 01:22:28 PM PDT 24 1389806717 ps
T403 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.2007211520 May 05 01:22:16 PM PDT 24 May 05 01:22:17 PM PDT 24 500135834 ps
T404 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.3079989957 May 05 01:22:10 PM PDT 24 May 05 01:22:12 PM PDT 24 619474911 ps
T405 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.1910938054 May 05 01:22:30 PM PDT 24 May 05 01:22:31 PM PDT 24 488905303 ps
T406 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.2177176237 May 05 01:22:21 PM PDT 24 May 05 01:22:23 PM PDT 24 8947740243 ps
T407 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.2722777169 May 05 01:22:36 PM PDT 24 May 05 01:22:38 PM PDT 24 471829341 ps
T408 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.1540004149 May 05 01:22:20 PM PDT 24 May 05 01:22:35 PM PDT 24 8287643877 ps
T409 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.1942267405 May 05 01:22:36 PM PDT 24 May 05 01:22:38 PM PDT 24 436227774 ps
T410 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.3192551683 May 05 01:22:14 PM PDT 24 May 05 01:22:19 PM PDT 24 4367946683 ps
T411 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.926021908 May 05 01:22:16 PM PDT 24 May 05 01:22:17 PM PDT 24 417530688 ps
T412 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.1407281754 May 05 01:21:57 PM PDT 24 May 05 01:21:58 PM PDT 24 442207530 ps
T413 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.1830328260 May 05 01:22:20 PM PDT 24 May 05 01:22:21 PM PDT 24 418287823 ps
T414 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.38307181 May 05 01:22:00 PM PDT 24 May 05 01:22:03 PM PDT 24 2599684575 ps
T415 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.4226757203 May 05 01:22:00 PM PDT 24 May 05 01:22:02 PM PDT 24 405941732 ps
T416 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.2701504395 May 05 01:22:36 PM PDT 24 May 05 01:22:38 PM PDT 24 523892092 ps
T417 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.281926078 May 05 01:22:31 PM PDT 24 May 05 01:22:35 PM PDT 24 8719136326 ps
T418 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.1893006718 May 05 01:22:28 PM PDT 24 May 05 01:22:30 PM PDT 24 614746948 ps
T419 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.3845088430 May 05 01:22:33 PM PDT 24 May 05 01:22:35 PM PDT 24 379924323 ps
T420 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.4115901342 May 05 01:22:36 PM PDT 24 May 05 01:22:38 PM PDT 24 353813360 ps

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.3253123778
Short name T10
Test name
Test status
Simulation time 151193977705 ps
CPU time 298.39 seconds
Started May 05 01:09:02 PM PDT 24
Finished May 05 01:14:01 PM PDT 24
Peak memory 198472 kb
Host smart-6149f0b1-1bce-4228-b512-988b47f400c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253123778 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.3253123778
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.103689635
Short name T36
Test name
Test status
Simulation time 8574908961 ps
CPU time 4.59 seconds
Started May 05 01:22:26 PM PDT 24
Finished May 05 01:22:31 PM PDT 24
Peak memory 197952 kb
Host smart-bb2182b9-ba7f-42f7-9c9c-0e6986066be9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103689635 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl
_intg_err.103689635
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.386984324
Short name T45
Test name
Test status
Simulation time 63715710769 ps
CPU time 524.54 seconds
Started May 05 01:08:39 PM PDT 24
Finished May 05 01:17:24 PM PDT 24
Peak memory 198452 kb
Host smart-439b1d6f-196e-48d0-8529-44de220c79e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386984324 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.386984324
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.2905860819
Short name T1
Test name
Test status
Simulation time 21030319939 ps
CPU time 126.85 seconds
Started May 05 01:09:12 PM PDT 24
Finished May 05 01:11:19 PM PDT 24
Peak memory 198344 kb
Host smart-07b585e5-5a0a-4fb1-8b67-60b6dc9a6d9b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905860819 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.2905860819
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.3856945248
Short name T17
Test name
Test status
Simulation time 7713036930 ps
CPU time 4.17 seconds
Started May 05 01:08:15 PM PDT 24
Finished May 05 01:08:19 PM PDT 24
Peak memory 215124 kb
Host smart-36d810c4-fa4f-4ec8-aaf0-daaaf6f8c4ec
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856945248 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.3856945248
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.1097243056
Short name T2
Test name
Test status
Simulation time 62818952877 ps
CPU time 106.4 seconds
Started May 05 01:09:19 PM PDT 24
Finished May 05 01:11:06 PM PDT 24
Peak memory 183204 kb
Host smart-3927861c-bc1d-4cdd-8224-81a0353f5093
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097243056 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_
all.1097243056
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.2779604675
Short name T53
Test name
Test status
Simulation time 552279960 ps
CPU time 1.11 seconds
Started May 05 01:21:47 PM PDT 24
Finished May 05 01:21:49 PM PDT 24
Peak memory 193116 kb
Host smart-bfadc319-4375-4598-89c3-5c5b01ccf06c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779604675 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_a
liasing.2779604675
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.806530834
Short name T127
Test name
Test status
Simulation time 118171545831 ps
CPU time 330.23 seconds
Started May 05 01:08:44 PM PDT 24
Finished May 05 01:14:15 PM PDT 24
Peak memory 198432 kb
Host smart-28a616c3-5d22-4243-ac89-4f9c3aad303f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806530834 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.806530834
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.2083895035
Short name T49
Test name
Test status
Simulation time 324187708 ps
CPU time 1.07 seconds
Started May 05 01:22:15 PM PDT 24
Finished May 05 01:22:17 PM PDT 24
Peak memory 193048 kb
Host smart-82986c40-4ab3-44dc-8b57-7f576e69d1f8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083895035 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.2083895035
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.1450697371
Short name T59
Test name
Test status
Simulation time 7911804036 ps
CPU time 4.34 seconds
Started May 05 01:21:46 PM PDT 24
Finished May 05 01:21:51 PM PDT 24
Peak memory 192160 kb
Host smart-27130d19-a4ff-46bb-afca-69573d2519b2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450697371 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_b
it_bash.1450697371
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.1784548892
Short name T339
Test name
Test status
Simulation time 1105968617 ps
CPU time 1.41 seconds
Started May 05 01:21:48 PM PDT 24
Finished May 05 01:21:50 PM PDT 24
Peak memory 183616 kb
Host smart-9747de99-ac0a-4770-ab15-b6a62d1e1ef7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784548892 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_h
w_reset.1784548892
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.3271672195
Short name T385
Test name
Test status
Simulation time 420438684 ps
CPU time 0.7 seconds
Started May 05 01:21:46 PM PDT 24
Finished May 05 01:21:47 PM PDT 24
Peak memory 195804 kb
Host smart-324c7d03-e3d3-4826-b9d2-625d9974986e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271672195 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.3271672195
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.2794501901
Short name T370
Test name
Test status
Simulation time 332909911 ps
CPU time 1.11 seconds
Started May 05 01:21:47 PM PDT 24
Finished May 05 01:21:48 PM PDT 24
Peak memory 192972 kb
Host smart-a96bfe58-bbe8-4c2c-b11b-fc866995c81b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794501901 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.2794501901
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.1643255669
Short name T375
Test name
Test status
Simulation time 369506200 ps
CPU time 1.1 seconds
Started May 05 01:21:48 PM PDT 24
Finished May 05 01:21:50 PM PDT 24
Peak memory 183524 kb
Host smart-d9440b3d-c96c-435d-a313-136c299dc0cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643255669 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.1643255669
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.1919666835
Short name T288
Test name
Test status
Simulation time 344311922 ps
CPU time 0.59 seconds
Started May 05 01:21:47 PM PDT 24
Finished May 05 01:21:48 PM PDT 24
Peak memory 183480 kb
Host smart-266bc66f-142f-456a-ad8c-4d312901a727
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919666835 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_t
imer_mem_partial_access.1919666835
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.589678930
Short name T399
Test name
Test status
Simulation time 412690869 ps
CPU time 0.75 seconds
Started May 05 01:21:46 PM PDT 24
Finished May 05 01:21:47 PM PDT 24
Peak memory 183532 kb
Host smart-df0019ee-747c-446d-898f-056ce10d7813
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589678930 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_wa
lk.589678930
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.221743909
Short name T328
Test name
Test status
Simulation time 2372297052 ps
CPU time 2.35 seconds
Started May 05 01:21:47 PM PDT 24
Finished May 05 01:21:49 PM PDT 24
Peak memory 194600 kb
Host smart-e0371b87-d1b8-432a-807b-b68de6b15ef2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221743909 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_
timer_same_csr_outstanding.221743909
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.4197273630
Short name T326
Test name
Test status
Simulation time 561340943 ps
CPU time 2.21 seconds
Started May 05 01:21:46 PM PDT 24
Finished May 05 01:21:48 PM PDT 24
Peak memory 198472 kb
Host smart-e544b219-bd66-4541-9657-9470ed64f723
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197273630 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.4197273630
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.2538785509
Short name T343
Test name
Test status
Simulation time 7983406810 ps
CPU time 13.48 seconds
Started May 05 01:21:48 PM PDT 24
Finished May 05 01:22:01 PM PDT 24
Peak memory 197884 kb
Host smart-53aab045-19b4-46e1-b695-ec2c737cfb91
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538785509 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl
_intg_err.2538785509
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.850466600
Short name T368
Test name
Test status
Simulation time 606297613 ps
CPU time 1.57 seconds
Started May 05 01:21:51 PM PDT 24
Finished May 05 01:21:53 PM PDT 24
Peak memory 183656 kb
Host smart-8a12af47-af98-4881-b771-0f28b810fc21
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850466600 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_al
iasing.850466600
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.2440175110
Short name T48
Test name
Test status
Simulation time 7626558079 ps
CPU time 4.81 seconds
Started May 05 01:21:49 PM PDT 24
Finished May 05 01:21:55 PM PDT 24
Peak memory 192104 kb
Host smart-61d978cf-843f-48da-9010-79ebb25eb808
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440175110 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_b
it_bash.2440175110
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.2623887803
Short name T39
Test name
Test status
Simulation time 896532822 ps
CPU time 1.49 seconds
Started May 05 01:21:50 PM PDT 24
Finished May 05 01:21:52 PM PDT 24
Peak memory 183676 kb
Host smart-05166151-ad03-44fb-adee-6e43a9401049
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623887803 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_h
w_reset.2623887803
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.3499578265
Short name T390
Test name
Test status
Simulation time 354359192 ps
CPU time 0.89 seconds
Started May 05 01:21:49 PM PDT 24
Finished May 05 01:21:51 PM PDT 24
Peak memory 195080 kb
Host smart-513267d0-461b-465c-9085-521c655d3420
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499578265 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.3499578265
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.614662575
Short name T388
Test name
Test status
Simulation time 326878636 ps
CPU time 0.78 seconds
Started May 05 01:21:50 PM PDT 24
Finished May 05 01:21:51 PM PDT 24
Peak memory 192916 kb
Host smart-50ec04af-b96c-40eb-beee-12b514a181cf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614662575 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.614662575
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.198261520
Short name T380
Test name
Test status
Simulation time 465816327 ps
CPU time 1.3 seconds
Started May 05 01:21:49 PM PDT 24
Finished May 05 01:21:50 PM PDT 24
Peak memory 183532 kb
Host smart-5726c753-87e3-4fe4-8209-8d1109a7485e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198261520 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.198261520
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.2901180315
Short name T360
Test name
Test status
Simulation time 389063592 ps
CPU time 0.65 seconds
Started May 05 01:21:51 PM PDT 24
Finished May 05 01:21:52 PM PDT 24
Peak memory 183464 kb
Host smart-e9a01098-96d3-415d-93b6-ec7db7cb235d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901180315 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_t
imer_mem_partial_access.2901180315
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.471010984
Short name T281
Test name
Test status
Simulation time 273015215 ps
CPU time 0.96 seconds
Started May 05 01:21:50 PM PDT 24
Finished May 05 01:21:52 PM PDT 24
Peak memory 183472 kb
Host smart-72d512b4-2387-43c5-8535-a1d643a16055
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471010984 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_wa
lk.471010984
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.3802598944
Short name T361
Test name
Test status
Simulation time 1971872050 ps
CPU time 3.16 seconds
Started May 05 01:21:49 PM PDT 24
Finished May 05 01:21:53 PM PDT 24
Peak memory 194140 kb
Host smart-249db391-111d-4025-a1bc-470654e845c0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802598944 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon
_timer_same_csr_outstanding.3802598944
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.3566522186
Short name T353
Test name
Test status
Simulation time 432074669 ps
CPU time 1.58 seconds
Started May 05 01:21:46 PM PDT 24
Finished May 05 01:21:48 PM PDT 24
Peak memory 198392 kb
Host smart-27a5be46-9c19-4e61-9ed1-fc595753ed91
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566522186 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.3566522186
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.4293114696
Short name T37
Test name
Test status
Simulation time 7766890479 ps
CPU time 5.95 seconds
Started May 05 01:21:50 PM PDT 24
Finished May 05 01:21:57 PM PDT 24
Peak memory 197700 kb
Host smart-c15dabf6-a841-4fbe-8fef-cfbc593155cb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293114696 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl
_intg_err.4293114696
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.1817895398
Short name T387
Test name
Test status
Simulation time 518130924 ps
CPU time 1.32 seconds
Started May 05 01:22:20 PM PDT 24
Finished May 05 01:22:23 PM PDT 24
Peak memory 195676 kb
Host smart-d6eaeb9d-4230-4f67-9508-a054dab72731
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817895398 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.1817895398
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.926021908
Short name T411
Test name
Test status
Simulation time 417530688 ps
CPU time 0.63 seconds
Started May 05 01:22:16 PM PDT 24
Finished May 05 01:22:17 PM PDT 24
Peak memory 183488 kb
Host smart-44b4480d-a1c2-45ac-b3e8-6d509a04cc65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926021908 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.926021908
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.1579418251
Short name T392
Test name
Test status
Simulation time 1550101376 ps
CPU time 1.63 seconds
Started May 05 01:22:19 PM PDT 24
Finished May 05 01:22:21 PM PDT 24
Peak memory 183648 kb
Host smart-0d774a3b-275c-4907-b5c0-cb25a8cf56a2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579418251 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.ao
n_timer_same_csr_outstanding.1579418251
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.2396527209
Short name T372
Test name
Test status
Simulation time 411786308 ps
CPU time 2.54 seconds
Started May 05 01:22:14 PM PDT 24
Finished May 05 01:22:17 PM PDT 24
Peak memory 198448 kb
Host smart-a3323196-5915-4654-9e8d-d2eb0d244d3c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396527209 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.2396527209
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.3192551683
Short name T410
Test name
Test status
Simulation time 4367946683 ps
CPU time 4.05 seconds
Started May 05 01:22:14 PM PDT 24
Finished May 05 01:22:19 PM PDT 24
Peak memory 197232 kb
Host smart-bc979d8e-cbbe-4480-af72-e2061bf7d3ef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192551683 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_t
l_intg_err.3192551683
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.324890725
Short name T310
Test name
Test status
Simulation time 467675997 ps
CPU time 0.93 seconds
Started May 05 01:22:20 PM PDT 24
Finished May 05 01:22:22 PM PDT 24
Peak memory 195620 kb
Host smart-93508a54-95b8-4a38-80cb-6470e8012819
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324890725 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.324890725
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.3704478171
Short name T351
Test name
Test status
Simulation time 455007609 ps
CPU time 0.75 seconds
Started May 05 01:22:20 PM PDT 24
Finished May 05 01:22:22 PM PDT 24
Peak memory 192896 kb
Host smart-0c1740f9-205f-462d-a69f-8917ddb978ef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704478171 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.3704478171
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.4159882019
Short name T313
Test name
Test status
Simulation time 517386647 ps
CPU time 0.64 seconds
Started May 05 01:22:21 PM PDT 24
Finished May 05 01:22:22 PM PDT 24
Peak memory 183492 kb
Host smart-3e536fe6-51c6-4729-88b4-1fb27a01fa11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159882019 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.4159882019
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.3077242964
Short name T400
Test name
Test status
Simulation time 1590701883 ps
CPU time 0.88 seconds
Started May 05 01:22:20 PM PDT 24
Finished May 05 01:22:22 PM PDT 24
Peak memory 193200 kb
Host smart-1c95d2e9-5f53-4579-8fa3-19446e0581b9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077242964 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.ao
n_timer_same_csr_outstanding.3077242964
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.1912539210
Short name T378
Test name
Test status
Simulation time 540126047 ps
CPU time 1.46 seconds
Started May 05 01:22:19 PM PDT 24
Finished May 05 01:22:21 PM PDT 24
Peak memory 198404 kb
Host smart-3101ca84-90b1-4b47-a712-7a23ef9cd774
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912539210 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.1912539210
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.505625838
Short name T307
Test name
Test status
Simulation time 4827197366 ps
CPU time 2.71 seconds
Started May 05 01:22:20 PM PDT 24
Finished May 05 01:22:23 PM PDT 24
Peak memory 197372 kb
Host smart-dfedee54-113e-40c0-98a7-18086fd5e991
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505625838 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl
_intg_err.505625838
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.1404069471
Short name T396
Test name
Test status
Simulation time 533977415 ps
CPU time 0.91 seconds
Started May 05 01:22:20 PM PDT 24
Finished May 05 01:22:22 PM PDT 24
Peak memory 196780 kb
Host smart-d830048e-3b7a-4298-b694-731b8d5a3bc0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404069471 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.1404069471
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.33745621
Short name T356
Test name
Test status
Simulation time 484904292 ps
CPU time 0.94 seconds
Started May 05 01:22:20 PM PDT 24
Finished May 05 01:22:22 PM PDT 24
Peak memory 183856 kb
Host smart-3335444d-f104-4fa8-b797-33dce36644d1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33745621 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.33745621
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.1830328260
Short name T413
Test name
Test status
Simulation time 418287823 ps
CPU time 1.1 seconds
Started May 05 01:22:20 PM PDT 24
Finished May 05 01:22:21 PM PDT 24
Peak memory 183528 kb
Host smart-6c46e578-b48d-467c-b917-0142c6723843
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830328260 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.1830328260
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.1526834826
Short name T72
Test name
Test status
Simulation time 904737880 ps
CPU time 1.04 seconds
Started May 05 01:22:20 PM PDT 24
Finished May 05 01:22:22 PM PDT 24
Peak memory 193076 kb
Host smart-33069214-8ef7-44df-aa43-29b0a17eb3d0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526834826 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.ao
n_timer_same_csr_outstanding.1526834826
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.2232946297
Short name T300
Test name
Test status
Simulation time 992997264 ps
CPU time 1.88 seconds
Started May 05 01:22:20 PM PDT 24
Finished May 05 01:22:23 PM PDT 24
Peak memory 198504 kb
Host smart-667c113a-adcf-414a-9773-088f475b2318
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232946297 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.2232946297
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.2177176237
Short name T406
Test name
Test status
Simulation time 8947740243 ps
CPU time 2.14 seconds
Started May 05 01:22:21 PM PDT 24
Finished May 05 01:22:23 PM PDT 24
Peak memory 197768 kb
Host smart-8d4a7465-cf64-4e1e-b50c-3640ea99d799
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177176237 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_t
l_intg_err.2177176237
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.3840432124
Short name T33
Test name
Test status
Simulation time 537147263 ps
CPU time 1.38 seconds
Started May 05 01:22:25 PM PDT 24
Finished May 05 01:22:27 PM PDT 24
Peak memory 194708 kb
Host smart-5bbf70eb-be31-45f8-9496-b7945a751e0e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840432124 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.3840432124
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.1099352590
Short name T306
Test name
Test status
Simulation time 375690791 ps
CPU time 0.77 seconds
Started May 05 01:22:21 PM PDT 24
Finished May 05 01:22:22 PM PDT 24
Peak memory 183696 kb
Host smart-7dcaedae-6879-4ec7-8e55-41f689c11ee9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099352590 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.1099352590
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.2664937248
Short name T305
Test name
Test status
Simulation time 429226529 ps
CPU time 1.11 seconds
Started May 05 01:22:22 PM PDT 24
Finished May 05 01:22:23 PM PDT 24
Peak memory 183468 kb
Host smart-08bcee79-383a-47ed-9219-9184a7364075
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664937248 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.2664937248
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.760266780
Short name T397
Test name
Test status
Simulation time 963542643 ps
CPU time 1.35 seconds
Started May 05 01:22:25 PM PDT 24
Finished May 05 01:22:26 PM PDT 24
Peak memory 193192 kb
Host smart-09126564-8e28-4fb0-b19c-ddec016961cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760266780 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon
_timer_same_csr_outstanding.760266780
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.55010636
Short name T302
Test name
Test status
Simulation time 502877792 ps
CPU time 1.21 seconds
Started May 05 01:22:22 PM PDT 24
Finished May 05 01:22:24 PM PDT 24
Peak memory 197832 kb
Host smart-cee86f6b-b19c-4a7d-8b7a-489f16c79f99
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55010636 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.55010636
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.1540004149
Short name T408
Test name
Test status
Simulation time 8287643877 ps
CPU time 14.16 seconds
Started May 05 01:22:20 PM PDT 24
Finished May 05 01:22:35 PM PDT 24
Peak memory 197852 kb
Host smart-5831df5f-93e9-4ca4-b8f0-c97946dad11b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540004149 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_t
l_intg_err.1540004149
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.3756248034
Short name T317
Test name
Test status
Simulation time 495026684 ps
CPU time 0.98 seconds
Started May 05 01:22:24 PM PDT 24
Finished May 05 01:22:25 PM PDT 24
Peak memory 195240 kb
Host smart-4aefdf75-ea86-4094-a0c4-10c7b65efb0e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756248034 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.3756248034
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.1707773942
Short name T73
Test name
Test status
Simulation time 433714291 ps
CPU time 0.65 seconds
Started May 05 01:22:23 PM PDT 24
Finished May 05 01:22:24 PM PDT 24
Peak memory 193044 kb
Host smart-88d72df4-789f-4e07-98ce-934453299a39
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707773942 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.1707773942
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.3711918080
Short name T359
Test name
Test status
Simulation time 530975140 ps
CPU time 0.69 seconds
Started May 05 01:22:24 PM PDT 24
Finished May 05 01:22:25 PM PDT 24
Peak memory 183484 kb
Host smart-b9b3899f-b6e8-4750-9710-aa9b97612724
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711918080 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.3711918080
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.3630606164
Short name T402
Test name
Test status
Simulation time 1389806717 ps
CPU time 1.31 seconds
Started May 05 01:22:26 PM PDT 24
Finished May 05 01:22:28 PM PDT 24
Peak memory 193108 kb
Host smart-4a1554d9-82ba-439d-9669-777725e9be79
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630606164 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao
n_timer_same_csr_outstanding.3630606164
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.284941291
Short name T291
Test name
Test status
Simulation time 722363513 ps
CPU time 1.79 seconds
Started May 05 01:22:25 PM PDT 24
Finished May 05 01:22:27 PM PDT 24
Peak memory 198436 kb
Host smart-d0c73491-b8dc-4a89-9ff0-01c247d5a387
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284941291 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.284941291
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.2086937486
Short name T391
Test name
Test status
Simulation time 4163474097 ps
CPU time 3.93 seconds
Started May 05 01:22:27 PM PDT 24
Finished May 05 01:22:31 PM PDT 24
Peak memory 197216 kb
Host smart-e6d3683a-1f19-4b5a-b95c-4027473dbe4c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086937486 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_t
l_intg_err.2086937486
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.2335022094
Short name T333
Test name
Test status
Simulation time 675191014 ps
CPU time 0.79 seconds
Started May 05 01:22:27 PM PDT 24
Finished May 05 01:22:28 PM PDT 24
Peak memory 197020 kb
Host smart-01ffb9ac-d135-4478-9b49-8f1855eef74e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335022094 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.2335022094
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.2015716624
Short name T50
Test name
Test status
Simulation time 405097806 ps
CPU time 0.83 seconds
Started May 05 01:22:24 PM PDT 24
Finished May 05 01:22:25 PM PDT 24
Peak memory 193112 kb
Host smart-b4b1f90f-35bc-4db0-8e5b-aa5fcb9d02d9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015716624 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.2015716624
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.976333069
Short name T371
Test name
Test status
Simulation time 297082998 ps
CPU time 0.76 seconds
Started May 05 01:22:25 PM PDT 24
Finished May 05 01:22:26 PM PDT 24
Peak memory 183428 kb
Host smart-453d9e45-6a23-4dcb-a6ee-43c9a132b80b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976333069 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.976333069
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.1324251845
Short name T349
Test name
Test status
Simulation time 1195972101 ps
CPU time 1.82 seconds
Started May 05 01:22:23 PM PDT 24
Finished May 05 01:22:25 PM PDT 24
Peak memory 183608 kb
Host smart-2c0eb327-3522-45db-b49f-ae7e15231585
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324251845 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.ao
n_timer_same_csr_outstanding.1324251845
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.3595577860
Short name T358
Test name
Test status
Simulation time 381161742 ps
CPU time 1.85 seconds
Started May 05 01:22:26 PM PDT 24
Finished May 05 01:22:28 PM PDT 24
Peak memory 198384 kb
Host smart-ed45a43b-3c79-408e-ac3c-0cbc656b7c3f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595577860 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.3595577860
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.2142289100
Short name T365
Test name
Test status
Simulation time 7513351675 ps
CPU time 7.25 seconds
Started May 05 01:22:24 PM PDT 24
Finished May 05 01:22:32 PM PDT 24
Peak memory 197896 kb
Host smart-1cce2738-ce5f-42ec-a9db-bdffa895b82a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142289100 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_t
l_intg_err.2142289100
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.1505443784
Short name T394
Test name
Test status
Simulation time 565350937 ps
CPU time 0.9 seconds
Started May 05 01:22:29 PM PDT 24
Finished May 05 01:22:31 PM PDT 24
Peak memory 196240 kb
Host smart-126a31e7-0710-48c3-a0f3-cc972d7675c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505443784 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.1505443784
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.398091315
Short name T32
Test name
Test status
Simulation time 390392315 ps
CPU time 0.72 seconds
Started May 05 01:22:24 PM PDT 24
Finished May 05 01:22:25 PM PDT 24
Peak memory 192984 kb
Host smart-fb3618bf-b1c1-4d41-888c-661b42e316a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398091315 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.398091315
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.2911755756
Short name T301
Test name
Test status
Simulation time 543420108 ps
CPU time 0.71 seconds
Started May 05 01:22:27 PM PDT 24
Finished May 05 01:22:28 PM PDT 24
Peak memory 183524 kb
Host smart-b1abf952-14bc-4b32-a328-2fb62ab97f2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911755756 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.2911755756
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.2253056719
Short name T398
Test name
Test status
Simulation time 2796350571 ps
CPU time 4.9 seconds
Started May 05 01:22:27 PM PDT 24
Finished May 05 01:22:32 PM PDT 24
Peak memory 183816 kb
Host smart-998687f9-42da-47e3-9a29-db57dd2a9a09
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253056719 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.ao
n_timer_same_csr_outstanding.2253056719
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.780295202
Short name T337
Test name
Test status
Simulation time 525432880 ps
CPU time 1.62 seconds
Started May 05 01:22:26 PM PDT 24
Finished May 05 01:22:28 PM PDT 24
Peak memory 198416 kb
Host smart-6820ea2c-8342-4ce4-a768-8368a810c68d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780295202 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.780295202
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.1557515616
Short name T338
Test name
Test status
Simulation time 8541286128 ps
CPU time 3.82 seconds
Started May 05 01:22:30 PM PDT 24
Finished May 05 01:22:34 PM PDT 24
Peak memory 197756 kb
Host smart-cdbb5e4b-f4ee-409d-ba04-52ba8121c216
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557515616 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_t
l_intg_err.1557515616
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.3753988510
Short name T350
Test name
Test status
Simulation time 468569897 ps
CPU time 0.75 seconds
Started May 05 01:22:32 PM PDT 24
Finished May 05 01:22:33 PM PDT 24
Peak memory 195376 kb
Host smart-1c124344-9e54-48bf-b109-9d943ceae8e5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753988510 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.3753988510
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.1376254884
Short name T54
Test name
Test status
Simulation time 730687951 ps
CPU time 0.61 seconds
Started May 05 01:22:25 PM PDT 24
Finished May 05 01:22:26 PM PDT 24
Peak memory 193052 kb
Host smart-654f6ce1-7166-4fda-85d6-36d181a7f702
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376254884 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.1376254884
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.3515893666
Short name T319
Test name
Test status
Simulation time 288552244 ps
CPU time 0.96 seconds
Started May 05 01:22:24 PM PDT 24
Finished May 05 01:22:26 PM PDT 24
Peak memory 183532 kb
Host smart-0bcfe508-3363-49fa-b1ae-90c9230cfb12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515893666 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.3515893666
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.3135913100
Short name T347
Test name
Test status
Simulation time 1594771126 ps
CPU time 1.16 seconds
Started May 05 01:22:30 PM PDT 24
Finished May 05 01:22:31 PM PDT 24
Peak memory 183628 kb
Host smart-32dd92e2-4991-484a-9ee3-08fc681c011b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135913100 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.ao
n_timer_same_csr_outstanding.3135913100
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.1204642553
Short name T401
Test name
Test status
Simulation time 389137849 ps
CPU time 2.37 seconds
Started May 05 01:22:27 PM PDT 24
Finished May 05 01:22:30 PM PDT 24
Peak memory 198420 kb
Host smart-4cb7196b-35cc-444c-be81-d53dfda015ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204642553 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.1204642553
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.1893006718
Short name T418
Test name
Test status
Simulation time 614746948 ps
CPU time 1.65 seconds
Started May 05 01:22:28 PM PDT 24
Finished May 05 01:22:30 PM PDT 24
Peak memory 196408 kb
Host smart-db9d9b62-2041-409f-9512-c5a84595aef5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893006718 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.1893006718
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.2383210487
Short name T60
Test name
Test status
Simulation time 320277174 ps
CPU time 0.85 seconds
Started May 05 01:22:30 PM PDT 24
Finished May 05 01:22:31 PM PDT 24
Peak memory 183808 kb
Host smart-c3f4e5c8-8828-43f3-a9a6-0eef0a3af232
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383210487 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.2383210487
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.538697181
Short name T374
Test name
Test status
Simulation time 417690435 ps
CPU time 0.66 seconds
Started May 05 01:22:30 PM PDT 24
Finished May 05 01:22:31 PM PDT 24
Peak memory 183536 kb
Host smart-74828f07-ddd6-4251-939f-02b17a710f09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538697181 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.538697181
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.1814460514
Short name T79
Test name
Test status
Simulation time 1482652702 ps
CPU time 2.9 seconds
Started May 05 01:22:28 PM PDT 24
Finished May 05 01:22:32 PM PDT 24
Peak memory 183828 kb
Host smart-57508f5c-bad6-4395-993b-becd14a0e0f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814460514 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.ao
n_timer_same_csr_outstanding.1814460514
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.3549427522
Short name T296
Test name
Test status
Simulation time 452599407 ps
CPU time 2.42 seconds
Started May 05 01:22:30 PM PDT 24
Finished May 05 01:22:33 PM PDT 24
Peak memory 198436 kb
Host smart-d83b8136-0cf1-45fe-a095-4c5a3dc43324
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549427522 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.3549427522
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.3015825005
Short name T366
Test name
Test status
Simulation time 7873773321 ps
CPU time 13.04 seconds
Started May 05 01:22:31 PM PDT 24
Finished May 05 01:22:45 PM PDT 24
Peak memory 198452 kb
Host smart-c2c25617-a996-4519-bbcd-b0a33354165d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015825005 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_t
l_intg_err.3015825005
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.1924375162
Short name T332
Test name
Test status
Simulation time 350730764 ps
CPU time 0.78 seconds
Started May 05 01:22:33 PM PDT 24
Finished May 05 01:22:34 PM PDT 24
Peak memory 195412 kb
Host smart-11544fde-21dc-4f59-b40f-675b1acae45f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924375162 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.1924375162
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.1792697260
Short name T382
Test name
Test status
Simulation time 452813837 ps
CPU time 1.31 seconds
Started May 05 01:22:32 PM PDT 24
Finished May 05 01:22:34 PM PDT 24
Peak memory 193072 kb
Host smart-113a9470-077b-4ab9-b028-d4ebf8db7cb0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792697260 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.1792697260
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.1997027789
Short name T315
Test name
Test status
Simulation time 280614822 ps
CPU time 0.88 seconds
Started May 05 01:22:28 PM PDT 24
Finished May 05 01:22:29 PM PDT 24
Peak memory 183508 kb
Host smart-4262a8ce-d338-4202-8bf7-d716ed502d22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997027789 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.1997027789
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.925840256
Short name T336
Test name
Test status
Simulation time 1483639044 ps
CPU time 1.47 seconds
Started May 05 01:22:31 PM PDT 24
Finished May 05 01:22:33 PM PDT 24
Peak memory 193260 kb
Host smart-9c3e5767-499d-48e8-9335-3b71366418e8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925840256 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon
_timer_same_csr_outstanding.925840256
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.1169694715
Short name T377
Test name
Test status
Simulation time 351244714 ps
CPU time 2.7 seconds
Started May 05 01:22:32 PM PDT 24
Finished May 05 01:22:35 PM PDT 24
Peak memory 198392 kb
Host smart-c621d916-5946-42e8-9f79-5d7e73240c01
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169694715 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.1169694715
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.281926078
Short name T417
Test name
Test status
Simulation time 8719136326 ps
CPU time 2.85 seconds
Started May 05 01:22:31 PM PDT 24
Finished May 05 01:22:35 PM PDT 24
Peak memory 197844 kb
Host smart-3706deb0-924b-4272-90f5-7e0ced19c9b1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281926078 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl
_intg_err.281926078
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.1927237852
Short name T61
Test name
Test status
Simulation time 633176494 ps
CPU time 1.05 seconds
Started May 05 01:21:55 PM PDT 24
Finished May 05 01:21:56 PM PDT 24
Peak memory 193812 kb
Host smart-8f7dfa1a-9639-4bdc-993a-826c569adb92
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927237852 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_a
liasing.1927237852
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.3259187561
Short name T303
Test name
Test status
Simulation time 7067523806 ps
CPU time 4.08 seconds
Started May 05 01:21:54 PM PDT 24
Finished May 05 01:21:59 PM PDT 24
Peak memory 192112 kb
Host smart-1c3b7fbb-694c-4c98-a2ef-c9a9d413535e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259187561 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_b
it_bash.3259187561
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.2563236877
Short name T289
Test name
Test status
Simulation time 743125385 ps
CPU time 1.22 seconds
Started May 05 01:21:55 PM PDT 24
Finished May 05 01:21:57 PM PDT 24
Peak memory 183672 kb
Host smart-86815b56-346d-45b7-9b83-26810d5413e9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563236877 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_h
w_reset.2563236877
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.178578401
Short name T304
Test name
Test status
Simulation time 395572959 ps
CPU time 0.78 seconds
Started May 05 01:22:01 PM PDT 24
Finished May 05 01:22:02 PM PDT 24
Peak memory 195108 kb
Host smart-73596d9c-7141-4e4e-bbe5-a91afdc66877
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178578401 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.178578401
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.1675655597
Short name T286
Test name
Test status
Simulation time 536073830 ps
CPU time 0.76 seconds
Started May 05 01:21:57 PM PDT 24
Finished May 05 01:21:58 PM PDT 24
Peak memory 193052 kb
Host smart-5d8800e1-d7bf-4611-95e8-ee0a31b10f88
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675655597 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.1675655597
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.3762545477
Short name T284
Test name
Test status
Simulation time 390242219 ps
CPU time 0.65 seconds
Started May 05 01:21:50 PM PDT 24
Finished May 05 01:21:51 PM PDT 24
Peak memory 183524 kb
Host smart-fec13be5-70f7-4905-b768-c39c3839223c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762545477 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.3762545477
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.1407281754
Short name T412
Test name
Test status
Simulation time 442207530 ps
CPU time 1.12 seconds
Started May 05 01:21:57 PM PDT 24
Finished May 05 01:21:58 PM PDT 24
Peak memory 183460 kb
Host smart-212effc2-9315-459a-9d39-94cc930bb4a4
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407281754 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_t
imer_mem_partial_access.1407281754
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.2029327722
Short name T357
Test name
Test status
Simulation time 345879445 ps
CPU time 0.64 seconds
Started May 05 01:21:53 PM PDT 24
Finished May 05 01:21:53 PM PDT 24
Peak memory 183500 kb
Host smart-c0a8b457-58ab-4cde-bf4f-373ce4202cd0
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029327722 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_w
alk.2029327722
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.2683629510
Short name T76
Test name
Test status
Simulation time 2561119401 ps
CPU time 4.19 seconds
Started May 05 01:21:56 PM PDT 24
Finished May 05 01:22:01 PM PDT 24
Peak memory 194292 kb
Host smart-817e62ba-a92e-4000-b83e-3feff7d71c2e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683629510 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon
_timer_same_csr_outstanding.2683629510
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.899127267
Short name T279
Test name
Test status
Simulation time 871127907 ps
CPU time 2.08 seconds
Started May 05 01:21:51 PM PDT 24
Finished May 05 01:21:53 PM PDT 24
Peak memory 198472 kb
Host smart-54f19f9d-7c65-4845-a1ab-229f5d418533
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899127267 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.899127267
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.167665496
Short name T308
Test name
Test status
Simulation time 4719538559 ps
CPU time 1.96 seconds
Started May 05 01:21:51 PM PDT 24
Finished May 05 01:21:53 PM PDT 24
Peak memory 196212 kb
Host smart-ad945e59-46fd-4735-aec8-39bbd206e67e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167665496 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_
intg_err.167665496
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.3045959559
Short name T278
Test name
Test status
Simulation time 411371223 ps
CPU time 0.71 seconds
Started May 05 01:22:30 PM PDT 24
Finished May 05 01:22:31 PM PDT 24
Peak memory 183528 kb
Host smart-5b59b2f1-0434-492d-b91d-6e9a366af9e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045959559 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.3045959559
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.3553012237
Short name T362
Test name
Test status
Simulation time 474306818 ps
CPU time 1.24 seconds
Started May 05 01:22:30 PM PDT 24
Finished May 05 01:22:32 PM PDT 24
Peak memory 183528 kb
Host smart-1b757d8a-4d41-48d0-9711-5619552052ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553012237 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.3553012237
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.2873396044
Short name T294
Test name
Test status
Simulation time 298992186 ps
CPU time 0.68 seconds
Started May 05 01:22:31 PM PDT 24
Finished May 05 01:22:32 PM PDT 24
Peak memory 183436 kb
Host smart-8ee9a948-1498-4306-a539-cec23319287c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873396044 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.2873396044
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.2214329555
Short name T384
Test name
Test status
Simulation time 276436052 ps
CPU time 0.94 seconds
Started May 05 01:22:30 PM PDT 24
Finished May 05 01:22:31 PM PDT 24
Peak memory 183556 kb
Host smart-acecd365-3cc2-409c-b4c1-9a7213380fc1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214329555 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.2214329555
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.1910938054
Short name T405
Test name
Test status
Simulation time 488905303 ps
CPU time 0.67 seconds
Started May 05 01:22:30 PM PDT 24
Finished May 05 01:22:31 PM PDT 24
Peak memory 183532 kb
Host smart-e26fd163-dbd5-4dcf-966c-3ccf6f5f622c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910938054 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.1910938054
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.168399668
Short name T323
Test name
Test status
Simulation time 546311578 ps
CPU time 0.55 seconds
Started May 05 01:22:28 PM PDT 24
Finished May 05 01:22:29 PM PDT 24
Peak memory 183432 kb
Host smart-7df4bf36-3b5b-4ea2-a0d1-0ba470d0403b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168399668 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.168399668
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.3658024658
Short name T298
Test name
Test status
Simulation time 429258042 ps
CPU time 0.68 seconds
Started May 05 01:22:31 PM PDT 24
Finished May 05 01:22:32 PM PDT 24
Peak memory 183492 kb
Host smart-5d4d1354-3aa3-41f9-b2b1-95d61d6ed101
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658024658 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.3658024658
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.937128476
Short name T293
Test name
Test status
Simulation time 504738947 ps
CPU time 1.25 seconds
Started May 05 01:22:33 PM PDT 24
Finished May 05 01:22:34 PM PDT 24
Peak memory 183524 kb
Host smart-160867ea-9b13-41a7-83d3-e7bebd4e4f24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937128476 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.937128476
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.4278136991
Short name T322
Test name
Test status
Simulation time 332305707 ps
CPU time 0.71 seconds
Started May 05 01:22:31 PM PDT 24
Finished May 05 01:22:33 PM PDT 24
Peak memory 183484 kb
Host smart-ec597afa-a29a-450f-8c34-164c8d9f7f4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278136991 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.4278136991
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.4228242522
Short name T299
Test name
Test status
Simulation time 460804941 ps
CPU time 0.6 seconds
Started May 05 01:22:33 PM PDT 24
Finished May 05 01:22:34 PM PDT 24
Peak memory 183512 kb
Host smart-a259627f-e3b1-48d4-bcd3-512c6cb767e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228242522 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.4228242522
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.2153229181
Short name T51
Test name
Test status
Simulation time 575921169 ps
CPU time 0.98 seconds
Started May 05 01:21:57 PM PDT 24
Finished May 05 01:21:58 PM PDT 24
Peak memory 194144 kb
Host smart-ff02ac70-b719-4f8f-8eb7-099d8f568202
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153229181 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_a
liasing.2153229181
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.2356792122
Short name T57
Test name
Test status
Simulation time 4313947701 ps
CPU time 3.81 seconds
Started May 05 01:21:59 PM PDT 24
Finished May 05 01:22:03 PM PDT 24
Peak memory 195032 kb
Host smart-eee4f873-d48e-48ff-b858-c2ba55d29b5c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356792122 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_b
it_bash.2356792122
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.2313408620
Short name T389
Test name
Test status
Simulation time 1253469179 ps
CPU time 1.54 seconds
Started May 05 01:21:54 PM PDT 24
Finished May 05 01:21:56 PM PDT 24
Peak memory 183708 kb
Host smart-299d7862-7cad-44a7-9fd2-cabb608b3086
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313408620 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_h
w_reset.2313408620
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.3235242344
Short name T325
Test name
Test status
Simulation time 439473948 ps
CPU time 1.28 seconds
Started May 05 01:21:57 PM PDT 24
Finished May 05 01:21:59 PM PDT 24
Peak memory 195872 kb
Host smart-83706888-9b96-42a2-aeb0-e820c26a4ada
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235242344 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.3235242344
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.3556212342
Short name T367
Test name
Test status
Simulation time 422190049 ps
CPU time 0.9 seconds
Started May 05 01:21:55 PM PDT 24
Finished May 05 01:21:57 PM PDT 24
Peak memory 183736 kb
Host smart-5038ed74-3054-49c9-bbad-1bf0a867ef68
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556212342 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.3556212342
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.1421373749
Short name T285
Test name
Test status
Simulation time 410838126 ps
CPU time 1.12 seconds
Started May 05 01:21:57 PM PDT 24
Finished May 05 01:21:58 PM PDT 24
Peak memory 183524 kb
Host smart-624f03eb-4826-4e85-90bc-c0d90a26ff83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421373749 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.1421373749
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.4041875719
Short name T287
Test name
Test status
Simulation time 308783318 ps
CPU time 0.62 seconds
Started May 05 01:22:00 PM PDT 24
Finished May 05 01:22:02 PM PDT 24
Peak memory 183416 kb
Host smart-ea27e02b-3555-407b-a684-533c8a8d6e78
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041875719 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_t
imer_mem_partial_access.4041875719
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.3164260248
Short name T295
Test name
Test status
Simulation time 579418463 ps
CPU time 0.55 seconds
Started May 05 01:21:55 PM PDT 24
Finished May 05 01:21:56 PM PDT 24
Peak memory 183508 kb
Host smart-5f7d5343-5b8d-4937-aad3-81d5dcc52cc3
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164260248 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_w
alk.3164260248
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.943041896
Short name T77
Test name
Test status
Simulation time 2239887135 ps
CPU time 2.12 seconds
Started May 05 01:21:55 PM PDT 24
Finished May 05 01:21:57 PM PDT 24
Peak memory 194280 kb
Host smart-b38b4d89-3465-499b-9533-3b8635de0aba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943041896 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_
timer_same_csr_outstanding.943041896
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.657425993
Short name T282
Test name
Test status
Simulation time 478442875 ps
CPU time 1.37 seconds
Started May 05 01:21:56 PM PDT 24
Finished May 05 01:21:58 PM PDT 24
Peak memory 198432 kb
Host smart-6f10e011-9c62-4d47-92a6-f695824f959b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657425993 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.657425993
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.403712715
Short name T334
Test name
Test status
Simulation time 8183035722 ps
CPU time 4.62 seconds
Started May 05 01:21:55 PM PDT 24
Finished May 05 01:22:00 PM PDT 24
Peak memory 197828 kb
Host smart-4914a399-b6de-46e3-b30f-56df8f7c847e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403712715 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_
intg_err.403712715
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.3298596836
Short name T373
Test name
Test status
Simulation time 517068886 ps
CPU time 0.58 seconds
Started May 05 01:22:35 PM PDT 24
Finished May 05 01:22:36 PM PDT 24
Peak memory 183516 kb
Host smart-cf86a6be-bffd-4ce0-90ce-6b5114f2f5ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298596836 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.3298596836
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.3845088430
Short name T419
Test name
Test status
Simulation time 379924323 ps
CPU time 0.64 seconds
Started May 05 01:22:33 PM PDT 24
Finished May 05 01:22:35 PM PDT 24
Peak memory 183524 kb
Host smart-1c6fa94f-58c4-4879-b37b-13a229a99c6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845088430 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.3845088430
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.1566354798
Short name T324
Test name
Test status
Simulation time 298881625 ps
CPU time 1.05 seconds
Started May 05 01:22:33 PM PDT 24
Finished May 05 01:22:35 PM PDT 24
Peak memory 183552 kb
Host smart-56e2d87e-11ea-49be-9ff4-d27aa82b282f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566354798 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.1566354798
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.2329569092
Short name T383
Test name
Test status
Simulation time 505566140 ps
CPU time 0.74 seconds
Started May 05 01:22:34 PM PDT 24
Finished May 05 01:22:35 PM PDT 24
Peak memory 183732 kb
Host smart-71d9706c-6ea9-4872-b9aa-31a65980e388
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329569092 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.2329569092
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.325592849
Short name T327
Test name
Test status
Simulation time 413631010 ps
CPU time 0.79 seconds
Started May 05 01:22:35 PM PDT 24
Finished May 05 01:22:36 PM PDT 24
Peak memory 183528 kb
Host smart-da80b3b0-3653-4475-bf96-556eaa1ce474
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325592849 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.325592849
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.2543953905
Short name T312
Test name
Test status
Simulation time 298415155 ps
CPU time 1.04 seconds
Started May 05 01:22:36 PM PDT 24
Finished May 05 01:22:38 PM PDT 24
Peak memory 183488 kb
Host smart-4b0f67c9-aba7-4990-b89b-791c5f40702a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543953905 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.2543953905
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.1053514613
Short name T309
Test name
Test status
Simulation time 406963611 ps
CPU time 0.59 seconds
Started May 05 01:22:35 PM PDT 24
Finished May 05 01:22:36 PM PDT 24
Peak memory 183524 kb
Host smart-c065d6da-5747-468c-8f78-95a1719accd4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053514613 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.1053514613
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.4115901342
Short name T420
Test name
Test status
Simulation time 353813360 ps
CPU time 1.07 seconds
Started May 05 01:22:36 PM PDT 24
Finished May 05 01:22:38 PM PDT 24
Peak memory 183508 kb
Host smart-9933cd1d-6619-4461-bfd8-c28778b005ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115901342 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.4115901342
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.963763836
Short name T283
Test name
Test status
Simulation time 354387539 ps
CPU time 1.04 seconds
Started May 05 01:22:33 PM PDT 24
Finished May 05 01:22:34 PM PDT 24
Peak memory 183476 kb
Host smart-7cafdf85-d343-45d4-879e-e12bfc6d7860
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963763836 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.963763836
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.1524511
Short name T314
Test name
Test status
Simulation time 275450328 ps
CPU time 0.7 seconds
Started May 05 01:22:36 PM PDT 24
Finished May 05 01:22:37 PM PDT 24
Peak memory 183524 kb
Host smart-df55c125-905c-47f6-ac1b-3407efaed580
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524511 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.1524511
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.1299692856
Short name T58
Test name
Test status
Simulation time 384957875 ps
CPU time 0.95 seconds
Started May 05 01:22:04 PM PDT 24
Finished May 05 01:22:05 PM PDT 24
Peak memory 193084 kb
Host smart-e9196662-c4a9-4137-8c40-f699351e8ed6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299692856 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_a
liasing.1299692856
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.1536767683
Short name T52
Test name
Test status
Simulation time 12046795760 ps
CPU time 18.32 seconds
Started May 05 01:22:00 PM PDT 24
Finished May 05 01:22:18 PM PDT 24
Peak memory 195680 kb
Host smart-a7b3e111-4642-43ae-a296-c98820c5aff4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536767683 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_b
it_bash.1536767683
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.2440146052
Short name T55
Test name
Test status
Simulation time 1144971780 ps
CPU time 2.33 seconds
Started May 05 01:22:00 PM PDT 24
Finished May 05 01:22:03 PM PDT 24
Peak memory 183620 kb
Host smart-f66ac26e-720a-4dcd-9622-1fee0b6daf9b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440146052 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_h
w_reset.2440146052
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.1300389062
Short name T316
Test name
Test status
Simulation time 492309688 ps
CPU time 0.95 seconds
Started May 05 01:22:00 PM PDT 24
Finished May 05 01:22:01 PM PDT 24
Peak memory 198192 kb
Host smart-072f4971-abb3-4d3a-8b18-777680d309c6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300389062 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.1300389062
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.703509369
Short name T98
Test name
Test status
Simulation time 418139340 ps
CPU time 0.68 seconds
Started May 05 01:22:01 PM PDT 24
Finished May 05 01:22:02 PM PDT 24
Peak memory 183596 kb
Host smart-acf7469b-ff34-4a85-9d20-f6baa8ea6983
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703509369 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.703509369
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.1604262589
Short name T363
Test name
Test status
Simulation time 288862830 ps
CPU time 0.9 seconds
Started May 05 01:22:00 PM PDT 24
Finished May 05 01:22:02 PM PDT 24
Peak memory 183572 kb
Host smart-4fe24732-bdaa-4a5e-a48a-093d5f8821da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604262589 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.1604262589
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.1553376262
Short name T345
Test name
Test status
Simulation time 340788095 ps
CPU time 1 seconds
Started May 05 01:22:00 PM PDT 24
Finished May 05 01:22:01 PM PDT 24
Peak memory 183472 kb
Host smart-4a7ae0c6-cf4d-43aa-b432-34eb0aee16a2
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553376262 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_t
imer_mem_partial_access.1553376262
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.2470090502
Short name T346
Test name
Test status
Simulation time 525196201 ps
CPU time 0.7 seconds
Started May 05 01:22:02 PM PDT 24
Finished May 05 01:22:03 PM PDT 24
Peak memory 183524 kb
Host smart-d035155e-f18b-4213-85fb-9b2178f85262
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470090502 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_w
alk.2470090502
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.3799580100
Short name T393
Test name
Test status
Simulation time 1826381329 ps
CPU time 3.38 seconds
Started May 05 01:21:59 PM PDT 24
Finished May 05 01:22:03 PM PDT 24
Peak memory 193084 kb
Host smart-1b8336bd-11d4-40a0-93bc-0d931cb69790
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799580100 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon
_timer_same_csr_outstanding.3799580100
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.1729096909
Short name T381
Test name
Test status
Simulation time 486560516 ps
CPU time 1.56 seconds
Started May 05 01:21:57 PM PDT 24
Finished May 05 01:21:59 PM PDT 24
Peak memory 198468 kb
Host smart-7bbc838f-cb09-4908-9c11-7933df76e521
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729096909 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.1729096909
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.4210723741
Short name T292
Test name
Test status
Simulation time 8086841210 ps
CPU time 12.85 seconds
Started May 05 01:22:00 PM PDT 24
Finished May 05 01:22:14 PM PDT 24
Peak memory 197924 kb
Host smart-65af79f2-f4a7-43d0-8b97-19ba63e742e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210723741 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl
_intg_err.4210723741
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.3307969347
Short name T341
Test name
Test status
Simulation time 362166672 ps
CPU time 0.64 seconds
Started May 05 01:22:37 PM PDT 24
Finished May 05 01:22:38 PM PDT 24
Peak memory 183528 kb
Host smart-07692300-c40f-40a0-8ede-152ebe99330b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307969347 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.3307969347
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.1884558478
Short name T297
Test name
Test status
Simulation time 357349580 ps
CPU time 0.57 seconds
Started May 05 01:22:34 PM PDT 24
Finished May 05 01:22:35 PM PDT 24
Peak memory 183576 kb
Host smart-3106c739-092c-4ef8-8b2d-e707a4b30f6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884558478 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.1884558478
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.2712400313
Short name T290
Test name
Test status
Simulation time 393382162 ps
CPU time 0.67 seconds
Started May 05 01:22:37 PM PDT 24
Finished May 05 01:22:38 PM PDT 24
Peak memory 183512 kb
Host smart-dec92e96-df2c-4693-9c89-291a4b6081d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712400313 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.2712400313
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.469604400
Short name T280
Test name
Test status
Simulation time 509938241 ps
CPU time 1.08 seconds
Started May 05 01:22:34 PM PDT 24
Finished May 05 01:22:36 PM PDT 24
Peak memory 183520 kb
Host smart-373e2555-4195-49f5-9b7b-70908e74c9da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469604400 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.469604400
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.181563851
Short name T330
Test name
Test status
Simulation time 503654742 ps
CPU time 0.7 seconds
Started May 05 01:22:34 PM PDT 24
Finished May 05 01:22:35 PM PDT 24
Peak memory 183484 kb
Host smart-5e931ed3-febd-48b9-8e73-d27b067c79a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181563851 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.181563851
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.3414447969
Short name T318
Test name
Test status
Simulation time 445462183 ps
CPU time 0.73 seconds
Started May 05 01:22:36 PM PDT 24
Finished May 05 01:22:37 PM PDT 24
Peak memory 183512 kb
Host smart-955088bf-4f12-4c9f-b184-4a949a0855ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414447969 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.3414447969
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.2722777169
Short name T407
Test name
Test status
Simulation time 471829341 ps
CPU time 0.67 seconds
Started May 05 01:22:36 PM PDT 24
Finished May 05 01:22:38 PM PDT 24
Peak memory 183524 kb
Host smart-cf07adf4-3eca-47fe-89e3-df3fd6ccae34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722777169 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.2722777169
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.988397372
Short name T395
Test name
Test status
Simulation time 427422474 ps
CPU time 1.15 seconds
Started May 05 01:22:35 PM PDT 24
Finished May 05 01:22:37 PM PDT 24
Peak memory 183432 kb
Host smart-ac1c3e7f-b898-4a8e-9618-8370f8d9a1a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988397372 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.988397372
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.2701504395
Short name T416
Test name
Test status
Simulation time 523892092 ps
CPU time 0.68 seconds
Started May 05 01:22:36 PM PDT 24
Finished May 05 01:22:38 PM PDT 24
Peak memory 183532 kb
Host smart-c0c7e3ec-7638-4f62-a024-93732bee6b64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701504395 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.2701504395
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.1942267405
Short name T409
Test name
Test status
Simulation time 436227774 ps
CPU time 0.82 seconds
Started May 05 01:22:36 PM PDT 24
Finished May 05 01:22:38 PM PDT 24
Peak memory 183512 kb
Host smart-b9d97f45-5ddb-4541-b237-6175b39a8ab3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942267405 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.1942267405
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.1237278164
Short name T320
Test name
Test status
Simulation time 429834925 ps
CPU time 0.73 seconds
Started May 05 01:22:04 PM PDT 24
Finished May 05 01:22:06 PM PDT 24
Peak memory 195440 kb
Host smart-48533033-a8b8-4ad4-a939-cd14eec86027
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237278164 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.1237278164
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.4226757203
Short name T415
Test name
Test status
Simulation time 405941732 ps
CPU time 0.84 seconds
Started May 05 01:22:00 PM PDT 24
Finished May 05 01:22:02 PM PDT 24
Peak memory 192960 kb
Host smart-af5cef24-4200-458d-b529-15204b192440
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226757203 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.4226757203
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.824508106
Short name T369
Test name
Test status
Simulation time 360535434 ps
CPU time 0.7 seconds
Started May 05 01:22:02 PM PDT 24
Finished May 05 01:22:03 PM PDT 24
Peak memory 183524 kb
Host smart-8cdbb42e-0404-4c32-80f8-632f0aa56871
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824508106 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.824508106
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.38307181
Short name T414
Test name
Test status
Simulation time 2599684575 ps
CPU time 1.84 seconds
Started May 05 01:22:00 PM PDT 24
Finished May 05 01:22:03 PM PDT 24
Peak memory 194272 kb
Host smart-fd411bf1-d45d-4197-8ef5-f5349426211d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38307181 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_t
imer_same_csr_outstanding.38307181
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.3355738813
Short name T344
Test name
Test status
Simulation time 540747689 ps
CPU time 1.51 seconds
Started May 05 01:21:59 PM PDT 24
Finished May 05 01:22:00 PM PDT 24
Peak memory 198144 kb
Host smart-266cb410-f898-44a3-88f0-b4a192297e4c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355738813 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.3355738813
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.2857505273
Short name T348
Test name
Test status
Simulation time 8800513194 ps
CPU time 4.93 seconds
Started May 05 01:22:01 PM PDT 24
Finished May 05 01:22:06 PM PDT 24
Peak memory 197812 kb
Host smart-96c66cf3-df9b-4644-b9c3-693f663cc99a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857505273 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl
_intg_err.2857505273
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.3079989957
Short name T404
Test name
Test status
Simulation time 619474911 ps
CPU time 0.88 seconds
Started May 05 01:22:10 PM PDT 24
Finished May 05 01:22:12 PM PDT 24
Peak memory 198328 kb
Host smart-2907aeae-1860-483f-8f6c-47dc8287dc55
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079989957 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.3079989957
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.3141743790
Short name T71
Test name
Test status
Simulation time 403918960 ps
CPU time 0.74 seconds
Started May 05 01:22:04 PM PDT 24
Finished May 05 01:22:05 PM PDT 24
Peak memory 192900 kb
Host smart-f5306b66-1eff-46e7-849c-90b11d364c87
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141743790 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.3141743790
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.2462270041
Short name T354
Test name
Test status
Simulation time 399964735 ps
CPU time 1.07 seconds
Started May 05 01:22:06 PM PDT 24
Finished May 05 01:22:07 PM PDT 24
Peak memory 183504 kb
Host smart-7494b468-9372-4d00-98fe-2b730e04823d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462270041 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.2462270041
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.3727572188
Short name T75
Test name
Test status
Simulation time 2360440572 ps
CPU time 4.03 seconds
Started May 05 01:22:10 PM PDT 24
Finished May 05 01:22:15 PM PDT 24
Peak memory 183912 kb
Host smart-0d64d3bd-835c-4920-95dc-0a352a8fa5df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727572188 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon
_timer_same_csr_outstanding.3727572188
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.1895907565
Short name T379
Test name
Test status
Simulation time 421359780 ps
CPU time 1.82 seconds
Started May 05 01:22:04 PM PDT 24
Finished May 05 01:22:07 PM PDT 24
Peak memory 198440 kb
Host smart-6337f343-e4ff-481a-b929-b1d4189db405
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895907565 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.1895907565
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.3903966183
Short name T97
Test name
Test status
Simulation time 8064583726 ps
CPU time 10.76 seconds
Started May 05 01:22:05 PM PDT 24
Finished May 05 01:22:16 PM PDT 24
Peak memory 197808 kb
Host smart-7b6a475d-864e-4d68-9197-cd635050bbd2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903966183 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl
_intg_err.3903966183
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.2870331810
Short name T364
Test name
Test status
Simulation time 506080111 ps
CPU time 1.03 seconds
Started May 05 01:22:11 PM PDT 24
Finished May 05 01:22:13 PM PDT 24
Peak memory 195652 kb
Host smart-532036c1-7387-4662-b3e0-17e68e35fe54
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870331810 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.2870331810
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.135570592
Short name T376
Test name
Test status
Simulation time 558015442 ps
CPU time 0.82 seconds
Started May 05 01:22:12 PM PDT 24
Finished May 05 01:22:13 PM PDT 24
Peak memory 192976 kb
Host smart-795ce7f9-075a-4714-8660-7ba775c27455
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135570592 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.135570592
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.1154881606
Short name T321
Test name
Test status
Simulation time 322676405 ps
CPU time 1.01 seconds
Started May 05 01:22:10 PM PDT 24
Finished May 05 01:22:12 PM PDT 24
Peak memory 183532 kb
Host smart-b7ae5c6a-3131-4af7-8255-65ad85e49bf3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154881606 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.1154881606
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.3790845388
Short name T74
Test name
Test status
Simulation time 1242488630 ps
CPU time 1.19 seconds
Started May 05 01:22:12 PM PDT 24
Finished May 05 01:22:14 PM PDT 24
Peak memory 183652 kb
Host smart-842e23f6-d869-4e2c-87a4-287257bd8a90
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790845388 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon
_timer_same_csr_outstanding.3790845388
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.3090329382
Short name T386
Test name
Test status
Simulation time 354549521 ps
CPU time 1.96 seconds
Started May 05 01:22:10 PM PDT 24
Finished May 05 01:22:13 PM PDT 24
Peak memory 198404 kb
Host smart-73a58c11-1534-448b-91ac-eaa8809fd8b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090329382 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.3090329382
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.177282545
Short name T329
Test name
Test status
Simulation time 7356534223 ps
CPU time 11.71 seconds
Started May 05 01:22:11 PM PDT 24
Finished May 05 01:22:23 PM PDT 24
Peak memory 197860 kb
Host smart-1fde7330-b846-4cb5-ba57-6d88f35496e6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177282545 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_
intg_err.177282545
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.1249104218
Short name T355
Test name
Test status
Simulation time 350011118 ps
CPU time 1.12 seconds
Started May 05 01:22:17 PM PDT 24
Finished May 05 01:22:19 PM PDT 24
Peak memory 195180 kb
Host smart-701f997a-7528-481f-abef-da3488a265f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249104218 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.1249104218
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.3108591339
Short name T78
Test name
Test status
Simulation time 544091452 ps
CPU time 0.79 seconds
Started May 05 01:22:11 PM PDT 24
Finished May 05 01:22:12 PM PDT 24
Peak memory 183632 kb
Host smart-31f01801-1da1-48ca-a8a5-f07966fea213
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108591339 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.3108591339
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.1149345227
Short name T335
Test name
Test status
Simulation time 273130218 ps
CPU time 0.71 seconds
Started May 05 01:22:11 PM PDT 24
Finished May 05 01:22:12 PM PDT 24
Peak memory 183524 kb
Host smart-1d3b08a2-1061-4173-afb8-2e8392753b6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149345227 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.1149345227
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.788083500
Short name T331
Test name
Test status
Simulation time 3004355114 ps
CPU time 4.06 seconds
Started May 05 01:22:16 PM PDT 24
Finished May 05 01:22:20 PM PDT 24
Peak memory 194572 kb
Host smart-48e6282b-a744-447b-a408-4b0536931669
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788083500 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_
timer_same_csr_outstanding.788083500
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.1990297394
Short name T352
Test name
Test status
Simulation time 273549754 ps
CPU time 1.44 seconds
Started May 05 01:22:12 PM PDT 24
Finished May 05 01:22:14 PM PDT 24
Peak memory 198164 kb
Host smart-590a8dcc-c28d-4169-a962-e5457a62b8b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990297394 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.1990297394
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.2947700626
Short name T311
Test name
Test status
Simulation time 9115056553 ps
CPU time 2.76 seconds
Started May 05 01:22:11 PM PDT 24
Finished May 05 01:22:14 PM PDT 24
Peak memory 197920 kb
Host smart-6517c8f1-d467-44a7-9689-02988400c716
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947700626 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl
_intg_err.2947700626
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.167698598
Short name T34
Test name
Test status
Simulation time 582465658 ps
CPU time 1.24 seconds
Started May 05 01:22:16 PM PDT 24
Finished May 05 01:22:18 PM PDT 24
Peak memory 198260 kb
Host smart-38c61465-6a3b-4ae5-9060-8ef5fb84501d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167698598 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.167698598
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.2442589049
Short name T56
Test name
Test status
Simulation time 353344389 ps
CPU time 0.71 seconds
Started May 05 01:22:16 PM PDT 24
Finished May 05 01:22:17 PM PDT 24
Peak memory 183596 kb
Host smart-ec694fc2-dd6f-453b-b027-b525e3ae1a03
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442589049 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.2442589049
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.2007211520
Short name T403
Test name
Test status
Simulation time 500135834 ps
CPU time 0.71 seconds
Started May 05 01:22:16 PM PDT 24
Finished May 05 01:22:17 PM PDT 24
Peak memory 183532 kb
Host smart-c7c091fb-56df-4d7a-91a4-da3cdb1b1aa5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007211520 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.2007211520
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.2360412230
Short name T340
Test name
Test status
Simulation time 2895713658 ps
CPU time 4.25 seconds
Started May 05 01:22:15 PM PDT 24
Finished May 05 01:22:19 PM PDT 24
Peak memory 183744 kb
Host smart-62f41462-38a1-46a4-a8ab-f054481a7118
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360412230 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon
_timer_same_csr_outstanding.2360412230
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.2112427439
Short name T342
Test name
Test status
Simulation time 549175446 ps
CPU time 1.91 seconds
Started May 05 01:22:18 PM PDT 24
Finished May 05 01:22:20 PM PDT 24
Peak memory 198360 kb
Host smart-f3e1942a-d26f-4ee0-ae78-0b5679d5de4c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112427439 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.2112427439
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.1346031831
Short name T38
Test name
Test status
Simulation time 8442875806 ps
CPU time 6.84 seconds
Started May 05 01:22:15 PM PDT 24
Finished May 05 01:22:23 PM PDT 24
Peak memory 197568 kb
Host smart-c70c4d0c-58fc-484e-965d-28e9c821e586
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346031831 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl
_intg_err.1346031831
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_jump.4247880479
Short name T225
Test name
Test status
Simulation time 518177937 ps
CPU time 1.07 seconds
Started May 05 01:08:08 PM PDT 24
Finished May 05 01:08:10 PM PDT 24
Peak memory 183500 kb
Host smart-77fed1e4-7579-4861-b7b0-435b1571728d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247880479 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.4247880479
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.1169623763
Short name T238
Test name
Test status
Simulation time 32809357312 ps
CPU time 27.46 seconds
Started May 05 01:08:10 PM PDT 24
Finished May 05 01:08:38 PM PDT 24
Peak memory 191792 kb
Host smart-60a08913-7b19-4a8c-aa1b-fe4472078c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169623763 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.1169623763
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.109455453
Short name T232
Test name
Test status
Simulation time 413970794 ps
CPU time 1.23 seconds
Started May 05 01:08:08 PM PDT 24
Finished May 05 01:08:09 PM PDT 24
Peak memory 183484 kb
Host smart-a78fa562-d891-4df3-b918-d8d7e59e0de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109455453 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.109455453
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.3210064021
Short name T131
Test name
Test status
Simulation time 198559729058 ps
CPU time 149.04 seconds
Started May 05 01:08:14 PM PDT 24
Finished May 05 01:10:44 PM PDT 24
Peak memory 183788 kb
Host smart-6360e520-b574-43ef-82bc-03bfbed72eac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210064021 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_a
ll.3210064021
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.1416634389
Short name T260
Test name
Test status
Simulation time 10543151825 ps
CPU time 105.91 seconds
Started May 05 01:08:13 PM PDT 24
Finished May 05 01:10:00 PM PDT 24
Peak memory 198472 kb
Host smart-60d8d35e-a5ce-4884-b1bc-4d5b274d8d4a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416634389 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.1416634389
Directory /workspace/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.aon_timer_jump.2320024779
Short name T128
Test name
Test status
Simulation time 453635386 ps
CPU time 1.25 seconds
Started May 05 01:08:25 PM PDT 24
Finished May 05 01:08:27 PM PDT 24
Peak memory 183472 kb
Host smart-3ab78a8d-516e-427b-a375-0923ed46a046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320024779 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.2320024779
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.3343247256
Short name T105
Test name
Test status
Simulation time 11915897401 ps
CPU time 18.29 seconds
Started May 05 01:08:24 PM PDT 24
Finished May 05 01:08:43 PM PDT 24
Peak memory 183512 kb
Host smart-276019bf-2ba2-40eb-9208-7558c0f2903c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343247256 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.3343247256
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.1850950308
Short name T16
Test name
Test status
Simulation time 8180103089 ps
CPU time 4.16 seconds
Started May 05 01:08:12 PM PDT 24
Finished May 05 01:08:17 PM PDT 24
Peak memory 215232 kb
Host smart-ea65ba9d-bd34-4b60-ac00-fc87d373e65c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850950308 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.1850950308
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.991560604
Short name T185
Test name
Test status
Simulation time 557670406 ps
CPU time 0.6 seconds
Started May 05 01:08:15 PM PDT 24
Finished May 05 01:08:16 PM PDT 24
Peak memory 183388 kb
Host smart-bad8fa9f-5afd-4ae0-9fc3-2401063eba49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991560604 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.991560604
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.3090801018
Short name T249
Test name
Test status
Simulation time 381873388047 ps
CPU time 148.68 seconds
Started May 05 01:08:13 PM PDT 24
Finished May 05 01:10:42 PM PDT 24
Peak memory 194472 kb
Host smart-1f63db8f-74cc-4947-b291-0a3063354a64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090801018 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_a
ll.3090801018
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.2365993923
Short name T31
Test name
Test status
Simulation time 29657162658 ps
CPU time 215.68 seconds
Started May 05 01:08:22 PM PDT 24
Finished May 05 01:11:59 PM PDT 24
Peak memory 198416 kb
Host smart-d7500067-d39b-47d7-bb2f-4500fa759d5f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365993923 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.2365993923
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.aon_timer_jump.2163057804
Short name T210
Test name
Test status
Simulation time 454204142 ps
CPU time 0.7 seconds
Started May 05 01:08:31 PM PDT 24
Finished May 05 01:08:32 PM PDT 24
Peak memory 183444 kb
Host smart-99837afc-65f5-4628-9ab0-0586982187ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163057804 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.2163057804
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.3297981793
Short name T122
Test name
Test status
Simulation time 32559280754 ps
CPU time 48.03 seconds
Started May 05 01:08:33 PM PDT 24
Finished May 05 01:09:22 PM PDT 24
Peak memory 183540 kb
Host smart-2bc6fef3-80ff-42f4-a10b-e884b94939e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297981793 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.3297981793
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.3339386108
Short name T269
Test name
Test status
Simulation time 509927048 ps
CPU time 0.75 seconds
Started May 05 01:08:33 PM PDT 24
Finished May 05 01:08:34 PM PDT 24
Peak memory 183504 kb
Host smart-2e51791c-528a-4a75-8a1f-dcc6347787ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339386108 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.3339386108
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.347485548
Short name T109
Test name
Test status
Simulation time 39808914068 ps
CPU time 12.39 seconds
Started May 05 01:08:46 PM PDT 24
Finished May 05 01:08:59 PM PDT 24
Peak memory 183556 kb
Host smart-32da3c12-ec9e-40a3-acd9-af7484cfbc7b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347485548 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_a
ll.347485548
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_jump.391656274
Short name T27
Test name
Test status
Simulation time 426387782 ps
CPU time 0.84 seconds
Started May 05 01:08:33 PM PDT 24
Finished May 05 01:08:34 PM PDT 24
Peak memory 183508 kb
Host smart-2e5f9a94-9d70-4295-b130-77cd3367c25a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391656274 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.391656274
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.2616458198
Short name T158
Test name
Test status
Simulation time 23262255243 ps
CPU time 33.5 seconds
Started May 05 01:08:38 PM PDT 24
Finished May 05 01:09:13 PM PDT 24
Peak memory 183556 kb
Host smart-ceab70c1-9962-4516-bce6-5f53785b838f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616458198 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.2616458198
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.2722256996
Short name T125
Test name
Test status
Simulation time 586658678 ps
CPU time 0.71 seconds
Started May 05 01:08:32 PM PDT 24
Finished May 05 01:08:34 PM PDT 24
Peak memory 183440 kb
Host smart-104fcee9-6aa3-4359-9da9-54fa08e142f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722256996 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.2722256996
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.3584270797
Short name T19
Test name
Test status
Simulation time 211255101853 ps
CPU time 140.51 seconds
Started May 05 01:08:32 PM PDT 24
Finished May 05 01:10:54 PM PDT 24
Peak memory 194156 kb
Host smart-266769ff-536e-4d5c-a3af-a15bb89ecdf3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584270797 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_
all.3584270797
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.998243961
Short name T41
Test name
Test status
Simulation time 20146118241 ps
CPU time 222.35 seconds
Started May 05 01:08:44 PM PDT 24
Finished May 05 01:12:27 PM PDT 24
Peak memory 198428 kb
Host smart-c3e438ce-0de6-4b86-a30c-7dd982bd3d1d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998243961 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand_reset.998243961
Directory /workspace/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.aon_timer_jump.1620235604
Short name T126
Test name
Test status
Simulation time 560922333 ps
CPU time 0.8 seconds
Started May 05 01:08:42 PM PDT 24
Finished May 05 01:08:43 PM PDT 24
Peak memory 183488 kb
Host smart-afa16f2c-ad1c-4761-a244-2cee9c1597da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620235604 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.1620235604
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.3586528217
Short name T130
Test name
Test status
Simulation time 29251225784 ps
CPU time 11.58 seconds
Started May 05 01:08:41 PM PDT 24
Finished May 05 01:08:53 PM PDT 24
Peak memory 191756 kb
Host smart-dc1d6bbb-fde5-4055-9b44-efef648bd8e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586528217 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.3586528217
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.3118504297
Short name T144
Test name
Test status
Simulation time 417743775 ps
CPU time 1.14 seconds
Started May 05 01:08:32 PM PDT 24
Finished May 05 01:08:34 PM PDT 24
Peak memory 183440 kb
Host smart-8c6902e2-6678-4baa-aa1a-0db692345662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118504297 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.3118504297
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.1165367582
Short name T85
Test name
Test status
Simulation time 195681070258 ps
CPU time 289.35 seconds
Started May 05 01:08:43 PM PDT 24
Finished May 05 01:13:33 PM PDT 24
Peak memory 195036 kb
Host smart-81caf3cc-9bb0-4d2b-9dbf-2200cffef9da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165367582 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_
all.1165367582
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.1831345462
Short name T247
Test name
Test status
Simulation time 76191846155 ps
CPU time 148.11 seconds
Started May 05 01:08:32 PM PDT 24
Finished May 05 01:11:01 PM PDT 24
Peak memory 198404 kb
Host smart-2cfcf1d0-d630-4685-be91-c3b89d9c48c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831345462 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.1831345462
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_jump.1763126536
Short name T151
Test name
Test status
Simulation time 462381988 ps
CPU time 0.89 seconds
Started May 05 01:08:39 PM PDT 24
Finished May 05 01:08:41 PM PDT 24
Peak memory 183444 kb
Host smart-1bbaae15-a0d6-4a0a-b98c-2a8c762eaf2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763126536 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.1763126536
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.2922247796
Short name T273
Test name
Test status
Simulation time 31262833038 ps
CPU time 51.78 seconds
Started May 05 01:08:41 PM PDT 24
Finished May 05 01:09:33 PM PDT 24
Peak memory 183560 kb
Host smart-348f9847-b74c-487d-9c7a-7c75a9b0108e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922247796 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.2922247796
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.2351982677
Short name T213
Test name
Test status
Simulation time 527790984 ps
CPU time 0.73 seconds
Started May 05 01:08:31 PM PDT 24
Finished May 05 01:08:33 PM PDT 24
Peak memory 183492 kb
Host smart-eb1e9064-317b-4e16-8089-30205dbfb125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351982677 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.2351982677
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.3533220503
Short name T222
Test name
Test status
Simulation time 118635100787 ps
CPU time 48.42 seconds
Started May 05 01:08:42 PM PDT 24
Finished May 05 01:09:31 PM PDT 24
Peak memory 183596 kb
Host smart-8581e08e-bdb1-4f7e-a8bb-223d77117e3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533220503 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_
all.3533220503
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.1219059977
Short name T44
Test name
Test status
Simulation time 785890736811 ps
CPU time 401.32 seconds
Started May 05 01:08:41 PM PDT 24
Finished May 05 01:15:23 PM PDT 24
Peak memory 198508 kb
Host smart-6d2ec69a-98af-4f5e-8a21-94ce5bd79fc6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219059977 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.1219059977
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.aon_timer_jump.2640929070
Short name T176
Test name
Test status
Simulation time 566802189 ps
CPU time 1.28 seconds
Started May 05 01:08:40 PM PDT 24
Finished May 05 01:08:42 PM PDT 24
Peak memory 183396 kb
Host smart-d4c7657d-f8f5-47c5-9d69-267749f56599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640929070 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.2640929070
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.2004246358
Short name T276
Test name
Test status
Simulation time 23020191847 ps
CPU time 8.79 seconds
Started May 05 01:08:39 PM PDT 24
Finished May 05 01:08:48 PM PDT 24
Peak memory 183464 kb
Host smart-61d0f00b-04a7-46d2-bc41-d0b85f6d0022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004246358 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.2004246358
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.2712539923
Short name T256
Test name
Test status
Simulation time 400421548 ps
CPU time 0.66 seconds
Started May 05 01:08:33 PM PDT 24
Finished May 05 01:08:34 PM PDT 24
Peak memory 183504 kb
Host smart-fb520ce0-30a6-4b03-8d4d-427616764ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712539923 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.2712539923
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.3328388342
Short name T156
Test name
Test status
Simulation time 173678146638 ps
CPU time 36.67 seconds
Started May 05 01:08:42 PM PDT 24
Finished May 05 01:09:20 PM PDT 24
Peak memory 195016 kb
Host smart-993d0340-d4b1-4180-aa09-2fe6ac02878c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328388342 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_
all.3328388342
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.2463698186
Short name T93
Test name
Test status
Simulation time 332745296483 ps
CPU time 627.67 seconds
Started May 05 01:08:35 PM PDT 24
Finished May 05 01:19:03 PM PDT 24
Peak memory 199528 kb
Host smart-eec977d6-4b68-45e3-9be4-bab24916cf79
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463698186 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.2463698186
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.aon_timer_jump.514432319
Short name T104
Test name
Test status
Simulation time 363533053 ps
CPU time 1.19 seconds
Started May 05 01:08:38 PM PDT 24
Finished May 05 01:08:39 PM PDT 24
Peak memory 183412 kb
Host smart-08ea921c-9a7e-47ae-aee9-1f6e58a6f971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514432319 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.514432319
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.2898451751
Short name T228
Test name
Test status
Simulation time 32165370194 ps
CPU time 29.07 seconds
Started May 05 01:08:42 PM PDT 24
Finished May 05 01:09:12 PM PDT 24
Peak memory 191724 kb
Host smart-9a462639-1e1f-462e-91a9-dd1d310f87af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898451751 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.2898451751
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.1616972786
Short name T261
Test name
Test status
Simulation time 455210283 ps
CPU time 0.81 seconds
Started May 05 01:08:42 PM PDT 24
Finished May 05 01:08:43 PM PDT 24
Peak memory 183492 kb
Host smart-2c22fc3a-5fc6-475b-9fb4-b81f8a946b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616972786 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.1616972786
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.1862263716
Short name T26
Test name
Test status
Simulation time 173293226038 ps
CPU time 64.36 seconds
Started May 05 01:08:35 PM PDT 24
Finished May 05 01:09:40 PM PDT 24
Peak memory 194808 kb
Host smart-a5084736-d454-4cb5-87fb-faafe4a80a81
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862263716 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_
all.1862263716
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_jump.894974325
Short name T138
Test name
Test status
Simulation time 437880322 ps
CPU time 0.88 seconds
Started May 05 01:08:33 PM PDT 24
Finished May 05 01:08:35 PM PDT 24
Peak memory 183464 kb
Host smart-9b25881d-cdaa-42e7-88a9-6a767df063d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894974325 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.894974325
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.58223566
Short name T6
Test name
Test status
Simulation time 1394499915 ps
CPU time 2.54 seconds
Started May 05 01:08:33 PM PDT 24
Finished May 05 01:08:36 PM PDT 24
Peak memory 183508 kb
Host smart-a9623106-91f4-428a-ac5f-9c748d1d8d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58223566 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.58223566
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.1352381600
Short name T81
Test name
Test status
Simulation time 351947647 ps
CPU time 1.06 seconds
Started May 05 01:08:45 PM PDT 24
Finished May 05 01:08:46 PM PDT 24
Peak memory 183488 kb
Host smart-e5315b45-1fad-4c07-b25b-c0aadaf82a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352381600 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.1352381600
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.1576543476
Short name T264
Test name
Test status
Simulation time 63331423094 ps
CPU time 17.54 seconds
Started May 05 01:08:48 PM PDT 24
Finished May 05 01:09:06 PM PDT 24
Peak memory 195224 kb
Host smart-7a206b49-9e7a-438d-accf-42141cee9ead
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576543476 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_
all.1576543476
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.1011927567
Short name T203
Test name
Test status
Simulation time 52503226006 ps
CPU time 411.8 seconds
Started May 05 01:08:43 PM PDT 24
Finished May 05 01:15:35 PM PDT 24
Peak memory 198428 kb
Host smart-859073c0-ad47-41ad-886c-f61efc62af16
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011927567 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.1011927567
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.aon_timer_jump.2136899992
Short name T80
Test name
Test status
Simulation time 363753991 ps
CPU time 0.66 seconds
Started May 05 01:08:41 PM PDT 24
Finished May 05 01:08:42 PM PDT 24
Peak memory 183480 kb
Host smart-62bfd70d-0871-4bf7-91c7-791a7dc3a687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136899992 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.2136899992
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.424123804
Short name T241
Test name
Test status
Simulation time 18130169140 ps
CPU time 15.71 seconds
Started May 05 01:08:36 PM PDT 24
Finished May 05 01:08:52 PM PDT 24
Peak memory 183552 kb
Host smart-677998c7-15c7-4c1e-8392-e41c76c165fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424123804 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.424123804
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.115284071
Short name T150
Test name
Test status
Simulation time 600965648 ps
CPU time 1.16 seconds
Started May 05 01:08:34 PM PDT 24
Finished May 05 01:08:36 PM PDT 24
Peak memory 183548 kb
Host smart-893a957c-acd9-4d03-a38e-708e0b2c72dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115284071 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.115284071
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.1261914145
Short name T267
Test name
Test status
Simulation time 156761881471 ps
CPU time 45.42 seconds
Started May 05 01:08:37 PM PDT 24
Finished May 05 01:09:23 PM PDT 24
Peak memory 183640 kb
Host smart-aa1ebaa1-11f7-4fb2-8fc0-619277e94397
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261914145 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_
all.1261914145
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.902690970
Short name T66
Test name
Test status
Simulation time 95648590429 ps
CPU time 256.61 seconds
Started May 05 01:08:37 PM PDT 24
Finished May 05 01:12:54 PM PDT 24
Peak memory 198436 kb
Host smart-48036168-fba4-4a45-b99b-4f6752a2e9a1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902690970 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.902690970
Directory /workspace/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.aon_timer_jump.474764218
Short name T235
Test name
Test status
Simulation time 409303368 ps
CPU time 0.69 seconds
Started May 05 01:08:41 PM PDT 24
Finished May 05 01:08:42 PM PDT 24
Peak memory 183488 kb
Host smart-d69101ef-8ab8-4a07-a2f1-2b94562049a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474764218 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.474764218
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.1223493410
Short name T277
Test name
Test status
Simulation time 39139901913 ps
CPU time 17.26 seconds
Started May 05 01:08:46 PM PDT 24
Finished May 05 01:09:04 PM PDT 24
Peak memory 183552 kb
Host smart-24b2d805-e9d9-41f5-a3de-fa66108deebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223493410 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.1223493410
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.3418668284
Short name T142
Test name
Test status
Simulation time 525019159 ps
CPU time 0.74 seconds
Started May 05 01:08:46 PM PDT 24
Finished May 05 01:08:47 PM PDT 24
Peak memory 183488 kb
Host smart-1d78d5b7-3eae-46be-a281-bba4fd626bee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418668284 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.3418668284
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.3378182530
Short name T96
Test name
Test status
Simulation time 122710540264 ps
CPU time 136.12 seconds
Started May 05 01:08:43 PM PDT 24
Finished May 05 01:11:00 PM PDT 24
Peak memory 183728 kb
Host smart-dee15eee-18eb-4497-a4f3-34d04f383459
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378182530 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_
all.3378182530
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_jump.3764085768
Short name T63
Test name
Test status
Simulation time 461305629 ps
CPU time 0.98 seconds
Started May 05 01:08:39 PM PDT 24
Finished May 05 01:08:40 PM PDT 24
Peak memory 183488 kb
Host smart-e6ffadff-846a-4e37-9936-9cf2477b5d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764085768 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.3764085768
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.439565143
Short name T3
Test name
Test status
Simulation time 35134329408 ps
CPU time 32.03 seconds
Started May 05 01:08:39 PM PDT 24
Finished May 05 01:09:12 PM PDT 24
Peak memory 183572 kb
Host smart-119891ed-4374-4d3c-b26a-fdec43a3d57f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439565143 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.439565143
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.1921410568
Short name T242
Test name
Test status
Simulation time 506318070 ps
CPU time 1.35 seconds
Started May 05 01:08:44 PM PDT 24
Finished May 05 01:08:46 PM PDT 24
Peak memory 183488 kb
Host smart-4ce4791b-a287-4433-b4af-5da5d2dd876a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921410568 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.1921410568
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.1755948323
Short name T216
Test name
Test status
Simulation time 198333288498 ps
CPU time 79.4 seconds
Started May 05 01:08:40 PM PDT 24
Finished May 05 01:10:00 PM PDT 24
Peak memory 194060 kb
Host smart-465e389e-9df9-4906-aca0-3fd77608f8b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755948323 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_
all.1755948323
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.2862589057
Short name T251
Test name
Test status
Simulation time 33533863000 ps
CPU time 337.06 seconds
Started May 05 01:08:41 PM PDT 24
Finished May 05 01:14:18 PM PDT 24
Peak memory 198472 kb
Host smart-966068db-ba0b-4e4f-afce-2bf9dee74c8e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862589057 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.2862589057
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_jump.1815445194
Short name T172
Test name
Test status
Simulation time 497373185 ps
CPU time 0.66 seconds
Started May 05 01:08:24 PM PDT 24
Finished May 05 01:08:25 PM PDT 24
Peak memory 183440 kb
Host smart-1b3a0eab-b376-461b-beef-d0d5b37ea558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815445194 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.1815445194
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.4016369825
Short name T13
Test name
Test status
Simulation time 1470207447 ps
CPU time 1.62 seconds
Started May 05 01:08:21 PM PDT 24
Finished May 05 01:08:23 PM PDT 24
Peak memory 183504 kb
Host smart-32a51175-1d28-48cb-9e18-7ce2c16f2a4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016369825 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.4016369825
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.1753062260
Short name T20
Test name
Test status
Simulation time 7684794492 ps
CPU time 4.74 seconds
Started May 05 01:08:22 PM PDT 24
Finished May 05 01:08:27 PM PDT 24
Peak memory 215488 kb
Host smart-4c942e9f-1498-4eb7-832d-7d21062a0746
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753062260 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.1753062260
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.1561088157
Short name T120
Test name
Test status
Simulation time 592806019 ps
CPU time 0.73 seconds
Started May 05 01:08:15 PM PDT 24
Finished May 05 01:08:16 PM PDT 24
Peak memory 183484 kb
Host smart-2885edcc-b1cb-495b-997d-e17d64d43cea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561088157 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.1561088157
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.294320050
Short name T136
Test name
Test status
Simulation time 91382433203 ps
CPU time 140.17 seconds
Started May 05 01:08:24 PM PDT 24
Finished May 05 01:10:44 PM PDT 24
Peak memory 191664 kb
Host smart-7019e9ae-d430-452f-a379-a134eed80270
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294320050 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_al
l.294320050
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.2290832044
Short name T270
Test name
Test status
Simulation time 39989573677 ps
CPU time 150.2 seconds
Started May 05 01:08:14 PM PDT 24
Finished May 05 01:10:45 PM PDT 24
Peak memory 198700 kb
Host smart-b13d6559-7f8c-4cc3-a94e-66ed5386f003
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290832044 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.2290832044
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.aon_timer_jump.868646754
Short name T224
Test name
Test status
Simulation time 352405551 ps
CPU time 1.09 seconds
Started May 05 01:08:43 PM PDT 24
Finished May 05 01:08:45 PM PDT 24
Peak memory 183732 kb
Host smart-dbdbd812-c222-47a2-980a-3ec92e5167e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868646754 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.868646754
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.3793913012
Short name T161
Test name
Test status
Simulation time 4969767347 ps
CPU time 2.5 seconds
Started May 05 01:08:42 PM PDT 24
Finished May 05 01:08:45 PM PDT 24
Peak memory 191744 kb
Host smart-f92018ce-1a39-4b59-8247-fd64906fc81f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793913012 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.3793913012
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.3242195785
Short name T110
Test name
Test status
Simulation time 600243363 ps
CPU time 0.57 seconds
Started May 05 01:08:45 PM PDT 24
Finished May 05 01:08:47 PM PDT 24
Peak memory 183420 kb
Host smart-ebc0f552-2ac9-4cbb-a9ec-085c33d78bef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242195785 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.3242195785
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.1144056920
Short name T86
Test name
Test status
Simulation time 75678527164 ps
CPU time 30.49 seconds
Started May 05 01:08:50 PM PDT 24
Finished May 05 01:09:21 PM PDT 24
Peak memory 183488 kb
Host smart-0a6a5f55-fd41-4175-93c4-a3041c887021
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144056920 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_
all.1144056920
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.301302260
Short name T263
Test name
Test status
Simulation time 60144915244 ps
CPU time 452.15 seconds
Started May 05 01:08:49 PM PDT 24
Finished May 05 01:16:22 PM PDT 24
Peak memory 198476 kb
Host smart-6dc17ff5-364d-4172-bd3b-217d8843235c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301302260 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.301302260
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_jump.2109424441
Short name T87
Test name
Test status
Simulation time 457251536 ps
CPU time 0.72 seconds
Started May 05 01:08:39 PM PDT 24
Finished May 05 01:08:40 PM PDT 24
Peak memory 183448 kb
Host smart-200ed44a-958e-4cb1-bfaa-1cfbf149bf99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109424441 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.2109424441
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.3006830404
Short name T9
Test name
Test status
Simulation time 23929942731 ps
CPU time 40.34 seconds
Started May 05 01:08:49 PM PDT 24
Finished May 05 01:09:30 PM PDT 24
Peak memory 191748 kb
Host smart-44e96196-62ed-4113-bf04-45f37b49dbcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006830404 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.3006830404
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.1228136863
Short name T227
Test name
Test status
Simulation time 580825623 ps
CPU time 1.43 seconds
Started May 05 01:08:42 PM PDT 24
Finished May 05 01:08:43 PM PDT 24
Peak memory 183444 kb
Host smart-c59c992a-393f-4e29-9bcf-3994fc8f34b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228136863 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.1228136863
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.2165533479
Short name T195
Test name
Test status
Simulation time 105044503941 ps
CPU time 43.18 seconds
Started May 05 01:08:42 PM PDT 24
Finished May 05 01:09:26 PM PDT 24
Peak memory 194872 kb
Host smart-57cb78d3-bf3f-40d9-975f-5ded9e0120b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165533479 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_
all.2165533479
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_jump.1801449571
Short name T219
Test name
Test status
Simulation time 387242988 ps
CPU time 0.64 seconds
Started May 05 01:08:42 PM PDT 24
Finished May 05 01:08:44 PM PDT 24
Peak memory 183444 kb
Host smart-98f7ae02-bae2-4816-ad09-6e3ea9408059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801449571 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.1801449571
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.1207888925
Short name T204
Test name
Test status
Simulation time 6728021530 ps
CPU time 3.22 seconds
Started May 05 01:08:42 PM PDT 24
Finished May 05 01:08:46 PM PDT 24
Peak memory 183524 kb
Host smart-63362cec-7148-460d-bdfc-6068ba89ba1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207888925 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.1207888925
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.495153894
Short name T115
Test name
Test status
Simulation time 412929938 ps
CPU time 0.7 seconds
Started May 05 01:08:45 PM PDT 24
Finished May 05 01:08:46 PM PDT 24
Peak memory 183452 kb
Host smart-664846d7-5604-4c1b-99e3-2ceec6028616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495153894 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.495153894
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.106490139
Short name T208
Test name
Test status
Simulation time 184010028605 ps
CPU time 72.37 seconds
Started May 05 01:08:39 PM PDT 24
Finished May 05 01:09:52 PM PDT 24
Peak memory 183548 kb
Host smart-849c881f-3f67-4ce5-a61a-f988a3da5ab1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106490139 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_a
ll.106490139
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.3905473962
Short name T146
Test name
Test status
Simulation time 54452428251 ps
CPU time 232.43 seconds
Started May 05 01:08:40 PM PDT 24
Finished May 05 01:12:33 PM PDT 24
Peak memory 198380 kb
Host smart-a27f0310-0144-4330-b3ac-d6e881de814e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905473962 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.3905473962
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.aon_timer_jump.3329784175
Short name T145
Test name
Test status
Simulation time 569585201 ps
CPU time 1 seconds
Started May 05 01:08:43 PM PDT 24
Finished May 05 01:08:45 PM PDT 24
Peak memory 183496 kb
Host smart-2fe5f90b-850f-40dd-8a29-8f5e2e8d884d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329784175 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.3329784175
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.150133757
Short name T171
Test name
Test status
Simulation time 31077539808 ps
CPU time 42.93 seconds
Started May 05 01:08:45 PM PDT 24
Finished May 05 01:09:29 PM PDT 24
Peak memory 191752 kb
Host smart-2b82add9-af53-4724-be57-88c4a4140ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150133757 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.150133757
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.3902700975
Short name T274
Test name
Test status
Simulation time 376712762 ps
CPU time 1.16 seconds
Started May 05 01:08:40 PM PDT 24
Finished May 05 01:08:42 PM PDT 24
Peak memory 183484 kb
Host smart-b3d094b5-005e-4c1f-a91c-45f381da73a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902700975 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.3902700975
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.1641771310
Short name T132
Test name
Test status
Simulation time 56636014217 ps
CPU time 77.04 seconds
Started May 05 01:08:43 PM PDT 24
Finished May 05 01:10:01 PM PDT 24
Peak memory 195240 kb
Host smart-613a5e05-a842-42c5-8192-d29ac135cb4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641771310 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_
all.1641771310
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.3263446783
Short name T90
Test name
Test status
Simulation time 76817909754 ps
CPU time 477.36 seconds
Started May 05 01:08:42 PM PDT 24
Finished May 05 01:16:40 PM PDT 24
Peak memory 198484 kb
Host smart-4e9412c9-c385-4de8-94af-50be88933330
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263446783 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.3263446783
Directory /workspace/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.aon_timer_jump.4209373262
Short name T149
Test name
Test status
Simulation time 534535971 ps
CPU time 0.65 seconds
Started May 05 01:08:46 PM PDT 24
Finished May 05 01:08:47 PM PDT 24
Peak memory 183480 kb
Host smart-e87c2948-ff01-45bc-9ab5-f6b8cbcde88b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209373262 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.4209373262
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.572828283
Short name T119
Test name
Test status
Simulation time 1895768410 ps
CPU time 3.37 seconds
Started May 05 01:08:40 PM PDT 24
Finished May 05 01:08:44 PM PDT 24
Peak memory 183496 kb
Host smart-ad0f86de-a367-4496-9db1-0ceb34f3b4c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572828283 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.572828283
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.141011774
Short name T252
Test name
Test status
Simulation time 394122156 ps
CPU time 0.68 seconds
Started May 05 01:08:46 PM PDT 24
Finished May 05 01:08:48 PM PDT 24
Peak memory 183420 kb
Host smart-1cf0446c-e56b-4141-a716-b34e8b49f03c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141011774 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.141011774
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.4194421389
Short name T221
Test name
Test status
Simulation time 98840669119 ps
CPU time 37.68 seconds
Started May 05 01:08:49 PM PDT 24
Finished May 05 01:09:27 PM PDT 24
Peak memory 183556 kb
Host smart-5e43325d-4929-4424-b5db-bb5ea49e24d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194421389 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_
all.4194421389
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.1428031385
Short name T178
Test name
Test status
Simulation time 38066169078 ps
CPU time 318.4 seconds
Started May 05 01:08:43 PM PDT 24
Finished May 05 01:14:02 PM PDT 24
Peak memory 198348 kb
Host smart-33ce4816-caae-4165-990f-16168447551e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428031385 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand_reset.1428031385
Directory /workspace/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.aon_timer_jump.4118017451
Short name T88
Test name
Test status
Simulation time 383635598 ps
CPU time 0.7 seconds
Started May 05 01:08:49 PM PDT 24
Finished May 05 01:08:51 PM PDT 24
Peak memory 183416 kb
Host smart-f739ea80-8332-4986-8591-3a41a2053bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118017451 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.4118017451
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.1391625493
Short name T211
Test name
Test status
Simulation time 29959667380 ps
CPU time 22.3 seconds
Started May 05 01:08:52 PM PDT 24
Finished May 05 01:09:14 PM PDT 24
Peak memory 191728 kb
Host smart-54749b8f-e7e0-4b12-9fb8-de645c0d8ea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391625493 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.1391625493
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.1184193664
Short name T244
Test name
Test status
Simulation time 461623074 ps
CPU time 0.73 seconds
Started May 05 01:08:56 PM PDT 24
Finished May 05 01:08:57 PM PDT 24
Peak memory 183504 kb
Host smart-8aab30ea-b022-420a-a70e-3d48ea2b0d08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184193664 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.1184193664
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.4203713022
Short name T233
Test name
Test status
Simulation time 130550343215 ps
CPU time 201.61 seconds
Started May 05 01:08:45 PM PDT 24
Finished May 05 01:12:07 PM PDT 24
Peak memory 183508 kb
Host smart-b3f55db3-8ba9-42c8-838e-4ffdf4049f6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203713022 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_
all.4203713022
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_jump.1478793200
Short name T5
Test name
Test status
Simulation time 507744035 ps
CPU time 1.37 seconds
Started May 05 01:08:50 PM PDT 24
Finished May 05 01:08:52 PM PDT 24
Peak memory 183416 kb
Host smart-c93df744-d2b5-4d1e-ab05-95b0cc664b1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478793200 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.1478793200
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.432359290
Short name T8
Test name
Test status
Simulation time 26674454949 ps
CPU time 3.21 seconds
Started May 05 01:08:44 PM PDT 24
Finished May 05 01:08:47 PM PDT 24
Peak memory 183552 kb
Host smart-0a2e9d8f-0706-42b9-8db0-ed81448edcd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432359290 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.432359290
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.4227079869
Short name T67
Test name
Test status
Simulation time 589492445 ps
CPU time 0.68 seconds
Started May 05 01:08:48 PM PDT 24
Finished May 05 01:08:49 PM PDT 24
Peak memory 183492 kb
Host smart-0631eb87-87cb-4981-adfd-8d0ca7df8da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227079869 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.4227079869
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.3127033210
Short name T83
Test name
Test status
Simulation time 156823743776 ps
CPU time 235.49 seconds
Started May 05 01:08:46 PM PDT 24
Finished May 05 01:12:42 PM PDT 24
Peak memory 183508 kb
Host smart-0cc2bfb2-f6a6-488e-bafc-cb4d2b1d229c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127033210 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_
all.3127033210
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.3072746743
Short name T92
Test name
Test status
Simulation time 43697856934 ps
CPU time 182.22 seconds
Started May 05 01:08:44 PM PDT 24
Finished May 05 01:11:47 PM PDT 24
Peak memory 198524 kb
Host smart-b24b34bd-2624-42b6-9325-107ece7ad315
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072746743 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.3072746743
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_jump.511456948
Short name T137
Test name
Test status
Simulation time 608238878 ps
CPU time 0.73 seconds
Started May 05 01:08:50 PM PDT 24
Finished May 05 01:08:51 PM PDT 24
Peak memory 183320 kb
Host smart-2014bd75-28ef-4a4c-b014-04808633aa0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511456948 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.511456948
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.1520889232
Short name T237
Test name
Test status
Simulation time 8643166600 ps
CPU time 4.32 seconds
Started May 05 01:08:54 PM PDT 24
Finished May 05 01:08:59 PM PDT 24
Peak memory 191716 kb
Host smart-59c643b8-72c7-4451-b1b5-f7410d46c778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520889232 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.1520889232
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.4027184146
Short name T114
Test name
Test status
Simulation time 454775951 ps
CPU time 1.22 seconds
Started May 05 01:08:46 PM PDT 24
Finished May 05 01:08:48 PM PDT 24
Peak memory 183480 kb
Host smart-b5606650-ff9f-42cb-b837-7240ea074899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027184146 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.4027184146
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.2451355612
Short name T162
Test name
Test status
Simulation time 136205704205 ps
CPU time 285.28 seconds
Started May 05 01:08:53 PM PDT 24
Finished May 05 01:13:39 PM PDT 24
Peak memory 198528 kb
Host smart-be234864-11b4-45b9-8e99-80ee94263dd4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451355612 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.2451355612
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_jump.3042949542
Short name T24
Test name
Test status
Simulation time 415893367 ps
CPU time 0.85 seconds
Started May 05 01:08:48 PM PDT 24
Finished May 05 01:08:50 PM PDT 24
Peak memory 183484 kb
Host smart-7bc8d754-201f-4a67-a51c-ca777bbff689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042949542 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.3042949542
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.4017738111
Short name T106
Test name
Test status
Simulation time 8121335263 ps
CPU time 11.78 seconds
Started May 05 01:08:49 PM PDT 24
Finished May 05 01:09:02 PM PDT 24
Peak memory 183516 kb
Host smart-6d0ed42d-6d21-4000-a5ee-c1fdae62f54f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017738111 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.4017738111
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.927743921
Short name T250
Test name
Test status
Simulation time 392754024 ps
CPU time 1.17 seconds
Started May 05 01:08:49 PM PDT 24
Finished May 05 01:08:51 PM PDT 24
Peak memory 183408 kb
Host smart-a1513c64-690e-404b-a539-76df9db831ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927743921 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.927743921
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.358874084
Short name T95
Test name
Test status
Simulation time 362490507438 ps
CPU time 631.81 seconds
Started May 05 01:08:49 PM PDT 24
Finished May 05 01:19:22 PM PDT 24
Peak memory 191772 kb
Host smart-79eb7080-4e19-4958-a5ae-9891581061ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358874084 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_a
ll.358874084
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.1317953081
Short name T42
Test name
Test status
Simulation time 76608630984 ps
CPU time 299.45 seconds
Started May 05 01:08:55 PM PDT 24
Finished May 05 01:13:55 PM PDT 24
Peak memory 198516 kb
Host smart-0ebcf473-3ba0-4ca8-9014-00308ccf7b88
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317953081 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.1317953081
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.aon_timer_jump.3199882263
Short name T62
Test name
Test status
Simulation time 528604365 ps
CPU time 0.74 seconds
Started May 05 01:08:50 PM PDT 24
Finished May 05 01:08:51 PM PDT 24
Peak memory 183500 kb
Host smart-f9faa28d-399a-42d3-a4c2-15858d866ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199882263 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.3199882263
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.3314101035
Short name T275
Test name
Test status
Simulation time 18635510358 ps
CPU time 6.27 seconds
Started May 05 01:08:55 PM PDT 24
Finished May 05 01:09:02 PM PDT 24
Peak memory 183552 kb
Host smart-62dbeaac-3c84-4c61-9a07-717571b59edd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314101035 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.3314101035
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.514758777
Short name T257
Test name
Test status
Simulation time 542415006 ps
CPU time 0.88 seconds
Started May 05 01:08:48 PM PDT 24
Finished May 05 01:08:49 PM PDT 24
Peak memory 183548 kb
Host smart-01460bc2-e671-4f85-b7b1-02afdf2eac18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514758777 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.514758777
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.237346549
Short name T18
Test name
Test status
Simulation time 5164018686 ps
CPU time 2.84 seconds
Started May 05 01:08:50 PM PDT 24
Finished May 05 01:08:54 PM PDT 24
Peak memory 191740 kb
Host smart-1e96b0ed-68e2-4779-a019-51d9e9400967
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237346549 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_a
ll.237346549
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.1156203330
Short name T190
Test name
Test status
Simulation time 695472365029 ps
CPU time 792.79 seconds
Started May 05 01:08:48 PM PDT 24
Finished May 05 01:22:01 PM PDT 24
Peak memory 201564 kb
Host smart-122b782c-fcd1-48d0-91d6-56734eaf1a85
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156203330 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.1156203330
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.aon_timer_jump.2199545489
Short name T266
Test name
Test status
Simulation time 529482558 ps
CPU time 0.69 seconds
Started May 05 01:08:23 PM PDT 24
Finished May 05 01:08:24 PM PDT 24
Peak memory 183500 kb
Host smart-d736943b-3192-41d1-83fe-a616e6f97921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199545489 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.2199545489
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.3672295533
Short name T124
Test name
Test status
Simulation time 12538514996 ps
CPU time 19.49 seconds
Started May 05 01:08:23 PM PDT 24
Finished May 05 01:08:43 PM PDT 24
Peak memory 183464 kb
Host smart-3ced009b-88c7-4d17-8120-e6fca6f42829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672295533 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.3672295533
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.2911024336
Short name T21
Test name
Test status
Simulation time 4026195270 ps
CPU time 2.23 seconds
Started May 05 01:08:35 PM PDT 24
Finished May 05 01:08:38 PM PDT 24
Peak memory 214804 kb
Host smart-ce2bace1-6980-465e-89a5-0b307c1d5133
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911024336 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.2911024336
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.1366354637
Short name T173
Test name
Test status
Simulation time 411547786 ps
CPU time 0.6 seconds
Started May 05 01:08:23 PM PDT 24
Finished May 05 01:08:24 PM PDT 24
Peak memory 183508 kb
Host smart-7f275886-2924-4849-8f94-dc84c0450f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366354637 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.1366354637
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.2673645342
Short name T35
Test name
Test status
Simulation time 25068607958 ps
CPU time 10.97 seconds
Started May 05 01:08:24 PM PDT 24
Finished May 05 01:08:36 PM PDT 24
Peak memory 183564 kb
Host smart-6335a625-6a6f-4c9f-85f6-cbf68ef74822
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673645342 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_a
ll.2673645342
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/30.aon_timer_jump.422363485
Short name T160
Test name
Test status
Simulation time 583295767 ps
CPU time 0.76 seconds
Started May 05 01:08:48 PM PDT 24
Finished May 05 01:08:50 PM PDT 24
Peak memory 183468 kb
Host smart-5f8c0e14-8f14-4e68-9178-b46be4419ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422363485 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.422363485
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.746722121
Short name T193
Test name
Test status
Simulation time 34856261908 ps
CPU time 25.99 seconds
Started May 05 01:08:53 PM PDT 24
Finished May 05 01:09:19 PM PDT 24
Peak memory 183552 kb
Host smart-1c50fd1b-c311-454c-a560-6762d76f36a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746722121 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.746722121
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.1167513760
Short name T134
Test name
Test status
Simulation time 355080635 ps
CPU time 1 seconds
Started May 05 01:08:55 PM PDT 24
Finished May 05 01:08:56 PM PDT 24
Peak memory 183412 kb
Host smart-77bea649-31c1-4fa5-89e1-d4af298f14af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167513760 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.1167513760
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.3042428138
Short name T153
Test name
Test status
Simulation time 126728858464 ps
CPU time 203.61 seconds
Started May 05 01:08:53 PM PDT 24
Finished May 05 01:12:17 PM PDT 24
Peak memory 191740 kb
Host smart-dd9e7678-d4d1-47aa-966f-d80ad64bdadf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042428138 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_
all.3042428138
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.117022883
Short name T255
Test name
Test status
Simulation time 87506564348 ps
CPU time 240.58 seconds
Started May 05 01:08:55 PM PDT 24
Finished May 05 01:12:56 PM PDT 24
Peak memory 198688 kb
Host smart-5dfea7d0-20ed-463b-897a-56f25a53f984
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117022883 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.117022883
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.aon_timer_jump.150722439
Short name T64
Test name
Test status
Simulation time 405073337 ps
CPU time 1.13 seconds
Started May 05 01:08:53 PM PDT 24
Finished May 05 01:08:55 PM PDT 24
Peak memory 183496 kb
Host smart-f64c03c8-18fc-4936-9583-6f109a14f7c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150722439 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.150722439
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.2178233895
Short name T189
Test name
Test status
Simulation time 51496490086 ps
CPU time 22.39 seconds
Started May 05 01:08:53 PM PDT 24
Finished May 05 01:09:16 PM PDT 24
Peak memory 183556 kb
Host smart-4ed97483-d41f-4c3e-abf7-1a739659c86a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178233895 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.2178233895
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.4117851310
Short name T107
Test name
Test status
Simulation time 484539488 ps
CPU time 1.2 seconds
Started May 05 01:08:53 PM PDT 24
Finished May 05 01:08:55 PM PDT 24
Peak memory 183460 kb
Host smart-7ca7bfc0-69ee-427e-9638-bc1a0201c115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117851310 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.4117851310
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.2506672966
Short name T169
Test name
Test status
Simulation time 21484976325 ps
CPU time 15.02 seconds
Started May 05 01:08:53 PM PDT 24
Finished May 05 01:09:08 PM PDT 24
Peak memory 183540 kb
Host smart-c584ea91-33ee-4972-b1df-2896df59e9fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506672966 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_
all.2506672966
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.3898458003
Short name T231
Test name
Test status
Simulation time 73349165713 ps
CPU time 314.47 seconds
Started May 05 01:08:54 PM PDT 24
Finished May 05 01:14:09 PM PDT 24
Peak memory 198720 kb
Host smart-a9daf3f3-a14d-4cb7-9e9a-dfa293acdcdf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898458003 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.3898458003
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.aon_timer_jump.3835875358
Short name T197
Test name
Test status
Simulation time 577799296 ps
CPU time 1.48 seconds
Started May 05 01:08:53 PM PDT 24
Finished May 05 01:08:55 PM PDT 24
Peak memory 183544 kb
Host smart-d5fa27ed-8154-4f7b-b7cd-2735c8efadfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835875358 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.3835875358
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.2824750264
Short name T200
Test name
Test status
Simulation time 32146616349 ps
CPU time 14.6 seconds
Started May 05 01:08:56 PM PDT 24
Finished May 05 01:09:11 PM PDT 24
Peak memory 183560 kb
Host smart-f24b3d0b-f4c3-4f4d-a734-b363b268de13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824750264 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.2824750264
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.1505722535
Short name T157
Test name
Test status
Simulation time 418213078 ps
CPU time 0.83 seconds
Started May 05 01:08:54 PM PDT 24
Finished May 05 01:08:55 PM PDT 24
Peak memory 183488 kb
Host smart-e5d48744-d8bd-42e4-b2c8-e034ed8f4205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505722535 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.1505722535
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.4087576289
Short name T199
Test name
Test status
Simulation time 64669327098 ps
CPU time 21.18 seconds
Started May 05 01:08:56 PM PDT 24
Finished May 05 01:09:18 PM PDT 24
Peak memory 183544 kb
Host smart-67b215b7-40c0-474f-929a-02f360da67bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087576289 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_
all.4087576289
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_jump.2587372898
Short name T253
Test name
Test status
Simulation time 524461879 ps
CPU time 1.07 seconds
Started May 05 01:09:00 PM PDT 24
Finished May 05 01:09:02 PM PDT 24
Peak memory 183448 kb
Host smart-78c52a08-09aa-4cd8-be92-e9ca55beb446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587372898 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.2587372898
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.3638875761
Short name T214
Test name
Test status
Simulation time 36673830052 ps
CPU time 5.97 seconds
Started May 05 01:08:53 PM PDT 24
Finished May 05 01:08:59 PM PDT 24
Peak memory 183516 kb
Host smart-815e1736-d152-41f4-aae0-eb2b0f47a3e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638875761 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.3638875761
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.3035106818
Short name T236
Test name
Test status
Simulation time 500799745 ps
CPU time 1.22 seconds
Started May 05 01:08:56 PM PDT 24
Finished May 05 01:08:57 PM PDT 24
Peak memory 183492 kb
Host smart-eb3d8373-8514-4322-a99d-22a152b17054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035106818 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.3035106818
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.740733410
Short name T84
Test name
Test status
Simulation time 49021859555 ps
CPU time 68.4 seconds
Started May 05 01:08:58 PM PDT 24
Finished May 05 01:10:08 PM PDT 24
Peak memory 183500 kb
Host smart-4c5bfb51-9361-4b93-8574-05b7c1940819
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740733410 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_a
ll.740733410
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.2225615298
Short name T198
Test name
Test status
Simulation time 14401563575 ps
CPU time 110.2 seconds
Started May 05 01:08:59 PM PDT 24
Finished May 05 01:10:50 PM PDT 24
Peak memory 198480 kb
Host smart-859298b7-3ff5-4e2a-8b0c-655ab3d28ea3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225615298 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.2225615298
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.aon_timer_jump.3555608118
Short name T201
Test name
Test status
Simulation time 403565324 ps
CPU time 0.71 seconds
Started May 05 01:08:58 PM PDT 24
Finished May 05 01:09:00 PM PDT 24
Peak memory 183448 kb
Host smart-aab94a77-2262-4302-9914-26eb13304f6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555608118 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.3555608118
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.2531065386
Short name T103
Test name
Test status
Simulation time 26283535959 ps
CPU time 9.85 seconds
Started May 05 01:09:00 PM PDT 24
Finished May 05 01:09:11 PM PDT 24
Peak memory 183512 kb
Host smart-574f0e59-1079-4bd4-9404-fc80b79a247e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531065386 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.2531065386
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.45584931
Short name T135
Test name
Test status
Simulation time 580634616 ps
CPU time 0.81 seconds
Started May 05 01:08:59 PM PDT 24
Finished May 05 01:09:01 PM PDT 24
Peak memory 183492 kb
Host smart-9c024637-d956-4cde-803d-f299bdcf788a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45584931 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.45584931
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.2140505596
Short name T143
Test name
Test status
Simulation time 117751193949 ps
CPU time 187.08 seconds
Started May 05 01:09:02 PM PDT 24
Finished May 05 01:12:09 PM PDT 24
Peak memory 183572 kb
Host smart-4ce81ad6-8714-4eb5-9aa3-6ded264de78e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140505596 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_
all.2140505596
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.3279189822
Short name T91
Test name
Test status
Simulation time 711267964323 ps
CPU time 554.71 seconds
Started May 05 01:09:03 PM PDT 24
Finished May 05 01:18:18 PM PDT 24
Peak memory 199004 kb
Host smart-cafb3a5e-2fa5-453e-a077-b7daac5cdc5f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279189822 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.3279189822
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.aon_timer_jump.2722268130
Short name T65
Test name
Test status
Simulation time 344677049 ps
CPU time 1.05 seconds
Started May 05 01:08:59 PM PDT 24
Finished May 05 01:09:01 PM PDT 24
Peak memory 183492 kb
Host smart-b392e383-53d2-47cc-8204-16368ad87311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722268130 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.2722268130
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.4278145990
Short name T265
Test name
Test status
Simulation time 28308188879 ps
CPU time 11.79 seconds
Started May 05 01:08:58 PM PDT 24
Finished May 05 01:09:11 PM PDT 24
Peak memory 191772 kb
Host smart-95829dd9-fee5-4442-8740-7d4ab82f9aeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278145990 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.4278145990
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.1261445562
Short name T209
Test name
Test status
Simulation time 559958446 ps
CPU time 1.35 seconds
Started May 05 01:09:01 PM PDT 24
Finished May 05 01:09:03 PM PDT 24
Peak memory 183472 kb
Host smart-8699d015-8008-40c4-9670-137c1a32d993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261445562 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.1261445562
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.151790890
Short name T101
Test name
Test status
Simulation time 287672095730 ps
CPU time 432.96 seconds
Started May 05 01:08:58 PM PDT 24
Finished May 05 01:16:12 PM PDT 24
Peak memory 183520 kb
Host smart-3a0c977e-9267-4373-ac49-e6af398183a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151790890 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_a
ll.151790890
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_jump.764476402
Short name T163
Test name
Test status
Simulation time 433429044 ps
CPU time 1.11 seconds
Started May 05 01:09:02 PM PDT 24
Finished May 05 01:09:04 PM PDT 24
Peak memory 183480 kb
Host smart-518d55b1-1117-4121-9144-b16bc21891f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764476402 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.764476402
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.3182549968
Short name T82
Test name
Test status
Simulation time 39169296081 ps
CPU time 30.39 seconds
Started May 05 01:08:58 PM PDT 24
Finished May 05 01:09:30 PM PDT 24
Peak memory 183520 kb
Host smart-c4999d27-6c7a-4875-a815-cc6f55ba0738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182549968 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.3182549968
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.4053216432
Short name T111
Test name
Test status
Simulation time 550590596 ps
CPU time 0.85 seconds
Started May 05 01:09:02 PM PDT 24
Finished May 05 01:09:03 PM PDT 24
Peak memory 183440 kb
Host smart-b3e02b77-3baf-4e44-a758-3a8efef6a83c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053216432 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.4053216432
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.2520509242
Short name T147
Test name
Test status
Simulation time 13992068475 ps
CPU time 21.11 seconds
Started May 05 01:08:59 PM PDT 24
Finished May 05 01:09:21 PM PDT 24
Peak memory 183788 kb
Host smart-dab8dc3f-1aa2-459e-a919-2106eb5a6f4b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520509242 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_
all.2520509242
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.3117238744
Short name T148
Test name
Test status
Simulation time 42072434542 ps
CPU time 446.34 seconds
Started May 05 01:09:01 PM PDT 24
Finished May 05 01:16:28 PM PDT 24
Peak memory 198436 kb
Host smart-8c7c7eeb-3802-4f65-a110-878753ffcb82
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117238744 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.3117238744
Directory /workspace/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.aon_timer_jump.462092543
Short name T217
Test name
Test status
Simulation time 479346814 ps
CPU time 0.71 seconds
Started May 05 01:08:58 PM PDT 24
Finished May 05 01:08:59 PM PDT 24
Peak memory 183500 kb
Host smart-cb00423f-f54f-42b0-b046-2297c0e42b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462092543 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.462092543
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.2819337195
Short name T196
Test name
Test status
Simulation time 25695410963 ps
CPU time 4.54 seconds
Started May 05 01:08:59 PM PDT 24
Finished May 05 01:09:04 PM PDT 24
Peak memory 183548 kb
Host smart-a1f78e3e-ca15-415f-bd2b-e8806594e184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819337195 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.2819337195
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.1689495466
Short name T69
Test name
Test status
Simulation time 510627558 ps
CPU time 1.1 seconds
Started May 05 01:09:01 PM PDT 24
Finished May 05 01:09:03 PM PDT 24
Peak memory 183488 kb
Host smart-ebb8b6bd-61f8-4457-9611-84165e5c0343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689495466 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.1689495466
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.636724382
Short name T234
Test name
Test status
Simulation time 44242900076 ps
CPU time 27.06 seconds
Started May 05 01:09:09 PM PDT 24
Finished May 05 01:09:36 PM PDT 24
Peak memory 195136 kb
Host smart-20c14ec5-8ac6-4b09-9a68-d8fd5a8c58e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636724382 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_a
ll.636724382
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.2262434330
Short name T212
Test name
Test status
Simulation time 26697099195 ps
CPU time 284.49 seconds
Started May 05 01:09:05 PM PDT 24
Finished May 05 01:13:50 PM PDT 24
Peak memory 198428 kb
Host smart-f8b39b17-baf6-424b-b088-5ec505a1f87f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262434330 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.2262434330
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.aon_timer_jump.1751521827
Short name T175
Test name
Test status
Simulation time 425788408 ps
CPU time 0.69 seconds
Started May 05 01:09:05 PM PDT 24
Finished May 05 01:09:06 PM PDT 24
Peak memory 183476 kb
Host smart-82aac96a-2398-45c5-b2f6-edb71a0db701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751521827 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.1751521827
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.855785465
Short name T129
Test name
Test status
Simulation time 18315521475 ps
CPU time 15.33 seconds
Started May 05 01:09:04 PM PDT 24
Finished May 05 01:09:20 PM PDT 24
Peak memory 183560 kb
Host smart-6da1f628-7daf-4394-8449-e08ee075d989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855785465 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.855785465
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.3867340812
Short name T207
Test name
Test status
Simulation time 376208632 ps
CPU time 1.16 seconds
Started May 05 01:09:03 PM PDT 24
Finished May 05 01:09:05 PM PDT 24
Peak memory 183508 kb
Host smart-bafa7082-2027-41d7-a35d-f6e7126135e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867340812 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.3867340812
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.4213953512
Short name T140
Test name
Test status
Simulation time 59593961391 ps
CPU time 48.19 seconds
Started May 05 01:09:03 PM PDT 24
Finished May 05 01:09:52 PM PDT 24
Peak memory 183528 kb
Host smart-c5022f47-588b-4106-a834-c8b588153add
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213953512 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_
all.4213953512
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.2941602554
Short name T223
Test name
Test status
Simulation time 270906355874 ps
CPU time 551.38 seconds
Started May 05 01:09:08 PM PDT 24
Finished May 05 01:18:21 PM PDT 24
Peak memory 198872 kb
Host smart-298c67ed-b8fb-4fcc-b34f-04814615f9bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941602554 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand_reset.2941602554
Directory /workspace/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.aon_timer_jump.371291126
Short name T240
Test name
Test status
Simulation time 470583760 ps
CPU time 0.74 seconds
Started May 05 01:09:09 PM PDT 24
Finished May 05 01:09:10 PM PDT 24
Peak memory 183488 kb
Host smart-0a042bb1-fcd4-495e-a7fa-e07d70c2bfac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371291126 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.371291126
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.3915411918
Short name T226
Test name
Test status
Simulation time 4432329202 ps
CPU time 7 seconds
Started May 05 01:09:09 PM PDT 24
Finished May 05 01:09:22 PM PDT 24
Peak memory 191756 kb
Host smart-5b4cf4b0-162d-4dff-9dae-2f8160d0f8f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915411918 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.3915411918
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.1554560161
Short name T100
Test name
Test status
Simulation time 355671223 ps
CPU time 1.08 seconds
Started May 05 01:09:03 PM PDT 24
Finished May 05 01:09:10 PM PDT 24
Peak memory 183488 kb
Host smart-9911ac7b-f34b-4eed-97cf-8a8fc5ee0ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554560161 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.1554560161
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.74571575
Short name T139
Test name
Test status
Simulation time 89003122078 ps
CPU time 23.7 seconds
Started May 05 01:09:05 PM PDT 24
Finished May 05 01:09:29 PM PDT 24
Peak memory 193824 kb
Host smart-015a8c3f-a2d2-454e-87ed-b4c0140334c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74571575 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_al
l.74571575
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.506787370
Short name T40
Test name
Test status
Simulation time 354002424560 ps
CPU time 280.6 seconds
Started May 05 01:09:04 PM PDT 24
Finished May 05 01:13:45 PM PDT 24
Peak memory 198424 kb
Host smart-68707f3b-0af6-4552-a428-ca3c2e284c6d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506787370 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.506787370
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_jump.674811707
Short name T271
Test name
Test status
Simulation time 427025723 ps
CPU time 0.66 seconds
Started May 05 01:08:25 PM PDT 24
Finished May 05 01:08:26 PM PDT 24
Peak memory 183492 kb
Host smart-d266977d-cd4d-4a32-8001-ba739b7c5902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674811707 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.674811707
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.1426695743
Short name T182
Test name
Test status
Simulation time 29110622698 ps
CPU time 45.13 seconds
Started May 05 01:08:23 PM PDT 24
Finished May 05 01:09:08 PM PDT 24
Peak memory 183524 kb
Host smart-9e43d35b-73bb-4d8f-b3a0-6f7483707f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426695743 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.1426695743
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.2072556991
Short name T15
Test name
Test status
Simulation time 7476714454 ps
CPU time 14.2 seconds
Started May 05 01:08:37 PM PDT 24
Finished May 05 01:08:52 PM PDT 24
Peak memory 215224 kb
Host smart-5d9b1f33-a2fa-4415-b0be-86fa602db800
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072556991 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.2072556991
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.4096434907
Short name T12
Test name
Test status
Simulation time 347873190 ps
CPU time 0.78 seconds
Started May 05 01:08:23 PM PDT 24
Finished May 05 01:08:24 PM PDT 24
Peak memory 183500 kb
Host smart-461c6bbc-5df4-400f-896b-dd2660b4019c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096434907 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.4096434907
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.540698294
Short name T188
Test name
Test status
Simulation time 208104689425 ps
CPU time 150.11 seconds
Started May 05 01:08:18 PM PDT 24
Finished May 05 01:10:48 PM PDT 24
Peak memory 195092 kb
Host smart-c10ffb39-a449-4556-a2b8-e9ce8cfd9bee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540698294 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_al
l.540698294
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.2463661011
Short name T205
Test name
Test status
Simulation time 85209750424 ps
CPU time 344.32 seconds
Started May 05 01:08:28 PM PDT 24
Finished May 05 01:14:13 PM PDT 24
Peak memory 214804 kb
Host smart-3080b22d-217f-4d44-8cc0-1f3bb9f8deb8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463661011 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.2463661011
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.aon_timer_jump.2518058933
Short name T155
Test name
Test status
Simulation time 501202137 ps
CPU time 0.7 seconds
Started May 05 01:09:04 PM PDT 24
Finished May 05 01:09:05 PM PDT 24
Peak memory 183360 kb
Host smart-0fb51e1f-235a-48fc-9e7b-5baab9c88978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518058933 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.2518058933
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.1218578596
Short name T117
Test name
Test status
Simulation time 5701138949 ps
CPU time 7.97 seconds
Started May 05 01:09:09 PM PDT 24
Finished May 05 01:09:17 PM PDT 24
Peak memory 183552 kb
Host smart-df35dee9-1da3-4360-85f2-eeeab012252d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218578596 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.1218578596
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.1360345997
Short name T28
Test name
Test status
Simulation time 386321485 ps
CPU time 0.66 seconds
Started May 05 01:09:03 PM PDT 24
Finished May 05 01:09:04 PM PDT 24
Peak memory 183456 kb
Host smart-bbee9475-836e-4837-90a2-1b5454f184f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360345997 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.1360345997
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.2884270606
Short name T22
Test name
Test status
Simulation time 121929853429 ps
CPU time 164.38 seconds
Started May 05 01:09:02 PM PDT 24
Finished May 05 01:11:47 PM PDT 24
Peak memory 183540 kb
Host smart-636a57e0-cc12-4361-b1f9-e9ceb637b939
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884270606 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_
all.2884270606
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_jump.2399080265
Short name T191
Test name
Test status
Simulation time 353918223 ps
CPU time 0.99 seconds
Started May 05 01:09:06 PM PDT 24
Finished May 05 01:09:08 PM PDT 24
Peak memory 183488 kb
Host smart-cf148de1-fd06-46b1-99c1-ac6728babd26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399080265 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.2399080265
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.728585139
Short name T99
Test name
Test status
Simulation time 43002141306 ps
CPU time 37.22 seconds
Started May 05 01:09:08 PM PDT 24
Finished May 05 01:09:46 PM PDT 24
Peak memory 183476 kb
Host smart-8140fe22-d757-46b5-b32c-d9d6e9bafef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728585139 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.728585139
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.422570855
Short name T11
Test name
Test status
Simulation time 472252552 ps
CPU time 0.93 seconds
Started May 05 01:09:08 PM PDT 24
Finished May 05 01:09:10 PM PDT 24
Peak memory 183392 kb
Host smart-95a75c28-b529-40e7-96d8-078a60fd341a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422570855 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.422570855
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.712086275
Short name T187
Test name
Test status
Simulation time 189194471173 ps
CPU time 143.6 seconds
Started May 05 01:09:10 PM PDT 24
Finished May 05 01:11:34 PM PDT 24
Peak memory 195192 kb
Host smart-1f3e16a0-57cf-49fd-b90b-2d35f104956d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712086275 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_a
ll.712086275
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.2832189567
Short name T89
Test name
Test status
Simulation time 759223279367 ps
CPU time 656.58 seconds
Started May 05 01:09:15 PM PDT 24
Finished May 05 01:20:13 PM PDT 24
Peak memory 199920 kb
Host smart-8f165903-b673-47b5-bb62-3355a1be72d8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832189567 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.2832189567
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.aon_timer_jump.1593044699
Short name T46
Test name
Test status
Simulation time 588975076 ps
CPU time 0.64 seconds
Started May 05 01:09:15 PM PDT 24
Finished May 05 01:09:17 PM PDT 24
Peak memory 183388 kb
Host smart-a169f2fc-f59b-49b3-999f-57bf9e1520a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593044699 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.1593044699
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.319231279
Short name T259
Test name
Test status
Simulation time 10341612277 ps
CPU time 18.29 seconds
Started May 05 01:09:15 PM PDT 24
Finished May 05 01:09:34 PM PDT 24
Peak memory 191680 kb
Host smart-63aec01b-3c63-4f7e-8286-04abf43fae29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319231279 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.319231279
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.699232243
Short name T152
Test name
Test status
Simulation time 516682070 ps
CPU time 0.84 seconds
Started May 05 01:09:10 PM PDT 24
Finished May 05 01:09:12 PM PDT 24
Peak memory 183464 kb
Host smart-990cc3d7-75dd-4cbc-83a7-2f40b8dfc67d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699232243 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.699232243
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.2733242213
Short name T206
Test name
Test status
Simulation time 24005039765 ps
CPU time 10.44 seconds
Started May 05 01:09:10 PM PDT 24
Finished May 05 01:09:21 PM PDT 24
Peak memory 183548 kb
Host smart-27e2280f-124e-4c5b-900f-9a029e757de3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733242213 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_
all.2733242213
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.3437815492
Short name T248
Test name
Test status
Simulation time 53636269517 ps
CPU time 387.74 seconds
Started May 05 01:09:09 PM PDT 24
Finished May 05 01:15:37 PM PDT 24
Peak memory 198396 kb
Host smart-b8fbc12a-9114-4ee7-82b9-c3ce1ed0dfd8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437815492 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.3437815492
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.aon_timer_jump.60013514
Short name T166
Test name
Test status
Simulation time 511701518 ps
CPU time 1.29 seconds
Started May 05 01:09:08 PM PDT 24
Finished May 05 01:09:10 PM PDT 24
Peak memory 183484 kb
Host smart-df43fd1a-c2cb-4f84-8103-84a42c7b2896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60013514 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.60013514
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.618749067
Short name T218
Test name
Test status
Simulation time 41964345243 ps
CPU time 15.7 seconds
Started May 05 01:09:10 PM PDT 24
Finished May 05 01:09:26 PM PDT 24
Peak memory 183560 kb
Host smart-e4bee739-eb63-4dda-95eb-e38bc5f27c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618749067 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.618749067
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.30927928
Short name T14
Test name
Test status
Simulation time 450375788 ps
CPU time 0.74 seconds
Started May 05 01:09:10 PM PDT 24
Finished May 05 01:09:11 PM PDT 24
Peak memory 183476 kb
Host smart-423ba7db-6673-47fb-9c02-0a32272e1631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30927928 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.30927928
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.301608524
Short name T246
Test name
Test status
Simulation time 83770774958 ps
CPU time 30.49 seconds
Started May 05 01:09:09 PM PDT 24
Finished May 05 01:09:40 PM PDT 24
Peak memory 183488 kb
Host smart-93e2c2ef-07f5-42c4-8c40-01e68a6bb08f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301608524 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_a
ll.301608524
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.4076115320
Short name T174
Test name
Test status
Simulation time 756725365331 ps
CPU time 1308 seconds
Started May 05 01:09:09 PM PDT 24
Finished May 05 01:30:58 PM PDT 24
Peak memory 208836 kb
Host smart-9a7ca3ef-68b0-47b6-820d-a865e7eeefab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076115320 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.4076115320
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.aon_timer_jump.1990511890
Short name T141
Test name
Test status
Simulation time 388652215 ps
CPU time 0.81 seconds
Started May 05 01:09:10 PM PDT 24
Finished May 05 01:09:11 PM PDT 24
Peak memory 183500 kb
Host smart-8d371c09-b000-4822-8851-90a33937f73f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990511890 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.1990511890
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.952040546
Short name T230
Test name
Test status
Simulation time 21213297897 ps
CPU time 18.61 seconds
Started May 05 01:09:12 PM PDT 24
Finished May 05 01:09:31 PM PDT 24
Peak memory 183552 kb
Host smart-7863a693-44a3-4b0b-9c62-aff7a296f746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952040546 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.952040546
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.3221951304
Short name T168
Test name
Test status
Simulation time 574495864 ps
CPU time 0.72 seconds
Started May 05 01:09:11 PM PDT 24
Finished May 05 01:09:12 PM PDT 24
Peak memory 183476 kb
Host smart-c06afa64-60e0-4351-9a5b-c628a31a3953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221951304 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.3221951304
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.2721515035
Short name T113
Test name
Test status
Simulation time 104657151479 ps
CPU time 49.24 seconds
Started May 05 01:09:08 PM PDT 24
Finished May 05 01:09:58 PM PDT 24
Peak memory 193640 kb
Host smart-5580a7ef-3a31-4224-a933-f19cb393ab07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721515035 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_
all.2721515035
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_jump.3275226031
Short name T167
Test name
Test status
Simulation time 552742471 ps
CPU time 0.75 seconds
Started May 05 01:09:10 PM PDT 24
Finished May 05 01:09:11 PM PDT 24
Peak memory 183468 kb
Host smart-4ceb49d1-a039-4f1a-b89b-829773a6a45a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275226031 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.3275226031
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.2416178261
Short name T186
Test name
Test status
Simulation time 22804888421 ps
CPU time 37.35 seconds
Started May 05 01:09:10 PM PDT 24
Finished May 05 01:09:53 PM PDT 24
Peak memory 183560 kb
Host smart-5f7de697-696d-4b82-8f37-16f011f2bd95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416178261 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.2416178261
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.1089685076
Short name T258
Test name
Test status
Simulation time 425035288 ps
CPU time 1.08 seconds
Started May 05 01:09:12 PM PDT 24
Finished May 05 01:09:13 PM PDT 24
Peak memory 183440 kb
Host smart-791405e5-7234-4381-8049-f37fc38e26cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089685076 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.1089685076
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.527500957
Short name T215
Test name
Test status
Simulation time 271247769301 ps
CPU time 67.81 seconds
Started May 05 01:09:12 PM PDT 24
Finished May 05 01:10:20 PM PDT 24
Peak memory 183620 kb
Host smart-04ccc9a9-6f6d-415b-ade9-4a81b51113b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527500957 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_a
ll.527500957
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.1974276373
Short name T94
Test name
Test status
Simulation time 15365718414 ps
CPU time 119.56 seconds
Started May 05 01:09:10 PM PDT 24
Finished May 05 01:11:10 PM PDT 24
Peak memory 198420 kb
Host smart-90b30986-fedb-42dd-8aca-4b38d3fe7bcc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974276373 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.1974276373
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.aon_timer_jump.893986760
Short name T165
Test name
Test status
Simulation time 492159822 ps
CPU time 0.72 seconds
Started May 05 01:09:16 PM PDT 24
Finished May 05 01:09:17 PM PDT 24
Peak memory 183480 kb
Host smart-e2371814-297a-472c-86c9-1987f7b0a132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893986760 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.893986760
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.2085376814
Short name T202
Test name
Test status
Simulation time 11591849389 ps
CPU time 17.5 seconds
Started May 05 01:09:14 PM PDT 24
Finished May 05 01:09:32 PM PDT 24
Peak memory 183548 kb
Host smart-c4e000cd-ec2d-47eb-8817-daf785a0f2a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085376814 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.2085376814
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.2102531464
Short name T183
Test name
Test status
Simulation time 341791256 ps
CPU time 1 seconds
Started May 05 01:09:09 PM PDT 24
Finished May 05 01:09:11 PM PDT 24
Peak memory 183500 kb
Host smart-a3373f4a-37a1-4add-bfcc-2ca696db4926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102531464 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.2102531464
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.686647627
Short name T177
Test name
Test status
Simulation time 134394353232 ps
CPU time 36.09 seconds
Started May 05 01:09:19 PM PDT 24
Finished May 05 01:09:55 PM PDT 24
Peak memory 183472 kb
Host smart-0e7aa4e6-37eb-4fd6-a25c-ef81f9e5548b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686647627 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_a
ll.686647627
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.2202991671
Short name T123
Test name
Test status
Simulation time 25556812810 ps
CPU time 197.46 seconds
Started May 05 01:09:16 PM PDT 24
Finished May 05 01:12:34 PM PDT 24
Peak memory 198444 kb
Host smart-5a54ac48-29a8-4506-8504-673c4753b394
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202991671 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.2202991671
Directory /workspace/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.aon_timer_jump.1035034957
Short name T245
Test name
Test status
Simulation time 464575096 ps
CPU time 0.89 seconds
Started May 05 01:09:17 PM PDT 24
Finished May 05 01:09:18 PM PDT 24
Peak memory 183444 kb
Host smart-b3a4b140-883c-4bd6-8ddd-3a9416b56a53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035034957 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.1035034957
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.2214132050
Short name T108
Test name
Test status
Simulation time 33679344339 ps
CPU time 13.2 seconds
Started May 05 01:09:15 PM PDT 24
Finished May 05 01:09:29 PM PDT 24
Peak memory 183564 kb
Host smart-32d0b15d-3b3b-4a1b-8fbf-661930ce4e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214132050 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.2214132050
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.1904499453
Short name T194
Test name
Test status
Simulation time 365023328 ps
CPU time 1.15 seconds
Started May 05 01:09:19 PM PDT 24
Finished May 05 01:09:20 PM PDT 24
Peak memory 183168 kb
Host smart-1d10fc17-d957-42d8-85a3-eef15c146e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904499453 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.1904499453
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_jump.1915761406
Short name T118
Test name
Test status
Simulation time 472667729 ps
CPU time 0.91 seconds
Started May 05 01:09:14 PM PDT 24
Finished May 05 01:09:15 PM PDT 24
Peak memory 183484 kb
Host smart-702a067c-5193-4471-a200-828eefeae970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915761406 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.1915761406
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.2076011743
Short name T112
Test name
Test status
Simulation time 12978504599 ps
CPU time 6.04 seconds
Started May 05 01:09:18 PM PDT 24
Finished May 05 01:09:24 PM PDT 24
Peak memory 191764 kb
Host smart-c011fc00-b66f-4f8e-82a2-53463a259798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076011743 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.2076011743
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.713999000
Short name T262
Test name
Test status
Simulation time 619936886 ps
CPU time 0.95 seconds
Started May 05 01:09:23 PM PDT 24
Finished May 05 01:09:24 PM PDT 24
Peak memory 183484 kb
Host smart-2d0c226a-b74f-4bdc-8214-8dc78fc089c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713999000 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.713999000
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.3671440355
Short name T133
Test name
Test status
Simulation time 54242978691 ps
CPU time 20.95 seconds
Started May 05 01:09:17 PM PDT 24
Finished May 05 01:09:38 PM PDT 24
Peak memory 183548 kb
Host smart-a4d192ab-ed52-4af5-8a42-68dee7b14687
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671440355 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_
all.3671440355
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_jump.1822879184
Short name T25
Test name
Test status
Simulation time 476551793 ps
CPU time 0.73 seconds
Started May 05 01:09:25 PM PDT 24
Finished May 05 01:09:26 PM PDT 24
Peak memory 183472 kb
Host smart-d80e044f-de4a-4792-9332-511350c2ac1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822879184 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.1822879184
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.1327315336
Short name T154
Test name
Test status
Simulation time 30299850052 ps
CPU time 4.83 seconds
Started May 05 01:09:14 PM PDT 24
Finished May 05 01:09:19 PM PDT 24
Peak memory 183556 kb
Host smart-41222ec3-2eec-4a76-9f8b-04161fc65dfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327315336 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.1327315336
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.4046793112
Short name T192
Test name
Test status
Simulation time 488210606 ps
CPU time 0.67 seconds
Started May 05 01:09:15 PM PDT 24
Finished May 05 01:09:16 PM PDT 24
Peak memory 183440 kb
Host smart-136bc49b-f089-45e7-a818-60f0d6a6f0ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046793112 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.4046793112
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.3908766910
Short name T70
Test name
Test status
Simulation time 70082603704 ps
CPU time 105.69 seconds
Started May 05 01:09:14 PM PDT 24
Finished May 05 01:11:00 PM PDT 24
Peak memory 183572 kb
Host smart-52bd26f8-7a1e-4536-a2ac-63cac29350da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908766910 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_
all.3908766910
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_jump.1139335466
Short name T239
Test name
Test status
Simulation time 641359014 ps
CPU time 0.64 seconds
Started May 05 01:08:18 PM PDT 24
Finished May 05 01:08:19 PM PDT 24
Peak memory 183488 kb
Host smart-5fe3f932-1eeb-450f-89ca-e6f3810b1f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139335466 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.1139335466
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.3687995047
Short name T4
Test name
Test status
Simulation time 26661255795 ps
CPU time 11.77 seconds
Started May 05 01:08:37 PM PDT 24
Finished May 05 01:08:50 PM PDT 24
Peak memory 183556 kb
Host smart-b2357cd3-1903-4bb3-ad7c-97419885c4e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687995047 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.3687995047
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.1569659664
Short name T179
Test name
Test status
Simulation time 489976804 ps
CPU time 1.2 seconds
Started May 05 01:08:29 PM PDT 24
Finished May 05 01:08:31 PM PDT 24
Peak memory 183440 kb
Host smart-afb1de79-6405-43b2-98e8-ff1b77161322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569659664 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.1569659664
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.3346794433
Short name T159
Test name
Test status
Simulation time 173442908430 ps
CPU time 133.02 seconds
Started May 05 01:08:28 PM PDT 24
Finished May 05 01:10:41 PM PDT 24
Peak memory 193772 kb
Host smart-89a53489-d755-4499-841d-83ceb0a181ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346794433 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_a
ll.3346794433
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.1734873042
Short name T47
Test name
Test status
Simulation time 65192423071 ps
CPU time 348.65 seconds
Started May 05 01:08:34 PM PDT 24
Finished May 05 01:14:23 PM PDT 24
Peak memory 198496 kb
Host smart-c9e218b5-0e99-4182-9366-6fea39113169
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734873042 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.1734873042
Directory /workspace/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.aon_timer_jump.2915860767
Short name T116
Test name
Test status
Simulation time 507749057 ps
CPU time 0.69 seconds
Started May 05 01:08:34 PM PDT 24
Finished May 05 01:08:35 PM PDT 24
Peak memory 183476 kb
Host smart-90acdf06-dd3a-4625-ab10-745df1eab4e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915860767 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.2915860767
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.777250358
Short name T170
Test name
Test status
Simulation time 6455845248 ps
CPU time 10.77 seconds
Started May 05 01:08:35 PM PDT 24
Finished May 05 01:08:46 PM PDT 24
Peak memory 192000 kb
Host smart-30714792-7b9b-494d-9b2b-29c6c549ab3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777250358 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.777250358
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.358100799
Short name T68
Test name
Test status
Simulation time 449414732 ps
CPU time 1.14 seconds
Started May 05 01:08:28 PM PDT 24
Finished May 05 01:08:30 PM PDT 24
Peak memory 183444 kb
Host smart-d71c09ba-b115-4bd5-84c4-59ac9a8df691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358100799 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.358100799
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.2980763683
Short name T121
Test name
Test status
Simulation time 85724202904 ps
CPU time 133.42 seconds
Started May 05 01:08:38 PM PDT 24
Finished May 05 01:10:52 PM PDT 24
Peak memory 183532 kb
Host smart-1a7af42b-a9e1-4d28-9418-8a1ad7692dcc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980763683 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_a
ll.2980763683
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.1968752603
Short name T7
Test name
Test status
Simulation time 113861115130 ps
CPU time 218.46 seconds
Started May 05 01:08:28 PM PDT 24
Finished May 05 01:12:08 PM PDT 24
Peak memory 198400 kb
Host smart-4e065b56-39bb-49cb-8ec2-fbd864abd55d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968752603 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.1968752603
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.aon_timer_jump.228376601
Short name T29
Test name
Test status
Simulation time 580788630 ps
CPU time 1.39 seconds
Started May 05 01:08:27 PM PDT 24
Finished May 05 01:08:29 PM PDT 24
Peak memory 183492 kb
Host smart-136caca1-b66a-42a8-96a9-40db14f809df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228376601 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.228376601
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.1385035742
Short name T184
Test name
Test status
Simulation time 32306270014 ps
CPU time 13.02 seconds
Started May 05 01:08:28 PM PDT 24
Finished May 05 01:08:41 PM PDT 24
Peak memory 191764 kb
Host smart-af8238da-217b-4d49-8b3e-7918fb7d215a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385035742 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.1385035742
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.2754543186
Short name T220
Test name
Test status
Simulation time 363701216 ps
CPU time 0.8 seconds
Started May 05 01:08:32 PM PDT 24
Finished May 05 01:08:33 PM PDT 24
Peak memory 183484 kb
Host smart-ce39b96c-7a8a-4959-a70b-e461d85efe16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754543186 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.2754543186
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.1943596022
Short name T180
Test name
Test status
Simulation time 18105205413 ps
CPU time 30.31 seconds
Started May 05 01:08:27 PM PDT 24
Finished May 05 01:08:58 PM PDT 24
Peak memory 193656 kb
Host smart-9f4d76f3-8483-480f-b756-95ef93a4019b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943596022 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_a
ll.1943596022
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.3133157542
Short name T243
Test name
Test status
Simulation time 224791809345 ps
CPU time 497.57 seconds
Started May 05 01:08:28 PM PDT 24
Finished May 05 01:16:47 PM PDT 24
Peak memory 198448 kb
Host smart-e04a833f-96b7-4e64-8de8-3f7c9f287e20
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133157542 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.3133157542
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.aon_timer_jump.1951710973
Short name T229
Test name
Test status
Simulation time 376326397 ps
CPU time 1.02 seconds
Started May 05 01:08:38 PM PDT 24
Finished May 05 01:08:40 PM PDT 24
Peak memory 183396 kb
Host smart-b08d6760-9fd8-4fb1-85df-c7f03b84be78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951710973 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.1951710973
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.1966896235
Short name T23
Test name
Test status
Simulation time 2900996023 ps
CPU time 4.86 seconds
Started May 05 01:08:31 PM PDT 24
Finished May 05 01:08:37 PM PDT 24
Peak memory 183564 kb
Host smart-ee2d6e9f-671a-4d03-96b2-f0ea7826a8a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966896235 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.1966896235
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.1252791420
Short name T30
Test name
Test status
Simulation time 504639001 ps
CPU time 0.9 seconds
Started May 05 01:08:27 PM PDT 24
Finished May 05 01:08:28 PM PDT 24
Peak memory 183496 kb
Host smart-b0f36fbd-1d35-410e-9a08-f83d300afa13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252791420 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.1252791420
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.618263185
Short name T254
Test name
Test status
Simulation time 9227577101 ps
CPU time 10.22 seconds
Started May 05 01:08:28 PM PDT 24
Finished May 05 01:08:39 PM PDT 24
Peak memory 195296 kb
Host smart-60dbefad-43f9-45d4-bd5b-9e1db8c1744b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618263185 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_al
l.618263185
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.524210121
Short name T43
Test name
Test status
Simulation time 390963282331 ps
CPU time 958.05 seconds
Started May 05 01:08:22 PM PDT 24
Finished May 05 01:24:21 PM PDT 24
Peak memory 204848 kb
Host smart-bee6fcc5-b827-4688-a2e6-381502051730
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524210121 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.524210121
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.aon_timer_jump.738113422
Short name T102
Test name
Test status
Simulation time 413651582 ps
CPU time 1.22 seconds
Started May 05 01:08:39 PM PDT 24
Finished May 05 01:08:41 PM PDT 24
Peak memory 183468 kb
Host smart-f8fd2759-1fbd-47aa-865d-77342e742627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738113422 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.738113422
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.382224988
Short name T164
Test name
Test status
Simulation time 44302390345 ps
CPU time 36.52 seconds
Started May 05 01:08:28 PM PDT 24
Finished May 05 01:09:05 PM PDT 24
Peak memory 191724 kb
Host smart-1d3ba901-3e66-4a68-8d23-62e64091bd9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382224988 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.382224988
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.1901599273
Short name T181
Test name
Test status
Simulation time 585507083 ps
CPU time 0.78 seconds
Started May 05 01:08:40 PM PDT 24
Finished May 05 01:08:41 PM PDT 24
Peak memory 183480 kb
Host smart-4a5c83ba-c4c9-4cfd-b76d-d3cddc234765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901599273 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.1901599273
Directory /workspace/9.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.861195807
Short name T268
Test name
Test status
Simulation time 91473954155 ps
CPU time 126.03 seconds
Started May 05 01:08:30 PM PDT 24
Finished May 05 01:10:36 PM PDT 24
Peak memory 194460 kb
Host smart-a8019639-d196-4e55-8370-993ee4c2efa4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861195807 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_al
l.861195807
Directory /workspace/9.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.2123560273
Short name T272
Test name
Test status
Simulation time 86188549914 ps
CPU time 97.32 seconds
Started May 05 01:08:29 PM PDT 24
Finished May 05 01:10:07 PM PDT 24
Peak memory 206680 kb
Host smart-f490c60a-a49f-4ad7-9a87-4d4652762f76
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123560273 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.2123560273
Directory /workspace/9.aon_timer_stress_all_with_rand_reset/latest
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