Unified Coverage Report :: Group :: aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

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Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
24.86	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv

Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	173	130	43	24.86

Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
bark_thold_cp	34	32	2	5.88	100	1	1	0
bite_thold_cp	34	32	2	5.88	100	1	1	0
pause_in_sleep_cp	2	1	1	50.00	100	1	1	2
prescale_cp	34	1	33	97.06	100	1	1	0
wdog_regwen_cp	2	0	2	100.00	100	1	1	2
wkup_cause_cp	1	0	1	100.00	100	1	1	0
wkup_thold_cp	66	64	2	3.03	100	1	1	0

Summary for Variable bark_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	32	2	5.88

User Defined Bins for bark_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bark_max	0	1	1
bark[1]	0	1	1
bark[2]	0	1	1
bark[3]	0	1	1
bark[4]	0	1	1
bark[5]	0	1	1
bark[6]	0	1	1
bark[7]	0	1	1
bark[8]	0	1	1
bark[9]	0	1	1
bark[10]	0	1	1
bark[11]	0	1	1
bark[12]	0	1	1
bark[13]	0	1	1
bark[14]	0	1	1
bark[15]	0	1	1
bark[16]	0	1	1
bark[17]	0	1	1
bark[18]	0	1	1
bark[19]	0	1	1
bark[20]	0	1	1
bark[21]	0	1	1
bark[22]	0	1	1
bark[23]	0	1	1
bark[24]	0	1	1
bark[25]	0	1	1
bark[26]	0	1	1
bark[27]	0	1	1
bark[28]	0	1	1
bark[29]	0	1	1
bark[30]	0	1	1
bark[31]	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bark[0]	48537	1		T1	14		T2	14		T3	14
bark_0	4430	1		T1	7		T2	7		T3	7

Summary for Variable bite_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	32	2	5.88

User Defined Bins for bite_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bite_max	0	1	1
bite[1]	0	1	1
bite[2]	0	1	1
bite[3]	0	1	1
bite[4]	0	1	1
bite[5]	0	1	1
bite[6]	0	1	1
bite[7]	0	1	1
bite[8]	0	1	1
bite[9]	0	1	1
bite[10]	0	1	1
bite[11]	0	1	1
bite[12]	0	1	1
bite[13]	0	1	1
bite[14]	0	1	1
bite[15]	0	1	1
bite[16]	0	1	1
bite[17]	0	1	1
bite[18]	0	1	1
bite[19]	0	1	1
bite[20]	0	1	1
bite[21]	0	1	1
bite[22]	0	1	1
bite[23]	0	1	1
bite[24]	0	1	1
bite[25]	0	1	1
bite[26]	0	1	1
bite[27]	0	1	1
bite[28]	0	1	1
bite[29]	0	1	1
bite[30]	0	1	1
bite[31]	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bite[0]	48063	1		T1	13		T2	13		T3	13
bite_0	4904	1		T1	8		T2	8		T3	8

Summary for Variable pause_in_sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for pause_in_sleep_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
[auto[1]]	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	52967	1		T1	21		T2	21		T3	21

Summary for Variable prescale_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for prescale_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prescale_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
prescale[0]	1235	1		T97	9		T35	19		T98	9
prescale[1]	1058	1		T16	23		T21	107		T33	19
prescale[2]	1022	1		T16	19		T21	68		T99	19
prescale[3]	941	1		T20	111		T100	28		T44	56
prescale[4]	650	1		T101	9		T44	2		T102	19
prescale[5]	1113	1		T20	37		T21	19		T103	19
prescale[6]	493	1		T8	2		T20	20		T21	79
prescale[7]	540	1		T17	23		T20	2		T104	24
prescale[8]	582	1		T15	23		T30	23		T105	19
prescale[9]	889	1		T20	19		T21	19		T45	24
prescale[10]	516	1		T21	79		T44	9		T106	40
prescale[11]	1139	1		T21	123		T27	20		T45	93
prescale[12]	678	1		T18	37		T35	18		T20	2
prescale[13]	866	1		T16	19		T18	19		T20	67
prescale[14]	685	1		T8	23		T100	19		T105	40
prescale[15]	580	1		T105	93		T44	52		T79	2
prescale[16]	856	1		T19	23		T107	18		T33	9
prescale[17]	1046	1		T18	14		T20	57		T100	61
prescale[18]	829	1		T8	40		T103	53		T30	123
prescale[19]	1109	1		T20	19		T104	78		T108	9
prescale[20]	763	1		T8	2		T18	40		T20	94
prescale[21]	969	1		T16	19		T18	32		T21	63
prescale[22]	1208	1		T7	9		T15	44		T20	30
prescale[23]	634	1		T17	28		T19	59		T20	67
prescale[24]	767	1		T104	19		T34	29		T44	2
prescale[25]	1142	1		T8	2		T20	2		T34	27
prescale[26]	863	1		T8	49		T19	37		T47	9
prescale[27]	824	1		T16	37		T100	40		T27	39
prescale[28]	875	1		T16	19		T19	28		T33	2
prescale[29]	745	1		T20	19		T104	40		T30	63
prescale[30]	690	1		T21	40		T30	23		T44	19
prescale[31]	754	1		T17	59		T34	42		T44	19
prescale_0	25906	1		T1	21		T2	21		T3	21

Summary for Variable wdog_regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wdog_regwen_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	39792	1		T1	21		T2	9		T3	21
auto[1]	13175	1		T2	12		T5	12		T7	10

Summary for Variable wkup_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for wkup_cause_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup_cause_cleared	52967	1		T1	21		T2	21		T3	21

Summary for Variable wkup_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	66	64	2	3.03

User Defined Bins for wkup_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
wkup_max	0	1	1
wkup[1]	0	1	1
wkup[2]	0	1	1
wkup[3]	0	1	1
wkup[4]	0	1	1
wkup[5]	0	1	1
wkup[6]	0	1	1
wkup[7]	0	1	1
wkup[8]	0	1	1
wkup[9]	0	1	1
wkup[10]	0	1	1
wkup[11]	0	1	1
wkup[12]	0	1	1
wkup[13]	0	1	1
wkup[14]	0	1	1
wkup[15]	0	1	1
wkup[16]	0	1	1
wkup[17]	0	1	1
wkup[18]	0	1	1
wkup[19]	0	1	1
wkup[20]	0	1	1
wkup[21]	0	1	1
wkup[22]	0	1	1
wkup[23]	0	1	1
wkup[24]	0	1	1
wkup[25]	0	1	1
wkup[26]	0	1	1
wkup[27]	0	1	1
wkup[28]	0	1	1
wkup[29]	0	1	1
wkup[30]	0	1	1
wkup[31]	0	1	1
wkup[32]	0	1	1
wkup[33]	0	1	1
wkup[34]	0	1	1
wkup[35]	0	1	1
wkup[36]	0	1	1
wkup[37]	0	1	1
wkup[38]	0	1	1
wkup[39]	0	1	1
wkup[40]	0	1	1
wkup[41]	0	1	1
wkup[42]	0	1	1
wkup[43]	0	1	1
wkup[44]	0	1	1
wkup[45]	0	1	1
wkup[46]	0	1	1
wkup[47]	0	1	1
wkup[48]	0	1	1
wkup[49]	0	1	1
wkup[50]	0	1	1
wkup[51]	0	1	1
wkup[52]	0	1	1
wkup[53]	0	1	1
wkup[54]	0	1	1
wkup[55]	0	1	1
wkup[56]	0	1	1
wkup[57]	0	1	1
wkup[58]	0	1	1
wkup[59]	0	1	1
wkup[60]	0	1	1
wkup[61]	0	1	1
wkup[62]	0	1	1
wkup[63]	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup[0]	49468	1		T1	16		T2	16		T3	16
wkup_0	3499	1		T1	5		T2	5		T3	5

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