Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
92.98 99.25 93.67 100.00 98.40 99.51 67.06


Total test records in report: 422
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T282 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.1142603699 May 09 02:06:54 PM PDT 24 May 09 02:06:56 PM PDT 24 531864219 ps
T37 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.2706258003 May 09 02:07:27 PM PDT 24 May 09 02:07:29 PM PDT 24 448812813 ps
T38 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.3957356951 May 09 02:07:04 PM PDT 24 May 09 02:07:06 PM PDT 24 608461966 ps
T283 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.3260866327 May 09 02:07:48 PM PDT 24 May 09 02:07:51 PM PDT 24 407281871 ps
T284 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.2418789000 May 09 02:06:47 PM PDT 24 May 09 02:06:50 PM PDT 24 337425802 ps
T285 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.2242428729 May 09 02:07:27 PM PDT 24 May 09 02:07:30 PM PDT 24 310255111 ps
T286 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.3127608243 May 09 02:06:59 PM PDT 24 May 09 02:07:01 PM PDT 24 401987963 ps
T287 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.1759433363 May 09 02:06:36 PM PDT 24 May 09 02:06:41 PM PDT 24 581865090 ps
T288 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.763253861 May 09 02:07:29 PM PDT 24 May 09 02:07:33 PM PDT 24 490001839 ps
T289 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.895682988 May 09 02:07:37 PM PDT 24 May 09 02:07:40 PM PDT 24 373012068 ps
T290 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.2782578166 May 09 02:07:04 PM PDT 24 May 09 02:07:07 PM PDT 24 486350383 ps
T291 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.2330406282 May 09 02:07:04 PM PDT 24 May 09 02:07:07 PM PDT 24 484130728 ps
T42 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.2208771127 May 09 02:07:19 PM PDT 24 May 09 02:07:21 PM PDT 24 325653076 ps
T292 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.3202854257 May 09 02:07:04 PM PDT 24 May 09 02:07:06 PM PDT 24 520652780 ps
T71 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.2136728869 May 09 02:06:46 PM PDT 24 May 09 02:06:48 PM PDT 24 557773922 ps
T293 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.3165689070 May 09 02:06:35 PM PDT 24 May 09 02:06:38 PM PDT 24 498651972 ps
T43 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.20060073 May 09 02:07:28 PM PDT 24 May 09 02:07:31 PM PDT 24 543967309 ps
T72 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.126322865 May 09 02:07:39 PM PDT 24 May 09 02:07:42 PM PDT 24 447970596 ps
T73 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.79858570 May 09 02:07:29 PM PDT 24 May 09 02:07:34 PM PDT 24 1236749694 ps
T39 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.4187938420 May 09 02:07:05 PM PDT 24 May 09 02:07:10 PM PDT 24 4829916638 ps
T294 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.3207086847 May 09 02:06:36 PM PDT 24 May 09 02:06:40 PM PDT 24 322278863 ps
T295 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.4184786450 May 09 02:07:40 PM PDT 24 May 09 02:07:43 PM PDT 24 402903142 ps
T296 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.1639565702 May 09 02:07:38 PM PDT 24 May 09 02:07:41 PM PDT 24 359737833 ps
T297 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.647016370 May 09 02:07:48 PM PDT 24 May 09 02:07:50 PM PDT 24 422800654 ps
T298 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.1034522086 May 09 02:07:38 PM PDT 24 May 09 02:07:41 PM PDT 24 524519671 ps
T40 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.3516511376 May 09 02:07:27 PM PDT 24 May 09 02:07:32 PM PDT 24 7927030820 ps
T299 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.2611570237 May 09 02:07:40 PM PDT 24 May 09 02:07:43 PM PDT 24 397499956 ps
T41 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.1413906624 May 09 02:06:45 PM PDT 24 May 09 02:06:52 PM PDT 24 3767733763 ps
T300 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.550243949 May 09 02:06:56 PM PDT 24 May 09 02:07:00 PM PDT 24 461306404 ps
T74 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.2262125052 May 09 02:07:06 PM PDT 24 May 09 02:07:10 PM PDT 24 1138179147 ps
T301 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.1746056758 May 09 02:07:37 PM PDT 24 May 09 02:07:40 PM PDT 24 330917558 ps
T302 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.2216013713 May 09 02:07:43 PM PDT 24 May 09 02:07:44 PM PDT 24 489023127 ps
T303 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.349521386 May 09 02:07:27 PM PDT 24 May 09 02:07:31 PM PDT 24 604774453 ps
T109 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.3570382041 May 09 02:07:39 PM PDT 24 May 09 02:07:44 PM PDT 24 4192131426 ps
T304 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.3956661709 May 09 02:06:44 PM PDT 24 May 09 02:06:46 PM PDT 24 534739187 ps
T305 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.57098721 May 09 02:07:38 PM PDT 24 May 09 02:07:41 PM PDT 24 340392134 ps
T306 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.3278068709 May 09 02:06:54 PM PDT 24 May 09 02:07:01 PM PDT 24 3782896187 ps
T75 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.1794886256 May 09 02:07:08 PM PDT 24 May 09 02:07:11 PM PDT 24 354756638 ps
T307 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.1899343395 May 09 02:07:07 PM PDT 24 May 09 02:07:11 PM PDT 24 503203964 ps
T308 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.1762112695 May 09 02:07:37 PM PDT 24 May 09 02:07:40 PM PDT 24 511837945 ps
T309 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.3996772655 May 09 02:07:38 PM PDT 24 May 09 02:07:41 PM PDT 24 491931010 ps
T76 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.3360371115 May 09 02:07:36 PM PDT 24 May 09 02:07:37 PM PDT 24 456403985 ps
T310 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.584271695 May 09 02:06:47 PM PDT 24 May 09 02:06:50 PM PDT 24 476576489 ps
T311 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.2590718914 May 09 02:06:46 PM PDT 24 May 09 02:06:48 PM PDT 24 320372564 ps
T312 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.1229147996 May 09 02:06:45 PM PDT 24 May 09 02:06:47 PM PDT 24 483182154 ps
T313 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.3002832590 May 09 02:06:35 PM PDT 24 May 09 02:06:41 PM PDT 24 548272156 ps
T77 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.2003643889 May 09 02:07:37 PM PDT 24 May 09 02:07:40 PM PDT 24 2695680864 ps
T314 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.2581373359 May 09 02:07:08 PM PDT 24 May 09 02:07:10 PM PDT 24 328078182 ps
T315 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.910261451 May 09 02:07:39 PM PDT 24 May 09 02:07:42 PM PDT 24 422740007 ps
T59 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.1709147598 May 09 02:07:39 PM PDT 24 May 09 02:07:42 PM PDT 24 277942378 ps
T316 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.510980891 May 09 02:06:47 PM PDT 24 May 09 02:07:02 PM PDT 24 8683619497 ps
T317 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.2169883163 May 09 02:07:39 PM PDT 24 May 09 02:07:42 PM PDT 24 448972160 ps
T318 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.3253739008 May 09 02:07:40 PM PDT 24 May 09 02:07:43 PM PDT 24 388696538 ps
T60 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.2413870887 May 09 02:06:59 PM PDT 24 May 09 02:07:01 PM PDT 24 603249097 ps
T61 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.1205467383 May 09 02:06:58 PM PDT 24 May 09 02:07:21 PM PDT 24 13692093096 ps
T319 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.4261116794 May 09 02:07:48 PM PDT 24 May 09 02:07:50 PM PDT 24 337047536 ps
T320 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.1952611724 May 09 02:07:15 PM PDT 24 May 09 02:07:18 PM PDT 24 1257354860 ps
T321 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.908988108 May 09 02:07:15 PM PDT 24 May 09 02:07:19 PM PDT 24 3800564209 ps
T62 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.1381369126 May 09 02:06:47 PM PDT 24 May 09 02:06:50 PM PDT 24 1286762474 ps
T322 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.1290958001 May 09 02:07:28 PM PDT 24 May 09 02:07:31 PM PDT 24 462557464 ps
T323 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.842050178 May 09 02:07:48 PM PDT 24 May 09 02:07:50 PM PDT 24 390257385 ps
T324 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.965671571 May 09 02:07:38 PM PDT 24 May 09 02:07:42 PM PDT 24 4450379974 ps
T325 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.3544025982 May 09 02:06:46 PM PDT 24 May 09 02:06:49 PM PDT 24 505890689 ps
T326 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.133684505 May 09 02:07:27 PM PDT 24 May 09 02:07:29 PM PDT 24 508499791 ps
T63 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.2721146428 May 09 02:06:55 PM PDT 24 May 09 02:06:57 PM PDT 24 419827084 ps
T64 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.2202504462 May 09 02:06:47 PM PDT 24 May 09 02:06:50 PM PDT 24 1321000655 ps
T327 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.2828931492 May 09 02:07:48 PM PDT 24 May 09 02:07:50 PM PDT 24 341702819 ps
T328 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.3703786478 May 09 02:07:38 PM PDT 24 May 09 02:07:40 PM PDT 24 372206469 ps
T329 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.3002916659 May 09 02:07:29 PM PDT 24 May 09 02:07:46 PM PDT 24 7845404016 ps
T65 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.3514830576 May 09 02:06:47 PM PDT 24 May 09 02:06:59 PM PDT 24 11583786749 ps
T330 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.1302513916 May 09 02:07:29 PM PDT 24 May 09 02:07:33 PM PDT 24 458887995 ps
T331 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.1813922756 May 09 02:07:37 PM PDT 24 May 09 02:07:39 PM PDT 24 283429711 ps
T332 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.3525983966 May 09 02:06:36 PM PDT 24 May 09 02:06:41 PM PDT 24 461770238 ps
T333 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.1086914941 May 09 02:07:40 PM PDT 24 May 09 02:07:43 PM PDT 24 338061886 ps
T334 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.1352014839 May 09 02:07:48 PM PDT 24 May 09 02:07:50 PM PDT 24 300462799 ps
T335 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.221953604 May 09 02:07:05 PM PDT 24 May 09 02:07:12 PM PDT 24 4432218970 ps
T336 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.1912360578 May 09 02:07:15 PM PDT 24 May 09 02:07:19 PM PDT 24 398070285 ps
T337 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.2020505802 May 09 02:06:57 PM PDT 24 May 09 02:07:01 PM PDT 24 2904602241 ps
T338 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.2108084136 May 09 02:06:35 PM PDT 24 May 09 02:06:39 PM PDT 24 707309756 ps
T339 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.156364988 May 09 02:06:45 PM PDT 24 May 09 02:06:48 PM PDT 24 1197151292 ps
T340 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.32471887 May 09 02:07:30 PM PDT 24 May 09 02:07:36 PM PDT 24 622794049 ps
T341 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.3776553380 May 09 02:06:55 PM PDT 24 May 09 02:07:05 PM PDT 24 4186143592 ps
T68 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.4054271721 May 09 02:06:35 PM PDT 24 May 09 02:06:43 PM PDT 24 8554320578 ps
T342 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.3677863717 May 09 02:07:17 PM PDT 24 May 09 02:07:19 PM PDT 24 474733252 ps
T343 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.2447310400 May 09 02:07:39 PM PDT 24 May 09 02:07:43 PM PDT 24 420493908 ps
T344 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.2976503965 May 09 02:07:28 PM PDT 24 May 09 02:07:32 PM PDT 24 533328060 ps
T66 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.3271881543 May 09 02:06:46 PM PDT 24 May 09 02:07:01 PM PDT 24 4216667346 ps
T345 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.3400548781 May 09 02:06:47 PM PDT 24 May 09 02:06:50 PM PDT 24 658347861 ps
T346 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.3323126596 May 09 02:07:05 PM PDT 24 May 09 02:07:08 PM PDT 24 4244670315 ps
T347 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.1141840822 May 09 02:07:47 PM PDT 24 May 09 02:07:49 PM PDT 24 371092520 ps
T348 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.3787496616 May 09 02:06:55 PM PDT 24 May 09 02:06:58 PM PDT 24 489652312 ps
T349 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.1200271066 May 09 02:07:27 PM PDT 24 May 09 02:07:30 PM PDT 24 388961242 ps
T350 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.2838788927 May 09 02:07:37 PM PDT 24 May 09 02:07:40 PM PDT 24 281179973 ps
T69 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.2801684454 May 09 02:07:27 PM PDT 24 May 09 02:07:30 PM PDT 24 335552152 ps
T351 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.3135067779 May 09 02:07:29 PM PDT 24 May 09 02:07:34 PM PDT 24 338108433 ps
T113 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.3338300778 May 09 02:07:29 PM PDT 24 May 09 02:07:45 PM PDT 24 8295489239 ps
T352 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.1071816472 May 09 02:07:36 PM PDT 24 May 09 02:07:38 PM PDT 24 542931325 ps
T353 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.2907165191 May 09 02:07:04 PM PDT 24 May 09 02:07:07 PM PDT 24 1533691542 ps
T110 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.4050704004 May 09 02:07:16 PM PDT 24 May 09 02:07:31 PM PDT 24 8031581168 ps
T354 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.4262691017 May 09 02:06:48 PM PDT 24 May 09 02:06:53 PM PDT 24 1456139623 ps
T355 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.3851652580 May 09 02:07:30 PM PDT 24 May 09 02:07:34 PM PDT 24 385097558 ps
T356 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.970041397 May 09 02:07:30 PM PDT 24 May 09 02:07:35 PM PDT 24 725944546 ps
T357 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.3292123973 May 09 02:07:16 PM PDT 24 May 09 02:07:18 PM PDT 24 311205822 ps
T358 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.3395488148 May 09 02:06:48 PM PDT 24 May 09 02:06:50 PM PDT 24 357582823 ps
T359 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.4134099932 May 09 02:07:39 PM PDT 24 May 09 02:07:45 PM PDT 24 2030171828 ps
T360 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.192678961 May 09 02:07:37 PM PDT 24 May 09 02:07:40 PM PDT 24 352778413 ps
T361 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.1506075423 May 09 02:06:45 PM PDT 24 May 09 02:06:47 PM PDT 24 464626708 ps
T362 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.1423194892 May 09 02:07:46 PM PDT 24 May 09 02:07:48 PM PDT 24 286776501 ps
T363 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.780175712 May 09 02:07:25 PM PDT 24 May 09 02:07:27 PM PDT 24 317818828 ps
T364 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.3898556173 May 09 02:06:55 PM PDT 24 May 09 02:06:58 PM PDT 24 622849015 ps
T365 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.4096555644 May 09 02:07:36 PM PDT 24 May 09 02:07:39 PM PDT 24 352076845 ps
T366 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.2247382369 May 09 02:06:36 PM PDT 24 May 09 02:06:40 PM PDT 24 482596493 ps
T70 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.3260610287 May 09 02:06:46 PM PDT 24 May 09 02:06:52 PM PDT 24 6779592346 ps
T367 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.2925813418 May 09 02:07:48 PM PDT 24 May 09 02:07:51 PM PDT 24 506602006 ps
T368 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.1981885935 May 09 02:06:46 PM PDT 24 May 09 02:06:49 PM PDT 24 545105723 ps
T369 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.3138900428 May 09 02:07:39 PM PDT 24 May 09 02:07:42 PM PDT 24 1548925882 ps
T370 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.2120433545 May 09 02:06:45 PM PDT 24 May 09 02:06:47 PM PDT 24 358770375 ps
T371 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.230358472 May 09 02:07:29 PM PDT 24 May 09 02:07:32 PM PDT 24 362758841 ps
T372 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.1988967426 May 09 02:07:38 PM PDT 24 May 09 02:07:40 PM PDT 24 447288940 ps
T373 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.3284542504 May 09 02:07:40 PM PDT 24 May 09 02:07:44 PM PDT 24 469294901 ps
T374 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.1514874378 May 09 02:07:15 PM PDT 24 May 09 02:07:20 PM PDT 24 1426044467 ps
T375 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.3559727640 May 09 02:07:47 PM PDT 24 May 09 02:07:48 PM PDT 24 408544806 ps
T376 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.2956106633 May 09 02:06:45 PM PDT 24 May 09 02:06:49 PM PDT 24 4604583744 ps
T67 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.46140347 May 09 02:06:45 PM PDT 24 May 09 02:06:47 PM PDT 24 399957615 ps
T377 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.284844604 May 09 02:07:30 PM PDT 24 May 09 02:07:35 PM PDT 24 409480465 ps
T111 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.2026373167 May 09 02:07:27 PM PDT 24 May 09 02:07:31 PM PDT 24 4487016039 ps
T378 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.3643084220 May 09 02:07:30 PM PDT 24 May 09 02:07:34 PM PDT 24 1992998181 ps
T379 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.3176065049 May 09 02:07:28 PM PDT 24 May 09 02:07:32 PM PDT 24 1412291877 ps
T380 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.900702084 May 09 02:07:28 PM PDT 24 May 09 02:07:32 PM PDT 24 1467894993 ps
T381 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.2195389942 May 09 02:07:14 PM PDT 24 May 09 02:07:16 PM PDT 24 507083835 ps
T382 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.68367497 May 09 02:07:38 PM PDT 24 May 09 02:07:42 PM PDT 24 507578889 ps
T383 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.2394945868 May 09 02:07:38 PM PDT 24 May 09 02:07:43 PM PDT 24 4191470108 ps
T384 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.1518976420 May 09 02:06:55 PM PDT 24 May 09 02:06:57 PM PDT 24 550088138 ps
T385 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.85177783 May 09 02:07:40 PM PDT 24 May 09 02:07:44 PM PDT 24 439842699 ps
T386 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.1544208857 May 09 02:07:06 PM PDT 24 May 09 02:07:09 PM PDT 24 490788729 ps
T387 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.354924611 May 09 02:07:05 PM PDT 24 May 09 02:07:08 PM PDT 24 362486639 ps
T388 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.2109118885 May 09 02:07:31 PM PDT 24 May 09 02:07:35 PM PDT 24 416037311 ps
T389 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.3624263368 May 09 02:07:30 PM PDT 24 May 09 02:07:34 PM PDT 24 339550260 ps
T390 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.2807327497 May 09 02:06:35 PM PDT 24 May 09 02:06:51 PM PDT 24 8946411657 ps
T391 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.3529889627 May 09 02:07:48 PM PDT 24 May 09 02:07:50 PM PDT 24 499344917 ps
T392 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.1546207940 May 09 02:06:53 PM PDT 24 May 09 02:06:55 PM PDT 24 1365961871 ps
T393 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.1089489569 May 09 02:07:29 PM PDT 24 May 09 02:07:33 PM PDT 24 335470883 ps
T394 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.633807863 May 09 02:06:49 PM PDT 24 May 09 02:06:51 PM PDT 24 990193366 ps
T395 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.3133250799 May 09 02:07:07 PM PDT 24 May 09 02:07:10 PM PDT 24 509972755 ps
T396 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.1596257053 May 09 02:07:48 PM PDT 24 May 09 02:07:51 PM PDT 24 369130261 ps
T397 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.1410308578 May 09 02:06:55 PM PDT 24 May 09 02:06:59 PM PDT 24 1378695968 ps
T398 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.3985306726 May 09 02:06:54 PM PDT 24 May 09 02:06:59 PM PDT 24 1490540868 ps
T399 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.881399633 May 09 02:07:15 PM PDT 24 May 09 02:07:18 PM PDT 24 532989074 ps
T400 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.3738619176 May 09 02:06:56 PM PDT 24 May 09 02:06:59 PM PDT 24 329505140 ps
T401 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.1416690848 May 09 02:06:46 PM PDT 24 May 09 02:06:48 PM PDT 24 344144794 ps
T112 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.1359832595 May 09 02:07:28 PM PDT 24 May 09 02:07:32 PM PDT 24 8739502473 ps
T402 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.2460332928 May 09 02:07:38 PM PDT 24 May 09 02:07:44 PM PDT 24 8132294522 ps
T403 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.1874325388 May 09 02:07:38 PM PDT 24 May 09 02:07:41 PM PDT 24 391477616 ps
T404 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.1317797534 May 09 02:06:45 PM PDT 24 May 09 02:06:47 PM PDT 24 481456689 ps
T405 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.4208939217 May 09 02:07:36 PM PDT 24 May 09 02:07:39 PM PDT 24 283656691 ps
T406 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.1178484125 May 09 02:07:40 PM PDT 24 May 09 02:07:49 PM PDT 24 2625486793 ps
T407 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.387594083 May 09 02:07:28 PM PDT 24 May 09 02:07:32 PM PDT 24 511394960 ps
T408 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.1743455982 May 09 02:06:34 PM PDT 24 May 09 02:06:37 PM PDT 24 541977182 ps
T409 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.1717811353 May 09 02:06:55 PM PDT 24 May 09 02:06:58 PM PDT 24 537632282 ps
T410 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.2027035111 May 09 02:06:35 PM PDT 24 May 09 02:06:41 PM PDT 24 2050101455 ps
T411 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.3243671804 May 09 02:06:45 PM PDT 24 May 09 02:06:48 PM PDT 24 1167526466 ps
T412 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.3953657023 May 09 02:07:29 PM PDT 24 May 09 02:07:33 PM PDT 24 460536408 ps
T413 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.2046375792 May 09 02:07:49 PM PDT 24 May 09 02:07:51 PM PDT 24 385988637 ps
T414 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.666321930 May 09 02:06:56 PM PDT 24 May 09 02:06:58 PM PDT 24 484395503 ps
T415 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.2618198972 May 09 02:07:27 PM PDT 24 May 09 02:07:29 PM PDT 24 1310741929 ps
T416 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.1396729582 May 09 02:06:55 PM PDT 24 May 09 02:06:58 PM PDT 24 537233041 ps
T417 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.2843107256 May 09 02:07:06 PM PDT 24 May 09 02:07:09 PM PDT 24 712731959 ps
T418 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.2230180406 May 09 02:07:30 PM PDT 24 May 09 02:07:34 PM PDT 24 433607486 ps
T419 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.1824296260 May 09 02:06:45 PM PDT 24 May 09 02:06:48 PM PDT 24 486773135 ps
T420 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.1340838655 May 09 02:06:35 PM PDT 24 May 09 02:06:38 PM PDT 24 1156872914 ps
T421 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.1701183598 May 09 02:07:46 PM PDT 24 May 09 02:07:48 PM PDT 24 459636220 ps
T422 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.4137540638 May 09 02:06:47 PM PDT 24 May 09 02:06:49 PM PDT 24 296845821 ps

Test location /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.2508718499
Short name T8
Test name
Test status
Simulation time 195710538974 ps
CPU time 612.53 seconds
Started May 09 02:05:10 PM PDT 24
Finished May 09 02:15:24 PM PDT 24
Peak memory 200208 kb
Host smart-f9ebeaca-228a-475e-8821-588cc1542a42
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508718499 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.2508718499
Directory /workspace/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.3101233800
Short name T15
Test name
Test status
Simulation time 76110132551 ps
CPU time 8.23 seconds
Started May 09 02:05:09 PM PDT 24
Finished May 09 02:05:18 PM PDT 24
Peak memory 195648 kb
Host smart-1ccb6919-5e35-4302-8fce-9a224b5ae502
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101233800 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_
all.3101233800
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.4187938420
Short name T39
Test name
Test status
Simulation time 4829916638 ps
CPU time 2.42 seconds
Started May 09 02:07:05 PM PDT 24
Finished May 09 02:07:10 PM PDT 24
Peak memory 197680 kb
Host smart-537186e1-a6f2-4c44-ba05-30761b080aec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187938420 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl
_intg_err.4187938420
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.3848094868
Short name T44
Test name
Test status
Simulation time 89464654256 ps
CPU time 599.89 seconds
Started May 09 02:04:38 PM PDT 24
Finished May 09 02:14:40 PM PDT 24
Peak memory 199064 kb
Host smart-eee34e52-02cd-4ebb-9bcc-6d870d4f4a3d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848094868 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.3848094868
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.3231455524
Short name T48
Test name
Test status
Simulation time 242788016731 ps
CPU time 325.99 seconds
Started May 09 02:05:04 PM PDT 24
Finished May 09 02:10:31 PM PDT 24
Peak memory 198560 kb
Host smart-6eede1fd-89a8-41ba-b862-0b632fd5a731
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231455524 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.3231455524
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.4249783871
Short name T16
Test name
Test status
Simulation time 290631125813 ps
CPU time 109.75 seconds
Started May 09 02:05:41 PM PDT 24
Finished May 09 02:07:33 PM PDT 24
Peak memory 183664 kb
Host smart-48190432-f79b-4a09-a458-b24b6f809cb0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249783871 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_
all.4249783871
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.1112849898
Short name T26
Test name
Test status
Simulation time 3962830895 ps
CPU time 7.07 seconds
Started May 09 02:04:02 PM PDT 24
Finished May 09 02:04:10 PM PDT 24
Peak memory 214972 kb
Host smart-b426cfa0-8d44-4d2d-8486-3fcf20953e60
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112849898 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.1112849898
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/31.aon_timer_jump.3080707508
Short name T11
Test name
Test status
Simulation time 486602455 ps
CPU time 0.77 seconds
Started May 09 02:05:31 PM PDT 24
Finished May 09 02:05:32 PM PDT 24
Peak memory 183552 kb
Host smart-1c5081bb-90d6-4ed0-9b93-04fdaeb817ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080707508 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.3080707508
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.1520376869
Short name T20
Test name
Test status
Simulation time 54121485473 ps
CPU time 582.78 seconds
Started May 09 02:05:28 PM PDT 24
Finished May 09 02:15:13 PM PDT 24
Peak memory 198548 kb
Host smart-eebebc49-f5ef-47a1-b412-923838807559
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520376869 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.1520376869
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.1709147598
Short name T59
Test name
Test status
Simulation time 277942378 ps
CPU time 0.93 seconds
Started May 09 02:07:39 PM PDT 24
Finished May 09 02:07:42 PM PDT 24
Peak memory 192956 kb
Host smart-b1aa6434-8919-43b9-8e64-c9b99d872c1c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709147598 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.1709147598
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.1413906624
Short name T41
Test name
Test status
Simulation time 3767733763 ps
CPU time 6.44 seconds
Started May 09 02:06:45 PM PDT 24
Finished May 09 02:06:52 PM PDT 24
Peak memory 197680 kb
Host smart-481d242f-d767-4a94-b8ce-493246029d4c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413906624 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl
_intg_err.1413906624
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.2026373167
Short name T111
Test name
Test status
Simulation time 4487016039 ps
CPU time 2.12 seconds
Started May 09 02:07:27 PM PDT 24
Finished May 09 02:07:31 PM PDT 24
Peak memory 196456 kb
Host smart-a95005a8-4141-41c1-83a6-97a8999f6963
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026373167 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_t
l_intg_err.2026373167
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.3525983966
Short name T332
Test name
Test status
Simulation time 461770238 ps
CPU time 1.36 seconds
Started May 09 02:06:36 PM PDT 24
Finished May 09 02:06:41 PM PDT 24
Peak memory 183624 kb
Host smart-43d991df-2c72-46d6-bd69-968466144223
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525983966 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_a
liasing.3525983966
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.4054271721
Short name T68
Test name
Test status
Simulation time 8554320578 ps
CPU time 4.9 seconds
Started May 09 02:06:35 PM PDT 24
Finished May 09 02:06:43 PM PDT 24
Peak memory 192200 kb
Host smart-46327e10-0a9c-432f-bd72-692e8707c4c8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054271721 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_b
it_bash.4054271721
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.1340838655
Short name T420
Test name
Test status
Simulation time 1156872914 ps
CPU time 1 seconds
Started May 09 02:06:35 PM PDT 24
Finished May 09 02:06:38 PM PDT 24
Peak memory 193004 kb
Host smart-aa71ec82-8783-419a-846a-3825e16b1de4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340838655 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_h
w_reset.1340838655
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.2108084136
Short name T338
Test name
Test status
Simulation time 707309756 ps
CPU time 0.85 seconds
Started May 09 02:06:35 PM PDT 24
Finished May 09 02:06:39 PM PDT 24
Peak memory 196452 kb
Host smart-dd02d605-c1c9-4b16-99c3-47cd0b4a6ce5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108084136 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.2108084136
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.1743455982
Short name T408
Test name
Test status
Simulation time 541977182 ps
CPU time 0.75 seconds
Started May 09 02:06:34 PM PDT 24
Finished May 09 02:06:37 PM PDT 24
Peak memory 183644 kb
Host smart-33863f2e-37ef-40a2-8753-ce4a2188d4c4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743455982 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.1743455982
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.3207086847
Short name T294
Test name
Test status
Simulation time 322278863 ps
CPU time 0.64 seconds
Started May 09 02:06:36 PM PDT 24
Finished May 09 02:06:40 PM PDT 24
Peak memory 183596 kb
Host smart-411535fb-062a-4908-ba3f-43d6c866ee4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207086847 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.3207086847
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.2247382369
Short name T366
Test name
Test status
Simulation time 482596493 ps
CPU time 0.93 seconds
Started May 09 02:06:36 PM PDT 24
Finished May 09 02:06:40 PM PDT 24
Peak memory 183500 kb
Host smart-bc0465b7-ff0e-476d-beeb-e2c18d771eb4
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247382369 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_t
imer_mem_partial_access.2247382369
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.3165689070
Short name T293
Test name
Test status
Simulation time 498651972 ps
CPU time 0.69 seconds
Started May 09 02:06:35 PM PDT 24
Finished May 09 02:06:38 PM PDT 24
Peak memory 183592 kb
Host smart-fbadb226-3c7b-4118-81bb-022c5bc5f665
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165689070 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_w
alk.3165689070
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.2027035111
Short name T410
Test name
Test status
Simulation time 2050101455 ps
CPU time 3.06 seconds
Started May 09 02:06:35 PM PDT 24
Finished May 09 02:06:41 PM PDT 24
Peak memory 191920 kb
Host smart-1477deb3-a15c-42a0-a6ea-fec0d360beae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027035111 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon
_timer_same_csr_outstanding.2027035111
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.3002832590
Short name T313
Test name
Test status
Simulation time 548272156 ps
CPU time 2.63 seconds
Started May 09 02:06:35 PM PDT 24
Finished May 09 02:06:41 PM PDT 24
Peak memory 198456 kb
Host smart-e90a14a9-51d2-4f9e-a0fe-3d19c3f444a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002832590 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.3002832590
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.2807327497
Short name T390
Test name
Test status
Simulation time 8946411657 ps
CPU time 12.1 seconds
Started May 09 02:06:35 PM PDT 24
Finished May 09 02:06:51 PM PDT 24
Peak memory 197784 kb
Host smart-2b0a93f2-5557-4ed7-b6df-a182bbfe767f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807327497 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl
_intg_err.2807327497
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.1981885935
Short name T368
Test name
Test status
Simulation time 545105723 ps
CPU time 0.85 seconds
Started May 09 02:06:46 PM PDT 24
Finished May 09 02:06:49 PM PDT 24
Peak memory 183648 kb
Host smart-e72195ed-23a4-4087-be70-b64e42dd8281
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981885935 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_a
liasing.1981885935
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.3271881543
Short name T66
Test name
Test status
Simulation time 4216667346 ps
CPU time 13.12 seconds
Started May 09 02:06:46 PM PDT 24
Finished May 09 02:07:01 PM PDT 24
Peak memory 192216 kb
Host smart-d67c7ba0-154b-4598-98ea-c0bfff8df675
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271881543 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_b
it_bash.3271881543
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.3400548781
Short name T345
Test name
Test status
Simulation time 658347861 ps
CPU time 1.59 seconds
Started May 09 02:06:47 PM PDT 24
Finished May 09 02:06:50 PM PDT 24
Peak memory 183696 kb
Host smart-31d8369b-fc4f-44e9-b9f3-ddcf49052401
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400548781 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_h
w_reset.3400548781
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.1824296260
Short name T419
Test name
Test status
Simulation time 486773135 ps
CPU time 0.79 seconds
Started May 09 02:06:45 PM PDT 24
Finished May 09 02:06:48 PM PDT 24
Peak memory 195628 kb
Host smart-51f8f00d-8bdf-4588-bd31-58ebdc22293d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824296260 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.1824296260
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.2136728869
Short name T71
Test name
Test status
Simulation time 557773922 ps
CPU time 1.02 seconds
Started May 09 02:06:46 PM PDT 24
Finished May 09 02:06:48 PM PDT 24
Peak memory 183656 kb
Host smart-98a01603-69f5-4c10-939c-aeefc73e8e1f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136728869 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.2136728869
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.3956661709
Short name T304
Test name
Test status
Simulation time 534739187 ps
CPU time 0.74 seconds
Started May 09 02:06:44 PM PDT 24
Finished May 09 02:06:46 PM PDT 24
Peak memory 183592 kb
Host smart-ae20f47b-21e0-472d-8744-e942fe0113eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956661709 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.3956661709
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.2418789000
Short name T284
Test name
Test status
Simulation time 337425802 ps
CPU time 0.77 seconds
Started May 09 02:06:47 PM PDT 24
Finished May 09 02:06:50 PM PDT 24
Peak memory 183560 kb
Host smart-bb34d989-39ef-423b-ac41-5098e53ffff7
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418789000 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_t
imer_mem_partial_access.2418789000
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.1506075423
Short name T361
Test name
Test status
Simulation time 464626708 ps
CPU time 0.89 seconds
Started May 09 02:06:45 PM PDT 24
Finished May 09 02:06:47 PM PDT 24
Peak memory 183616 kb
Host smart-bb749f8c-c542-4918-b9d3-8f0f0bc9d58e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506075423 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_w
alk.1506075423
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.4262691017
Short name T354
Test name
Test status
Simulation time 1456139623 ps
CPU time 3.79 seconds
Started May 09 02:06:48 PM PDT 24
Finished May 09 02:06:53 PM PDT 24
Peak memory 183700 kb
Host smart-69f325c6-92d3-4037-84dc-1118eb4d5e9c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262691017 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon
_timer_same_csr_outstanding.4262691017
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.1759433363
Short name T287
Test name
Test status
Simulation time 581865090 ps
CPU time 1.58 seconds
Started May 09 02:06:36 PM PDT 24
Finished May 09 02:06:41 PM PDT 24
Peak memory 198416 kb
Host smart-86a441de-a9e3-4a3c-818b-d84b98192861
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759433363 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.1759433363
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.349521386
Short name T303
Test name
Test status
Simulation time 604774453 ps
CPU time 1.52 seconds
Started May 09 02:07:27 PM PDT 24
Finished May 09 02:07:31 PM PDT 24
Peak memory 196900 kb
Host smart-b612ae69-1309-4568-8558-e64e7f0c6792
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349521386 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.349521386
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.1089489569
Short name T393
Test name
Test status
Simulation time 335470883 ps
CPU time 0.99 seconds
Started May 09 02:07:29 PM PDT 24
Finished May 09 02:07:33 PM PDT 24
Peak memory 193144 kb
Host smart-6a4ac256-2678-426f-a360-d9abb1ee0f92
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089489569 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.1089489569
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.780175712
Short name T363
Test name
Test status
Simulation time 317818828 ps
CPU time 0.64 seconds
Started May 09 02:07:25 PM PDT 24
Finished May 09 02:07:27 PM PDT 24
Peak memory 183556 kb
Host smart-3f644174-425f-4ce2-8d09-f636fc5a59c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780175712 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.780175712
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.523061587
Short name T36
Test name
Test status
Simulation time 3015352354 ps
CPU time 2.81 seconds
Started May 09 02:07:28 PM PDT 24
Finished May 09 02:07:34 PM PDT 24
Peak memory 194384 kb
Host smart-910cce46-f816-4dfe-b07a-3158f03d4a7a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523061587 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon
_timer_same_csr_outstanding.523061587
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.881399633
Short name T399
Test name
Test status
Simulation time 532989074 ps
CPU time 2.21 seconds
Started May 09 02:07:15 PM PDT 24
Finished May 09 02:07:18 PM PDT 24
Peak memory 198488 kb
Host smart-07927d86-c534-417c-bdce-bc0ecf927918
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881399633 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.881399633
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.908988108
Short name T321
Test name
Test status
Simulation time 3800564209 ps
CPU time 2.36 seconds
Started May 09 02:07:15 PM PDT 24
Finished May 09 02:07:19 PM PDT 24
Peak memory 197416 kb
Host smart-c516442c-7fc1-4d62-8b0d-383d3ee6559a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908988108 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl
_intg_err.908988108
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.1200271066
Short name T349
Test name
Test status
Simulation time 388961242 ps
CPU time 0.94 seconds
Started May 09 02:07:27 PM PDT 24
Finished May 09 02:07:30 PM PDT 24
Peak memory 196112 kb
Host smart-c3b93352-95df-4373-a405-448b5c5aaea4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200271066 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.1200271066
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.2801684454
Short name T69
Test name
Test status
Simulation time 335552152 ps
CPU time 1.15 seconds
Started May 09 02:07:27 PM PDT 24
Finished May 09 02:07:30 PM PDT 24
Peak memory 192932 kb
Host smart-1b7cbf6a-6d4b-4d73-9bfe-4c19285b22e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801684454 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.2801684454
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.133684505
Short name T326
Test name
Test status
Simulation time 508499791 ps
CPU time 0.58 seconds
Started May 09 02:07:27 PM PDT 24
Finished May 09 02:07:29 PM PDT 24
Peak memory 183576 kb
Host smart-15e26f84-ed0e-47ae-a2bb-28f486c9e1f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133684505 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.133684505
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.900702084
Short name T380
Test name
Test status
Simulation time 1467894993 ps
CPU time 1.75 seconds
Started May 09 02:07:28 PM PDT 24
Finished May 09 02:07:32 PM PDT 24
Peak memory 193268 kb
Host smart-fd7b9661-01f0-4ec5-9feb-200478d6169b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900702084 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon
_timer_same_csr_outstanding.900702084
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.3135067779
Short name T351
Test name
Test status
Simulation time 338108433 ps
CPU time 1.38 seconds
Started May 09 02:07:29 PM PDT 24
Finished May 09 02:07:34 PM PDT 24
Peak memory 198148 kb
Host smart-2a865154-d65d-4960-8fed-429a8b9d314a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135067779 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.3135067779
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.3338300778
Short name T113
Test name
Test status
Simulation time 8295489239 ps
CPU time 12.47 seconds
Started May 09 02:07:29 PM PDT 24
Finished May 09 02:07:45 PM PDT 24
Peak memory 197848 kb
Host smart-3bd13c3a-4df7-4537-ab1e-5b9e98d4dd14
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338300778 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_t
l_intg_err.3338300778
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.2976503965
Short name T344
Test name
Test status
Simulation time 533328060 ps
CPU time 0.71 seconds
Started May 09 02:07:28 PM PDT 24
Finished May 09 02:07:32 PM PDT 24
Peak memory 195124 kb
Host smart-8571e3a1-73b8-437c-90bf-a47840b7998a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976503965 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.2976503965
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.20060073
Short name T43
Test name
Test status
Simulation time 543967309 ps
CPU time 1.42 seconds
Started May 09 02:07:28 PM PDT 24
Finished May 09 02:07:31 PM PDT 24
Peak memory 193020 kb
Host smart-54bb0f37-5f2d-4485-880f-3ade10c55be6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20060073 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.20060073
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.1290958001
Short name T322
Test name
Test status
Simulation time 462557464 ps
CPU time 1.19 seconds
Started May 09 02:07:28 PM PDT 24
Finished May 09 02:07:31 PM PDT 24
Peak memory 182960 kb
Host smart-065cc225-5f6f-4d39-93e3-a5283fb8cc37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290958001 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.1290958001
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.79858570
Short name T73
Test name
Test status
Simulation time 1236749694 ps
CPU time 2.29 seconds
Started May 09 02:07:29 PM PDT 24
Finished May 09 02:07:34 PM PDT 24
Peak memory 193132 kb
Host smart-f9c14bb0-a128-47a5-85a6-36307413adda
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79858570 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_
timer_same_csr_outstanding.79858570
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.387594083
Short name T407
Test name
Test status
Simulation time 511394960 ps
CPU time 1.22 seconds
Started May 09 02:07:28 PM PDT 24
Finished May 09 02:07:32 PM PDT 24
Peak memory 198264 kb
Host smart-41d97042-582e-49cb-b3ff-72ff7192498a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387594083 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.387594083
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.3953657023
Short name T412
Test name
Test status
Simulation time 460536408 ps
CPU time 1.36 seconds
Started May 09 02:07:29 PM PDT 24
Finished May 09 02:07:33 PM PDT 24
Peak memory 196104 kb
Host smart-5f1b0a9e-97eb-4d8d-9266-45331aed546b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953657023 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.3953657023
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.2230180406
Short name T418
Test name
Test status
Simulation time 433607486 ps
CPU time 0.96 seconds
Started May 09 02:07:30 PM PDT 24
Finished May 09 02:07:34 PM PDT 24
Peak memory 183672 kb
Host smart-4cf94a07-a98b-4d66-bbb1-936e1b058332
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230180406 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.2230180406
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.3851652580
Short name T355
Test name
Test status
Simulation time 385097558 ps
CPU time 1.06 seconds
Started May 09 02:07:30 PM PDT 24
Finished May 09 02:07:34 PM PDT 24
Peak memory 183596 kb
Host smart-1ea84fe7-37cd-476f-a0c9-be14715f41a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851652580 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.3851652580
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.3176065049
Short name T379
Test name
Test status
Simulation time 1412291877 ps
CPU time 1.65 seconds
Started May 09 02:07:28 PM PDT 24
Finished May 09 02:07:32 PM PDT 24
Peak memory 183728 kb
Host smart-5155a306-7080-4c6d-9327-0f6c403fd444
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176065049 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.ao
n_timer_same_csr_outstanding.3176065049
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.3624263368
Short name T389
Test name
Test status
Simulation time 339550260 ps
CPU time 1.41 seconds
Started May 09 02:07:30 PM PDT 24
Finished May 09 02:07:34 PM PDT 24
Peak memory 198440 kb
Host smart-d88b7852-d2c7-4e1b-ae71-9acdce10cdc7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624263368 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.3624263368
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.3516511376
Short name T40
Test name
Test status
Simulation time 7927030820 ps
CPU time 4.29 seconds
Started May 09 02:07:27 PM PDT 24
Finished May 09 02:07:32 PM PDT 24
Peak memory 197804 kb
Host smart-535bb049-028e-49b4-a288-e75eac08b8bd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516511376 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_t
l_intg_err.3516511376
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.1302513916
Short name T330
Test name
Test status
Simulation time 458887995 ps
CPU time 0.94 seconds
Started May 09 02:07:29 PM PDT 24
Finished May 09 02:07:33 PM PDT 24
Peak memory 195732 kb
Host smart-9161c932-fd67-4932-a40c-146e9e9c5749
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302513916 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.1302513916
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.2706258003
Short name T37
Test name
Test status
Simulation time 448812813 ps
CPU time 0.71 seconds
Started May 09 02:07:27 PM PDT 24
Finished May 09 02:07:29 PM PDT 24
Peak memory 183656 kb
Host smart-95b97d16-c438-4da0-a330-5c3e1ea89be4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706258003 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.2706258003
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.2242428729
Short name T285
Test name
Test status
Simulation time 310255111 ps
CPU time 0.63 seconds
Started May 09 02:07:27 PM PDT 24
Finished May 09 02:07:30 PM PDT 24
Peak memory 183600 kb
Host smart-57d16232-d62f-430a-85ed-907008426285
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242428729 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.2242428729
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.2618198972
Short name T415
Test name
Test status
Simulation time 1310741929 ps
CPU time 1.14 seconds
Started May 09 02:07:27 PM PDT 24
Finished May 09 02:07:29 PM PDT 24
Peak memory 193164 kb
Host smart-4a04ae90-3f77-43e5-b0a1-05bc013ae0df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618198972 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao
n_timer_same_csr_outstanding.2618198972
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.284844604
Short name T377
Test name
Test status
Simulation time 409480465 ps
CPU time 2.01 seconds
Started May 09 02:07:30 PM PDT 24
Finished May 09 02:07:35 PM PDT 24
Peak memory 198476 kb
Host smart-4162aaca-2cd5-4405-b66b-a20b724927a0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284844604 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.284844604
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.3002916659
Short name T329
Test name
Test status
Simulation time 7845404016 ps
CPU time 14.03 seconds
Started May 09 02:07:29 PM PDT 24
Finished May 09 02:07:46 PM PDT 24
Peak memory 197888 kb
Host smart-87d63ea1-ee88-4268-ac39-5f79ee69a5b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002916659 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_t
l_intg_err.3002916659
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.2109118885
Short name T388
Test name
Test status
Simulation time 416037311 ps
CPU time 1.21 seconds
Started May 09 02:07:31 PM PDT 24
Finished May 09 02:07:35 PM PDT 24
Peak memory 196676 kb
Host smart-eeb251a7-0c8a-4839-9472-4f5f91819d96
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109118885 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.2109118885
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.230358472
Short name T371
Test name
Test status
Simulation time 362758841 ps
CPU time 0.69 seconds
Started May 09 02:07:29 PM PDT 24
Finished May 09 02:07:32 PM PDT 24
Peak memory 183828 kb
Host smart-545c5f55-f418-44a1-a72b-2a7c85d83630
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230358472 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.230358472
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.763253861
Short name T288
Test name
Test status
Simulation time 490001839 ps
CPU time 0.85 seconds
Started May 09 02:07:29 PM PDT 24
Finished May 09 02:07:33 PM PDT 24
Peak memory 183564 kb
Host smart-e6a4006c-ea2f-4e49-8c93-62d322bc7a7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763253861 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.763253861
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.3643084220
Short name T378
Test name
Test status
Simulation time 1992998181 ps
CPU time 1.3 seconds
Started May 09 02:07:30 PM PDT 24
Finished May 09 02:07:34 PM PDT 24
Peak memory 194616 kb
Host smart-5baff373-5cee-4df1-a148-b479b949bf1e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643084220 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.ao
n_timer_same_csr_outstanding.3643084220
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.970041397
Short name T356
Test name
Test status
Simulation time 725944546 ps
CPU time 1.57 seconds
Started May 09 02:07:30 PM PDT 24
Finished May 09 02:07:35 PM PDT 24
Peak memory 198444 kb
Host smart-8113ecb9-cf91-409b-ac9f-d6c3d15f6edd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970041397 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.970041397
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.1359832595
Short name T112
Test name
Test status
Simulation time 8739502473 ps
CPU time 2.18 seconds
Started May 09 02:07:28 PM PDT 24
Finished May 09 02:07:32 PM PDT 24
Peak memory 197412 kb
Host smart-a1b3dcd9-5242-49c4-bb84-fff4169f09d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359832595 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_t
l_intg_err.1359832595
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.192678961
Short name T360
Test name
Test status
Simulation time 352778413 ps
CPU time 0.93 seconds
Started May 09 02:07:37 PM PDT 24
Finished May 09 02:07:40 PM PDT 24
Peak memory 195856 kb
Host smart-8a5cf8fc-0efa-4c3c-ad43-0a4b9828553c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192678961 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.192678961
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.126322865
Short name T72
Test name
Test status
Simulation time 447970596 ps
CPU time 0.91 seconds
Started May 09 02:07:39 PM PDT 24
Finished May 09 02:07:42 PM PDT 24
Peak memory 183608 kb
Host smart-a4e91170-fb44-4e6f-829b-a1a6a2166d1f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126322865 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.126322865
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.3703786478
Short name T328
Test name
Test status
Simulation time 372206469 ps
CPU time 0.67 seconds
Started May 09 02:07:38 PM PDT 24
Finished May 09 02:07:40 PM PDT 24
Peak memory 183596 kb
Host smart-d301dd74-1d59-47e3-9145-2643441e89ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703786478 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.3703786478
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.3138900428
Short name T369
Test name
Test status
Simulation time 1548925882 ps
CPU time 1.11 seconds
Started May 09 02:07:39 PM PDT 24
Finished May 09 02:07:42 PM PDT 24
Peak memory 183720 kb
Host smart-06e88134-f0d4-48c7-a547-5c6f5760a6f6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138900428 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.ao
n_timer_same_csr_outstanding.3138900428
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.32471887
Short name T340
Test name
Test status
Simulation time 622794049 ps
CPU time 2.77 seconds
Started May 09 02:07:30 PM PDT 24
Finished May 09 02:07:36 PM PDT 24
Peak memory 198484 kb
Host smart-9a3f56b6-84df-4474-bb39-aa94e2d37236
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32471887 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.32471887
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.2460332928
Short name T402
Test name
Test status
Simulation time 8132294522 ps
CPU time 3.49 seconds
Started May 09 02:07:38 PM PDT 24
Finished May 09 02:07:44 PM PDT 24
Peak memory 197968 kb
Host smart-47c8b5a8-ec1c-4a06-aff4-5deace76322f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460332928 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_t
l_intg_err.2460332928
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.2169883163
Short name T317
Test name
Test status
Simulation time 448972160 ps
CPU time 1.12 seconds
Started May 09 02:07:39 PM PDT 24
Finished May 09 02:07:42 PM PDT 24
Peak memory 198288 kb
Host smart-3e4b905f-230b-45d7-9ab8-9c76b4a74073
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169883163 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.2169883163
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.1874325388
Short name T403
Test name
Test status
Simulation time 391477616 ps
CPU time 1.11 seconds
Started May 09 02:07:38 PM PDT 24
Finished May 09 02:07:41 PM PDT 24
Peak memory 183552 kb
Host smart-a74a1bdf-c94c-4035-a9fa-16352bd24a28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874325388 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.1874325388
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.2003643889
Short name T77
Test name
Test status
Simulation time 2695680864 ps
CPU time 1.72 seconds
Started May 09 02:07:37 PM PDT 24
Finished May 09 02:07:40 PM PDT 24
Peak memory 194344 kb
Host smart-532c6653-b23f-422a-845b-9d1c384a6d35
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003643889 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.ao
n_timer_same_csr_outstanding.2003643889
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.3284542504
Short name T373
Test name
Test status
Simulation time 469294901 ps
CPU time 1.97 seconds
Started May 09 02:07:40 PM PDT 24
Finished May 09 02:07:44 PM PDT 24
Peak memory 198512 kb
Host smart-8540f941-3f31-4d10-b8ff-31875ac069ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284542504 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.3284542504
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.2394945868
Short name T383
Test name
Test status
Simulation time 4191470108 ps
CPU time 2.52 seconds
Started May 09 02:07:38 PM PDT 24
Finished May 09 02:07:43 PM PDT 24
Peak memory 196428 kb
Host smart-969e2cbf-f5af-4793-8a3a-4769db9b607c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394945868 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_t
l_intg_err.2394945868
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.1071816472
Short name T352
Test name
Test status
Simulation time 542931325 ps
CPU time 1.02 seconds
Started May 09 02:07:36 PM PDT 24
Finished May 09 02:07:38 PM PDT 24
Peak memory 197804 kb
Host smart-b2f909c7-7e8c-42a0-a492-faf5ac0bb2c2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071816472 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.1071816472
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.3360371115
Short name T76
Test name
Test status
Simulation time 456403985 ps
CPU time 0.89 seconds
Started May 09 02:07:36 PM PDT 24
Finished May 09 02:07:37 PM PDT 24
Peak memory 183696 kb
Host smart-5a8e0afe-a13e-4a20-a3c7-cbd1b8e060af
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360371115 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.3360371115
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.1988967426
Short name T372
Test name
Test status
Simulation time 447288940 ps
CPU time 0.68 seconds
Started May 09 02:07:38 PM PDT 24
Finished May 09 02:07:40 PM PDT 24
Peak memory 183784 kb
Host smart-90ebeeee-d583-46bd-835b-68b996063e43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988967426 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.1988967426
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.1178484125
Short name T406
Test name
Test status
Simulation time 2625486793 ps
CPU time 6.45 seconds
Started May 09 02:07:40 PM PDT 24
Finished May 09 02:07:49 PM PDT 24
Peak memory 183788 kb
Host smart-efa62c8f-4d50-479b-9338-1e14011a0e53
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178484125 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.ao
n_timer_same_csr_outstanding.1178484125
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.2014997115
Short name T281
Test name
Test status
Simulation time 612386742 ps
CPU time 2.08 seconds
Started May 09 02:07:41 PM PDT 24
Finished May 09 02:07:45 PM PDT 24
Peak memory 198512 kb
Host smart-e26c4e28-c3a7-4019-bf98-d05257081f7a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014997115 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.2014997115
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.3570382041
Short name T109
Test name
Test status
Simulation time 4192131426 ps
CPU time 2.47 seconds
Started May 09 02:07:39 PM PDT 24
Finished May 09 02:07:44 PM PDT 24
Peak memory 197540 kb
Host smart-fa7b984d-2d6d-493b-af2c-248e3f39cb11
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570382041 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_t
l_intg_err.3570382041
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.3996772655
Short name T309
Test name
Test status
Simulation time 491931010 ps
CPU time 1.3 seconds
Started May 09 02:07:38 PM PDT 24
Finished May 09 02:07:41 PM PDT 24
Peak memory 195960 kb
Host smart-f74b5a21-0bc5-4348-b1d0-d19c1b8ffb1e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996772655 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.3996772655
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.1746056758
Short name T301
Test name
Test status
Simulation time 330917558 ps
CPU time 1.07 seconds
Started May 09 02:07:37 PM PDT 24
Finished May 09 02:07:40 PM PDT 24
Peak memory 183668 kb
Host smart-6e813c56-98b7-4f11-8ab9-041be5e88caf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746056758 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.1746056758
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.2447310400
Short name T343
Test name
Test status
Simulation time 420493908 ps
CPU time 1.11 seconds
Started May 09 02:07:39 PM PDT 24
Finished May 09 02:07:43 PM PDT 24
Peak memory 183580 kb
Host smart-2faca7d6-7796-4974-9dad-2e42c9572907
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447310400 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.2447310400
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.4134099932
Short name T359
Test name
Test status
Simulation time 2030171828 ps
CPU time 3.51 seconds
Started May 09 02:07:39 PM PDT 24
Finished May 09 02:07:45 PM PDT 24
Peak memory 194668 kb
Host smart-7796c558-bbe3-42ed-89fe-93e23b0ffc40
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134099932 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao
n_timer_same_csr_outstanding.4134099932
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.57098721
Short name T305
Test name
Test status
Simulation time 340392134 ps
CPU time 1.73 seconds
Started May 09 02:07:38 PM PDT 24
Finished May 09 02:07:41 PM PDT 24
Peak memory 198488 kb
Host smart-f5f4f86c-6b3b-430c-9f6f-6022961cfac6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57098721 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.57098721
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.965671571
Short name T324
Test name
Test status
Simulation time 4450379974 ps
CPU time 2.72 seconds
Started May 09 02:07:38 PM PDT 24
Finished May 09 02:07:42 PM PDT 24
Peak memory 197492 kb
Host smart-a7d1c1a0-772c-4283-9152-5fd4e5ebe9e5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965671571 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl
_intg_err.965671571
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.633807863
Short name T394
Test name
Test status
Simulation time 990193366 ps
CPU time 0.87 seconds
Started May 09 02:06:49 PM PDT 24
Finished May 09 02:06:51 PM PDT 24
Peak memory 194236 kb
Host smart-82a3a34b-b978-49b8-a48e-4aafbbbf4b84
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633807863 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_al
iasing.633807863
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.3260610287
Short name T70
Test name
Test status
Simulation time 6779592346 ps
CPU time 5.14 seconds
Started May 09 02:06:46 PM PDT 24
Finished May 09 02:06:52 PM PDT 24
Peak memory 194300 kb
Host smart-1967b488-a18f-434e-be42-8b5266e465af
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260610287 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_b
it_bash.3260610287
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.2202504462
Short name T64
Test name
Test status
Simulation time 1321000655 ps
CPU time 0.94 seconds
Started May 09 02:06:47 PM PDT 24
Finished May 09 02:06:50 PM PDT 24
Peak memory 183660 kb
Host smart-9032111e-85ea-4b4e-9eb0-e553d7d7b90e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202504462 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_h
w_reset.2202504462
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.2590718914
Short name T311
Test name
Test status
Simulation time 320372564 ps
CPU time 0.76 seconds
Started May 09 02:06:46 PM PDT 24
Finished May 09 02:06:48 PM PDT 24
Peak memory 195312 kb
Host smart-ddfc87fa-d180-4445-9809-83d2a3bdef61
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590718914 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.2590718914
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.584271695
Short name T310
Test name
Test status
Simulation time 476576489 ps
CPU time 0.74 seconds
Started May 09 02:06:47 PM PDT 24
Finished May 09 02:06:50 PM PDT 24
Peak memory 183652 kb
Host smart-e1550137-2389-4ee7-9648-8ab8d96e8b68
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584271695 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.584271695
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.1416690848
Short name T401
Test name
Test status
Simulation time 344144794 ps
CPU time 1.04 seconds
Started May 09 02:06:46 PM PDT 24
Finished May 09 02:06:48 PM PDT 24
Peak memory 183580 kb
Host smart-92eabee8-9d95-4ab0-a498-b3b74ce62d18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416690848 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.1416690848
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.2120433545
Short name T370
Test name
Test status
Simulation time 358770375 ps
CPU time 0.98 seconds
Started May 09 02:06:45 PM PDT 24
Finished May 09 02:06:47 PM PDT 24
Peak memory 183448 kb
Host smart-c6ee2a65-4cf7-4592-bda0-9280393e0773
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120433545 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_t
imer_mem_partial_access.2120433545
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.3395488148
Short name T358
Test name
Test status
Simulation time 357582823 ps
CPU time 0.64 seconds
Started May 09 02:06:48 PM PDT 24
Finished May 09 02:06:50 PM PDT 24
Peak memory 183604 kb
Host smart-9f284df9-1ac3-44d6-ae1e-03e7fdc03625
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395488148 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_w
alk.3395488148
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.3243671804
Short name T411
Test name
Test status
Simulation time 1167526466 ps
CPU time 1.48 seconds
Started May 09 02:06:45 PM PDT 24
Finished May 09 02:06:48 PM PDT 24
Peak memory 183632 kb
Host smart-d4cd18da-3566-41de-be12-ccb351b0d9e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243671804 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon
_timer_same_csr_outstanding.3243671804
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.156364988
Short name T339
Test name
Test status
Simulation time 1197151292 ps
CPU time 1.92 seconds
Started May 09 02:06:45 PM PDT 24
Finished May 09 02:06:48 PM PDT 24
Peak memory 198496 kb
Host smart-a5153a5e-040d-4849-bdfa-3cb72fc0a6ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156364988 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.156364988
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.2956106633
Short name T376
Test name
Test status
Simulation time 4604583744 ps
CPU time 2.73 seconds
Started May 09 02:06:45 PM PDT 24
Finished May 09 02:06:49 PM PDT 24
Peak memory 197700 kb
Host smart-6ec0a401-c191-45a7-aef4-d22f2d6dd13b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956106633 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl
_intg_err.2956106633
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.2838788927
Short name T350
Test name
Test status
Simulation time 281179973 ps
CPU time 0.65 seconds
Started May 09 02:07:37 PM PDT 24
Finished May 09 02:07:40 PM PDT 24
Peak memory 183548 kb
Host smart-9e4052b9-19fb-41be-97ef-b5b9f2adf393
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838788927 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.2838788927
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.1086914941
Short name T333
Test name
Test status
Simulation time 338061886 ps
CPU time 0.77 seconds
Started May 09 02:07:40 PM PDT 24
Finished May 09 02:07:43 PM PDT 24
Peak memory 183628 kb
Host smart-b15c853c-588e-4083-a483-5ce9f9b4a754
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086914941 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.1086914941
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.4184786450
Short name T295
Test name
Test status
Simulation time 402903142 ps
CPU time 1.1 seconds
Started May 09 02:07:40 PM PDT 24
Finished May 09 02:07:43 PM PDT 24
Peak memory 183572 kb
Host smart-d21771ad-676b-42f6-9ca9-3ce2d2399eb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184786450 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.4184786450
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.1762112695
Short name T308
Test name
Test status
Simulation time 511837945 ps
CPU time 1.22 seconds
Started May 09 02:07:37 PM PDT 24
Finished May 09 02:07:40 PM PDT 24
Peak memory 183620 kb
Host smart-db5b6137-c49a-4847-9ff8-5a2374e89992
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762112695 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.1762112695
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.895682988
Short name T289
Test name
Test status
Simulation time 373012068 ps
CPU time 1.09 seconds
Started May 09 02:07:37 PM PDT 24
Finished May 09 02:07:40 PM PDT 24
Peak memory 183552 kb
Host smart-b9734cc1-9f00-403e-919f-e7e801f83abf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895682988 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.895682988
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.4208939217
Short name T405
Test name
Test status
Simulation time 283656691 ps
CPU time 0.81 seconds
Started May 09 02:07:36 PM PDT 24
Finished May 09 02:07:39 PM PDT 24
Peak memory 183572 kb
Host smart-23a0863b-44b0-4390-940c-e63313918ad9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208939217 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.4208939217
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.910261451
Short name T315
Test name
Test status
Simulation time 422740007 ps
CPU time 0.69 seconds
Started May 09 02:07:39 PM PDT 24
Finished May 09 02:07:42 PM PDT 24
Peak memory 183504 kb
Host smart-8b76c99e-f899-4c79-bc06-321853f654f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910261451 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.910261451
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.2216013713
Short name T302
Test name
Test status
Simulation time 489023127 ps
CPU time 0.84 seconds
Started May 09 02:07:43 PM PDT 24
Finished May 09 02:07:44 PM PDT 24
Peak memory 183584 kb
Host smart-d0ac567e-9339-4a1f-9f43-644a5454e88d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216013713 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.2216013713
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.1639565702
Short name T296
Test name
Test status
Simulation time 359737833 ps
CPU time 1.17 seconds
Started May 09 02:07:38 PM PDT 24
Finished May 09 02:07:41 PM PDT 24
Peak memory 183592 kb
Host smart-f5ec3a64-d92f-4661-9d2d-f85445fda4ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639565702 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.1639565702
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.2611570237
Short name T299
Test name
Test status
Simulation time 397499956 ps
CPU time 1.19 seconds
Started May 09 02:07:40 PM PDT 24
Finished May 09 02:07:43 PM PDT 24
Peak memory 183584 kb
Host smart-50b8c73d-8422-4888-9513-0e4003df8af3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611570237 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.2611570237
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.2413870887
Short name T60
Test name
Test status
Simulation time 603249097 ps
CPU time 0.71 seconds
Started May 09 02:06:59 PM PDT 24
Finished May 09 02:07:01 PM PDT 24
Peak memory 183648 kb
Host smart-2f3949f0-e041-4acc-bcf2-aff5f6a5c48d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413870887 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_a
liasing.2413870887
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.3514830576
Short name T65
Test name
Test status
Simulation time 11583786749 ps
CPU time 10.73 seconds
Started May 09 02:06:47 PM PDT 24
Finished May 09 02:06:59 PM PDT 24
Peak memory 192192 kb
Host smart-80d7aff9-3d87-4a76-be67-7c0edffd7269
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514830576 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_b
it_bash.3514830576
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.1381369126
Short name T62
Test name
Test status
Simulation time 1286762474 ps
CPU time 1.14 seconds
Started May 09 02:06:47 PM PDT 24
Finished May 09 02:06:50 PM PDT 24
Peak memory 183668 kb
Host smart-e3d7f2b7-b08f-4f4a-917e-658c958416f4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381369126 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_h
w_reset.1381369126
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.3787496616
Short name T348
Test name
Test status
Simulation time 489652312 ps
CPU time 1.18 seconds
Started May 09 02:06:55 PM PDT 24
Finished May 09 02:06:58 PM PDT 24
Peak memory 197404 kb
Host smart-90e11dcc-74b7-448b-828a-ff51a6f30e22
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787496616 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.3787496616
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.46140347
Short name T67
Test name
Test status
Simulation time 399957615 ps
CPU time 1.13 seconds
Started May 09 02:06:45 PM PDT 24
Finished May 09 02:06:47 PM PDT 24
Peak memory 192936 kb
Host smart-c5766fec-3858-47a7-878c-fe20b32aee10
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46140347 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.46140347
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.1317797534
Short name T404
Test name
Test status
Simulation time 481456689 ps
CPU time 1.19 seconds
Started May 09 02:06:45 PM PDT 24
Finished May 09 02:06:47 PM PDT 24
Peak memory 183552 kb
Host smart-c86f651a-d1ba-43b2-ae06-20f521edda14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317797534 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.1317797534
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.4137540638
Short name T422
Test name
Test status
Simulation time 296845821 ps
CPU time 0.58 seconds
Started May 09 02:06:47 PM PDT 24
Finished May 09 02:06:49 PM PDT 24
Peak memory 183512 kb
Host smart-561e7a84-fc0f-405c-a074-a0ed2c8bf0cb
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137540638 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_t
imer_mem_partial_access.4137540638
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.3544025982
Short name T325
Test name
Test status
Simulation time 505890689 ps
CPU time 0.68 seconds
Started May 09 02:06:46 PM PDT 24
Finished May 09 02:06:49 PM PDT 24
Peak memory 183604 kb
Host smart-fb525356-66b1-48ae-b554-e08e710af135
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544025982 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_w
alk.3544025982
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.1410308578
Short name T397
Test name
Test status
Simulation time 1378695968 ps
CPU time 2.06 seconds
Started May 09 02:06:55 PM PDT 24
Finished May 09 02:06:59 PM PDT 24
Peak memory 183684 kb
Host smart-0cf54e90-2967-4a1f-a4d9-e21fdf534043
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410308578 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon
_timer_same_csr_outstanding.1410308578
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.1229147996
Short name T312
Test name
Test status
Simulation time 483182154 ps
CPU time 1.33 seconds
Started May 09 02:06:45 PM PDT 24
Finished May 09 02:06:47 PM PDT 24
Peak memory 198520 kb
Host smart-afd72e81-0260-4e23-ae2d-59b8d9cb1fbc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229147996 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.1229147996
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.510980891
Short name T316
Test name
Test status
Simulation time 8683619497 ps
CPU time 13.38 seconds
Started May 09 02:06:47 PM PDT 24
Finished May 09 02:07:02 PM PDT 24
Peak memory 197984 kb
Host smart-72cc2dce-87e9-4efa-b5dd-fe7b1f1e3bfd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510980891 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_
intg_err.510980891
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.1813922756
Short name T331
Test name
Test status
Simulation time 283429711 ps
CPU time 0.75 seconds
Started May 09 02:07:37 PM PDT 24
Finished May 09 02:07:39 PM PDT 24
Peak memory 183576 kb
Host smart-6b18201e-983b-4952-995c-8da6df5a7a32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813922756 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.1813922756
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.1034522086
Short name T298
Test name
Test status
Simulation time 524519671 ps
CPU time 1.01 seconds
Started May 09 02:07:38 PM PDT 24
Finished May 09 02:07:41 PM PDT 24
Peak memory 183572 kb
Host smart-f2e19d56-32d1-48c5-871c-864f19e60ccd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034522086 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.1034522086
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.3253739008
Short name T318
Test name
Test status
Simulation time 388696538 ps
CPU time 0.65 seconds
Started May 09 02:07:40 PM PDT 24
Finished May 09 02:07:43 PM PDT 24
Peak memory 183564 kb
Host smart-e98edb85-7f70-4a2d-8c60-53dc09f3bebc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253739008 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.3253739008
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.4096555644
Short name T365
Test name
Test status
Simulation time 352076845 ps
CPU time 1.03 seconds
Started May 09 02:07:36 PM PDT 24
Finished May 09 02:07:39 PM PDT 24
Peak memory 183392 kb
Host smart-8d624dc7-3bbd-49ca-beff-74a1cca6da9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096555644 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.4096555644
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.85177783
Short name T385
Test name
Test status
Simulation time 439842699 ps
CPU time 1.19 seconds
Started May 09 02:07:40 PM PDT 24
Finished May 09 02:07:44 PM PDT 24
Peak memory 183600 kb
Host smart-eacde7a3-0335-4e0a-9ab9-4702f1a19572
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85177783 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.85177783
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.68367497
Short name T382
Test name
Test status
Simulation time 507578889 ps
CPU time 1.31 seconds
Started May 09 02:07:38 PM PDT 24
Finished May 09 02:07:42 PM PDT 24
Peak memory 183576 kb
Host smart-b65d41b4-6e68-48da-86e8-44c59675fb7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68367497 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.68367497
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.3260866327
Short name T283
Test name
Test status
Simulation time 407281871 ps
CPU time 0.79 seconds
Started May 09 02:07:48 PM PDT 24
Finished May 09 02:07:51 PM PDT 24
Peak memory 183572 kb
Host smart-7d856366-8d55-4f5f-8197-a3790fd6e3ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260866327 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.3260866327
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.647016370
Short name T297
Test name
Test status
Simulation time 422800654 ps
CPU time 0.75 seconds
Started May 09 02:07:48 PM PDT 24
Finished May 09 02:07:50 PM PDT 24
Peak memory 183572 kb
Host smart-f8640db0-70e6-42f1-ab70-8c287962143f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647016370 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.647016370
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.3529889627
Short name T391
Test name
Test status
Simulation time 499344917 ps
CPU time 0.61 seconds
Started May 09 02:07:48 PM PDT 24
Finished May 09 02:07:50 PM PDT 24
Peak memory 183604 kb
Host smart-3ddde561-0852-42bd-85e8-b5cc47dfaaa9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529889627 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.3529889627
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.1701183598
Short name T421
Test name
Test status
Simulation time 459636220 ps
CPU time 0.72 seconds
Started May 09 02:07:46 PM PDT 24
Finished May 09 02:07:48 PM PDT 24
Peak memory 183612 kb
Host smart-9e204a99-4e0f-448a-b3c6-9076edabe804
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701183598 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.1701183598
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.2721146428
Short name T63
Test name
Test status
Simulation time 419827084 ps
CPU time 1.26 seconds
Started May 09 02:06:55 PM PDT 24
Finished May 09 02:06:57 PM PDT 24
Peak memory 183668 kb
Host smart-418b2d92-4731-49d2-93f5-0e003a777ae2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721146428 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_a
liasing.2721146428
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.1205467383
Short name T61
Test name
Test status
Simulation time 13692093096 ps
CPU time 21.61 seconds
Started May 09 02:06:58 PM PDT 24
Finished May 09 02:07:21 PM PDT 24
Peak memory 192188 kb
Host smart-f325c86b-2d32-4164-9ff7-9e9928ce0bd2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205467383 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_b
it_bash.1205467383
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.1546207940
Short name T392
Test name
Test status
Simulation time 1365961871 ps
CPU time 1.51 seconds
Started May 09 02:06:53 PM PDT 24
Finished May 09 02:06:55 PM PDT 24
Peak memory 193196 kb
Host smart-8faae306-2de0-44e5-8035-33f71a23f55e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546207940 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_h
w_reset.1546207940
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.1396729582
Short name T416
Test name
Test status
Simulation time 537233041 ps
CPU time 1.44 seconds
Started May 09 02:06:55 PM PDT 24
Finished May 09 02:06:58 PM PDT 24
Peak memory 195868 kb
Host smart-f5207f2a-2a44-4ab5-9704-056e5197c2b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396729582 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.1396729582
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.1717811353
Short name T409
Test name
Test status
Simulation time 537632282 ps
CPU time 0.97 seconds
Started May 09 02:06:55 PM PDT 24
Finished May 09 02:06:58 PM PDT 24
Peak memory 192900 kb
Host smart-a651eb2a-8ebb-43f1-b364-b607f36aff1a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717811353 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.1717811353
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.3127608243
Short name T286
Test name
Test status
Simulation time 401987963 ps
CPU time 0.68 seconds
Started May 09 02:06:59 PM PDT 24
Finished May 09 02:07:01 PM PDT 24
Peak memory 183556 kb
Host smart-c1206c87-6d0b-4a39-b6db-c100b4add4d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127608243 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.3127608243
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.3738619176
Short name T400
Test name
Test status
Simulation time 329505140 ps
CPU time 1.1 seconds
Started May 09 02:06:56 PM PDT 24
Finished May 09 02:06:59 PM PDT 24
Peak memory 183704 kb
Host smart-f10053dc-75b3-490d-a497-0868e95679c2
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738619176 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_t
imer_mem_partial_access.3738619176
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.1142603699
Short name T282
Test name
Test status
Simulation time 531864219 ps
CPU time 0.7 seconds
Started May 09 02:06:54 PM PDT 24
Finished May 09 02:06:56 PM PDT 24
Peak memory 183568 kb
Host smart-520c3546-1b7e-44e2-a25e-4b2340102c53
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142603699 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_w
alk.1142603699
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.3985306726
Short name T398
Test name
Test status
Simulation time 1490540868 ps
CPU time 3.97 seconds
Started May 09 02:06:54 PM PDT 24
Finished May 09 02:06:59 PM PDT 24
Peak memory 194284 kb
Host smart-67ce4616-0606-48fc-a7ef-9b0a42ceae8c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985306726 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon
_timer_same_csr_outstanding.3985306726
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.3898556173
Short name T364
Test name
Test status
Simulation time 622849015 ps
CPU time 1.13 seconds
Started May 09 02:06:55 PM PDT 24
Finished May 09 02:06:58 PM PDT 24
Peak memory 198032 kb
Host smart-e691f0f7-3667-4662-9c77-d7c98f627358
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898556173 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.3898556173
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.3278068709
Short name T306
Test name
Test status
Simulation time 3782896187 ps
CPU time 5.52 seconds
Started May 09 02:06:54 PM PDT 24
Finished May 09 02:07:01 PM PDT 24
Peak memory 197604 kb
Host smart-a623d06d-af0d-478c-8b5c-4e06951726f2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278068709 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl
_intg_err.3278068709
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.2925813418
Short name T367
Test name
Test status
Simulation time 506602006 ps
CPU time 1.19 seconds
Started May 09 02:07:48 PM PDT 24
Finished May 09 02:07:51 PM PDT 24
Peak memory 183584 kb
Host smart-f5a70f59-bedd-4ff6-b55a-1672bf75f7d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925813418 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.2925813418
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.3559727640
Short name T375
Test name
Test status
Simulation time 408544806 ps
CPU time 0.72 seconds
Started May 09 02:07:47 PM PDT 24
Finished May 09 02:07:48 PM PDT 24
Peak memory 183628 kb
Host smart-c4f78ee5-4772-4cd8-9513-e2345013c227
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559727640 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.3559727640
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.1596257053
Short name T396
Test name
Test status
Simulation time 369130261 ps
CPU time 1.11 seconds
Started May 09 02:07:48 PM PDT 24
Finished May 09 02:07:51 PM PDT 24
Peak memory 183576 kb
Host smart-cb82a373-cbaa-4655-aa91-79bc6466b820
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596257053 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.1596257053
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.1423194892
Short name T362
Test name
Test status
Simulation time 286776501 ps
CPU time 0.78 seconds
Started May 09 02:07:46 PM PDT 24
Finished May 09 02:07:48 PM PDT 24
Peak memory 183572 kb
Host smart-b7ac3337-cd3e-42aa-ad84-230da10e2d2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423194892 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.1423194892
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.1352014839
Short name T334
Test name
Test status
Simulation time 300462799 ps
CPU time 0.92 seconds
Started May 09 02:07:48 PM PDT 24
Finished May 09 02:07:50 PM PDT 24
Peak memory 183600 kb
Host smart-45e2c94a-2011-43b5-9a64-816bd2c7482e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352014839 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.1352014839
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.2046375792
Short name T413
Test name
Test status
Simulation time 385988637 ps
CPU time 0.93 seconds
Started May 09 02:07:49 PM PDT 24
Finished May 09 02:07:51 PM PDT 24
Peak memory 183592 kb
Host smart-0116d3b5-202f-47cd-8d06-3a4368140e1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046375792 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.2046375792
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.842050178
Short name T323
Test name
Test status
Simulation time 390257385 ps
CPU time 0.9 seconds
Started May 09 02:07:48 PM PDT 24
Finished May 09 02:07:50 PM PDT 24
Peak memory 183576 kb
Host smart-cf7c4429-6d4f-498f-8cbd-209371c17e80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842050178 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.842050178
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.2828931492
Short name T327
Test name
Test status
Simulation time 341702819 ps
CPU time 0.67 seconds
Started May 09 02:07:48 PM PDT 24
Finished May 09 02:07:50 PM PDT 24
Peak memory 183544 kb
Host smart-e1ee0fa6-7d5e-46e4-8928-71121faeff92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828931492 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.2828931492
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.1141840822
Short name T347
Test name
Test status
Simulation time 371092520 ps
CPU time 1.08 seconds
Started May 09 02:07:47 PM PDT 24
Finished May 09 02:07:49 PM PDT 24
Peak memory 183536 kb
Host smart-9e8ad5af-52c2-4efa-85fe-1600f54e11d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141840822 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.1141840822
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.4261116794
Short name T319
Test name
Test status
Simulation time 337047536 ps
CPU time 1.04 seconds
Started May 09 02:07:48 PM PDT 24
Finished May 09 02:07:50 PM PDT 24
Peak memory 183584 kb
Host smart-b3235b22-d15a-43e9-89fe-c01afac86bf2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261116794 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.4261116794
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.1544208857
Short name T386
Test name
Test status
Simulation time 490788729 ps
CPU time 1.37 seconds
Started May 09 02:07:06 PM PDT 24
Finished May 09 02:07:09 PM PDT 24
Peak memory 195644 kb
Host smart-da5c4a77-2a9b-4342-b3e5-867096c0b50c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544208857 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.1544208857
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.1518976420
Short name T384
Test name
Test status
Simulation time 550088138 ps
CPU time 1.46 seconds
Started May 09 02:06:55 PM PDT 24
Finished May 09 02:06:57 PM PDT 24
Peak memory 193024 kb
Host smart-36f01ba4-5c1b-4431-898e-d2d3fa0f9866
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518976420 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.1518976420
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.666321930
Short name T414
Test name
Test status
Simulation time 484395503 ps
CPU time 0.84 seconds
Started May 09 02:06:56 PM PDT 24
Finished May 09 02:06:58 PM PDT 24
Peak memory 183576 kb
Host smart-e43e2a62-1d53-4ec4-b6ea-5864c3d98cf8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666321930 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.666321930
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.2020505802
Short name T337
Test name
Test status
Simulation time 2904602241 ps
CPU time 2.71 seconds
Started May 09 02:06:57 PM PDT 24
Finished May 09 02:07:01 PM PDT 24
Peak memory 194416 kb
Host smart-87fe97d8-5850-4f54-baeb-188d198a47c0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020505802 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon
_timer_same_csr_outstanding.2020505802
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.550243949
Short name T300
Test name
Test status
Simulation time 461306404 ps
CPU time 1.84 seconds
Started May 09 02:06:56 PM PDT 24
Finished May 09 02:07:00 PM PDT 24
Peak memory 198512 kb
Host smart-8de362be-bb1e-41cb-9305-d0b8c42ba96d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550243949 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.550243949
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.3776553380
Short name T341
Test name
Test status
Simulation time 4186143592 ps
CPU time 7.53 seconds
Started May 09 02:06:55 PM PDT 24
Finished May 09 02:07:05 PM PDT 24
Peak memory 197292 kb
Host smart-88b4deb4-5a62-4c48-8a25-ccea0b92a9d3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776553380 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl
_intg_err.3776553380
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.2581373359
Short name T314
Test name
Test status
Simulation time 328078182 ps
CPU time 0.81 seconds
Started May 09 02:07:08 PM PDT 24
Finished May 09 02:07:10 PM PDT 24
Peak memory 194712 kb
Host smart-af4cb1fe-417a-4737-b499-e63f6b9821d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581373359 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.2581373359
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.3133250799
Short name T395
Test name
Test status
Simulation time 509972755 ps
CPU time 1.4 seconds
Started May 09 02:07:07 PM PDT 24
Finished May 09 02:07:10 PM PDT 24
Peak memory 183792 kb
Host smart-979666b0-088a-4860-8a86-e3108c0ff598
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133250799 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.3133250799
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.2258642364
Short name T280
Test name
Test status
Simulation time 326934475 ps
CPU time 0.63 seconds
Started May 09 02:07:05 PM PDT 24
Finished May 09 02:07:07 PM PDT 24
Peak memory 183580 kb
Host smart-9e24536f-54a0-47ca-8163-3c367a9bbcfb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258642364 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.2258642364
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.2907165191
Short name T353
Test name
Test status
Simulation time 1533691542 ps
CPU time 1.65 seconds
Started May 09 02:07:04 PM PDT 24
Finished May 09 02:07:07 PM PDT 24
Peak memory 193188 kb
Host smart-3a842c94-e161-414d-a125-aa0017a6b951
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907165191 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon
_timer_same_csr_outstanding.2907165191
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.2782578166
Short name T290
Test name
Test status
Simulation time 486350383 ps
CPU time 1.94 seconds
Started May 09 02:07:04 PM PDT 24
Finished May 09 02:07:07 PM PDT 24
Peak memory 198472 kb
Host smart-33c5ac31-74ff-4fd7-a54f-01606f12c880
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782578166 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.2782578166
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.221953604
Short name T335
Test name
Test status
Simulation time 4432218970 ps
CPU time 4.62 seconds
Started May 09 02:07:05 PM PDT 24
Finished May 09 02:07:12 PM PDT 24
Peak memory 197544 kb
Host smart-4b46b261-cf54-4789-9d23-4d6a16dee77e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221953604 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_
intg_err.221953604
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.3957356951
Short name T38
Test name
Test status
Simulation time 608461966 ps
CPU time 1.46 seconds
Started May 09 02:07:04 PM PDT 24
Finished May 09 02:07:06 PM PDT 24
Peak memory 195260 kb
Host smart-5830453a-c275-41c5-b335-1895c7609d80
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957356951 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.3957356951
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.354924611
Short name T387
Test name
Test status
Simulation time 362486639 ps
CPU time 0.69 seconds
Started May 09 02:07:05 PM PDT 24
Finished May 09 02:07:08 PM PDT 24
Peak memory 183868 kb
Host smart-4dab45a7-6b54-4936-b39e-d6c7cbb1c2e0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354924611 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.354924611
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.2330406282
Short name T291
Test name
Test status
Simulation time 484130728 ps
CPU time 1.26 seconds
Started May 09 02:07:04 PM PDT 24
Finished May 09 02:07:07 PM PDT 24
Peak memory 183612 kb
Host smart-ebdeef3d-6160-4572-9403-4f792847718e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330406282 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.2330406282
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.2262125052
Short name T74
Test name
Test status
Simulation time 1138179147 ps
CPU time 2.03 seconds
Started May 09 02:07:06 PM PDT 24
Finished May 09 02:07:10 PM PDT 24
Peak memory 183884 kb
Host smart-441d9557-ae2d-4042-99e7-ecb26a43f01e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262125052 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon
_timer_same_csr_outstanding.2262125052
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.1899343395
Short name T307
Test name
Test status
Simulation time 503203964 ps
CPU time 2.84 seconds
Started May 09 02:07:07 PM PDT 24
Finished May 09 02:07:11 PM PDT 24
Peak memory 198484 kb
Host smart-3d2fa01c-7369-4f67-90a8-99ed3c42ae20
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899343395 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.1899343395
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.2195389942
Short name T381
Test name
Test status
Simulation time 507083835 ps
CPU time 1.34 seconds
Started May 09 02:07:14 PM PDT 24
Finished May 09 02:07:16 PM PDT 24
Peak memory 195688 kb
Host smart-03348b01-8951-49d5-b99c-1b328a36efa1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195389942 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.2195389942
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.1794886256
Short name T75
Test name
Test status
Simulation time 354756638 ps
CPU time 1.07 seconds
Started May 09 02:07:08 PM PDT 24
Finished May 09 02:07:11 PM PDT 24
Peak memory 183652 kb
Host smart-18631417-db8b-400c-a6eb-0212d366e2f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794886256 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.1794886256
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.3202854257
Short name T292
Test name
Test status
Simulation time 520652780 ps
CPU time 0.59 seconds
Started May 09 02:07:04 PM PDT 24
Finished May 09 02:07:06 PM PDT 24
Peak memory 183596 kb
Host smart-40a8223c-4ad2-4d34-8959-a26bcc24c0e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202854257 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.3202854257
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.1514874378
Short name T374
Test name
Test status
Simulation time 1426044467 ps
CPU time 4.34 seconds
Started May 09 02:07:15 PM PDT 24
Finished May 09 02:07:20 PM PDT 24
Peak memory 193120 kb
Host smart-9edafdfd-368f-44e6-8e6a-60adaf255384
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514874378 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon
_timer_same_csr_outstanding.1514874378
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.2843107256
Short name T417
Test name
Test status
Simulation time 712731959 ps
CPU time 1.35 seconds
Started May 09 02:07:06 PM PDT 24
Finished May 09 02:07:09 PM PDT 24
Peak memory 198480 kb
Host smart-dc8f1e49-95d1-447d-890f-f306f4c76e7b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843107256 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.2843107256
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.3323126596
Short name T346
Test name
Test status
Simulation time 4244670315 ps
CPU time 2.13 seconds
Started May 09 02:07:05 PM PDT 24
Finished May 09 02:07:08 PM PDT 24
Peak memory 197152 kb
Host smart-494afc7d-6c11-4731-8d9b-e6bbbe117c60
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323126596 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl
_intg_err.3323126596
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.2208771127
Short name T42
Test name
Test status
Simulation time 325653076 ps
CPU time 1.2 seconds
Started May 09 02:07:19 PM PDT 24
Finished May 09 02:07:21 PM PDT 24
Peak memory 195672 kb
Host smart-267d64df-aea2-4d50-8c3b-f92bd5475487
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208771127 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.2208771127
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.3677863717
Short name T342
Test name
Test status
Simulation time 474733252 ps
CPU time 1.28 seconds
Started May 09 02:07:17 PM PDT 24
Finished May 09 02:07:19 PM PDT 24
Peak memory 183860 kb
Host smart-7bef4af8-0d2f-430e-82a1-0252cd16f5fb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677863717 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.3677863717
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.3292123973
Short name T357
Test name
Test status
Simulation time 311205822 ps
CPU time 1.01 seconds
Started May 09 02:07:16 PM PDT 24
Finished May 09 02:07:18 PM PDT 24
Peak memory 183532 kb
Host smart-a29338f4-0097-4ecf-a5f8-393c2a44cbf0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292123973 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.3292123973
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.1952611724
Short name T320
Test name
Test status
Simulation time 1257354860 ps
CPU time 2.02 seconds
Started May 09 02:07:15 PM PDT 24
Finished May 09 02:07:18 PM PDT 24
Peak memory 193400 kb
Host smart-f9815af0-9f5a-4226-94af-5b6ed7c88e3b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952611724 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon
_timer_same_csr_outstanding.1952611724
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.1912360578
Short name T336
Test name
Test status
Simulation time 398070285 ps
CPU time 2.35 seconds
Started May 09 02:07:15 PM PDT 24
Finished May 09 02:07:19 PM PDT 24
Peak memory 198468 kb
Host smart-c7723e79-a286-4af3-a1b1-3cef34b99d2d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912360578 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.1912360578
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.4050704004
Short name T110
Test name
Test status
Simulation time 8031581168 ps
CPU time 13.64 seconds
Started May 09 02:07:16 PM PDT 24
Finished May 09 02:07:31 PM PDT 24
Peak memory 197992 kb
Host smart-11284e57-f4ee-43db-8b77-0a3eba7b1787
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050704004 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl
_intg_err.4050704004
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_jump.964670559
Short name T28
Test name
Test status
Simulation time 425991574 ps
CPU time 0.74 seconds
Started May 09 02:04:06 PM PDT 24
Finished May 09 02:04:08 PM PDT 24
Peak memory 183548 kb
Host smart-afaf300e-dd30-4c80-982f-11f429f24991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964670559 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.964670559
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.3864128538
Short name T162
Test name
Test status
Simulation time 32202656145 ps
CPU time 8.69 seconds
Started May 09 02:04:06 PM PDT 24
Finished May 09 02:04:17 PM PDT 24
Peak memory 191824 kb
Host smart-e32a0ba4-3fb2-4514-a0e0-ad059b17d98a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864128538 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.3864128538
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.3973763963
Short name T117
Test name
Test status
Simulation time 543559109 ps
CPU time 0.76 seconds
Started May 09 02:04:05 PM PDT 24
Finished May 09 02:04:08 PM PDT 24
Peak memory 183540 kb
Host smart-86057f08-7760-40fc-9861-09dc027095c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973763963 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.3973763963
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.2970051559
Short name T99
Test name
Test status
Simulation time 324707119321 ps
CPU time 374.26 seconds
Started May 09 02:04:04 PM PDT 24
Finished May 09 02:10:20 PM PDT 24
Peak memory 191816 kb
Host smart-57c53a34-dcfc-428a-8d00-20713e8e262f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970051559 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_a
ll.2970051559
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.3808867289
Short name T83
Test name
Test status
Simulation time 92378552805 ps
CPU time 391.97 seconds
Started May 09 02:04:03 PM PDT 24
Finished May 09 02:10:37 PM PDT 24
Peak memory 198524 kb
Host smart-681cd875-ac73-4a7b-9904-0dadde5fad9a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808867289 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.3808867289
Directory /workspace/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.aon_timer_jump.3411385962
Short name T120
Test name
Test status
Simulation time 600738406 ps
CPU time 0.76 seconds
Started May 09 02:04:15 PM PDT 24
Finished May 09 02:04:17 PM PDT 24
Peak memory 183584 kb
Host smart-ddd63b62-50bb-4c98-99f4-0e2f8dbce17a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411385962 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.3411385962
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.1660424596
Short name T180
Test name
Test status
Simulation time 41693915392 ps
CPU time 15.49 seconds
Started May 09 02:04:16 PM PDT 24
Finished May 09 02:04:33 PM PDT 24
Peak memory 191824 kb
Host smart-00df8467-408a-4288-944d-d690cde6ef40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660424596 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.1660424596
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.1455918387
Short name T24
Test name
Test status
Simulation time 4567082594 ps
CPU time 6.79 seconds
Started May 09 02:04:15 PM PDT 24
Finished May 09 02:04:24 PM PDT 24
Peak memory 215176 kb
Host smart-9f913fd4-a5f6-45df-b69f-ef7bea58b1d5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455918387 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.1455918387
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.2492577109
Short name T190
Test name
Test status
Simulation time 567334601 ps
CPU time 1.39 seconds
Started May 09 02:04:06 PM PDT 24
Finished May 09 02:04:09 PM PDT 24
Peak memory 183556 kb
Host smart-bec6d091-9490-43e4-a205-5ee0a981a8ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492577109 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.2492577109
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.3671453810
Short name T138
Test name
Test status
Simulation time 79041158776 ps
CPU time 41.65 seconds
Started May 09 02:04:14 PM PDT 24
Finished May 09 02:04:56 PM PDT 24
Peak memory 193324 kb
Host smart-6c397768-38bb-43f7-b91f-3cb8ae757f9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671453810 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_a
ll.3671453810
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.3999632827
Short name T86
Test name
Test status
Simulation time 332472624891 ps
CPU time 651.71 seconds
Started May 09 02:04:15 PM PDT 24
Finished May 09 02:15:08 PM PDT 24
Peak memory 206744 kb
Host smart-5ec9e8f1-3262-4eb5-8075-00e04d2013c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999632827 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.3999632827
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.aon_timer_jump.1341038426
Short name T262
Test name
Test status
Simulation time 353037035 ps
CPU time 0.8 seconds
Started May 09 02:04:48 PM PDT 24
Finished May 09 02:04:50 PM PDT 24
Peak memory 183584 kb
Host smart-6376de1a-b5f0-46a6-9d28-d73d1a4f0dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341038426 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.1341038426
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.2152802965
Short name T137
Test name
Test status
Simulation time 48446829774 ps
CPU time 73.24 seconds
Started May 09 02:04:49 PM PDT 24
Finished May 09 02:06:03 PM PDT 24
Peak memory 183672 kb
Host smart-cdbf5376-783e-48f0-8f97-1cc5a862a6be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152802965 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.2152802965
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.2668111299
Short name T144
Test name
Test status
Simulation time 520722059 ps
CPU time 0.61 seconds
Started May 09 02:04:48 PM PDT 24
Finished May 09 02:04:50 PM PDT 24
Peak memory 183552 kb
Host smart-3d9d376b-9864-4698-83a5-661cb0a96374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668111299 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.2668111299
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.336908708
Short name T188
Test name
Test status
Simulation time 78128059760 ps
CPU time 112.64 seconds
Started May 09 02:04:49 PM PDT 24
Finished May 09 02:06:44 PM PDT 24
Peak memory 194308 kb
Host smart-1dca30d1-3484-4251-8cf1-7e6a81020e2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336908708 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_a
ll.336908708
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.692004036
Short name T211
Test name
Test status
Simulation time 80946340762 ps
CPU time 451.19 seconds
Started May 09 02:04:48 PM PDT 24
Finished May 09 02:12:20 PM PDT 24
Peak memory 198528 kb
Host smart-860a6bda-ed72-4580-bbfd-52ee5aa45d85
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692004036 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.692004036
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.aon_timer_jump.1093486701
Short name T191
Test name
Test status
Simulation time 595058620 ps
CPU time 0.77 seconds
Started May 09 02:04:49 PM PDT 24
Finished May 09 02:04:51 PM PDT 24
Peak memory 183488 kb
Host smart-9a57852a-ee39-4743-8762-1f6a3098631d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093486701 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.1093486701
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.2279330611
Short name T157
Test name
Test status
Simulation time 19124039674 ps
CPU time 30.85 seconds
Started May 09 02:04:48 PM PDT 24
Finished May 09 02:05:21 PM PDT 24
Peak memory 183604 kb
Host smart-edc01bf0-6371-4953-be91-0b1863e548eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279330611 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.2279330611
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.996150399
Short name T142
Test name
Test status
Simulation time 522179938 ps
CPU time 0.76 seconds
Started May 09 02:04:48 PM PDT 24
Finished May 09 02:04:50 PM PDT 24
Peak memory 183576 kb
Host smart-e39d1724-4aa8-4adf-9680-4c5da19efa49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996150399 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.996150399
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.1667014392
Short name T196
Test name
Test status
Simulation time 99853774859 ps
CPU time 32.3 seconds
Started May 09 02:04:49 PM PDT 24
Finished May 09 02:05:23 PM PDT 24
Peak memory 183664 kb
Host smart-63bb2001-160c-4726-9f3b-de19d0d72920
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667014392 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_
all.1667014392
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_jump.1693966880
Short name T95
Test name
Test status
Simulation time 519061236 ps
CPU time 0.92 seconds
Started May 09 02:04:50 PM PDT 24
Finished May 09 02:04:52 PM PDT 24
Peak memory 183548 kb
Host smart-6a7c71cb-6d9d-466f-a12a-8307018e773e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693966880 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.1693966880
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.2284346815
Short name T94
Test name
Test status
Simulation time 12614523550 ps
CPU time 9.5 seconds
Started May 09 02:04:49 PM PDT 24
Finished May 09 02:05:00 PM PDT 24
Peak memory 191784 kb
Host smart-e24a8be5-275e-44fb-85ca-a58bb7c9631b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284346815 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.2284346815
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.1476379414
Short name T125
Test name
Test status
Simulation time 566178983 ps
CPU time 0.93 seconds
Started May 09 02:04:48 PM PDT 24
Finished May 09 02:04:50 PM PDT 24
Peak memory 183536 kb
Host smart-5e533ce5-6431-490d-aa9f-447fb31a538a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476379414 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.1476379414
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.3047298919
Short name T176
Test name
Test status
Simulation time 224097863638 ps
CPU time 319.34 seconds
Started May 09 02:04:47 PM PDT 24
Finished May 09 02:10:07 PM PDT 24
Peak memory 195676 kb
Host smart-cba5b376-856f-4671-89f1-c329db11a44f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047298919 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_
all.3047298919
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.815727701
Short name T84
Test name
Test status
Simulation time 26920958087 ps
CPU time 202.54 seconds
Started May 09 02:04:49 PM PDT 24
Finished May 09 02:08:13 PM PDT 24
Peak memory 198540 kb
Host smart-0b9ea94b-aa00-43c6-b93b-77a6e39d2e5e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815727701 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.815727701
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_jump.3771926816
Short name T145
Test name
Test status
Simulation time 534763145 ps
CPU time 0.74 seconds
Started May 09 02:04:49 PM PDT 24
Finished May 09 02:04:51 PM PDT 24
Peak memory 183544 kb
Host smart-3e14a364-d002-4709-94d6-737e82bfb4ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771926816 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.3771926816
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.4103350060
Short name T119
Test name
Test status
Simulation time 14409309408 ps
CPU time 21.48 seconds
Started May 09 02:04:50 PM PDT 24
Finished May 09 02:05:13 PM PDT 24
Peak memory 191836 kb
Host smart-f5fe0f13-37d2-435f-9553-ef16e184a24f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103350060 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.4103350060
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.3672352725
Short name T189
Test name
Test status
Simulation time 391945140 ps
CPU time 1.07 seconds
Started May 09 02:04:49 PM PDT 24
Finished May 09 02:04:52 PM PDT 24
Peak memory 183600 kb
Host smart-dc933ad2-f47f-42c4-93e9-da122e355bfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672352725 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.3672352725
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.2634752857
Short name T132
Test name
Test status
Simulation time 120833530146 ps
CPU time 160.87 seconds
Started May 09 02:04:48 PM PDT 24
Finished May 09 02:07:31 PM PDT 24
Peak memory 183668 kb
Host smart-c0e84cf4-af84-4037-8dca-39ce96646868
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634752857 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_
all.2634752857
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.564445746
Short name T257
Test name
Test status
Simulation time 24369947244 ps
CPU time 255.45 seconds
Started May 09 02:04:48 PM PDT 24
Finished May 09 02:09:05 PM PDT 24
Peak memory 198556 kb
Host smart-e0742e74-fa1d-4c0f-a277-ce3b60f5bde7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564445746 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.564445746
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.aon_timer_jump.1911472837
Short name T255
Test name
Test status
Simulation time 578605697 ps
CPU time 0.81 seconds
Started May 09 02:04:50 PM PDT 24
Finished May 09 02:04:52 PM PDT 24
Peak memory 183556 kb
Host smart-28cd845e-5f00-493d-af06-19f32e01ee82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911472837 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.1911472837
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.71327893
Short name T129
Test name
Test status
Simulation time 7448214763 ps
CPU time 11.23 seconds
Started May 09 02:04:50 PM PDT 24
Finished May 09 02:05:03 PM PDT 24
Peak memory 183624 kb
Host smart-f4634654-d180-4470-9591-8d30b8847b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71327893 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.71327893
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.3359668199
Short name T163
Test name
Test status
Simulation time 380258419 ps
CPU time 0.8 seconds
Started May 09 02:04:50 PM PDT 24
Finished May 09 02:04:53 PM PDT 24
Peak memory 183552 kb
Host smart-f55c3057-04b8-4697-b88a-bd5afc645b15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359668199 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.3359668199
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.1690167265
Short name T213
Test name
Test status
Simulation time 95944049747 ps
CPU time 39.91 seconds
Started May 09 02:04:48 PM PDT 24
Finished May 09 02:05:29 PM PDT 24
Peak memory 183648 kb
Host smart-ed31ece5-b1ed-4cb9-bfa7-72d9c8623dcf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690167265 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_
all.1690167265
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_jump.3209794992
Short name T4
Test name
Test status
Simulation time 376660527 ps
CPU time 0.68 seconds
Started May 09 02:04:51 PM PDT 24
Finished May 09 02:04:53 PM PDT 24
Peak memory 183576 kb
Host smart-05f9552d-5dc6-4570-a77f-96bd9d1ffbba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209794992 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.3209794992
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.3826356121
Short name T236
Test name
Test status
Simulation time 35239932102 ps
CPU time 47.77 seconds
Started May 09 02:04:48 PM PDT 24
Finished May 09 02:05:37 PM PDT 24
Peak memory 191840 kb
Host smart-7e95f24e-d0c4-474b-a4fe-8fcd2eabd18b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826356121 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.3826356121
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.3001450444
Short name T170
Test name
Test status
Simulation time 426165428 ps
CPU time 0.69 seconds
Started May 09 02:04:49 PM PDT 24
Finished May 09 02:04:51 PM PDT 24
Peak memory 183576 kb
Host smart-8a603ae3-a83c-490e-8b13-bfccf9e35049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001450444 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.3001450444
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.4182765629
Short name T133
Test name
Test status
Simulation time 112707054414 ps
CPU time 146.65 seconds
Started May 09 02:05:00 PM PDT 24
Finished May 09 02:07:28 PM PDT 24
Peak memory 194856 kb
Host smart-68fc8fc9-2325-48fc-8052-a1ee0091128a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182765629 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_
all.4182765629
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.3659945407
Short name T80
Test name
Test status
Simulation time 410290222280 ps
CPU time 273.51 seconds
Started May 09 02:04:48 PM PDT 24
Finished May 09 02:09:23 PM PDT 24
Peak memory 198536 kb
Host smart-6c5ba1eb-c0da-4645-8279-8b1d3d662be3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659945407 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.3659945407
Directory /workspace/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.aon_timer_jump.2964334045
Short name T194
Test name
Test status
Simulation time 488093394 ps
CPU time 1.34 seconds
Started May 09 02:04:57 PM PDT 24
Finished May 09 02:05:00 PM PDT 24
Peak memory 183516 kb
Host smart-62dd8849-ee8b-4b6b-887e-bcbfda7e27ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964334045 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.2964334045
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.1218626338
Short name T128
Test name
Test status
Simulation time 5094374263 ps
CPU time 3.15 seconds
Started May 09 02:04:58 PM PDT 24
Finished May 09 02:05:03 PM PDT 24
Peak memory 183636 kb
Host smart-b63666db-b8a3-47ae-9e89-9cd3447b71a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218626338 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.1218626338
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.267798634
Short name T89
Test name
Test status
Simulation time 509483546 ps
CPU time 0.9 seconds
Started May 09 02:05:03 PM PDT 24
Finished May 09 02:05:04 PM PDT 24
Peak memory 183580 kb
Host smart-6b532a03-6170-409e-a6e9-f91e3593a034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267798634 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.267798634
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.283662444
Short name T19
Test name
Test status
Simulation time 389418624506 ps
CPU time 567.79 seconds
Started May 09 02:04:57 PM PDT 24
Finished May 09 02:14:25 PM PDT 24
Peak memory 195248 kb
Host smart-a64415f6-af76-433b-8611-59f685059ea3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283662444 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_a
ll.283662444
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/17.aon_timer_jump.574204830
Short name T3
Test name
Test status
Simulation time 592049515 ps
CPU time 1.52 seconds
Started May 09 02:04:59 PM PDT 24
Finished May 09 02:05:02 PM PDT 24
Peak memory 183568 kb
Host smart-31a1bc6f-e9b4-45b7-abe0-0918db6756cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574204830 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.574204830
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.2225339225
Short name T247
Test name
Test status
Simulation time 12004446326 ps
CPU time 4.83 seconds
Started May 09 02:04:59 PM PDT 24
Finished May 09 02:05:05 PM PDT 24
Peak memory 183604 kb
Host smart-877aa1a4-b544-4ae0-97a1-3549cf73bb91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225339225 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.2225339225
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.3810020387
Short name T52
Test name
Test status
Simulation time 435594752 ps
CPU time 1.21 seconds
Started May 09 02:04:59 PM PDT 24
Finished May 09 02:05:01 PM PDT 24
Peak memory 183556 kb
Host smart-d5f56b24-a81e-4fbb-8e9c-7fe920c19772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810020387 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.3810020387
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.3547332521
Short name T268
Test name
Test status
Simulation time 23722722748 ps
CPU time 239.69 seconds
Started May 09 02:04:58 PM PDT 24
Finished May 09 02:08:59 PM PDT 24
Peak memory 198536 kb
Host smart-aead7079-c34d-41ba-ae7f-08fdea955fdd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547332521 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.3547332521
Directory /workspace/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.aon_timer_jump.2752338504
Short name T5
Test name
Test status
Simulation time 402198248 ps
CPU time 0.75 seconds
Started May 09 02:05:00 PM PDT 24
Finished May 09 02:05:02 PM PDT 24
Peak memory 183556 kb
Host smart-168cff42-d478-4c70-b762-73919785029a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752338504 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.2752338504
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.1598862319
Short name T274
Test name
Test status
Simulation time 8264059897 ps
CPU time 12.49 seconds
Started May 09 02:04:58 PM PDT 24
Finished May 09 02:05:12 PM PDT 24
Peak memory 191840 kb
Host smart-7f0372a8-21e2-423e-a5b8-59e492c71387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598862319 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.1598862319
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.445489493
Short name T177
Test name
Test status
Simulation time 370902045 ps
CPU time 1.12 seconds
Started May 09 02:05:03 PM PDT 24
Finished May 09 02:05:05 PM PDT 24
Peak memory 183580 kb
Host smart-7f3465a2-1f19-4cc5-84fd-a9e13f17459e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445489493 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.445489493
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.1175922785
Short name T279
Test name
Test status
Simulation time 199465518265 ps
CPU time 85.01 seconds
Started May 09 02:04:57 PM PDT 24
Finished May 09 02:06:23 PM PDT 24
Peak memory 183576 kb
Host smart-a4bd12e1-e289-4156-9e23-110716e0edd8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175922785 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_
all.1175922785
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_jump.2256674771
Short name T166
Test name
Test status
Simulation time 473147655 ps
CPU time 0.61 seconds
Started May 09 02:05:00 PM PDT 24
Finished May 09 02:05:02 PM PDT 24
Peak memory 183540 kb
Host smart-d8332a13-35b8-4ddf-9597-298e6c859809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256674771 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.2256674771
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.1889487274
Short name T47
Test name
Test status
Simulation time 33630276190 ps
CPU time 11.61 seconds
Started May 09 02:04:58 PM PDT 24
Finished May 09 02:05:11 PM PDT 24
Peak memory 183608 kb
Host smart-7df8241b-170c-488f-8f00-0363a60ee462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889487274 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.1889487274
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.16169238
Short name T114
Test name
Test status
Simulation time 439682709 ps
CPU time 0.67 seconds
Started May 09 02:05:04 PM PDT 24
Finished May 09 02:05:05 PM PDT 24
Peak memory 183548 kb
Host smart-f0b77443-bc6c-4650-b8d1-e083bacafdfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16169238 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.16169238
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.886114352
Short name T230
Test name
Test status
Simulation time 52275320611 ps
CPU time 72.71 seconds
Started May 09 02:04:59 PM PDT 24
Finished May 09 02:06:13 PM PDT 24
Peak memory 183676 kb
Host smart-1ed37050-b967-4e66-b398-98d3aaccf3b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886114352 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_a
ll.886114352
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.3048438090
Short name T214
Test name
Test status
Simulation time 131243573863 ps
CPU time 278.78 seconds
Started May 09 02:04:59 PM PDT 24
Finished May 09 02:09:40 PM PDT 24
Peak memory 198556 kb
Host smart-7f241e49-a531-4be5-aa84-1b9be1cec32f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048438090 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.3048438090
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_jump.1999377341
Short name T249
Test name
Test status
Simulation time 571605278 ps
CPU time 1.38 seconds
Started May 09 02:04:17 PM PDT 24
Finished May 09 02:04:20 PM PDT 24
Peak memory 183592 kb
Host smart-34da3a25-0882-451a-91de-083ddeff72fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999377341 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.1999377341
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.1076612982
Short name T140
Test name
Test status
Simulation time 27809318601 ps
CPU time 3.56 seconds
Started May 09 02:04:16 PM PDT 24
Finished May 09 02:04:21 PM PDT 24
Peak memory 191868 kb
Host smart-563bf220-db22-4a64-a0e2-040e30c17e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076612982 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.1076612982
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.1363096483
Short name T22
Test name
Test status
Simulation time 3937773718 ps
CPU time 2.01 seconds
Started May 09 02:04:15 PM PDT 24
Finished May 09 02:04:19 PM PDT 24
Peak memory 214868 kb
Host smart-08b6424c-8034-4b20-b5ec-d6c384d3faef
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363096483 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.1363096483
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.799020518
Short name T217
Test name
Test status
Simulation time 509077356 ps
CPU time 0.91 seconds
Started May 09 02:04:15 PM PDT 24
Finished May 09 02:04:17 PM PDT 24
Peak memory 183528 kb
Host smart-54289867-bad2-4482-b5b0-e36180d9fb42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799020518 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.799020518
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.417464236
Short name T57
Test name
Test status
Simulation time 125314726124 ps
CPU time 33.33 seconds
Started May 09 02:04:17 PM PDT 24
Finished May 09 02:04:52 PM PDT 24
Peak memory 183672 kb
Host smart-3c83e007-953e-4a00-9399-524fc478aee9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417464236 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_al
l.417464236
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_jump.4244314126
Short name T154
Test name
Test status
Simulation time 562096389 ps
CPU time 0.67 seconds
Started May 09 02:05:01 PM PDT 24
Finished May 09 02:05:03 PM PDT 24
Peak memory 183576 kb
Host smart-3cec5cd1-4e55-4bb4-a153-815b4656a100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244314126 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.4244314126
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.1542598623
Short name T210
Test name
Test status
Simulation time 4636808769 ps
CPU time 7.09 seconds
Started May 09 02:04:59 PM PDT 24
Finished May 09 02:05:07 PM PDT 24
Peak memory 183632 kb
Host smart-247be453-6cd4-4da9-9920-c95330713507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542598623 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.1542598623
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.1949469714
Short name T218
Test name
Test status
Simulation time 472401869 ps
CPU time 0.61 seconds
Started May 09 02:05:04 PM PDT 24
Finished May 09 02:05:06 PM PDT 24
Peak memory 183560 kb
Host smart-3dd94789-ae4c-4642-a0aa-f9539c22368a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949469714 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.1949469714
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.2136865086
Short name T205
Test name
Test status
Simulation time 88840710308 ps
CPU time 210.08 seconds
Started May 09 02:05:02 PM PDT 24
Finished May 09 02:08:33 PM PDT 24
Peak memory 198480 kb
Host smart-9e708ce7-0575-4e3e-9fec-87ba263ecaee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136865086 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.2136865086
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_jump.637206907
Short name T263
Test name
Test status
Simulation time 362179973 ps
CPU time 1.06 seconds
Started May 09 02:05:09 PM PDT 24
Finished May 09 02:05:12 PM PDT 24
Peak memory 183552 kb
Host smart-75e42db7-533f-4d0b-91c9-91848864cd92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637206907 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.637206907
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.2831052360
Short name T231
Test name
Test status
Simulation time 32388882076 ps
CPU time 47.96 seconds
Started May 09 02:05:09 PM PDT 24
Finished May 09 02:05:59 PM PDT 24
Peak memory 183644 kb
Host smart-45e4efd5-6db7-482c-8159-3e976c739939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831052360 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.2831052360
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.1959083051
Short name T269
Test name
Test status
Simulation time 544501917 ps
CPU time 0.99 seconds
Started May 09 02:05:10 PM PDT 24
Finished May 09 02:05:13 PM PDT 24
Peak memory 183576 kb
Host smart-e9411720-3c21-4cd9-b216-ccc4f6845e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959083051 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.1959083051
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.1930013217
Short name T264
Test name
Test status
Simulation time 152816382266 ps
CPU time 27.74 seconds
Started May 09 02:05:09 PM PDT 24
Finished May 09 02:05:38 PM PDT 24
Peak memory 193792 kb
Host smart-77dbc40e-875a-46a7-bc14-34288413016c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930013217 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_
all.1930013217
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_jump.1220553642
Short name T51
Test name
Test status
Simulation time 590566432 ps
CPU time 0.97 seconds
Started May 09 02:05:11 PM PDT 24
Finished May 09 02:05:13 PM PDT 24
Peak memory 183552 kb
Host smart-467cfd94-2a58-4be7-8643-58e49b069aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220553642 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.1220553642
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.966973050
Short name T228
Test name
Test status
Simulation time 23700716550 ps
CPU time 10.52 seconds
Started May 09 02:05:12 PM PDT 24
Finished May 09 02:05:24 PM PDT 24
Peak memory 183616 kb
Host smart-2a4aba69-7f01-4742-abf0-f2c98a0c54fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966973050 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.966973050
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.1936265361
Short name T271
Test name
Test status
Simulation time 573040692 ps
CPU time 0.76 seconds
Started May 09 02:05:11 PM PDT 24
Finished May 09 02:05:14 PM PDT 24
Peak memory 183600 kb
Host smart-9c1d67f7-8e5e-43f7-ae93-e0175068afd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936265361 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.1936265361
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.3956029847
Short name T220
Test name
Test status
Simulation time 28487546818 ps
CPU time 11.86 seconds
Started May 09 02:05:10 PM PDT 24
Finished May 09 02:05:24 PM PDT 24
Peak memory 183604 kb
Host smart-2504beb0-8ed9-4a6d-b67f-e9497efd0be9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956029847 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_
all.3956029847
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.4139873105
Short name T153
Test name
Test status
Simulation time 29292984962 ps
CPU time 129.42 seconds
Started May 09 02:05:12 PM PDT 24
Finished May 09 02:07:23 PM PDT 24
Peak memory 198468 kb
Host smart-7335a1a8-169c-4105-b52f-76594bf6ceeb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139873105 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.4139873105
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.aon_timer_jump.1023934675
Short name T175
Test name
Test status
Simulation time 557036630 ps
CPU time 1.36 seconds
Started May 09 02:05:09 PM PDT 24
Finished May 09 02:05:12 PM PDT 24
Peak memory 183572 kb
Host smart-645a5d20-a383-4882-b60f-078670ef0176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023934675 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.1023934675
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.1318834554
Short name T151
Test name
Test status
Simulation time 15684928797 ps
CPU time 25.32 seconds
Started May 09 02:05:10 PM PDT 24
Finished May 09 02:05:37 PM PDT 24
Peak memory 191820 kb
Host smart-8b639316-b1d6-42d4-a956-f2e2636f623c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318834554 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.1318834554
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.3745885689
Short name T221
Test name
Test status
Simulation time 470974419 ps
CPU time 1.17 seconds
Started May 09 02:05:10 PM PDT 24
Finished May 09 02:05:12 PM PDT 24
Peak memory 183372 kb
Host smart-7f6bfc4a-5cf6-4616-8e8b-565d9c51aed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745885689 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.3745885689
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.1670849598
Short name T104
Test name
Test status
Simulation time 497005348802 ps
CPU time 767.77 seconds
Started May 09 02:05:20 PM PDT 24
Finished May 09 02:18:10 PM PDT 24
Peak memory 183676 kb
Host smart-7d1c8116-b3d8-4dc6-8aed-e529dd679a19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670849598 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_
all.1670849598
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.2979508006
Short name T270
Test name
Test status
Simulation time 127648143577 ps
CPU time 264.9 seconds
Started May 09 02:05:09 PM PDT 24
Finished May 09 02:09:35 PM PDT 24
Peak memory 198472 kb
Host smart-e33e9e46-2bc1-4319-96bd-00b170f29d42
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979508006 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.2979508006
Directory /workspace/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.aon_timer_jump.2923011471
Short name T2
Test name
Test status
Simulation time 441235787 ps
CPU time 0.71 seconds
Started May 09 02:05:22 PM PDT 24
Finished May 09 02:05:24 PM PDT 24
Peak memory 183540 kb
Host smart-d43c466a-b3a8-4eeb-b4be-c9ed042dbab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923011471 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.2923011471
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.2999411206
Short name T238
Test name
Test status
Simulation time 19870487172 ps
CPU time 3.77 seconds
Started May 09 02:05:20 PM PDT 24
Finished May 09 02:05:26 PM PDT 24
Peak memory 183604 kb
Host smart-e02cba39-df61-4c73-bdeb-eaebf4620139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999411206 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.2999411206
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.1843173102
Short name T143
Test name
Test status
Simulation time 490955157 ps
CPU time 0.86 seconds
Started May 09 02:05:19 PM PDT 24
Finished May 09 02:05:22 PM PDT 24
Peak memory 183580 kb
Host smart-40d98ba0-c97e-4bdd-a27b-7a825b7653a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843173102 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.1843173102
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.2377717730
Short name T243
Test name
Test status
Simulation time 46878242053 ps
CPU time 19.13 seconds
Started May 09 02:05:20 PM PDT 24
Finished May 09 02:05:41 PM PDT 24
Peak memory 191848 kb
Host smart-835066d5-6e95-4efc-940d-0931c9830bf6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377717730 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_
all.2377717730
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.239517113
Short name T261
Test name
Test status
Simulation time 113510445542 ps
CPU time 379.79 seconds
Started May 09 02:05:18 PM PDT 24
Finished May 09 02:11:40 PM PDT 24
Peak memory 198496 kb
Host smart-a1ac657d-698e-4807-9d4c-879cbb8bc836
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239517113 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand_reset.239517113
Directory /workspace/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.aon_timer_jump.1094210456
Short name T12
Test name
Test status
Simulation time 457019527 ps
CPU time 0.93 seconds
Started May 09 02:05:19 PM PDT 24
Finished May 09 02:05:22 PM PDT 24
Peak memory 183560 kb
Host smart-a071eb6b-5cec-4921-a65e-8e76bdc1f7d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094210456 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.1094210456
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.3561234790
Short name T150
Test name
Test status
Simulation time 22599316433 ps
CPU time 35.99 seconds
Started May 09 02:05:18 PM PDT 24
Finished May 09 02:05:56 PM PDT 24
Peak memory 183660 kb
Host smart-45505e1d-3608-4175-82da-6954e05eb147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561234790 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.3561234790
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.3141546294
Short name T146
Test name
Test status
Simulation time 601616314 ps
CPU time 1.49 seconds
Started May 09 02:05:19 PM PDT 24
Finished May 09 02:05:22 PM PDT 24
Peak memory 183576 kb
Host smart-019e808c-5315-4545-bc70-8c07faf084c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141546294 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.3141546294
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.1192744325
Short name T102
Test name
Test status
Simulation time 61935243713 ps
CPU time 87.54 seconds
Started May 09 02:05:19 PM PDT 24
Finished May 09 02:06:48 PM PDT 24
Peak memory 183604 kb
Host smart-90ee53ba-6abd-4b1b-be22-d1e1569e0997
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192744325 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_
all.1192744325
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.3268319059
Short name T159
Test name
Test status
Simulation time 70516960743 ps
CPU time 231.44 seconds
Started May 09 02:05:21 PM PDT 24
Finished May 09 02:09:14 PM PDT 24
Peak memory 198584 kb
Host smart-8f68627a-fa46-4e10-82c6-d8a3c45b1fcc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268319059 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.3268319059
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.aon_timer_jump.118672932
Short name T50
Test name
Test status
Simulation time 376233713 ps
CPU time 0.73 seconds
Started May 09 02:05:21 PM PDT 24
Finished May 09 02:05:23 PM PDT 24
Peak memory 183596 kb
Host smart-5df21511-47c3-4489-af2e-c0d7502f8aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118672932 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.118672932
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.342275297
Short name T130
Test name
Test status
Simulation time 33491858067 ps
CPU time 49.81 seconds
Started May 09 02:05:19 PM PDT 24
Finished May 09 02:06:11 PM PDT 24
Peak memory 183632 kb
Host smart-4f7ae281-8e30-4c99-a38c-d03c49825fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342275297 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.342275297
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.1048627772
Short name T244
Test name
Test status
Simulation time 520843482 ps
CPU time 1.3 seconds
Started May 09 02:05:22 PM PDT 24
Finished May 09 02:05:25 PM PDT 24
Peak memory 183560 kb
Host smart-ce7a1355-5047-490d-a4ad-86d28e6add98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048627772 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.1048627772
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.1562197972
Short name T54
Test name
Test status
Simulation time 174360272103 ps
CPU time 70.17 seconds
Started May 09 02:05:18 PM PDT 24
Finished May 09 02:06:30 PM PDT 24
Peak memory 194352 kb
Host smart-62017589-1390-4406-a430-603396cd2a60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562197972 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_
all.1562197972
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.3988778187
Short name T106
Test name
Test status
Simulation time 44630532238 ps
CPU time 495.53 seconds
Started May 09 02:05:20 PM PDT 24
Finished May 09 02:13:38 PM PDT 24
Peak memory 198476 kb
Host smart-dbd145d9-e000-484b-afcd-191c057d0138
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988778187 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.3988778187
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_jump.2717036931
Short name T31
Test name
Test status
Simulation time 500435456 ps
CPU time 1.34 seconds
Started May 09 02:05:20 PM PDT 24
Finished May 09 02:05:23 PM PDT 24
Peak memory 183544 kb
Host smart-b818c925-942a-4435-9276-d97dac113ad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717036931 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.2717036931
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.867572085
Short name T183
Test name
Test status
Simulation time 1906901047 ps
CPU time 0.73 seconds
Started May 09 02:05:20 PM PDT 24
Finished May 09 02:05:23 PM PDT 24
Peak memory 183564 kb
Host smart-65ca3f32-69eb-4db7-87da-0ae408801b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867572085 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.867572085
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.1622284139
Short name T195
Test name
Test status
Simulation time 437685541 ps
CPU time 1.14 seconds
Started May 09 02:05:22 PM PDT 24
Finished May 09 02:05:25 PM PDT 24
Peak memory 183560 kb
Host smart-a2c24f98-5ab2-4753-b2eb-1b764267e559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622284139 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.1622284139
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.128245362
Short name T18
Test name
Test status
Simulation time 169487170866 ps
CPU time 68.42 seconds
Started May 09 02:05:28 PM PDT 24
Finished May 09 02:06:37 PM PDT 24
Peak memory 195180 kb
Host smart-d32e527f-2804-47a6-9de2-318c0275f762
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128245362 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_a
ll.128245362
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_jump.4069776540
Short name T92
Test name
Test status
Simulation time 611109218 ps
CPU time 0.76 seconds
Started May 09 02:05:28 PM PDT 24
Finished May 09 02:05:30 PM PDT 24
Peak memory 183528 kb
Host smart-1b45ca59-2982-40be-8b28-58cb9b79f727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069776540 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.4069776540
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.2132710389
Short name T198
Test name
Test status
Simulation time 26033758617 ps
CPU time 28.9 seconds
Started May 09 02:05:29 PM PDT 24
Finished May 09 02:06:00 PM PDT 24
Peak memory 183580 kb
Host smart-84a504cf-dde8-490b-9f03-01509290d814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132710389 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.2132710389
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.3274009222
Short name T203
Test name
Test status
Simulation time 466090992 ps
CPU time 0.76 seconds
Started May 09 02:05:30 PM PDT 24
Finished May 09 02:05:32 PM PDT 24
Peak memory 183552 kb
Host smart-42b87b35-c36a-4e0a-a9bb-58f361e92604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274009222 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.3274009222
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.2565187240
Short name T266
Test name
Test status
Simulation time 29957519831 ps
CPU time 15.43 seconds
Started May 09 02:05:28 PM PDT 24
Finished May 09 02:05:45 PM PDT 24
Peak memory 194392 kb
Host smart-a419d33b-84cd-4174-a6cf-bb6e4418e8bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565187240 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_
all.2565187240
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.867704725
Short name T30
Test name
Test status
Simulation time 104840517101 ps
CPU time 502.6 seconds
Started May 09 02:05:29 PM PDT 24
Finished May 09 02:13:53 PM PDT 24
Peak memory 198572 kb
Host smart-b62bcbcb-e045-46bd-ad07-12b842332f19
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867704725 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.867704725
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.aon_timer_jump.3072655599
Short name T124
Test name
Test status
Simulation time 572646219 ps
CPU time 1.43 seconds
Started May 09 02:05:29 PM PDT 24
Finished May 09 02:05:32 PM PDT 24
Peak memory 183516 kb
Host smart-8f8ced69-ff9f-47b1-8c96-30abf36b7338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072655599 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.3072655599
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.924279927
Short name T149
Test name
Test status
Simulation time 26739071287 ps
CPU time 36.99 seconds
Started May 09 02:05:27 PM PDT 24
Finished May 09 02:06:05 PM PDT 24
Peak memory 183640 kb
Host smart-ef0efb80-9338-40d7-9c51-4777f3be8680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924279927 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.924279927
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.38421208
Short name T123
Test name
Test status
Simulation time 457886913 ps
CPU time 0.89 seconds
Started May 09 02:05:30 PM PDT 24
Finished May 09 02:05:32 PM PDT 24
Peak memory 183492 kb
Host smart-f086ea40-48d9-41a5-bb6b-30233364ae95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38421208 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.38421208
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.1536315212
Short name T254
Test name
Test status
Simulation time 37791835133 ps
CPU time 54.12 seconds
Started May 09 02:05:28 PM PDT 24
Finished May 09 02:06:24 PM PDT 24
Peak memory 183668 kb
Host smart-03dad816-3f95-4a21-a698-46baaea289f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536315212 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_
all.1536315212
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_jump.93132785
Short name T9
Test name
Test status
Simulation time 478437803 ps
CPU time 0.59 seconds
Started May 09 02:04:15 PM PDT 24
Finished May 09 02:04:16 PM PDT 24
Peak memory 183564 kb
Host smart-23def353-f170-46da-9745-d325756691d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93132785 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.93132785
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.3906144182
Short name T258
Test name
Test status
Simulation time 20233981595 ps
CPU time 17.97 seconds
Started May 09 02:04:15 PM PDT 24
Finished May 09 02:04:34 PM PDT 24
Peak memory 191844 kb
Host smart-a1b3de9c-82ea-435b-b6f7-844ff9eacbb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906144182 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.3906144182
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.2706726320
Short name T23
Test name
Test status
Simulation time 3912706948 ps
CPU time 3.57 seconds
Started May 09 02:04:15 PM PDT 24
Finished May 09 02:04:20 PM PDT 24
Peak memory 214916 kb
Host smart-5e6851ab-fcb6-4050-979a-ead5d3166092
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706726320 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.2706726320
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.4188888720
Short name T250
Test name
Test status
Simulation time 439489879 ps
CPU time 0.71 seconds
Started May 09 02:04:17 PM PDT 24
Finished May 09 02:04:20 PM PDT 24
Peak memory 183568 kb
Host smart-28121aa4-f8d1-4b89-9c5e-b30fbc1c5e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188888720 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.4188888720
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.4079970775
Short name T136
Test name
Test status
Simulation time 80494919357 ps
CPU time 33.03 seconds
Started May 09 02:04:15 PM PDT 24
Finished May 09 02:04:50 PM PDT 24
Peak memory 194872 kb
Host smart-21fc5f43-c92b-448c-a043-d47b92e67ec4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079970775 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_a
ll.4079970775
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.44202763
Short name T206
Test name
Test status
Simulation time 26223361035 ps
CPU time 269.07 seconds
Started May 09 02:04:15 PM PDT 24
Finished May 09 02:08:45 PM PDT 24
Peak memory 198516 kb
Host smart-751fa5a6-8b55-44e1-ba0f-92498971928c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44202763 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.44202763
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_jump.963443541
Short name T96
Test name
Test status
Simulation time 418795466 ps
CPU time 0.66 seconds
Started May 09 02:05:29 PM PDT 24
Finished May 09 02:05:31 PM PDT 24
Peak memory 183564 kb
Host smart-79a3aade-1db5-4fb4-a0ff-66f52726f74f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963443541 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.963443541
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.2694764251
Short name T182
Test name
Test status
Simulation time 15581299569 ps
CPU time 24.06 seconds
Started May 09 02:05:29 PM PDT 24
Finished May 09 02:05:54 PM PDT 24
Peak memory 191796 kb
Host smart-1155aef9-0c78-47aa-ba6c-c4c69307cdf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694764251 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.2694764251
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.2922602903
Short name T240
Test name
Test status
Simulation time 453627393 ps
CPU time 0.69 seconds
Started May 09 02:05:28 PM PDT 24
Finished May 09 02:05:30 PM PDT 24
Peak memory 183624 kb
Host smart-8f4b3d3a-15d3-404c-a289-b4c932d36fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922602903 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.2922602903
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.3198339081
Short name T107
Test name
Test status
Simulation time 48984377930 ps
CPU time 21.39 seconds
Started May 09 02:05:30 PM PDT 24
Finished May 09 02:05:52 PM PDT 24
Peak memory 183732 kb
Host smart-5e1d24e6-f77e-452c-9314-cf6391d98622
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198339081 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_
all.3198339081
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.3719665019
Short name T158
Test name
Test status
Simulation time 27040821430 ps
CPU time 217.74 seconds
Started May 09 02:05:28 PM PDT 24
Finished May 09 02:09:07 PM PDT 24
Peak memory 198568 kb
Host smart-c598083f-9773-425b-8a2e-dfdc1fd22a03
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719665019 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.3719665019
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.3814194332
Short name T227
Test name
Test status
Simulation time 30672658402 ps
CPU time 11.71 seconds
Started May 09 02:05:29 PM PDT 24
Finished May 09 02:05:42 PM PDT 24
Peak memory 191752 kb
Host smart-2d1ded9f-9630-44ea-b79e-9be1e75b22ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814194332 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.3814194332
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.3866709284
Short name T233
Test name
Test status
Simulation time 427776887 ps
CPU time 1.25 seconds
Started May 09 02:05:28 PM PDT 24
Finished May 09 02:05:31 PM PDT 24
Peak memory 183600 kb
Host smart-0f730740-6265-49e2-bd4e-96e34e93c289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866709284 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.3866709284
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.165988614
Short name T100
Test name
Test status
Simulation time 284546212892 ps
CPU time 408.63 seconds
Started May 09 02:05:40 PM PDT 24
Finished May 09 02:12:31 PM PDT 24
Peak memory 195192 kb
Host smart-7b504155-1c2a-43e8-8f94-f760e259e71f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165988614 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_a
ll.165988614
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.374450346
Short name T34
Test name
Test status
Simulation time 123432329022 ps
CPU time 236.94 seconds
Started May 09 02:05:41 PM PDT 24
Finished May 09 02:09:40 PM PDT 24
Peak memory 198484 kb
Host smart-cbfe30be-0762-451c-ab0c-0f5f42e08330
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374450346 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.374450346
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.aon_timer_jump.3213298585
Short name T14
Test name
Test status
Simulation time 379903923 ps
CPU time 0.85 seconds
Started May 09 02:05:40 PM PDT 24
Finished May 09 02:05:44 PM PDT 24
Peak memory 183556 kb
Host smart-7061de09-89b3-4b07-91f5-9dbc663b889e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213298585 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.3213298585
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.356540977
Short name T7
Test name
Test status
Simulation time 28895499685 ps
CPU time 6.37 seconds
Started May 09 02:05:41 PM PDT 24
Finished May 09 02:05:50 PM PDT 24
Peak memory 183592 kb
Host smart-ff7c8299-2d17-4ca6-a3ac-dacdea8bb952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356540977 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.356540977
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.3493855808
Short name T248
Test name
Test status
Simulation time 506653472 ps
CPU time 1.38 seconds
Started May 09 02:05:41 PM PDT 24
Finished May 09 02:05:45 PM PDT 24
Peak memory 183524 kb
Host smart-e90cb349-b58e-4a71-b3f4-aa6a52b8c5a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493855808 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.3493855808
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.2945986049
Short name T81
Test name
Test status
Simulation time 61347468966 ps
CPU time 222.81 seconds
Started May 09 02:05:40 PM PDT 24
Finished May 09 02:09:25 PM PDT 24
Peak memory 198536 kb
Host smart-a1560e05-b8bb-4791-87d8-8b53c5ae389a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945986049 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_reset.2945986049
Directory /workspace/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.aon_timer_jump.1973407864
Short name T121
Test name
Test status
Simulation time 582661664 ps
CPU time 0.66 seconds
Started May 09 02:05:40 PM PDT 24
Finished May 09 02:05:43 PM PDT 24
Peak memory 183572 kb
Host smart-880ee6b3-d862-4006-bea3-f6edf06f44da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973407864 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.1973407864
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.3902066019
Short name T172
Test name
Test status
Simulation time 9552728006 ps
CPU time 4.42 seconds
Started May 09 02:05:41 PM PDT 24
Finished May 09 02:05:48 PM PDT 24
Peak memory 183632 kb
Host smart-fbbb1e97-eb59-4b1a-824b-92a30eb4d899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902066019 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.3902066019
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.4282120495
Short name T223
Test name
Test status
Simulation time 390127324 ps
CPU time 0.86 seconds
Started May 09 02:05:41 PM PDT 24
Finished May 09 02:05:44 PM PDT 24
Peak memory 183560 kb
Host smart-d406478a-29af-46a5-a9e9-1c8f195fac03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282120495 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.4282120495
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.1262519789
Short name T35
Test name
Test status
Simulation time 21598455842 ps
CPU time 7.65 seconds
Started May 09 02:05:52 PM PDT 24
Finished May 09 02:06:01 PM PDT 24
Peak memory 183576 kb
Host smart-f3f5a444-691a-4878-b8a5-8a23bf064914
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262519789 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_
all.1262519789
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.246219908
Short name T58
Test name
Test status
Simulation time 82838074447 ps
CPU time 466.19 seconds
Started May 09 02:05:54 PM PDT 24
Finished May 09 02:13:43 PM PDT 24
Peak memory 198536 kb
Host smart-9de66df7-cd57-468c-8a54-d34acf1d94b6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246219908 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.246219908
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.aon_timer_jump.2495232529
Short name T259
Test name
Test status
Simulation time 366223957 ps
CPU time 1.05 seconds
Started May 09 02:05:56 PM PDT 24
Finished May 09 02:05:59 PM PDT 24
Peak memory 183516 kb
Host smart-02b9d57a-bab5-462d-a839-346867b6bc78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495232529 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.2495232529
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.3961692832
Short name T226
Test name
Test status
Simulation time 16006476675 ps
CPU time 21.15 seconds
Started May 09 02:05:53 PM PDT 24
Finished May 09 02:06:16 PM PDT 24
Peak memory 183584 kb
Host smart-92919a6c-ffc4-4a31-97d8-9ad8d0988d92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961692832 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.3961692832
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.2877075564
Short name T277
Test name
Test status
Simulation time 505368373 ps
CPU time 0.59 seconds
Started May 09 02:05:52 PM PDT 24
Finished May 09 02:05:54 PM PDT 24
Peak memory 183544 kb
Host smart-65df1c90-8c42-4f41-ad47-f85a54c11ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877075564 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.2877075564
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.2080538338
Short name T168
Test name
Test status
Simulation time 524122624744 ps
CPU time 772.29 seconds
Started May 09 02:05:53 PM PDT 24
Finished May 09 02:18:47 PM PDT 24
Peak memory 195572 kb
Host smart-873e11ce-c892-466c-9227-9ea55153154d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080538338 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_
all.2080538338
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.3793709175
Short name T56
Test name
Test status
Simulation time 676322486940 ps
CPU time 723.36 seconds
Started May 09 02:05:53 PM PDT 24
Finished May 09 02:17:59 PM PDT 24
Peak memory 200964 kb
Host smart-741aa135-7aa9-4420-a725-e59c28c89366
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793709175 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.3793709175
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.aon_timer_jump.1925117444
Short name T161
Test name
Test status
Simulation time 538803749 ps
CPU time 1.29 seconds
Started May 09 02:05:52 PM PDT 24
Finished May 09 02:05:54 PM PDT 24
Peak memory 183556 kb
Host smart-25405c7b-fe80-4e84-830c-ddc3d5682861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925117444 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.1925117444
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.2005577803
Short name T101
Test name
Test status
Simulation time 9159118991 ps
CPU time 5.86 seconds
Started May 09 02:05:53 PM PDT 24
Finished May 09 02:06:01 PM PDT 24
Peak memory 183632 kb
Host smart-d808acce-5770-4575-8842-be66b28729ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005577803 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.2005577803
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.1707367631
Short name T224
Test name
Test status
Simulation time 348785945 ps
CPU time 1.07 seconds
Started May 09 02:05:54 PM PDT 24
Finished May 09 02:05:57 PM PDT 24
Peak memory 183560 kb
Host smart-6bb5f8eb-0586-45d4-85f8-07f4fe64e53d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707367631 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.1707367631
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.2450574758
Short name T253
Test name
Test status
Simulation time 335061495745 ps
CPU time 293.54 seconds
Started May 09 02:05:53 PM PDT 24
Finished May 09 02:10:49 PM PDT 24
Peak memory 193344 kb
Host smart-f65ee9ba-35ee-4876-b186-5c18bd25ec0b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450574758 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_
all.2450574758
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.3852619020
Short name T49
Test name
Test status
Simulation time 127127568756 ps
CPU time 224.83 seconds
Started May 09 02:05:53 PM PDT 24
Finished May 09 02:09:40 PM PDT 24
Peak memory 198500 kb
Host smart-1b18f5f6-7e21-4ccc-9ce1-6f0135f925b2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852619020 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.3852619020
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.aon_timer_jump.1907506870
Short name T115
Test name
Test status
Simulation time 389799597 ps
CPU time 0.72 seconds
Started May 09 02:05:52 PM PDT 24
Finished May 09 02:05:55 PM PDT 24
Peak memory 183572 kb
Host smart-cca4532f-291d-43a3-b8ba-cd784e07b701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907506870 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.1907506870
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.1078537602
Short name T197
Test name
Test status
Simulation time 14606254424 ps
CPU time 4 seconds
Started May 09 02:05:53 PM PDT 24
Finished May 09 02:05:59 PM PDT 24
Peak memory 183636 kb
Host smart-ef1b1a6e-303a-49ee-8b1a-dca5c6a7c8f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078537602 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.1078537602
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.2094366975
Short name T32
Test name
Test status
Simulation time 576132547 ps
CPU time 1.47 seconds
Started May 09 02:05:55 PM PDT 24
Finished May 09 02:05:58 PM PDT 24
Peak memory 183580 kb
Host smart-61df09f2-b774-4406-ac73-303ad2d03375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094366975 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.2094366975
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.3816571872
Short name T251
Test name
Test status
Simulation time 677077468001 ps
CPU time 251.73 seconds
Started May 09 02:05:52 PM PDT 24
Finished May 09 02:10:06 PM PDT 24
Peak memory 191808 kb
Host smart-74ea4281-17a4-4dbb-b61f-b8105e23fe7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816571872 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_
all.3816571872
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.1324257368
Short name T85
Test name
Test status
Simulation time 264183965130 ps
CPU time 518.05 seconds
Started May 09 02:05:56 PM PDT 24
Finished May 09 02:14:36 PM PDT 24
Peak memory 198476 kb
Host smart-81002358-9fcc-4172-bb6c-71469ca0e872
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324257368 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.1324257368
Directory /workspace/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.aon_timer_jump.1739002424
Short name T278
Test name
Test status
Simulation time 532007231 ps
CPU time 1.44 seconds
Started May 09 02:05:52 PM PDT 24
Finished May 09 02:05:55 PM PDT 24
Peak memory 183584 kb
Host smart-f065b8ab-2d1e-4b5b-931c-364ee2c6ea29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739002424 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.1739002424
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.2026061844
Short name T55
Test name
Test status
Simulation time 37219567259 ps
CPU time 25.76 seconds
Started May 09 02:05:57 PM PDT 24
Finished May 09 02:06:25 PM PDT 24
Peak memory 183576 kb
Host smart-74d2b355-df71-4b44-984f-b65809cd645d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026061844 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.2026061844
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.3898190017
Short name T116
Test name
Test status
Simulation time 529845148 ps
CPU time 0.79 seconds
Started May 09 02:05:56 PM PDT 24
Finished May 09 02:05:59 PM PDT 24
Peak memory 183572 kb
Host smart-c4fa3893-7929-4cb5-b522-a71d92f9069e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898190017 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.3898190017
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.827663216
Short name T178
Test name
Test status
Simulation time 196338613308 ps
CPU time 67.35 seconds
Started May 09 02:05:52 PM PDT 24
Finished May 09 02:07:00 PM PDT 24
Peak memory 194844 kb
Host smart-8a8b1188-d82d-466a-affe-937d8bbf957f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827663216 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_a
ll.827663216
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.3711869102
Short name T187
Test name
Test status
Simulation time 17467454107 ps
CPU time 85.41 seconds
Started May 09 02:05:53 PM PDT 24
Finished May 09 02:07:21 PM PDT 24
Peak memory 198560 kb
Host smart-1fbbf88e-7088-4006-9755-75cb511abeb4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711869102 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.3711869102
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.aon_timer_jump.2281392935
Short name T204
Test name
Test status
Simulation time 402749940 ps
CPU time 1.21 seconds
Started May 09 02:05:54 PM PDT 24
Finished May 09 02:05:57 PM PDT 24
Peak memory 183576 kb
Host smart-85e86245-3bb5-4c31-b697-89fcbb629b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281392935 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.2281392935
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.2037343135
Short name T265
Test name
Test status
Simulation time 25351531651 ps
CPU time 17.64 seconds
Started May 09 02:05:54 PM PDT 24
Finished May 09 02:06:13 PM PDT 24
Peak memory 183620 kb
Host smart-af740764-b9ad-42ab-b512-919b8658e9f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037343135 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.2037343135
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.537832167
Short name T246
Test name
Test status
Simulation time 428296743 ps
CPU time 0.72 seconds
Started May 09 02:05:52 PM PDT 24
Finished May 09 02:05:54 PM PDT 24
Peak memory 183556 kb
Host smart-12a4c0a4-73fa-48ee-bab0-4eb6859a4c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537832167 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.537832167
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.1767009745
Short name T126
Test name
Test status
Simulation time 257185593204 ps
CPU time 346.85 seconds
Started May 09 02:05:53 PM PDT 24
Finished May 09 02:11:42 PM PDT 24
Peak memory 183648 kb
Host smart-d1866221-5f9c-42b3-afe5-978746988841
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767009745 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_
all.1767009745
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.1751800030
Short name T21
Test name
Test status
Simulation time 11565264695 ps
CPU time 104.6 seconds
Started May 09 02:05:53 PM PDT 24
Finished May 09 02:07:40 PM PDT 24
Peak memory 198460 kb
Host smart-a247c7aa-815e-4e31-b031-f81f9ace1e59
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751800030 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand_reset.1751800030
Directory /workspace/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.aon_timer_jump.489526078
Short name T118
Test name
Test status
Simulation time 425871071 ps
CPU time 0.92 seconds
Started May 09 02:06:03 PM PDT 24
Finished May 09 02:06:05 PM PDT 24
Peak memory 183568 kb
Host smart-14032a40-0af0-4d14-af94-25fc512b4ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489526078 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.489526078
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.1612349786
Short name T97
Test name
Test status
Simulation time 1106713640 ps
CPU time 1.99 seconds
Started May 09 02:06:05 PM PDT 24
Finished May 09 02:06:09 PM PDT 24
Peak memory 183552 kb
Host smart-6acd8c4b-c408-4596-af63-f6f0c8e17e73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612349786 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.1612349786
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.3711601059
Short name T160
Test name
Test status
Simulation time 409556126 ps
CPU time 0.82 seconds
Started May 09 02:06:02 PM PDT 24
Finished May 09 02:06:04 PM PDT 24
Peak memory 183608 kb
Host smart-8530dca2-d9b1-445c-bc4c-1df99901f126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711601059 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.3711601059
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.2522522234
Short name T202
Test name
Test status
Simulation time 76395452288 ps
CPU time 28.88 seconds
Started May 09 02:06:03 PM PDT 24
Finished May 09 02:06:33 PM PDT 24
Peak memory 183612 kb
Host smart-2ce1dce3-db78-49e6-9b1b-777c29390de0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522522234 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_
all.2522522234
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.3380269222
Short name T79
Test name
Test status
Simulation time 89614278593 ps
CPU time 970.02 seconds
Started May 09 02:06:02 PM PDT 24
Finished May 09 02:22:14 PM PDT 24
Peak memory 214912 kb
Host smart-3980e068-96e7-48b8-8566-d11f782c966c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380269222 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.3380269222
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_jump.3030757724
Short name T225
Test name
Test status
Simulation time 542288998 ps
CPU time 1.4 seconds
Started May 09 02:04:26 PM PDT 24
Finished May 09 02:04:28 PM PDT 24
Peak memory 183536 kb
Host smart-5bb151cb-7903-4997-9ee3-5d0ae8170b6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030757724 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.3030757724
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.1150320195
Short name T239
Test name
Test status
Simulation time 28073218566 ps
CPU time 42.14 seconds
Started May 09 02:04:25 PM PDT 24
Finished May 09 02:05:08 PM PDT 24
Peak memory 191852 kb
Host smart-72958756-0229-4f95-90ec-cc2d4d64c5b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150320195 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.1150320195
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.4170991230
Short name T25
Test name
Test status
Simulation time 7640701674 ps
CPU time 6.65 seconds
Started May 09 02:04:26 PM PDT 24
Finished May 09 02:04:34 PM PDT 24
Peak memory 215296 kb
Host smart-66e2b0ee-7861-4af1-8023-34ae613f4ed7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170991230 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.4170991230
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.3056183986
Short name T134
Test name
Test status
Simulation time 504369086 ps
CPU time 0.77 seconds
Started May 09 02:04:25 PM PDT 24
Finished May 09 02:04:27 PM PDT 24
Peak memory 183604 kb
Host smart-c2375d0b-1635-4801-99e8-33a4e0a4debf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056183986 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.3056183986
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.4055468915
Short name T216
Test name
Test status
Simulation time 7287403325 ps
CPU time 3.39 seconds
Started May 09 02:04:25 PM PDT 24
Finished May 09 02:04:30 PM PDT 24
Peak memory 194416 kb
Host smart-5f840b0c-e1db-453f-9e6f-2136f755d1f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055468915 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_a
ll.4055468915
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_jump.3936107094
Short name T272
Test name
Test status
Simulation time 489595195 ps
CPU time 1.16 seconds
Started May 09 02:06:02 PM PDT 24
Finished May 09 02:06:05 PM PDT 24
Peak memory 183548 kb
Host smart-62b54ab1-3ea4-421f-8273-9a77940cd280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936107094 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.3936107094
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.698986014
Short name T139
Test name
Test status
Simulation time 11744298279 ps
CPU time 19.9 seconds
Started May 09 02:06:03 PM PDT 24
Finished May 09 02:06:25 PM PDT 24
Peak memory 191808 kb
Host smart-4e2a9e36-bd7e-4a5a-a7f0-3c0636c0a1fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698986014 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.698986014
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.17941480
Short name T13
Test name
Test status
Simulation time 506876293 ps
CPU time 0.61 seconds
Started May 09 02:06:03 PM PDT 24
Finished May 09 02:06:05 PM PDT 24
Peak memory 183564 kb
Host smart-a62b9579-a7ad-4f91-a2b2-a217547fa87d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17941480 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.17941480
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.344344546
Short name T275
Test name
Test status
Simulation time 41074698639 ps
CPU time 66.12 seconds
Started May 09 02:06:04 PM PDT 24
Finished May 09 02:07:12 PM PDT 24
Peak memory 193980 kb
Host smart-2c36b074-1d50-48a0-91c2-d8671e3a4a10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344344546 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_a
ll.344344546
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.4159160220
Short name T201
Test name
Test status
Simulation time 130273545658 ps
CPU time 559.54 seconds
Started May 09 02:06:03 PM PDT 24
Finished May 09 02:15:25 PM PDT 24
Peak memory 199020 kb
Host smart-1168e68b-e284-47b3-b27a-f5ae07703378
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159160220 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.4159160220
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.aon_timer_jump.2793123542
Short name T6
Test name
Test status
Simulation time 355348087 ps
CPU time 0.76 seconds
Started May 09 02:06:04 PM PDT 24
Finished May 09 02:06:07 PM PDT 24
Peak memory 183516 kb
Host smart-fd4d9743-a361-494f-ab7e-453702b21ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793123542 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.2793123542
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.3148729886
Short name T256
Test name
Test status
Simulation time 24103001296 ps
CPU time 34.1 seconds
Started May 09 02:06:03 PM PDT 24
Finished May 09 02:06:39 PM PDT 24
Peak memory 191804 kb
Host smart-f4249cbc-7370-4dac-ab4b-f85c85aa29e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148729886 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.3148729886
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.1429087925
Short name T53
Test name
Test status
Simulation time 518854575 ps
CPU time 0.94 seconds
Started May 09 02:06:06 PM PDT 24
Finished May 09 02:06:08 PM PDT 24
Peak memory 183580 kb
Host smart-c7c28709-3a6c-4a05-9a2b-a2c832e7093a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429087925 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.1429087925
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.1125799058
Short name T135
Test name
Test status
Simulation time 64078156367 ps
CPU time 29.86 seconds
Started May 09 02:06:01 PM PDT 24
Finished May 09 02:06:32 PM PDT 24
Peak memory 194376 kb
Host smart-e04ae68b-47a4-46ea-a805-79ed704fa456
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125799058 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_
all.1125799058
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.1665814471
Short name T33
Test name
Test status
Simulation time 176054621855 ps
CPU time 382.31 seconds
Started May 09 02:06:03 PM PDT 24
Finished May 09 02:12:27 PM PDT 24
Peak memory 198560 kb
Host smart-7b6a5a6f-d101-47e4-b0ed-4215464650af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665814471 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.1665814471
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.aon_timer_jump.1914001665
Short name T173
Test name
Test status
Simulation time 534010981 ps
CPU time 0.83 seconds
Started May 09 02:06:03 PM PDT 24
Finished May 09 02:06:05 PM PDT 24
Peak memory 183500 kb
Host smart-d483f486-f005-49ab-bdef-b991004e254d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914001665 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.1914001665
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.2737402099
Short name T181
Test name
Test status
Simulation time 34445800815 ps
CPU time 12.65 seconds
Started May 09 02:06:05 PM PDT 24
Finished May 09 02:06:20 PM PDT 24
Peak memory 191840 kb
Host smart-cc67aea6-eca6-4708-8f7a-021c8386967b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737402099 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.2737402099
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.2999105177
Short name T212
Test name
Test status
Simulation time 509404577 ps
CPU time 1.3 seconds
Started May 09 02:06:05 PM PDT 24
Finished May 09 02:06:08 PM PDT 24
Peak memory 183560 kb
Host smart-0f549625-dec0-4c5b-96b2-12eb30e92ba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999105177 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.2999105177
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.4143880027
Short name T200
Test name
Test status
Simulation time 55437194373 ps
CPU time 84.41 seconds
Started May 09 02:06:04 PM PDT 24
Finished May 09 02:07:30 PM PDT 24
Peak memory 183648 kb
Host smart-f2a775cc-8cdb-40b5-9d1e-a07bc4d01f78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143880027 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_
all.4143880027
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.2167819129
Short name T88
Test name
Test status
Simulation time 249838129016 ps
CPU time 555.96 seconds
Started May 09 02:06:03 PM PDT 24
Finished May 09 02:15:21 PM PDT 24
Peak memory 198904 kb
Host smart-375a8e54-aa2a-4dac-8c0b-41bac3774cdb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167819129 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.2167819129
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.aon_timer_jump.432455878
Short name T174
Test name
Test status
Simulation time 552570423 ps
CPU time 0.73 seconds
Started May 09 02:06:04 PM PDT 24
Finished May 09 02:06:06 PM PDT 24
Peak memory 183564 kb
Host smart-632ea4df-a5bb-4338-95eb-5122a8e206f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432455878 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.432455878
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.1686610469
Short name T185
Test name
Test status
Simulation time 39905343750 ps
CPU time 15.58 seconds
Started May 09 02:06:04 PM PDT 24
Finished May 09 02:06:22 PM PDT 24
Peak memory 183536 kb
Host smart-99ef60f4-b176-41f0-99dc-285258dca460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686610469 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.1686610469
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.1808350970
Short name T186
Test name
Test status
Simulation time 422032332 ps
CPU time 1.15 seconds
Started May 09 02:06:05 PM PDT 24
Finished May 09 02:06:08 PM PDT 24
Peak memory 183476 kb
Host smart-d22f6bb4-53ce-4f27-8420-31ffce99913d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808350970 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.1808350970
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.2339979669
Short name T17
Test name
Test status
Simulation time 144437431199 ps
CPU time 90.77 seconds
Started May 09 02:06:14 PM PDT 24
Finished May 09 02:07:45 PM PDT 24
Peak memory 195096 kb
Host smart-ad9a4d51-341a-446f-aaa1-b65b564ccc33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339979669 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_
all.2339979669
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.699809721
Short name T46
Test name
Test status
Simulation time 37112890864 ps
CPU time 310.34 seconds
Started May 09 02:06:05 PM PDT 24
Finished May 09 02:11:17 PM PDT 24
Peak memory 198424 kb
Host smart-f2a58b5e-2ce9-4ab3-a625-9da26b7e4d0c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699809721 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.699809721
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.aon_timer_jump.3229071480
Short name T219
Test name
Test status
Simulation time 353496870 ps
CPU time 1.03 seconds
Started May 09 02:06:15 PM PDT 24
Finished May 09 02:06:17 PM PDT 24
Peak memory 183552 kb
Host smart-83caae60-0050-4d07-866f-5c65d9c9d330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229071480 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.3229071480
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.15527625
Short name T208
Test name
Test status
Simulation time 16523285646 ps
CPU time 26.21 seconds
Started May 09 02:06:13 PM PDT 24
Finished May 09 02:06:40 PM PDT 24
Peak memory 183672 kb
Host smart-dd5e69d0-d02c-479b-9981-723ca6c7a94d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15527625 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.15527625
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.2350468301
Short name T29
Test name
Test status
Simulation time 334893315 ps
CPU time 1.05 seconds
Started May 09 02:06:12 PM PDT 24
Finished May 09 02:06:15 PM PDT 24
Peak memory 183580 kb
Host smart-dc38926e-d734-4db3-bc90-801ce5ae7ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350468301 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.2350468301
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.240800400
Short name T105
Test name
Test status
Simulation time 347020204677 ps
CPU time 62.33 seconds
Started May 09 02:06:13 PM PDT 24
Finished May 09 02:07:17 PM PDT 24
Peak memory 194960 kb
Host smart-660f3414-fcc4-4f9a-8000-8d5071bd7523
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240800400 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_a
ll.240800400
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.3851275469
Short name T27
Test name
Test status
Simulation time 177012062328 ps
CPU time 453.14 seconds
Started May 09 02:06:14 PM PDT 24
Finished May 09 02:13:48 PM PDT 24
Peak memory 198584 kb
Host smart-a3e96df0-f546-4277-bdc5-81d62167c3fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851275469 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.3851275469
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.aon_timer_jump.13480145
Short name T222
Test name
Test status
Simulation time 448358416 ps
CPU time 0.68 seconds
Started May 09 02:06:14 PM PDT 24
Finished May 09 02:06:16 PM PDT 24
Peak memory 183548 kb
Host smart-f527fdbc-4bfa-4d4f-8954-ef260adb9b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13480145 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.13480145
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.3441813642
Short name T108
Test name
Test status
Simulation time 36889300259 ps
CPU time 58.89 seconds
Started May 09 02:06:13 PM PDT 24
Finished May 09 02:07:13 PM PDT 24
Peak memory 191784 kb
Host smart-78c291c3-7cb1-40d5-88c7-67e7a19ce7c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441813642 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.3441813642
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.58082605
Short name T90
Test name
Test status
Simulation time 711548893 ps
CPU time 0.58 seconds
Started May 09 02:06:12 PM PDT 24
Finished May 09 02:06:14 PM PDT 24
Peak memory 183520 kb
Host smart-ceb5689e-caa1-415c-8851-ca809886bbb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58082605 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.58082605
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.4267689545
Short name T103
Test name
Test status
Simulation time 91798648085 ps
CPU time 68.32 seconds
Started May 09 02:06:14 PM PDT 24
Finished May 09 02:07:24 PM PDT 24
Peak memory 195424 kb
Host smart-26f50fc3-4a1e-48ac-b8ef-89d13a1315ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267689545 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_
all.4267689545
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.3743204412
Short name T87
Test name
Test status
Simulation time 61616608279 ps
CPU time 440.23 seconds
Started May 09 02:06:14 PM PDT 24
Finished May 09 02:13:35 PM PDT 24
Peak memory 198536 kb
Host smart-5edf01b0-2d20-4486-b50c-1b1166a2afee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743204412 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.3743204412
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.aon_timer_jump.3596395540
Short name T91
Test name
Test status
Simulation time 571725372 ps
CPU time 1.44 seconds
Started May 09 02:06:14 PM PDT 24
Finished May 09 02:06:16 PM PDT 24
Peak memory 183552 kb
Host smart-4be5b5bc-49a6-4a66-acba-e5ba14d19676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596395540 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.3596395540
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.1998962601
Short name T267
Test name
Test status
Simulation time 53618350670 ps
CPU time 40.89 seconds
Started May 09 02:06:12 PM PDT 24
Finished May 09 02:06:55 PM PDT 24
Peak memory 183636 kb
Host smart-0bc533d7-4bfa-49ad-b8d3-e7b3b0a6865a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998962601 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.1998962601
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.3675062363
Short name T165
Test name
Test status
Simulation time 599159786 ps
CPU time 0.74 seconds
Started May 09 02:06:13 PM PDT 24
Finished May 09 02:06:15 PM PDT 24
Peak memory 183600 kb
Host smart-6cb82f53-47fa-4483-ade6-371ffbbd39a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675062363 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.3675062363
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.1140229445
Short name T171
Test name
Test status
Simulation time 112374046048 ps
CPU time 14.8 seconds
Started May 09 02:06:24 PM PDT 24
Finished May 09 02:06:40 PM PDT 24
Peak memory 183648 kb
Host smart-3e88829d-25d2-418a-b9fb-4fd1475b05b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140229445 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_
all.1140229445
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.2035445951
Short name T179
Test name
Test status
Simulation time 12806391085 ps
CPU time 90.93 seconds
Started May 09 02:06:22 PM PDT 24
Finished May 09 02:07:54 PM PDT 24
Peak memory 198572 kb
Host smart-1fefaf03-9592-4afd-8cc2-c6b4a4eb600a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035445951 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.2035445951
Directory /workspace/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.aon_timer_jump.1834427351
Short name T192
Test name
Test status
Simulation time 445577721 ps
CPU time 0.67 seconds
Started May 09 02:06:23 PM PDT 24
Finished May 09 02:06:26 PM PDT 24
Peak memory 183516 kb
Host smart-97023e9f-cf81-4abf-8c1d-b4f9fd57ac2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834427351 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.1834427351
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.3144214904
Short name T98
Test name
Test status
Simulation time 2168076571 ps
CPU time 2.28 seconds
Started May 09 02:06:24 PM PDT 24
Finished May 09 02:06:28 PM PDT 24
Peak memory 183688 kb
Host smart-7064e4ec-7b90-4e89-9108-1ad71ead538e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144214904 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.3144214904
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.2630817772
Short name T245
Test name
Test status
Simulation time 405804290 ps
CPU time 0.71 seconds
Started May 09 02:06:25 PM PDT 24
Finished May 09 02:06:27 PM PDT 24
Peak memory 183624 kb
Host smart-8b16a8e9-a431-45b1-869e-68e0d633f718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630817772 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.2630817772
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.3484129060
Short name T131
Test name
Test status
Simulation time 69640547768 ps
CPU time 49.54 seconds
Started May 09 02:06:24 PM PDT 24
Finished May 09 02:07:15 PM PDT 24
Peak memory 194400 kb
Host smart-e4bd2e5b-a364-45cb-b101-d75e7b780e25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484129060 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_
all.3484129060
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.2930677168
Short name T164
Test name
Test status
Simulation time 294284730485 ps
CPU time 178.84 seconds
Started May 09 02:06:25 PM PDT 24
Finished May 09 02:09:25 PM PDT 24
Peak memory 198536 kb
Host smart-8cce3880-bb69-451e-80a9-2894f6fbd97c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930677168 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.2930677168
Directory /workspace/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_jump.3389345528
Short name T1
Test name
Test status
Simulation time 584029902 ps
CPU time 1 seconds
Started May 09 02:06:23 PM PDT 24
Finished May 09 02:06:25 PM PDT 24
Peak memory 183552 kb
Host smart-2c7aef8c-bc70-4820-a831-830b97d44391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389345528 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.3389345528
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.1750793433
Short name T152
Test name
Test status
Simulation time 61025305900 ps
CPU time 26.52 seconds
Started May 09 02:06:24 PM PDT 24
Finished May 09 02:06:52 PM PDT 24
Peak memory 183552 kb
Host smart-8cc6b984-db96-4d6e-b05f-6641a59336fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750793433 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.1750793433
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.2313067462
Short name T235
Test name
Test status
Simulation time 427203758 ps
CPU time 1.17 seconds
Started May 09 02:06:23 PM PDT 24
Finished May 09 02:06:25 PM PDT 24
Peak memory 183600 kb
Host smart-b820d266-a4ba-475b-b182-247a2b16c845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313067462 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.2313067462
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.1687017085
Short name T184
Test name
Test status
Simulation time 15407876370 ps
CPU time 23.36 seconds
Started May 09 02:06:28 PM PDT 24
Finished May 09 02:06:52 PM PDT 24
Peak memory 183544 kb
Host smart-7d179b7f-2e29-416d-a6d5-20951795623b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687017085 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_
all.1687017085
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.1981179105
Short name T155
Test name
Test status
Simulation time 21111360895 ps
CPU time 191.55 seconds
Started May 09 02:06:24 PM PDT 24
Finished May 09 02:09:37 PM PDT 24
Peak memory 198520 kb
Host smart-9d4fcce0-aa6e-41cf-a5be-a77e65edc285
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981179105 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.1981179105
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.aon_timer_jump.2279010223
Short name T207
Test name
Test status
Simulation time 450810621 ps
CPU time 0.84 seconds
Started May 09 02:06:35 PM PDT 24
Finished May 09 02:06:38 PM PDT 24
Peak memory 183568 kb
Host smart-1c318c63-259c-492f-b8fe-93471052c259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279010223 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.2279010223
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.2592466165
Short name T193
Test name
Test status
Simulation time 12104107260 ps
CPU time 5.42 seconds
Started May 09 02:06:34 PM PDT 24
Finished May 09 02:06:42 PM PDT 24
Peak memory 183624 kb
Host smart-02d27e0f-2038-409b-a960-979108ade1be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592466165 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.2592466165
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.988932449
Short name T260
Test name
Test status
Simulation time 630140639 ps
CPU time 0.73 seconds
Started May 09 02:06:24 PM PDT 24
Finished May 09 02:06:27 PM PDT 24
Peak memory 183556 kb
Host smart-a154b41d-d140-46ec-995f-0583f2e0edf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988932449 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.988932449
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.293444622
Short name T209
Test name
Test status
Simulation time 123273555810 ps
CPU time 42.28 seconds
Started May 09 02:06:35 PM PDT 24
Finished May 09 02:07:20 PM PDT 24
Peak memory 183624 kb
Host smart-18e776fa-93c1-41e4-a9e9-80f74f4a2e35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293444622 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_a
ll.293444622
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.3936668410
Short name T234
Test name
Test status
Simulation time 43115935742 ps
CPU time 368.28 seconds
Started May 09 02:06:36 PM PDT 24
Finished May 09 02:12:48 PM PDT 24
Peak memory 198784 kb
Host smart-985247a2-5d3b-4ca9-819c-b555083ad28d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936668410 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.3936668410
Directory /workspace/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.aon_timer_jump.918785779
Short name T273
Test name
Test status
Simulation time 499280027 ps
CPU time 1.21 seconds
Started May 09 02:04:26 PM PDT 24
Finished May 09 02:04:29 PM PDT 24
Peak memory 183592 kb
Host smart-f1ac3cef-d57a-4603-bf1f-ca5713a4487e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918785779 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.918785779
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.916584725
Short name T127
Test name
Test status
Simulation time 41920698059 ps
CPU time 60.03 seconds
Started May 09 02:04:24 PM PDT 24
Finished May 09 02:05:25 PM PDT 24
Peak memory 183620 kb
Host smart-54a58a0a-e1e1-48eb-b95b-02a3eaaa5b1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916584725 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.916584725
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.2516915875
Short name T232
Test name
Test status
Simulation time 424420425 ps
CPU time 0.91 seconds
Started May 09 02:04:25 PM PDT 24
Finished May 09 02:04:27 PM PDT 24
Peak memory 183560 kb
Host smart-44ddd1a9-2f5b-49c5-82d5-2b5539481142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516915875 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.2516915875
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.337660989
Short name T229
Test name
Test status
Simulation time 377409630419 ps
CPU time 596.73 seconds
Started May 09 02:04:24 PM PDT 24
Finished May 09 02:14:22 PM PDT 24
Peak memory 195212 kb
Host smart-15007f7b-1c70-4a70-8df8-3d4d97450fca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337660989 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_al
l.337660989
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.3744634415
Short name T82
Test name
Test status
Simulation time 108619576383 ps
CPU time 321.99 seconds
Started May 09 02:04:26 PM PDT 24
Finished May 09 02:09:49 PM PDT 24
Peak memory 198468 kb
Host smart-6cce5cfb-cb6e-4b14-aec2-dffe8b56011a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744634415 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.3744634415
Directory /workspace/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.aon_timer_jump.2810743928
Short name T10
Test name
Test status
Simulation time 563454552 ps
CPU time 1.1 seconds
Started May 09 02:04:26 PM PDT 24
Finished May 09 02:04:28 PM PDT 24
Peak memory 183592 kb
Host smart-fac639b0-6a7f-40f1-b28e-c2d02c240dd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810743928 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.2810743928
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.3483555626
Short name T147
Test name
Test status
Simulation time 4888909082 ps
CPU time 1.38 seconds
Started May 09 02:04:26 PM PDT 24
Finished May 09 02:04:28 PM PDT 24
Peak memory 183616 kb
Host smart-8601d29b-7e62-4be8-9ba2-27f06c012498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483555626 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.3483555626
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.2581199374
Short name T122
Test name
Test status
Simulation time 490757791 ps
CPU time 0.75 seconds
Started May 09 02:04:25 PM PDT 24
Finished May 09 02:04:27 PM PDT 24
Peak memory 183544 kb
Host smart-fc41dea1-0535-4a5f-9613-6f639f1a46a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581199374 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.2581199374
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.2352706232
Short name T167
Test name
Test status
Simulation time 21981280886 ps
CPU time 10.34 seconds
Started May 09 02:04:38 PM PDT 24
Finished May 09 02:04:50 PM PDT 24
Peak memory 193792 kb
Host smart-64acede0-d7b2-4b6a-9b27-24c33b6ab7a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352706232 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_a
ll.2352706232
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_jump.3540638715
Short name T169
Test name
Test status
Simulation time 448504193 ps
CPU time 1.33 seconds
Started May 09 02:04:36 PM PDT 24
Finished May 09 02:04:39 PM PDT 24
Peak memory 183560 kb
Host smart-0d05e413-8836-4d75-8827-8ec359b742d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540638715 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.3540638715
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.3075449055
Short name T237
Test name
Test status
Simulation time 14638753084 ps
CPU time 5.85 seconds
Started May 09 02:04:37 PM PDT 24
Finished May 09 02:04:44 PM PDT 24
Peak memory 183624 kb
Host smart-14e80df8-1301-4b99-8e92-44cae73fd5b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075449055 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.3075449055
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.925846769
Short name T276
Test name
Test status
Simulation time 417510685 ps
CPU time 0.82 seconds
Started May 09 02:04:38 PM PDT 24
Finished May 09 02:04:40 PM PDT 24
Peak memory 183600 kb
Host smart-48ffadd9-f26c-455f-b698-0f74b46e0128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925846769 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.925846769
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.1408567211
Short name T156
Test name
Test status
Simulation time 58080849015 ps
CPU time 42.29 seconds
Started May 09 02:04:37 PM PDT 24
Finished May 09 02:05:21 PM PDT 24
Peak memory 183612 kb
Host smart-d966deaa-0678-4345-9da7-44704e0ca67e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408567211 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_a
ll.1408567211
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.361348810
Short name T252
Test name
Test status
Simulation time 160006589148 ps
CPU time 414.39 seconds
Started May 09 02:04:38 PM PDT 24
Finished May 09 02:11:34 PM PDT 24
Peak memory 198488 kb
Host smart-7a2fd86c-5a6e-4409-a45b-619310ee788d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361348810 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.361348810
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.aon_timer_jump.2534802365
Short name T215
Test name
Test status
Simulation time 474127225 ps
CPU time 1.22 seconds
Started May 09 02:04:39 PM PDT 24
Finished May 09 02:04:41 PM PDT 24
Peak memory 183548 kb
Host smart-daf0e63a-e21d-4da3-ab85-dbec5f795166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534802365 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.2534802365
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.2658446940
Short name T199
Test name
Test status
Simulation time 19566685580 ps
CPU time 27.22 seconds
Started May 09 02:04:37 PM PDT 24
Finished May 09 02:05:06 PM PDT 24
Peak memory 191844 kb
Host smart-c3d4e632-20cf-4047-b327-beedd3c69b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658446940 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.2658446940
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.1570124247
Short name T141
Test name
Test status
Simulation time 433468304 ps
CPU time 1.21 seconds
Started May 09 02:04:37 PM PDT 24
Finished May 09 02:04:39 PM PDT 24
Peak memory 183552 kb
Host smart-f3718b1d-06ec-49f4-bfb7-98d508bb09a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570124247 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.1570124247
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.3981331227
Short name T241
Test name
Test status
Simulation time 5996184190 ps
CPU time 2.99 seconds
Started May 09 02:04:37 PM PDT 24
Finished May 09 02:04:41 PM PDT 24
Peak memory 194112 kb
Host smart-a2c77aee-14bd-4ebf-9456-72ca535a8390
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981331227 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_a
ll.3981331227
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.2308676122
Short name T45
Test name
Test status
Simulation time 44080734477 ps
CPU time 476.78 seconds
Started May 09 02:04:38 PM PDT 24
Finished May 09 02:12:36 PM PDT 24
Peak memory 198528 kb
Host smart-0eca671f-7820-4710-b8f7-aad93db4a9eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308676122 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.2308676122
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.aon_timer_jump.3924159242
Short name T78
Test name
Test status
Simulation time 576122109 ps
CPU time 0.68 seconds
Started May 09 02:04:37 PM PDT 24
Finished May 09 02:04:39 PM PDT 24
Peak memory 183572 kb
Host smart-62cf12d7-4ded-4c04-bda3-63a48051d59f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924159242 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.3924159242
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.2864839961
Short name T148
Test name
Test status
Simulation time 12310101464 ps
CPU time 17.97 seconds
Started May 09 02:04:36 PM PDT 24
Finished May 09 02:04:56 PM PDT 24
Peak memory 183588 kb
Host smart-9cc01c88-6a3a-4764-b5db-237cde913a3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864839961 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.2864839961
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.3517935070
Short name T93
Test name
Test status
Simulation time 542790321 ps
CPU time 1.25 seconds
Started May 09 02:04:36 PM PDT 24
Finished May 09 02:04:39 PM PDT 24
Peak memory 183596 kb
Host smart-02ff8c8c-1bbe-4386-9ec0-f0b949989ed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517935070 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.3517935070
Directory /workspace/9.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.775468283
Short name T242
Test name
Test status
Simulation time 442846519321 ps
CPU time 665.81 seconds
Started May 09 02:04:48 PM PDT 24
Finished May 09 02:15:55 PM PDT 24
Peak memory 193992 kb
Host smart-910f5ed4-985d-401a-8564-95872aa3d479
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775468283 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_al
l.775468283
Directory /workspace/9.aon_timer_stress_all/latest
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