Unified Coverage Report :: Group :: aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
24.86	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv

---

Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	173	130	43	24.86

Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
bark_thold_cp	34	32	2	5.88	100	1	1	0
bite_thold_cp	34	32	2	5.88	100	1	1	0
pause_in_sleep_cp	2	1	1	50.00	100	1	1	2
prescale_cp	34	1	33	97.06	100	1	1	0
wdog_regwen_cp	2	0	2	100.00	100	1	1	2
wkup_cause_cp	1	0	1	100.00	100	1	1	0
wkup_thold_cp	66	64	2	3.03	100	1	1	0

Summary for Variable bark_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	32	2	5.88

User Defined Bins for bark_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bark_max	0	1	1
bark[1]	0	1	1
bark[2]	0	1	1
bark[3]	0	1	1
bark[4]	0	1	1
bark[5]	0	1	1
bark[6]	0	1	1
bark[7]	0	1	1
bark[8]	0	1	1
bark[9]	0	1	1
bark[10]	0	1	1
bark[11]	0	1	1
bark[12]	0	1	1
bark[13]	0	1	1
bark[14]	0	1	1
bark[15]	0	1	1
bark[16]	0	1	1
bark[17]	0	1	1
bark[18]	0	1	1
bark[19]	0	1	1
bark[20]	0	1	1
bark[21]	0	1	1
bark[22]	0	1	1
bark[23]	0	1	1
bark[24]	0	1	1
bark[25]	0	1	1
bark[26]	0	1	1
bark[27]	0	1	1
bark[28]	0	1	1
bark[29]	0	1	1
bark[30]	0	1	1
bark[31]	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bark[0]	53325	1		T1	1506		T2	12		T3	265
bark_0	4860	1		T1	86		T2	7		T3	7

---

Summary for Variable bite_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	32	2	5.88

User Defined Bins for bite_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bite_max	0	1	1
bite[1]	0	1	1
bite[2]	0	1	1
bite[3]	0	1	1
bite[4]	0	1	1
bite[5]	0	1	1
bite[6]	0	1	1
bite[7]	0	1	1
bite[8]	0	1	1
bite[9]	0	1	1
bite[10]	0	1	1
bite[11]	0	1	1
bite[12]	0	1	1
bite[13]	0	1	1
bite[14]	0	1	1
bite[15]	0	1	1
bite[16]	0	1	1
bite[17]	0	1	1
bite[18]	0	1	1
bite[19]	0	1	1
bite[20]	0	1	1
bite[21]	0	1	1
bite[22]	0	1	1
bite[23]	0	1	1
bite[24]	0	1	1
bite[25]	0	1	1
bite[26]	0	1	1
bite[27]	0	1	1
bite[28]	0	1	1
bite[29]	0	1	1
bite[30]	0	1	1
bite[31]	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bite[0]	52847	1		T1	1497		T2	11		T3	264
bite_0	5338	1		T1	95		T2	8		T3	8

---

Summary for Variable pause_in_sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for pause_in_sleep_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
[auto[1]]	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	58185	1		T1	1592		T2	19		T3	272

---

Summary for Variable prescale_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for prescale_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prescale_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
prescale[0]	1329	1		T10	19		T22	19		T33	40
prescale[1]	1329	1		T15	9		T17	24		T22	23
prescale[2]	1029	1		T13	49		T16	37		T32	19
prescale[3]	747	1		T1	20		T10	19		T33	23
prescale[4]	1065	1		T10	19		T17	56		T95	9
prescale[5]	703	1		T1	44		T96	9		T97	55
prescale[6]	662	1		T1	9		T3	19		T28	37
prescale[7]	1050	1		T10	82		T17	20		T22	19
prescale[8]	905	1		T12	23		T16	76		T28	23
prescale[9]	1254	1		T10	19		T17	101		T98	14
prescale[10]	1052	1		T13	20		T17	19		T99	19
prescale[11]	854	1		T1	60		T98	19		T32	23
prescale[12]	903	1		T1	133		T34	65		T37	37
prescale[13]	991	1		T4	9		T10	19		T16	24
prescale[14]	894	1		T1	97		T12	58		T34	83
prescale[15]	985	1		T1	28		T17	196		T100	44
prescale[16]	866	1		T1	40		T32	37		T33	87
prescale[17]	822	1		T2	9		T32	61		T101	19
prescale[18]	1157	1		T3	19		T17	11		T33	40
prescale[19]	670	1		T1	2		T28	9		T32	2
prescale[20]	380	1		T13	2		T23	23		T33	45
prescale[21]	798	1		T3	19		T33	47		T101	19
prescale[22]	956	1		T3	40		T13	2		T17	38
prescale[23]	908	1		T23	9		T32	2		T99	52
prescale[24]	965	1		T3	28		T33	2		T36	108
prescale[25]	1001	1		T3	28		T17	128		T22	19
prescale[26]	744	1		T1	184		T17	9		T33	42
prescale[27]	780	1		T13	2		T22	42		T99	19
prescale[28]	809	1		T3	23		T10	23		T33	2
prescale[29]	1291	1		T1	25		T3	44		T12	27
prescale[30]	1129	1		T17	159		T22	61		T28	37
prescale[31]	1192	1		T1	184		T10	19		T32	4
prescale_0	27965	1		T1	766		T2	10		T3	52

---

Summary for Variable wdog_regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wdog_regwen_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	45494	1		T1	1395		T2	19		T3	251
auto[1]	12691	1		T1	197		T3	21		T6	12

---

Summary for Variable wkup_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for wkup_cause_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup_cause_cleared	58185	1		T1	1592		T2	19		T3	272

---

Summary for Variable wkup_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	66	64	2	3.03

User Defined Bins for wkup_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
wkup_max	0	1	1
wkup[1]	0	1	1
wkup[2]	0	1	1
wkup[3]	0	1	1
wkup[4]	0	1	1
wkup[5]	0	1	1
wkup[6]	0	1	1
wkup[7]	0	1	1
wkup[8]	0	1	1
wkup[9]	0	1	1
wkup[10]	0	1	1
wkup[11]	0	1	1
wkup[12]	0	1	1
wkup[13]	0	1	1
wkup[14]	0	1	1
wkup[15]	0	1	1
wkup[16]	0	1	1
wkup[17]	0	1	1
wkup[18]	0	1	1
wkup[19]	0	1	1
wkup[20]	0	1	1
wkup[21]	0	1	1
wkup[22]	0	1	1
wkup[23]	0	1	1
wkup[24]	0	1	1
wkup[25]	0	1	1
wkup[26]	0	1	1
wkup[27]	0	1	1
wkup[28]	0	1	1
wkup[29]	0	1	1
wkup[30]	0	1	1
wkup[31]	0	1	1
wkup[32]	0	1	1
wkup[33]	0	1	1
wkup[34]	0	1	1
wkup[35]	0	1	1
wkup[36]	0	1	1
wkup[37]	0	1	1
wkup[38]	0	1	1
wkup[39]	0	1	1
wkup[40]	0	1	1
wkup[41]	0	1	1
wkup[42]	0	1	1
wkup[43]	0	1	1
wkup[44]	0	1	1
wkup[45]	0	1	1
wkup[46]	0	1	1
wkup[47]	0	1	1
wkup[48]	0	1	1
wkup[49]	0	1	1
wkup[50]	0	1	1
wkup[51]	0	1	1
wkup[52]	0	1	1
wkup[53]	0	1	1
wkup[54]	0	1	1
wkup[55]	0	1	1
wkup[56]	0	1	1
wkup[57]	0	1	1
wkup[58]	0	1	1
wkup[59]	0	1	1
wkup[60]	0	1	1
wkup[61]	0	1	1
wkup[62]	0	1	1
wkup[63]	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup[0]	54363	1		T1	1524		T2	14		T3	267
wkup_0	3822	1		T1	68		T2	5		T3	5