Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
92.98 99.25 93.67 100.00 98.40 99.51 67.06


Total test records in report: 421
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T27 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.3191135407 May 12 04:07:42 PM PDT 24 May 12 04:07:49 PM PDT 24 4161859176 ps
T29 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.390335293 May 12 04:07:42 PM PDT 24 May 12 04:07:44 PM PDT 24 559996255 ps
T109 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.2873257156 May 12 04:07:39 PM PDT 24 May 12 04:07:41 PM PDT 24 517628104 ps
T286 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.675963911 May 12 04:07:58 PM PDT 24 May 12 04:08:00 PM PDT 24 506269639 ps
T67 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.1201387944 May 12 04:07:28 PM PDT 24 May 12 04:07:29 PM PDT 24 1557241025 ps
T287 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.688860933 May 12 04:07:56 PM PDT 24 May 12 04:07:57 PM PDT 24 434919388 ps
T288 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.721444047 May 12 04:07:23 PM PDT 24 May 12 04:07:25 PM PDT 24 649374719 ps
T289 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.1660051050 May 12 04:07:55 PM PDT 24 May 12 04:07:57 PM PDT 24 457557872 ps
T110 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.3051512725 May 12 04:07:09 PM PDT 24 May 12 04:07:10 PM PDT 24 451043909 ps
T290 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.2064023272 May 12 04:07:54 PM PDT 24 May 12 04:07:55 PM PDT 24 615267827 ps
T291 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.1453198427 May 12 04:07:57 PM PDT 24 May 12 04:07:58 PM PDT 24 289424660 ps
T30 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.2985158735 May 12 04:07:18 PM PDT 24 May 12 04:07:23 PM PDT 24 8157749733 ps
T292 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.2750198972 May 12 04:07:58 PM PDT 24 May 12 04:08:00 PM PDT 24 343633601 ps
T53 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.1015207496 May 12 04:07:12 PM PDT 24 May 12 04:07:34 PM PDT 24 13697806091 ps
T31 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.813355204 May 12 04:07:35 PM PDT 24 May 12 04:07:38 PM PDT 24 4399625987 ps
T293 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.2237465627 May 12 04:07:54 PM PDT 24 May 12 04:07:55 PM PDT 24 295350926 ps
T294 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.1129910126 May 12 04:07:56 PM PDT 24 May 12 04:07:58 PM PDT 24 296885734 ps
T295 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.1145646306 May 12 04:07:08 PM PDT 24 May 12 04:07:10 PM PDT 24 602913209 ps
T54 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.1795679043 May 12 04:07:17 PM PDT 24 May 12 04:07:19 PM PDT 24 476987534 ps
T296 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.3763420869 May 12 04:07:21 PM PDT 24 May 12 04:07:23 PM PDT 24 465003957 ps
T107 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.3117857625 May 12 04:07:01 PM PDT 24 May 12 04:07:03 PM PDT 24 4584665254 ps
T297 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.607111328 May 12 04:07:50 PM PDT 24 May 12 04:07:52 PM PDT 24 495973435 ps
T55 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.337742588 May 12 04:07:06 PM PDT 24 May 12 04:07:07 PM PDT 24 479006125 ps
T102 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.623616294 May 12 04:07:49 PM PDT 24 May 12 04:07:58 PM PDT 24 4442334939 ps
T68 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.3848362673 May 12 04:07:26 PM PDT 24 May 12 04:07:27 PM PDT 24 364544423 ps
T298 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.316057154 May 12 04:07:20 PM PDT 24 May 12 04:07:22 PM PDT 24 311994173 ps
T69 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.4294608429 May 12 04:07:26 PM PDT 24 May 12 04:07:27 PM PDT 24 2313651049 ps
T103 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.3219248190 May 12 04:07:35 PM PDT 24 May 12 04:07:51 PM PDT 24 8686893518 ps
T299 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.3142757256 May 12 04:07:51 PM PDT 24 May 12 04:07:52 PM PDT 24 272100455 ps
T300 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.2471488537 May 12 04:07:45 PM PDT 24 May 12 04:07:46 PM PDT 24 557423109 ps
T70 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.928524827 May 12 04:07:12 PM PDT 24 May 12 04:07:14 PM PDT 24 1088392398 ps
T71 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.943431723 May 12 04:07:12 PM PDT 24 May 12 04:07:13 PM PDT 24 415948303 ps
T301 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.3636750840 May 12 04:07:25 PM PDT 24 May 12 04:07:28 PM PDT 24 2064004802 ps
T302 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.4058243567 May 12 04:07:51 PM PDT 24 May 12 04:07:52 PM PDT 24 474683210 ps
T106 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.4176739246 May 12 04:07:46 PM PDT 24 May 12 04:07:51 PM PDT 24 8552472705 ps
T72 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.3435667040 May 12 04:07:06 PM PDT 24 May 12 04:07:07 PM PDT 24 1797906222 ps
T56 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.1887444928 May 12 04:07:55 PM PDT 24 May 12 04:07:57 PM PDT 24 515332548 ps
T303 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.2442844470 May 12 04:07:50 PM PDT 24 May 12 04:07:52 PM PDT 24 584135512 ps
T304 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.3013501823 May 12 04:07:52 PM PDT 24 May 12 04:07:53 PM PDT 24 494676642 ps
T305 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.4170540987 May 12 04:07:54 PM PDT 24 May 12 04:07:56 PM PDT 24 481182576 ps
T306 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.3091153891 May 12 04:07:36 PM PDT 24 May 12 04:07:39 PM PDT 24 439395939 ps
T307 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.918108132 May 12 04:08:01 PM PDT 24 May 12 04:08:03 PM PDT 24 296995057 ps
T308 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.769169403 May 12 04:07:50 PM PDT 24 May 12 04:07:51 PM PDT 24 393400278 ps
T73 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.2453517360 May 12 04:07:34 PM PDT 24 May 12 04:07:38 PM PDT 24 2333652999 ps
T309 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.1047056851 May 12 04:07:52 PM PDT 24 May 12 04:07:54 PM PDT 24 566063284 ps
T310 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.3553887429 May 12 04:07:57 PM PDT 24 May 12 04:07:58 PM PDT 24 320642112 ps
T311 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.725287085 May 12 04:07:31 PM PDT 24 May 12 04:07:33 PM PDT 24 879305879 ps
T312 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.3222053171 May 12 04:07:18 PM PDT 24 May 12 04:07:19 PM PDT 24 359650411 ps
T313 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.2629302207 May 12 04:07:20 PM PDT 24 May 12 04:07:22 PM PDT 24 349122491 ps
T314 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.2892305830 May 12 04:07:43 PM PDT 24 May 12 04:07:44 PM PDT 24 379024035 ps
T108 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.711049052 May 12 04:07:45 PM PDT 24 May 12 04:07:49 PM PDT 24 4486542920 ps
T315 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.493935427 May 12 04:07:55 PM PDT 24 May 12 04:07:56 PM PDT 24 324075565 ps
T316 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.2408515359 May 12 04:07:47 PM PDT 24 May 12 04:07:49 PM PDT 24 385570790 ps
T317 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.2534021258 May 12 04:07:16 PM PDT 24 May 12 04:07:17 PM PDT 24 1262358718 ps
T318 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.690231082 May 12 04:07:01 PM PDT 24 May 12 04:07:04 PM PDT 24 307422146 ps
T319 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.1258613822 May 12 04:07:54 PM PDT 24 May 12 04:07:55 PM PDT 24 355267968 ps
T57 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.31198061 May 12 04:07:49 PM PDT 24 May 12 04:07:50 PM PDT 24 324783722 ps
T74 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.2596590607 May 12 04:07:47 PM PDT 24 May 12 04:07:51 PM PDT 24 1752113904 ps
T320 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.3704252572 May 12 04:07:38 PM PDT 24 May 12 04:07:39 PM PDT 24 537920589 ps
T321 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.3185710865 May 12 04:07:59 PM PDT 24 May 12 04:08:00 PM PDT 24 424557024 ps
T58 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.2279870514 May 12 04:07:34 PM PDT 24 May 12 04:07:35 PM PDT 24 434267048 ps
T322 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.368056013 May 12 04:07:19 PM PDT 24 May 12 04:07:22 PM PDT 24 959629685 ps
T323 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.2835092654 May 12 04:07:47 PM PDT 24 May 12 04:07:50 PM PDT 24 651924891 ps
T59 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.2686892110 May 12 04:07:06 PM PDT 24 May 12 04:07:07 PM PDT 24 417008205 ps
T324 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.356261861 May 12 04:07:45 PM PDT 24 May 12 04:07:47 PM PDT 24 1399937039 ps
T325 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.2858247222 May 12 04:07:31 PM PDT 24 May 12 04:07:33 PM PDT 24 347710350 ps
T326 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.290783567 May 12 04:07:20 PM PDT 24 May 12 04:07:31 PM PDT 24 8684522131 ps
T327 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.3152194852 May 12 04:07:43 PM PDT 24 May 12 04:07:44 PM PDT 24 516748231 ps
T328 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.478472032 May 12 04:07:24 PM PDT 24 May 12 04:07:26 PM PDT 24 549628822 ps
T329 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.1030787972 May 12 04:07:49 PM PDT 24 May 12 04:07:51 PM PDT 24 477093556 ps
T330 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.3280743233 May 12 04:07:16 PM PDT 24 May 12 04:07:17 PM PDT 24 284146022 ps
T331 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.601590531 May 12 04:07:31 PM PDT 24 May 12 04:07:33 PM PDT 24 512682015 ps
T332 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.582816775 May 12 04:07:44 PM PDT 24 May 12 04:07:46 PM PDT 24 393555070 ps
T333 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.1641670525 May 12 04:07:02 PM PDT 24 May 12 04:07:03 PM PDT 24 359920886 ps
T334 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.3413211619 May 12 04:07:09 PM PDT 24 May 12 04:07:17 PM PDT 24 4061227727 ps
T60 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.2617564855 May 12 04:07:19 PM PDT 24 May 12 04:07:26 PM PDT 24 13806070194 ps
T335 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.1729695040 May 12 04:07:22 PM PDT 24 May 12 04:07:30 PM PDT 24 2528730132 ps
T336 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.200269232 May 12 04:07:42 PM PDT 24 May 12 04:07:47 PM PDT 24 2867907504 ps
T337 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.195827664 May 12 04:07:51 PM PDT 24 May 12 04:07:55 PM PDT 24 4218991658 ps
T338 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.3487722099 May 12 04:07:51 PM PDT 24 May 12 04:07:54 PM PDT 24 361160219 ps
T339 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.2231319806 May 12 04:07:38 PM PDT 24 May 12 04:07:40 PM PDT 24 2219010074 ps
T340 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.3826944725 May 12 04:07:42 PM PDT 24 May 12 04:07:44 PM PDT 24 386968314 ps
T341 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.4188147416 May 12 04:07:53 PM PDT 24 May 12 04:07:56 PM PDT 24 2408453646 ps
T342 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.353013204 May 12 04:07:41 PM PDT 24 May 12 04:07:43 PM PDT 24 409663969 ps
T61 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.981086904 May 12 04:07:19 PM PDT 24 May 12 04:07:21 PM PDT 24 345183075 ps
T343 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.2540193971 May 12 04:07:54 PM PDT 24 May 12 04:07:56 PM PDT 24 304298434 ps
T344 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.1820390734 May 12 04:07:25 PM PDT 24 May 12 04:07:30 PM PDT 24 4271307883 ps
T345 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.1118332152 May 12 04:07:42 PM PDT 24 May 12 04:07:44 PM PDT 24 1161611088 ps
T346 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.3420921614 May 12 04:07:44 PM PDT 24 May 12 04:07:47 PM PDT 24 718012425 ps
T347 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.3776816913 May 12 04:07:11 PM PDT 24 May 12 04:07:12 PM PDT 24 323836469 ps
T348 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.4087292601 May 12 04:07:43 PM PDT 24 May 12 04:07:45 PM PDT 24 495262356 ps
T349 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.2641487034 May 12 04:07:44 PM PDT 24 May 12 04:07:45 PM PDT 24 352407776 ps
T350 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.1682288681 May 12 04:07:56 PM PDT 24 May 12 04:07:57 PM PDT 24 264431660 ps
T351 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.3569799712 May 12 04:06:59 PM PDT 24 May 12 04:07:00 PM PDT 24 487491107 ps
T352 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.43779428 May 12 04:07:31 PM PDT 24 May 12 04:07:33 PM PDT 24 389650708 ps
T353 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.3509801073 May 12 04:07:06 PM PDT 24 May 12 04:07:30 PM PDT 24 13918490848 ps
T354 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.1029686993 May 12 04:07:27 PM PDT 24 May 12 04:07:28 PM PDT 24 315393241 ps
T355 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.480799817 May 12 04:07:50 PM PDT 24 May 12 04:07:52 PM PDT 24 488097610 ps
T356 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.3249230821 May 12 04:07:17 PM PDT 24 May 12 04:07:19 PM PDT 24 999161927 ps
T64 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.3285139394 May 12 04:06:59 PM PDT 24 May 12 04:07:01 PM PDT 24 527475292 ps
T357 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.137505864 May 12 04:07:42 PM PDT 24 May 12 04:07:43 PM PDT 24 462503705 ps
T358 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.3238801001 May 12 04:07:42 PM PDT 24 May 12 04:07:44 PM PDT 24 496004777 ps
T359 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.3931436804 May 12 04:07:03 PM PDT 24 May 12 04:07:04 PM PDT 24 309262298 ps
T360 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.1925464341 May 12 04:07:34 PM PDT 24 May 12 04:07:36 PM PDT 24 1920816483 ps
T361 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.3115492858 May 12 04:07:50 PM PDT 24 May 12 04:07:54 PM PDT 24 1536268719 ps
T362 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.3853884003 May 12 04:06:59 PM PDT 24 May 12 04:07:01 PM PDT 24 556565153 ps
T363 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.1217310127 May 12 04:07:43 PM PDT 24 May 12 04:07:46 PM PDT 24 611228061 ps
T364 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.3871805694 May 12 04:07:44 PM PDT 24 May 12 04:07:45 PM PDT 24 417478027 ps
T365 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.1714462007 May 12 04:07:19 PM PDT 24 May 12 04:07:20 PM PDT 24 437796493 ps
T366 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.4252490760 May 12 04:07:11 PM PDT 24 May 12 04:07:12 PM PDT 24 294250941 ps
T66 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.3491006888 May 12 04:07:27 PM PDT 24 May 12 04:07:28 PM PDT 24 428501743 ps
T367 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.832577261 May 12 04:07:44 PM PDT 24 May 12 04:07:58 PM PDT 24 8066750008 ps
T368 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.3765829583 May 12 04:07:00 PM PDT 24 May 12 04:07:01 PM PDT 24 442942845 ps
T369 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.3063569909 May 12 04:07:56 PM PDT 24 May 12 04:07:58 PM PDT 24 472670776 ps
T370 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.4193185851 May 12 04:07:41 PM PDT 24 May 12 04:07:43 PM PDT 24 1054508489 ps
T371 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.3812577917 May 12 04:07:30 PM PDT 24 May 12 04:07:31 PM PDT 24 324456151 ps
T104 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.2384622913 May 12 04:07:02 PM PDT 24 May 12 04:07:08 PM PDT 24 4447844375 ps
T372 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.1480251381 May 12 04:07:13 PM PDT 24 May 12 04:07:15 PM PDT 24 362853519 ps
T373 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.1670917767 May 12 04:07:44 PM PDT 24 May 12 04:07:51 PM PDT 24 3447412580 ps
T374 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.844663581 May 12 04:07:28 PM PDT 24 May 12 04:07:30 PM PDT 24 695107772 ps
T375 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.2211909266 May 12 04:06:59 PM PDT 24 May 12 04:07:09 PM PDT 24 14267244601 ps
T376 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.2763600467 May 12 04:07:48 PM PDT 24 May 12 04:07:53 PM PDT 24 8945228080 ps
T377 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.2965534781 May 12 04:07:49 PM PDT 24 May 12 04:07:51 PM PDT 24 559616101 ps
T378 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.365534806 May 12 04:07:15 PM PDT 24 May 12 04:07:17 PM PDT 24 918998585 ps
T379 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.3467489063 May 12 04:07:57 PM PDT 24 May 12 04:07:58 PM PDT 24 340967028 ps
T380 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.2761436517 May 12 04:07:29 PM PDT 24 May 12 04:07:30 PM PDT 24 653515985 ps
T105 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.638233833 May 12 04:07:14 PM PDT 24 May 12 04:07:21 PM PDT 24 8675857776 ps
T381 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.2643820700 May 12 04:07:02 PM PDT 24 May 12 04:07:04 PM PDT 24 568926309 ps
T382 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.1681848193 May 12 04:07:42 PM PDT 24 May 12 04:07:44 PM PDT 24 457818036 ps
T383 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.1972225891 May 12 04:07:37 PM PDT 24 May 12 04:07:39 PM PDT 24 479218068 ps
T384 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.2455394519 May 12 04:07:55 PM PDT 24 May 12 04:07:56 PM PDT 24 391569877 ps
T385 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.224225433 May 12 04:07:01 PM PDT 24 May 12 04:07:03 PM PDT 24 1086181720 ps
T386 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.1681984755 May 12 04:07:54 PM PDT 24 May 12 04:07:55 PM PDT 24 351462315 ps
T387 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.3540983872 May 12 04:07:18 PM PDT 24 May 12 04:07:21 PM PDT 24 1052872917 ps
T65 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.3593638185 May 12 04:07:20 PM PDT 24 May 12 04:07:26 PM PDT 24 13961268444 ps
T388 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.2868287819 May 12 04:07:30 PM PDT 24 May 12 04:07:32 PM PDT 24 516872833 ps
T389 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.4260433536 May 12 04:07:16 PM PDT 24 May 12 04:07:19 PM PDT 24 2078500286 ps
T390 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.3949753366 May 12 04:07:58 PM PDT 24 May 12 04:07:59 PM PDT 24 431526930 ps
T391 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.115693097 May 12 04:07:01 PM PDT 24 May 12 04:07:03 PM PDT 24 285861250 ps
T392 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.954574582 May 12 04:07:50 PM PDT 24 May 12 04:07:51 PM PDT 24 464296847 ps
T393 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.66618396 May 12 04:06:59 PM PDT 24 May 12 04:07:02 PM PDT 24 914312799 ps
T394 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.3486458479 May 12 04:07:11 PM PDT 24 May 12 04:07:13 PM PDT 24 271503889 ps
T395 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.2335763773 May 12 04:07:58 PM PDT 24 May 12 04:07:59 PM PDT 24 552389396 ps
T62 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.3140157557 May 12 04:07:24 PM PDT 24 May 12 04:07:25 PM PDT 24 419244220 ps
T396 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.1108969192 May 12 04:07:51 PM PDT 24 May 12 04:07:56 PM PDT 24 2443415135 ps
T397 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.3716901690 May 12 04:07:47 PM PDT 24 May 12 04:07:49 PM PDT 24 2677790010 ps
T398 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.1569344260 May 12 04:07:37 PM PDT 24 May 12 04:07:38 PM PDT 24 447934256 ps
T399 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.2583868546 May 12 04:07:35 PM PDT 24 May 12 04:07:37 PM PDT 24 1230715105 ps
T400 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.886424934 May 12 04:07:57 PM PDT 24 May 12 04:07:59 PM PDT 24 352422428 ps
T63 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.2496680680 May 12 04:07:36 PM PDT 24 May 12 04:07:37 PM PDT 24 283440600 ps
T401 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.227126621 May 12 04:07:42 PM PDT 24 May 12 04:07:43 PM PDT 24 308405402 ps
T402 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.387247132 May 12 04:07:54 PM PDT 24 May 12 04:07:55 PM PDT 24 441808714 ps
T403 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.1390916737 May 12 04:07:03 PM PDT 24 May 12 04:07:05 PM PDT 24 430685329 ps
T404 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.1125250323 May 12 04:07:58 PM PDT 24 May 12 04:08:00 PM PDT 24 470771507 ps
T405 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.3219214208 May 12 04:07:36 PM PDT 24 May 12 04:07:45 PM PDT 24 4440805873 ps
T406 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.2575725097 May 12 04:07:15 PM PDT 24 May 12 04:07:16 PM PDT 24 556935837 ps
T407 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.3476355966 May 12 04:07:45 PM PDT 24 May 12 04:07:46 PM PDT 24 418018496 ps
T408 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.2272291709 May 12 04:07:31 PM PDT 24 May 12 04:07:36 PM PDT 24 1466487992 ps
T409 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.3217715872 May 12 04:07:00 PM PDT 24 May 12 04:07:03 PM PDT 24 1114242113 ps
T410 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.1503615673 May 12 04:08:11 PM PDT 24 May 12 04:08:13 PM PDT 24 509735262 ps
T411 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.2989555430 May 12 04:07:03 PM PDT 24 May 12 04:07:04 PM PDT 24 449640257 ps
T412 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.778197254 May 12 04:07:42 PM PDT 24 May 12 04:07:44 PM PDT 24 563112256 ps
T413 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.1363733044 May 12 04:07:15 PM PDT 24 May 12 04:07:17 PM PDT 24 526901562 ps
T414 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.1943422896 May 12 04:07:27 PM PDT 24 May 12 04:07:28 PM PDT 24 404516906 ps
T415 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.2455619986 May 12 04:07:51 PM PDT 24 May 12 04:07:55 PM PDT 24 4112020444 ps
T416 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.3618039116 May 12 04:07:34 PM PDT 24 May 12 04:07:40 PM PDT 24 8663060120 ps
T417 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.3635643432 May 12 04:07:28 PM PDT 24 May 12 04:07:42 PM PDT 24 8048163581 ps
T418 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.2955122888 May 12 04:07:34 PM PDT 24 May 12 04:07:36 PM PDT 24 297366126 ps
T419 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.4229987952 May 12 04:07:56 PM PDT 24 May 12 04:07:57 PM PDT 24 386502427 ps
T420 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.512556174 May 12 04:07:35 PM PDT 24 May 12 04:07:37 PM PDT 24 504835859 ps
T421 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.1753666054 May 12 04:07:22 PM PDT 24 May 12 04:07:25 PM PDT 24 453861590 ps

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.726717157
Short name T1
Test name
Test status
Simulation time 89371162432 ps
CPU time 336.53 seconds
Started May 12 01:58:47 PM PDT 24
Finished May 12 02:04:23 PM PDT 24
Peak memory 198464 kb
Host smart-1307b1c2-35a7-4908-897a-d5641c60cb6e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726717157 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.726717157
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.2824420930
Short name T12
Test name
Test status
Simulation time 277076458023 ps
CPU time 108.86 seconds
Started May 12 01:57:35 PM PDT 24
Finished May 12 01:59:24 PM PDT 24
Peak memory 195332 kb
Host smart-064cbedf-7ba5-4d17-97d6-58146f5b7324
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824420930 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_
all.2824420930
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.3191135407
Short name T27
Test name
Test status
Simulation time 4161859176 ps
CPU time 6.99 seconds
Started May 12 04:07:42 PM PDT 24
Finished May 12 04:07:49 PM PDT 24
Peak memory 197500 kb
Host smart-8a2d8b5e-4146-46d3-9a8d-6f323fb3f008
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191135407 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_t
l_intg_err.3191135407
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.1808717185
Short name T33
Test name
Test status
Simulation time 76492338911 ps
CPU time 371.12 seconds
Started May 12 01:58:26 PM PDT 24
Finished May 12 02:04:38 PM PDT 24
Peak memory 198656 kb
Host smart-45d0262f-6a5e-41c7-bbd1-b6277932e627
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808717185 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.1808717185
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.337742588
Short name T55
Test name
Test status
Simulation time 479006125 ps
CPU time 0.9 seconds
Started May 12 04:07:06 PM PDT 24
Finished May 12 04:07:07 PM PDT 24
Peak memory 183672 kb
Host smart-f909732d-1ce5-4869-9fa8-a602ca835427
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337742588 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_al
iasing.337742588
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.2730656000
Short name T11
Test name
Test status
Simulation time 4145657998 ps
CPU time 2.4 seconds
Started May 12 01:56:25 PM PDT 24
Finished May 12 01:56:27 PM PDT 24
Peak memory 214752 kb
Host smart-308fbeae-0f7f-43da-89a9-327ff818cbd3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730656000 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.2730656000
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.2367084809
Short name T36
Test name
Test status
Simulation time 177881895968 ps
CPU time 653.88 seconds
Started May 12 01:57:26 PM PDT 24
Finished May 12 02:08:20 PM PDT 24
Peak memory 206688 kb
Host smart-a5c8ff1a-6a13-4587-974a-868c4510cfac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367084809 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.2367084809
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.4176739246
Short name T106
Test name
Test status
Simulation time 8552472705 ps
CPU time 4.47 seconds
Started May 12 04:07:46 PM PDT 24
Finished May 12 04:07:51 PM PDT 24
Peak memory 197848 kb
Host smart-10cc832b-f7ac-4521-9d9b-248e69317cf2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176739246 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_t
l_intg_err.4176739246
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_jump.3375961521
Short name T6
Test name
Test status
Simulation time 337428507 ps
CPU time 1.1 seconds
Started May 12 01:56:21 PM PDT 24
Finished May 12 01:56:22 PM PDT 24
Peak memory 183492 kb
Host smart-dceff337-5b7b-41f4-90bf-277d06a70ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375961521 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.3375961521
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.2402305055
Short name T37
Test name
Test status
Simulation time 147153617600 ps
CPU time 621.92 seconds
Started May 12 01:57:47 PM PDT 24
Finished May 12 02:08:10 PM PDT 24
Peak memory 199484 kb
Host smart-3fade535-8ee0-43b1-b2d6-db7d03c2775b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402305055 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.2402305055
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.3435667040
Short name T72
Test name
Test status
Simulation time 1797906222 ps
CPU time 1.33 seconds
Started May 12 04:07:06 PM PDT 24
Finished May 12 04:07:07 PM PDT 24
Peak memory 183692 kb
Host smart-23fccb8d-e57b-4c8f-92ce-90b28368bd0e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435667040 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon
_timer_same_csr_outstanding.3435667040
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.2384622913
Short name T104
Test name
Test status
Simulation time 4447844375 ps
CPU time 4.55 seconds
Started May 12 04:07:02 PM PDT 24
Finished May 12 04:07:08 PM PDT 24
Peak memory 197548 kb
Host smart-80da4d37-fad2-4e48-83c8-9bf970a1a843
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384622913 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl
_intg_err.2384622913
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.3285139394
Short name T64
Test name
Test status
Simulation time 527475292 ps
CPU time 1.34 seconds
Started May 12 04:06:59 PM PDT 24
Finished May 12 04:07:01 PM PDT 24
Peak memory 193844 kb
Host smart-274d2ad1-09a4-47f0-9444-874b147fa24c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285139394 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_a
liasing.3285139394
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.2211909266
Short name T375
Test name
Test status
Simulation time 14267244601 ps
CPU time 9.42 seconds
Started May 12 04:06:59 PM PDT 24
Finished May 12 04:07:09 PM PDT 24
Peak memory 192192 kb
Host smart-2b715202-5df1-4744-80c4-c98e56d5ad38
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211909266 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_b
it_bash.2211909266
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.224225433
Short name T385
Test name
Test status
Simulation time 1086181720 ps
CPU time 1.56 seconds
Started May 12 04:07:01 PM PDT 24
Finished May 12 04:07:03 PM PDT 24
Peak memory 183712 kb
Host smart-0aae2e2a-b63a-4c3c-a646-a454cc69c1fa
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224225433 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_hw
_reset.224225433
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.3853884003
Short name T362
Test name
Test status
Simulation time 556565153 ps
CPU time 1.23 seconds
Started May 12 04:06:59 PM PDT 24
Finished May 12 04:07:01 PM PDT 24
Peak memory 196028 kb
Host smart-c8f51df0-446a-4043-86ef-22e01ea3abab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853884003 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.3853884003
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.2989555430
Short name T411
Test name
Test status
Simulation time 449640257 ps
CPU time 0.77 seconds
Started May 12 04:07:03 PM PDT 24
Finished May 12 04:07:04 PM PDT 24
Peak memory 193160 kb
Host smart-29affbea-7c75-4142-80e8-a002328178cc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989555430 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.2989555430
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.115693097
Short name T391
Test name
Test status
Simulation time 285861250 ps
CPU time 0.97 seconds
Started May 12 04:07:01 PM PDT 24
Finished May 12 04:07:03 PM PDT 24
Peak memory 183560 kb
Host smart-e2a0b604-0588-48ae-8fef-ab5ebcfc6a85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115693097 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.115693097
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.3765829583
Short name T368
Test name
Test status
Simulation time 442942845 ps
CPU time 0.66 seconds
Started May 12 04:07:00 PM PDT 24
Finished May 12 04:07:01 PM PDT 24
Peak memory 183504 kb
Host smart-08292be4-e931-451a-8ae4-0af9cbd76dd9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765829583 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_t
imer_mem_partial_access.3765829583
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.3569799712
Short name T351
Test name
Test status
Simulation time 487491107 ps
CPU time 0.69 seconds
Started May 12 04:06:59 PM PDT 24
Finished May 12 04:07:00 PM PDT 24
Peak memory 183576 kb
Host smart-36583f9b-b5b2-44dc-af15-59d335021044
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569799712 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_w
alk.3569799712
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.3217715872
Short name T409
Test name
Test status
Simulation time 1114242113 ps
CPU time 2.44 seconds
Started May 12 04:07:00 PM PDT 24
Finished May 12 04:07:03 PM PDT 24
Peak memory 193116 kb
Host smart-2f1562ff-05ec-41bf-aa78-6765dd454b2a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217715872 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon
_timer_same_csr_outstanding.3217715872
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.66618396
Short name T393
Test name
Test status
Simulation time 914312799 ps
CPU time 2.55 seconds
Started May 12 04:06:59 PM PDT 24
Finished May 12 04:07:02 PM PDT 24
Peak memory 198448 kb
Host smart-c3852f2b-8604-41ec-93d8-7362b02b6823
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66618396 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.66618396
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.3117857625
Short name T107
Test name
Test status
Simulation time 4584665254 ps
CPU time 1.8 seconds
Started May 12 04:07:01 PM PDT 24
Finished May 12 04:07:03 PM PDT 24
Peak memory 197420 kb
Host smart-8d38fe85-b755-42b9-bce2-cb9d77646c03
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117857625 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl
_intg_err.3117857625
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.3509801073
Short name T353
Test name
Test status
Simulation time 13918490848 ps
CPU time 23.05 seconds
Started May 12 04:07:06 PM PDT 24
Finished May 12 04:07:30 PM PDT 24
Peak memory 192152 kb
Host smart-0bc4c197-84c8-4265-b141-c7381e9550a8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509801073 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_b
it_bash.3509801073
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.2643820700
Short name T381
Test name
Test status
Simulation time 568926309 ps
CPU time 0.93 seconds
Started May 12 04:07:02 PM PDT 24
Finished May 12 04:07:04 PM PDT 24
Peak memory 183680 kb
Host smart-0b6f0741-c6fa-4a81-84a1-b8f30fc500c0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643820700 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_h
w_reset.2643820700
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.3051512725
Short name T110
Test name
Test status
Simulation time 451043909 ps
CPU time 0.67 seconds
Started May 12 04:07:09 PM PDT 24
Finished May 12 04:07:10 PM PDT 24
Peak memory 195760 kb
Host smart-cbbe51b4-4829-4e3d-a35e-b8641556df25
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051512725 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.3051512725
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.2686892110
Short name T59
Test name
Test status
Simulation time 417008205 ps
CPU time 0.61 seconds
Started May 12 04:07:06 PM PDT 24
Finished May 12 04:07:07 PM PDT 24
Peak memory 183672 kb
Host smart-e7621276-7d44-447b-8b5e-bae303164575
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686892110 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.2686892110
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.1390916737
Short name T403
Test name
Test status
Simulation time 430685329 ps
CPU time 0.69 seconds
Started May 12 04:07:03 PM PDT 24
Finished May 12 04:07:05 PM PDT 24
Peak memory 183520 kb
Host smart-5f244a94-8d55-4ec9-98a0-e131ca6bbe0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390916737 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.1390916737
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.1641670525
Short name T333
Test name
Test status
Simulation time 359920886 ps
CPU time 0.74 seconds
Started May 12 04:07:02 PM PDT 24
Finished May 12 04:07:03 PM PDT 24
Peak memory 183496 kb
Host smart-68021082-2f11-4435-9934-0a7fa3cf999a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641670525 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_t
imer_mem_partial_access.1641670525
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.3931436804
Short name T359
Test name
Test status
Simulation time 309262298 ps
CPU time 1.01 seconds
Started May 12 04:07:03 PM PDT 24
Finished May 12 04:07:04 PM PDT 24
Peak memory 183568 kb
Host smart-53711c3c-e97a-4f03-a597-de7f256639e3
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931436804 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_w
alk.3931436804
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.690231082
Short name T318
Test name
Test status
Simulation time 307422146 ps
CPU time 2.37 seconds
Started May 12 04:07:01 PM PDT 24
Finished May 12 04:07:04 PM PDT 24
Peak memory 198436 kb
Host smart-6f655122-04ad-40aa-a347-8f50468f6515
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690231082 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.690231082
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.512556174
Short name T420
Test name
Test status
Simulation time 504835859 ps
CPU time 1.11 seconds
Started May 12 04:07:35 PM PDT 24
Finished May 12 04:07:37 PM PDT 24
Peak memory 197180 kb
Host smart-7e37e67f-ce2b-48e5-bb56-a8be7cc243b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512556174 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.512556174
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.1569344260
Short name T398
Test name
Test status
Simulation time 447934256 ps
CPU time 0.7 seconds
Started May 12 04:07:37 PM PDT 24
Finished May 12 04:07:38 PM PDT 24
Peak memory 191980 kb
Host smart-6c079514-65f8-42af-bd31-a0a0ef042172
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569344260 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.1569344260
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.3238801001
Short name T358
Test name
Test status
Simulation time 496004777 ps
CPU time 0.99 seconds
Started May 12 04:07:42 PM PDT 24
Finished May 12 04:07:44 PM PDT 24
Peak memory 183588 kb
Host smart-b27d1fb7-0132-4626-aed5-f56b7477747f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238801001 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.3238801001
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.200269232
Short name T336
Test name
Test status
Simulation time 2867907504 ps
CPU time 3.96 seconds
Started May 12 04:07:42 PM PDT 24
Finished May 12 04:07:47 PM PDT 24
Peak memory 194344 kb
Host smart-b94c1070-d5a9-4179-b227-29663fd2ca2e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200269232 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon
_timer_same_csr_outstanding.200269232
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.3091153891
Short name T306
Test name
Test status
Simulation time 439395939 ps
CPU time 1.92 seconds
Started May 12 04:07:36 PM PDT 24
Finished May 12 04:07:39 PM PDT 24
Peak memory 198456 kb
Host smart-19973e70-0c08-49fe-86df-2559773df23f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091153891 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.3091153891
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.3219214208
Short name T405
Test name
Test status
Simulation time 4440805873 ps
CPU time 8.39 seconds
Started May 12 04:07:36 PM PDT 24
Finished May 12 04:07:45 PM PDT 24
Peak memory 196180 kb
Host smart-bc354e2d-f282-4ec8-9051-b2782e40ae5c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219214208 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_t
l_intg_err.3219214208
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.2873257156
Short name T109
Test name
Test status
Simulation time 517628104 ps
CPU time 1.39 seconds
Started May 12 04:07:39 PM PDT 24
Finished May 12 04:07:41 PM PDT 24
Peak memory 196180 kb
Host smart-37f803e0-f2da-4869-a234-4cdcb78f1ade
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873257156 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.2873257156
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.227126621
Short name T401
Test name
Test status
Simulation time 308405402 ps
CPU time 0.64 seconds
Started May 12 04:07:42 PM PDT 24
Finished May 12 04:07:43 PM PDT 24
Peak memory 191984 kb
Host smart-322f526b-3f6d-47c1-8733-550f9da6eeb4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227126621 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.227126621
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.582816775
Short name T332
Test name
Test status
Simulation time 393555070 ps
CPU time 0.66 seconds
Started May 12 04:07:44 PM PDT 24
Finished May 12 04:07:46 PM PDT 24
Peak memory 183524 kb
Host smart-e9100b39-a1f9-42d0-b89f-4306f4778676
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582816775 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.582816775
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.2231319806
Short name T339
Test name
Test status
Simulation time 2219010074 ps
CPU time 1.71 seconds
Started May 12 04:07:38 PM PDT 24
Finished May 12 04:07:40 PM PDT 24
Peak memory 184012 kb
Host smart-961f665e-e314-48ff-be47-28788dca821f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231319806 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.ao
n_timer_same_csr_outstanding.2231319806
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.2583868546
Short name T399
Test name
Test status
Simulation time 1230715105 ps
CPU time 1.28 seconds
Started May 12 04:07:35 PM PDT 24
Finished May 12 04:07:37 PM PDT 24
Peak memory 198468 kb
Host smart-d7d084c6-ad44-4dcf-8b93-f335b4fcdb9b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583868546 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.2583868546
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.3618039116
Short name T416
Test name
Test status
Simulation time 8663060120 ps
CPU time 4.53 seconds
Started May 12 04:07:34 PM PDT 24
Finished May 12 04:07:40 PM PDT 24
Peak memory 197916 kb
Host smart-b15e16cd-c744-4572-824f-e8d9bb2faa27
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618039116 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_t
l_intg_err.3618039116
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.390335293
Short name T29
Test name
Test status
Simulation time 559996255 ps
CPU time 1.1 seconds
Started May 12 04:07:42 PM PDT 24
Finished May 12 04:07:44 PM PDT 24
Peak memory 198360 kb
Host smart-68137fbd-b123-47ed-ad7b-6bb99aaa0b88
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390335293 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.390335293
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.353013204
Short name T342
Test name
Test status
Simulation time 409663969 ps
CPU time 0.77 seconds
Started May 12 04:07:41 PM PDT 24
Finished May 12 04:07:43 PM PDT 24
Peak memory 191968 kb
Host smart-46320c66-da03-4ef0-800f-487457ba4956
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353013204 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.353013204
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.3826944725
Short name T340
Test name
Test status
Simulation time 386968314 ps
CPU time 1.11 seconds
Started May 12 04:07:42 PM PDT 24
Finished May 12 04:07:44 PM PDT 24
Peak memory 183596 kb
Host smart-1491e65e-d116-4c0c-86b8-97ad5bdcab07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826944725 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.3826944725
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.4193185851
Short name T370
Test name
Test status
Simulation time 1054508489 ps
CPU time 1.82 seconds
Started May 12 04:07:41 PM PDT 24
Finished May 12 04:07:43 PM PDT 24
Peak memory 193236 kb
Host smart-339e0a14-1a6f-4137-a54f-c917efea854c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193185851 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.ao
n_timer_same_csr_outstanding.4193185851
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.3420921614
Short name T346
Test name
Test status
Simulation time 718012425 ps
CPU time 1.99 seconds
Started May 12 04:07:44 PM PDT 24
Finished May 12 04:07:47 PM PDT 24
Peak memory 198432 kb
Host smart-91f71bdf-a4f1-467b-a4e7-da57c4d61024
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420921614 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.3420921614
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.3871805694
Short name T364
Test name
Test status
Simulation time 417478027 ps
CPU time 0.97 seconds
Started May 12 04:07:44 PM PDT 24
Finished May 12 04:07:45 PM PDT 24
Peak memory 197132 kb
Host smart-8d7e0933-79ab-4aac-ab38-6029bd13720b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871805694 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.3871805694
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.778197254
Short name T412
Test name
Test status
Simulation time 563112256 ps
CPU time 0.83 seconds
Started May 12 04:07:42 PM PDT 24
Finished May 12 04:07:44 PM PDT 24
Peak memory 183888 kb
Host smart-e683d540-1611-47b7-ace9-401ffa355340
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778197254 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.778197254
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.4087292601
Short name T348
Test name
Test status
Simulation time 495262356 ps
CPU time 1.31 seconds
Started May 12 04:07:43 PM PDT 24
Finished May 12 04:07:45 PM PDT 24
Peak memory 183572 kb
Host smart-cd4ce126-7e58-42df-b31d-11889ec10cc6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087292601 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.4087292601
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.1118332152
Short name T345
Test name
Test status
Simulation time 1161611088 ps
CPU time 0.86 seconds
Started May 12 04:07:42 PM PDT 24
Finished May 12 04:07:44 PM PDT 24
Peak memory 183924 kb
Host smart-877a4aca-470c-4d87-afd8-22e4ca8e3845
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118332152 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.ao
n_timer_same_csr_outstanding.1118332152
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.1217310127
Short name T363
Test name
Test status
Simulation time 611228061 ps
CPU time 1.97 seconds
Started May 12 04:07:43 PM PDT 24
Finished May 12 04:07:46 PM PDT 24
Peak memory 198488 kb
Host smart-990695c2-c65b-432f-b7f8-481d853ae6ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217310127 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.1217310127
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.832577261
Short name T367
Test name
Test status
Simulation time 8066750008 ps
CPU time 13.36 seconds
Started May 12 04:07:44 PM PDT 24
Finished May 12 04:07:58 PM PDT 24
Peak memory 197952 kb
Host smart-66bdee84-0735-4aba-a7eb-c4d40a98f528
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832577261 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl
_intg_err.832577261
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.593063236
Short name T26
Test name
Test status
Simulation time 448097224 ps
CPU time 0.87 seconds
Started May 12 04:07:45 PM PDT 24
Finished May 12 04:07:47 PM PDT 24
Peak memory 196736 kb
Host smart-93e307e4-35ed-426c-85d7-7682c282f428
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593063236 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.593063236
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.2892305830
Short name T314
Test name
Test status
Simulation time 379024035 ps
CPU time 0.66 seconds
Started May 12 04:07:43 PM PDT 24
Finished May 12 04:07:44 PM PDT 24
Peak memory 183892 kb
Host smart-34254faf-e120-4278-be9d-a092acdb5d4d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892305830 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.2892305830
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.1030787972
Short name T329
Test name
Test status
Simulation time 477093556 ps
CPU time 0.57 seconds
Started May 12 04:07:49 PM PDT 24
Finished May 12 04:07:51 PM PDT 24
Peak memory 183564 kb
Host smart-c443b71a-9912-43d5-8850-fd87b63fc1b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030787972 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.1030787972
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.3115492858
Short name T361
Test name
Test status
Simulation time 1536268719 ps
CPU time 3.8 seconds
Started May 12 04:07:50 PM PDT 24
Finished May 12 04:07:54 PM PDT 24
Peak memory 183872 kb
Host smart-d2fcecbb-6636-4b55-947c-657c109fbc35
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115492858 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao
n_timer_same_csr_outstanding.3115492858
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.1681848193
Short name T382
Test name
Test status
Simulation time 457818036 ps
CPU time 1.28 seconds
Started May 12 04:07:42 PM PDT 24
Finished May 12 04:07:44 PM PDT 24
Peak memory 198476 kb
Host smart-58a55138-7d2b-46e4-ab87-2a4d2b03e165
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681848193 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.1681848193
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.711049052
Short name T108
Test name
Test status
Simulation time 4486542920 ps
CPU time 3.29 seconds
Started May 12 04:07:45 PM PDT 24
Finished May 12 04:07:49 PM PDT 24
Peak memory 196400 kb
Host smart-5736d083-ac5f-4377-b7f3-b47272301701
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711049052 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl
_intg_err.711049052
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.607111328
Short name T297
Test name
Test status
Simulation time 495973435 ps
CPU time 1.12 seconds
Started May 12 04:07:50 PM PDT 24
Finished May 12 04:07:52 PM PDT 24
Peak memory 196272 kb
Host smart-2fe1f929-2ac6-4812-b355-93e327b2a59a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607111328 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.607111328
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.3476355966
Short name T407
Test name
Test status
Simulation time 418018496 ps
CPU time 0.9 seconds
Started May 12 04:07:45 PM PDT 24
Finished May 12 04:07:46 PM PDT 24
Peak memory 193036 kb
Host smart-dc2feeb2-026b-4aea-a493-d25f2b1ca48f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476355966 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.3476355966
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.2471488537
Short name T300
Test name
Test status
Simulation time 557423109 ps
CPU time 0.63 seconds
Started May 12 04:07:45 PM PDT 24
Finished May 12 04:07:46 PM PDT 24
Peak memory 183532 kb
Host smart-6131f888-3aaa-4214-ab0b-fb7f475a5d1e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471488537 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.2471488537
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.1670917767
Short name T373
Test name
Test status
Simulation time 3447412580 ps
CPU time 5.6 seconds
Started May 12 04:07:44 PM PDT 24
Finished May 12 04:07:51 PM PDT 24
Peak memory 191968 kb
Host smart-4a25f2f1-360d-4364-af52-f52034e4fae0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670917767 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.ao
n_timer_same_csr_outstanding.1670917767
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.2442844470
Short name T303
Test name
Test status
Simulation time 584135512 ps
CPU time 2.17 seconds
Started May 12 04:07:50 PM PDT 24
Finished May 12 04:07:52 PM PDT 24
Peak memory 198460 kb
Host smart-ffb70a7e-890f-4162-a5cb-4e516f9d4c88
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442844470 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.2442844470
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.623616294
Short name T102
Test name
Test status
Simulation time 4442334939 ps
CPU time 8.05 seconds
Started May 12 04:07:49 PM PDT 24
Finished May 12 04:07:58 PM PDT 24
Peak memory 197468 kb
Host smart-37851b2f-351a-403d-98ab-16a8756d4d4a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623616294 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl
_intg_err.623616294
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.2703652212
Short name T25
Test name
Test status
Simulation time 544995891 ps
CPU time 0.97 seconds
Started May 12 04:07:52 PM PDT 24
Finished May 12 04:07:54 PM PDT 24
Peak memory 195504 kb
Host smart-3ab77142-aab1-43a0-80f6-781e0f73b8ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703652212 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.2703652212
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.2641487034
Short name T349
Test name
Test status
Simulation time 352407776 ps
CPU time 1.08 seconds
Started May 12 04:07:44 PM PDT 24
Finished May 12 04:07:45 PM PDT 24
Peak memory 183816 kb
Host smart-88e85cc4-fe52-4450-83d7-157b95df6e42
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641487034 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.2641487034
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.3152194852
Short name T327
Test name
Test status
Simulation time 516748231 ps
CPU time 0.72 seconds
Started May 12 04:07:43 PM PDT 24
Finished May 12 04:07:44 PM PDT 24
Peak memory 183556 kb
Host smart-0c1d3f06-80f4-4217-84d3-829a3dc02b37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152194852 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.3152194852
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.2596590607
Short name T74
Test name
Test status
Simulation time 1752113904 ps
CPU time 3.33 seconds
Started May 12 04:07:47 PM PDT 24
Finished May 12 04:07:51 PM PDT 24
Peak memory 193268 kb
Host smart-bfba8db8-02bf-4cf5-9061-3c43ba4798b9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596590607 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.ao
n_timer_same_csr_outstanding.2596590607
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.356261861
Short name T324
Test name
Test status
Simulation time 1399937039 ps
CPU time 1.56 seconds
Started May 12 04:07:45 PM PDT 24
Finished May 12 04:07:47 PM PDT 24
Peak memory 198480 kb
Host smart-4cf9d2d2-19de-44bb-a9f7-dd451ea5d5f1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356261861 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.356261861
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.2965534781
Short name T377
Test name
Test status
Simulation time 559616101 ps
CPU time 1.43 seconds
Started May 12 04:07:49 PM PDT 24
Finished May 12 04:07:51 PM PDT 24
Peak memory 195588 kb
Host smart-96a35a25-ad8a-4039-8b5a-0b3146ce4772
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965534781 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.2965534781
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.1887444928
Short name T56
Test name
Test status
Simulation time 515332548 ps
CPU time 0.81 seconds
Started May 12 04:07:55 PM PDT 24
Finished May 12 04:07:57 PM PDT 24
Peak memory 192948 kb
Host smart-dcd0e48a-9814-4f59-84a5-bd05b8e16b86
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887444928 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.1887444928
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.2408515359
Short name T316
Test name
Test status
Simulation time 385570790 ps
CPU time 1.1 seconds
Started May 12 04:07:47 PM PDT 24
Finished May 12 04:07:49 PM PDT 24
Peak memory 183588 kb
Host smart-51d31ebf-39d9-4159-9cee-24355167638a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408515359 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.2408515359
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.3716901690
Short name T397
Test name
Test status
Simulation time 2677790010 ps
CPU time 1.64 seconds
Started May 12 04:07:47 PM PDT 24
Finished May 12 04:07:49 PM PDT 24
Peak memory 183748 kb
Host smart-4a3ac69d-aab7-4fe0-aa94-0c30d2d291ce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716901690 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.ao
n_timer_same_csr_outstanding.3716901690
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.2835092654
Short name T323
Test name
Test status
Simulation time 651924891 ps
CPU time 2.52 seconds
Started May 12 04:07:47 PM PDT 24
Finished May 12 04:07:50 PM PDT 24
Peak memory 198480 kb
Host smart-90bca135-e819-40a3-95d6-4b2c0d3926db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835092654 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.2835092654
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.195827664
Short name T337
Test name
Test status
Simulation time 4218991658 ps
CPU time 3.78 seconds
Started May 12 04:07:51 PM PDT 24
Finished May 12 04:07:55 PM PDT 24
Peak memory 196140 kb
Host smart-844ef105-3b15-4ca9-9498-c46981a279c3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195827664 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl
_intg_err.195827664
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.769169403
Short name T308
Test name
Test status
Simulation time 393400278 ps
CPU time 1.29 seconds
Started May 12 04:07:50 PM PDT 24
Finished May 12 04:07:51 PM PDT 24
Peak memory 195740 kb
Host smart-189dde16-35f6-47df-bdb7-daa409fb1fdc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769169403 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.769169403
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.31198061
Short name T57
Test name
Test status
Simulation time 324783722 ps
CPU time 0.72 seconds
Started May 12 04:07:49 PM PDT 24
Finished May 12 04:07:50 PM PDT 24
Peak memory 192980 kb
Host smart-0f3ad457-4981-44c3-a389-a8cc9b82b104
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31198061 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.31198061
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.3142757256
Short name T299
Test name
Test status
Simulation time 272100455 ps
CPU time 0.95 seconds
Started May 12 04:07:51 PM PDT 24
Finished May 12 04:07:52 PM PDT 24
Peak memory 183572 kb
Host smart-7a1ebcbb-ca0f-444f-9d4d-446af2b83cbd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142757256 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.3142757256
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.1108969192
Short name T396
Test name
Test status
Simulation time 2443415135 ps
CPU time 4.42 seconds
Started May 12 04:07:51 PM PDT 24
Finished May 12 04:07:56 PM PDT 24
Peak memory 194524 kb
Host smart-93ea6816-2774-4ec7-b85a-83fd6c5a9d88
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108969192 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.ao
n_timer_same_csr_outstanding.1108969192
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.1047056851
Short name T309
Test name
Test status
Simulation time 566063284 ps
CPU time 1.55 seconds
Started May 12 04:07:52 PM PDT 24
Finished May 12 04:07:54 PM PDT 24
Peak memory 198400 kb
Host smart-ca8952ca-75d1-4223-8085-d25625ca71b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047056851 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.1047056851
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.2763600467
Short name T376
Test name
Test status
Simulation time 8945228080 ps
CPU time 4.84 seconds
Started May 12 04:07:48 PM PDT 24
Finished May 12 04:07:53 PM PDT 24
Peak memory 198044 kb
Host smart-5535d0ff-9982-4289-97db-60bc0649e6b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763600467 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_t
l_intg_err.2763600467
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.480799817
Short name T355
Test name
Test status
Simulation time 488097610 ps
CPU time 0.98 seconds
Started May 12 04:07:50 PM PDT 24
Finished May 12 04:07:52 PM PDT 24
Peak memory 195544 kb
Host smart-3d64e583-b4d9-484f-b6d3-ce3e0c8e3fb6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480799817 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.480799817
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.954574582
Short name T392
Test name
Test status
Simulation time 464296847 ps
CPU time 1.21 seconds
Started May 12 04:07:50 PM PDT 24
Finished May 12 04:07:51 PM PDT 24
Peak memory 183788 kb
Host smart-92599ae6-6b86-4f58-a9b4-dd173fec4bd5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954574582 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.954574582
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.3013501823
Short name T304
Test name
Test status
Simulation time 494676642 ps
CPU time 0.89 seconds
Started May 12 04:07:52 PM PDT 24
Finished May 12 04:07:53 PM PDT 24
Peak memory 183516 kb
Host smart-8301b5f6-d271-4414-842e-cf773af49c44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013501823 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.3013501823
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.4188147416
Short name T341
Test name
Test status
Simulation time 2408453646 ps
CPU time 2.66 seconds
Started May 12 04:07:53 PM PDT 24
Finished May 12 04:07:56 PM PDT 24
Peak memory 194832 kb
Host smart-7675f87c-dde0-401d-8f5e-a1c89038a643
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188147416 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao
n_timer_same_csr_outstanding.4188147416
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.3487722099
Short name T338
Test name
Test status
Simulation time 361160219 ps
CPU time 2.07 seconds
Started May 12 04:07:51 PM PDT 24
Finished May 12 04:07:54 PM PDT 24
Peak memory 198468 kb
Host smart-c1447303-9af5-45ab-aee8-3fdbbc287e38
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487722099 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.3487722099
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.2455619986
Short name T415
Test name
Test status
Simulation time 4112020444 ps
CPU time 3.03 seconds
Started May 12 04:07:51 PM PDT 24
Finished May 12 04:07:55 PM PDT 24
Peak memory 197592 kb
Host smart-6fd91635-4a9b-481e-919f-fa01b59a3045
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455619986 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_t
l_intg_err.2455619986
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.1363733044
Short name T413
Test name
Test status
Simulation time 526901562 ps
CPU time 1.23 seconds
Started May 12 04:07:15 PM PDT 24
Finished May 12 04:07:17 PM PDT 24
Peak memory 183672 kb
Host smart-89251602-c692-4220-86ed-c4a1216a672b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363733044 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_a
liasing.1363733044
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.1015207496
Short name T53
Test name
Test status
Simulation time 13697806091 ps
CPU time 21.03 seconds
Started May 12 04:07:12 PM PDT 24
Finished May 12 04:07:34 PM PDT 24
Peak memory 192164 kb
Host smart-ff5ead5c-a891-428f-a2eb-d1c4172c65ff
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015207496 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_b
it_bash.1015207496
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.365534806
Short name T378
Test name
Test status
Simulation time 918998585 ps
CPU time 1.33 seconds
Started May 12 04:07:15 PM PDT 24
Finished May 12 04:07:17 PM PDT 24
Peak memory 183736 kb
Host smart-40a6b9ec-8e76-42d9-b89a-ba24b932aa15
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365534806 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_hw
_reset.365534806
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.2575725097
Short name T406
Test name
Test status
Simulation time 556935837 ps
CPU time 1.43 seconds
Started May 12 04:07:15 PM PDT 24
Finished May 12 04:07:16 PM PDT 24
Peak memory 195840 kb
Host smart-f55ab9eb-0195-4deb-8883-4c71eeb76f13
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575725097 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.2575725097
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.943431723
Short name T71
Test name
Test status
Simulation time 415948303 ps
CPU time 0.92 seconds
Started May 12 04:07:12 PM PDT 24
Finished May 12 04:07:13 PM PDT 24
Peak memory 183856 kb
Host smart-80e3756c-2f34-4611-b22f-f1edceb7dd30
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943431723 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.943431723
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.3776816913
Short name T347
Test name
Test status
Simulation time 323836469 ps
CPU time 0.77 seconds
Started May 12 04:07:11 PM PDT 24
Finished May 12 04:07:12 PM PDT 24
Peak memory 183572 kb
Host smart-6f1ca58e-0213-4615-8802-becf783480d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776816913 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.3776816913
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.3486458479
Short name T394
Test name
Test status
Simulation time 271503889 ps
CPU time 0.97 seconds
Started May 12 04:07:11 PM PDT 24
Finished May 12 04:07:13 PM PDT 24
Peak memory 183448 kb
Host smart-5a2458e7-31b2-408e-b21e-905d44309e93
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486458479 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_t
imer_mem_partial_access.3486458479
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.4252490760
Short name T366
Test name
Test status
Simulation time 294250941 ps
CPU time 0.59 seconds
Started May 12 04:07:11 PM PDT 24
Finished May 12 04:07:12 PM PDT 24
Peak memory 183568 kb
Host smart-297dba29-0ac7-4435-86d7-7d3d3230880b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252490760 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_w
alk.4252490760
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.928524827
Short name T70
Test name
Test status
Simulation time 1088392398 ps
CPU time 1.85 seconds
Started May 12 04:07:12 PM PDT 24
Finished May 12 04:07:14 PM PDT 24
Peak memory 193160 kb
Host smart-f015ba3b-b641-4d95-b1b6-b8ebabf1efb3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928524827 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_
timer_same_csr_outstanding.928524827
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.1145646306
Short name T295
Test name
Test status
Simulation time 602913209 ps
CPU time 1.31 seconds
Started May 12 04:07:08 PM PDT 24
Finished May 12 04:07:10 PM PDT 24
Peak memory 198472 kb
Host smart-0b36a298-0043-431d-aa1b-7fd793519bae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145646306 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.1145646306
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.3413211619
Short name T334
Test name
Test status
Simulation time 4061227727 ps
CPU time 7.22 seconds
Started May 12 04:07:09 PM PDT 24
Finished May 12 04:07:17 PM PDT 24
Peak memory 197660 kb
Host smart-0d82a6f4-c2b3-453c-820e-40362076d45c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413211619 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl
_intg_err.3413211619
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.4058243567
Short name T302
Test name
Test status
Simulation time 474683210 ps
CPU time 0.66 seconds
Started May 12 04:07:51 PM PDT 24
Finished May 12 04:07:52 PM PDT 24
Peak memory 183584 kb
Host smart-08474c2b-d399-4078-ad06-1843fee4e63c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058243567 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.4058243567
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.493935427
Short name T315
Test name
Test status
Simulation time 324075565 ps
CPU time 0.65 seconds
Started May 12 04:07:55 PM PDT 24
Finished May 12 04:07:56 PM PDT 24
Peak memory 183564 kb
Host smart-d2986d6b-9730-422b-8d85-70adf01b854c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493935427 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.493935427
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.2237465627
Short name T293
Test name
Test status
Simulation time 295350926 ps
CPU time 0.76 seconds
Started May 12 04:07:54 PM PDT 24
Finished May 12 04:07:55 PM PDT 24
Peak memory 183572 kb
Host smart-b893a215-9823-43ab-ad4c-11999dbf3fec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237465627 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.2237465627
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.1258613822
Short name T319
Test name
Test status
Simulation time 355267968 ps
CPU time 0.89 seconds
Started May 12 04:07:54 PM PDT 24
Finished May 12 04:07:55 PM PDT 24
Peak memory 183680 kb
Host smart-c56e2ef4-3e40-49e1-84de-92c59542c365
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258613822 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.1258613822
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.2540193971
Short name T343
Test name
Test status
Simulation time 304298434 ps
CPU time 0.65 seconds
Started May 12 04:07:54 PM PDT 24
Finished May 12 04:07:56 PM PDT 24
Peak memory 183556 kb
Host smart-a0247e35-02ae-4f10-a701-e13eba06a4e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540193971 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.2540193971
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.688860933
Short name T287
Test name
Test status
Simulation time 434919388 ps
CPU time 0.63 seconds
Started May 12 04:07:56 PM PDT 24
Finished May 12 04:07:57 PM PDT 24
Peak memory 183532 kb
Host smart-ed93708b-81e2-4bc1-b221-9bbc7eec46c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688860933 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.688860933
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.2064023272
Short name T290
Test name
Test status
Simulation time 615267827 ps
CPU time 0.59 seconds
Started May 12 04:07:54 PM PDT 24
Finished May 12 04:07:55 PM PDT 24
Peak memory 183588 kb
Host smart-89c90887-b488-4f60-93ab-b5a3207972d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064023272 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.2064023272
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.4229987952
Short name T419
Test name
Test status
Simulation time 386502427 ps
CPU time 0.81 seconds
Started May 12 04:07:56 PM PDT 24
Finished May 12 04:07:57 PM PDT 24
Peak memory 183596 kb
Host smart-1879bb32-ac6a-4f99-9d5a-f2dfc43dc501
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229987952 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.4229987952
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.1129910126
Short name T294
Test name
Test status
Simulation time 296885734 ps
CPU time 0.97 seconds
Started May 12 04:07:56 PM PDT 24
Finished May 12 04:07:58 PM PDT 24
Peak memory 183572 kb
Host smart-5ae4c9f5-ee1f-4aa8-b0c7-660de8a64850
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129910126 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.1129910126
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.2455394519
Short name T384
Test name
Test status
Simulation time 391569877 ps
CPU time 0.98 seconds
Started May 12 04:07:55 PM PDT 24
Finished May 12 04:07:56 PM PDT 24
Peak memory 183588 kb
Host smart-9c4fbffd-cfdd-47e4-9a39-3957901099cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455394519 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.2455394519
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.1795679043
Short name T54
Test name
Test status
Simulation time 476987534 ps
CPU time 0.85 seconds
Started May 12 04:07:17 PM PDT 24
Finished May 12 04:07:19 PM PDT 24
Peak memory 183656 kb
Host smart-d8fad207-3fd1-4c02-aec9-f07156d17fc7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795679043 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_a
liasing.1795679043
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.2617564855
Short name T60
Test name
Test status
Simulation time 13806070194 ps
CPU time 6.03 seconds
Started May 12 04:07:19 PM PDT 24
Finished May 12 04:07:26 PM PDT 24
Peak memory 192136 kb
Host smart-e6e2c18a-4c47-4f68-839a-7ca994759fc0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617564855 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_b
it_bash.2617564855
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.368056013
Short name T322
Test name
Test status
Simulation time 959629685 ps
CPU time 2.15 seconds
Started May 12 04:07:19 PM PDT 24
Finished May 12 04:07:22 PM PDT 24
Peak memory 183712 kb
Host smart-2a03d95d-0f68-4205-b63f-1d169799aeef
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368056013 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_hw
_reset.368056013
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.3249230821
Short name T356
Test name
Test status
Simulation time 999161927 ps
CPU time 0.92 seconds
Started May 12 04:07:17 PM PDT 24
Finished May 12 04:07:19 PM PDT 24
Peak memory 198308 kb
Host smart-58251161-4be4-4776-a8b4-f2d1723c3f2f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249230821 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.3249230821
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.981086904
Short name T61
Test name
Test status
Simulation time 345183075 ps
CPU time 1.22 seconds
Started May 12 04:07:19 PM PDT 24
Finished May 12 04:07:21 PM PDT 24
Peak memory 192924 kb
Host smart-24e0a538-37ae-48e5-b10a-feba051cc2cc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981086904 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.981086904
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.1714462007
Short name T365
Test name
Test status
Simulation time 437796493 ps
CPU time 0.59 seconds
Started May 12 04:07:19 PM PDT 24
Finished May 12 04:07:20 PM PDT 24
Peak memory 183560 kb
Host smart-3ed309b9-5a5e-49f0-83d2-c68698159d64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714462007 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.1714462007
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.1480251381
Short name T372
Test name
Test status
Simulation time 362853519 ps
CPU time 0.56 seconds
Started May 12 04:07:13 PM PDT 24
Finished May 12 04:07:15 PM PDT 24
Peak memory 183508 kb
Host smart-ad81f2dc-abf9-4462-a357-96449d19fb49
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480251381 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_t
imer_mem_partial_access.1480251381
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.3280743233
Short name T330
Test name
Test status
Simulation time 284146022 ps
CPU time 0.7 seconds
Started May 12 04:07:16 PM PDT 24
Finished May 12 04:07:17 PM PDT 24
Peak memory 183584 kb
Host smart-65b7195e-40b6-4e13-8f34-d10ec739a167
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280743233 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_w
alk.3280743233
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.3540983872
Short name T387
Test name
Test status
Simulation time 1052872917 ps
CPU time 2.26 seconds
Started May 12 04:07:18 PM PDT 24
Finished May 12 04:07:21 PM PDT 24
Peak memory 183832 kb
Host smart-3b033130-78e7-44e9-ba0d-b3c83461fd53
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540983872 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon
_timer_same_csr_outstanding.3540983872
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.2534021258
Short name T317
Test name
Test status
Simulation time 1262358718 ps
CPU time 1.24 seconds
Started May 12 04:07:16 PM PDT 24
Finished May 12 04:07:17 PM PDT 24
Peak memory 198492 kb
Host smart-9812f363-7ab5-4c96-9c74-0b81c9da2a8c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534021258 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.2534021258
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.638233833
Short name T105
Test name
Test status
Simulation time 8675857776 ps
CPU time 6.84 seconds
Started May 12 04:07:14 PM PDT 24
Finished May 12 04:07:21 PM PDT 24
Peak memory 197816 kb
Host smart-d5f0f3d7-3cd3-4fe1-aa7b-0597151bb269
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638233833 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_
intg_err.638233833
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.1682288681
Short name T350
Test name
Test status
Simulation time 264431660 ps
CPU time 0.96 seconds
Started May 12 04:07:56 PM PDT 24
Finished May 12 04:07:57 PM PDT 24
Peak memory 183564 kb
Host smart-1a53e547-2879-4739-ba43-56ce9a96e0f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682288681 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.1682288681
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.3063569909
Short name T369
Test name
Test status
Simulation time 472670776 ps
CPU time 0.86 seconds
Started May 12 04:07:56 PM PDT 24
Finished May 12 04:07:58 PM PDT 24
Peak memory 183576 kb
Host smart-e235a185-7b8e-459e-880f-ec41c95045b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063569909 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.3063569909
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.1681984755
Short name T386
Test name
Test status
Simulation time 351462315 ps
CPU time 0.66 seconds
Started May 12 04:07:54 PM PDT 24
Finished May 12 04:07:55 PM PDT 24
Peak memory 183572 kb
Host smart-3ede5081-2f4a-4a25-bed4-ea5cc21834b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681984755 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.1681984755
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.387247132
Short name T402
Test name
Test status
Simulation time 441808714 ps
CPU time 1.24 seconds
Started May 12 04:07:54 PM PDT 24
Finished May 12 04:07:55 PM PDT 24
Peak memory 183588 kb
Host smart-a6827be4-0ffa-4bb9-9170-acb266544b35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387247132 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.387247132
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.1453198427
Short name T291
Test name
Test status
Simulation time 289424660 ps
CPU time 0.97 seconds
Started May 12 04:07:57 PM PDT 24
Finished May 12 04:07:58 PM PDT 24
Peak memory 183572 kb
Host smart-943cd783-e683-43f6-9021-a772cd2f4ee1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453198427 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.1453198427
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.4170540987
Short name T305
Test name
Test status
Simulation time 481182576 ps
CPU time 0.7 seconds
Started May 12 04:07:54 PM PDT 24
Finished May 12 04:07:56 PM PDT 24
Peak memory 183588 kb
Host smart-513b6eac-70a1-46a1-8a2a-8067d42f722f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170540987 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.4170540987
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.3467489063
Short name T379
Test name
Test status
Simulation time 340967028 ps
CPU time 0.82 seconds
Started May 12 04:07:57 PM PDT 24
Finished May 12 04:07:58 PM PDT 24
Peak memory 183576 kb
Host smart-3c7995f5-9536-4b4f-bd71-885bd0e42b1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467489063 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.3467489063
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.2971434137
Short name T284
Test name
Test status
Simulation time 425883242 ps
CPU time 1.18 seconds
Started May 12 04:07:54 PM PDT 24
Finished May 12 04:07:56 PM PDT 24
Peak memory 183532 kb
Host smart-85c457b3-9bde-424f-9e95-7a0468c20075
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971434137 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.2971434137
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.1503615673
Short name T410
Test name
Test status
Simulation time 509735262 ps
CPU time 1.21 seconds
Started May 12 04:08:11 PM PDT 24
Finished May 12 04:08:13 PM PDT 24
Peak memory 183588 kb
Host smart-157ab042-83ae-4e63-98d7-fc3b97a0c1e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503615673 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.1503615673
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.1660051050
Short name T289
Test name
Test status
Simulation time 457557872 ps
CPU time 1.25 seconds
Started May 12 04:07:55 PM PDT 24
Finished May 12 04:07:57 PM PDT 24
Peak memory 183592 kb
Host smart-0a72aad3-9148-480f-a45c-174cb2c95ae4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660051050 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.1660051050
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.844663581
Short name T374
Test name
Test status
Simulation time 695107772 ps
CPU time 1.76 seconds
Started May 12 04:07:28 PM PDT 24
Finished May 12 04:07:30 PM PDT 24
Peak memory 183632 kb
Host smart-41c44161-0331-4c5a-9db0-bc521198355c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844663581 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_al
iasing.844663581
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.3593638185
Short name T65
Test name
Test status
Simulation time 13961268444 ps
CPU time 4.99 seconds
Started May 12 04:07:20 PM PDT 24
Finished May 12 04:07:26 PM PDT 24
Peak memory 195904 kb
Host smart-88093361-25e9-44fe-a0e8-21a698554adc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593638185 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_b
it_bash.3593638185
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.721444047
Short name T288
Test name
Test status
Simulation time 649374719 ps
CPU time 1.43 seconds
Started May 12 04:07:23 PM PDT 24
Finished May 12 04:07:25 PM PDT 24
Peak memory 183636 kb
Host smart-e76386ac-d89e-4afd-b5b1-72a57f3aee5a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721444047 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_hw
_reset.721444047
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.2629302207
Short name T313
Test name
Test status
Simulation time 349122491 ps
CPU time 0.9 seconds
Started May 12 04:07:20 PM PDT 24
Finished May 12 04:07:22 PM PDT 24
Peak memory 195460 kb
Host smart-59a99985-25cc-4d62-9d22-bda4bb86a088
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629302207 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.2629302207
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.3140157557
Short name T62
Test name
Test status
Simulation time 419244220 ps
CPU time 1.22 seconds
Started May 12 04:07:24 PM PDT 24
Finished May 12 04:07:25 PM PDT 24
Peak memory 193024 kb
Host smart-71ffbc0e-4a6f-4b2c-ab9a-84b6c64dc208
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140157557 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.3140157557
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.3222053171
Short name T312
Test name
Test status
Simulation time 359650411 ps
CPU time 1.04 seconds
Started May 12 04:07:18 PM PDT 24
Finished May 12 04:07:19 PM PDT 24
Peak memory 183556 kb
Host smart-785565f9-9e99-4a1d-b1aa-85316892e09e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222053171 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.3222053171
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.3763420869
Short name T296
Test name
Test status
Simulation time 465003957 ps
CPU time 0.64 seconds
Started May 12 04:07:21 PM PDT 24
Finished May 12 04:07:23 PM PDT 24
Peak memory 183500 kb
Host smart-5c2fa917-58c3-4f6c-a10f-649abe1797e5
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763420869 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_t
imer_mem_partial_access.3763420869
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.316057154
Short name T298
Test name
Test status
Simulation time 311994173 ps
CPU time 1.04 seconds
Started May 12 04:07:20 PM PDT 24
Finished May 12 04:07:22 PM PDT 24
Peak memory 183568 kb
Host smart-8e48630a-fe78-4e9d-b9d1-cf6facaa47a9
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316057154 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_wa
lk.316057154
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.1729695040
Short name T335
Test name
Test status
Simulation time 2528730132 ps
CPU time 6.63 seconds
Started May 12 04:07:22 PM PDT 24
Finished May 12 04:07:30 PM PDT 24
Peak memory 194636 kb
Host smart-ae300ae3-d315-46f2-98b2-8aeecbbd8d9d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729695040 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon
_timer_same_csr_outstanding.1729695040
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.4260433536
Short name T389
Test name
Test status
Simulation time 2078500286 ps
CPU time 2.11 seconds
Started May 12 04:07:16 PM PDT 24
Finished May 12 04:07:19 PM PDT 24
Peak memory 198432 kb
Host smart-7f43ce43-df21-4454-be37-b9b372280bfb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260433536 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.4260433536
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.2985158735
Short name T30
Test name
Test status
Simulation time 8157749733 ps
CPU time 4.46 seconds
Started May 12 04:07:18 PM PDT 24
Finished May 12 04:07:23 PM PDT 24
Peak memory 197888 kb
Host smart-9aee01e9-cd1c-4b8d-976e-86d752338dbd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985158735 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl
_intg_err.2985158735
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.1149638280
Short name T285
Test name
Test status
Simulation time 460008799 ps
CPU time 1.18 seconds
Started May 12 04:07:54 PM PDT 24
Finished May 12 04:07:56 PM PDT 24
Peak memory 183564 kb
Host smart-afe954a5-197e-4cfb-a9ae-9c83790c2f11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149638280 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.1149638280
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.1125250323
Short name T404
Test name
Test status
Simulation time 470771507 ps
CPU time 1.28 seconds
Started May 12 04:07:58 PM PDT 24
Finished May 12 04:08:00 PM PDT 24
Peak memory 183588 kb
Host smart-99e9d8f4-bc7d-4886-8334-8c83d7badb5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125250323 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.1125250323
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.675963911
Short name T286
Test name
Test status
Simulation time 506269639 ps
CPU time 1.37 seconds
Started May 12 04:07:58 PM PDT 24
Finished May 12 04:08:00 PM PDT 24
Peak memory 183592 kb
Host smart-1542bd9d-c9e9-4b20-8d21-2d2d5014805d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675963911 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.675963911
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.2335763773
Short name T395
Test name
Test status
Simulation time 552389396 ps
CPU time 0.64 seconds
Started May 12 04:07:58 PM PDT 24
Finished May 12 04:07:59 PM PDT 24
Peak memory 183596 kb
Host smart-6088f147-e891-49b3-85ca-e27c81bfeae0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335763773 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.2335763773
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.3949753366
Short name T390
Test name
Test status
Simulation time 431526930 ps
CPU time 0.82 seconds
Started May 12 04:07:58 PM PDT 24
Finished May 12 04:07:59 PM PDT 24
Peak memory 183580 kb
Host smart-01457444-6044-4bd1-bdba-fa2e91b50557
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949753366 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.3949753366
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.886424934
Short name T400
Test name
Test status
Simulation time 352422428 ps
CPU time 0.81 seconds
Started May 12 04:07:57 PM PDT 24
Finished May 12 04:07:59 PM PDT 24
Peak memory 183564 kb
Host smart-4c3030e5-4395-4126-842e-92ffd83c9861
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886424934 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.886424934
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.2750198972
Short name T292
Test name
Test status
Simulation time 343633601 ps
CPU time 0.58 seconds
Started May 12 04:07:58 PM PDT 24
Finished May 12 04:08:00 PM PDT 24
Peak memory 183568 kb
Host smart-cee6ef5d-ae0b-4073-9fed-611e1f207e55
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750198972 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.2750198972
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.3553887429
Short name T310
Test name
Test status
Simulation time 320642112 ps
CPU time 0.66 seconds
Started May 12 04:07:57 PM PDT 24
Finished May 12 04:07:58 PM PDT 24
Peak memory 183580 kb
Host smart-6235b5d5-71ab-4566-a17c-c6a07f8ecf17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553887429 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.3553887429
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.3185710865
Short name T321
Test name
Test status
Simulation time 424557024 ps
CPU time 1.12 seconds
Started May 12 04:07:59 PM PDT 24
Finished May 12 04:08:00 PM PDT 24
Peak memory 183568 kb
Host smart-d004dabf-105a-4e42-9c72-4c2926aa114d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185710865 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.3185710865
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.918108132
Short name T307
Test name
Test status
Simulation time 296995057 ps
CPU time 0.84 seconds
Started May 12 04:08:01 PM PDT 24
Finished May 12 04:08:03 PM PDT 24
Peak memory 183588 kb
Host smart-9d51b692-3958-4414-8cfc-6305173b55f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918108132 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.918108132
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.478472032
Short name T328
Test name
Test status
Simulation time 549628822 ps
CPU time 0.84 seconds
Started May 12 04:07:24 PM PDT 24
Finished May 12 04:07:26 PM PDT 24
Peak memory 195796 kb
Host smart-850f7b13-46eb-43db-a4c8-96567c6e7cc3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478472032 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.478472032
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.3848362673
Short name T68
Test name
Test status
Simulation time 364544423 ps
CPU time 0.67 seconds
Started May 12 04:07:26 PM PDT 24
Finished May 12 04:07:27 PM PDT 24
Peak memory 183632 kb
Host smart-0acfd399-1b09-4cbe-bd7a-a0141b875ffc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848362673 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.3848362673
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.1029686993
Short name T354
Test name
Test status
Simulation time 315393241 ps
CPU time 0.58 seconds
Started May 12 04:07:27 PM PDT 24
Finished May 12 04:07:28 PM PDT 24
Peak memory 183544 kb
Host smart-0c55e622-a416-43ce-a89d-6fafad522a85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029686993 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.1029686993
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.4294608429
Short name T69
Test name
Test status
Simulation time 2313651049 ps
CPU time 0.95 seconds
Started May 12 04:07:26 PM PDT 24
Finished May 12 04:07:27 PM PDT 24
Peak memory 194748 kb
Host smart-297c3195-4798-4c12-be50-0e786e41103f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294608429 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon
_timer_same_csr_outstanding.4294608429
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.1753666054
Short name T421
Test name
Test status
Simulation time 453861590 ps
CPU time 2.15 seconds
Started May 12 04:07:22 PM PDT 24
Finished May 12 04:07:25 PM PDT 24
Peak memory 198484 kb
Host smart-6a747a0a-3a42-4855-9ca2-9cdae9630469
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753666054 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.1753666054
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.290783567
Short name T326
Test name
Test status
Simulation time 8684522131 ps
CPU time 10.67 seconds
Started May 12 04:07:20 PM PDT 24
Finished May 12 04:07:31 PM PDT 24
Peak memory 198100 kb
Host smart-d5efed80-7350-4cba-9fd3-5b339645a4ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290783567 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_
intg_err.290783567
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.2868287819
Short name T388
Test name
Test status
Simulation time 516872833 ps
CPU time 1.49 seconds
Started May 12 04:07:30 PM PDT 24
Finished May 12 04:07:32 PM PDT 24
Peak memory 195744 kb
Host smart-3cd76308-2511-4518-a18a-56f8b9fb2092
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868287819 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.2868287819
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.3491006888
Short name T66
Test name
Test status
Simulation time 428501743 ps
CPU time 0.88 seconds
Started May 12 04:07:27 PM PDT 24
Finished May 12 04:07:28 PM PDT 24
Peak memory 183648 kb
Host smart-1ba20433-21aa-4353-9d28-aebf8250cbd9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491006888 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.3491006888
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.1943422896
Short name T414
Test name
Test status
Simulation time 404516906 ps
CPU time 0.67 seconds
Started May 12 04:07:27 PM PDT 24
Finished May 12 04:07:28 PM PDT 24
Peak memory 183572 kb
Host smart-4c1ef3ca-49fb-4d54-aa15-f4e2dba22d85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943422896 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.1943422896
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.1201387944
Short name T67
Test name
Test status
Simulation time 1557241025 ps
CPU time 1.16 seconds
Started May 12 04:07:28 PM PDT 24
Finished May 12 04:07:29 PM PDT 24
Peak memory 183788 kb
Host smart-4de0e26d-3e72-46a0-91db-837b468e4236
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201387944 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon
_timer_same_csr_outstanding.1201387944
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.3636750840
Short name T301
Test name
Test status
Simulation time 2064004802 ps
CPU time 2.16 seconds
Started May 12 04:07:25 PM PDT 24
Finished May 12 04:07:28 PM PDT 24
Peak memory 198504 kb
Host smart-aac1209e-49bd-4b75-9f8f-466d9d42ccb4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636750840 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.3636750840
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.1820390734
Short name T344
Test name
Test status
Simulation time 4271307883 ps
CPU time 4.11 seconds
Started May 12 04:07:25 PM PDT 24
Finished May 12 04:07:30 PM PDT 24
Peak memory 197652 kb
Host smart-23cd5242-075b-4246-b9a7-2fd8dfbe2be6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820390734 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl
_intg_err.1820390734
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.725287085
Short name T311
Test name
Test status
Simulation time 879305879 ps
CPU time 0.87 seconds
Started May 12 04:07:31 PM PDT 24
Finished May 12 04:07:33 PM PDT 24
Peak memory 198032 kb
Host smart-74ab21f8-021f-4cdb-a2da-abb79d126c28
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725287085 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.725287085
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.2279870514
Short name T58
Test name
Test status
Simulation time 434267048 ps
CPU time 0.73 seconds
Started May 12 04:07:34 PM PDT 24
Finished May 12 04:07:35 PM PDT 24
Peak memory 183780 kb
Host smart-3ac75bb7-1187-464f-9d85-68b84923bbb2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279870514 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.2279870514
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.3812577917
Short name T371
Test name
Test status
Simulation time 324456151 ps
CPU time 0.79 seconds
Started May 12 04:07:30 PM PDT 24
Finished May 12 04:07:31 PM PDT 24
Peak memory 183528 kb
Host smart-a9b8f75c-4fac-49ce-958e-e0e1b734f80d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812577917 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.3812577917
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.2272291709
Short name T408
Test name
Test status
Simulation time 1466487992 ps
CPU time 3.98 seconds
Started May 12 04:07:31 PM PDT 24
Finished May 12 04:07:36 PM PDT 24
Peak memory 193164 kb
Host smart-8d572cca-ff09-49df-86d2-d487295a97be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272291709 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon
_timer_same_csr_outstanding.2272291709
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.2761436517
Short name T380
Test name
Test status
Simulation time 653515985 ps
CPU time 1.36 seconds
Started May 12 04:07:29 PM PDT 24
Finished May 12 04:07:30 PM PDT 24
Peak memory 198312 kb
Host smart-d1a9200a-9e7f-435c-9643-02a6c72bc6d5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761436517 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.2761436517
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.3635643432
Short name T417
Test name
Test status
Simulation time 8048163581 ps
CPU time 13.91 seconds
Started May 12 04:07:28 PM PDT 24
Finished May 12 04:07:42 PM PDT 24
Peak memory 197912 kb
Host smart-7028bb1a-a119-4a36-a774-e5244241e039
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635643432 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl
_intg_err.3635643432
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.601590531
Short name T331
Test name
Test status
Simulation time 512682015 ps
CPU time 1.39 seconds
Started May 12 04:07:31 PM PDT 24
Finished May 12 04:07:33 PM PDT 24
Peak memory 195700 kb
Host smart-ba135db5-4fb4-4eb0-b33f-62616ae554e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601590531 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.601590531
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.2496680680
Short name T63
Test name
Test status
Simulation time 283440600 ps
CPU time 0.97 seconds
Started May 12 04:07:36 PM PDT 24
Finished May 12 04:07:37 PM PDT 24
Peak memory 183644 kb
Host smart-3fd6815a-3ef7-40af-b649-ec3d0f1a7918
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496680680 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.2496680680
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.2955122888
Short name T418
Test name
Test status
Simulation time 297366126 ps
CPU time 0.65 seconds
Started May 12 04:07:34 PM PDT 24
Finished May 12 04:07:36 PM PDT 24
Peak memory 183524 kb
Host smart-28534b82-0f91-40aa-80d2-153ee5799b70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955122888 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.2955122888
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.2453517360
Short name T73
Test name
Test status
Simulation time 2333652999 ps
CPU time 3.1 seconds
Started May 12 04:07:34 PM PDT 24
Finished May 12 04:07:38 PM PDT 24
Peak memory 183764 kb
Host smart-df2cb262-ee2b-4c04-a621-d5d2d9525084
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453517360 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon
_timer_same_csr_outstanding.2453517360
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.2858247222
Short name T325
Test name
Test status
Simulation time 347710350 ps
CPU time 1.38 seconds
Started May 12 04:07:31 PM PDT 24
Finished May 12 04:07:33 PM PDT 24
Peak memory 198500 kb
Host smart-04762ba1-2a13-46cd-b171-4724f2883e5e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858247222 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.2858247222
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.3219248190
Short name T103
Test name
Test status
Simulation time 8686893518 ps
CPU time 15.3 seconds
Started May 12 04:07:35 PM PDT 24
Finished May 12 04:07:51 PM PDT 24
Peak memory 197828 kb
Host smart-92cce8be-bfef-4ac3-be9d-51109e2632e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219248190 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl
_intg_err.3219248190
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.1972225891
Short name T383
Test name
Test status
Simulation time 479218068 ps
CPU time 1.01 seconds
Started May 12 04:07:37 PM PDT 24
Finished May 12 04:07:39 PM PDT 24
Peak memory 195688 kb
Host smart-4e9142cd-332e-4711-8555-b4b71ba23dce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972225891 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.1972225891
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.3704252572
Short name T320
Test name
Test status
Simulation time 537920589 ps
CPU time 0.67 seconds
Started May 12 04:07:38 PM PDT 24
Finished May 12 04:07:39 PM PDT 24
Peak memory 183760 kb
Host smart-3e6393be-bd54-4caf-aa44-e64940fbf20e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704252572 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.3704252572
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.137505864
Short name T357
Test name
Test status
Simulation time 462503705 ps
CPU time 0.66 seconds
Started May 12 04:07:42 PM PDT 24
Finished May 12 04:07:43 PM PDT 24
Peak memory 183592 kb
Host smart-5d604a86-4bde-4de8-8b0a-ef292f62fd17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137505864 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.137505864
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.1925464341
Short name T360
Test name
Test status
Simulation time 1920816483 ps
CPU time 1.46 seconds
Started May 12 04:07:34 PM PDT 24
Finished May 12 04:07:36 PM PDT 24
Peak memory 183820 kb
Host smart-59b8a972-b810-4c89-a242-dca986d2b8a0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925464341 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon
_timer_same_csr_outstanding.1925464341
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.43779428
Short name T352
Test name
Test status
Simulation time 389650708 ps
CPU time 1.17 seconds
Started May 12 04:07:31 PM PDT 24
Finished May 12 04:07:33 PM PDT 24
Peak memory 198296 kb
Host smart-83cde3f0-97f3-4c1e-b2ff-142c69667b17
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43779428 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.43779428
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.813355204
Short name T31
Test name
Test status
Simulation time 4399625987 ps
CPU time 2.09 seconds
Started May 12 04:07:35 PM PDT 24
Finished May 12 04:07:38 PM PDT 24
Peak memory 196368 kb
Host smart-e582401f-d0bd-4eef-b5b8-c039701e97aa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813355204 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_
intg_err.813355204
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.3649661816
Short name T196
Test name
Test status
Simulation time 2356134418 ps
CPU time 1.2 seconds
Started May 12 01:56:22 PM PDT 24
Finished May 12 01:56:23 PM PDT 24
Peak memory 183532 kb
Host smart-0f830cd6-5b15-4f7a-9ed0-929b2c1c3014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649661816 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.3649661816
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.3050504340
Short name T179
Test name
Test status
Simulation time 401324359 ps
CPU time 0.69 seconds
Started May 12 01:56:20 PM PDT 24
Finished May 12 01:56:21 PM PDT 24
Peak memory 183476 kb
Host smart-ae8114c0-911c-413b-bed4-163fb22a3919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050504340 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.3050504340
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.3647950666
Short name T219
Test name
Test status
Simulation time 394991252070 ps
CPU time 601.58 seconds
Started May 12 01:56:23 PM PDT 24
Finished May 12 02:06:25 PM PDT 24
Peak memory 193592 kb
Host smart-c6df3f95-c550-4eac-85cb-a4f7603a0e2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647950666 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_a
ll.3647950666
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_jump.1506341435
Short name T75
Test name
Test status
Simulation time 457725540 ps
CPU time 1.33 seconds
Started May 12 01:56:24 PM PDT 24
Finished May 12 01:56:26 PM PDT 24
Peak memory 183428 kb
Host smart-bed636a3-1217-4d41-8894-ede1ce96fb27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506341435 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.1506341435
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.2934915665
Short name T15
Test name
Test status
Simulation time 1950522686 ps
CPU time 1.24 seconds
Started May 12 01:56:24 PM PDT 24
Finished May 12 01:56:25 PM PDT 24
Peak memory 183484 kb
Host smart-1c0c9b71-65a8-4700-a0fc-ce35dbbdd967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934915665 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.2934915665
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.4104309778
Short name T20
Test name
Test status
Simulation time 8426156140 ps
CPU time 3.94 seconds
Started May 12 01:56:27 PM PDT 24
Finished May 12 01:56:31 PM PDT 24
Peak memory 215492 kb
Host smart-a6895f89-3e62-492c-9b00-3161a129cb68
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104309778 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.4104309778
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.1808512734
Short name T207
Test name
Test status
Simulation time 379531772 ps
CPU time 0.71 seconds
Started May 12 01:56:24 PM PDT 24
Finished May 12 01:56:25 PM PDT 24
Peak memory 183744 kb
Host smart-fc917c9a-40d1-4f31-a48a-8d7945e3b523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808512734 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.1808512734
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.2882086044
Short name T101
Test name
Test status
Simulation time 221605848564 ps
CPU time 87.62 seconds
Started May 12 01:56:24 PM PDT 24
Finished May 12 01:57:52 PM PDT 24
Peak memory 183592 kb
Host smart-3954efd0-e134-4406-851e-bf28169baf40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882086044 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_a
ll.2882086044
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.4027090076
Short name T86
Test name
Test status
Simulation time 162251433985 ps
CPU time 434.7 seconds
Started May 12 01:56:24 PM PDT 24
Finished May 12 02:03:39 PM PDT 24
Peak memory 214536 kb
Host smart-3ecc61a1-42f3-4635-8ef9-d56c682ca060
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027090076 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.4027090076
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.aon_timer_jump.3919244909
Short name T9
Test name
Test status
Simulation time 431670747 ps
CPU time 0.91 seconds
Started May 12 01:57:22 PM PDT 24
Finished May 12 01:57:23 PM PDT 24
Peak memory 183512 kb
Host smart-50a1f6a1-9842-4cd5-a138-369761578fe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919244909 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.3919244909
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.3302194147
Short name T80
Test name
Test status
Simulation time 9882673719 ps
CPU time 2.76 seconds
Started May 12 01:57:22 PM PDT 24
Finished May 12 01:57:25 PM PDT 24
Peak memory 191736 kb
Host smart-a221b5a9-bb8d-49dd-ab7b-d9ec99fc0703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302194147 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.3302194147
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.283714254
Short name T7
Test name
Test status
Simulation time 529359693 ps
CPU time 0.91 seconds
Started May 12 01:57:23 PM PDT 24
Finished May 12 01:57:24 PM PDT 24
Peak memory 183492 kb
Host smart-d6072d9b-a69e-4e80-8ceb-0ee5333c4932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283714254 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.283714254
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.3733862046
Short name T145
Test name
Test status
Simulation time 196877160368 ps
CPU time 82.42 seconds
Started May 12 01:57:26 PM PDT 24
Finished May 12 01:58:49 PM PDT 24
Peak memory 183544 kb
Host smart-94bc1b4f-b703-477b-afa9-17eed5625c54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733862046 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_
all.3733862046
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_jump.2328381564
Short name T241
Test name
Test status
Simulation time 559416012 ps
CPU time 0.74 seconds
Started May 12 01:57:24 PM PDT 24
Finished May 12 01:57:25 PM PDT 24
Peak memory 183472 kb
Host smart-aca4ddb6-4d8e-4add-84b8-67757bfa0c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328381564 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.2328381564
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.2344069161
Short name T200
Test name
Test status
Simulation time 37508214127 ps
CPU time 45.56 seconds
Started May 12 01:57:25 PM PDT 24
Finished May 12 01:58:11 PM PDT 24
Peak memory 183532 kb
Host smart-b7baff47-fc41-451c-8d99-10b115d06141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344069161 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.2344069161
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.1842855607
Short name T116
Test name
Test status
Simulation time 594858810 ps
CPU time 0.77 seconds
Started May 12 01:57:24 PM PDT 24
Finished May 12 01:57:25 PM PDT 24
Peak memory 183496 kb
Host smart-2166bf3d-86c5-4553-862c-e53ad513a901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842855607 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.1842855607
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.1362462626
Short name T147
Test name
Test status
Simulation time 175246707738 ps
CPU time 66.22 seconds
Started May 12 01:57:24 PM PDT 24
Finished May 12 01:58:30 PM PDT 24
Peak memory 194536 kb
Host smart-acbd7476-d773-4be5-93b4-0ec03ea3143a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362462626 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_
all.1362462626
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.827924916
Short name T162
Test name
Test status
Simulation time 66665880849 ps
CPU time 187.16 seconds
Started May 12 01:57:25 PM PDT 24
Finished May 12 02:00:33 PM PDT 24
Peak memory 198428 kb
Host smart-b9b6f70c-1e7a-4110-b8b1-ec0a1d3511fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827924916 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand_reset.827924916
Directory /workspace/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.aon_timer_jump.1634768499
Short name T259
Test name
Test status
Simulation time 547375267 ps
CPU time 0.96 seconds
Started May 12 01:57:27 PM PDT 24
Finished May 12 01:57:28 PM PDT 24
Peak memory 183428 kb
Host smart-ea77d57e-6bba-4b89-8165-ef1ffabcb709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634768499 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.1634768499
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.1443016385
Short name T124
Test name
Test status
Simulation time 9151917840 ps
CPU time 3.62 seconds
Started May 12 01:57:28 PM PDT 24
Finished May 12 01:57:32 PM PDT 24
Peak memory 191708 kb
Host smart-346d8fde-cde8-4e52-b2b6-7185890fecb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443016385 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.1443016385
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.3018653675
Short name T273
Test name
Test status
Simulation time 354968977 ps
CPU time 1.11 seconds
Started May 12 01:57:28 PM PDT 24
Finished May 12 01:57:29 PM PDT 24
Peak memory 183508 kb
Host smart-27e6c3a0-3f4b-4d30-808b-3bf27adb3f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018653675 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.3018653675
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.2536148984
Short name T135
Test name
Test status
Simulation time 191617885165 ps
CPU time 74.91 seconds
Started May 12 01:57:31 PM PDT 24
Finished May 12 01:58:46 PM PDT 24
Peak memory 183544 kb
Host smart-d96bd32f-ffaa-4a8c-95cc-1934a3126b7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536148984 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_
all.2536148984
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.4117384774
Short name T47
Test name
Test status
Simulation time 91419554756 ps
CPU time 334.34 seconds
Started May 12 01:57:28 PM PDT 24
Finished May 12 02:03:03 PM PDT 24
Peak memory 198364 kb
Host smart-7d5036cd-ada6-4726-bb67-c84554edffcd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117384774 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.4117384774
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_jump.3928850893
Short name T129
Test name
Test status
Simulation time 575720850 ps
CPU time 0.68 seconds
Started May 12 01:57:31 PM PDT 24
Finished May 12 01:57:33 PM PDT 24
Peak memory 183400 kb
Host smart-d2b25826-f8dd-448f-b45d-8f621bfd3c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928850893 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.3928850893
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.909509090
Short name T267
Test name
Test status
Simulation time 49470017855 ps
CPU time 24.36 seconds
Started May 12 01:57:31 PM PDT 24
Finished May 12 01:57:56 PM PDT 24
Peak memory 183588 kb
Host smart-426e1f07-3753-4646-99f3-842288c733aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909509090 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.909509090
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.479738741
Short name T199
Test name
Test status
Simulation time 341894816 ps
CPU time 1.08 seconds
Started May 12 01:57:33 PM PDT 24
Finished May 12 01:57:34 PM PDT 24
Peak memory 183500 kb
Host smart-2f661327-ddf4-4efe-95e5-7f6ffaaa0762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479738741 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.479738741
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.444489580
Short name T89
Test name
Test status
Simulation time 223862145753 ps
CPU time 412.37 seconds
Started May 12 01:57:32 PM PDT 24
Finished May 12 02:04:25 PM PDT 24
Peak memory 198464 kb
Host smart-80cfd933-51c0-48c2-b6e3-c327de332644
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444489580 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.444489580
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.aon_timer_jump.3921928818
Short name T149
Test name
Test status
Simulation time 553060341 ps
CPU time 0.94 seconds
Started May 12 01:57:38 PM PDT 24
Finished May 12 01:57:39 PM PDT 24
Peak memory 183496 kb
Host smart-8f1fe0f9-9280-4622-b641-fd1a55b73459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921928818 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.3921928818
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.4279698934
Short name T185
Test name
Test status
Simulation time 58429170337 ps
CPU time 91.24 seconds
Started May 12 01:57:36 PM PDT 24
Finished May 12 01:59:08 PM PDT 24
Peak memory 183576 kb
Host smart-2ca90290-3c90-44da-840c-3748af2e0a36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279698934 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.4279698934
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.68712304
Short name T143
Test name
Test status
Simulation time 550593034 ps
CPU time 0.62 seconds
Started May 12 01:57:36 PM PDT 24
Finished May 12 01:57:37 PM PDT 24
Peak memory 183432 kb
Host smart-9d8040ed-28ee-41be-bb20-8c0e2504b65f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68712304 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.68712304
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.2731781561
Short name T274
Test name
Test status
Simulation time 361001507419 ps
CPU time 262.78 seconds
Started May 12 01:57:40 PM PDT 24
Finished May 12 02:02:03 PM PDT 24
Peak memory 194468 kb
Host smart-945acf5c-7cab-4840-b362-32604f4554d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731781561 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_
all.2731781561
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.195195694
Short name T38
Test name
Test status
Simulation time 60496433462 ps
CPU time 181.49 seconds
Started May 12 01:57:39 PM PDT 24
Finished May 12 02:00:40 PM PDT 24
Peak memory 198528 kb
Host smart-5b6d37c9-17ef-4307-b386-7c2d6857ea96
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195195694 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.195195694
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.aon_timer_jump.2225882877
Short name T49
Test name
Test status
Simulation time 423841828 ps
CPU time 0.66 seconds
Started May 12 01:57:43 PM PDT 24
Finished May 12 01:57:44 PM PDT 24
Peak memory 183496 kb
Host smart-5382957a-6464-46de-8a8d-d8b8b6577b65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225882877 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.2225882877
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.3568065649
Short name T257
Test name
Test status
Simulation time 53541739515 ps
CPU time 13.52 seconds
Started May 12 01:57:44 PM PDT 24
Finished May 12 01:57:57 PM PDT 24
Peak memory 183564 kb
Host smart-92c4903d-1bee-43c8-aea3-167ed02f6cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568065649 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.3568065649
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.3691178814
Short name T206
Test name
Test status
Simulation time 514767036 ps
CPU time 0.76 seconds
Started May 12 01:57:44 PM PDT 24
Finished May 12 01:57:45 PM PDT 24
Peak memory 183504 kb
Host smart-03af009f-d6d4-4730-aa1b-3c610b897092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691178814 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.3691178814
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.3353213549
Short name T253
Test name
Test status
Simulation time 406409721978 ps
CPU time 566.47 seconds
Started May 12 01:57:44 PM PDT 24
Finished May 12 02:07:11 PM PDT 24
Peak memory 194832 kb
Host smart-9d6d77f0-086e-443f-a979-22ad791f0403
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353213549 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_
all.3353213549
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.3098008272
Short name T201
Test name
Test status
Simulation time 238440612574 ps
CPU time 615.6 seconds
Started May 12 01:57:44 PM PDT 24
Finished May 12 02:08:00 PM PDT 24
Peak memory 200376 kb
Host smart-732af69f-b535-40ce-8621-b1fd772390cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098008272 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.3098008272
Directory /workspace/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.aon_timer_jump.1711141848
Short name T190
Test name
Test status
Simulation time 430096451 ps
CPU time 0.68 seconds
Started May 12 01:57:47 PM PDT 24
Finished May 12 01:57:48 PM PDT 24
Peak memory 183392 kb
Host smart-5a2562ec-be9f-4e57-b826-511e695e91d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711141848 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.1711141848
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.3220408930
Short name T212
Test name
Test status
Simulation time 25895689846 ps
CPU time 21.9 seconds
Started May 12 01:57:47 PM PDT 24
Finished May 12 01:58:09 PM PDT 24
Peak memory 183456 kb
Host smart-f9672073-a4f8-498e-b8fb-da8dd0e3f011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220408930 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.3220408930
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.3417020069
Short name T133
Test name
Test status
Simulation time 493473254 ps
CPU time 1.3 seconds
Started May 12 01:57:44 PM PDT 24
Finished May 12 01:57:46 PM PDT 24
Peak memory 183484 kb
Host smart-753c0bd7-559f-4d7d-ac93-d7cdc8634329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417020069 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.3417020069
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.56428126
Short name T137
Test name
Test status
Simulation time 49217974074 ps
CPU time 20.35 seconds
Started May 12 01:57:46 PM PDT 24
Finished May 12 01:58:07 PM PDT 24
Peak memory 194956 kb
Host smart-08fe1172-780c-45e4-9b9f-2ce02048aedd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56428126 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_al
l.56428126
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/17.aon_timer_jump.4226721390
Short name T45
Test name
Test status
Simulation time 521138664 ps
CPU time 1.38 seconds
Started May 12 01:57:47 PM PDT 24
Finished May 12 01:57:48 PM PDT 24
Peak memory 183496 kb
Host smart-e521ccbd-f5ef-4bad-8072-48cd3639df35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226721390 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.4226721390
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.1475351426
Short name T122
Test name
Test status
Simulation time 13146044884 ps
CPU time 19.1 seconds
Started May 12 01:57:47 PM PDT 24
Finished May 12 01:58:06 PM PDT 24
Peak memory 191760 kb
Host smart-4e77b572-0c1e-4e37-8bd0-0f58609d3f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475351426 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.1475351426
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.2526456806
Short name T220
Test name
Test status
Simulation time 455204438 ps
CPU time 0.89 seconds
Started May 12 01:57:45 PM PDT 24
Finished May 12 01:57:46 PM PDT 24
Peak memory 183500 kb
Host smart-b46cc36a-eec4-4520-9992-9f1c35b4767c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526456806 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.2526456806
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.1845404466
Short name T275
Test name
Test status
Simulation time 3304360132 ps
CPU time 3.16 seconds
Started May 12 01:57:51 PM PDT 24
Finished May 12 01:57:54 PM PDT 24
Peak memory 193816 kb
Host smart-ad4eddfc-321b-4ff5-b4d9-ba6bd98b130c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845404466 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_
all.1845404466
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.4044806431
Short name T50
Test name
Test status
Simulation time 83135746125 ps
CPU time 479.84 seconds
Started May 12 01:57:46 PM PDT 24
Finished May 12 02:05:46 PM PDT 24
Peak memory 198520 kb
Host smart-e67f8458-914a-4eb5-a30b-08e6060a8d1b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044806431 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.4044806431
Directory /workspace/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.aon_timer_jump.3565388431
Short name T278
Test name
Test status
Simulation time 467432022 ps
CPU time 1.43 seconds
Started May 12 01:57:50 PM PDT 24
Finished May 12 01:57:52 PM PDT 24
Peak memory 183444 kb
Host smart-df719475-e47a-4091-8046-54588fa74acf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565388431 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.3565388431
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.26103635
Short name T117
Test name
Test status
Simulation time 29743329457 ps
CPU time 41.59 seconds
Started May 12 01:57:52 PM PDT 24
Finished May 12 01:58:34 PM PDT 24
Peak memory 183540 kb
Host smart-c18556ce-13f9-4f62-b9b6-7b0d5998f5c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26103635 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.26103635
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.3579219807
Short name T166
Test name
Test status
Simulation time 489379167 ps
CPU time 0.69 seconds
Started May 12 01:57:55 PM PDT 24
Finished May 12 01:57:56 PM PDT 24
Peak memory 183396 kb
Host smart-41b80bd6-661e-4c01-995c-4cf8b3fed613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579219807 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.3579219807
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.4164318769
Short name T177
Test name
Test status
Simulation time 155023589544 ps
CPU time 124.32 seconds
Started May 12 01:57:54 PM PDT 24
Finished May 12 01:59:58 PM PDT 24
Peak memory 194480 kb
Host smart-d82dcc58-7d61-44f3-8741-e3ce7372662a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164318769 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_
all.4164318769
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.1975200665
Short name T237
Test name
Test status
Simulation time 348657135305 ps
CPU time 969.43 seconds
Started May 12 01:57:52 PM PDT 24
Finished May 12 02:14:01 PM PDT 24
Peak memory 204092 kb
Host smart-2c41b28f-e40b-4816-a1e5-56d24a4ca582
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975200665 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.1975200665
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.aon_timer_jump.1403366178
Short name T121
Test name
Test status
Simulation time 459667079 ps
CPU time 0.62 seconds
Started May 12 01:57:55 PM PDT 24
Finished May 12 01:57:56 PM PDT 24
Peak memory 183492 kb
Host smart-ecc534bd-d2b0-42c1-9332-f28c28bb7df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403366178 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.1403366178
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.2294798122
Short name T250
Test name
Test status
Simulation time 32862212599 ps
CPU time 22.66 seconds
Started May 12 01:57:54 PM PDT 24
Finished May 12 01:58:17 PM PDT 24
Peak memory 191788 kb
Host smart-34d33989-d281-41b9-95b2-7ddb1228ca49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294798122 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.2294798122
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.1841313532
Short name T186
Test name
Test status
Simulation time 477066002 ps
CPU time 0.74 seconds
Started May 12 01:57:55 PM PDT 24
Finished May 12 01:57:56 PM PDT 24
Peak memory 183436 kb
Host smart-7cee46b6-b04e-4512-afeb-d42b25db392d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841313532 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.1841313532
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.1959610504
Short name T97
Test name
Test status
Simulation time 269509440667 ps
CPU time 445.97 seconds
Started May 12 01:57:57 PM PDT 24
Finished May 12 02:05:24 PM PDT 24
Peak memory 183464 kb
Host smart-67924d9a-9df5-4812-9a28-97c3c05cbbae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959610504 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_
all.1959610504
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_jump.312988011
Short name T130
Test name
Test status
Simulation time 481069128 ps
CPU time 0.71 seconds
Started May 12 01:56:37 PM PDT 24
Finished May 12 01:56:38 PM PDT 24
Peak memory 183476 kb
Host smart-543e5ec2-d282-4459-b9c3-4e125d395941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312988011 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.312988011
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.1970378371
Short name T96
Test name
Test status
Simulation time 7010282195 ps
CPU time 5.69 seconds
Started May 12 01:56:32 PM PDT 24
Finished May 12 01:56:38 PM PDT 24
Peak memory 191760 kb
Host smart-180037f0-1b8f-4d86-affe-fb1a07de6db1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970378371 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.1970378371
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.1973490537
Short name T21
Test name
Test status
Simulation time 4330250338 ps
CPU time 7.43 seconds
Started May 12 01:56:44 PM PDT 24
Finished May 12 01:56:52 PM PDT 24
Peak memory 215028 kb
Host smart-b1318b47-6228-4ba0-90bd-52c27b8b2dbc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973490537 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.1973490537
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.2822449685
Short name T144
Test name
Test status
Simulation time 454814559 ps
CPU time 0.74 seconds
Started May 12 01:56:28 PM PDT 24
Finished May 12 01:56:28 PM PDT 24
Peak memory 183500 kb
Host smart-c908857c-6239-4664-b08e-f7cc32f969b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822449685 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.2822449685
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.3706090967
Short name T3
Test name
Test status
Simulation time 567614305788 ps
CPU time 860.22 seconds
Started May 12 01:56:45 PM PDT 24
Finished May 12 02:11:06 PM PDT 24
Peak memory 194092 kb
Host smart-b6f0dd7c-7092-4b26-af1b-195bb2251b8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706090967 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_a
ll.3706090967
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.1733971114
Short name T242
Test name
Test status
Simulation time 86818921050 ps
CPU time 690.79 seconds
Started May 12 01:56:47 PM PDT 24
Finished May 12 02:08:18 PM PDT 24
Peak memory 200460 kb
Host smart-91bb4f88-2977-4c4d-8703-6ec4c57b0dbd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733971114 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.1733971114
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.aon_timer_jump.3290734795
Short name T209
Test name
Test status
Simulation time 393041158 ps
CPU time 1.07 seconds
Started May 12 01:57:56 PM PDT 24
Finished May 12 01:57:58 PM PDT 24
Peak memory 183512 kb
Host smart-c98b5b9f-1bca-4f0f-850c-9990792d5dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290734795 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.3290734795
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.3710422034
Short name T180
Test name
Test status
Simulation time 27096953262 ps
CPU time 23.26 seconds
Started May 12 01:57:54 PM PDT 24
Finished May 12 01:58:18 PM PDT 24
Peak memory 183536 kb
Host smart-62436ce3-5b04-4c68-b216-b95e09ee358d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710422034 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.3710422034
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.740188887
Short name T239
Test name
Test status
Simulation time 509218586 ps
CPU time 0.7 seconds
Started May 12 01:57:54 PM PDT 24
Finished May 12 01:57:55 PM PDT 24
Peak memory 183484 kb
Host smart-9d5a6e9c-3237-4a07-8f23-60b26bb5169a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740188887 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.740188887
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.1859143414
Short name T170
Test name
Test status
Simulation time 212641267062 ps
CPU time 320.99 seconds
Started May 12 01:57:58 PM PDT 24
Finished May 12 02:03:19 PM PDT 24
Peak memory 195228 kb
Host smart-4e621c2b-b446-4aa8-aff5-94e3f16ae9a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859143414 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_
all.1859143414
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.3786821449
Short name T84
Test name
Test status
Simulation time 193244284166 ps
CPU time 442.67 seconds
Started May 12 01:57:58 PM PDT 24
Finished May 12 02:05:21 PM PDT 24
Peak memory 214424 kb
Host smart-a1b13ba1-abfd-401e-82ab-d5a90af674a8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786821449 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.3786821449
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_jump.3778808437
Short name T41
Test name
Test status
Simulation time 466179688 ps
CPU time 0.62 seconds
Started May 12 01:58:01 PM PDT 24
Finished May 12 01:58:02 PM PDT 24
Peak memory 183456 kb
Host smart-da5e6070-b028-435a-95fc-e4a2bc30c647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778808437 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.3778808437
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.1646243210
Short name T262
Test name
Test status
Simulation time 43040611326 ps
CPU time 17.94 seconds
Started May 12 01:58:01 PM PDT 24
Finished May 12 01:58:19 PM PDT 24
Peak memory 183536 kb
Host smart-6df1b2ff-d443-4f65-a670-9bd70a30b28f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646243210 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.1646243210
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.3025116726
Short name T188
Test name
Test status
Simulation time 535619619 ps
CPU time 1.3 seconds
Started May 12 01:57:58 PM PDT 24
Finished May 12 01:57:59 PM PDT 24
Peak memory 183488 kb
Host smart-f8438501-4fce-4bfe-b6ef-8b0fd8b33d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025116726 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.3025116726
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.799367222
Short name T282
Test name
Test status
Simulation time 94379761759 ps
CPU time 72.98 seconds
Started May 12 01:58:04 PM PDT 24
Finished May 12 01:59:17 PM PDT 24
Peak memory 183544 kb
Host smart-fb6278e9-885e-4612-bf48-55944c8a907e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799367222 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_a
ll.799367222
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.2504564203
Short name T150
Test name
Test status
Simulation time 38260820125 ps
CPU time 270.68 seconds
Started May 12 01:58:00 PM PDT 24
Finished May 12 02:02:31 PM PDT 24
Peak memory 198440 kb
Host smart-ceaccdf6-fb84-4a22-98a5-3287fed71527
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504564203 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.2504564203
Directory /workspace/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.aon_timer_jump.3384059300
Short name T140
Test name
Test status
Simulation time 541297370 ps
CPU time 0.98 seconds
Started May 12 01:58:04 PM PDT 24
Finished May 12 01:58:05 PM PDT 24
Peak memory 183492 kb
Host smart-ba9f6126-a7fc-46e4-9558-50482e77a2c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384059300 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.3384059300
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.1547272946
Short name T235
Test name
Test status
Simulation time 41397874378 ps
CPU time 17.98 seconds
Started May 12 01:58:03 PM PDT 24
Finished May 12 01:58:21 PM PDT 24
Peak memory 183536 kb
Host smart-01f75a8b-de56-42eb-8dc9-cf4943b4c2af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547272946 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.1547272946
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.18320545
Short name T221
Test name
Test status
Simulation time 450220585 ps
CPU time 0.86 seconds
Started May 12 01:58:04 PM PDT 24
Finished May 12 01:58:05 PM PDT 24
Peak memory 183504 kb
Host smart-77c437ea-f6d5-4c57-b4ec-af525c56a143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18320545 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.18320545
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.2255384714
Short name T23
Test name
Test status
Simulation time 76769339370 ps
CPU time 31.52 seconds
Started May 12 01:58:08 PM PDT 24
Finished May 12 01:58:40 PM PDT 24
Peak memory 193612 kb
Host smart-80077b6c-47e3-4762-9974-e78df6aa675b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255384714 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_
all.2255384714
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.1022993941
Short name T87
Test name
Test status
Simulation time 52328694378 ps
CPU time 586.72 seconds
Started May 12 01:58:08 PM PDT 24
Finished May 12 02:07:55 PM PDT 24
Peak memory 198472 kb
Host smart-15503d08-9115-48c3-8378-67a6556731cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022993941 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.1022993941
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.aon_timer_jump.1560405407
Short name T79
Test name
Test status
Simulation time 365756174 ps
CPU time 1.13 seconds
Started May 12 01:58:08 PM PDT 24
Finished May 12 01:58:09 PM PDT 24
Peak memory 183488 kb
Host smart-a883d2a1-8e9c-44a6-b79f-c1e819a7683e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560405407 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.1560405407
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.1581943833
Short name T223
Test name
Test status
Simulation time 42437591887 ps
CPU time 15.46 seconds
Started May 12 01:58:09 PM PDT 24
Finished May 12 01:58:24 PM PDT 24
Peak memory 183564 kb
Host smart-93c24ad5-700c-40c7-971e-00cb4f4a6898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581943833 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.1581943833
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.1369263717
Short name T260
Test name
Test status
Simulation time 468784376 ps
CPU time 1.34 seconds
Started May 12 01:58:07 PM PDT 24
Finished May 12 01:58:09 PM PDT 24
Peak memory 183436 kb
Host smart-3c721fde-6786-44b1-8b60-e7e6237ca93a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369263717 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.1369263717
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.1609637835
Short name T211
Test name
Test status
Simulation time 122601670828 ps
CPU time 181.21 seconds
Started May 12 01:58:08 PM PDT 24
Finished May 12 02:01:09 PM PDT 24
Peak memory 194976 kb
Host smart-80e5de67-b91d-4c62-8426-699f1763c415
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609637835 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_
all.1609637835
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.685451317
Short name T17
Test name
Test status
Simulation time 712347728258 ps
CPU time 607.36 seconds
Started May 12 01:58:07 PM PDT 24
Finished May 12 02:08:15 PM PDT 24
Peak memory 199632 kb
Host smart-a5646e59-e905-4d64-b109-fd4e1bf29ee5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685451317 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.685451317
Directory /workspace/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.aon_timer_jump.4248417981
Short name T230
Test name
Test status
Simulation time 346999034 ps
CPU time 0.69 seconds
Started May 12 01:58:11 PM PDT 24
Finished May 12 01:58:12 PM PDT 24
Peak memory 183432 kb
Host smart-b5d8ae36-af5e-404e-be11-beb264929ab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248417981 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.4248417981
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.3843069656
Short name T244
Test name
Test status
Simulation time 27482067405 ps
CPU time 12.56 seconds
Started May 12 01:58:10 PM PDT 24
Finished May 12 01:58:23 PM PDT 24
Peak memory 191664 kb
Host smart-ae2b2f12-7a7f-4269-a088-fa3fabf0b657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843069656 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.3843069656
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.721420470
Short name T208
Test name
Test status
Simulation time 456137115 ps
CPU time 0.85 seconds
Started May 12 01:58:08 PM PDT 24
Finished May 12 01:58:09 PM PDT 24
Peak memory 183472 kb
Host smart-0f427a6a-dde2-4903-9247-eda1bc2c10e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721420470 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.721420470
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.2326962694
Short name T82
Test name
Test status
Simulation time 168831758266 ps
CPU time 209.87 seconds
Started May 12 01:58:14 PM PDT 24
Finished May 12 02:01:45 PM PDT 24
Peak memory 183520 kb
Host smart-876657fa-dd49-45a5-a8ed-e1d30db15e88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326962694 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_
all.2326962694
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/25.aon_timer_jump.1781542652
Short name T115
Test name
Test status
Simulation time 564084250 ps
CPU time 0.6 seconds
Started May 12 01:58:14 PM PDT 24
Finished May 12 01:58:15 PM PDT 24
Peak memory 183324 kb
Host smart-c046cf20-cd73-478c-885b-9fd7ac70e06a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781542652 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.1781542652
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.4199312876
Short name T184
Test name
Test status
Simulation time 21669702767 ps
CPU time 7.33 seconds
Started May 12 01:58:17 PM PDT 24
Finished May 12 01:58:25 PM PDT 24
Peak memory 183456 kb
Host smart-e35d3293-755c-43eb-a2ca-5f0c6c11af49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199312876 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.4199312876
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.1811906237
Short name T195
Test name
Test status
Simulation time 366189494 ps
CPU time 0.89 seconds
Started May 12 01:58:15 PM PDT 24
Finished May 12 01:58:16 PM PDT 24
Peak memory 183496 kb
Host smart-a163c6a0-705a-4f2d-b7cb-80209e473562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811906237 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.1811906237
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.2195316769
Short name T249
Test name
Test status
Simulation time 160093858279 ps
CPU time 134.34 seconds
Started May 12 01:58:19 PM PDT 24
Finished May 12 02:00:34 PM PDT 24
Peak memory 194520 kb
Host smart-d9f00928-9c3b-4dfb-a9c9-527433ec38c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195316769 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_
all.2195316769
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.2909004742
Short name T224
Test name
Test status
Simulation time 59953597483 ps
CPU time 346.32 seconds
Started May 12 01:58:18 PM PDT 24
Finished May 12 02:04:04 PM PDT 24
Peak memory 206684 kb
Host smart-f885ca6e-ff82-40cf-9a4a-c38ae4716f61
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909004742 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.2909004742
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.aon_timer_jump.2644482128
Short name T5
Test name
Test status
Simulation time 550706931 ps
CPU time 0.76 seconds
Started May 12 01:58:18 PM PDT 24
Finished May 12 01:58:19 PM PDT 24
Peak memory 183476 kb
Host smart-17deb2d8-d04d-413b-8414-ac7461104de4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644482128 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.2644482128
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.1871766098
Short name T214
Test name
Test status
Simulation time 11210162719 ps
CPU time 16.64 seconds
Started May 12 01:58:20 PM PDT 24
Finished May 12 01:58:37 PM PDT 24
Peak memory 183368 kb
Host smart-86aef4d9-9c3a-4d9b-9c32-64903a6f8372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871766098 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.1871766098
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.945212089
Short name T126
Test name
Test status
Simulation time 366254407 ps
CPU time 0.82 seconds
Started May 12 01:58:17 PM PDT 24
Finished May 12 01:58:18 PM PDT 24
Peak memory 183744 kb
Host smart-a3332b5f-27b0-47c7-b737-5f8d442977ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945212089 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.945212089
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.2864623601
Short name T283
Test name
Test status
Simulation time 62293059442 ps
CPU time 95.59 seconds
Started May 12 01:58:19 PM PDT 24
Finished May 12 01:59:55 PM PDT 24
Peak memory 195280 kb
Host smart-a165a437-174c-40e0-96fc-20dd60f3061d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864623601 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_
all.2864623601
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.1751176933
Short name T210
Test name
Test status
Simulation time 40730072979 ps
CPU time 338.58 seconds
Started May 12 01:58:20 PM PDT 24
Finished May 12 02:03:59 PM PDT 24
Peak memory 198364 kb
Host smart-c688265c-f813-4638-9666-855e624be4df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751176933 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.1751176933
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_jump.3960381059
Short name T193
Test name
Test status
Simulation time 479469697 ps
CPU time 1.22 seconds
Started May 12 01:58:23 PM PDT 24
Finished May 12 01:58:24 PM PDT 24
Peak memory 183440 kb
Host smart-2a72705b-30fc-4d19-820d-7831d9abdd2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960381059 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.3960381059
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.4254002314
Short name T171
Test name
Test status
Simulation time 15457257604 ps
CPU time 3.27 seconds
Started May 12 01:58:23 PM PDT 24
Finished May 12 01:58:27 PM PDT 24
Peak memory 183508 kb
Host smart-33f8eff1-0d47-487a-a363-f914b0a53b65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254002314 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.4254002314
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.1875328174
Short name T240
Test name
Test status
Simulation time 432672552 ps
CPU time 0.68 seconds
Started May 12 01:58:22 PM PDT 24
Finished May 12 01:58:23 PM PDT 24
Peak memory 183500 kb
Host smart-6b443100-854b-4f3a-8878-5d2a7123cafd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875328174 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.1875328174
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.2410183418
Short name T156
Test name
Test status
Simulation time 37576571163 ps
CPU time 60.25 seconds
Started May 12 01:58:26 PM PDT 24
Finished May 12 01:59:26 PM PDT 24
Peak memory 183572 kb
Host smart-7150ef56-3cc2-4d67-aa5d-3bc40d6b6682
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410183418 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_
all.2410183418
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.1381984446
Short name T255
Test name
Test status
Simulation time 112513385977 ps
CPU time 340.09 seconds
Started May 12 01:58:22 PM PDT 24
Finished May 12 02:04:03 PM PDT 24
Peak memory 198480 kb
Host smart-834ae282-794b-4411-865c-1ad7f47dbbb1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381984446 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.1381984446
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_jump.463578376
Short name T264
Test name
Test status
Simulation time 545163692 ps
CPU time 0.58 seconds
Started May 12 01:58:24 PM PDT 24
Finished May 12 01:58:25 PM PDT 24
Peak memory 183496 kb
Host smart-80c0ffde-66f4-486a-8451-06a35d419a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463578376 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.463578376
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.2293621748
Short name T233
Test name
Test status
Simulation time 36713161655 ps
CPU time 29.39 seconds
Started May 12 01:58:25 PM PDT 24
Finished May 12 01:58:55 PM PDT 24
Peak memory 183540 kb
Host smart-67bbdf00-eb1f-4e77-9f2c-1e56158d5564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293621748 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.2293621748
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.3621248362
Short name T178
Test name
Test status
Simulation time 602014233 ps
CPU time 0.76 seconds
Started May 12 01:58:25 PM PDT 24
Finished May 12 01:58:26 PM PDT 24
Peak memory 183500 kb
Host smart-df2ddbf2-42a2-492a-ab4b-e784e75cf623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621248362 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.3621248362
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.3145353730
Short name T98
Test name
Test status
Simulation time 75209787917 ps
CPU time 34.19 seconds
Started May 12 01:58:25 PM PDT 24
Finished May 12 01:58:59 PM PDT 24
Peak memory 195260 kb
Host smart-f6bbae68-a2ad-475e-8735-26d2e977439d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145353730 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_
all.3145353730
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.720675151
Short name T90
Test name
Test status
Simulation time 63135825846 ps
CPU time 123.69 seconds
Started May 12 01:58:24 PM PDT 24
Finished May 12 02:00:28 PM PDT 24
Peak memory 198448 kb
Host smart-67382f95-f0b1-480d-9582-9c9049ffc160
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720675151 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.720675151
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.aon_timer_jump.3941813737
Short name T113
Test name
Test status
Simulation time 348044523 ps
CPU time 0.69 seconds
Started May 12 01:58:27 PM PDT 24
Finished May 12 01:58:28 PM PDT 24
Peak memory 183388 kb
Host smart-657300b2-5749-43fc-909c-cb3f0f2a21e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941813737 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.3941813737
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.2914860058
Short name T2
Test name
Test status
Simulation time 34819758789 ps
CPU time 5.69 seconds
Started May 12 01:58:25 PM PDT 24
Finished May 12 01:58:31 PM PDT 24
Peak memory 183560 kb
Host smart-6ac20450-aae9-46ba-b7f6-0a2e342655cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914860058 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.2914860058
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.3459206651
Short name T280
Test name
Test status
Simulation time 394502205 ps
CPU time 1.23 seconds
Started May 12 01:58:25 PM PDT 24
Finished May 12 01:58:26 PM PDT 24
Peak memory 183504 kb
Host smart-f80b815a-1c48-4e80-94b1-7049a6bbbff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459206651 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.3459206651
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_jump.327366781
Short name T131
Test name
Test status
Simulation time 420244000 ps
CPU time 1.15 seconds
Started May 12 01:56:50 PM PDT 24
Finished May 12 01:56:52 PM PDT 24
Peak memory 183488 kb
Host smart-74404d1d-3687-4b13-8a10-38dae7f63f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327366781 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.327366781
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.1960202606
Short name T46
Test name
Test status
Simulation time 59490937085 ps
CPU time 34.6 seconds
Started May 12 01:56:48 PM PDT 24
Finished May 12 01:57:24 PM PDT 24
Peak memory 191740 kb
Host smart-98f4d8b3-01a1-4d89-9f2e-48ab9608906e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960202606 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.1960202606
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.1702408282
Short name T19
Test name
Test status
Simulation time 4256758847 ps
CPU time 2.54 seconds
Started May 12 01:57:00 PM PDT 24
Finished May 12 01:57:03 PM PDT 24
Peak memory 214816 kb
Host smart-4b65b99e-7866-456f-9987-f873064f419c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702408282 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.1702408282
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.2491932511
Short name T269
Test name
Test status
Simulation time 449112879 ps
CPU time 0.61 seconds
Started May 12 01:56:49 PM PDT 24
Finished May 12 01:56:50 PM PDT 24
Peak memory 183476 kb
Host smart-33614628-708d-4c97-adb0-09de8ffe9b05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491932511 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.2491932511
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.3579079861
Short name T263
Test name
Test status
Simulation time 65741095255 ps
CPU time 97.94 seconds
Started May 12 01:56:59 PM PDT 24
Finished May 12 01:58:37 PM PDT 24
Peak memory 193152 kb
Host smart-19110893-4083-4da0-966d-05c3bd105d5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579079861 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_a
ll.3579079861
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.97136733
Short name T42
Test name
Test status
Simulation time 88602655538 ps
CPU time 715.13 seconds
Started May 12 01:56:51 PM PDT 24
Finished May 12 02:08:46 PM PDT 24
Peak memory 199472 kb
Host smart-595ee59d-2573-4c54-bbc2-deeb344a6eb2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97136733 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.97136733
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_jump.705204355
Short name T138
Test name
Test status
Simulation time 555141819 ps
CPU time 1.4 seconds
Started May 12 01:58:27 PM PDT 24
Finished May 12 01:58:29 PM PDT 24
Peak memory 183444 kb
Host smart-28a18b16-8567-4800-aa4b-ced847ef102e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705204355 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.705204355
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.4042019065
Short name T141
Test name
Test status
Simulation time 4937415482 ps
CPU time 8.4 seconds
Started May 12 01:58:27 PM PDT 24
Finished May 12 01:58:36 PM PDT 24
Peak memory 191788 kb
Host smart-350815dd-27e0-4676-b79b-845c8822f133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042019065 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.4042019065
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.461132176
Short name T111
Test name
Test status
Simulation time 602254164 ps
CPU time 0.75 seconds
Started May 12 01:58:27 PM PDT 24
Finished May 12 01:58:29 PM PDT 24
Peak memory 183484 kb
Host smart-dd817870-3b05-46cf-9ab1-3cdc690c351e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461132176 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.461132176
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.895715020
Short name T276
Test name
Test status
Simulation time 14306711185 ps
CPU time 22.11 seconds
Started May 12 01:58:26 PM PDT 24
Finished May 12 01:58:49 PM PDT 24
Peak memory 183544 kb
Host smart-3f5a3dc6-5087-4353-9d85-9ccf88d357cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895715020 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_a
ll.895715020
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_jump.1041205189
Short name T78
Test name
Test status
Simulation time 490746869 ps
CPU time 0.78 seconds
Started May 12 01:58:30 PM PDT 24
Finished May 12 01:58:31 PM PDT 24
Peak memory 183432 kb
Host smart-6cf2a906-f114-4614-9540-4d9d161cc17b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041205189 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.1041205189
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.2240234581
Short name T187
Test name
Test status
Simulation time 50001142857 ps
CPU time 18.48 seconds
Started May 12 01:58:31 PM PDT 24
Finished May 12 01:58:50 PM PDT 24
Peak memory 183508 kb
Host smart-73e80d38-5a6a-4931-a71c-d888abc49fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240234581 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.2240234581
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.2713341972
Short name T252
Test name
Test status
Simulation time 375389316 ps
CPU time 0.87 seconds
Started May 12 01:58:32 PM PDT 24
Finished May 12 01:58:33 PM PDT 24
Peak memory 183496 kb
Host smart-3eaa0e98-d28d-410e-bab4-6e18d7b8a3d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713341972 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.2713341972
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.4246708928
Short name T168
Test name
Test status
Simulation time 224114979276 ps
CPU time 98.9 seconds
Started May 12 01:58:30 PM PDT 24
Finished May 12 02:00:09 PM PDT 24
Peak memory 183580 kb
Host smart-b46ab9ab-d884-4681-b63c-9f6c3a07c814
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246708928 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_
all.4246708928
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.448386373
Short name T85
Test name
Test status
Simulation time 377374281279 ps
CPU time 250.67 seconds
Started May 12 01:58:31 PM PDT 24
Finished May 12 02:02:42 PM PDT 24
Peak memory 198420 kb
Host smart-8031e3f2-642b-4da2-a86a-8cd4c207c530
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448386373 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.448386373
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.aon_timer_jump.2501541449
Short name T136
Test name
Test status
Simulation time 599145379 ps
CPU time 0.76 seconds
Started May 12 01:58:34 PM PDT 24
Finished May 12 01:58:35 PM PDT 24
Peak memory 183480 kb
Host smart-aebbd681-ecdf-4f55-bba4-fb547bd36406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501541449 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.2501541449
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.2368802326
Short name T43
Test name
Test status
Simulation time 37513880931 ps
CPU time 16.33 seconds
Started May 12 01:58:34 PM PDT 24
Finished May 12 01:58:51 PM PDT 24
Peak memory 191732 kb
Host smart-e794d1ec-3020-42ea-8a6d-a425092e9ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368802326 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.2368802326
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.3582988952
Short name T191
Test name
Test status
Simulation time 600470063 ps
CPU time 0.91 seconds
Started May 12 01:58:36 PM PDT 24
Finished May 12 01:58:38 PM PDT 24
Peak memory 183396 kb
Host smart-5f2c2a13-9bbd-423a-a635-51d8d4a95d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582988952 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.3582988952
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.377260560
Short name T44
Test name
Test status
Simulation time 232751692957 ps
CPU time 156.78 seconds
Started May 12 01:58:38 PM PDT 24
Finished May 12 02:01:15 PM PDT 24
Peak memory 195340 kb
Host smart-1f169919-6287-4c19-bbf7-adca32e186c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377260560 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_a
ll.377260560
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_jump.1630134199
Short name T218
Test name
Test status
Simulation time 389058952 ps
CPU time 1.1 seconds
Started May 12 01:58:37 PM PDT 24
Finished May 12 01:58:39 PM PDT 24
Peak memory 183388 kb
Host smart-5ca9e25f-921c-4ad7-b0e5-e2d3d75eb6c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630134199 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.1630134199
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.1749366506
Short name T226
Test name
Test status
Simulation time 36056163162 ps
CPU time 15.22 seconds
Started May 12 01:58:40 PM PDT 24
Finished May 12 01:58:55 PM PDT 24
Peak memory 191764 kb
Host smart-67a0442d-c709-4c37-bd1e-00fbd0b220ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749366506 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.1749366506
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.1433484334
Short name T181
Test name
Test status
Simulation time 392751669 ps
CPU time 1.17 seconds
Started May 12 01:58:36 PM PDT 24
Finished May 12 01:58:38 PM PDT 24
Peak memory 183476 kb
Host smart-8e1229e8-ccd4-4824-83f3-01eb053f1e80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433484334 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.1433484334
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.3089853148
Short name T231
Test name
Test status
Simulation time 169193000674 ps
CPU time 277.53 seconds
Started May 12 01:58:36 PM PDT 24
Finished May 12 02:03:14 PM PDT 24
Peak memory 193900 kb
Host smart-9cc40e6f-d995-4287-8814-80dabd72e80e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089853148 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_
all.3089853148
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.58844286
Short name T88
Test name
Test status
Simulation time 66508917004 ps
CPU time 669.21 seconds
Started May 12 01:58:36 PM PDT 24
Finished May 12 02:09:46 PM PDT 24
Peak memory 199316 kb
Host smart-f01fc705-6322-4089-a35c-d655ef823d79
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58844286 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.58844286
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.aon_timer_jump.3397995871
Short name T194
Test name
Test status
Simulation time 533782689 ps
CPU time 0.73 seconds
Started May 12 01:58:39 PM PDT 24
Finished May 12 01:58:40 PM PDT 24
Peak memory 183488 kb
Host smart-04850e69-c825-4ace-950b-789bbe8e5add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397995871 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.3397995871
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.2806129249
Short name T142
Test name
Test status
Simulation time 17072611426 ps
CPU time 7.42 seconds
Started May 12 01:58:40 PM PDT 24
Finished May 12 01:58:48 PM PDT 24
Peak memory 183488 kb
Host smart-7714fa37-d3b3-4a82-9e5b-d3fc1726c640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806129249 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.2806129249
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.3820928752
Short name T14
Test name
Test status
Simulation time 453664324 ps
CPU time 0.64 seconds
Started May 12 01:58:40 PM PDT 24
Finished May 12 01:58:41 PM PDT 24
Peak memory 183496 kb
Host smart-20ac516b-4083-4fe6-a3e6-278877e1b076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820928752 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.3820928752
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.3006358428
Short name T83
Test name
Test status
Simulation time 227543567505 ps
CPU time 287.82 seconds
Started May 12 01:58:40 PM PDT 24
Finished May 12 02:03:28 PM PDT 24
Peak memory 198532 kb
Host smart-af8ba048-738b-4b62-b362-b8704dd092ed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006358428 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.3006358428
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.aon_timer_jump.2161863882
Short name T228
Test name
Test status
Simulation time 632209882 ps
CPU time 0.78 seconds
Started May 12 01:58:44 PM PDT 24
Finished May 12 01:58:46 PM PDT 24
Peak memory 183420 kb
Host smart-70f93817-0eea-46ce-9401-6f0eb55f3e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161863882 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.2161863882
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.1720912625
Short name T128
Test name
Test status
Simulation time 24466362689 ps
CPU time 6.95 seconds
Started May 12 01:58:45 PM PDT 24
Finished May 12 01:58:52 PM PDT 24
Peak memory 183560 kb
Host smart-3466e460-138a-49d0-98fe-6229ef50b239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720912625 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.1720912625
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.4011512693
Short name T132
Test name
Test status
Simulation time 401877850 ps
CPU time 0.67 seconds
Started May 12 01:58:41 PM PDT 24
Finished May 12 01:58:42 PM PDT 24
Peak memory 183480 kb
Host smart-71f76e6c-5da2-4a18-80a5-e5c677555a5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011512693 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.4011512693
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.3307810489
Short name T173
Test name
Test status
Simulation time 49542017099 ps
CPU time 6.83 seconds
Started May 12 01:58:46 PM PDT 24
Finished May 12 01:58:54 PM PDT 24
Peak memory 194004 kb
Host smart-ae536a31-5752-4e8a-bf70-adaa2fd79271
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307810489 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_
all.3307810489
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_jump.1254689746
Short name T227
Test name
Test status
Simulation time 447593459 ps
CPU time 0.68 seconds
Started May 12 01:58:49 PM PDT 24
Finished May 12 01:58:50 PM PDT 24
Peak memory 183488 kb
Host smart-6a5799e1-7ef8-4aa0-933c-7925920a02f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254689746 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.1254689746
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.1605300648
Short name T119
Test name
Test status
Simulation time 10808323748 ps
CPU time 7.84 seconds
Started May 12 01:58:47 PM PDT 24
Finished May 12 01:58:56 PM PDT 24
Peak memory 191528 kb
Host smart-1e396e3f-7496-4afc-8a4c-6c1fe3711f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605300648 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.1605300648
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.61467178
Short name T81
Test name
Test status
Simulation time 576339186 ps
CPU time 1.04 seconds
Started May 12 01:58:47 PM PDT 24
Finished May 12 01:58:49 PM PDT 24
Peak memory 183244 kb
Host smart-d316d024-90ac-482a-8d68-32a523ff79ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61467178 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.61467178
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.26187684
Short name T161
Test name
Test status
Simulation time 105637721278 ps
CPU time 56.71 seconds
Started May 12 01:58:49 PM PDT 24
Finished May 12 01:59:46 PM PDT 24
Peak memory 193632 kb
Host smart-240e082e-86c1-4bed-90c4-bf7d8065ff2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26187684 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_al
l.26187684
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.2221985083
Short name T248
Test name
Test status
Simulation time 83637095171 ps
CPU time 663.65 seconds
Started May 12 01:58:51 PM PDT 24
Finished May 12 02:09:56 PM PDT 24
Peak memory 199568 kb
Host smart-f2b9a399-8937-4ebd-af08-22ed3c261e3e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221985083 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.2221985083
Directory /workspace/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.aon_timer_jump.649562096
Short name T120
Test name
Test status
Simulation time 467494754 ps
CPU time 0.73 seconds
Started May 12 01:58:53 PM PDT 24
Finished May 12 01:58:54 PM PDT 24
Peak memory 183744 kb
Host smart-43e28da1-e767-42d6-ac08-4ce1f5276fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649562096 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.649562096
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.1307363596
Short name T127
Test name
Test status
Simulation time 54994393890 ps
CPU time 70.81 seconds
Started May 12 01:58:55 PM PDT 24
Finished May 12 02:00:06 PM PDT 24
Peak memory 183456 kb
Host smart-8221b739-f0a8-4d76-83b9-b8c039485a84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307363596 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.1307363596
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.2957149875
Short name T164
Test name
Test status
Simulation time 481065358 ps
CPU time 0.63 seconds
Started May 12 01:58:52 PM PDT 24
Finished May 12 01:58:53 PM PDT 24
Peak memory 183480 kb
Host smart-ec235bff-ac47-4e63-8143-0a6ef962fdbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957149875 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.2957149875
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.1997282322
Short name T197
Test name
Test status
Simulation time 16685557283 ps
CPU time 2.19 seconds
Started May 12 01:58:52 PM PDT 24
Finished May 12 01:58:55 PM PDT 24
Peak memory 195352 kb
Host smart-fe1fcd81-a761-4d41-8073-61c69ec1cc3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997282322 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_
all.1997282322
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.3784218387
Short name T13
Test name
Test status
Simulation time 68313275207 ps
CPU time 99.59 seconds
Started May 12 01:58:54 PM PDT 24
Finished May 12 02:00:34 PM PDT 24
Peak memory 198540 kb
Host smart-a2a7107b-d3c1-4fa5-974b-c94e09151d5d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784218387 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.3784218387
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.aon_timer_jump.406904303
Short name T265
Test name
Test status
Simulation time 601929000 ps
CPU time 0.63 seconds
Started May 12 01:58:56 PM PDT 24
Finished May 12 01:58:57 PM PDT 24
Peak memory 183460 kb
Host smart-ef569b66-7375-4b13-8947-8b1fae815f6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406904303 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.406904303
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.3151245286
Short name T118
Test name
Test status
Simulation time 10126150466 ps
CPU time 16.39 seconds
Started May 12 01:58:56 PM PDT 24
Finished May 12 01:59:13 PM PDT 24
Peak memory 183532 kb
Host smart-7d8aec60-00a1-494f-8e68-0b2e86a8b0c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151245286 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.3151245286
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.3422052063
Short name T256
Test name
Test status
Simulation time 573944077 ps
CPU time 1.48 seconds
Started May 12 01:58:57 PM PDT 24
Finished May 12 01:58:59 PM PDT 24
Peak memory 183500 kb
Host smart-a28a3ecc-7651-458b-af73-9fe47038ca0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422052063 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.3422052063
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.2531337657
Short name T169
Test name
Test status
Simulation time 77094045357 ps
CPU time 31.96 seconds
Started May 12 01:59:08 PM PDT 24
Finished May 12 01:59:41 PM PDT 24
Peak memory 194884 kb
Host smart-d7bc0cd2-f39c-437e-b6b5-6b4d89c79323
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531337657 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_
all.2531337657
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.1566346887
Short name T281
Test name
Test status
Simulation time 459032743127 ps
CPU time 425.51 seconds
Started May 12 01:59:08 PM PDT 24
Finished May 12 02:06:14 PM PDT 24
Peak memory 198476 kb
Host smart-87decac6-09d5-4c87-9c0d-12fea35fc4d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566346887 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand_reset.1566346887
Directory /workspace/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.aon_timer_jump.683089702
Short name T155
Test name
Test status
Simulation time 513658440 ps
CPU time 0.73 seconds
Started May 12 01:58:59 PM PDT 24
Finished May 12 01:59:00 PM PDT 24
Peak memory 183488 kb
Host smart-461de5f2-9988-4439-9536-ddcd89cf337c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683089702 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.683089702
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.2720931710
Short name T39
Test name
Test status
Simulation time 15428341431 ps
CPU time 5.84 seconds
Started May 12 01:59:08 PM PDT 24
Finished May 12 01:59:15 PM PDT 24
Peak memory 182980 kb
Host smart-1caa72f6-6e71-4938-8858-78b91bd1f278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720931710 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.2720931710
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.3479575694
Short name T245
Test name
Test status
Simulation time 363450383 ps
CPU time 1.05 seconds
Started May 12 01:59:08 PM PDT 24
Finished May 12 01:59:10 PM PDT 24
Peak memory 183376 kb
Host smart-8e0dba67-8412-4230-9246-f423adb7016b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479575694 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.3479575694
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.3372163107
Short name T100
Test name
Test status
Simulation time 161494450042 ps
CPU time 117.35 seconds
Started May 12 01:58:58 PM PDT 24
Finished May 12 02:00:56 PM PDT 24
Peak memory 183464 kb
Host smart-11d2cf0f-f7d7-4b88-82a3-d8ba8b923802
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372163107 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_
all.3372163107
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.966983329
Short name T279
Test name
Test status
Simulation time 254556581050 ps
CPU time 721.51 seconds
Started May 12 01:59:08 PM PDT 24
Finished May 12 02:11:10 PM PDT 24
Peak memory 209100 kb
Host smart-0b3ea8bd-3dcf-4aa0-bc83-ccc931f28f65
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966983329 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.966983329
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_jump.1005612805
Short name T163
Test name
Test status
Simulation time 410556311 ps
CPU time 0.89 seconds
Started May 12 01:56:59 PM PDT 24
Finished May 12 01:57:00 PM PDT 24
Peak memory 183452 kb
Host smart-d4116982-d37d-452f-82bc-90d02e59ee4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005612805 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.1005612805
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.1162307691
Short name T153
Test name
Test status
Simulation time 39192320768 ps
CPU time 52.28 seconds
Started May 12 01:57:00 PM PDT 24
Finished May 12 01:57:52 PM PDT 24
Peak memory 183512 kb
Host smart-d3aa1abc-a6e4-438c-b448-d37634ae6df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162307691 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.1162307691
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.147481410
Short name T18
Test name
Test status
Simulation time 8046173796 ps
CPU time 6.52 seconds
Started May 12 01:57:03 PM PDT 24
Finished May 12 01:57:10 PM PDT 24
Peak memory 215168 kb
Host smart-a0d56ba2-a528-42ba-8a27-68a15a4c2447
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147481410 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.147481410
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.1143065699
Short name T139
Test name
Test status
Simulation time 578742232 ps
CPU time 0.76 seconds
Started May 12 01:57:00 PM PDT 24
Finished May 12 01:57:01 PM PDT 24
Peak memory 183448 kb
Host smart-1b753dad-860a-44f0-9c72-92d7509deebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143065699 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.1143065699
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.1385255451
Short name T151
Test name
Test status
Simulation time 46472890487 ps
CPU time 72.03 seconds
Started May 12 01:57:05 PM PDT 24
Finished May 12 01:58:18 PM PDT 24
Peak memory 193912 kb
Host smart-f0be68ab-5b68-459e-b3d9-561454914d0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385255451 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_a
ll.1385255451
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.3737689604
Short name T35
Test name
Test status
Simulation time 74678510028 ps
CPU time 150.37 seconds
Started May 12 01:56:56 PM PDT 24
Finished May 12 01:59:27 PM PDT 24
Peak memory 198432 kb
Host smart-9a7087b6-926e-4cf8-bd56-723fb72ba518
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737689604 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.3737689604
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.aon_timer_jump.2442068232
Short name T8
Test name
Test status
Simulation time 411916215 ps
CPU time 1.06 seconds
Started May 12 01:59:02 PM PDT 24
Finished May 12 01:59:04 PM PDT 24
Peak memory 183388 kb
Host smart-3efc2691-773e-4c14-86ce-c52626992a14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442068232 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.2442068232
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.459957294
Short name T176
Test name
Test status
Simulation time 51391029055 ps
CPU time 22.17 seconds
Started May 12 01:59:08 PM PDT 24
Finished May 12 01:59:31 PM PDT 24
Peak memory 191216 kb
Host smart-5e28d2b5-973b-4ea8-ac00-a72684bbb28e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459957294 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.459957294
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.1950202140
Short name T202
Test name
Test status
Simulation time 523593888 ps
CPU time 0.77 seconds
Started May 12 01:59:00 PM PDT 24
Finished May 12 01:59:01 PM PDT 24
Peak memory 183504 kb
Host smart-effec1da-23df-4b8d-8fc6-c607799a0567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950202140 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.1950202140
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.857221707
Short name T76
Test name
Test status
Simulation time 91700183148 ps
CPU time 39.05 seconds
Started May 12 01:59:02 PM PDT 24
Finished May 12 01:59:42 PM PDT 24
Peak memory 193716 kb
Host smart-b3f3157c-a2ad-439a-98cf-25168950c718
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857221707 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_a
ll.857221707
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.2791868015
Short name T32
Test name
Test status
Simulation time 187492207541 ps
CPU time 426.03 seconds
Started May 12 01:59:01 PM PDT 24
Finished May 12 02:06:08 PM PDT 24
Peak memory 198484 kb
Host smart-2c17ef0b-0f24-4311-841b-581951bc120e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791868015 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.2791868015
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.aon_timer_jump.647658743
Short name T167
Test name
Test status
Simulation time 511829491 ps
CPU time 1.23 seconds
Started May 12 01:59:06 PM PDT 24
Finished May 12 01:59:08 PM PDT 24
Peak memory 183476 kb
Host smart-4b68a7fb-1e9d-4c10-ada3-3da0dd7b9f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647658743 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.647658743
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.1114967439
Short name T51
Test name
Test status
Simulation time 50367418595 ps
CPU time 73.16 seconds
Started May 12 01:59:06 PM PDT 24
Finished May 12 02:00:20 PM PDT 24
Peak memory 183564 kb
Host smart-e34a93ee-3751-43b2-977f-7e2613ac259e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114967439 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.1114967439
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.3139854663
Short name T183
Test name
Test status
Simulation time 575698499 ps
CPU time 0.91 seconds
Started May 12 01:59:02 PM PDT 24
Finished May 12 01:59:04 PM PDT 24
Peak memory 183508 kb
Host smart-6c1a385a-699a-4514-b0f9-37d42a86c028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139854663 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.3139854663
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.305694918
Short name T93
Test name
Test status
Simulation time 93708186799 ps
CPU time 292.63 seconds
Started May 12 01:59:05 PM PDT 24
Finished May 12 02:03:59 PM PDT 24
Peak memory 198420 kb
Host smart-155c57fc-2924-49b1-b761-825bedf85a45
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305694918 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.305694918
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.aon_timer_jump.1948731661
Short name T236
Test name
Test status
Simulation time 434851330 ps
CPU time 0.91 seconds
Started May 12 01:59:10 PM PDT 24
Finished May 12 01:59:11 PM PDT 24
Peak memory 183488 kb
Host smart-23467e94-d6be-43c9-a9a8-66bf5ab9b31c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948731661 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.1948731661
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.1597157359
Short name T213
Test name
Test status
Simulation time 4411117472 ps
CPU time 2.41 seconds
Started May 12 01:59:05 PM PDT 24
Finished May 12 01:59:08 PM PDT 24
Peak memory 183532 kb
Host smart-ac1c5d92-c498-48da-bac9-918223a4f136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597157359 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.1597157359
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.724208872
Short name T182
Test name
Test status
Simulation time 569879180 ps
CPU time 0.84 seconds
Started May 12 01:59:07 PM PDT 24
Finished May 12 01:59:08 PM PDT 24
Peak memory 183500 kb
Host smart-bbcb5f03-ab96-43ee-a945-51beb18a1780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724208872 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.724208872
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.1947347528
Short name T22
Test name
Test status
Simulation time 234147542655 ps
CPU time 65.05 seconds
Started May 12 01:59:09 PM PDT 24
Finished May 12 02:00:14 PM PDT 24
Peak memory 183504 kb
Host smart-69085c1f-727b-4eef-98eb-b23ade56f226
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947347528 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_
all.1947347528
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.3132798399
Short name T261
Test name
Test status
Simulation time 241332587214 ps
CPU time 512.48 seconds
Started May 12 01:59:10 PM PDT 24
Finished May 12 02:07:43 PM PDT 24
Peak memory 198652 kb
Host smart-a45d9f5c-e811-47da-b30a-ecad01060773
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132798399 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.3132798399
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.aon_timer_jump.3215592192
Short name T271
Test name
Test status
Simulation time 547888036 ps
CPU time 1.32 seconds
Started May 12 01:59:10 PM PDT 24
Finished May 12 01:59:12 PM PDT 24
Peak memory 183496 kb
Host smart-a6871cb3-4ce2-42da-b75a-ccd8296739b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215592192 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.3215592192
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.3762079087
Short name T152
Test name
Test status
Simulation time 4097780689 ps
CPU time 3.51 seconds
Started May 12 01:59:10 PM PDT 24
Finished May 12 01:59:13 PM PDT 24
Peak memory 183564 kb
Host smart-5118bbfd-6c3e-4378-ba3a-919954db1dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762079087 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.3762079087
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.2417957432
Short name T238
Test name
Test status
Simulation time 427478021 ps
CPU time 1.13 seconds
Started May 12 01:59:10 PM PDT 24
Finished May 12 01:59:12 PM PDT 24
Peak memory 183532 kb
Host smart-ca957862-3027-44eb-acff-ad0aa02459a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417957432 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.2417957432
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.1864661541
Short name T146
Test name
Test status
Simulation time 350925785361 ps
CPU time 47.46 seconds
Started May 12 01:59:13 PM PDT 24
Finished May 12 02:00:01 PM PDT 24
Peak memory 193568 kb
Host smart-213b19cb-ec4e-4fdb-8222-a65ddf8ae9b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864661541 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_
all.1864661541
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.3894032134
Short name T272
Test name
Test status
Simulation time 83033147566 ps
CPU time 612.61 seconds
Started May 12 01:59:13 PM PDT 24
Finished May 12 02:09:26 PM PDT 24
Peak memory 199228 kb
Host smart-6610a171-1d7a-439a-b228-7a478102127d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894032134 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.3894032134
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.aon_timer_jump.1984445109
Short name T112
Test name
Test status
Simulation time 453533964 ps
CPU time 1.24 seconds
Started May 12 01:59:19 PM PDT 24
Finished May 12 01:59:20 PM PDT 24
Peak memory 183488 kb
Host smart-1e249019-cbd9-4a18-9b0e-027847fa78d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984445109 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.1984445109
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.1349629333
Short name T225
Test name
Test status
Simulation time 34130509733 ps
CPU time 11.26 seconds
Started May 12 01:59:16 PM PDT 24
Finished May 12 01:59:28 PM PDT 24
Peak memory 183536 kb
Host smart-e2b911a6-43bc-42f0-ba9e-db0a3c59d58a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349629333 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.1349629333
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.371990272
Short name T203
Test name
Test status
Simulation time 343845678 ps
CPU time 0.91 seconds
Started May 12 01:59:15 PM PDT 24
Finished May 12 01:59:16 PM PDT 24
Peak memory 183460 kb
Host smart-09ba42bc-32e6-4de3-8c2b-62a68baf1aa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371990272 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.371990272
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.1364513077
Short name T243
Test name
Test status
Simulation time 139696653117 ps
CPU time 37.8 seconds
Started May 12 01:59:19 PM PDT 24
Finished May 12 01:59:57 PM PDT 24
Peak memory 193720 kb
Host smart-478f3f37-7f6b-40f3-9db7-a4c4b79591c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364513077 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_
all.1364513077
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.2124544370
Short name T172
Test name
Test status
Simulation time 344821881168 ps
CPU time 897.36 seconds
Started May 12 01:59:19 PM PDT 24
Finished May 12 02:14:17 PM PDT 24
Peak memory 203288 kb
Host smart-04bae553-c221-43de-ab52-4208e1a1095e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124544370 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.2124544370
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.aon_timer_jump.3079132417
Short name T189
Test name
Test status
Simulation time 436110113 ps
CPU time 0.91 seconds
Started May 12 01:59:19 PM PDT 24
Finished May 12 01:59:20 PM PDT 24
Peak memory 183396 kb
Host smart-97ede41a-b951-4278-9fee-7ba0afe74be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079132417 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.3079132417
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.652824459
Short name T266
Test name
Test status
Simulation time 9520365700 ps
CPU time 16.65 seconds
Started May 12 01:59:19 PM PDT 24
Finished May 12 01:59:36 PM PDT 24
Peak memory 183512 kb
Host smart-186d9c85-d7cf-4580-8d12-ac91fdc0690a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652824459 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.652824459
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.4110150589
Short name T158
Test name
Test status
Simulation time 588364955 ps
CPU time 0.69 seconds
Started May 12 01:59:21 PM PDT 24
Finished May 12 01:59:22 PM PDT 24
Peak memory 183488 kb
Host smart-e2400a8e-ba16-47da-b86f-36581117e877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110150589 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.4110150589
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.1653193300
Short name T99
Test name
Test status
Simulation time 234520193747 ps
CPU time 341.16 seconds
Started May 12 01:59:19 PM PDT 24
Finished May 12 02:05:00 PM PDT 24
Peak memory 194116 kb
Host smart-128eff23-9c39-460e-b553-f59bdd5031b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653193300 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_
all.1653193300
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.2040362825
Short name T92
Test name
Test status
Simulation time 182699569085 ps
CPU time 315.73 seconds
Started May 12 01:59:19 PM PDT 24
Finished May 12 02:04:35 PM PDT 24
Peak memory 198464 kb
Host smart-d614b560-6c88-4f75-838c-8541679cb9df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040362825 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.2040362825
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.aon_timer_jump.4036192920
Short name T160
Test name
Test status
Simulation time 386055812 ps
CPU time 1.1 seconds
Started May 12 01:59:26 PM PDT 24
Finished May 12 01:59:28 PM PDT 24
Peak memory 183464 kb
Host smart-d41d4b2d-6462-42be-bc91-4517d69c243c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036192920 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.4036192920
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.1055636125
Short name T134
Test name
Test status
Simulation time 20827730161 ps
CPU time 29.59 seconds
Started May 12 01:59:21 PM PDT 24
Finished May 12 01:59:51 PM PDT 24
Peak memory 183568 kb
Host smart-5b10378d-e6e4-419a-b77b-9ac423238229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055636125 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.1055636125
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.2317984346
Short name T157
Test name
Test status
Simulation time 620554950 ps
CPU time 0.7 seconds
Started May 12 01:59:24 PM PDT 24
Finished May 12 01:59:25 PM PDT 24
Peak memory 183436 kb
Host smart-fcf38dfe-e4af-427f-b2c2-b6fcb7659e66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317984346 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.2317984346
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.1950749187
Short name T192
Test name
Test status
Simulation time 285814443486 ps
CPU time 436.95 seconds
Started May 12 01:59:27 PM PDT 24
Finished May 12 02:06:44 PM PDT 24
Peak memory 183468 kb
Host smart-3f0b844c-7b41-490c-8da4-0a0861d0e641
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950749187 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_
all.1950749187
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.1242050691
Short name T159
Test name
Test status
Simulation time 46152526156 ps
CPU time 362.14 seconds
Started May 12 01:59:22 PM PDT 24
Finished May 12 02:05:24 PM PDT 24
Peak memory 198364 kb
Host smart-d581b5f8-2115-4e41-8664-02691ebb662e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242050691 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.1242050691
Directory /workspace/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.aon_timer_jump.1282624549
Short name T246
Test name
Test status
Simulation time 613261771 ps
CPU time 0.79 seconds
Started May 12 01:59:26 PM PDT 24
Finished May 12 01:59:27 PM PDT 24
Peak memory 183468 kb
Host smart-3fb547ad-8f30-451f-b6f4-58618837bc3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282624549 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.1282624549
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.1321734100
Short name T148
Test name
Test status
Simulation time 25968895793 ps
CPU time 11.29 seconds
Started May 12 01:59:26 PM PDT 24
Finished May 12 01:59:37 PM PDT 24
Peak memory 183536 kb
Host smart-6cc29e0d-10c7-434d-82cc-83a08056b412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321734100 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.1321734100
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.345610752
Short name T222
Test name
Test status
Simulation time 414456381 ps
CPU time 0.61 seconds
Started May 12 01:59:26 PM PDT 24
Finished May 12 01:59:27 PM PDT 24
Peak memory 183468 kb
Host smart-43b6b3ef-9e2a-4352-9223-2b8c7660dd89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345610752 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.345610752
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.3252845262
Short name T28
Test name
Test status
Simulation time 141453188303 ps
CPU time 31.03 seconds
Started May 12 01:59:30 PM PDT 24
Finished May 12 02:00:01 PM PDT 24
Peak memory 195308 kb
Host smart-560bd7a9-4d5d-41ab-999a-1a6e7cfdda15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252845262 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_
all.3252845262
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.4251820393
Short name T174
Test name
Test status
Simulation time 217126276140 ps
CPU time 206.42 seconds
Started May 12 01:59:24 PM PDT 24
Finished May 12 02:02:51 PM PDT 24
Peak memory 198496 kb
Host smart-c82d04ed-eb88-404f-993d-a87b20ec48ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251820393 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.4251820393
Directory /workspace/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_jump.1987047947
Short name T216
Test name
Test status
Simulation time 396619482 ps
CPU time 0.66 seconds
Started May 12 01:59:28 PM PDT 24
Finished May 12 01:59:29 PM PDT 24
Peak memory 183480 kb
Host smart-8bfec7f2-830a-40c8-ac08-be651e1e92e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987047947 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.1987047947
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.2154702326
Short name T125
Test name
Test status
Simulation time 59603022129 ps
CPU time 95.31 seconds
Started May 12 01:59:29 PM PDT 24
Finished May 12 02:01:04 PM PDT 24
Peak memory 191660 kb
Host smart-d3c59a12-6797-4778-bb75-bb4a5d09f7a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154702326 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.2154702326
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.2840103217
Short name T247
Test name
Test status
Simulation time 433283945 ps
CPU time 1.11 seconds
Started May 12 01:59:29 PM PDT 24
Finished May 12 01:59:31 PM PDT 24
Peak memory 183480 kb
Host smart-8cbb6104-c416-49b8-8ed6-c7d7a581d0f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840103217 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.2840103217
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.629387347
Short name T232
Test name
Test status
Simulation time 47111397577 ps
CPU time 4.86 seconds
Started May 12 01:59:33 PM PDT 24
Finished May 12 01:59:39 PM PDT 24
Peak memory 183572 kb
Host smart-04d4418e-dfbc-4926-b4db-d509ded0257a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629387347 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_a
ll.629387347
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_jump.1852296938
Short name T254
Test name
Test status
Simulation time 563126416 ps
CPU time 0.76 seconds
Started May 12 01:59:38 PM PDT 24
Finished May 12 01:59:39 PM PDT 24
Peak memory 183420 kb
Host smart-fc27add3-054b-4211-a4ca-28ae4d053b67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852296938 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.1852296938
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.1284293310
Short name T95
Test name
Test status
Simulation time 8642025049 ps
CPU time 2.24 seconds
Started May 12 01:59:38 PM PDT 24
Finished May 12 01:59:40 PM PDT 24
Peak memory 191760 kb
Host smart-a82d2814-0623-4df7-aef2-28934708fdfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284293310 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.1284293310
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.2764905471
Short name T175
Test name
Test status
Simulation time 457006041 ps
CPU time 0.7 seconds
Started May 12 01:59:37 PM PDT 24
Finished May 12 01:59:38 PM PDT 24
Peak memory 183504 kb
Host smart-47302fc1-312e-4346-931a-c2cb8d776818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764905471 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.2764905471
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.1587600915
Short name T204
Test name
Test status
Simulation time 192139570902 ps
CPU time 69.45 seconds
Started May 12 01:59:39 PM PDT 24
Finished May 12 02:00:49 PM PDT 24
Peak memory 183532 kb
Host smart-ae7fc313-3d95-411a-9b39-b5eabe29e2a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587600915 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_
all.1587600915
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.2319802086
Short name T154
Test name
Test status
Simulation time 41010201799 ps
CPU time 346.8 seconds
Started May 12 01:59:37 PM PDT 24
Finished May 12 02:05:24 PM PDT 24
Peak memory 198528 kb
Host smart-196458cc-7be0-4ddf-95fe-3ed68db8dd0a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319802086 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.2319802086
Directory /workspace/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.aon_timer_jump.3009191805
Short name T251
Test name
Test status
Simulation time 623259612 ps
CPU time 1.02 seconds
Started May 12 01:56:58 PM PDT 24
Finished May 12 01:56:59 PM PDT 24
Peak memory 183504 kb
Host smart-56c1d24e-9469-4cf5-ace6-c05211e9550c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009191805 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.3009191805
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.1505070178
Short name T217
Test name
Test status
Simulation time 23929249045 ps
CPU time 5.99 seconds
Started May 12 01:56:58 PM PDT 24
Finished May 12 01:57:04 PM PDT 24
Peak memory 183540 kb
Host smart-0f5c6c5b-a51c-481b-ba9a-95bfa2886088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505070178 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.1505070178
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.996598116
Short name T123
Test name
Test status
Simulation time 469304383 ps
CPU time 1.05 seconds
Started May 12 01:56:58 PM PDT 24
Finished May 12 01:56:59 PM PDT 24
Peak memory 183508 kb
Host smart-6e3e74a3-aa01-4df7-8ec0-584a9cb15fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996598116 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.996598116
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.3498876872
Short name T77
Test name
Test status
Simulation time 108180493781 ps
CPU time 153.62 seconds
Started May 12 01:57:00 PM PDT 24
Finished May 12 01:59:34 PM PDT 24
Peak memory 183556 kb
Host smart-7f0dba1b-fbee-4ddb-93da-a4a5f5d064e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498876872 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_a
ll.3498876872
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.1716512948
Short name T94
Test name
Test status
Simulation time 125595527121 ps
CPU time 365.19 seconds
Started May 12 01:56:58 PM PDT 24
Finished May 12 02:03:03 PM PDT 24
Peak memory 198512 kb
Host smart-816808fc-a2cf-488f-b6fd-1b08755c0de0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716512948 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.1716512948
Directory /workspace/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.aon_timer_jump.1199472720
Short name T48
Test name
Test status
Simulation time 576599513 ps
CPU time 1.57 seconds
Started May 12 01:57:03 PM PDT 24
Finished May 12 01:57:05 PM PDT 24
Peak memory 183448 kb
Host smart-86c99526-3381-428e-bfd2-61a1e5e2b536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199472720 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.1199472720
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.2483148649
Short name T4
Test name
Test status
Simulation time 17744495633 ps
CPU time 14.27 seconds
Started May 12 01:57:05 PM PDT 24
Finished May 12 01:57:19 PM PDT 24
Peak memory 183548 kb
Host smart-f0c6e509-684f-436b-b41a-dbf61f390761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483148649 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.2483148649
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.2122422509
Short name T114
Test name
Test status
Simulation time 507627273 ps
CPU time 0.72 seconds
Started May 12 01:57:01 PM PDT 24
Finished May 12 01:57:02 PM PDT 24
Peak memory 183472 kb
Host smart-2a94cf6b-8627-49cb-90f4-356e68a433e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122422509 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.2122422509
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.242858953
Short name T10
Test name
Test status
Simulation time 230429578554 ps
CPU time 88.13 seconds
Started May 12 01:57:09 PM PDT 24
Finished May 12 01:58:37 PM PDT 24
Peak memory 194928 kb
Host smart-778ab490-4a6d-4ed2-8ca2-0a251a31c9a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242858953 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_al
l.242858953
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.2750736821
Short name T52
Test name
Test status
Simulation time 57667447610 ps
CPU time 511.43 seconds
Started May 12 01:57:05 PM PDT 24
Finished May 12 02:05:36 PM PDT 24
Peak memory 198472 kb
Host smart-5479ca08-1a19-446b-bd03-fc397348fb70
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750736821 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.2750736821
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.aon_timer_jump.3595161122
Short name T205
Test name
Test status
Simulation time 497170921 ps
CPU time 1.19 seconds
Started May 12 01:57:07 PM PDT 24
Finished May 12 01:57:08 PM PDT 24
Peak memory 183436 kb
Host smart-6e3de61b-6154-4074-a612-c4e5800ed129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595161122 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.3595161122
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.1179139553
Short name T258
Test name
Test status
Simulation time 41503496583 ps
CPU time 11.12 seconds
Started May 12 01:57:09 PM PDT 24
Finished May 12 01:57:21 PM PDT 24
Peak memory 183488 kb
Host smart-8661b5b2-a452-452e-81e1-1b1b6d1d9a58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179139553 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.1179139553
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.2422122963
Short name T24
Test name
Test status
Simulation time 521488881 ps
CPU time 0.72 seconds
Started May 12 01:57:08 PM PDT 24
Finished May 12 01:57:09 PM PDT 24
Peak memory 183484 kb
Host smart-000297e2-bc85-439e-8eb8-2a2515ca236e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422122963 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.2422122963
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.2953545878
Short name T270
Test name
Test status
Simulation time 338566172296 ps
CPU time 149.01 seconds
Started May 12 01:57:09 PM PDT 24
Finished May 12 01:59:38 PM PDT 24
Peak memory 183796 kb
Host smart-0e360c53-63a6-43f1-b2ed-482af74929e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953545878 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_a
ll.2953545878
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.250377184
Short name T91
Test name
Test status
Simulation time 41788845028 ps
CPU time 276.3 seconds
Started May 12 01:57:07 PM PDT 24
Finished May 12 02:01:44 PM PDT 24
Peak memory 198404 kb
Host smart-a9644154-22ce-4821-8b0b-c093e180232f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250377184 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.250377184
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.aon_timer_jump.541335024
Short name T268
Test name
Test status
Simulation time 431702383 ps
CPU time 1.18 seconds
Started May 12 01:57:12 PM PDT 24
Finished May 12 01:57:13 PM PDT 24
Peak memory 183496 kb
Host smart-2cddd7cd-c0e6-425e-a744-69db84222e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541335024 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.541335024
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.1808864571
Short name T165
Test name
Test status
Simulation time 15323167312 ps
CPU time 23.65 seconds
Started May 12 01:57:17 PM PDT 24
Finished May 12 01:57:41 PM PDT 24
Peak memory 191992 kb
Host smart-5e06227d-1eb6-411d-80d2-f948c65ff0ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808864571 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.1808864571
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.2804479746
Short name T234
Test name
Test status
Simulation time 401624326 ps
CPU time 0.85 seconds
Started May 12 01:57:08 PM PDT 24
Finished May 12 01:57:09 PM PDT 24
Peak memory 183484 kb
Host smart-d2a86c21-01f8-4bb9-8e6e-f990ebb56956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804479746 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.2804479746
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.745596667
Short name T229
Test name
Test status
Simulation time 128791507493 ps
CPU time 93.46 seconds
Started May 12 01:57:15 PM PDT 24
Finished May 12 01:58:49 PM PDT 24
Peak memory 194780 kb
Host smart-00377d6c-308c-43cb-84d9-b83ed97a2c92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745596667 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_al
l.745596667
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.4037528358
Short name T34
Test name
Test status
Simulation time 43936457711 ps
CPU time 356.11 seconds
Started May 12 01:57:16 PM PDT 24
Finished May 12 02:03:12 PM PDT 24
Peak memory 198520 kb
Host smart-80d5c1df-c2bd-4b99-ac78-f5f20800d4fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037528358 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.4037528358
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.aon_timer_jump.1196081590
Short name T215
Test name
Test status
Simulation time 369746494 ps
CPU time 1.14 seconds
Started May 12 01:57:22 PM PDT 24
Finished May 12 01:57:23 PM PDT 24
Peak memory 183420 kb
Host smart-3abfc848-3cac-423e-9189-63875ae9021e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196081590 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.1196081590
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.2904500127
Short name T40
Test name
Test status
Simulation time 15777590165 ps
CPU time 19.78 seconds
Started May 12 01:57:18 PM PDT 24
Finished May 12 01:57:38 PM PDT 24
Peak memory 183392 kb
Host smart-eaaddd29-60a4-4683-85ea-3e1e125ed6b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904500127 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.2904500127
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.3307321140
Short name T198
Test name
Test status
Simulation time 478942050 ps
CPU time 1.21 seconds
Started May 12 01:57:19 PM PDT 24
Finished May 12 01:57:20 PM PDT 24
Peak memory 183396 kb
Host smart-c8d6c180-70dc-4067-ac88-30157f50daf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307321140 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.3307321140
Directory /workspace/9.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.25369902
Short name T16
Test name
Test status
Simulation time 115982906368 ps
CPU time 182.91 seconds
Started May 12 01:57:22 PM PDT 24
Finished May 12 02:00:25 PM PDT 24
Peak memory 183568 kb
Host smart-eeb0d821-531f-495d-930e-2588dd3bd69a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25369902 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all
.25369902
Directory /workspace/9.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.1652669623
Short name T277
Test name
Test status
Simulation time 23101989249 ps
CPU time 228.64 seconds
Started May 12 01:57:22 PM PDT 24
Finished May 12 02:01:11 PM PDT 24
Peak memory 198432 kb
Host smart-93f22740-dc68-4e5e-b98a-dee3eeafd848
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652669623 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.1652669623
Directory /workspace/9.aon_timer_stress_all_with_rand_reset/latest
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