Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
92.98 99.25 93.67 100.00 98.40 99.51 67.06


Total test records in report: 420
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T283 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.3731998411 May 14 02:07:20 PM PDT 24 May 14 02:07:22 PM PDT 24 296504854 ps
T29 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.3687687692 May 14 02:07:04 PM PDT 24 May 14 02:07:06 PM PDT 24 354082485 ps
T30 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.838962905 May 14 02:07:13 PM PDT 24 May 14 02:07:18 PM PDT 24 2298714893 ps
T50 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.2389306852 May 14 02:05:02 PM PDT 24 May 14 02:05:09 PM PDT 24 5233895953 ps
T31 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.671657740 May 14 02:07:13 PM PDT 24 May 14 02:07:15 PM PDT 24 352067014 ps
T284 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.93027624 May 14 02:07:41 PM PDT 24 May 14 02:07:44 PM PDT 24 357654780 ps
T285 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.1766454853 May 14 02:06:41 PM PDT 24 May 14 02:06:43 PM PDT 24 383022117 ps
T286 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.1710089399 May 14 02:07:41 PM PDT 24 May 14 02:07:43 PM PDT 24 406358413 ps
T61 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.3164683436 May 14 02:07:29 PM PDT 24 May 14 02:07:31 PM PDT 24 332815260 ps
T287 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.4186200773 May 14 02:07:33 PM PDT 24 May 14 02:07:35 PM PDT 24 395243356 ps
T32 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.120977414 May 14 02:04:59 PM PDT 24 May 14 02:05:04 PM PDT 24 4266723800 ps
T89 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.1214652834 May 14 02:07:33 PM PDT 24 May 14 02:07:35 PM PDT 24 452746043 ps
T62 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.610615438 May 14 02:07:30 PM PDT 24 May 14 02:07:35 PM PDT 24 2943476371 ps
T288 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.3355096938 May 14 02:07:32 PM PDT 24 May 14 02:07:35 PM PDT 24 441947527 ps
T289 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.2851365068 May 14 02:07:30 PM PDT 24 May 14 02:07:32 PM PDT 24 537371350 ps
T290 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.2965970608 May 14 02:07:05 PM PDT 24 May 14 02:07:08 PM PDT 24 360680951 ps
T51 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.3094116032 May 14 02:06:55 PM PDT 24 May 14 02:06:58 PM PDT 24 647636597 ps
T291 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.1349414070 May 14 02:06:55 PM PDT 24 May 14 02:06:57 PM PDT 24 424772751 ps
T292 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.3436609322 May 14 02:07:06 PM PDT 24 May 14 02:07:09 PM PDT 24 461223605 ps
T90 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.1347666830 May 14 02:07:24 PM PDT 24 May 14 02:07:27 PM PDT 24 618403824 ps
T293 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.1566552654 May 14 02:07:43 PM PDT 24 May 14 02:07:44 PM PDT 24 282706094 ps
T294 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.3625852008 May 14 02:07:30 PM PDT 24 May 14 02:07:31 PM PDT 24 500306344 ps
T63 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.194331710 May 14 02:07:30 PM PDT 24 May 14 02:07:32 PM PDT 24 1703477024 ps
T295 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.1741923984 May 14 02:06:40 PM PDT 24 May 14 02:06:45 PM PDT 24 7198159587 ps
T296 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.2733590568 May 14 02:05:01 PM PDT 24 May 14 02:05:03 PM PDT 24 508866910 ps
T33 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.622036188 May 14 02:07:12 PM PDT 24 May 14 02:07:17 PM PDT 24 4197782033 ps
T34 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.198251803 May 14 02:07:31 PM PDT 24 May 14 02:07:39 PM PDT 24 4452097632 ps
T297 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.2524337511 May 14 02:07:33 PM PDT 24 May 14 02:07:35 PM PDT 24 507512286 ps
T298 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.219542266 May 14 02:07:26 PM PDT 24 May 14 02:07:31 PM PDT 24 8642083646 ps
T299 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.3295165010 May 14 02:07:40 PM PDT 24 May 14 02:07:42 PM PDT 24 468532493 ps
T52 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.2222886276 May 14 02:06:56 PM PDT 24 May 14 02:06:59 PM PDT 24 440538204 ps
T300 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.1221790125 May 14 02:07:12 PM PDT 24 May 14 02:07:14 PM PDT 24 523293406 ps
T64 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.1803260465 May 14 02:05:01 PM PDT 24 May 14 02:05:04 PM PDT 24 1959109071 ps
T65 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.1759755428 May 14 02:06:45 PM PDT 24 May 14 02:06:46 PM PDT 24 322438075 ps
T66 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.1465605440 May 14 02:06:51 PM PDT 24 May 14 02:06:55 PM PDT 24 2235598369 ps
T67 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.2440841505 May 14 02:07:04 PM PDT 24 May 14 02:07:06 PM PDT 24 435054267 ps
T301 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.520817657 May 14 02:07:15 PM PDT 24 May 14 02:07:16 PM PDT 24 636467553 ps
T302 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.3014943195 May 14 02:05:00 PM PDT 24 May 14 02:05:03 PM PDT 24 316062275 ps
T303 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.2124820451 May 14 02:07:37 PM PDT 24 May 14 02:07:39 PM PDT 24 337119142 ps
T304 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.2623522908 May 14 02:07:15 PM PDT 24 May 14 02:07:17 PM PDT 24 1207533473 ps
T305 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.3089316620 May 14 02:07:23 PM PDT 24 May 14 02:07:25 PM PDT 24 593595904 ps
T306 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.469450774 May 14 02:06:53 PM PDT 24 May 14 02:06:57 PM PDT 24 356722068 ps
T307 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.2791947817 May 14 02:07:38 PM PDT 24 May 14 02:07:42 PM PDT 24 458746090 ps
T84 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.2335041904 May 14 02:07:20 PM PDT 24 May 14 02:07:23 PM PDT 24 4076534532 ps
T308 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.1414731943 May 14 02:06:55 PM PDT 24 May 14 02:06:57 PM PDT 24 294016479 ps
T53 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.1507513402 May 14 02:05:02 PM PDT 24 May 14 02:05:05 PM PDT 24 355550883 ps
T68 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.4025701831 May 14 02:07:06 PM PDT 24 May 14 02:07:09 PM PDT 24 1974808699 ps
T309 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.1758379863 May 14 02:07:22 PM PDT 24 May 14 02:07:26 PM PDT 24 8336030760 ps
T310 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.1476043323 May 14 02:07:26 PM PDT 24 May 14 02:07:28 PM PDT 24 3664055180 ps
T54 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.4223353694 May 14 02:06:40 PM PDT 24 May 14 02:06:42 PM PDT 24 1191942553 ps
T311 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.4115433395 May 14 02:07:21 PM PDT 24 May 14 02:07:24 PM PDT 24 439382345 ps
T312 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.542209497 May 14 02:07:05 PM PDT 24 May 14 02:07:09 PM PDT 24 2331072526 ps
T313 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.2710634710 May 14 02:07:22 PM PDT 24 May 14 02:07:24 PM PDT 24 887205851 ps
T314 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.57098537 May 14 02:07:32 PM PDT 24 May 14 02:07:36 PM PDT 24 580937128 ps
T315 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.2895903972 May 14 02:06:56 PM PDT 24 May 14 02:06:58 PM PDT 24 303678795 ps
T316 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.1721995458 May 14 02:07:23 PM PDT 24 May 14 02:07:29 PM PDT 24 2370354751 ps
T58 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.3581814883 May 14 02:05:00 PM PDT 24 May 14 02:05:03 PM PDT 24 310286690 ps
T317 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.3718537339 May 14 02:06:48 PM PDT 24 May 14 02:06:51 PM PDT 24 356907796 ps
T318 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.3115708087 May 14 02:07:39 PM PDT 24 May 14 02:07:42 PM PDT 24 508004990 ps
T319 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.2724953860 May 14 02:06:46 PM PDT 24 May 14 02:06:48 PM PDT 24 506148866 ps
T60 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.2092340038 May 14 02:06:46 PM PDT 24 May 14 02:06:49 PM PDT 24 975888005 ps
T59 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.2944043764 May 14 02:06:40 PM PDT 24 May 14 02:06:42 PM PDT 24 544253304 ps
T320 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.3950922097 May 14 02:07:14 PM PDT 24 May 14 02:07:18 PM PDT 24 533119881 ps
T321 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.2272868799 May 14 02:07:29 PM PDT 24 May 14 02:07:30 PM PDT 24 976051811 ps
T322 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.3648775925 May 14 02:07:15 PM PDT 24 May 14 02:07:18 PM PDT 24 4335657439 ps
T323 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.3394234643 May 14 02:07:38 PM PDT 24 May 14 02:07:40 PM PDT 24 537385788 ps
T324 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.404145494 May 14 02:07:06 PM PDT 24 May 14 02:07:10 PM PDT 24 1224155310 ps
T325 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.3194014503 May 14 02:07:32 PM PDT 24 May 14 02:07:33 PM PDT 24 519627709 ps
T326 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.1843411938 May 14 02:05:03 PM PDT 24 May 14 02:05:07 PM PDT 24 560841837 ps
T327 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.2856739035 May 14 02:07:21 PM PDT 24 May 14 02:07:24 PM PDT 24 822247885 ps
T328 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.2797941059 May 14 02:07:39 PM PDT 24 May 14 02:07:41 PM PDT 24 304156565 ps
T329 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.203060147 May 14 02:07:14 PM PDT 24 May 14 02:07:16 PM PDT 24 495295766 ps
T330 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.2926139626 May 14 02:07:30 PM PDT 24 May 14 02:07:32 PM PDT 24 413211041 ps
T331 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.3643487480 May 14 02:06:46 PM PDT 24 May 14 02:06:48 PM PDT 24 297091781 ps
T332 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.281176737 May 14 02:07:03 PM PDT 24 May 14 02:07:05 PM PDT 24 413681358 ps
T333 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.2736452627 May 14 02:06:42 PM PDT 24 May 14 02:06:43 PM PDT 24 428783657 ps
T334 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.2791071873 May 14 02:07:32 PM PDT 24 May 14 02:07:34 PM PDT 24 472177194 ps
T335 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.1969571084 May 14 02:07:38 PM PDT 24 May 14 02:07:41 PM PDT 24 339302866 ps
T336 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.3236705739 May 14 02:07:22 PM PDT 24 May 14 02:07:25 PM PDT 24 527929617 ps
T337 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.682877042 May 14 02:07:21 PM PDT 24 May 14 02:07:23 PM PDT 24 472315889 ps
T86 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.695574594 May 14 02:06:54 PM PDT 24 May 14 02:06:58 PM PDT 24 7704048248 ps
T338 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.165442883 May 14 02:06:54 PM PDT 24 May 14 02:06:56 PM PDT 24 571441338 ps
T339 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.1501293776 May 14 02:07:38 PM PDT 24 May 14 02:07:41 PM PDT 24 387795083 ps
T340 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.3785594524 May 14 02:06:47 PM PDT 24 May 14 02:06:50 PM PDT 24 637793782 ps
T87 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.2025871304 May 14 02:06:48 PM PDT 24 May 14 02:06:53 PM PDT 24 8512426014 ps
T88 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.914044580 May 14 02:07:23 PM PDT 24 May 14 02:07:39 PM PDT 24 8500440357 ps
T341 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.3825786232 May 14 02:07:33 PM PDT 24 May 14 02:07:39 PM PDT 24 8551897848 ps
T342 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.3780318514 May 14 02:07:38 PM PDT 24 May 14 02:07:40 PM PDT 24 290237024 ps
T343 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.3446620564 May 14 02:07:38 PM PDT 24 May 14 02:07:40 PM PDT 24 334907325 ps
T344 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.3856996677 May 14 02:07:21 PM PDT 24 May 14 02:07:24 PM PDT 24 474732286 ps
T345 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.1657463769 May 14 02:07:13 PM PDT 24 May 14 02:07:17 PM PDT 24 1754187256 ps
T346 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.2096887741 May 14 02:07:04 PM PDT 24 May 14 02:07:08 PM PDT 24 1276125075 ps
T347 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.3777423688 May 14 02:05:01 PM PDT 24 May 14 02:05:03 PM PDT 24 451978581 ps
T348 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.2965679646 May 14 02:07:33 PM PDT 24 May 14 02:07:35 PM PDT 24 559754322 ps
T349 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.2516284983 May 14 02:07:39 PM PDT 24 May 14 02:07:42 PM PDT 24 428709207 ps
T350 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.1752031903 May 14 02:07:32 PM PDT 24 May 14 02:07:35 PM PDT 24 1237206117 ps
T351 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.76335623 May 14 02:07:04 PM PDT 24 May 14 02:07:07 PM PDT 24 506237112 ps
T352 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.416980088 May 14 02:07:39 PM PDT 24 May 14 02:07:42 PM PDT 24 412172903 ps
T353 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.513330456 May 14 02:06:39 PM PDT 24 May 14 02:06:40 PM PDT 24 491420217 ps
T354 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.3764058675 May 14 02:06:41 PM PDT 24 May 14 02:06:46 PM PDT 24 9081675001 ps
T355 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.2028100633 May 14 02:07:14 PM PDT 24 May 14 02:07:16 PM PDT 24 389555950 ps
T356 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.2770173002 May 14 02:07:23 PM PDT 24 May 14 02:07:25 PM PDT 24 1250223111 ps
T357 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.1842256118 May 14 02:07:42 PM PDT 24 May 14 02:07:44 PM PDT 24 489393632 ps
T358 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.2230620887 May 14 02:06:51 PM PDT 24 May 14 02:06:53 PM PDT 24 2541491817 ps
T359 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.4253103428 May 14 02:06:39 PM PDT 24 May 14 02:06:43 PM PDT 24 2262035569 ps
T55 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.1196913752 May 14 02:06:38 PM PDT 24 May 14 02:06:41 PM PDT 24 672010942 ps
T360 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.1410140099 May 14 02:05:01 PM PDT 24 May 14 02:05:03 PM PDT 24 656871302 ps
T361 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.2105751368 May 14 02:06:55 PM PDT 24 May 14 02:06:58 PM PDT 24 439161117 ps
T362 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.4290748434 May 14 02:06:45 PM PDT 24 May 14 02:07:06 PM PDT 24 7033283121 ps
T363 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.3970984003 May 14 02:07:05 PM PDT 24 May 14 02:07:07 PM PDT 24 459131373 ps
T364 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.2193489840 May 14 02:07:28 PM PDT 24 May 14 02:07:29 PM PDT 24 451843587 ps
T365 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.1433150982 May 14 02:07:30 PM PDT 24 May 14 02:07:36 PM PDT 24 8536888235 ps
T366 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.3361085207 May 14 02:07:39 PM PDT 24 May 14 02:07:42 PM PDT 24 394148101 ps
T367 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.4021507238 May 14 02:06:41 PM PDT 24 May 14 02:06:43 PM PDT 24 401442464 ps
T368 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.2730541597 May 14 02:06:53 PM PDT 24 May 14 02:06:54 PM PDT 24 408586269 ps
T369 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.1617809033 May 14 02:05:02 PM PDT 24 May 14 02:05:04 PM PDT 24 319832580 ps
T370 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.148765377 May 14 02:07:43 PM PDT 24 May 14 02:07:44 PM PDT 24 348342841 ps
T85 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.3569309406 May 14 02:06:47 PM PDT 24 May 14 02:06:56 PM PDT 24 8106290435 ps
T371 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.3183494968 May 14 02:05:00 PM PDT 24 May 14 02:05:03 PM PDT 24 314670069 ps
T372 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.2349638401 May 14 02:06:48 PM PDT 24 May 14 02:06:50 PM PDT 24 336781069 ps
T373 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.1802642042 May 14 02:06:55 PM PDT 24 May 14 02:07:00 PM PDT 24 2197951707 ps
T374 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.2093189276 May 14 02:07:22 PM PDT 24 May 14 02:07:24 PM PDT 24 521620229 ps
T375 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.2779022421 May 14 02:07:22 PM PDT 24 May 14 02:07:25 PM PDT 24 359138216 ps
T376 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.3200681384 May 14 02:07:43 PM PDT 24 May 14 02:07:45 PM PDT 24 396038886 ps
T377 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.1108990708 May 14 02:06:54 PM PDT 24 May 14 02:06:57 PM PDT 24 505893603 ps
T56 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.922584346 May 14 02:06:40 PM PDT 24 May 14 02:06:43 PM PDT 24 465195609 ps
T378 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.2201018108 May 14 02:07:04 PM PDT 24 May 14 02:07:07 PM PDT 24 477126076 ps
T379 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.3258431565 May 14 02:06:39 PM PDT 24 May 14 02:06:43 PM PDT 24 500415646 ps
T380 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.302850881 May 14 02:06:51 PM PDT 24 May 14 02:06:53 PM PDT 24 434598069 ps
T381 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.2415911349 May 14 02:06:55 PM PDT 24 May 14 02:06:57 PM PDT 24 395324610 ps
T382 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.3895785633 May 14 02:06:55 PM PDT 24 May 14 02:06:57 PM PDT 24 806802427 ps
T383 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.102319935 May 14 02:07:23 PM PDT 24 May 14 02:07:28 PM PDT 24 492914389 ps
T384 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.2745251589 May 14 02:07:06 PM PDT 24 May 14 02:07:14 PM PDT 24 4388399844 ps
T385 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.1671161850 May 14 02:07:31 PM PDT 24 May 14 02:07:35 PM PDT 24 850627419 ps
T386 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.3758695238 May 14 02:06:55 PM PDT 24 May 14 02:06:58 PM PDT 24 8753105874 ps
T387 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.3485692677 May 14 02:05:04 PM PDT 24 May 14 02:05:13 PM PDT 24 4208385231 ps
T388 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.3041258660 May 14 02:07:05 PM PDT 24 May 14 02:07:07 PM PDT 24 564103527 ps
T389 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.3239243413 May 14 02:07:30 PM PDT 24 May 14 02:07:32 PM PDT 24 369521235 ps
T390 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.4169950318 May 14 02:07:40 PM PDT 24 May 14 02:07:43 PM PDT 24 482929600 ps
T391 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.117786622 May 14 02:06:55 PM PDT 24 May 14 02:06:57 PM PDT 24 409788636 ps
T392 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.2462432756 May 14 02:07:04 PM PDT 24 May 14 02:07:06 PM PDT 24 514955438 ps
T393 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.2090149711 May 14 02:06:39 PM PDT 24 May 14 02:06:41 PM PDT 24 581571529 ps
T394 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.3363731267 May 14 02:07:22 PM PDT 24 May 14 02:07:28 PM PDT 24 4063617864 ps
T395 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.2441990979 May 14 02:07:39 PM PDT 24 May 14 02:07:42 PM PDT 24 508019833 ps
T396 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.1735197309 May 14 02:06:40 PM PDT 24 May 14 02:06:42 PM PDT 24 367868445 ps
T397 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.896431415 May 14 02:07:43 PM PDT 24 May 14 02:07:45 PM PDT 24 393419397 ps
T398 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.3551648059 May 14 02:07:39 PM PDT 24 May 14 02:07:41 PM PDT 24 416847840 ps
T399 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.3376982087 May 14 02:07:39 PM PDT 24 May 14 02:07:42 PM PDT 24 401891333 ps
T400 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.2260532098 May 14 02:07:38 PM PDT 24 May 14 02:07:41 PM PDT 24 504356353 ps
T401 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.3907394711 May 14 02:07:05 PM PDT 24 May 14 02:07:11 PM PDT 24 7956164087 ps
T57 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.3864648689 May 14 02:06:40 PM PDT 24 May 14 02:06:43 PM PDT 24 613061691 ps
T402 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.81948767 May 14 02:06:56 PM PDT 24 May 14 02:07:04 PM PDT 24 2552790477 ps
T403 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.1673635946 May 14 02:06:45 PM PDT 24 May 14 02:06:47 PM PDT 24 536771649 ps
T404 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.3468686805 May 14 02:07:39 PM PDT 24 May 14 02:07:43 PM PDT 24 450888720 ps
T405 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.3179521575 May 14 02:05:02 PM PDT 24 May 14 02:05:04 PM PDT 24 333177242 ps
T406 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.1517468783 May 14 02:06:51 PM PDT 24 May 14 02:06:52 PM PDT 24 290231843 ps
T407 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.2972179885 May 14 02:07:22 PM PDT 24 May 14 02:07:25 PM PDT 24 500897046 ps
T408 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.1346036737 May 14 02:07:04 PM PDT 24 May 14 02:07:06 PM PDT 24 320516154 ps
T409 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.2020246051 May 14 02:06:40 PM PDT 24 May 14 02:06:42 PM PDT 24 297802981 ps
T410 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.967182933 May 14 02:07:26 PM PDT 24 May 14 02:07:29 PM PDT 24 379300720 ps
T411 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.3904579223 May 14 02:07:38 PM PDT 24 May 14 02:07:42 PM PDT 24 482146549 ps
T412 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.798156224 May 14 02:07:33 PM PDT 24 May 14 02:07:34 PM PDT 24 390334478 ps
T413 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.4238469456 May 14 02:07:04 PM PDT 24 May 14 02:07:09 PM PDT 24 8260429396 ps
T414 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.1674145936 May 14 02:06:48 PM PDT 24 May 14 02:06:50 PM PDT 24 467148073 ps
T415 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.3811209411 May 14 02:07:22 PM PDT 24 May 14 02:07:25 PM PDT 24 555583769 ps
T416 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.2634953361 May 14 02:06:54 PM PDT 24 May 14 02:06:57 PM PDT 24 518397254 ps
T417 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.3593286809 May 14 02:07:23 PM PDT 24 May 14 02:07:26 PM PDT 24 511417528 ps
T418 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.2998943462 May 14 02:07:21 PM PDT 24 May 14 02:07:23 PM PDT 24 405493552 ps
T419 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.81647886 May 14 02:07:21 PM PDT 24 May 14 02:07:23 PM PDT 24 410173844 ps
T420 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.3496706605 May 14 02:07:06 PM PDT 24 May 14 02:07:10 PM PDT 24 481367937 ps

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.3054648585
Short name T10
Test name
Test status
Simulation time 50410997036 ps
CPU time 562.51 seconds
Started May 14 04:17:16 PM PDT 24
Finished May 14 04:26:40 PM PDT 24
Peak memory 198472 kb
Host smart-1ddab65a-1758-4684-b598-0b27059e1352
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054648585 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.3054648585
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.2234210590
Short name T3
Test name
Test status
Simulation time 69383085272 ps
CPU time 494.82 seconds
Started May 14 04:17:27 PM PDT 24
Finished May 14 04:25:43 PM PDT 24
Peak memory 198528 kb
Host smart-298f2737-5af8-4fd9-a2fd-ce0c24f1e696
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234210590 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.2234210590
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.120977414
Short name T32
Test name
Test status
Simulation time 4266723800 ps
CPU time 3.48 seconds
Started May 14 02:04:59 PM PDT 24
Finished May 14 02:05:04 PM PDT 24
Peak memory 197716 kb
Host smart-d9a5aebb-1c37-4e3f-858c-114a71408461
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120977414 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_
intg_err.120977414
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.1897360383
Short name T16
Test name
Test status
Simulation time 4477469287 ps
CPU time 8.29 seconds
Started May 14 04:16:11 PM PDT 24
Finished May 14 04:16:22 PM PDT 24
Peak memory 215596 kb
Host smart-4963931f-a365-4f5a-bca8-d2ffa91b8bbc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897360383 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.1897360383
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.2732174350
Short name T6
Test name
Test status
Simulation time 274410077526 ps
CPU time 169.19 seconds
Started May 14 04:17:16 PM PDT 24
Finished May 14 04:20:07 PM PDT 24
Peak memory 183784 kb
Host smart-91f5376d-790e-48e0-b352-a8aa9bb54dea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732174350 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_
all.2732174350
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.1614589498
Short name T37
Test name
Test status
Simulation time 110389519517 ps
CPU time 198.67 seconds
Started May 14 04:17:04 PM PDT 24
Finished May 14 04:20:28 PM PDT 24
Peak memory 198484 kb
Host smart-77271f3e-0904-494b-b4b5-34826a081488
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614589498 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.1614589498
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.3569309406
Short name T85
Test name
Test status
Simulation time 8106290435 ps
CPU time 7.36 seconds
Started May 14 02:06:47 PM PDT 24
Finished May 14 02:06:56 PM PDT 24
Peak memory 198060 kb
Host smart-48ab07fb-6d0f-46ea-8ca4-f0c409cdb01a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569309406 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl
_intg_err.3569309406
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.3581814883
Short name T58
Test name
Test status
Simulation time 310286690 ps
CPU time 1.14 seconds
Started May 14 02:05:00 PM PDT 24
Finished May 14 02:05:03 PM PDT 24
Peak memory 183748 kb
Host smart-4cc98fe4-748c-413b-944e-53d03fa50c31
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581814883 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_a
liasing.3581814883
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.1803260465
Short name T64
Test name
Test status
Simulation time 1959109071 ps
CPU time 1.46 seconds
Started May 14 02:05:01 PM PDT 24
Finished May 14 02:05:04 PM PDT 24
Peak memory 194316 kb
Host smart-52f9560e-31eb-439c-b083-c67c62cb5570
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803260465 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon
_timer_same_csr_outstanding.1803260465
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.2389306852
Short name T50
Test name
Test status
Simulation time 5233895953 ps
CPU time 4.9 seconds
Started May 14 02:05:02 PM PDT 24
Finished May 14 02:05:09 PM PDT 24
Peak memory 192284 kb
Host smart-e73b5273-6899-4a2a-b208-d882d9038ccd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389306852 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_b
it_bash.2389306852
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.1410140099
Short name T360
Test name
Test status
Simulation time 656871302 ps
CPU time 0.69 seconds
Started May 14 02:05:01 PM PDT 24
Finished May 14 02:05:03 PM PDT 24
Peak memory 183804 kb
Host smart-ec03da33-71d5-4358-8a2f-e0261b8d1f81
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410140099 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_h
w_reset.1410140099
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.2733590568
Short name T296
Test name
Test status
Simulation time 508866910 ps
CPU time 1 seconds
Started May 14 02:05:01 PM PDT 24
Finished May 14 02:05:03 PM PDT 24
Peak memory 195768 kb
Host smart-6c486b1b-607a-4f1e-af12-e708e4cce6bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733590568 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.2733590568
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.1507513402
Short name T53
Test name
Test status
Simulation time 355550883 ps
CPU time 1.16 seconds
Started May 14 02:05:02 PM PDT 24
Finished May 14 02:05:05 PM PDT 24
Peak memory 192992 kb
Host smart-fe63c462-ab93-40b5-a68d-52f8f7d4d9c1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507513402 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.1507513402
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.3179521575
Short name T405
Test name
Test status
Simulation time 333177242 ps
CPU time 0.95 seconds
Started May 14 02:05:02 PM PDT 24
Finished May 14 02:05:04 PM PDT 24
Peak memory 183668 kb
Host smart-46fa388a-e76b-488d-80c6-12ce98cf0b95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179521575 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.3179521575
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.3014943195
Short name T302
Test name
Test status
Simulation time 316062275 ps
CPU time 0.66 seconds
Started May 14 02:05:00 PM PDT 24
Finished May 14 02:05:03 PM PDT 24
Peak memory 183632 kb
Host smart-668afd79-de78-4b46-9b5f-ae563185add6
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014943195 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_t
imer_mem_partial_access.3014943195
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.3183494968
Short name T371
Test name
Test status
Simulation time 314670069 ps
CPU time 0.63 seconds
Started May 14 02:05:00 PM PDT 24
Finished May 14 02:05:03 PM PDT 24
Peak memory 183688 kb
Host smart-d92645d5-2e2d-4fb0-b677-1ea518a1427c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183494968 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_w
alk.3183494968
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.3574620415
Short name T281
Test name
Test status
Simulation time 588868373 ps
CPU time 2.08 seconds
Started May 14 02:05:00 PM PDT 24
Finished May 14 02:05:04 PM PDT 24
Peak memory 198528 kb
Host smart-64dfe805-8711-45ca-83aa-a2b64e1e5ed1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574620415 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.3574620415
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.1196913752
Short name T55
Test name
Test status
Simulation time 672010942 ps
CPU time 1.65 seconds
Started May 14 02:06:38 PM PDT 24
Finished May 14 02:06:41 PM PDT 24
Peak memory 191980 kb
Host smart-d5c8c1e7-e939-4bac-b8f7-36ccab6652fe
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196913752 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_a
liasing.1196913752
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.3864648689
Short name T57
Test name
Test status
Simulation time 613061691 ps
CPU time 2.3 seconds
Started May 14 02:06:40 PM PDT 24
Finished May 14 02:06:43 PM PDT 24
Peak memory 192172 kb
Host smart-76cb9c1a-7c1d-4835-995e-369670b72e58
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864648689 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_b
it_bash.3864648689
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.2090149711
Short name T393
Test name
Test status
Simulation time 581571529 ps
CPU time 1.04 seconds
Started May 14 02:06:39 PM PDT 24
Finished May 14 02:06:41 PM PDT 24
Peak memory 183744 kb
Host smart-38b307be-999f-4bd7-84c1-4b88d5772720
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090149711 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_h
w_reset.2090149711
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.513330456
Short name T353
Test name
Test status
Simulation time 491420217 ps
CPU time 0.96 seconds
Started May 14 02:06:39 PM PDT 24
Finished May 14 02:06:40 PM PDT 24
Peak memory 196992 kb
Host smart-3bf624f3-3306-404e-ae57-b9a21b7124ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513330456 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.513330456
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.922584346
Short name T56
Test name
Test status
Simulation time 465195609 ps
CPU time 1.41 seconds
Started May 14 02:06:40 PM PDT 24
Finished May 14 02:06:43 PM PDT 24
Peak memory 184028 kb
Host smart-47a8a12e-750f-4180-a189-5d3cc252a7b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922584346 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.922584346
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.3777423688
Short name T347
Test name
Test status
Simulation time 451978581 ps
CPU time 0.65 seconds
Started May 14 02:05:01 PM PDT 24
Finished May 14 02:05:03 PM PDT 24
Peak memory 183676 kb
Host smart-b502e298-bce0-4842-ae23-4d29f2c6d0a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777423688 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.3777423688
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.2736452627
Short name T333
Test name
Test status
Simulation time 428783657 ps
CPU time 1.12 seconds
Started May 14 02:06:42 PM PDT 24
Finished May 14 02:06:43 PM PDT 24
Peak memory 183596 kb
Host smart-4da4aedc-f2fd-48cc-8060-1640bccc38bd
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736452627 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_t
imer_mem_partial_access.2736452627
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.1617809033
Short name T369
Test name
Test status
Simulation time 319832580 ps
CPU time 0.91 seconds
Started May 14 02:05:02 PM PDT 24
Finished May 14 02:05:04 PM PDT 24
Peak memory 183620 kb
Host smart-6b2ee771-748e-4abf-90c9-c2171cfc10db
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617809033 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_w
alk.1617809033
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.4253103428
Short name T359
Test name
Test status
Simulation time 2262035569 ps
CPU time 2.14 seconds
Started May 14 02:06:39 PM PDT 24
Finished May 14 02:06:43 PM PDT 24
Peak memory 184060 kb
Host smart-51db0c39-abe5-4457-a45e-952a50dfe0d0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253103428 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon
_timer_same_csr_outstanding.4253103428
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.1843411938
Short name T326
Test name
Test status
Simulation time 560841837 ps
CPU time 2.89 seconds
Started May 14 02:05:03 PM PDT 24
Finished May 14 02:05:07 PM PDT 24
Peak memory 198632 kb
Host smart-dde47a12-daa6-4eba-b163-1ae8ecefbc8d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843411938 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.1843411938
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.3485692677
Short name T387
Test name
Test status
Simulation time 4208385231 ps
CPU time 7.83 seconds
Started May 14 02:05:04 PM PDT 24
Finished May 14 02:05:13 PM PDT 24
Peak memory 197612 kb
Host smart-9167e7e3-80b3-4210-8d8d-c3e1b8c164cb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485692677 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl
_intg_err.3485692677
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.520817657
Short name T301
Test name
Test status
Simulation time 636467553 ps
CPU time 1.12 seconds
Started May 14 02:07:15 PM PDT 24
Finished May 14 02:07:16 PM PDT 24
Peak memory 198356 kb
Host smart-ec6482ac-fdc3-4e41-a5ac-935af1d237a9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520817657 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.520817657
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.671657740
Short name T31
Test name
Test status
Simulation time 352067014 ps
CPU time 0.84 seconds
Started May 14 02:07:13 PM PDT 24
Finished May 14 02:07:15 PM PDT 24
Peak memory 193192 kb
Host smart-9d7bcd8e-b281-4501-a237-fb5ee339f587
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671657740 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.671657740
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.203060147
Short name T329
Test name
Test status
Simulation time 495295766 ps
CPU time 0.72 seconds
Started May 14 02:07:14 PM PDT 24
Finished May 14 02:07:16 PM PDT 24
Peak memory 183696 kb
Host smart-4c7264c9-b48b-4bb5-8a69-f40f3275f3e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203060147 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.203060147
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.838962905
Short name T30
Test name
Test status
Simulation time 2298714893 ps
CPU time 3.77 seconds
Started May 14 02:07:13 PM PDT 24
Finished May 14 02:07:18 PM PDT 24
Peak memory 183924 kb
Host smart-0feb4104-0383-4bc4-9b9e-07db7836b131
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838962905 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon
_timer_same_csr_outstanding.838962905
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.3950922097
Short name T320
Test name
Test status
Simulation time 533119881 ps
CPU time 3.29 seconds
Started May 14 02:07:14 PM PDT 24
Finished May 14 02:07:18 PM PDT 24
Peak memory 198628 kb
Host smart-df964619-9c76-4440-9fed-090cbb7e2b3a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950922097 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.3950922097
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.622036188
Short name T33
Test name
Test status
Simulation time 4197782033 ps
CPU time 4.18 seconds
Started May 14 02:07:12 PM PDT 24
Finished May 14 02:07:17 PM PDT 24
Peak memory 197704 kb
Host smart-d4840986-3a9f-4c8b-994a-d60210aab09a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622036188 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl
_intg_err.622036188
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.1221790125
Short name T300
Test name
Test status
Simulation time 523293406 ps
CPU time 1.44 seconds
Started May 14 02:07:12 PM PDT 24
Finished May 14 02:07:14 PM PDT 24
Peak memory 195344 kb
Host smart-86c2b4ee-ea31-455c-8d49-69c89260d236
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221790125 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.1221790125
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.2028100633
Short name T355
Test name
Test status
Simulation time 389555950 ps
CPU time 1.27 seconds
Started May 14 02:07:14 PM PDT 24
Finished May 14 02:07:16 PM PDT 24
Peak memory 193092 kb
Host smart-510e17c7-a0c8-4878-9952-8c3bc4f13e60
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028100633 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.2028100633
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.682877042
Short name T337
Test name
Test status
Simulation time 472315889 ps
CPU time 0.88 seconds
Started May 14 02:07:21 PM PDT 24
Finished May 14 02:07:23 PM PDT 24
Peak memory 183708 kb
Host smart-afc6c1b3-4082-41fe-8de8-367a1a6a5c1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682877042 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.682877042
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.1657463769
Short name T345
Test name
Test status
Simulation time 1754187256 ps
CPU time 2.71 seconds
Started May 14 02:07:13 PM PDT 24
Finished May 14 02:07:17 PM PDT 24
Peak memory 193408 kb
Host smart-a64e4352-71fd-4f18-9b5b-bec5112f49ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657463769 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.ao
n_timer_same_csr_outstanding.1657463769
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.2623522908
Short name T304
Test name
Test status
Simulation time 1207533473 ps
CPU time 1.35 seconds
Started May 14 02:07:15 PM PDT 24
Finished May 14 02:07:17 PM PDT 24
Peak memory 198596 kb
Host smart-b54ba8b4-1789-47f2-81da-64c9719dff3b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623522908 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.2623522908
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.3648775925
Short name T322
Test name
Test status
Simulation time 4335657439 ps
CPU time 2.02 seconds
Started May 14 02:07:15 PM PDT 24
Finished May 14 02:07:18 PM PDT 24
Peak memory 196596 kb
Host smart-7a687fb9-d805-4fda-9ca3-8430f0cb0eb1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648775925 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_t
l_intg_err.3648775925
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.1347666830
Short name T90
Test name
Test status
Simulation time 618403824 ps
CPU time 1.26 seconds
Started May 14 02:07:24 PM PDT 24
Finished May 14 02:07:27 PM PDT 24
Peak memory 196472 kb
Host smart-5db123a8-8e7e-4cde-a4fe-f0026c58866f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347666830 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.1347666830
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.81647886
Short name T419
Test name
Test status
Simulation time 410173844 ps
CPU time 1.27 seconds
Started May 14 02:07:21 PM PDT 24
Finished May 14 02:07:23 PM PDT 24
Peak memory 193112 kb
Host smart-a23a041b-ea1e-4ab7-a717-307f134d5cc5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81647886 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.81647886
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.2972179885
Short name T407
Test name
Test status
Simulation time 500897046 ps
CPU time 1.19 seconds
Started May 14 02:07:22 PM PDT 24
Finished May 14 02:07:25 PM PDT 24
Peak memory 183588 kb
Host smart-e955f902-b63d-4b0a-8829-267c0fe77780
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972179885 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.2972179885
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.1721995458
Short name T316
Test name
Test status
Simulation time 2370354751 ps
CPU time 3.72 seconds
Started May 14 02:07:23 PM PDT 24
Finished May 14 02:07:29 PM PDT 24
Peak memory 193728 kb
Host smart-e2442f34-45b8-4ae1-a083-8fc82d577cbb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721995458 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.ao
n_timer_same_csr_outstanding.1721995458
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.102319935
Short name T383
Test name
Test status
Simulation time 492914389 ps
CPU time 2.58 seconds
Started May 14 02:07:23 PM PDT 24
Finished May 14 02:07:28 PM PDT 24
Peak memory 198504 kb
Host smart-02fd8c06-f8f9-459f-83f9-fa5bb6555a6a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102319935 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.102319935
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.2335041904
Short name T84
Test name
Test status
Simulation time 4076534532 ps
CPU time 2.42 seconds
Started May 14 02:07:20 PM PDT 24
Finished May 14 02:07:23 PM PDT 24
Peak memory 197556 kb
Host smart-070f2c1d-598a-4768-b907-358a8bb33f1a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335041904 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_t
l_intg_err.2335041904
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.3236705739
Short name T336
Test name
Test status
Simulation time 527929617 ps
CPU time 1.33 seconds
Started May 14 02:07:22 PM PDT 24
Finished May 14 02:07:25 PM PDT 24
Peak memory 195516 kb
Host smart-667a76d3-fe4c-4be9-b0e4-924da3d48d2d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236705739 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.3236705739
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.3593286809
Short name T417
Test name
Test status
Simulation time 511417528 ps
CPU time 0.8 seconds
Started May 14 02:07:23 PM PDT 24
Finished May 14 02:07:26 PM PDT 24
Peak memory 193220 kb
Host smart-137fb286-b8f5-47a5-a982-3f3fb2955b8a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593286809 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.3593286809
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.2998943462
Short name T418
Test name
Test status
Simulation time 405493552 ps
CPU time 0.81 seconds
Started May 14 02:07:21 PM PDT 24
Finished May 14 02:07:23 PM PDT 24
Peak memory 183672 kb
Host smart-1b145a10-ada2-4f85-b68a-db4ea940a726
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998943462 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.2998943462
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.2770173002
Short name T356
Test name
Test status
Simulation time 1250223111 ps
CPU time 1.06 seconds
Started May 14 02:07:23 PM PDT 24
Finished May 14 02:07:25 PM PDT 24
Peak memory 183844 kb
Host smart-9012e3dd-fed8-4e0a-8f82-69ef8d0813b9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770173002 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.ao
n_timer_same_csr_outstanding.2770173002
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.2856739035
Short name T327
Test name
Test status
Simulation time 822247885 ps
CPU time 1.4 seconds
Started May 14 02:07:21 PM PDT 24
Finished May 14 02:07:24 PM PDT 24
Peak memory 198528 kb
Host smart-c8ec1208-fc19-4083-b364-c8085d838542
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856739035 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.2856739035
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.1758379863
Short name T309
Test name
Test status
Simulation time 8336030760 ps
CPU time 2.46 seconds
Started May 14 02:07:22 PM PDT 24
Finished May 14 02:07:26 PM PDT 24
Peak memory 197972 kb
Host smart-a50daa2f-3426-4066-bed3-5cff389548c2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758379863 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_t
l_intg_err.1758379863
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.1628270976
Short name T28
Test name
Test status
Simulation time 393139993 ps
CPU time 1.19 seconds
Started May 14 02:07:24 PM PDT 24
Finished May 14 02:07:27 PM PDT 24
Peak memory 195944 kb
Host smart-ba6a3add-8adc-4373-854c-5ee1fa77ff77
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628270976 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.1628270976
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.3089316620
Short name T305
Test name
Test status
Simulation time 593595904 ps
CPU time 0.61 seconds
Started May 14 02:07:23 PM PDT 24
Finished May 14 02:07:25 PM PDT 24
Peak memory 183712 kb
Host smart-f0c97f74-914e-4156-b0a1-b936bc0264b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089316620 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.3089316620
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.4115433395
Short name T311
Test name
Test status
Simulation time 439382345 ps
CPU time 0.64 seconds
Started May 14 02:07:21 PM PDT 24
Finished May 14 02:07:24 PM PDT 24
Peak memory 183724 kb
Host smart-1924255e-23cb-4e85-81bb-028043b7aeea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115433395 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.4115433395
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.2710634710
Short name T313
Test name
Test status
Simulation time 887205851 ps
CPU time 0.99 seconds
Started May 14 02:07:22 PM PDT 24
Finished May 14 02:07:24 PM PDT 24
Peak memory 183900 kb
Host smart-47659fd6-bbde-42f4-bf65-b62074decc4b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710634710 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao
n_timer_same_csr_outstanding.2710634710
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.967182933
Short name T410
Test name
Test status
Simulation time 379300720 ps
CPU time 2.29 seconds
Started May 14 02:07:26 PM PDT 24
Finished May 14 02:07:29 PM PDT 24
Peak memory 198612 kb
Host smart-15b14942-1eb6-4f89-a7fb-6d1b87bcb237
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967182933 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.967182933
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.219542266
Short name T298
Test name
Test status
Simulation time 8642083646 ps
CPU time 4.07 seconds
Started May 14 02:07:26 PM PDT 24
Finished May 14 02:07:31 PM PDT 24
Peak memory 198016 kb
Host smart-261d5917-8c79-4eba-8fc0-ddb449fff138
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219542266 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl
_intg_err.219542266
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.3811209411
Short name T415
Test name
Test status
Simulation time 555583769 ps
CPU time 1.38 seconds
Started May 14 02:07:22 PM PDT 24
Finished May 14 02:07:25 PM PDT 24
Peak memory 196072 kb
Host smart-08ef777c-62bc-4582-a4ab-d8d0b84f4e60
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811209411 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.3811209411
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.2093189276
Short name T374
Test name
Test status
Simulation time 521620229 ps
CPU time 0.99 seconds
Started May 14 02:07:22 PM PDT 24
Finished May 14 02:07:24 PM PDT 24
Peak memory 183748 kb
Host smart-657b6d26-f76a-458f-b245-040e39b89ea6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093189276 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.2093189276
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.3731998411
Short name T283
Test name
Test status
Simulation time 296504854 ps
CPU time 0.92 seconds
Started May 14 02:07:20 PM PDT 24
Finished May 14 02:07:22 PM PDT 24
Peak memory 183680 kb
Host smart-26a497ac-b805-4329-819d-bca8a4dd178d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731998411 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.3731998411
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.1476043323
Short name T310
Test name
Test status
Simulation time 3664055180 ps
CPU time 1.38 seconds
Started May 14 02:07:26 PM PDT 24
Finished May 14 02:07:28 PM PDT 24
Peak memory 183876 kb
Host smart-5dd01a53-9094-48a9-89ae-a992f171005a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476043323 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.ao
n_timer_same_csr_outstanding.1476043323
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.2097348573
Short name T279
Test name
Test status
Simulation time 485397340 ps
CPU time 2.61 seconds
Started May 14 02:07:23 PM PDT 24
Finished May 14 02:07:27 PM PDT 24
Peak memory 198564 kb
Host smart-f47916db-1783-415a-b187-a2237be90e5e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097348573 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.2097348573
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.914044580
Short name T88
Test name
Test status
Simulation time 8500440357 ps
CPU time 14.32 seconds
Started May 14 02:07:23 PM PDT 24
Finished May 14 02:07:39 PM PDT 24
Peak memory 197900 kb
Host smart-23cb13e4-0075-4e7e-8429-6d7818a85db3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914044580 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl
_intg_err.914044580
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.2193489840
Short name T364
Test name
Test status
Simulation time 451843587 ps
CPU time 0.82 seconds
Started May 14 02:07:28 PM PDT 24
Finished May 14 02:07:29 PM PDT 24
Peak memory 195956 kb
Host smart-cc3675d2-66ff-4a2a-88f6-b9c146f78c2c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193489840 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.2193489840
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.3856996677
Short name T344
Test name
Test status
Simulation time 474732286 ps
CPU time 1.36 seconds
Started May 14 02:07:21 PM PDT 24
Finished May 14 02:07:24 PM PDT 24
Peak memory 183748 kb
Host smart-6ed8f86d-1cc9-41c4-8d77-d2b4df3cba47
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856996677 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.3856996677
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.2779022421
Short name T375
Test name
Test status
Simulation time 359138216 ps
CPU time 0.92 seconds
Started May 14 02:07:22 PM PDT 24
Finished May 14 02:07:25 PM PDT 24
Peak memory 183688 kb
Host smart-23685dfd-c50e-43cb-ac6f-c21c27ddf38d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779022421 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.2779022421
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.2272868799
Short name T321
Test name
Test status
Simulation time 976051811 ps
CPU time 0.67 seconds
Started May 14 02:07:29 PM PDT 24
Finished May 14 02:07:30 PM PDT 24
Peak memory 193288 kb
Host smart-aa370894-b31c-4222-9aa7-5a3a4711da8c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272868799 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.ao
n_timer_same_csr_outstanding.2272868799
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.2330423639
Short name T280
Test name
Test status
Simulation time 1053940577 ps
CPU time 1.22 seconds
Started May 14 02:07:23 PM PDT 24
Finished May 14 02:07:26 PM PDT 24
Peak memory 198476 kb
Host smart-2f2a3497-b381-4a85-a208-a23cfb42e1a1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330423639 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.2330423639
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.3363731267
Short name T394
Test name
Test status
Simulation time 4063617864 ps
CPU time 4.2 seconds
Started May 14 02:07:22 PM PDT 24
Finished May 14 02:07:28 PM PDT 24
Peak memory 197368 kb
Host smart-94c47613-a791-485d-9d6c-d6bc1a432852
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363731267 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_t
l_intg_err.3363731267
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.3355096938
Short name T288
Test name
Test status
Simulation time 441947527 ps
CPU time 1.34 seconds
Started May 14 02:07:32 PM PDT 24
Finished May 14 02:07:35 PM PDT 24
Peak memory 196872 kb
Host smart-464c0dbd-d11b-47e1-8abc-589ab8ac2b38
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355096938 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.3355096938
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.3164683436
Short name T61
Test name
Test status
Simulation time 332815260 ps
CPU time 0.69 seconds
Started May 14 02:07:29 PM PDT 24
Finished May 14 02:07:31 PM PDT 24
Peak memory 183708 kb
Host smart-c7065a1f-ed6f-4730-b292-9382dbaabb5d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164683436 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.3164683436
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.798156224
Short name T412
Test name
Test status
Simulation time 390334478 ps
CPU time 0.67 seconds
Started May 14 02:07:33 PM PDT 24
Finished May 14 02:07:34 PM PDT 24
Peak memory 183672 kb
Host smart-8829ac5b-5913-4234-9786-e06234446871
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798156224 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.798156224
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.610615438
Short name T62
Test name
Test status
Simulation time 2943476371 ps
CPU time 3.78 seconds
Started May 14 02:07:30 PM PDT 24
Finished May 14 02:07:35 PM PDT 24
Peak memory 194700 kb
Host smart-eec6d294-69d6-4fdc-8816-5f84568dec53
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610615438 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon
_timer_same_csr_outstanding.610615438
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.2965679646
Short name T348
Test name
Test status
Simulation time 559754322 ps
CPU time 1.37 seconds
Started May 14 02:07:33 PM PDT 24
Finished May 14 02:07:35 PM PDT 24
Peak memory 198616 kb
Host smart-7b2d39e9-e1e2-4c60-94ba-59f3762f85d8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965679646 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.2965679646
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.198251803
Short name T34
Test name
Test status
Simulation time 4452097632 ps
CPU time 7.77 seconds
Started May 14 02:07:31 PM PDT 24
Finished May 14 02:07:39 PM PDT 24
Peak memory 197596 kb
Host smart-77bffb47-421b-4ebb-b254-55fc213541fa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198251803 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl
_intg_err.198251803
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.2791071873
Short name T334
Test name
Test status
Simulation time 472177194 ps
CPU time 0.93 seconds
Started May 14 02:07:32 PM PDT 24
Finished May 14 02:07:34 PM PDT 24
Peak memory 194852 kb
Host smart-8e4a3c40-ce68-4b3a-b1c7-fe48f80a4834
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791071873 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.2791071873
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.1214652834
Short name T89
Test name
Test status
Simulation time 452746043 ps
CPU time 1.18 seconds
Started May 14 02:07:33 PM PDT 24
Finished May 14 02:07:35 PM PDT 24
Peak memory 193084 kb
Host smart-76ab0052-0e0f-403a-bf3e-123d6af64fa9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214652834 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.1214652834
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.2524337511
Short name T297
Test name
Test status
Simulation time 507512286 ps
CPU time 1.32 seconds
Started May 14 02:07:33 PM PDT 24
Finished May 14 02:07:35 PM PDT 24
Peak memory 183700 kb
Host smart-e88ccc32-6cda-4419-b2d5-399060e593aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524337511 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.2524337511
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.194331710
Short name T63
Test name
Test status
Simulation time 1703477024 ps
CPU time 0.88 seconds
Started May 14 02:07:30 PM PDT 24
Finished May 14 02:07:32 PM PDT 24
Peak memory 193680 kb
Host smart-29577df4-74f9-4522-bb73-6bda6c2b70d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194331710 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon
_timer_same_csr_outstanding.194331710
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.1671161850
Short name T385
Test name
Test status
Simulation time 850627419 ps
CPU time 2.27 seconds
Started May 14 02:07:31 PM PDT 24
Finished May 14 02:07:35 PM PDT 24
Peak memory 198588 kb
Host smart-44900204-d5f6-4f02-8503-7c37771d4ee3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671161850 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.1671161850
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.3825786232
Short name T341
Test name
Test status
Simulation time 8551897848 ps
CPU time 4.67 seconds
Started May 14 02:07:33 PM PDT 24
Finished May 14 02:07:39 PM PDT 24
Peak memory 197932 kb
Host smart-de7528d9-3e73-40ad-8c46-69050e387c41
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825786232 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_t
l_intg_err.3825786232
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.2851365068
Short name T289
Test name
Test status
Simulation time 537371350 ps
CPU time 0.9 seconds
Started May 14 02:07:30 PM PDT 24
Finished May 14 02:07:32 PM PDT 24
Peak memory 196524 kb
Host smart-4606f298-b550-4385-9685-bc70906de6c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851365068 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.2851365068
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.3194014503
Short name T325
Test name
Test status
Simulation time 519627709 ps
CPU time 0.8 seconds
Started May 14 02:07:32 PM PDT 24
Finished May 14 02:07:33 PM PDT 24
Peak memory 193256 kb
Host smart-a936c040-5fdc-45af-8ab5-6eeb7e6f0b2f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194014503 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.3194014503
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.4186200773
Short name T287
Test name
Test status
Simulation time 395243356 ps
CPU time 1.08 seconds
Started May 14 02:07:33 PM PDT 24
Finished May 14 02:07:35 PM PDT 24
Peak memory 183728 kb
Host smart-1b92f45d-ed20-48c7-8a5d-950fc1dbfd73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186200773 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.4186200773
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.1752031903
Short name T350
Test name
Test status
Simulation time 1237206117 ps
CPU time 1.66 seconds
Started May 14 02:07:32 PM PDT 24
Finished May 14 02:07:35 PM PDT 24
Peak memory 193760 kb
Host smart-fd1bfc43-1e99-4511-8aaa-cdc44bb65222
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752031903 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao
n_timer_same_csr_outstanding.1752031903
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.57098537
Short name T314
Test name
Test status
Simulation time 580937128 ps
CPU time 2.41 seconds
Started May 14 02:07:32 PM PDT 24
Finished May 14 02:07:36 PM PDT 24
Peak memory 198560 kb
Host smart-4656bd49-f21a-4ed7-90f1-3107e82ee3b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57098537 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.57098537
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.1433150982
Short name T365
Test name
Test status
Simulation time 8536888235 ps
CPU time 4.77 seconds
Started May 14 02:07:30 PM PDT 24
Finished May 14 02:07:36 PM PDT 24
Peak memory 198108 kb
Host smart-6123fb60-f964-4c5b-9aa6-99ee22067239
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433150982 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_t
l_intg_err.1433150982
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.2944043764
Short name T59
Test name
Test status
Simulation time 544253304 ps
CPU time 0.86 seconds
Started May 14 02:06:40 PM PDT 24
Finished May 14 02:06:42 PM PDT 24
Peak memory 193296 kb
Host smart-56d0b450-5751-4011-add3-7463f5622e23
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944043764 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_a
liasing.2944043764
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.1741923984
Short name T295
Test name
Test status
Simulation time 7198159587 ps
CPU time 3.92 seconds
Started May 14 02:06:40 PM PDT 24
Finished May 14 02:06:45 PM PDT 24
Peak memory 192296 kb
Host smart-a6a55a5a-8d26-4499-9900-389106be391e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741923984 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_b
it_bash.1741923984
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.4223353694
Short name T54
Test name
Test status
Simulation time 1191942553 ps
CPU time 1.18 seconds
Started May 14 02:06:40 PM PDT 24
Finished May 14 02:06:42 PM PDT 24
Peak memory 183816 kb
Host smart-c1ed3e6f-cc76-4c39-8f2b-7755a3172a58
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223353694 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_h
w_reset.4223353694
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.1673635946
Short name T403
Test name
Test status
Simulation time 536771649 ps
CPU time 0.9 seconds
Started May 14 02:06:45 PM PDT 24
Finished May 14 02:06:47 PM PDT 24
Peak memory 196752 kb
Host smart-ca39e5f5-43c1-4c0e-afd8-2ac297e91e69
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673635946 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.1673635946
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.4021507238
Short name T367
Test name
Test status
Simulation time 401442464 ps
CPU time 0.8 seconds
Started May 14 02:06:41 PM PDT 24
Finished May 14 02:06:43 PM PDT 24
Peak memory 193020 kb
Host smart-3078ea71-c67f-4513-882c-fbbd97fec629
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021507238 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.4021507238
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.1766454853
Short name T285
Test name
Test status
Simulation time 383022117 ps
CPU time 0.66 seconds
Started May 14 02:06:41 PM PDT 24
Finished May 14 02:06:43 PM PDT 24
Peak memory 183636 kb
Host smart-23bca77b-c898-4df6-be33-f4f5535bba6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766454853 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.1766454853
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.2020246051
Short name T409
Test name
Test status
Simulation time 297802981 ps
CPU time 0.63 seconds
Started May 14 02:06:40 PM PDT 24
Finished May 14 02:06:42 PM PDT 24
Peak memory 183656 kb
Host smart-21d0ba3f-16af-4909-bda6-e1c2aff9b470
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020246051 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_t
imer_mem_partial_access.2020246051
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.1735197309
Short name T396
Test name
Test status
Simulation time 367868445 ps
CPU time 0.65 seconds
Started May 14 02:06:40 PM PDT 24
Finished May 14 02:06:42 PM PDT 24
Peak memory 183664 kb
Host smart-7f7500d1-315c-45c4-b624-89fa83bf1379
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735197309 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_w
alk.1735197309
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.2230620887
Short name T358
Test name
Test status
Simulation time 2541491817 ps
CPU time 1.57 seconds
Started May 14 02:06:51 PM PDT 24
Finished May 14 02:06:53 PM PDT 24
Peak memory 184084 kb
Host smart-724c4e3e-e7a0-4bd2-9a04-43a26a1520fe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230620887 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon
_timer_same_csr_outstanding.2230620887
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.3258431565
Short name T379
Test name
Test status
Simulation time 500415646 ps
CPU time 2.57 seconds
Started May 14 02:06:39 PM PDT 24
Finished May 14 02:06:43 PM PDT 24
Peak memory 198532 kb
Host smart-bf9bd603-0499-4c5b-9f4d-2ebeb07923c3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258431565 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.3258431565
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.3764058675
Short name T354
Test name
Test status
Simulation time 9081675001 ps
CPU time 3.83 seconds
Started May 14 02:06:41 PM PDT 24
Finished May 14 02:06:46 PM PDT 24
Peak memory 197952 kb
Host smart-1e6e8df4-022b-4b29-950a-e125ac162224
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764058675 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl
_intg_err.3764058675
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.3625852008
Short name T294
Test name
Test status
Simulation time 500306344 ps
CPU time 0.71 seconds
Started May 14 02:07:30 PM PDT 24
Finished May 14 02:07:31 PM PDT 24
Peak memory 183676 kb
Host smart-f8f3f9b7-166b-448c-bda7-5a76391cdd2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625852008 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.3625852008
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.3239243413
Short name T389
Test name
Test status
Simulation time 369521235 ps
CPU time 1.15 seconds
Started May 14 02:07:30 PM PDT 24
Finished May 14 02:07:32 PM PDT 24
Peak memory 183744 kb
Host smart-a3e5e31f-5d6a-414b-9f20-267668b62081
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239243413 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.3239243413
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.2926139626
Short name T330
Test name
Test status
Simulation time 413211041 ps
CPU time 0.7 seconds
Started May 14 02:07:30 PM PDT 24
Finished May 14 02:07:32 PM PDT 24
Peak memory 183628 kb
Host smart-144d8599-3dc9-451f-9bff-5b290b9045ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926139626 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.2926139626
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.2516284983
Short name T349
Test name
Test status
Simulation time 428709207 ps
CPU time 1.09 seconds
Started May 14 02:07:39 PM PDT 24
Finished May 14 02:07:42 PM PDT 24
Peak memory 183692 kb
Host smart-4d07bd0f-6c2a-4eda-81cc-6469bb2c09ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516284983 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.2516284983
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.3551648059
Short name T398
Test name
Test status
Simulation time 416847840 ps
CPU time 0.67 seconds
Started May 14 02:07:39 PM PDT 24
Finished May 14 02:07:41 PM PDT 24
Peak memory 183672 kb
Host smart-52fb15d3-2e44-4309-881b-0a3ff0690cdb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551648059 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.3551648059
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.3468686805
Short name T404
Test name
Test status
Simulation time 450888720 ps
CPU time 1.15 seconds
Started May 14 02:07:39 PM PDT 24
Finished May 14 02:07:43 PM PDT 24
Peak memory 183636 kb
Host smart-f1585c80-4e7c-4863-ac28-ce884d4bdae2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468686805 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.3468686805
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.3376982087
Short name T399
Test name
Test status
Simulation time 401891333 ps
CPU time 1.16 seconds
Started May 14 02:07:39 PM PDT 24
Finished May 14 02:07:42 PM PDT 24
Peak memory 183624 kb
Host smart-85838dcf-4c9a-43ea-98bd-f08017fcea44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376982087 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.3376982087
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.2797941059
Short name T328
Test name
Test status
Simulation time 304156565 ps
CPU time 0.76 seconds
Started May 14 02:07:39 PM PDT 24
Finished May 14 02:07:41 PM PDT 24
Peak memory 183636 kb
Host smart-65f8a803-7527-4706-9f09-76b173b374e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797941059 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.2797941059
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.1842256118
Short name T357
Test name
Test status
Simulation time 489393632 ps
CPU time 0.73 seconds
Started May 14 02:07:42 PM PDT 24
Finished May 14 02:07:44 PM PDT 24
Peak memory 183700 kb
Host smart-9f07a6bd-53fc-430d-90af-90714cd7c57a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842256118 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.1842256118
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.896431415
Short name T397
Test name
Test status
Simulation time 393419397 ps
CPU time 0.81 seconds
Started May 14 02:07:43 PM PDT 24
Finished May 14 02:07:45 PM PDT 24
Peak memory 183696 kb
Host smart-0d65084e-949f-4dcb-8914-508c032a43fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896431415 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.896431415
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.2724953860
Short name T319
Test name
Test status
Simulation time 506148866 ps
CPU time 1.34 seconds
Started May 14 02:06:46 PM PDT 24
Finished May 14 02:06:48 PM PDT 24
Peak memory 183752 kb
Host smart-b8644b9d-7b16-4419-926e-0044862255a6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724953860 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_a
liasing.2724953860
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.4290748434
Short name T362
Test name
Test status
Simulation time 7033283121 ps
CPU time 19.09 seconds
Started May 14 02:06:45 PM PDT 24
Finished May 14 02:07:06 PM PDT 24
Peak memory 192312 kb
Host smart-883210d2-b750-4c55-ac58-a41e8a008c80
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290748434 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_b
it_bash.4290748434
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.2092340038
Short name T60
Test name
Test status
Simulation time 975888005 ps
CPU time 2.04 seconds
Started May 14 02:06:46 PM PDT 24
Finished May 14 02:06:49 PM PDT 24
Peak memory 183772 kb
Host smart-89ef7712-22b6-4cc7-bf2f-92449bd7879f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092340038 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_h
w_reset.2092340038
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.2349638401
Short name T372
Test name
Test status
Simulation time 336781069 ps
CPU time 0.86 seconds
Started May 14 02:06:48 PM PDT 24
Finished May 14 02:06:50 PM PDT 24
Peak memory 195200 kb
Host smart-0ff5775f-5e80-43e5-bffe-677606757114
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349638401 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.2349638401
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.1759755428
Short name T65
Test name
Test status
Simulation time 322438075 ps
CPU time 1.07 seconds
Started May 14 02:06:45 PM PDT 24
Finished May 14 02:06:46 PM PDT 24
Peak memory 193068 kb
Host smart-511e937b-7f72-47f9-b86a-08560fa892da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759755428 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.1759755428
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.1674145936
Short name T414
Test name
Test status
Simulation time 467148073 ps
CPU time 1.14 seconds
Started May 14 02:06:48 PM PDT 24
Finished May 14 02:06:50 PM PDT 24
Peak memory 183660 kb
Host smart-429c919a-9f73-4950-8970-2c1c1f56a6b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674145936 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.1674145936
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.302850881
Short name T380
Test name
Test status
Simulation time 434598069 ps
CPU time 0.67 seconds
Started May 14 02:06:51 PM PDT 24
Finished May 14 02:06:53 PM PDT 24
Peak memory 183600 kb
Host smart-f7388889-f087-4bc6-b896-87a774138178
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302850881 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_ti
mer_mem_partial_access.302850881
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.3643487480
Short name T331
Test name
Test status
Simulation time 297091781 ps
CPU time 0.99 seconds
Started May 14 02:06:46 PM PDT 24
Finished May 14 02:06:48 PM PDT 24
Peak memory 183676 kb
Host smart-05ca1d72-50ae-4f15-8a91-d8847159d209
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643487480 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_w
alk.3643487480
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.1465605440
Short name T66
Test name
Test status
Simulation time 2235598369 ps
CPU time 3.38 seconds
Started May 14 02:06:51 PM PDT 24
Finished May 14 02:06:55 PM PDT 24
Peak memory 194424 kb
Host smart-fedf5d56-529d-4989-b931-efa2fbaea3ad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465605440 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon
_timer_same_csr_outstanding.1465605440
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.3718537339
Short name T317
Test name
Test status
Simulation time 356907796 ps
CPU time 1.94 seconds
Started May 14 02:06:48 PM PDT 24
Finished May 14 02:06:51 PM PDT 24
Peak memory 198548 kb
Host smart-43286c2b-cbba-42be-848e-07f7f99043a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718537339 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.3718537339
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.2025871304
Short name T87
Test name
Test status
Simulation time 8512426014 ps
CPU time 4.22 seconds
Started May 14 02:06:48 PM PDT 24
Finished May 14 02:06:53 PM PDT 24
Peak memory 198144 kb
Host smart-d48d9a27-b6b3-47b3-996d-0c1e2d5240ff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025871304 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl
_intg_err.2025871304
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.93027624
Short name T284
Test name
Test status
Simulation time 357654780 ps
CPU time 0.67 seconds
Started May 14 02:07:41 PM PDT 24
Finished May 14 02:07:44 PM PDT 24
Peak memory 183656 kb
Host smart-36d3043b-4576-439d-a8f5-9e8b06574b61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93027624 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.93027624
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.2124820451
Short name T303
Test name
Test status
Simulation time 337119142 ps
CPU time 0.68 seconds
Started May 14 02:07:37 PM PDT 24
Finished May 14 02:07:39 PM PDT 24
Peak memory 183592 kb
Host smart-f5909656-872b-4241-951f-8c02ecb29a30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124820451 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.2124820451
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.416980088
Short name T352
Test name
Test status
Simulation time 412172903 ps
CPU time 1.17 seconds
Started May 14 02:07:39 PM PDT 24
Finished May 14 02:07:42 PM PDT 24
Peak memory 183688 kb
Host smart-0f3bb347-22e3-4515-ac25-d8ee9a6ee822
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416980088 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.416980088
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.2441990979
Short name T395
Test name
Test status
Simulation time 508019833 ps
CPU time 0.73 seconds
Started May 14 02:07:39 PM PDT 24
Finished May 14 02:07:42 PM PDT 24
Peak memory 183676 kb
Host smart-45143223-d1dd-4dd7-a610-3921b97f7ef7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441990979 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.2441990979
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.3446620564
Short name T343
Test name
Test status
Simulation time 334907325 ps
CPU time 0.57 seconds
Started May 14 02:07:38 PM PDT 24
Finished May 14 02:07:40 PM PDT 24
Peak memory 183680 kb
Host smart-b559a83f-a498-4229-9729-47d06d1a9eea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446620564 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.3446620564
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.3904579223
Short name T411
Test name
Test status
Simulation time 482146549 ps
CPU time 1.2 seconds
Started May 14 02:07:38 PM PDT 24
Finished May 14 02:07:42 PM PDT 24
Peak memory 183680 kb
Host smart-332ed8a7-2f83-4ef5-b829-59c47927061e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904579223 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.3904579223
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.3361085207
Short name T366
Test name
Test status
Simulation time 394148101 ps
CPU time 0.66 seconds
Started May 14 02:07:39 PM PDT 24
Finished May 14 02:07:42 PM PDT 24
Peak memory 183692 kb
Host smart-281488df-a573-41c2-9997-b568790a0154
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361085207 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.3361085207
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.2791947817
Short name T307
Test name
Test status
Simulation time 458746090 ps
CPU time 1.29 seconds
Started May 14 02:07:38 PM PDT 24
Finished May 14 02:07:42 PM PDT 24
Peak memory 183672 kb
Host smart-9dce5796-0cd7-4031-8a8f-d35b46ebd52f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791947817 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.2791947817
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.2260532098
Short name T400
Test name
Test status
Simulation time 504356353 ps
CPU time 0.72 seconds
Started May 14 02:07:38 PM PDT 24
Finished May 14 02:07:41 PM PDT 24
Peak memory 183740 kb
Host smart-2b2e34ef-f4a1-49e0-8394-fd1ef7dfbd60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260532098 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.2260532098
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.3780318514
Short name T342
Test name
Test status
Simulation time 290237024 ps
CPU time 0.94 seconds
Started May 14 02:07:38 PM PDT 24
Finished May 14 02:07:40 PM PDT 24
Peak memory 183724 kb
Host smart-6728fedd-2b8f-4316-9b15-9e8e7f57828d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780318514 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.3780318514
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.2222886276
Short name T52
Test name
Test status
Simulation time 440538204 ps
CPU time 1.43 seconds
Started May 14 02:06:56 PM PDT 24
Finished May 14 02:06:59 PM PDT 24
Peak memory 193172 kb
Host smart-83ae4338-ff98-44f9-b661-16bcbaf7c67b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222886276 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_a
liasing.2222886276
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.3094116032
Short name T51
Test name
Test status
Simulation time 647636597 ps
CPU time 1.7 seconds
Started May 14 02:06:55 PM PDT 24
Finished May 14 02:06:58 PM PDT 24
Peak memory 192232 kb
Host smart-1e891589-cb20-47fb-ab39-6213d22c0443
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094116032 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_b
it_bash.3094116032
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.3895785633
Short name T382
Test name
Test status
Simulation time 806802427 ps
CPU time 0.82 seconds
Started May 14 02:06:55 PM PDT 24
Finished May 14 02:06:57 PM PDT 24
Peak memory 183808 kb
Host smart-94119ed8-d9c4-49c2-a7c0-6fd31e6815ff
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895785633 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_h
w_reset.3895785633
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.1108990708
Short name T377
Test name
Test status
Simulation time 505893603 ps
CPU time 1.46 seconds
Started May 14 02:06:54 PM PDT 24
Finished May 14 02:06:57 PM PDT 24
Peak memory 196348 kb
Host smart-b5f20ab7-5cb1-4b1f-b708-70d4ed009fe1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108990708 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.1108990708
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.2634953361
Short name T416
Test name
Test status
Simulation time 518397254 ps
CPU time 1.42 seconds
Started May 14 02:06:54 PM PDT 24
Finished May 14 02:06:57 PM PDT 24
Peak memory 193032 kb
Host smart-e3ca30b5-af05-4f4e-8617-5b450e89c02d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634953361 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.2634953361
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.1517468783
Short name T406
Test name
Test status
Simulation time 290231843 ps
CPU time 0.65 seconds
Started May 14 02:06:51 PM PDT 24
Finished May 14 02:06:52 PM PDT 24
Peak memory 183672 kb
Host smart-a6c80f8d-0e5a-4b30-9ae6-e1480ca9e486
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517468783 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.1517468783
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.117786622
Short name T391
Test name
Test status
Simulation time 409788636 ps
CPU time 1.23 seconds
Started May 14 02:06:55 PM PDT 24
Finished May 14 02:06:57 PM PDT 24
Peak memory 183604 kb
Host smart-8730e6b8-3b4a-4f08-bd74-1312a21f0f2b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117786622 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_ti
mer_mem_partial_access.117786622
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.1414731943
Short name T308
Test name
Test status
Simulation time 294016479 ps
CPU time 0.82 seconds
Started May 14 02:06:55 PM PDT 24
Finished May 14 02:06:57 PM PDT 24
Peak memory 183676 kb
Host smart-19100749-588d-459c-9d97-7aa877638213
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414731943 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_w
alk.1414731943
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.81948767
Short name T402
Test name
Test status
Simulation time 2552790477 ps
CPU time 6.06 seconds
Started May 14 02:06:56 PM PDT 24
Finished May 14 02:07:04 PM PDT 24
Peak memory 183932 kb
Host smart-f422efde-b77a-46cd-82b7-364d4d04d91b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81948767 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_t
imer_same_csr_outstanding.81948767
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.3785594524
Short name T340
Test name
Test status
Simulation time 637793782 ps
CPU time 2.25 seconds
Started May 14 02:06:47 PM PDT 24
Finished May 14 02:06:50 PM PDT 24
Peak memory 198596 kb
Host smart-109cbc69-1fa7-4bc1-ba71-d004aa2c5135
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785594524 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.3785594524
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.3295165010
Short name T299
Test name
Test status
Simulation time 468532493 ps
CPU time 0.86 seconds
Started May 14 02:07:40 PM PDT 24
Finished May 14 02:07:42 PM PDT 24
Peak memory 183656 kb
Host smart-e2dd6c78-cf6c-44c6-8075-5e5f2f0aea41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295165010 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.3295165010
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.4169950318
Short name T390
Test name
Test status
Simulation time 482929600 ps
CPU time 1.23 seconds
Started May 14 02:07:40 PM PDT 24
Finished May 14 02:07:43 PM PDT 24
Peak memory 183676 kb
Host smart-37b274b5-d28a-48bd-b534-bbad333085c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169950318 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.4169950318
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.148765377
Short name T370
Test name
Test status
Simulation time 348342841 ps
CPU time 0.61 seconds
Started May 14 02:07:43 PM PDT 24
Finished May 14 02:07:44 PM PDT 24
Peak memory 183636 kb
Host smart-9f913e71-5092-4904-a314-4d5f6340776a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148765377 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.148765377
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.1566552654
Short name T293
Test name
Test status
Simulation time 282706094 ps
CPU time 0.66 seconds
Started May 14 02:07:43 PM PDT 24
Finished May 14 02:07:44 PM PDT 24
Peak memory 183636 kb
Host smart-20185e87-2a94-413c-82db-f6803aeec8e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566552654 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.1566552654
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.1710089399
Short name T286
Test name
Test status
Simulation time 406358413 ps
CPU time 0.69 seconds
Started May 14 02:07:41 PM PDT 24
Finished May 14 02:07:43 PM PDT 24
Peak memory 183672 kb
Host smart-8db22f07-39a8-4cf5-833b-09a467bc95eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710089399 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.1710089399
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.3115708087
Short name T318
Test name
Test status
Simulation time 508004990 ps
CPU time 0.75 seconds
Started May 14 02:07:39 PM PDT 24
Finished May 14 02:07:42 PM PDT 24
Peak memory 183640 kb
Host smart-a1c09392-0fd8-4f0d-a91a-a0fcdcdb35ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115708087 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.3115708087
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.3394234643
Short name T323
Test name
Test status
Simulation time 537385788 ps
CPU time 0.69 seconds
Started May 14 02:07:38 PM PDT 24
Finished May 14 02:07:40 PM PDT 24
Peak memory 183684 kb
Host smart-7c62b9cf-586a-4fb8-af19-f173a272feb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394234643 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.3394234643
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.1969571084
Short name T335
Test name
Test status
Simulation time 339302866 ps
CPU time 0.62 seconds
Started May 14 02:07:38 PM PDT 24
Finished May 14 02:07:41 PM PDT 24
Peak memory 183668 kb
Host smart-ef39380f-6c74-4a3d-9e48-cd209119662d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969571084 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.1969571084
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.3200681384
Short name T376
Test name
Test status
Simulation time 396038886 ps
CPU time 0.69 seconds
Started May 14 02:07:43 PM PDT 24
Finished May 14 02:07:45 PM PDT 24
Peak memory 183700 kb
Host smart-6716c28b-3a04-4122-91c1-ab1d53d26010
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200681384 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.3200681384
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.1501293776
Short name T339
Test name
Test status
Simulation time 387795083 ps
CPU time 1.18 seconds
Started May 14 02:07:38 PM PDT 24
Finished May 14 02:07:41 PM PDT 24
Peak memory 183680 kb
Host smart-0e27d9af-5421-4111-acdf-8bab8a694a07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501293776 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.1501293776
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.2105751368
Short name T361
Test name
Test status
Simulation time 439161117 ps
CPU time 0.79 seconds
Started May 14 02:06:55 PM PDT 24
Finished May 14 02:06:58 PM PDT 24
Peak memory 196104 kb
Host smart-c5da3194-7ca9-4450-9ff5-78aaec99b21c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105751368 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.2105751368
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.1349414070
Short name T291
Test name
Test status
Simulation time 424772751 ps
CPU time 0.74 seconds
Started May 14 02:06:55 PM PDT 24
Finished May 14 02:06:57 PM PDT 24
Peak memory 183712 kb
Host smart-f508d5c0-48f3-4c7e-8f8c-85979bf0c650
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349414070 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.1349414070
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.2415911349
Short name T381
Test name
Test status
Simulation time 395324610 ps
CPU time 0.67 seconds
Started May 14 02:06:55 PM PDT 24
Finished May 14 02:06:57 PM PDT 24
Peak memory 183696 kb
Host smart-c270d1f3-ddf5-4670-a490-414f2d008cec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415911349 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.2415911349
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.1802642042
Short name T373
Test name
Test status
Simulation time 2197951707 ps
CPU time 3.92 seconds
Started May 14 02:06:55 PM PDT 24
Finished May 14 02:07:00 PM PDT 24
Peak memory 194168 kb
Host smart-dab7acea-4981-4c83-a98b-b96c2e8b4832
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802642042 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon
_timer_same_csr_outstanding.1802642042
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.165442883
Short name T338
Test name
Test status
Simulation time 571441338 ps
CPU time 1.74 seconds
Started May 14 02:06:54 PM PDT 24
Finished May 14 02:06:56 PM PDT 24
Peak memory 198564 kb
Host smart-b65a70ce-fde6-443b-9c8a-9cf175fc5134
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165442883 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.165442883
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.695574594
Short name T86
Test name
Test status
Simulation time 7704048248 ps
CPU time 3.17 seconds
Started May 14 02:06:54 PM PDT 24
Finished May 14 02:06:58 PM PDT 24
Peak memory 197932 kb
Host smart-31c0e36a-d3d0-46eb-befe-49436dbf3b26
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695574594 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_
intg_err.695574594
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.2965970608
Short name T290
Test name
Test status
Simulation time 360680951 ps
CPU time 1.05 seconds
Started May 14 02:07:05 PM PDT 24
Finished May 14 02:07:08 PM PDT 24
Peak memory 195996 kb
Host smart-c6c61d5b-1ec7-4af5-a54e-bb9cd69d4960
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965970608 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.2965970608
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.2730541597
Short name T368
Test name
Test status
Simulation time 408586269 ps
CPU time 0.73 seconds
Started May 14 02:06:53 PM PDT 24
Finished May 14 02:06:54 PM PDT 24
Peak memory 193028 kb
Host smart-3136bcd8-7b5d-4e91-ad0c-6a108e4ae1b0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730541597 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.2730541597
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.2895903972
Short name T315
Test name
Test status
Simulation time 303678795 ps
CPU time 0.97 seconds
Started May 14 02:06:56 PM PDT 24
Finished May 14 02:06:58 PM PDT 24
Peak memory 183644 kb
Host smart-f5b65a75-56f9-43dc-b29f-6405ab221b07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895903972 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.2895903972
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.542209497
Short name T312
Test name
Test status
Simulation time 2331072526 ps
CPU time 2.76 seconds
Started May 14 02:07:05 PM PDT 24
Finished May 14 02:07:09 PM PDT 24
Peak memory 194464 kb
Host smart-6826d4b2-a738-48ed-be26-cf5f07d9ba87
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542209497 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_
timer_same_csr_outstanding.542209497
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.469450774
Short name T306
Test name
Test status
Simulation time 356722068 ps
CPU time 2.88 seconds
Started May 14 02:06:53 PM PDT 24
Finished May 14 02:06:57 PM PDT 24
Peak memory 198612 kb
Host smart-0ef04e44-6a9c-4690-87df-e3927bdee835
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469450774 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.469450774
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.3758695238
Short name T386
Test name
Test status
Simulation time 8753105874 ps
CPU time 2.01 seconds
Started May 14 02:06:55 PM PDT 24
Finished May 14 02:06:58 PM PDT 24
Peak memory 197896 kb
Host smart-f73e92cd-0477-432c-875b-b5a21bfec92c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758695238 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl
_intg_err.3758695238
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.3041258660
Short name T388
Test name
Test status
Simulation time 564103527 ps
CPU time 0.91 seconds
Started May 14 02:07:05 PM PDT 24
Finished May 14 02:07:07 PM PDT 24
Peak memory 196944 kb
Host smart-2bb7ea07-46fe-4446-ba25-0bf4532a2d40
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041258660 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.3041258660
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.2440841505
Short name T67
Test name
Test status
Simulation time 435054267 ps
CPU time 0.6 seconds
Started May 14 02:07:04 PM PDT 24
Finished May 14 02:07:06 PM PDT 24
Peak memory 183888 kb
Host smart-322cfe9f-0e7c-45af-9f67-5078201d5d03
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440841505 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.2440841505
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.1346036737
Short name T408
Test name
Test status
Simulation time 320516154 ps
CPU time 0.68 seconds
Started May 14 02:07:04 PM PDT 24
Finished May 14 02:07:06 PM PDT 24
Peak memory 183672 kb
Host smart-4f06606b-3845-4a15-a46f-73768594ad5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346036737 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.1346036737
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.404145494
Short name T324
Test name
Test status
Simulation time 1224155310 ps
CPU time 2.44 seconds
Started May 14 02:07:06 PM PDT 24
Finished May 14 02:07:10 PM PDT 24
Peak memory 193328 kb
Host smart-5715fe2e-9b25-4161-8781-1b03e49896b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404145494 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_
timer_same_csr_outstanding.404145494
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.281176737
Short name T332
Test name
Test status
Simulation time 413681358 ps
CPU time 1.36 seconds
Started May 14 02:07:03 PM PDT 24
Finished May 14 02:07:05 PM PDT 24
Peak memory 198392 kb
Host smart-2e1c574f-6c9f-4be2-8a16-0a5292db1694
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281176737 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.281176737
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.2745251589
Short name T384
Test name
Test status
Simulation time 4388399844 ps
CPU time 6.64 seconds
Started May 14 02:07:06 PM PDT 24
Finished May 14 02:07:14 PM PDT 24
Peak memory 197384 kb
Host smart-a0c9787a-443c-4b66-8477-18d15e2d46ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745251589 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl
_intg_err.2745251589
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.2201018108
Short name T378
Test name
Test status
Simulation time 477126076 ps
CPU time 1.04 seconds
Started May 14 02:07:04 PM PDT 24
Finished May 14 02:07:07 PM PDT 24
Peak memory 195968 kb
Host smart-603e9069-b08f-4e3f-b5a1-6fd63d735600
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201018108 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.2201018108
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.3687687692
Short name T29
Test name
Test status
Simulation time 354082485 ps
CPU time 1.06 seconds
Started May 14 02:07:04 PM PDT 24
Finished May 14 02:07:06 PM PDT 24
Peak memory 193048 kb
Host smart-5980cb6f-10ec-4d01-81ef-ae9a34854d2e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687687692 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.3687687692
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.76335623
Short name T351
Test name
Test status
Simulation time 506237112 ps
CPU time 1.34 seconds
Started May 14 02:07:04 PM PDT 24
Finished May 14 02:07:07 PM PDT 24
Peak memory 183692 kb
Host smart-a6b91c95-1699-4db0-9087-c3b8a257356d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76335623 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.76335623
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.4025701831
Short name T68
Test name
Test status
Simulation time 1974808699 ps
CPU time 1.66 seconds
Started May 14 02:07:06 PM PDT 24
Finished May 14 02:07:09 PM PDT 24
Peak memory 194708 kb
Host smart-4e5638ed-a2b0-4879-a872-3b888786d8a5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025701831 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon
_timer_same_csr_outstanding.4025701831
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.3436609322
Short name T292
Test name
Test status
Simulation time 461223605 ps
CPU time 1.87 seconds
Started May 14 02:07:06 PM PDT 24
Finished May 14 02:07:09 PM PDT 24
Peak memory 198564 kb
Host smart-fd215194-1d17-44a2-9b49-66d010e3fb64
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436609322 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.3436609322
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.3907394711
Short name T401
Test name
Test status
Simulation time 7956164087 ps
CPU time 4.08 seconds
Started May 14 02:07:05 PM PDT 24
Finished May 14 02:07:11 PM PDT 24
Peak memory 198032 kb
Host smart-504f90e9-9384-4ea5-adba-f4e7a266bfc4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907394711 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl
_intg_err.3907394711
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.3970984003
Short name T363
Test name
Test status
Simulation time 459131373 ps
CPU time 1.2 seconds
Started May 14 02:07:05 PM PDT 24
Finished May 14 02:07:07 PM PDT 24
Peak memory 195992 kb
Host smart-634cdbc7-0e2c-49a1-be1c-61673a19dfd0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970984003 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.3970984003
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.2462432756
Short name T392
Test name
Test status
Simulation time 514955438 ps
CPU time 1.28 seconds
Started May 14 02:07:04 PM PDT 24
Finished May 14 02:07:06 PM PDT 24
Peak memory 183916 kb
Host smart-9918bf40-fad4-4273-a858-6dfd663266a2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462432756 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.2462432756
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.75804121
Short name T282
Test name
Test status
Simulation time 299467260 ps
CPU time 0.96 seconds
Started May 14 02:07:05 PM PDT 24
Finished May 14 02:07:07 PM PDT 24
Peak memory 183696 kb
Host smart-b0c2b151-a196-432c-b134-9ba4e7eca4c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75804121 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.75804121
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.2096887741
Short name T346
Test name
Test status
Simulation time 1276125075 ps
CPU time 2.51 seconds
Started May 14 02:07:04 PM PDT 24
Finished May 14 02:07:08 PM PDT 24
Peak memory 193256 kb
Host smart-bde256bb-bef2-451f-bb56-9b94d2a33237
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096887741 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon
_timer_same_csr_outstanding.2096887741
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.3496706605
Short name T420
Test name
Test status
Simulation time 481367937 ps
CPU time 2.89 seconds
Started May 14 02:07:06 PM PDT 24
Finished May 14 02:07:10 PM PDT 24
Peak memory 198580 kb
Host smart-3c90d089-bf0a-41a4-87c0-5cc9994a4613
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496706605 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.3496706605
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.4238469456
Short name T413
Test name
Test status
Simulation time 8260429396 ps
CPU time 3.53 seconds
Started May 14 02:07:04 PM PDT 24
Finished May 14 02:07:09 PM PDT 24
Peak memory 198140 kb
Host smart-43bc93f5-a622-4487-a6e2-5a74c4e61b5e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238469456 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl
_intg_err.4238469456
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_jump.4258434836
Short name T191
Test name
Test status
Simulation time 378331298 ps
CPU time 0.67 seconds
Started May 14 04:16:11 PM PDT 24
Finished May 14 04:16:14 PM PDT 24
Peak memory 183608 kb
Host smart-e6f5b2dd-507b-4680-9e0d-cf0acb4cb542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258434836 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.4258434836
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.2768519725
Short name T121
Test name
Test status
Simulation time 33403118812 ps
CPU time 11.06 seconds
Started May 14 04:16:10 PM PDT 24
Finished May 14 04:16:23 PM PDT 24
Peak memory 183724 kb
Host smart-0105ef0d-6946-4404-9100-bcdcd2c31d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768519725 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.2768519725
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.1837021427
Short name T133
Test name
Test status
Simulation time 487489737 ps
CPU time 1.42 seconds
Started May 14 04:16:12 PM PDT 24
Finished May 14 04:16:15 PM PDT 24
Peak memory 183576 kb
Host smart-e945dba5-ba5f-4864-98ff-b6a295cc6113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837021427 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.1837021427
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.4012906879
Short name T225
Test name
Test status
Simulation time 327994708725 ps
CPU time 151.32 seconds
Started May 14 04:16:10 PM PDT 24
Finished May 14 04:18:43 PM PDT 24
Peak memory 195052 kb
Host smart-9cb60b88-eccc-494e-9983-172d67d0120b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012906879 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_a
ll.4012906879
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.2251185988
Short name T147
Test name
Test status
Simulation time 68669030623 ps
CPU time 526.66 seconds
Started May 14 04:16:08 PM PDT 24
Finished May 14 04:24:55 PM PDT 24
Peak memory 198552 kb
Host smart-dc151930-0031-4620-9fd4-bb56f2383764
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251185988 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.2251185988
Directory /workspace/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.aon_timer_jump.2739850035
Short name T193
Test name
Test status
Simulation time 516949167 ps
CPU time 1.4 seconds
Started May 14 04:16:11 PM PDT 24
Finished May 14 04:16:14 PM PDT 24
Peak memory 183628 kb
Host smart-bc5551df-bcf5-471b-abad-7f99d16e3768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739850035 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.2739850035
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.1304759980
Short name T203
Test name
Test status
Simulation time 7897849823 ps
CPU time 13.5 seconds
Started May 14 04:16:10 PM PDT 24
Finished May 14 04:16:25 PM PDT 24
Peak memory 183624 kb
Host smart-fe8b796a-fe86-4062-8e47-50d6d883f5d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304759980 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.1304759980
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.3109152810
Short name T17
Test name
Test status
Simulation time 4761264071 ps
CPU time 2.72 seconds
Started May 14 04:16:10 PM PDT 24
Finished May 14 04:16:15 PM PDT 24
Peak memory 215244 kb
Host smart-60ab3066-7d83-4acb-99c9-b6d0d06f611a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109152810 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.3109152810
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.425946020
Short name T140
Test name
Test status
Simulation time 562623757 ps
CPU time 0.59 seconds
Started May 14 04:16:11 PM PDT 24
Finished May 14 04:16:14 PM PDT 24
Peak memory 183604 kb
Host smart-fad59229-1bb7-4bba-a97f-05efd74caf83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425946020 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.425946020
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.3894071708
Short name T238
Test name
Test status
Simulation time 68493316944 ps
CPU time 25.47 seconds
Started May 14 04:16:09 PM PDT 24
Finished May 14 04:16:35 PM PDT 24
Peak memory 183612 kb
Host smart-97ee62d1-1c9e-4f5e-a533-bc8bcb342370
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894071708 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_a
ll.3894071708
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/10.aon_timer_jump.594375223
Short name T182
Test name
Test status
Simulation time 392778187 ps
CPU time 0.89 seconds
Started May 14 04:16:27 PM PDT 24
Finished May 14 04:16:30 PM PDT 24
Peak memory 183580 kb
Host smart-ca4306a0-4bda-4f21-80be-4f7284b87804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594375223 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.594375223
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.1387550171
Short name T42
Test name
Test status
Simulation time 25201068636 ps
CPU time 10.12 seconds
Started May 14 04:16:31 PM PDT 24
Finished May 14 04:16:43 PM PDT 24
Peak memory 183640 kb
Host smart-81f55366-06cd-4bf2-b35d-45a870f1dd40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387550171 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.1387550171
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.1645377062
Short name T112
Test name
Test status
Simulation time 419615044 ps
CPU time 1 seconds
Started May 14 04:16:26 PM PDT 24
Finished May 14 04:16:29 PM PDT 24
Peak memory 183584 kb
Host smart-ab95a86b-81b1-4590-b618-9c98a56d7296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645377062 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.1645377062
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.2082499160
Short name T146
Test name
Test status
Simulation time 111957070778 ps
CPU time 181.39 seconds
Started May 14 04:16:31 PM PDT 24
Finished May 14 04:19:34 PM PDT 24
Peak memory 194800 kb
Host smart-2d1ceefc-a62e-45eb-842e-076ddc08c81e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082499160 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_
all.2082499160
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.2415799361
Short name T172
Test name
Test status
Simulation time 167865209310 ps
CPU time 913.82 seconds
Started May 14 04:16:27 PM PDT 24
Finished May 14 04:31:43 PM PDT 24
Peak memory 203644 kb
Host smart-846d770d-9a93-41a7-883f-16367668913b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415799361 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.2415799361
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.aon_timer_jump.2725744167
Short name T13
Test name
Test status
Simulation time 438594834 ps
CPU time 0.76 seconds
Started May 14 04:16:28 PM PDT 24
Finished May 14 04:16:31 PM PDT 24
Peak memory 183608 kb
Host smart-94ca7cbe-757c-4609-8b40-284aa4ab8dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725744167 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.2725744167
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.1193042868
Short name T264
Test name
Test status
Simulation time 39192876718 ps
CPU time 12.8 seconds
Started May 14 04:16:26 PM PDT 24
Finished May 14 04:16:41 PM PDT 24
Peak memory 183640 kb
Host smart-8705e702-818e-4abb-b110-3482512a9b3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193042868 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.1193042868
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.3405708969
Short name T23
Test name
Test status
Simulation time 561124841 ps
CPU time 1.37 seconds
Started May 14 04:16:27 PM PDT 24
Finished May 14 04:16:30 PM PDT 24
Peak memory 183608 kb
Host smart-a04a2544-45e6-4007-945a-ac6b540d4a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405708969 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.3405708969
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.2974633629
Short name T251
Test name
Test status
Simulation time 152719182488 ps
CPU time 116.18 seconds
Started May 14 04:16:27 PM PDT 24
Finished May 14 04:18:25 PM PDT 24
Peak memory 194040 kb
Host smart-f61b80a7-85c9-477a-98a3-e3dff0bdb9e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974633629 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_
all.2974633629
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.1152155677
Short name T69
Test name
Test status
Simulation time 70659440363 ps
CPU time 767.81 seconds
Started May 14 04:16:29 PM PDT 24
Finished May 14 04:29:19 PM PDT 24
Peak memory 200612 kb
Host smart-cd6a630f-7107-48bc-b3b4-ec665e3df3ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152155677 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand_reset.1152155677
Directory /workspace/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.aon_timer_jump.67378189
Short name T113
Test name
Test status
Simulation time 479937494 ps
CPU time 1.26 seconds
Started May 14 04:16:35 PM PDT 24
Finished May 14 04:16:37 PM PDT 24
Peak memory 183596 kb
Host smart-c480a8a4-5377-43a5-90a4-bf44b0830a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67378189 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.67378189
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.1444733786
Short name T242
Test name
Test status
Simulation time 21388806119 ps
CPU time 9.46 seconds
Started May 14 04:16:33 PM PDT 24
Finished May 14 04:16:44 PM PDT 24
Peak memory 183632 kb
Host smart-0fa9d9f3-51ca-44b6-b068-72da40637d4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444733786 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.1444733786
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.2104808518
Short name T205
Test name
Test status
Simulation time 425543541 ps
CPU time 1.13 seconds
Started May 14 04:16:33 PM PDT 24
Finished May 14 04:16:35 PM PDT 24
Peak memory 183764 kb
Host smart-02065d86-a9d3-48c2-8286-5f85a89a7212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104808518 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.2104808518
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.3020325578
Short name T145
Test name
Test status
Simulation time 316198879474 ps
CPU time 464.79 seconds
Started May 14 04:16:35 PM PDT 24
Finished May 14 04:24:21 PM PDT 24
Peak memory 195356 kb
Host smart-42bea7fe-ec01-4826-a951-9addcffb6646
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020325578 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_
all.3020325578
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.3867861560
Short name T188
Test name
Test status
Simulation time 19982828775 ps
CPU time 198.36 seconds
Started May 14 04:16:34 PM PDT 24
Finished May 14 04:19:54 PM PDT 24
Peak memory 198548 kb
Host smart-29071f97-025d-4131-b51b-63292a914ab6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867861560 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.3867861560
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_jump.2881064449
Short name T106
Test name
Test status
Simulation time 463136510 ps
CPU time 0.88 seconds
Started May 14 04:16:33 PM PDT 24
Finished May 14 04:16:36 PM PDT 24
Peak memory 183688 kb
Host smart-87ba8f5f-0c23-471e-8c39-b28266fadc84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881064449 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.2881064449
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.854121890
Short name T277
Test name
Test status
Simulation time 18717638083 ps
CPU time 27.24 seconds
Started May 14 04:16:33 PM PDT 24
Finished May 14 04:17:01 PM PDT 24
Peak memory 191876 kb
Host smart-71cd09bd-a0eb-4a57-9c05-fd99c14d1c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854121890 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.854121890
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.188282442
Short name T253
Test name
Test status
Simulation time 587684024 ps
CPU time 0.67 seconds
Started May 14 04:16:34 PM PDT 24
Finished May 14 04:16:36 PM PDT 24
Peak memory 183668 kb
Host smart-5cde45ec-376b-439a-a5bb-db1cc597fbf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188282442 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.188282442
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.1025063356
Short name T82
Test name
Test status
Simulation time 4413290515 ps
CPU time 1.74 seconds
Started May 14 04:16:34 PM PDT 24
Finished May 14 04:16:37 PM PDT 24
Peak memory 183680 kb
Host smart-08badf0e-2eee-48be-a90a-ebe1b9db7a29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025063356 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_
all.1025063356
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.3530288021
Short name T235
Test name
Test status
Simulation time 129260583412 ps
CPU time 381.5 seconds
Started May 14 04:16:35 PM PDT 24
Finished May 14 04:22:58 PM PDT 24
Peak memory 198472 kb
Host smart-f22d80d8-e114-4a39-98c7-75ea31f31f5e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530288021 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.3530288021
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.aon_timer_jump.633138061
Short name T194
Test name
Test status
Simulation time 652526673 ps
CPU time 1.14 seconds
Started May 14 04:16:35 PM PDT 24
Finished May 14 04:16:37 PM PDT 24
Peak memory 183580 kb
Host smart-c0dee2e0-d779-4bcf-98cd-7e41eeb0b1ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633138061 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.633138061
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.4208512354
Short name T271
Test name
Test status
Simulation time 31871302405 ps
CPU time 53.41 seconds
Started May 14 04:16:33 PM PDT 24
Finished May 14 04:17:27 PM PDT 24
Peak memory 183592 kb
Host smart-95b9b8cc-9db6-4039-9b26-0124d3f109cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208512354 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.4208512354
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.3673874318
Short name T114
Test name
Test status
Simulation time 424179260 ps
CPU time 0.73 seconds
Started May 14 04:16:34 PM PDT 24
Finished May 14 04:16:36 PM PDT 24
Peak memory 183564 kb
Host smart-4d4cfb83-1f4d-443b-9a51-77782443a8d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673874318 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.3673874318
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.3043377722
Short name T196
Test name
Test status
Simulation time 84924333087 ps
CPU time 36.09 seconds
Started May 14 04:16:42 PM PDT 24
Finished May 14 04:17:19 PM PDT 24
Peak memory 183588 kb
Host smart-7d1581ea-5cfa-4d9d-94f2-c9a12e4a9d5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043377722 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_
all.3043377722
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.94332352
Short name T49
Test name
Test status
Simulation time 73701529224 ps
CPU time 162.1 seconds
Started May 14 04:16:35 PM PDT 24
Finished May 14 04:19:19 PM PDT 24
Peak memory 198616 kb
Host smart-33d1f833-dfb6-4905-bb9f-1b249b92bb26
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94332352 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.94332352
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.aon_timer_jump.2152036118
Short name T21
Test name
Test status
Simulation time 589175994 ps
CPU time 1.49 seconds
Started May 14 04:16:41 PM PDT 24
Finished May 14 04:16:43 PM PDT 24
Peak memory 183688 kb
Host smart-dd02bb20-8149-47e8-803c-178591b6abe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152036118 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.2152036118
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.879103604
Short name T120
Test name
Test status
Simulation time 27468538693 ps
CPU time 44 seconds
Started May 14 04:16:41 PM PDT 24
Finished May 14 04:17:26 PM PDT 24
Peak memory 191828 kb
Host smart-b54d8be7-8058-4918-a6b6-d2f45a33f144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879103604 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.879103604
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.602387487
Short name T1
Test name
Test status
Simulation time 600913025 ps
CPU time 0.76 seconds
Started May 14 04:16:40 PM PDT 24
Finished May 14 04:16:42 PM PDT 24
Peak memory 183608 kb
Host smart-d9d6eb55-b3de-4ab5-8d87-e9d18b7be73d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602387487 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.602387487
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.1548955263
Short name T237
Test name
Test status
Simulation time 96608950859 ps
CPU time 42.49 seconds
Started May 14 04:16:52 PM PDT 24
Finished May 14 04:17:36 PM PDT 24
Peak memory 194016 kb
Host smart-ed420f42-ed1a-46f5-8af3-bc6c8e40e380
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548955263 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_
all.1548955263
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.3333735448
Short name T74
Test name
Test status
Simulation time 83389390293 ps
CPU time 340.82 seconds
Started May 14 04:16:42 PM PDT 24
Finished May 14 04:22:24 PM PDT 24
Peak memory 198516 kb
Host smart-07bb6869-14e2-408d-a4c8-94b2b6cac7dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333735448 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.3333735448
Directory /workspace/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.aon_timer_jump.3701692189
Short name T195
Test name
Test status
Simulation time 538266507 ps
CPU time 1.42 seconds
Started May 14 04:16:46 PM PDT 24
Finished May 14 04:16:49 PM PDT 24
Peak memory 183532 kb
Host smart-2c79b391-2d2a-4e95-9fcd-909198388210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701692189 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.3701692189
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.1880107087
Short name T170
Test name
Test status
Simulation time 37586463672 ps
CPU time 20.9 seconds
Started May 14 04:16:48 PM PDT 24
Finished May 14 04:17:10 PM PDT 24
Peak memory 183640 kb
Host smart-6fca32de-d048-41dc-bc55-1d00717fc9d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880107087 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.1880107087
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.1418735749
Short name T262
Test name
Test status
Simulation time 568802477 ps
CPU time 0.75 seconds
Started May 14 04:16:47 PM PDT 24
Finished May 14 04:16:49 PM PDT 24
Peak memory 183620 kb
Host smart-a02a94ab-91ed-42c7-a73d-05942b76a2bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418735749 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.1418735749
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.1842337428
Short name T80
Test name
Test status
Simulation time 79618027594 ps
CPU time 30.77 seconds
Started May 14 04:16:52 PM PDT 24
Finished May 14 04:17:24 PM PDT 24
Peak memory 183664 kb
Host smart-9cd1aaff-9fd4-4e76-b64a-ac9be43ac526
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842337428 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_
all.1842337428
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.2694508362
Short name T185
Test name
Test status
Simulation time 41092992951 ps
CPU time 255.55 seconds
Started May 14 04:16:51 PM PDT 24
Finished May 14 04:21:08 PM PDT 24
Peak memory 198528 kb
Host smart-1adbf569-fa33-40b8-9610-9b79b61883e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694508362 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.2694508362
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.aon_timer_jump.308060507
Short name T92
Test name
Test status
Simulation time 590523729 ps
CPU time 0.99 seconds
Started May 14 04:16:48 PM PDT 24
Finished May 14 04:16:50 PM PDT 24
Peak memory 183488 kb
Host smart-5db3fa3c-3ceb-4e0c-b236-bba837238852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308060507 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.308060507
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.1237163916
Short name T265
Test name
Test status
Simulation time 17382761251 ps
CPU time 29.53 seconds
Started May 14 04:16:47 PM PDT 24
Finished May 14 04:17:18 PM PDT 24
Peak memory 183624 kb
Host smart-5160f0ab-6f1c-4937-af69-f0dfddb7b35c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237163916 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.1237163916
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.1567117811
Short name T4
Test name
Test status
Simulation time 346237678 ps
CPU time 1.1 seconds
Started May 14 04:16:48 PM PDT 24
Finished May 14 04:16:51 PM PDT 24
Peak memory 183496 kb
Host smart-79bc1cbf-eba5-41c9-822c-668413ae85f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567117811 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.1567117811
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.1205428446
Short name T47
Test name
Test status
Simulation time 66590883029 ps
CPU time 112.91 seconds
Started May 14 04:16:47 PM PDT 24
Finished May 14 04:18:40 PM PDT 24
Peak memory 194152 kb
Host smart-359cd8ee-50c3-4740-9c8b-f4f02633e0ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205428446 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_
all.1205428446
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.1810675422
Short name T48
Test name
Test status
Simulation time 88764398536 ps
CPU time 959.92 seconds
Started May 14 04:16:48 PM PDT 24
Finished May 14 04:32:49 PM PDT 24
Peak memory 204132 kb
Host smart-f645a4b0-b2d0-49de-ad48-9a3e63261a70
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810675422 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.1810675422
Directory /workspace/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.aon_timer_jump.2316271477
Short name T99
Test name
Test status
Simulation time 424092598 ps
CPU time 0.75 seconds
Started May 14 04:16:47 PM PDT 24
Finished May 14 04:16:49 PM PDT 24
Peak memory 183580 kb
Host smart-549e79ce-caee-4270-b9e9-eafedbfdbbb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316271477 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.2316271477
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.3414269846
Short name T255
Test name
Test status
Simulation time 40236746517 ps
CPU time 14.2 seconds
Started May 14 04:16:48 PM PDT 24
Finished May 14 04:17:03 PM PDT 24
Peak memory 183752 kb
Host smart-e8e2be7c-1946-40d9-80a5-f5282f66cb94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414269846 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.3414269846
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.1069001753
Short name T96
Test name
Test status
Simulation time 507129864 ps
CPU time 1.09 seconds
Started May 14 04:16:47 PM PDT 24
Finished May 14 04:16:50 PM PDT 24
Peak memory 183608 kb
Host smart-ede179c3-9b7b-4e6b-a21b-cd77e67837aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069001753 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.1069001753
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.3261022634
Short name T43
Test name
Test status
Simulation time 36036335946 ps
CPU time 49.93 seconds
Started May 14 04:16:55 PM PDT 24
Finished May 14 04:17:46 PM PDT 24
Peak memory 183652 kb
Host smart-5b4295be-0214-4a66-8414-84f5638e5417
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261022634 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_
all.3261022634
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.1943693433
Short name T77
Test name
Test status
Simulation time 99915344376 ps
CPU time 769.87 seconds
Started May 14 04:16:49 PM PDT 24
Finished May 14 04:29:40 PM PDT 24
Peak memory 201148 kb
Host smart-b9326c0a-1581-4eb1-8172-7389f198b519
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943693433 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.1943693433
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.aon_timer_jump.3527270034
Short name T26
Test name
Test status
Simulation time 498256606 ps
CPU time 0.85 seconds
Started May 14 04:16:55 PM PDT 24
Finished May 14 04:16:57 PM PDT 24
Peak memory 183500 kb
Host smart-f5f0dbf9-84fa-44fb-a0b5-24fc7e332a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527270034 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.3527270034
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.2691562326
Short name T135
Test name
Test status
Simulation time 14494210009 ps
CPU time 5.87 seconds
Started May 14 04:16:55 PM PDT 24
Finished May 14 04:17:01 PM PDT 24
Peak memory 183752 kb
Host smart-50a78e3b-03a8-4471-b90e-78f481f6fb18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691562326 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.2691562326
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.86823346
Short name T8
Test name
Test status
Simulation time 432026674 ps
CPU time 1.26 seconds
Started May 14 04:16:57 PM PDT 24
Finished May 14 04:16:59 PM PDT 24
Peak memory 183604 kb
Host smart-bf335b1c-f67b-482c-a731-19e456e3a563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86823346 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.86823346
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.1390385437
Short name T239
Test name
Test status
Simulation time 76873455128 ps
CPU time 99.65 seconds
Started May 14 04:17:05 PM PDT 24
Finished May 14 04:18:50 PM PDT 24
Peak memory 194928 kb
Host smart-f3929e02-7b1f-4974-ab58-593a4dc6e6d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390385437 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_
all.1390385437
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.1217253192
Short name T260
Test name
Test status
Simulation time 82484036197 ps
CPU time 228.79 seconds
Started May 14 04:16:58 PM PDT 24
Finished May 14 04:20:48 PM PDT 24
Peak memory 198636 kb
Host smart-98192488-0b0e-4dc3-8db3-5d1af81f7869
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217253192 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.1217253192
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_jump.1857020848
Short name T160
Test name
Test status
Simulation time 431294864 ps
CPU time 0.76 seconds
Started May 14 04:16:11 PM PDT 24
Finished May 14 04:16:14 PM PDT 24
Peak memory 183608 kb
Host smart-1d3c5935-0be0-4fd2-8a52-b1a0f0946e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857020848 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.1857020848
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.3797970742
Short name T228
Test name
Test status
Simulation time 35022682532 ps
CPU time 50.54 seconds
Started May 14 04:16:09 PM PDT 24
Finished May 14 04:17:01 PM PDT 24
Peak memory 183652 kb
Host smart-bf7554c4-7c7a-418c-9d1c-161d2e58899b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797970742 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.3797970742
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.2681654826
Short name T15
Test name
Test status
Simulation time 8217547524 ps
CPU time 3.43 seconds
Started May 14 04:16:17 PM PDT 24
Finished May 14 04:16:22 PM PDT 24
Peak memory 215364 kb
Host smart-a573acb6-1ef7-4212-8794-61ae74abd5d4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681654826 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.2681654826
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.4254024220
Short name T275
Test name
Test status
Simulation time 380411704 ps
CPU time 0.68 seconds
Started May 14 04:16:10 PM PDT 24
Finished May 14 04:16:12 PM PDT 24
Peak memory 183608 kb
Host smart-5b95e540-e6f9-42d6-ae36-da6350c76a47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254024220 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.4254024220
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.3983206999
Short name T138
Test name
Test status
Simulation time 39430840255 ps
CPU time 15.2 seconds
Started May 14 04:16:17 PM PDT 24
Finished May 14 04:16:34 PM PDT 24
Peak memory 183696 kb
Host smart-a6763479-5d4d-4f5b-81c5-c5f632499542
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983206999 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_a
ll.3983206999
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.2671474358
Short name T39
Test name
Test status
Simulation time 40611395846 ps
CPU time 269.21 seconds
Started May 14 04:16:10 PM PDT 24
Finished May 14 04:20:40 PM PDT 24
Peak memory 206712 kb
Host smart-67b6df07-1850-47cf-888b-f9a874bfcf25
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671474358 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.2671474358
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.aon_timer_jump.3057599216
Short name T136
Test name
Test status
Simulation time 533392301 ps
CPU time 0.97 seconds
Started May 14 04:17:03 PM PDT 24
Finished May 14 04:17:09 PM PDT 24
Peak memory 183496 kb
Host smart-a7e8997f-e08a-4dcd-a7b9-0e2392a17a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057599216 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.3057599216
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.2931106783
Short name T22
Test name
Test status
Simulation time 11538039602 ps
CPU time 9.02 seconds
Started May 14 04:17:06 PM PDT 24
Finished May 14 04:17:21 PM PDT 24
Peak memory 191840 kb
Host smart-26ef1b95-b7df-4724-8d0b-a3725dca2847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931106783 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.2931106783
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.4119381087
Short name T131
Test name
Test status
Simulation time 428473842 ps
CPU time 1.19 seconds
Started May 14 04:17:03 PM PDT 24
Finished May 14 04:17:09 PM PDT 24
Peak memory 183596 kb
Host smart-0a1df7ad-1667-4636-8cd4-60788cd73d66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119381087 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.4119381087
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.3087972680
Short name T250
Test name
Test status
Simulation time 341289793566 ps
CPU time 86.89 seconds
Started May 14 04:17:06 PM PDT 24
Finished May 14 04:18:38 PM PDT 24
Peak memory 194536 kb
Host smart-c8d68818-e17a-4095-b5c0-88dafa8b00f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087972680 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_
all.3087972680
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.567000533
Short name T233
Test name
Test status
Simulation time 150256585931 ps
CPU time 481.26 seconds
Started May 14 04:17:04 PM PDT 24
Finished May 14 04:25:10 PM PDT 24
Peak memory 198528 kb
Host smart-74355472-08af-4995-a7ef-6c6f725dfa65
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567000533 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.567000533
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_jump.831809968
Short name T207
Test name
Test status
Simulation time 512904011 ps
CPU time 1.34 seconds
Started May 14 04:17:04 PM PDT 24
Finished May 14 04:17:11 PM PDT 24
Peak memory 183516 kb
Host smart-df23cc65-6c2f-4eac-99e3-5706d4d62830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831809968 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.831809968
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.3157812411
Short name T210
Test name
Test status
Simulation time 12178068022 ps
CPU time 9 seconds
Started May 14 04:17:05 PM PDT 24
Finished May 14 04:17:19 PM PDT 24
Peak memory 183668 kb
Host smart-0666c96d-f93e-4d1a-b76f-3e056ea0466e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157812411 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.3157812411
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.3582550221
Short name T224
Test name
Test status
Simulation time 394852071 ps
CPU time 1.14 seconds
Started May 14 04:17:04 PM PDT 24
Finished May 14 04:17:11 PM PDT 24
Peak memory 183604 kb
Host smart-eb366bd5-0861-41a5-86d6-5b44a1b82e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582550221 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.3582550221
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.1337738838
Short name T105
Test name
Test status
Simulation time 43424348216 ps
CPU time 64.34 seconds
Started May 14 04:17:03 PM PDT 24
Finished May 14 04:18:12 PM PDT 24
Peak memory 183616 kb
Host smart-38cad854-fa9b-442b-917e-4da5aef498ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337738838 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_
all.1337738838
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_jump.3727009199
Short name T198
Test name
Test status
Simulation time 526699338 ps
CPU time 1.17 seconds
Started May 14 04:17:04 PM PDT 24
Finished May 14 04:17:11 PM PDT 24
Peak memory 183648 kb
Host smart-eef3acaf-f3e9-409f-b983-487da2f8c08c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727009199 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.3727009199
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.3336640685
Short name T127
Test name
Test status
Simulation time 30244504831 ps
CPU time 10.42 seconds
Started May 14 04:17:04 PM PDT 24
Finished May 14 04:17:19 PM PDT 24
Peak memory 183632 kb
Host smart-f4695c44-aa12-440e-ae7e-35c5d54948f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336640685 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.3336640685
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.799429486
Short name T215
Test name
Test status
Simulation time 532175468 ps
CPU time 0.74 seconds
Started May 14 04:17:03 PM PDT 24
Finished May 14 04:17:09 PM PDT 24
Peak memory 183668 kb
Host smart-8120d864-6812-45f7-82c5-c2997f41af16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799429486 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.799429486
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.3289952857
Short name T190
Test name
Test status
Simulation time 70745475041 ps
CPU time 120.11 seconds
Started May 14 04:17:04 PM PDT 24
Finished May 14 04:19:09 PM PDT 24
Peak memory 183648 kb
Host smart-3efb849f-b053-43f8-b70a-cbc6064ad4d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289952857 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_
all.3289952857
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.597360809
Short name T150
Test name
Test status
Simulation time 14319920281 ps
CPU time 104.37 seconds
Started May 14 04:17:03 PM PDT 24
Finished May 14 04:18:52 PM PDT 24
Peak memory 198504 kb
Host smart-05b604c9-763b-4c2b-9894-32d4a7d6054f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597360809 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.597360809
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.aon_timer_jump.3394281761
Short name T217
Test name
Test status
Simulation time 459122479 ps
CPU time 0.9 seconds
Started May 14 04:17:04 PM PDT 24
Finished May 14 04:17:10 PM PDT 24
Peak memory 183544 kb
Host smart-7444709d-acf0-43a9-8b2b-94b5f772d431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394281761 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.3394281761
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.1369276397
Short name T5
Test name
Test status
Simulation time 23663302292 ps
CPU time 10.45 seconds
Started May 14 04:17:03 PM PDT 24
Finished May 14 04:17:18 PM PDT 24
Peak memory 183640 kb
Host smart-2ca2ab71-ec02-48b8-a167-0269cf69677a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369276397 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.1369276397
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.3688262952
Short name T201
Test name
Test status
Simulation time 492657662 ps
CPU time 0.72 seconds
Started May 14 04:17:04 PM PDT 24
Finished May 14 04:17:10 PM PDT 24
Peak memory 183520 kb
Host smart-323f58fe-050a-49c2-8c2c-c60b4c8ac028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688262952 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.3688262952
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.1991037602
Short name T200
Test name
Test status
Simulation time 265991890716 ps
CPU time 104.68 seconds
Started May 14 04:17:03 PM PDT 24
Finished May 14 04:18:51 PM PDT 24
Peak memory 183696 kb
Host smart-9b773fa0-e73a-4627-8381-2b49cd84c6bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991037602 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_
all.1991037602
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.541760489
Short name T211
Test name
Test status
Simulation time 48557632657 ps
CPU time 541.28 seconds
Started May 14 04:17:04 PM PDT 24
Finished May 14 04:26:11 PM PDT 24
Peak memory 198496 kb
Host smart-64496153-c774-4156-8953-1d34204eb42e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541760489 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.541760489
Directory /workspace/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.aon_timer_jump.1528562593
Short name T236
Test name
Test status
Simulation time 572465632 ps
CPU time 0.83 seconds
Started May 14 04:17:04 PM PDT 24
Finished May 14 04:17:10 PM PDT 24
Peak memory 183580 kb
Host smart-0d8fa789-6799-4a6f-b6c3-1ad5316cd08c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528562593 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.1528562593
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.3273801307
Short name T153
Test name
Test status
Simulation time 11246188636 ps
CPU time 4.19 seconds
Started May 14 04:17:05 PM PDT 24
Finished May 14 04:17:14 PM PDT 24
Peak memory 191868 kb
Host smart-13fe467b-e776-44db-8cde-e021398dc9e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273801307 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.3273801307
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.188083649
Short name T110
Test name
Test status
Simulation time 515015934 ps
CPU time 1.28 seconds
Started May 14 04:17:02 PM PDT 24
Finished May 14 04:17:06 PM PDT 24
Peak memory 183508 kb
Host smart-96bd8c4f-4921-49c9-abb7-fd7e79a52fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188083649 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.188083649
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.2531201523
Short name T192
Test name
Test status
Simulation time 136419198995 ps
CPU time 101.73 seconds
Started May 14 04:17:02 PM PDT 24
Finished May 14 04:18:45 PM PDT 24
Peak memory 195448 kb
Host smart-00f15a9a-3ea9-4ca8-92ab-d40a53e54784
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531201523 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_
all.2531201523
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.3390730911
Short name T7
Test name
Test status
Simulation time 19552903375 ps
CPU time 159.83 seconds
Started May 14 04:17:03 PM PDT 24
Finished May 14 04:19:47 PM PDT 24
Peak memory 198564 kb
Host smart-549b6071-d6f9-4234-b15e-85273c47b5fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390730911 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand_reset.3390730911
Directory /workspace/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.aon_timer_jump.4209058594
Short name T174
Test name
Test status
Simulation time 453047604 ps
CPU time 0.98 seconds
Started May 14 04:17:05 PM PDT 24
Finished May 14 04:17:11 PM PDT 24
Peak memory 183568 kb
Host smart-d048ecbf-c7e8-4bc5-8de7-374a1615e99b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209058594 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.4209058594
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.3289665377
Short name T226
Test name
Test status
Simulation time 22891005681 ps
CPU time 9.55 seconds
Started May 14 04:17:02 PM PDT 24
Finished May 14 04:17:14 PM PDT 24
Peak memory 183668 kb
Host smart-57a0c8cd-b27e-4ba1-b605-b3be860035cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289665377 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.3289665377
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.2417751873
Short name T94
Test name
Test status
Simulation time 505893726 ps
CPU time 1.17 seconds
Started May 14 04:17:03 PM PDT 24
Finished May 14 04:17:07 PM PDT 24
Peak memory 183688 kb
Host smart-4d273e70-b284-43b4-8d60-520503cf2517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417751873 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.2417751873
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.263134939
Short name T2
Test name
Test status
Simulation time 140382175176 ps
CPU time 229.27 seconds
Started May 14 04:17:05 PM PDT 24
Finished May 14 04:21:00 PM PDT 24
Peak memory 183636 kb
Host smart-c675d011-bfff-44db-b13d-ff0efac3b20f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263134939 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_a
ll.263134939
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_jump.229219917
Short name T227
Test name
Test status
Simulation time 415767243 ps
CPU time 0.87 seconds
Started May 14 04:17:03 PM PDT 24
Finished May 14 04:17:08 PM PDT 24
Peak memory 183536 kb
Host smart-8f631e40-7cb7-465a-841e-9c70fe9b4fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229219917 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.229219917
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.1240779438
Short name T187
Test name
Test status
Simulation time 30705492908 ps
CPU time 46.65 seconds
Started May 14 04:17:05 PM PDT 24
Finished May 14 04:17:57 PM PDT 24
Peak memory 183700 kb
Host smart-f4a784ec-20cd-4801-9446-b8672392c45f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240779438 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.1240779438
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.709028179
Short name T208
Test name
Test status
Simulation time 489811983 ps
CPU time 0.73 seconds
Started May 14 04:17:05 PM PDT 24
Finished May 14 04:17:11 PM PDT 24
Peak memory 183596 kb
Host smart-ddf8d626-4908-49b3-85ba-867cee627159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709028179 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.709028179
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.1575368335
Short name T155
Test name
Test status
Simulation time 277446443639 ps
CPU time 102.07 seconds
Started May 14 04:17:04 PM PDT 24
Finished May 14 04:18:51 PM PDT 24
Peak memory 183632 kb
Host smart-c80b6ca1-2a04-4194-9825-ca29d8fad9e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575368335 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_
all.1575368335
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.4004698515
Short name T247
Test name
Test status
Simulation time 13115370962 ps
CPU time 109.88 seconds
Started May 14 04:17:04 PM PDT 24
Finished May 14 04:18:59 PM PDT 24
Peak memory 198496 kb
Host smart-73ad7640-eecc-4969-ba85-d962a3f406cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004698515 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.4004698515
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_jump.3666853287
Short name T108
Test name
Test status
Simulation time 504226642 ps
CPU time 1.31 seconds
Started May 14 04:17:01 PM PDT 24
Finished May 14 04:17:04 PM PDT 24
Peak memory 183544 kb
Host smart-bb1e4942-0ba1-4261-b237-5e3981f0c1bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666853287 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.3666853287
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.2218836671
Short name T156
Test name
Test status
Simulation time 61445841814 ps
CPU time 26.19 seconds
Started May 14 04:17:03 PM PDT 24
Finished May 14 04:17:34 PM PDT 24
Peak memory 191840 kb
Host smart-ce6747cd-4e65-4f94-8fe9-ae0b88736b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218836671 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.2218836671
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.2514783079
Short name T117
Test name
Test status
Simulation time 428489333 ps
CPU time 0.92 seconds
Started May 14 04:17:04 PM PDT 24
Finished May 14 04:17:11 PM PDT 24
Peak memory 183624 kb
Host smart-8d1a88bf-572c-47f3-b228-27a1edf752ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514783079 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.2514783079
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.1991162894
Short name T158
Test name
Test status
Simulation time 83647635985 ps
CPU time 16.08 seconds
Started May 14 04:17:04 PM PDT 24
Finished May 14 04:17:26 PM PDT 24
Peak memory 183720 kb
Host smart-70de5d6c-5d51-4eef-999a-706da2bc59ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991162894 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_
all.1991162894
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.1088565955
Short name T278
Test name
Test status
Simulation time 138238670680 ps
CPU time 354.79 seconds
Started May 14 04:17:04 PM PDT 24
Finished May 14 04:23:04 PM PDT 24
Peak memory 198512 kb
Host smart-c884bddd-addd-455f-921c-46bcd1364e6f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088565955 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.1088565955
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_jump.289275020
Short name T178
Test name
Test status
Simulation time 541094072 ps
CPU time 0.93 seconds
Started May 14 04:17:10 PM PDT 24
Finished May 14 04:17:14 PM PDT 24
Peak memory 183580 kb
Host smart-8be799d8-4001-47b5-b771-5fa0e05e47b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289275020 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.289275020
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.3079968716
Short name T246
Test name
Test status
Simulation time 51478852923 ps
CPU time 18.36 seconds
Started May 14 04:17:12 PM PDT 24
Finished May 14 04:17:33 PM PDT 24
Peak memory 191956 kb
Host smart-e499f25a-25db-4419-8a66-f59e8c8fd9e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079968716 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.3079968716
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.2765583380
Short name T95
Test name
Test status
Simulation time 568611199 ps
CPU time 0.82 seconds
Started May 14 04:17:03 PM PDT 24
Finished May 14 04:17:08 PM PDT 24
Peak memory 183608 kb
Host smart-9780432d-4d14-4c12-b044-61638c11967c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765583380 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.2765583380
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.1455324886
Short name T81
Test name
Test status
Simulation time 139655092965 ps
CPU time 240.72 seconds
Started May 14 04:17:12 PM PDT 24
Finished May 14 04:21:15 PM PDT 24
Peak memory 193716 kb
Host smart-d13c678a-0f33-43e9-a59c-5b753f953b67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455324886 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_
all.1455324886
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.103875777
Short name T38
Test name
Test status
Simulation time 92411672661 ps
CPU time 196.94 seconds
Started May 14 04:17:11 PM PDT 24
Finished May 14 04:20:31 PM PDT 24
Peak memory 198516 kb
Host smart-cc028859-1d1e-4693-b66f-49ece2097f69
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103875777 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.103875777
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.aon_timer_jump.3565649015
Short name T209
Test name
Test status
Simulation time 555524462 ps
CPU time 1.06 seconds
Started May 14 04:17:11 PM PDT 24
Finished May 14 04:17:15 PM PDT 24
Peak memory 183548 kb
Host smart-77884e6a-f180-424b-92c6-0d798152d483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565649015 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.3565649015
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.2674809577
Short name T267
Test name
Test status
Simulation time 26948970606 ps
CPU time 39.34 seconds
Started May 14 04:17:12 PM PDT 24
Finished May 14 04:17:54 PM PDT 24
Peak memory 191884 kb
Host smart-8ca7f345-404a-4bbb-b300-d2cfde72dda9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674809577 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.2674809577
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.1556447774
Short name T126
Test name
Test status
Simulation time 478236068 ps
CPU time 0.68 seconds
Started May 14 04:17:10 PM PDT 24
Finished May 14 04:17:14 PM PDT 24
Peak memory 183604 kb
Host smart-c8fa1d1c-8381-495c-be98-8528dc911001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556447774 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.1556447774
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.1660583811
Short name T149
Test name
Test status
Simulation time 173139851594 ps
CPU time 204.3 seconds
Started May 14 04:17:10 PM PDT 24
Finished May 14 04:20:37 PM PDT 24
Peak memory 183660 kb
Host smart-94a41d93-a3ff-44f6-aafa-6b25f02f7e24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660583811 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_
all.1660583811
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_jump.3141451778
Short name T109
Test name
Test status
Simulation time 420267957 ps
CPU time 1.12 seconds
Started May 14 04:16:15 PM PDT 24
Finished May 14 04:16:18 PM PDT 24
Peak memory 183608 kb
Host smart-b449ae86-637e-4dcf-b461-eef3cfa34be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141451778 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.3141451778
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.1597843802
Short name T27
Test name
Test status
Simulation time 52730724559 ps
CPU time 91.25 seconds
Started May 14 04:16:15 PM PDT 24
Finished May 14 04:17:48 PM PDT 24
Peak memory 183580 kb
Host smart-dd07f4b8-457a-43b2-8026-7dffc0d1f83a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597843802 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.1597843802
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.4137622032
Short name T14
Test name
Test status
Simulation time 3901517738 ps
CPU time 1.23 seconds
Started May 14 04:16:15 PM PDT 24
Finished May 14 04:16:18 PM PDT 24
Peak memory 214852 kb
Host smart-d2cf7772-78be-4145-8baf-c5e9a9e7b613
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137622032 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.4137622032
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.833066354
Short name T222
Test name
Test status
Simulation time 432977115 ps
CPU time 0.85 seconds
Started May 14 04:16:15 PM PDT 24
Finished May 14 04:16:18 PM PDT 24
Peak memory 183692 kb
Host smart-2362ea33-34d7-4ec6-98f7-0fc4bd3a4263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833066354 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.833066354
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.460343018
Short name T139
Test name
Test status
Simulation time 41978820757 ps
CPU time 14.48 seconds
Started May 14 04:16:18 PM PDT 24
Finished May 14 04:16:34 PM PDT 24
Peak memory 193092 kb
Host smart-e5ba78c7-2daa-462a-b4f5-525163384586
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460343018 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_al
l.460343018
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.2749364664
Short name T73
Test name
Test status
Simulation time 13931890759 ps
CPU time 98.51 seconds
Started May 14 04:16:14 PM PDT 24
Finished May 14 04:17:55 PM PDT 24
Peak memory 198448 kb
Host smart-5ad919c7-da1c-4533-af78-027a7896e336
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749364664 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.2749364664
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_jump.1699528286
Short name T103
Test name
Test status
Simulation time 413076457 ps
CPU time 1.28 seconds
Started May 14 04:17:12 PM PDT 24
Finished May 14 04:17:16 PM PDT 24
Peak memory 183668 kb
Host smart-76c38488-a4ad-49b7-948b-c195022eaca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699528286 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.1699528286
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.1872939600
Short name T24
Test name
Test status
Simulation time 22876367340 ps
CPU time 9.81 seconds
Started May 14 04:17:12 PM PDT 24
Finished May 14 04:17:25 PM PDT 24
Peak memory 183644 kb
Host smart-e9b3f6b7-5dd5-4551-8f7f-b9c2ed5e5e87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872939600 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.1872939600
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.2261654749
Short name T167
Test name
Test status
Simulation time 476715972 ps
CPU time 0.91 seconds
Started May 14 04:17:11 PM PDT 24
Finished May 14 04:17:15 PM PDT 24
Peak memory 183580 kb
Host smart-0b32e0bc-6a93-4f6e-b66a-123c747d47ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261654749 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.2261654749
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.3291092264
Short name T220
Test name
Test status
Simulation time 156792590382 ps
CPU time 258.14 seconds
Started May 14 04:17:10 PM PDT 24
Finished May 14 04:21:32 PM PDT 24
Peak memory 195304 kb
Host smart-079d57b9-b623-4540-8796-95b8561dbe33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291092264 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_
all.3291092264
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.4201431955
Short name T163
Test name
Test status
Simulation time 89995444549 ps
CPU time 439 seconds
Started May 14 04:17:09 PM PDT 24
Finished May 14 04:24:32 PM PDT 24
Peak memory 198552 kb
Host smart-9d1ac056-3cdf-456c-b040-95c997f0a30b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201431955 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.4201431955
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.aon_timer_jump.3020639730
Short name T161
Test name
Test status
Simulation time 486091636 ps
CPU time 0.91 seconds
Started May 14 04:17:09 PM PDT 24
Finished May 14 04:17:13 PM PDT 24
Peak memory 183604 kb
Host smart-1b31c595-b506-43a4-b700-2361c0342787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020639730 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.3020639730
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.2690861019
Short name T124
Test name
Test status
Simulation time 29723084789 ps
CPU time 10.52 seconds
Started May 14 04:17:12 PM PDT 24
Finished May 14 04:17:26 PM PDT 24
Peak memory 183668 kb
Host smart-31e7a789-2144-426b-a451-25216374b472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690861019 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.2690861019
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.918876842
Short name T100
Test name
Test status
Simulation time 409257052 ps
CPU time 1.14 seconds
Started May 14 04:17:09 PM PDT 24
Finished May 14 04:17:14 PM PDT 24
Peak memory 183628 kb
Host smart-96ac555a-6ad2-4940-8e6e-b9c9cacae43c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918876842 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.918876842
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.1726230717
Short name T46
Test name
Test status
Simulation time 136042539196 ps
CPU time 212.71 seconds
Started May 14 04:17:11 PM PDT 24
Finished May 14 04:20:46 PM PDT 24
Peak memory 183672 kb
Host smart-8e44c54d-c8a2-4a7f-bebb-5d92d8c72b52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726230717 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_
all.1726230717
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.1459969416
Short name T258
Test name
Test status
Simulation time 11521967388 ps
CPU time 79.18 seconds
Started May 14 04:17:10 PM PDT 24
Finished May 14 04:18:33 PM PDT 24
Peak memory 198480 kb
Host smart-65365e3e-33cd-4ddd-9ee8-794dd9b8772c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459969416 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.1459969416
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.aon_timer_jump.3246099804
Short name T122
Test name
Test status
Simulation time 436353299 ps
CPU time 0.9 seconds
Started May 14 04:17:12 PM PDT 24
Finished May 14 04:17:15 PM PDT 24
Peak memory 183688 kb
Host smart-6237f4eb-c697-419d-9925-8ef40167488a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246099804 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.3246099804
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.3480482419
Short name T143
Test name
Test status
Simulation time 10814905504 ps
CPU time 17.75 seconds
Started May 14 04:17:14 PM PDT 24
Finished May 14 04:17:34 PM PDT 24
Peak memory 183640 kb
Host smart-f7b4b692-95ec-421c-8180-7a81978db9f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480482419 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.3480482419
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.2339785365
Short name T162
Test name
Test status
Simulation time 467529861 ps
CPU time 1.33 seconds
Started May 14 04:17:11 PM PDT 24
Finished May 14 04:17:15 PM PDT 24
Peak memory 183572 kb
Host smart-697fdaf4-4bd1-480b-a725-d276b114dd76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339785365 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.2339785365
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.1534149427
Short name T157
Test name
Test status
Simulation time 140085697434 ps
CPU time 19.3 seconds
Started May 14 04:17:12 PM PDT 24
Finished May 14 04:17:34 PM PDT 24
Peak memory 183740 kb
Host smart-867c2cf1-6c7a-4ae6-9386-542fea9eff5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534149427 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_
all.1534149427
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.2745980701
Short name T230
Test name
Test status
Simulation time 20476016285 ps
CPU time 112.6 seconds
Started May 14 04:17:12 PM PDT 24
Finished May 14 04:19:07 PM PDT 24
Peak memory 198576 kb
Host smart-86bccc06-ff2c-4253-b2dc-4cfabaef4658
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745980701 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_reset.2745980701
Directory /workspace/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.aon_timer_jump.2764679800
Short name T243
Test name
Test status
Simulation time 415882471 ps
CPU time 0.92 seconds
Started May 14 04:17:10 PM PDT 24
Finished May 14 04:17:14 PM PDT 24
Peak memory 183572 kb
Host smart-24922cd1-731b-4661-9fd4-cf7aa7a2e0c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764679800 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.2764679800
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.1636823017
Short name T259
Test name
Test status
Simulation time 27643082506 ps
CPU time 42.42 seconds
Started May 14 04:17:11 PM PDT 24
Finished May 14 04:17:56 PM PDT 24
Peak memory 183668 kb
Host smart-615d6126-e9d2-4ccc-af0c-24da9d6f2d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636823017 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.1636823017
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.1333956338
Short name T97
Test name
Test status
Simulation time 354482664 ps
CPU time 1.05 seconds
Started May 14 04:17:10 PM PDT 24
Finished May 14 04:17:14 PM PDT 24
Peak memory 183596 kb
Host smart-5b30d108-8337-436a-9120-806f0abef8af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333956338 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.1333956338
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.2831519174
Short name T41
Test name
Test status
Simulation time 89033933762 ps
CPU time 67.54 seconds
Started May 14 04:17:13 PM PDT 24
Finished May 14 04:18:23 PM PDT 24
Peak memory 194200 kb
Host smart-ef6ab3d4-824c-4873-99fd-46e711c97009
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831519174 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_
all.2831519174
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.409467202
Short name T252
Test name
Test status
Simulation time 169790449668 ps
CPU time 340.83 seconds
Started May 14 04:17:12 PM PDT 24
Finished May 14 04:22:55 PM PDT 24
Peak memory 198584 kb
Host smart-7a063fdd-4da6-4193-8dda-cf7c88d33796
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409467202 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.409467202
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.aon_timer_jump.3510556075
Short name T206
Test name
Test status
Simulation time 521474112 ps
CPU time 1.29 seconds
Started May 14 04:17:15 PM PDT 24
Finished May 14 04:17:18 PM PDT 24
Peak memory 183488 kb
Host smart-ce268a6d-0d8f-4d5d-af9f-619196e77f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510556075 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.3510556075
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.2194890507
Short name T79
Test name
Test status
Simulation time 1358006844 ps
CPU time 2.25 seconds
Started May 14 04:17:14 PM PDT 24
Finished May 14 04:17:19 PM PDT 24
Peak memory 183544 kb
Host smart-836fc69a-2940-4bc7-b404-b123e356e42e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194890507 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.2194890507
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.2002207657
Short name T91
Test name
Test status
Simulation time 346629583 ps
CPU time 1.11 seconds
Started May 14 04:17:10 PM PDT 24
Finished May 14 04:17:14 PM PDT 24
Peak memory 183604 kb
Host smart-00e929e0-13a0-44ca-8873-3e0928eecbcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002207657 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.2002207657
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.1689849007
Short name T257
Test name
Test status
Simulation time 30977839241 ps
CPU time 24.74 seconds
Started May 14 04:17:15 PM PDT 24
Finished May 14 04:17:42 PM PDT 24
Peak memory 183660 kb
Host smart-10af2b29-82a4-43c0-8a12-dba8a2c6ac2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689849007 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_
all.1689849007
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/35.aon_timer_jump.1675041201
Short name T104
Test name
Test status
Simulation time 532514934 ps
CPU time 0.7 seconds
Started May 14 04:17:15 PM PDT 24
Finished May 14 04:17:18 PM PDT 24
Peak memory 183512 kb
Host smart-9149e60a-c48f-4745-a622-d7cdfc3ec3b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675041201 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.1675041201
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.1939809220
Short name T123
Test name
Test status
Simulation time 37215731465 ps
CPU time 12.31 seconds
Started May 14 04:17:18 PM PDT 24
Finished May 14 04:17:32 PM PDT 24
Peak memory 191884 kb
Host smart-8d9e9b39-4cce-4653-8aca-419ed457ab7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939809220 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.1939809220
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.1939482693
Short name T263
Test name
Test status
Simulation time 471515072 ps
CPU time 1.28 seconds
Started May 14 04:17:15 PM PDT 24
Finished May 14 04:17:19 PM PDT 24
Peak memory 183572 kb
Host smart-48e0a8e2-6a01-4ece-b3e6-170148ef0341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939482693 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.1939482693
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.3124670866
Short name T197
Test name
Test status
Simulation time 53067565664 ps
CPU time 228.8 seconds
Started May 14 04:17:15 PM PDT 24
Finished May 14 04:21:06 PM PDT 24
Peak memory 198524 kb
Host smart-33d3b7bc-914f-4e58-b091-981ff27a1036
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124670866 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.3124670866
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.aon_timer_jump.2415626141
Short name T98
Test name
Test status
Simulation time 518886193 ps
CPU time 1.38 seconds
Started May 14 04:17:17 PM PDT 24
Finished May 14 04:17:20 PM PDT 24
Peak memory 183572 kb
Host smart-23824e95-3e9e-4200-a72f-d054ca67106b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415626141 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.2415626141
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.301491108
Short name T240
Test name
Test status
Simulation time 16121139170 ps
CPU time 26.11 seconds
Started May 14 04:17:16 PM PDT 24
Finished May 14 04:17:44 PM PDT 24
Peak memory 191820 kb
Host smart-58e18159-e7cb-4673-b317-79a8a99ab461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301491108 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.301491108
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.687443983
Short name T19
Test name
Test status
Simulation time 382672141 ps
CPU time 1 seconds
Started May 14 04:17:15 PM PDT 24
Finished May 14 04:17:18 PM PDT 24
Peak memory 183608 kb
Host smart-9dde3b8b-c089-488b-9e60-e9ab983e26c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687443983 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.687443983
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.1267289834
Short name T128
Test name
Test status
Simulation time 213136967600 ps
CPU time 45.4 seconds
Started May 14 04:17:14 PM PDT 24
Finished May 14 04:18:02 PM PDT 24
Peak memory 183648 kb
Host smart-5090de9d-ea51-447c-a256-85cf46ee5c0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267289834 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_
all.1267289834
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.854648012
Short name T276
Test name
Test status
Simulation time 89034766659 ps
CPU time 258.89 seconds
Started May 14 04:17:14 PM PDT 24
Finished May 14 04:21:35 PM PDT 24
Peak memory 198540 kb
Host smart-cc5dc56b-6886-4ff1-ace5-07df0ba7b139
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854648012 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.854648012
Directory /workspace/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.aon_timer_jump.3878748422
Short name T214
Test name
Test status
Simulation time 594977343 ps
CPU time 1.42 seconds
Started May 14 04:17:16 PM PDT 24
Finished May 14 04:17:20 PM PDT 24
Peak memory 183580 kb
Host smart-402fe820-bc4c-4457-84c8-d2ad8e207704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878748422 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.3878748422
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.3001997949
Short name T151
Test name
Test status
Simulation time 53055361223 ps
CPU time 68.59 seconds
Started May 14 04:17:18 PM PDT 24
Finished May 14 04:18:28 PM PDT 24
Peak memory 183820 kb
Host smart-942c0168-1497-46c6-83c3-b06c4c6748bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001997949 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.3001997949
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.902424097
Short name T266
Test name
Test status
Simulation time 591128587 ps
CPU time 0.95 seconds
Started May 14 04:17:17 PM PDT 24
Finished May 14 04:17:19 PM PDT 24
Peak memory 183576 kb
Host smart-f8850d05-868e-4a0f-a269-b4e80261b125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902424097 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.902424097
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_jump.3616912470
Short name T173
Test name
Test status
Simulation time 450003589 ps
CPU time 1.24 seconds
Started May 14 04:17:17 PM PDT 24
Finished May 14 04:17:20 PM PDT 24
Peak memory 183624 kb
Host smart-f6ce0028-345c-4249-b60e-9e4ac711a3c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616912470 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.3616912470
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.2612523621
Short name T164
Test name
Test status
Simulation time 20274914428 ps
CPU time 31.95 seconds
Started May 14 04:17:18 PM PDT 24
Finished May 14 04:17:52 PM PDT 24
Peak memory 183824 kb
Host smart-875435d5-205f-4a73-b6d8-fcef5228f042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612523621 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.2612523621
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.4243841581
Short name T101
Test name
Test status
Simulation time 408924635 ps
CPU time 0.69 seconds
Started May 14 04:17:14 PM PDT 24
Finished May 14 04:17:17 PM PDT 24
Peak memory 183584 kb
Host smart-0a58903b-be06-423b-816d-4fa97d347886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243841581 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.4243841581
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.1076323966
Short name T248
Test name
Test status
Simulation time 282501166530 ps
CPU time 475.59 seconds
Started May 14 04:17:17 PM PDT 24
Finished May 14 04:25:14 PM PDT 24
Peak memory 183696 kb
Host smart-3ac9bce8-c397-4473-aeae-a8d3e10c1f52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076323966 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_
all.1076323966
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.206195202
Short name T36
Test name
Test status
Simulation time 359182511621 ps
CPU time 664.33 seconds
Started May 14 04:17:14 PM PDT 24
Finished May 14 04:28:21 PM PDT 24
Peak memory 200944 kb
Host smart-856229cb-8c5f-4a6f-aa3b-e31f52c9e304
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206195202 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand_reset.206195202
Directory /workspace/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.aon_timer_jump.3352167199
Short name T189
Test name
Test status
Simulation time 457314031 ps
CPU time 0.75 seconds
Started May 14 04:17:16 PM PDT 24
Finished May 14 04:17:19 PM PDT 24
Peak memory 183608 kb
Host smart-09dbc2f0-3de6-4609-8644-6df5f0c6387a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352167199 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.3352167199
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.573425542
Short name T272
Test name
Test status
Simulation time 25764225592 ps
CPU time 8.54 seconds
Started May 14 04:17:15 PM PDT 24
Finished May 14 04:17:26 PM PDT 24
Peak memory 191848 kb
Host smart-438c4d2e-2710-4906-bde4-a2150bb4c7cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573425542 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.573425542
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.1429617204
Short name T176
Test name
Test status
Simulation time 464807626 ps
CPU time 0.7 seconds
Started May 14 04:17:18 PM PDT 24
Finished May 14 04:17:20 PM PDT 24
Peak memory 183584 kb
Host smart-d0b4cae0-008c-46b0-b4af-fcaf1a21665b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429617204 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.1429617204
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.931858119
Short name T141
Test name
Test status
Simulation time 370187566611 ps
CPU time 561.66 seconds
Started May 14 04:17:18 PM PDT 24
Finished May 14 04:26:41 PM PDT 24
Peak memory 193720 kb
Host smart-3eca9f67-d39a-419a-bdae-e32ab8712595
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931858119 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_a
ll.931858119
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.1170946131
Short name T71
Test name
Test status
Simulation time 70688822491 ps
CPU time 465.4 seconds
Started May 14 04:17:17 PM PDT 24
Finished May 14 04:25:04 PM PDT 24
Peak memory 198560 kb
Host smart-8e77403b-e725-4775-9038-9a3e29d0e362
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170946131 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.1170946131
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_jump.103937843
Short name T234
Test name
Test status
Simulation time 404580128 ps
CPU time 1.11 seconds
Started May 14 04:16:15 PM PDT 24
Finished May 14 04:16:18 PM PDT 24
Peak memory 183496 kb
Host smart-f75e06e1-7305-47e4-85a8-96ab3a71fb1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103937843 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.103937843
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.3079329709
Short name T179
Test name
Test status
Simulation time 50570138259 ps
CPU time 35.17 seconds
Started May 14 04:16:16 PM PDT 24
Finished May 14 04:16:53 PM PDT 24
Peak memory 183668 kb
Host smart-3efe2e18-28ba-41f5-984b-fc63b343b8e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079329709 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.3079329709
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.2206762473
Short name T18
Test name
Test status
Simulation time 7593567320 ps
CPU time 4.04 seconds
Started May 14 04:16:18 PM PDT 24
Finished May 14 04:16:24 PM PDT 24
Peak memory 215376 kb
Host smart-b70be94f-7f64-4da3-8a7e-ef4e1716d317
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206762473 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.2206762473
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.2123129113
Short name T152
Test name
Test status
Simulation time 546608388 ps
CPU time 0.6 seconds
Started May 14 04:16:15 PM PDT 24
Finished May 14 04:16:18 PM PDT 24
Peak memory 183560 kb
Host smart-a8069adf-de95-47f0-b379-3a891ddd46c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123129113 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.2123129113
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.2709591104
Short name T130
Test name
Test status
Simulation time 148422478174 ps
CPU time 219.84 seconds
Started May 14 04:16:15 PM PDT 24
Finished May 14 04:19:57 PM PDT 24
Peak memory 183644 kb
Host smart-1965fae5-94d6-455f-9cd9-6952be481f02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709591104 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_a
ll.2709591104
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.1326836449
Short name T78
Test name
Test status
Simulation time 156562684004 ps
CPU time 340.16 seconds
Started May 14 04:16:14 PM PDT 24
Finished May 14 04:21:56 PM PDT 24
Peak memory 198452 kb
Host smart-ca52979b-ca24-4309-b8b0-66ea00a9e8e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326836449 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.1326836449
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.aon_timer_jump.584786704
Short name T119
Test name
Test status
Simulation time 455365131 ps
CPU time 0.89 seconds
Started May 14 04:17:19 PM PDT 24
Finished May 14 04:17:21 PM PDT 24
Peak memory 183760 kb
Host smart-1f528cfe-b0e5-4554-b689-d4fde7d70331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584786704 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.584786704
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.1914909739
Short name T256
Test name
Test status
Simulation time 30838263924 ps
CPU time 21.57 seconds
Started May 14 04:17:15 PM PDT 24
Finished May 14 04:17:39 PM PDT 24
Peak memory 183588 kb
Host smart-a6cb67f4-0b39-47f2-9dab-cf7b1f43b91c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914909739 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.1914909739
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.3162420729
Short name T241
Test name
Test status
Simulation time 344245695 ps
CPU time 1.05 seconds
Started May 14 04:17:17 PM PDT 24
Finished May 14 04:17:20 PM PDT 24
Peak memory 183584 kb
Host smart-6fc14c53-cef1-433c-8441-60aad5291363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162420729 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.3162420729
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.3807812357
Short name T181
Test name
Test status
Simulation time 94579713119 ps
CPU time 69.93 seconds
Started May 14 04:17:18 PM PDT 24
Finished May 14 04:18:30 PM PDT 24
Peak memory 183692 kb
Host smart-046260f7-0d62-4f38-bf14-f132e967b7f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807812357 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_
all.3807812357
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.2438576457
Short name T40
Test name
Test status
Simulation time 50698336663 ps
CPU time 349.99 seconds
Started May 14 04:17:16 PM PDT 24
Finished May 14 04:23:08 PM PDT 24
Peak memory 198516 kb
Host smart-7080d334-687c-4d90-85b0-37536c30c3bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438576457 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.2438576457
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.aon_timer_jump.3057753874
Short name T212
Test name
Test status
Simulation time 384135446 ps
CPU time 0.88 seconds
Started May 14 04:17:24 PM PDT 24
Finished May 14 04:17:26 PM PDT 24
Peak memory 183668 kb
Host smart-60ddba51-c0f4-443a-92bc-404fc9866529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057753874 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.3057753874
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.4020845103
Short name T125
Test name
Test status
Simulation time 51586903652 ps
CPU time 13.57 seconds
Started May 14 04:17:21 PM PDT 24
Finished May 14 04:17:35 PM PDT 24
Peak memory 183656 kb
Host smart-b3f9683f-9518-47ad-9e5b-b850c1c11dd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020845103 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.4020845103
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.2148837465
Short name T11
Test name
Test status
Simulation time 622592025 ps
CPU time 0.75 seconds
Started May 14 04:17:23 PM PDT 24
Finished May 14 04:17:25 PM PDT 24
Peak memory 183568 kb
Host smart-866d5c33-5c5f-465f-9314-4e5e9a90f4a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148837465 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.2148837465
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.2351637802
Short name T115
Test name
Test status
Simulation time 126522010907 ps
CPU time 51.89 seconds
Started May 14 04:17:22 PM PDT 24
Finished May 14 04:18:15 PM PDT 24
Peak memory 183600 kb
Host smart-dc169922-b3fb-409b-81b1-02da6e0417fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351637802 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_
all.2351637802
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.4117357035
Short name T20
Test name
Test status
Simulation time 42272015123 ps
CPU time 363.15 seconds
Started May 14 04:17:21 PM PDT 24
Finished May 14 04:23:24 PM PDT 24
Peak memory 198496 kb
Host smart-e21ba41d-d447-4ebd-b2f8-0f80424123d0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117357035 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.4117357035
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.aon_timer_jump.1045853596
Short name T25
Test name
Test status
Simulation time 407874952 ps
CPU time 0.86 seconds
Started May 14 04:17:21 PM PDT 24
Finished May 14 04:17:22 PM PDT 24
Peak memory 183600 kb
Host smart-6aa1f6fd-89ef-42a2-94b9-d29a6ca7ea7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045853596 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.1045853596
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.1836695438
Short name T269
Test name
Test status
Simulation time 20559580047 ps
CPU time 29.38 seconds
Started May 14 04:17:22 PM PDT 24
Finished May 14 04:17:53 PM PDT 24
Peak memory 191884 kb
Host smart-2663a555-c4d2-4fe0-bc8d-da84c5578fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836695438 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.1836695438
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.2060248474
Short name T9
Test name
Test status
Simulation time 405025355 ps
CPU time 0.96 seconds
Started May 14 04:17:22 PM PDT 24
Finished May 14 04:17:25 PM PDT 24
Peak memory 183572 kb
Host smart-131cdadc-4a66-4623-8db5-da7bf08bb841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060248474 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.2060248474
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.4057891979
Short name T159
Test name
Test status
Simulation time 68263817768 ps
CPU time 16.53 seconds
Started May 14 04:17:24 PM PDT 24
Finished May 14 04:17:42 PM PDT 24
Peak memory 183808 kb
Host smart-cfecd547-18e6-40da-8858-49d48745def9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057891979 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_
all.4057891979
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_jump.4257874220
Short name T165
Test name
Test status
Simulation time 563179033 ps
CPU time 0.79 seconds
Started May 14 04:17:22 PM PDT 24
Finished May 14 04:17:23 PM PDT 24
Peak memory 183596 kb
Host smart-7393980d-45c1-40f6-ac08-4f369f25bc91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257874220 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.4257874220
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.4213798224
Short name T168
Test name
Test status
Simulation time 34880019455 ps
CPU time 12.17 seconds
Started May 14 04:17:23 PM PDT 24
Finished May 14 04:17:37 PM PDT 24
Peak memory 183632 kb
Host smart-52564e54-04b5-4b5d-95dc-22c77e2b20bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213798224 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.4213798224
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.1718043616
Short name T171
Test name
Test status
Simulation time 456986558 ps
CPU time 1.08 seconds
Started May 14 04:17:23 PM PDT 24
Finished May 14 04:17:26 PM PDT 24
Peak memory 183640 kb
Host smart-e6ea0be8-9747-4c4e-9603-f29cadfaecd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718043616 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.1718043616
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.1285647146
Short name T218
Test name
Test status
Simulation time 3935641949 ps
CPU time 3.44 seconds
Started May 14 04:17:23 PM PDT 24
Finished May 14 04:17:28 PM PDT 24
Peak memory 193972 kb
Host smart-e70da14b-a7e7-41d5-9cb5-f2ea64bca636
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285647146 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_
all.1285647146
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.3647363662
Short name T70
Test name
Test status
Simulation time 56360952087 ps
CPU time 447.9 seconds
Started May 14 04:17:23 PM PDT 24
Finished May 14 04:24:52 PM PDT 24
Peak memory 198540 kb
Host smart-e44c28da-4f66-4dc3-8f5e-5b631bbdcd97
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647363662 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.3647363662
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.aon_timer_jump.971772911
Short name T270
Test name
Test status
Simulation time 400609840 ps
CPU time 1.13 seconds
Started May 14 04:17:21 PM PDT 24
Finished May 14 04:17:23 PM PDT 24
Peak memory 183500 kb
Host smart-856d4a86-8423-47ec-adba-eb7ed905097e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971772911 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.971772911
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.47523374
Short name T144
Test name
Test status
Simulation time 7451294214 ps
CPU time 11.7 seconds
Started May 14 04:17:22 PM PDT 24
Finished May 14 04:17:35 PM PDT 24
Peak memory 183636 kb
Host smart-f8c6e167-ab6a-43dd-bc81-4c0e188b07ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47523374 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.47523374
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.414225700
Short name T254
Test name
Test status
Simulation time 476273688 ps
CPU time 0.78 seconds
Started May 14 04:17:21 PM PDT 24
Finished May 14 04:17:23 PM PDT 24
Peak memory 183628 kb
Host smart-30ab58fb-cc16-416b-a865-651381996ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414225700 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.414225700
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.224114167
Short name T118
Test name
Test status
Simulation time 86600972124 ps
CPU time 7.62 seconds
Started May 14 04:17:20 PM PDT 24
Finished May 14 04:17:29 PM PDT 24
Peak memory 195136 kb
Host smart-30a194c7-d63f-4aef-aa33-2dccf4a71741
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224114167 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_a
ll.224114167
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.4022111109
Short name T231
Test name
Test status
Simulation time 56702465926 ps
CPU time 230.65 seconds
Started May 14 04:17:22 PM PDT 24
Finished May 14 04:21:14 PM PDT 24
Peak memory 198548 kb
Host smart-2a20a2f4-833d-48fa-9cc6-42f7fb510bb4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022111109 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.4022111109
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.aon_timer_jump.1028201246
Short name T213
Test name
Test status
Simulation time 385198554 ps
CPU time 1.16 seconds
Started May 14 04:17:28 PM PDT 24
Finished May 14 04:17:30 PM PDT 24
Peak memory 183592 kb
Host smart-648f1072-29cb-4ce2-a933-2b203b075312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028201246 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.1028201246
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.1853854060
Short name T245
Test name
Test status
Simulation time 11119892750 ps
CPU time 4.25 seconds
Started May 14 04:17:32 PM PDT 24
Finished May 14 04:17:37 PM PDT 24
Peak memory 183684 kb
Host smart-a5f4682d-d625-44cc-aa98-0cb036e8e03c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853854060 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.1853854060
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.399933317
Short name T107
Test name
Test status
Simulation time 505285674 ps
CPU time 0.72 seconds
Started May 14 04:17:29 PM PDT 24
Finished May 14 04:17:31 PM PDT 24
Peak memory 183608 kb
Host smart-59c0166a-0afc-43cb-a550-9dd1231e11cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399933317 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.399933317
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.2877107338
Short name T12
Test name
Test status
Simulation time 59282728379 ps
CPU time 100.31 seconds
Started May 14 04:17:28 PM PDT 24
Finished May 14 04:19:09 PM PDT 24
Peak memory 194416 kb
Host smart-6de8472c-fc1e-4010-8923-9d1349b2e904
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877107338 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_
all.2877107338
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/46.aon_timer_jump.1019941765
Short name T261
Test name
Test status
Simulation time 397241545 ps
CPU time 1.15 seconds
Started May 14 04:17:29 PM PDT 24
Finished May 14 04:17:31 PM PDT 24
Peak memory 183528 kb
Host smart-5acc2d9e-b971-46a7-9e6b-83459d5de9de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019941765 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.1019941765
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.4261238414
Short name T180
Test name
Test status
Simulation time 22174023046 ps
CPU time 32.96 seconds
Started May 14 04:17:29 PM PDT 24
Finished May 14 04:18:03 PM PDT 24
Peak memory 183752 kb
Host smart-fac56ee4-20a0-44c0-b499-41e9567ec126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261238414 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.4261238414
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.590625120
Short name T93
Test name
Test status
Simulation time 592540520 ps
CPU time 1.04 seconds
Started May 14 04:17:29 PM PDT 24
Finished May 14 04:17:31 PM PDT 24
Peak memory 183596 kb
Host smart-372ab970-502e-4533-bfef-a244ea3de4dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590625120 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.590625120
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.3193883769
Short name T249
Test name
Test status
Simulation time 352688992854 ps
CPU time 136.1 seconds
Started May 14 04:17:28 PM PDT 24
Finished May 14 04:19:45 PM PDT 24
Peak memory 195176 kb
Host smart-5d226866-c3b3-4f20-9638-93f9e1fc6c43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193883769 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_
all.3193883769
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_jump.3124458715
Short name T134
Test name
Test status
Simulation time 529361301 ps
CPU time 1.38 seconds
Started May 14 04:17:37 PM PDT 24
Finished May 14 04:17:40 PM PDT 24
Peak memory 183544 kb
Host smart-c32ba8e9-0962-4ef0-a60e-aa1e9c21ca74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124458715 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.3124458715
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.3923831522
Short name T221
Test name
Test status
Simulation time 16375507545 ps
CPU time 25.42 seconds
Started May 14 04:17:30 PM PDT 24
Finished May 14 04:17:56 PM PDT 24
Peak memory 183664 kb
Host smart-51f1a319-8487-4b41-afe4-57345c32bbcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923831522 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.3923831522
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.2984868157
Short name T169
Test name
Test status
Simulation time 340894041 ps
CPU time 1.09 seconds
Started May 14 04:17:28 PM PDT 24
Finished May 14 04:17:30 PM PDT 24
Peak memory 183612 kb
Host smart-81d57f4e-6e99-4a33-ad85-2ce436f7be20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984868157 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.2984868157
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.2974402723
Short name T83
Test name
Test status
Simulation time 9616413003 ps
CPU time 4.54 seconds
Started May 14 04:17:37 PM PDT 24
Finished May 14 04:17:43 PM PDT 24
Peak memory 183628 kb
Host smart-c115fc9a-566f-46e0-8731-f3b685214138
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974402723 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_
all.2974402723
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.2252983306
Short name T219
Test name
Test status
Simulation time 115206150137 ps
CPU time 311.93 seconds
Started May 14 04:17:36 PM PDT 24
Finished May 14 04:22:49 PM PDT 24
Peak memory 206704 kb
Host smart-a3d446d9-672a-4dcf-9517-63919d16fc46
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252983306 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.2252983306
Directory /workspace/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_jump.2542112527
Short name T142
Test name
Test status
Simulation time 496382273 ps
CPU time 0.74 seconds
Started May 14 04:17:38 PM PDT 24
Finished May 14 04:17:41 PM PDT 24
Peak memory 183596 kb
Host smart-70a49827-af15-433b-92dd-9019ec0235a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542112527 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.2542112527
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.2478011733
Short name T184
Test name
Test status
Simulation time 32330431714 ps
CPU time 43.89 seconds
Started May 14 04:17:36 PM PDT 24
Finished May 14 04:18:20 PM PDT 24
Peak memory 191884 kb
Host smart-34175a5d-c021-4b20-8c23-56e6efc7c0bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478011733 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.2478011733
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.944050751
Short name T216
Test name
Test status
Simulation time 383872526 ps
CPU time 0.82 seconds
Started May 14 04:17:37 PM PDT 24
Finished May 14 04:17:40 PM PDT 24
Peak memory 183560 kb
Host smart-2aeab02f-23e1-4631-943f-fab91d4f2a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944050751 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.944050751
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.1642749005
Short name T183
Test name
Test status
Simulation time 17900925141 ps
CPU time 3.17 seconds
Started May 14 04:17:37 PM PDT 24
Finished May 14 04:17:42 PM PDT 24
Peak memory 195512 kb
Host smart-73c78d1a-c6ef-4b7b-b91b-f34f30c4f5e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642749005 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_
all.1642749005
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.870719448
Short name T76
Test name
Test status
Simulation time 48937193709 ps
CPU time 389.27 seconds
Started May 14 04:17:36 PM PDT 24
Finished May 14 04:24:06 PM PDT 24
Peak memory 198564 kb
Host smart-abbb7fb6-059a-42f7-b6b3-93619affff48
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870719448 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.870719448
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.aon_timer_jump.3369290057
Short name T154
Test name
Test status
Simulation time 411779062 ps
CPU time 0.63 seconds
Started May 14 04:17:37 PM PDT 24
Finished May 14 04:17:39 PM PDT 24
Peak memory 183600 kb
Host smart-c4ee0c09-b6fc-48c9-9c2a-f70a732a9447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369290057 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.3369290057
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.636639564
Short name T129
Test name
Test status
Simulation time 59971280263 ps
CPU time 95.23 seconds
Started May 14 04:17:36 PM PDT 24
Finished May 14 04:19:13 PM PDT 24
Peak memory 191880 kb
Host smart-2773d068-471a-49be-9267-0370ded86bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636639564 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.636639564
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.2392317029
Short name T274
Test name
Test status
Simulation time 436524877 ps
CPU time 1.22 seconds
Started May 14 04:17:39 PM PDT 24
Finished May 14 04:17:41 PM PDT 24
Peak memory 183612 kb
Host smart-0838944f-0655-441a-99cf-7b185a112bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392317029 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.2392317029
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.3240558607
Short name T204
Test name
Test status
Simulation time 56445454090 ps
CPU time 19.6 seconds
Started May 14 04:17:38 PM PDT 24
Finished May 14 04:18:00 PM PDT 24
Peak memory 183588 kb
Host smart-72c59768-78e6-4ec6-8535-ef8f2a68fae2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240558607 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_
all.3240558607
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_jump.2026255691
Short name T44
Test name
Test status
Simulation time 435869768 ps
CPU time 1.16 seconds
Started May 14 04:16:21 PM PDT 24
Finished May 14 04:16:24 PM PDT 24
Peak memory 183512 kb
Host smart-844cc45a-9b8b-49dd-9221-0c53daed1128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026255691 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.2026255691
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.502833024
Short name T244
Test name
Test status
Simulation time 40733870590 ps
CPU time 62.73 seconds
Started May 14 04:16:22 PM PDT 24
Finished May 14 04:17:27 PM PDT 24
Peak memory 183676 kb
Host smart-1bc6e8a0-ed4b-4b8b-be93-0c715fe3a983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502833024 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.502833024
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.1260237028
Short name T102
Test name
Test status
Simulation time 491770532 ps
CPU time 1.19 seconds
Started May 14 04:16:18 PM PDT 24
Finished May 14 04:16:21 PM PDT 24
Peak memory 183636 kb
Host smart-f6ca0322-0dab-419a-a950-510b82771e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260237028 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.1260237028
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.2591299031
Short name T186
Test name
Test status
Simulation time 166240481717 ps
CPU time 251.66 seconds
Started May 14 04:16:21 PM PDT 24
Finished May 14 04:20:35 PM PDT 24
Peak memory 183616 kb
Host smart-c3937da4-5dfc-410a-8e91-fb2381c74d28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591299031 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_a
ll.2591299031
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_jump.858935891
Short name T72
Test name
Test status
Simulation time 344178426 ps
CPU time 1.02 seconds
Started May 14 04:16:23 PM PDT 24
Finished May 14 04:16:26 PM PDT 24
Peak memory 183560 kb
Host smart-2c11b150-431a-4c4f-a781-21c32fa85b6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858935891 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.858935891
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.4208765219
Short name T132
Test name
Test status
Simulation time 34960091847 ps
CPU time 25.73 seconds
Started May 14 04:16:22 PM PDT 24
Finished May 14 04:16:49 PM PDT 24
Peak memory 191872 kb
Host smart-e8f8adff-3b58-45d9-b1dc-b70726a90b05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208765219 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.4208765219
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.1514997859
Short name T232
Test name
Test status
Simulation time 518266849 ps
CPU time 1.3 seconds
Started May 14 04:16:24 PM PDT 24
Finished May 14 04:16:28 PM PDT 24
Peak memory 183568 kb
Host smart-985f01d7-30d3-4a4d-9b09-d7642142d510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514997859 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.1514997859
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.1248687013
Short name T166
Test name
Test status
Simulation time 306958821400 ps
CPU time 561.38 seconds
Started May 14 04:16:23 PM PDT 24
Finished May 14 04:25:47 PM PDT 24
Peak memory 198672 kb
Host smart-4cb717e6-6683-4112-9a51-ceb843109257
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248687013 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.1248687013
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.aon_timer_jump.1230110485
Short name T223
Test name
Test status
Simulation time 606606969 ps
CPU time 0.61 seconds
Started May 14 04:16:24 PM PDT 24
Finished May 14 04:16:27 PM PDT 24
Peak memory 183576 kb
Host smart-80186a54-7232-42ee-b614-afa273aa0fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230110485 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.1230110485
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.734494164
Short name T229
Test name
Test status
Simulation time 55016688568 ps
CPU time 19.02 seconds
Started May 14 04:16:24 PM PDT 24
Finished May 14 04:16:45 PM PDT 24
Peak memory 183640 kb
Host smart-6a989008-86a9-42db-a4d4-d9fec6814e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734494164 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.734494164
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.3197570265
Short name T268
Test name
Test status
Simulation time 381016477 ps
CPU time 1.18 seconds
Started May 14 04:16:22 PM PDT 24
Finished May 14 04:16:25 PM PDT 24
Peak memory 183608 kb
Host smart-4b0e84c9-dc42-4197-8457-72f94f0c60e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197570265 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.3197570265
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.402827532
Short name T273
Test name
Test status
Simulation time 218176928009 ps
CPU time 71.71 seconds
Started May 14 04:16:28 PM PDT 24
Finished May 14 04:17:42 PM PDT 24
Peak memory 194708 kb
Host smart-8c2102fe-c14f-4bbf-a891-c98aaf6dbc32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402827532 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_al
l.402827532
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.2835273815
Short name T137
Test name
Test status
Simulation time 9458969408 ps
CPU time 98.66 seconds
Started May 14 04:16:23 PM PDT 24
Finished May 14 04:18:04 PM PDT 24
Peak memory 198564 kb
Host smart-94769ee4-809b-4e21-87e8-c71083920593
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835273815 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.2835273815
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.aon_timer_jump.1219331161
Short name T148
Test name
Test status
Simulation time 598028322 ps
CPU time 0.68 seconds
Started May 14 04:16:27 PM PDT 24
Finished May 14 04:16:30 PM PDT 24
Peak memory 183692 kb
Host smart-d81b2d3d-c894-4679-9861-a02943767f09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219331161 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.1219331161
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.1056747311
Short name T199
Test name
Test status
Simulation time 24132901425 ps
CPU time 32.13 seconds
Started May 14 04:16:27 PM PDT 24
Finished May 14 04:17:01 PM PDT 24
Peak memory 191872 kb
Host smart-d993bd21-1912-458e-8766-2564c079a089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056747311 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.1056747311
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.2549886142
Short name T111
Test name
Test status
Simulation time 426695695 ps
CPU time 1.12 seconds
Started May 14 04:16:27 PM PDT 24
Finished May 14 04:16:30 PM PDT 24
Peak memory 183560 kb
Host smart-8cc65282-5846-47b5-b832-dbc7d07dddb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549886142 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.2549886142
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.3489019560
Short name T45
Test name
Test status
Simulation time 34796998462 ps
CPU time 13.94 seconds
Started May 14 04:16:29 PM PDT 24
Finished May 14 04:16:45 PM PDT 24
Peak memory 195288 kb
Host smart-df05f268-fe5b-416c-a34c-e860b8c56d8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489019560 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_a
ll.3489019560
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.2511587067
Short name T75
Test name
Test status
Simulation time 426394200036 ps
CPU time 497.88 seconds
Started May 14 04:16:27 PM PDT 24
Finished May 14 04:24:47 PM PDT 24
Peak memory 198464 kb
Host smart-cf6878d3-b7ea-4395-9bef-2ae3ad688475
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511587067 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.2511587067
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.aon_timer_jump.3376188090
Short name T177
Test name
Test status
Simulation time 417339652 ps
CPU time 0.72 seconds
Started May 14 04:16:27 PM PDT 24
Finished May 14 04:16:31 PM PDT 24
Peak memory 183572 kb
Host smart-edaa252f-fc89-4f4e-b410-e0dd92f78364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376188090 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.3376188090
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.1428916504
Short name T202
Test name
Test status
Simulation time 7325826900 ps
CPU time 12.91 seconds
Started May 14 04:16:29 PM PDT 24
Finished May 14 04:16:44 PM PDT 24
Peak memory 183636 kb
Host smart-b6c0a160-afb6-418d-a6d0-c3c92399c64e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428916504 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.1428916504
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.1001476207
Short name T175
Test name
Test status
Simulation time 383168952 ps
CPU time 1.1 seconds
Started May 14 04:16:27 PM PDT 24
Finished May 14 04:16:30 PM PDT 24
Peak memory 183544 kb
Host smart-84fdb9eb-df8c-4bf0-802b-fbbc8719f7f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001476207 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.1001476207
Directory /workspace/9.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.1427885776
Short name T116
Test name
Test status
Simulation time 106530473636 ps
CPU time 172.23 seconds
Started May 14 04:16:32 PM PDT 24
Finished May 14 04:19:25 PM PDT 24
Peak memory 194148 kb
Host smart-31374ce6-7324-47f8-8f7f-822104a39f30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427885776 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_a
ll.1427885776
Directory /workspace/9.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.452484238
Short name T35
Test name
Test status
Simulation time 66943257297 ps
CPU time 753.75 seconds
Started May 14 04:16:29 PM PDT 24
Finished May 14 04:29:05 PM PDT 24
Peak memory 199908 kb
Host smart-c0b0fc56-9135-42b6-8a59-279bcbd4f70e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452484238 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.452484238
Directory /workspace/9.aon_timer_stress_all_with_rand_reset/latest
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