Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
92.98 99.25 93.67 100.00 98.40 99.51 67.06


Total test records in report: 413
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html
T34 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.1852868808 May 16 01:50:22 PM PDT 24 May 16 01:50:29 PM PDT 24 3863066486 ps
T35 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.294074655 May 16 01:50:54 PM PDT 24 May 16 01:51:02 PM PDT 24 4330713203 ps
T99 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.541329771 May 16 01:50:20 PM PDT 24 May 16 01:50:24 PM PDT 24 386184516 ps
T283 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.1456749530 May 16 01:50:33 PM PDT 24 May 16 01:50:36 PM PDT 24 407083806 ps
T69 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.2719102313 May 16 01:51:04 PM PDT 24 May 16 01:51:09 PM PDT 24 1294709063 ps
T284 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.1066988228 May 16 01:51:38 PM PDT 24 May 16 01:51:41 PM PDT 24 406603919 ps
T55 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.3049868876 May 16 01:51:19 PM PDT 24 May 16 01:51:21 PM PDT 24 354678330 ps
T285 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.3920869572 May 16 01:50:19 PM PDT 24 May 16 01:50:20 PM PDT 24 419436545 ps
T286 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.1471321393 May 16 01:51:32 PM PDT 24 May 16 01:51:36 PM PDT 24 299314930 ps
T287 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.1298640135 May 16 01:51:38 PM PDT 24 May 16 01:51:40 PM PDT 24 325661523 ps
T70 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.2240730822 May 16 01:51:29 PM PDT 24 May 16 01:51:32 PM PDT 24 1773057274 ps
T71 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.3382120699 May 16 01:50:45 PM PDT 24 May 16 01:50:49 PM PDT 24 2607459504 ps
T72 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.857801156 May 16 01:50:21 PM PDT 24 May 16 01:50:26 PM PDT 24 1447099597 ps
T56 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.3564103824 May 16 01:50:33 PM PDT 24 May 16 01:50:52 PM PDT 24 11181701413 ps
T288 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.2678322071 May 16 01:50:35 PM PDT 24 May 16 01:51:04 PM PDT 24 13936096831 ps
T37 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.3052551426 May 16 01:50:33 PM PDT 24 May 16 01:50:41 PM PDT 24 4200681934 ps
T289 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.853787605 May 16 01:50:20 PM PDT 24 May 16 01:50:25 PM PDT 24 445874178 ps
T290 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.674618916 May 16 01:51:21 PM PDT 24 May 16 01:51:24 PM PDT 24 557010250 ps
T291 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.2156853387 May 16 01:50:22 PM PDT 24 May 16 01:50:27 PM PDT 24 770142922 ps
T292 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.3710382543 May 16 01:51:39 PM PDT 24 May 16 01:51:42 PM PDT 24 308830228 ps
T293 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.1326307156 May 16 01:50:21 PM PDT 24 May 16 01:50:25 PM PDT 24 733060404 ps
T91 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.1700977283 May 16 01:51:20 PM PDT 24 May 16 01:51:30 PM PDT 24 4421972772 ps
T294 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.1500173577 May 16 01:50:34 PM PDT 24 May 16 01:50:36 PM PDT 24 419336766 ps
T57 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.856445422 May 16 01:50:33 PM PDT 24 May 16 01:50:36 PM PDT 24 513449019 ps
T295 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.186920182 May 16 01:51:29 PM PDT 24 May 16 01:51:33 PM PDT 24 798284485 ps
T296 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.1764964713 May 16 01:51:30 PM PDT 24 May 16 01:51:34 PM PDT 24 535137775 ps
T297 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.1364154073 May 16 01:50:21 PM PDT 24 May 16 01:50:26 PM PDT 24 396831440 ps
T73 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.2173107017 May 16 01:50:44 PM PDT 24 May 16 01:50:49 PM PDT 24 1568623248 ps
T298 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.853847834 May 16 01:51:32 PM PDT 24 May 16 01:51:35 PM PDT 24 470300614 ps
T299 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.3109237136 May 16 01:51:31 PM PDT 24 May 16 01:51:34 PM PDT 24 457061726 ps
T58 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.3795274811 May 16 01:50:25 PM PDT 24 May 16 01:50:28 PM PDT 24 542394339 ps
T300 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.2568729634 May 16 01:51:31 PM PDT 24 May 16 01:51:35 PM PDT 24 422323204 ps
T301 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.2503668931 May 16 01:51:04 PM PDT 24 May 16 01:51:07 PM PDT 24 467336236 ps
T302 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.841430491 May 16 01:51:30 PM PDT 24 May 16 01:51:34 PM PDT 24 480835444 ps
T303 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.1813274451 May 16 01:51:19 PM PDT 24 May 16 01:51:22 PM PDT 24 357020616 ps
T304 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.1011004772 May 16 01:50:26 PM PDT 24 May 16 01:50:29 PM PDT 24 476414424 ps
T305 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.2870047384 May 16 01:51:03 PM PDT 24 May 16 01:51:05 PM PDT 24 369717000 ps
T64 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.532364675 May 16 01:50:33 PM PDT 24 May 16 01:50:35 PM PDT 24 517946168 ps
T59 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.441693904 May 16 01:50:19 PM PDT 24 May 16 01:50:22 PM PDT 24 339983293 ps
T306 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.3344155241 May 16 01:50:20 PM PDT 24 May 16 01:50:25 PM PDT 24 539537228 ps
T307 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.2648701524 May 16 01:51:32 PM PDT 24 May 16 01:51:36 PM PDT 24 482044076 ps
T308 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.1031500859 May 16 01:50:34 PM PDT 24 May 16 01:50:37 PM PDT 24 835929135 ps
T74 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.224859585 May 16 01:51:20 PM PDT 24 May 16 01:51:25 PM PDT 24 2621824205 ps
T309 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.2526065083 May 16 01:51:05 PM PDT 24 May 16 01:51:15 PM PDT 24 4198552523 ps
T310 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.3100135867 May 16 01:51:03 PM PDT 24 May 16 01:51:05 PM PDT 24 401955455 ps
T311 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.338369443 May 16 01:51:20 PM PDT 24 May 16 01:51:23 PM PDT 24 302251747 ps
T312 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.1655519017 May 16 01:51:20 PM PDT 24 May 16 01:51:25 PM PDT 24 529031191 ps
T60 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.4239385906 May 16 01:50:44 PM PDT 24 May 16 01:50:46 PM PDT 24 506163748 ps
T313 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.3631087619 May 16 01:51:40 PM PDT 24 May 16 01:51:42 PM PDT 24 475246136 ps
T314 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.3150516194 May 16 01:50:43 PM PDT 24 May 16 01:50:44 PM PDT 24 500740051 ps
T65 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.1635117650 May 16 01:50:21 PM PDT 24 May 16 01:50:37 PM PDT 24 10199865149 ps
T61 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.161216036 May 16 01:50:20 PM PDT 24 May 16 01:50:42 PM PDT 24 12860997028 ps
T315 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.1793364390 May 16 01:50:33 PM PDT 24 May 16 01:50:36 PM PDT 24 464150756 ps
T316 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.1394526727 May 16 01:50:21 PM PDT 24 May 16 01:50:26 PM PDT 24 397294990 ps
T317 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.432186116 May 16 01:51:32 PM PDT 24 May 16 01:51:35 PM PDT 24 518270750 ps
T318 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.1156101940 May 16 01:51:39 PM PDT 24 May 16 01:51:42 PM PDT 24 475710086 ps
T319 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.2801777613 May 16 01:51:06 PM PDT 24 May 16 01:51:09 PM PDT 24 380549680 ps
T66 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.930685532 May 16 01:50:32 PM PDT 24 May 16 01:50:36 PM PDT 24 1017493489 ps
T320 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.2260598709 May 16 01:51:05 PM PDT 24 May 16 01:51:10 PM PDT 24 4129865849 ps
T321 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.1637629172 May 16 01:51:18 PM PDT 24 May 16 01:51:21 PM PDT 24 377093492 ps
T322 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.317343271 May 16 01:50:19 PM PDT 24 May 16 01:50:22 PM PDT 24 477095574 ps
T92 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.582763256 May 16 01:51:30 PM PDT 24 May 16 01:51:39 PM PDT 24 4227011597 ps
T323 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.4088241557 May 16 01:51:32 PM PDT 24 May 16 01:51:36 PM PDT 24 1501249427 ps
T324 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.2279984443 May 16 01:51:04 PM PDT 24 May 16 01:51:08 PM PDT 24 396493634 ps
T325 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.3600279412 May 16 01:50:43 PM PDT 24 May 16 01:50:47 PM PDT 24 385970011 ps
T326 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.3733484257 May 16 01:50:33 PM PDT 24 May 16 01:50:36 PM PDT 24 528964543 ps
T327 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.4218962273 May 16 01:50:53 PM PDT 24 May 16 01:50:54 PM PDT 24 1275369335 ps
T328 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.677702006 May 16 01:51:05 PM PDT 24 May 16 01:51:09 PM PDT 24 1581897024 ps
T329 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.2736920347 May 16 01:51:38 PM PDT 24 May 16 01:51:40 PM PDT 24 450515958 ps
T330 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.272788028 May 16 01:51:30 PM PDT 24 May 16 01:51:32 PM PDT 24 332818230 ps
T331 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.3300455487 May 16 01:50:32 PM PDT 24 May 16 01:50:34 PM PDT 24 353788803 ps
T62 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.345369762 May 16 01:51:06 PM PDT 24 May 16 01:51:10 PM PDT 24 380265296 ps
T332 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.2376194688 May 16 01:51:05 PM PDT 24 May 16 01:51:09 PM PDT 24 573272555 ps
T333 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.120127676 May 16 01:51:19 PM PDT 24 May 16 01:51:22 PM PDT 24 1443173602 ps
T334 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.2688893119 May 16 01:50:50 PM PDT 24 May 16 01:50:52 PM PDT 24 379026953 ps
T335 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.630550728 May 16 01:51:29 PM PDT 24 May 16 01:51:31 PM PDT 24 402195567 ps
T336 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.3652100683 May 16 01:51:37 PM PDT 24 May 16 01:51:39 PM PDT 24 493360849 ps
T337 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.1869471132 May 16 01:50:44 PM PDT 24 May 16 01:50:46 PM PDT 24 326686482 ps
T338 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.603489863 May 16 01:51:04 PM PDT 24 May 16 01:51:07 PM PDT 24 530603810 ps
T67 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.2665120749 May 16 01:51:33 PM PDT 24 May 16 01:51:37 PM PDT 24 443806530 ps
T96 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.3244743432 May 16 01:51:06 PM PDT 24 May 16 01:51:10 PM PDT 24 4580859278 ps
T339 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.2214441355 May 16 01:51:04 PM PDT 24 May 16 01:51:07 PM PDT 24 402319253 ps
T340 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.808048591 May 16 01:51:31 PM PDT 24 May 16 01:51:35 PM PDT 24 340854823 ps
T341 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.3057115460 May 16 01:50:44 PM PDT 24 May 16 01:50:46 PM PDT 24 406796334 ps
T97 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.807438579 May 16 01:50:44 PM PDT 24 May 16 01:50:50 PM PDT 24 8223583191 ps
T342 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.2487722233 May 16 01:51:19 PM PDT 24 May 16 01:51:22 PM PDT 24 389315461 ps
T343 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.486685001 May 16 01:51:31 PM PDT 24 May 16 01:51:34 PM PDT 24 287981435 ps
T344 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.847777334 May 16 01:51:05 PM PDT 24 May 16 01:51:09 PM PDT 24 454265250 ps
T345 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.3168862540 May 16 01:50:47 PM PDT 24 May 16 01:50:48 PM PDT 24 373204596 ps
T346 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.2503135988 May 16 01:51:29 PM PDT 24 May 16 01:51:32 PM PDT 24 463658954 ps
T347 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.2839349325 May 16 01:51:31 PM PDT 24 May 16 01:51:34 PM PDT 24 288775863 ps
T348 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.943056618 May 16 01:50:35 PM PDT 24 May 16 01:50:38 PM PDT 24 507463720 ps
T349 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.2299116005 May 16 01:50:33 PM PDT 24 May 16 01:50:35 PM PDT 24 605211321 ps
T350 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.2292517992 May 16 01:51:04 PM PDT 24 May 16 01:51:08 PM PDT 24 511332436 ps
T351 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.2053760433 May 16 01:51:31 PM PDT 24 May 16 01:51:35 PM PDT 24 463961022 ps
T352 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.270089968 May 16 01:50:26 PM PDT 24 May 16 01:50:30 PM PDT 24 1271838199 ps
T68 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.1974190204 May 16 01:50:34 PM PDT 24 May 16 01:50:37 PM PDT 24 999185684 ps
T353 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.48821638 May 16 01:51:30 PM PDT 24 May 16 01:51:34 PM PDT 24 266562638 ps
T354 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.869921005 May 16 01:51:31 PM PDT 24 May 16 01:51:38 PM PDT 24 3985154543 ps
T355 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.2719984752 May 16 01:50:43 PM PDT 24 May 16 01:50:44 PM PDT 24 334613134 ps
T356 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.131600949 May 16 01:51:30 PM PDT 24 May 16 01:51:35 PM PDT 24 927992529 ps
T98 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.3560786232 May 16 01:51:05 PM PDT 24 May 16 01:51:10 PM PDT 24 4533737610 ps
T357 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.1735152051 May 16 01:51:21 PM PDT 24 May 16 01:51:25 PM PDT 24 1268192379 ps
T358 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.1336358170 May 16 01:51:31 PM PDT 24 May 16 01:51:34 PM PDT 24 404401026 ps
T359 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.2359307161 May 16 01:50:19 PM PDT 24 May 16 01:50:24 PM PDT 24 810347257 ps
T360 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.3587851777 May 16 01:51:19 PM PDT 24 May 16 01:51:35 PM PDT 24 8271748487 ps
T93 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.1507329130 May 16 01:50:45 PM PDT 24 May 16 01:50:58 PM PDT 24 8817812600 ps
T361 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.1940948945 May 16 01:50:19 PM PDT 24 May 16 01:50:22 PM PDT 24 311100815 ps
T362 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.3811202394 May 16 01:51:31 PM PDT 24 May 16 01:51:35 PM PDT 24 555191244 ps
T363 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.1055082021 May 16 01:51:04 PM PDT 24 May 16 01:51:08 PM PDT 24 443245280 ps
T364 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.3527559224 May 16 01:50:35 PM PDT 24 May 16 01:50:39 PM PDT 24 2228484227 ps
T365 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.2559134360 May 16 01:50:41 PM PDT 24 May 16 01:50:42 PM PDT 24 316924955 ps
T366 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.1731630445 May 16 01:51:04 PM PDT 24 May 16 01:51:08 PM PDT 24 545672650 ps
T367 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.4043553857 May 16 01:51:03 PM PDT 24 May 16 01:51:05 PM PDT 24 1955531464 ps
T368 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.2491776598 May 16 01:50:39 PM PDT 24 May 16 01:50:44 PM PDT 24 1337126325 ps
T369 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.2237463433 May 16 01:51:32 PM PDT 24 May 16 01:51:36 PM PDT 24 340872602 ps
T370 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.1039901063 May 16 01:51:39 PM PDT 24 May 16 01:51:41 PM PDT 24 493825326 ps
T371 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.923378728 May 16 01:50:22 PM PDT 24 May 16 01:50:30 PM PDT 24 4143170016 ps
T372 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.1566490652 May 16 01:50:21 PM PDT 24 May 16 01:50:26 PM PDT 24 380277658 ps
T373 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.2811880955 May 16 01:50:21 PM PDT 24 May 16 01:50:25 PM PDT 24 393441927 ps
T374 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.892330693 May 16 01:50:36 PM PDT 24 May 16 01:50:40 PM PDT 24 493869533 ps
T375 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.1430266465 May 16 01:51:04 PM PDT 24 May 16 01:51:15 PM PDT 24 4421941661 ps
T376 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.3267721869 May 16 01:50:43 PM PDT 24 May 16 01:50:46 PM PDT 24 553318441 ps
T377 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.1533622026 May 16 01:51:20 PM PDT 24 May 16 01:51:25 PM PDT 24 4058432432 ps
T378 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.3084950039 May 16 01:51:39 PM PDT 24 May 16 01:51:42 PM PDT 24 408998043 ps
T379 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.4207429006 May 16 01:51:30 PM PDT 24 May 16 01:51:33 PM PDT 24 547887894 ps
T380 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.3181442110 May 16 01:51:38 PM PDT 24 May 16 01:51:40 PM PDT 24 495264500 ps
T381 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.2576531640 May 16 01:50:54 PM PDT 24 May 16 01:50:55 PM PDT 24 372643098 ps
T382 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.3299950926 May 16 01:51:29 PM PDT 24 May 16 01:51:32 PM PDT 24 504993232 ps
T383 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.2055195807 May 16 01:51:05 PM PDT 24 May 16 01:51:08 PM PDT 24 714010545 ps
T384 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.310589922 May 16 01:50:22 PM PDT 24 May 16 01:50:26 PM PDT 24 359318923 ps
T385 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.4022557957 May 16 01:51:40 PM PDT 24 May 16 01:51:43 PM PDT 24 348189407 ps
T386 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.1842801759 May 16 01:51:06 PM PDT 24 May 16 01:51:13 PM PDT 24 2839054206 ps
T387 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.2237432474 May 16 01:50:24 PM PDT 24 May 16 01:50:40 PM PDT 24 8435682377 ps
T388 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.819739003 May 16 01:50:21 PM PDT 24 May 16 01:50:35 PM PDT 24 7120633086 ps
T389 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.2763402039 May 16 01:51:19 PM PDT 24 May 16 01:51:22 PM PDT 24 1305881249 ps
T390 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.1193148075 May 16 01:50:22 PM PDT 24 May 16 01:50:26 PM PDT 24 272043306 ps
T391 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.1412214368 May 16 01:51:39 PM PDT 24 May 16 01:51:42 PM PDT 24 384510236 ps
T392 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.472311079 May 16 01:50:17 PM PDT 24 May 16 01:50:19 PM PDT 24 660325988 ps
T393 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.4278504941 May 16 01:51:21 PM PDT 24 May 16 01:51:25 PM PDT 24 361345169 ps
T394 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.1648607111 May 16 01:51:21 PM PDT 24 May 16 01:51:23 PM PDT 24 500446306 ps
T395 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.4062315678 May 16 01:50:17 PM PDT 24 May 16 01:50:19 PM PDT 24 552213290 ps
T396 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.2084699621 May 16 01:51:40 PM PDT 24 May 16 01:51:43 PM PDT 24 455092514 ps
T397 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.1600116407 May 16 01:51:32 PM PDT 24 May 16 01:51:36 PM PDT 24 490382160 ps
T398 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.1566860679 May 16 01:51:04 PM PDT 24 May 16 01:51:07 PM PDT 24 815699813 ps
T399 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.3118025831 May 16 01:50:35 PM PDT 24 May 16 01:50:38 PM PDT 24 713794964 ps
T400 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.433834913 May 16 01:51:04 PM PDT 24 May 16 01:51:08 PM PDT 24 308542470 ps
T94 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.1670434855 May 16 01:50:36 PM PDT 24 May 16 01:50:42 PM PDT 24 7669665595 ps
T95 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.1613692830 May 16 01:50:35 PM PDT 24 May 16 01:50:50 PM PDT 24 8503401008 ps
T401 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.3147998061 May 16 01:51:29 PM PDT 24 May 16 01:51:32 PM PDT 24 1074670960 ps
T402 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.2949641706 May 16 01:50:44 PM PDT 24 May 16 01:50:46 PM PDT 24 399383105 ps
T403 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.382378362 May 16 01:51:33 PM PDT 24 May 16 01:51:36 PM PDT 24 419126005 ps
T404 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.2390643828 May 16 01:50:35 PM PDT 24 May 16 01:50:38 PM PDT 24 1514011515 ps
T405 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.3513773857 May 16 01:50:34 PM PDT 24 May 16 01:50:37 PM PDT 24 343288277 ps
T406 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.336378428 May 16 01:51:04 PM PDT 24 May 16 01:51:07 PM PDT 24 634940186 ps
T63 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.4202284731 May 16 01:50:36 PM PDT 24 May 16 01:50:38 PM PDT 24 352775871 ps
T407 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.3688171888 May 16 01:50:44 PM PDT 24 May 16 01:50:47 PM PDT 24 424805986 ps
T408 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.2676684829 May 16 01:50:55 PM PDT 24 May 16 01:50:56 PM PDT 24 481803117 ps
T409 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.4211348072 May 16 01:50:43 PM PDT 24 May 16 01:50:45 PM PDT 24 505776116 ps
T410 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.3593255402 May 16 01:50:21 PM PDT 24 May 16 01:50:25 PM PDT 24 836703521 ps
T411 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.910747329 May 16 01:51:20 PM PDT 24 May 16 01:51:23 PM PDT 24 593835188 ps
T412 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.1661608833 May 16 01:51:19 PM PDT 24 May 16 01:51:22 PM PDT 24 4507479524 ps
T413 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.91877941 May 16 01:50:40 PM PDT 24 May 16 01:50:41 PM PDT 24 291130057 ps

Test location /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.2792998804
Short name T4
Test name
Test status
Simulation time 232070647904 ps
CPU time 460.2 seconds
Started May 16 02:55:32 PM PDT 24
Finished May 16 03:03:18 PM PDT 24
Peak memory 198488 kb
Host smart-4496face-0d74-433b-b586-e8e360427ed9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792998804 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.2792998804
Directory /workspace/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.4118676985
Short name T39
Test name
Test status
Simulation time 33452277047 ps
CPU time 370.33 seconds
Started May 16 02:56:19 PM PDT 24
Finished May 16 03:02:32 PM PDT 24
Peak memory 198460 kb
Host smart-a810dde0-179b-486b-a254-badc77911c4d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118676985 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.4118676985
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.294074655
Short name T35
Test name
Test status
Simulation time 4330713203 ps
CPU time 7.67 seconds
Started May 16 01:50:54 PM PDT 24
Finished May 16 01:51:02 PM PDT 24
Peak memory 197784 kb
Host smart-e5f35a62-dd96-4cdc-9605-88449cf27dbe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294074655 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_
intg_err.294074655
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.1664297315
Short name T11
Test name
Test status
Simulation time 234923887329 ps
CPU time 388.36 seconds
Started May 16 02:55:48 PM PDT 24
Finished May 16 03:02:19 PM PDT 24
Peak memory 194120 kb
Host smart-3c065f79-c75d-4c7a-8abe-6dbf915446c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664297315 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_
all.1664297315
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.4199918800
Short name T15
Test name
Test status
Simulation time 8375055566 ps
CPU time 11.78 seconds
Started May 16 02:55:31 PM PDT 24
Finished May 16 02:55:48 PM PDT 24
Peak memory 215236 kb
Host smart-96935272-5872-403b-a795-f7183d6dc647
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199918800 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.4199918800
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.2226964077
Short name T78
Test name
Test status
Simulation time 402259449437 ps
CPU time 488.77 seconds
Started May 16 02:55:28 PM PDT 24
Finished May 16 03:03:44 PM PDT 24
Peak memory 206684 kb
Host smart-19f6f4cd-e3d4-41ef-9e46-1fd34996eb96
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226964077 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.2226964077
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.4239385906
Short name T60
Test name
Test status
Simulation time 506163748 ps
CPU time 0.82 seconds
Started May 16 01:50:44 PM PDT 24
Finished May 16 01:50:46 PM PDT 24
Peak memory 193020 kb
Host smart-9746a594-ad7d-4d78-83b4-22c05e925f04
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239385906 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.4239385906
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.1670434855
Short name T94
Test name
Test status
Simulation time 7669665595 ps
CPU time 4.35 seconds
Started May 16 01:50:36 PM PDT 24
Finished May 16 01:50:42 PM PDT 24
Peak memory 198180 kb
Host smart-af1c6d2e-5fcb-41fc-a5ce-032fa6e69fc1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670434855 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl
_intg_err.1670434855
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.2201328564
Short name T41
Test name
Test status
Simulation time 84043958293 ps
CPU time 686.32 seconds
Started May 16 02:55:43 PM PDT 24
Finished May 16 03:07:10 PM PDT 24
Peak memory 200464 kb
Host smart-674e7bb9-bda4-4ef3-8518-bf488dcb54eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201328564 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.2201328564
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.1911508554
Short name T6
Test name
Test status
Simulation time 204611498271 ps
CPU time 81.91 seconds
Started May 16 02:55:50 PM PDT 24
Finished May 16 02:57:14 PM PDT 24
Peak memory 183604 kb
Host smart-45b92454-d40c-4aa5-9d19-73b6b051fb96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911508554 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_
all.1911508554
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.441693904
Short name T59
Test name
Test status
Simulation time 339983293 ps
CPU time 1.17 seconds
Started May 16 01:50:19 PM PDT 24
Finished May 16 01:50:22 PM PDT 24
Peak memory 183760 kb
Host smart-04995851-429e-433b-8281-de608ebc2b97
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441693904 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_al
iasing.441693904
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.1635117650
Short name T65
Test name
Test status
Simulation time 10199865149 ps
CPU time 13.02 seconds
Started May 16 01:50:21 PM PDT 24
Finished May 16 01:50:37 PM PDT 24
Peak memory 192312 kb
Host smart-688594cd-874a-41f3-8657-0fbb18da52d8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635117650 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_b
it_bash.1635117650
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.3593255402
Short name T410
Test name
Test status
Simulation time 836703521 ps
CPU time 0.94 seconds
Started May 16 01:50:21 PM PDT 24
Finished May 16 01:50:25 PM PDT 24
Peak memory 183812 kb
Host smart-7d06e9fb-9f6e-4963-93ff-6fd713a43dc5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593255402 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_h
w_reset.3593255402
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.1364154073
Short name T297
Test name
Test status
Simulation time 396831440 ps
CPU time 1.14 seconds
Started May 16 01:50:21 PM PDT 24
Finished May 16 01:50:26 PM PDT 24
Peak memory 195848 kb
Host smart-4be066d8-f654-47c4-a234-f64f4dab0241
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364154073 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.1364154073
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.4062315678
Short name T395
Test name
Test status
Simulation time 552213290 ps
CPU time 0.64 seconds
Started May 16 01:50:17 PM PDT 24
Finished May 16 01:50:19 PM PDT 24
Peak memory 183744 kb
Host smart-acb9f951-6275-4222-be60-6e748d9f03a9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062315678 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.4062315678
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.310589922
Short name T384
Test name
Test status
Simulation time 359318923 ps
CPU time 0.64 seconds
Started May 16 01:50:22 PM PDT 24
Finished May 16 01:50:26 PM PDT 24
Peak memory 183664 kb
Host smart-b3171912-e788-437e-bef4-134808ac0694
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310589922 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.310589922
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.1566490652
Short name T372
Test name
Test status
Simulation time 380277658 ps
CPU time 1.04 seconds
Started May 16 01:50:21 PM PDT 24
Finished May 16 01:50:26 PM PDT 24
Peak memory 183596 kb
Host smart-f27c3b92-c102-472a-bccc-b8247e34e7c7
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566490652 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_t
imer_mem_partial_access.1566490652
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.3615126057
Short name T282
Test name
Test status
Simulation time 386926786 ps
CPU time 0.54 seconds
Started May 16 01:50:21 PM PDT 24
Finished May 16 01:50:25 PM PDT 24
Peak memory 183664 kb
Host smart-884e8921-75f0-4aaf-b8c9-b99f2c0511d0
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615126057 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_w
alk.3615126057
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.270089968
Short name T352
Test name
Test status
Simulation time 1271838199 ps
CPU time 1.61 seconds
Started May 16 01:50:26 PM PDT 24
Finished May 16 01:50:30 PM PDT 24
Peak memory 193248 kb
Host smart-d26c4f21-8373-49af-835c-1716c89306b9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270089968 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_
timer_same_csr_outstanding.270089968
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.3344155241
Short name T306
Test name
Test status
Simulation time 539537228 ps
CPU time 2.41 seconds
Started May 16 01:50:20 PM PDT 24
Finished May 16 01:50:25 PM PDT 24
Peak memory 198652 kb
Host smart-cc50075a-3076-4d88-b440-2aa4d2bfa2d8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344155241 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.3344155241
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.923378728
Short name T371
Test name
Test status
Simulation time 4143170016 ps
CPU time 4.3 seconds
Started May 16 01:50:22 PM PDT 24
Finished May 16 01:50:30 PM PDT 24
Peak memory 197708 kb
Host smart-5603530f-3956-4294-86c8-f53c0c44729c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923378728 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_
intg_err.923378728
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.472311079
Short name T392
Test name
Test status
Simulation time 660325988 ps
CPU time 1.1 seconds
Started May 16 01:50:17 PM PDT 24
Finished May 16 01:50:19 PM PDT 24
Peak memory 192044 kb
Host smart-b3a116cb-0237-4e01-9f8e-0f9fd0d23ef7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472311079 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_al
iasing.472311079
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.161216036
Short name T61
Test name
Test status
Simulation time 12860997028 ps
CPU time 19.52 seconds
Started May 16 01:50:20 PM PDT 24
Finished May 16 01:50:42 PM PDT 24
Peak memory 192316 kb
Host smart-4e35228d-26d6-468a-a875-54d22494cbbe
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161216036 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_bi
t_bash.161216036
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.2156853387
Short name T291
Test name
Test status
Simulation time 770142922 ps
CPU time 1.72 seconds
Started May 16 01:50:22 PM PDT 24
Finished May 16 01:50:27 PM PDT 24
Peak memory 183728 kb
Host smart-9312f88c-1eaf-4f1f-8169-ab19aeb5a085
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156853387 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_h
w_reset.2156853387
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.541329771
Short name T99
Test name
Test status
Simulation time 386184516 ps
CPU time 1.27 seconds
Started May 16 01:50:20 PM PDT 24
Finished May 16 01:50:24 PM PDT 24
Peak memory 196212 kb
Host smart-f6054f03-b297-4762-8476-657c52c92902
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541329771 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.541329771
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.1940948945
Short name T361
Test name
Test status
Simulation time 311100815 ps
CPU time 1.04 seconds
Started May 16 01:50:19 PM PDT 24
Finished May 16 01:50:22 PM PDT 24
Peak memory 183752 kb
Host smart-8501f6bb-c1a7-47aa-9c36-0e0f5426c685
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940948945 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.1940948945
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.1394526727
Short name T316
Test name
Test status
Simulation time 397294990 ps
CPU time 0.71 seconds
Started May 16 01:50:21 PM PDT 24
Finished May 16 01:50:26 PM PDT 24
Peak memory 183640 kb
Host smart-c0cdf648-4553-4ea1-8d1b-e1819798a105
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394526727 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.1394526727
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.963608604
Short name T275
Test name
Test status
Simulation time 404915253 ps
CPU time 0.67 seconds
Started May 16 01:50:19 PM PDT 24
Finished May 16 01:50:22 PM PDT 24
Peak memory 183592 kb
Host smart-16dfabf7-2ffc-4095-bf27-826d4cde3895
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963608604 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_ti
mer_mem_partial_access.963608604
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.1011004772
Short name T304
Test name
Test status
Simulation time 476414424 ps
CPU time 1.02 seconds
Started May 16 01:50:26 PM PDT 24
Finished May 16 01:50:29 PM PDT 24
Peak memory 183660 kb
Host smart-b85dd626-e26c-4d3c-9c6e-3d9e0d2e12c5
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011004772 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_w
alk.1011004772
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.857801156
Short name T72
Test name
Test status
Simulation time 1447099597 ps
CPU time 1.31 seconds
Started May 16 01:50:21 PM PDT 24
Finished May 16 01:50:26 PM PDT 24
Peak memory 193344 kb
Host smart-94219ea9-1faa-433a-8335-13eaf20cc917
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857801156 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_
timer_same_csr_outstanding.857801156
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.853787605
Short name T289
Test name
Test status
Simulation time 445874178 ps
CPU time 2.77 seconds
Started May 16 01:50:20 PM PDT 24
Finished May 16 01:50:25 PM PDT 24
Peak memory 198624 kb
Host smart-2f04f27f-6862-4d92-92ff-ca6b0ac357ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853787605 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.853787605
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.1852868808
Short name T34
Test name
Test status
Simulation time 3863066486 ps
CPU time 3.78 seconds
Started May 16 01:50:22 PM PDT 24
Finished May 16 01:50:29 PM PDT 24
Peak memory 197772 kb
Host smart-e7caa6cb-d8cd-4039-87c9-5c18485739a3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852868808 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl
_intg_err.1852868808
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.603489863
Short name T338
Test name
Test status
Simulation time 530603810 ps
CPU time 1.05 seconds
Started May 16 01:51:04 PM PDT 24
Finished May 16 01:51:07 PM PDT 24
Peak memory 195616 kb
Host smart-ab3cec42-d72b-4934-aae1-3c6f570ff87c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603489863 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.603489863
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.433834913
Short name T400
Test name
Test status
Simulation time 308542470 ps
CPU time 1.16 seconds
Started May 16 01:51:04 PM PDT 24
Finished May 16 01:51:08 PM PDT 24
Peak memory 193056 kb
Host smart-38c35307-9d83-41b8-bc94-bc7b7f542baa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433834913 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.433834913
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.3100135867
Short name T310
Test name
Test status
Simulation time 401955455 ps
CPU time 0.72 seconds
Started May 16 01:51:03 PM PDT 24
Finished May 16 01:51:05 PM PDT 24
Peak memory 183680 kb
Host smart-46083fcf-7197-4061-b4bf-c94cf68ff0df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100135867 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.3100135867
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.1842801759
Short name T386
Test name
Test status
Simulation time 2839054206 ps
CPU time 4.23 seconds
Started May 16 01:51:06 PM PDT 24
Finished May 16 01:51:13 PM PDT 24
Peak memory 194072 kb
Host smart-ea9a31ce-7572-4cb3-8da6-f2aad15b7dd8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842801759 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.ao
n_timer_same_csr_outstanding.1842801759
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.1055082021
Short name T363
Test name
Test status
Simulation time 443245280 ps
CPU time 1.75 seconds
Started May 16 01:51:04 PM PDT 24
Finished May 16 01:51:08 PM PDT 24
Peak memory 198352 kb
Host smart-53deb045-46a5-402a-9f1b-458e783de192
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055082021 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.1055082021
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.3244743432
Short name T96
Test name
Test status
Simulation time 4580859278 ps
CPU time 1.59 seconds
Started May 16 01:51:06 PM PDT 24
Finished May 16 01:51:10 PM PDT 24
Peak memory 196584 kb
Host smart-7e1e28f9-4ea2-49c2-ba00-68a1a3862af8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244743432 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_t
l_intg_err.3244743432
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.1731630445
Short name T366
Test name
Test status
Simulation time 545672650 ps
CPU time 0.95 seconds
Started May 16 01:51:04 PM PDT 24
Finished May 16 01:51:08 PM PDT 24
Peak memory 195948 kb
Host smart-acc9dd58-fb1b-4c80-80d7-c85e3f26ef2b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731630445 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.1731630445
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.2801777613
Short name T319
Test name
Test status
Simulation time 380549680 ps
CPU time 0.88 seconds
Started May 16 01:51:06 PM PDT 24
Finished May 16 01:51:09 PM PDT 24
Peak memory 192064 kb
Host smart-98df7dba-726f-4179-ab69-7958f9b8f89f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801777613 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.2801777613
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.2214441355
Short name T339
Test name
Test status
Simulation time 402319253 ps
CPU time 0.7 seconds
Started May 16 01:51:04 PM PDT 24
Finished May 16 01:51:07 PM PDT 24
Peak memory 183600 kb
Host smart-3b12476c-c568-4717-b64c-caf8bf97830c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214441355 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.2214441355
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.4043553857
Short name T367
Test name
Test status
Simulation time 1955531464 ps
CPU time 1.06 seconds
Started May 16 01:51:03 PM PDT 24
Finished May 16 01:51:05 PM PDT 24
Peak memory 183808 kb
Host smart-2bbf56fa-e5f4-44cc-8ff2-50678c2b5999
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043553857 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.ao
n_timer_same_csr_outstanding.4043553857
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.194489461
Short name T281
Test name
Test status
Simulation time 454891817 ps
CPU time 2.1 seconds
Started May 16 01:51:05 PM PDT 24
Finished May 16 01:51:10 PM PDT 24
Peak memory 198564 kb
Host smart-7510eebe-248a-44c4-bf2a-2b444aade3f1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194489461 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.194489461
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.1430266465
Short name T375
Test name
Test status
Simulation time 4421941661 ps
CPU time 7.5 seconds
Started May 16 01:51:04 PM PDT 24
Finished May 16 01:51:15 PM PDT 24
Peak memory 197828 kb
Host smart-837d8c22-c098-4309-82ff-44e06de6cd72
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430266465 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_t
l_intg_err.1430266465
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.2055195807
Short name T383
Test name
Test status
Simulation time 714010545 ps
CPU time 0.94 seconds
Started May 16 01:51:05 PM PDT 24
Finished May 16 01:51:08 PM PDT 24
Peak memory 198472 kb
Host smart-a97fe4a5-4032-4a2f-b22d-b0683ff3b504
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055195807 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.2055195807
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.847777334
Short name T344
Test name
Test status
Simulation time 454265250 ps
CPU time 0.83 seconds
Started May 16 01:51:05 PM PDT 24
Finished May 16 01:51:09 PM PDT 24
Peak memory 193040 kb
Host smart-1789ceef-aa8e-4f87-ad0a-84e373cfe7f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847777334 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.847777334
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.2503668931
Short name T301
Test name
Test status
Simulation time 467336236 ps
CPU time 0.63 seconds
Started May 16 01:51:04 PM PDT 24
Finished May 16 01:51:07 PM PDT 24
Peak memory 183676 kb
Host smart-9c4c62da-d645-4c72-bee4-3e74e627be9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503668931 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.2503668931
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.2719102313
Short name T69
Test name
Test status
Simulation time 1294709063 ps
CPU time 1.52 seconds
Started May 16 01:51:04 PM PDT 24
Finished May 16 01:51:09 PM PDT 24
Peak memory 183968 kb
Host smart-2d17408f-3cb1-4888-825a-eba8caaac9b5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719102313 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.ao
n_timer_same_csr_outstanding.2719102313
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.2376194688
Short name T332
Test name
Test status
Simulation time 573272555 ps
CPU time 1.47 seconds
Started May 16 01:51:05 PM PDT 24
Finished May 16 01:51:09 PM PDT 24
Peak memory 198604 kb
Host smart-5c2e657d-384a-41ad-a2b4-f8cce694f835
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376194688 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.2376194688
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.2260598709
Short name T320
Test name
Test status
Simulation time 4129865849 ps
CPU time 2.39 seconds
Started May 16 01:51:05 PM PDT 24
Finished May 16 01:51:10 PM PDT 24
Peak memory 197664 kb
Host smart-92cb3ce4-0dcb-4216-8d5d-29b5a53a67ba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260598709 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_t
l_intg_err.2260598709
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.674618916
Short name T290
Test name
Test status
Simulation time 557010250 ps
CPU time 1.11 seconds
Started May 16 01:51:21 PM PDT 24
Finished May 16 01:51:24 PM PDT 24
Peak memory 195968 kb
Host smart-2f08ec32-2acd-4b6d-bee0-77ac8118b5c2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674618916 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.674618916
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.345369762
Short name T62
Test name
Test status
Simulation time 380265296 ps
CPU time 0.86 seconds
Started May 16 01:51:06 PM PDT 24
Finished May 16 01:51:10 PM PDT 24
Peak memory 193044 kb
Host smart-a4de847a-976e-4eaf-9666-f9fdcf19c21c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345369762 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.345369762
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.3077527302
Short name T280
Test name
Test status
Simulation time 381337671 ps
CPU time 1.11 seconds
Started May 16 01:51:04 PM PDT 24
Finished May 16 01:51:07 PM PDT 24
Peak memory 183716 kb
Host smart-d8072f8d-d1e2-4929-b7fd-874c0b370976
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077527302 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.3077527302
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.131600949
Short name T356
Test name
Test status
Simulation time 927992529 ps
CPU time 2.63 seconds
Started May 16 01:51:30 PM PDT 24
Finished May 16 01:51:35 PM PDT 24
Peak memory 193336 kb
Host smart-c4f3825a-7c92-4638-a468-937a1fab8473
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131600949 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon
_timer_same_csr_outstanding.131600949
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.2279984443
Short name T324
Test name
Test status
Simulation time 396493634 ps
CPU time 2.93 seconds
Started May 16 01:51:04 PM PDT 24
Finished May 16 01:51:08 PM PDT 24
Peak memory 198608 kb
Host smart-2e2bf1f9-9451-4c4e-88bc-aad2f825ef91
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279984443 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.2279984443
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.2526065083
Short name T309
Test name
Test status
Simulation time 4198552523 ps
CPU time 7.87 seconds
Started May 16 01:51:05 PM PDT 24
Finished May 16 01:51:15 PM PDT 24
Peak memory 197620 kb
Host smart-c6bae324-dd94-4aca-810d-c01ce8991656
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526065083 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_t
l_intg_err.2526065083
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.1675251289
Short name T32
Test name
Test status
Simulation time 567380330 ps
CPU time 1.46 seconds
Started May 16 01:51:20 PM PDT 24
Finished May 16 01:51:24 PM PDT 24
Peak memory 196096 kb
Host smart-e3776c4d-d42b-42df-b2a4-fd120ed67234
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675251289 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.1675251289
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.3763095346
Short name T31
Test name
Test status
Simulation time 329913521 ps
CPU time 1.08 seconds
Started May 16 01:51:20 PM PDT 24
Finished May 16 01:51:23 PM PDT 24
Peak memory 193040 kb
Host smart-465bd018-ca1d-4017-9678-c22729c20020
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763095346 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.3763095346
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.1870009015
Short name T277
Test name
Test status
Simulation time 368336201 ps
CPU time 1.14 seconds
Started May 16 01:51:22 PM PDT 24
Finished May 16 01:51:25 PM PDT 24
Peak memory 183672 kb
Host smart-bc5da6b6-b054-4c84-aa76-924fc6234b09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870009015 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.1870009015
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.2763402039
Short name T389
Test name
Test status
Simulation time 1305881249 ps
CPU time 1.54 seconds
Started May 16 01:51:19 PM PDT 24
Finished May 16 01:51:22 PM PDT 24
Peak memory 193404 kb
Host smart-85fa795b-0b73-4989-b42a-20364a8a38fd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763402039 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao
n_timer_same_csr_outstanding.2763402039
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.1655519017
Short name T312
Test name
Test status
Simulation time 529031191 ps
CPU time 2.73 seconds
Started May 16 01:51:20 PM PDT 24
Finished May 16 01:51:25 PM PDT 24
Peak memory 198552 kb
Host smart-e774f53f-21fd-4eba-a6a7-5db689940a49
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655519017 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.1655519017
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.1533622026
Short name T377
Test name
Test status
Simulation time 4058432432 ps
CPU time 2.42 seconds
Started May 16 01:51:20 PM PDT 24
Finished May 16 01:51:25 PM PDT 24
Peak memory 196440 kb
Host smart-1ccdab3e-26f7-4781-b88e-744a8513f9b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533622026 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_t
l_intg_err.1533622026
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.910747329
Short name T411
Test name
Test status
Simulation time 593835188 ps
CPU time 0.85 seconds
Started May 16 01:51:20 PM PDT 24
Finished May 16 01:51:23 PM PDT 24
Peak memory 195736 kb
Host smart-e2579ea7-6ab8-44a8-bbb9-21a96b9d7014
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910747329 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.910747329
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.1637629172
Short name T321
Test name
Test status
Simulation time 377093492 ps
CPU time 1.16 seconds
Started May 16 01:51:18 PM PDT 24
Finished May 16 01:51:21 PM PDT 24
Peak memory 183932 kb
Host smart-f692b6d0-feec-4228-8e6e-30bac963ab4f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637629172 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.1637629172
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.1648607111
Short name T394
Test name
Test status
Simulation time 500446306 ps
CPU time 0.67 seconds
Started May 16 01:51:21 PM PDT 24
Finished May 16 01:51:23 PM PDT 24
Peak memory 183672 kb
Host smart-b74892c6-909d-46e0-80d7-2e8227888090
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648607111 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.1648607111
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.120127676
Short name T333
Test name
Test status
Simulation time 1443173602 ps
CPU time 1.57 seconds
Started May 16 01:51:19 PM PDT 24
Finished May 16 01:51:22 PM PDT 24
Peak memory 193372 kb
Host smart-75045e8c-5c99-4f0b-98d8-2c1b24287292
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120127676 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon
_timer_same_csr_outstanding.120127676
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.1735152051
Short name T357
Test name
Test status
Simulation time 1268192379 ps
CPU time 1.93 seconds
Started May 16 01:51:21 PM PDT 24
Finished May 16 01:51:25 PM PDT 24
Peak memory 198624 kb
Host smart-692c29b1-895f-43cd-9abe-9f186a0c11ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735152051 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.1735152051
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.1661608833
Short name T412
Test name
Test status
Simulation time 4507479524 ps
CPU time 1.82 seconds
Started May 16 01:51:19 PM PDT 24
Finished May 16 01:51:22 PM PDT 24
Peak memory 197528 kb
Host smart-03957909-e298-4d02-9457-aa16a72b7a15
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661608833 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_t
l_intg_err.1661608833
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.2487722233
Short name T342
Test name
Test status
Simulation time 389315461 ps
CPU time 0.9 seconds
Started May 16 01:51:19 PM PDT 24
Finished May 16 01:51:22 PM PDT 24
Peak memory 195224 kb
Host smart-7466a03b-ea98-4898-98dc-cacedf93d484
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487722233 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.2487722233
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.3049868876
Short name T55
Test name
Test status
Simulation time 354678330 ps
CPU time 1.12 seconds
Started May 16 01:51:19 PM PDT 24
Finished May 16 01:51:21 PM PDT 24
Peak memory 193064 kb
Host smart-3d05b211-2d64-4690-b2f0-e1cc2e017f89
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049868876 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.3049868876
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.338369443
Short name T311
Test name
Test status
Simulation time 302251747 ps
CPU time 0.92 seconds
Started May 16 01:51:20 PM PDT 24
Finished May 16 01:51:23 PM PDT 24
Peak memory 183780 kb
Host smart-15ed6ec8-34f3-41c8-96ef-be511b8f418d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338369443 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.338369443
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.224859585
Short name T74
Test name
Test status
Simulation time 2621824205 ps
CPU time 2.21 seconds
Started May 16 01:51:20 PM PDT 24
Finished May 16 01:51:25 PM PDT 24
Peak memory 183952 kb
Host smart-bcc10a33-b1b8-4bd9-a2d8-efb1fc2cb94f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224859585 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon
_timer_same_csr_outstanding.224859585
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.4278504941
Short name T393
Test name
Test status
Simulation time 361345169 ps
CPU time 2.22 seconds
Started May 16 01:51:21 PM PDT 24
Finished May 16 01:51:25 PM PDT 24
Peak memory 198628 kb
Host smart-6db6fc2c-19ef-4323-af8a-70b82eee1e3f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278504941 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.4278504941
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.3587851777
Short name T360
Test name
Test status
Simulation time 8271748487 ps
CPU time 14.02 seconds
Started May 16 01:51:19 PM PDT 24
Finished May 16 01:51:35 PM PDT 24
Peak memory 198112 kb
Host smart-9e6a9aca-e1fe-42e9-a51b-aba2f5642ac8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587851777 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_t
l_intg_err.3587851777
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.3811202394
Short name T362
Test name
Test status
Simulation time 555191244 ps
CPU time 1.44 seconds
Started May 16 01:51:31 PM PDT 24
Finished May 16 01:51:35 PM PDT 24
Peak memory 196928 kb
Host smart-7799a869-2fff-4e4b-9510-8c3e9d64a4e7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811202394 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.3811202394
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.272788028
Short name T330
Test name
Test status
Simulation time 332818230 ps
CPU time 0.98 seconds
Started May 16 01:51:30 PM PDT 24
Finished May 16 01:51:32 PM PDT 24
Peak memory 192004 kb
Host smart-e1a15fd2-0ea9-4e35-ab18-81585602b85f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272788028 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.272788028
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.3652100683
Short name T336
Test name
Test status
Simulation time 493360849 ps
CPU time 0.7 seconds
Started May 16 01:51:37 PM PDT 24
Finished May 16 01:51:39 PM PDT 24
Peak memory 183668 kb
Host smart-8c4e64d2-e121-4dfc-857c-a54e442129fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652100683 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.3652100683
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.4088241557
Short name T323
Test name
Test status
Simulation time 1501249427 ps
CPU time 1.51 seconds
Started May 16 01:51:32 PM PDT 24
Finished May 16 01:51:36 PM PDT 24
Peak memory 193336 kb
Host smart-1c4bfa72-42a4-46ee-9cb5-06b9216aeef6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088241557 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.ao
n_timer_same_csr_outstanding.4088241557
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.1813274451
Short name T303
Test name
Test status
Simulation time 357020616 ps
CPU time 2.41 seconds
Started May 16 01:51:19 PM PDT 24
Finished May 16 01:51:22 PM PDT 24
Peak memory 198568 kb
Host smart-c7bc3ad7-d94d-4809-a710-1147faf4e12c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813274451 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.1813274451
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.1700977283
Short name T91
Test name
Test status
Simulation time 4421972772 ps
CPU time 7.57 seconds
Started May 16 01:51:20 PM PDT 24
Finished May 16 01:51:30 PM PDT 24
Peak memory 197476 kb
Host smart-0fda32a6-39b7-458b-8f6e-80cb41845200
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700977283 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_t
l_intg_err.1700977283
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.2053760433
Short name T351
Test name
Test status
Simulation time 463961022 ps
CPU time 1.3 seconds
Started May 16 01:51:31 PM PDT 24
Finished May 16 01:51:35 PM PDT 24
Peak memory 195856 kb
Host smart-c07f4cde-3327-4a4e-ae42-09def7b55ca5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053760433 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.2053760433
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.2665120749
Short name T67
Test name
Test status
Simulation time 443806530 ps
CPU time 1.25 seconds
Started May 16 01:51:33 PM PDT 24
Finished May 16 01:51:37 PM PDT 24
Peak memory 184004 kb
Host smart-5f33c657-beff-44e4-9fe5-70a64e68bb73
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665120749 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.2665120749
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.1066988228
Short name T284
Test name
Test status
Simulation time 406603919 ps
CPU time 0.86 seconds
Started May 16 01:51:38 PM PDT 24
Finished May 16 01:51:41 PM PDT 24
Peak memory 183668 kb
Host smart-74d31464-b9bc-4847-9ea4-03e420c420c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066988228 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.1066988228
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.3147998061
Short name T401
Test name
Test status
Simulation time 1074670960 ps
CPU time 1.22 seconds
Started May 16 01:51:29 PM PDT 24
Finished May 16 01:51:32 PM PDT 24
Peak memory 193240 kb
Host smart-17fea23d-472d-4a41-ba27-643890ea2659
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147998061 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.ao
n_timer_same_csr_outstanding.3147998061
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.2237463433
Short name T369
Test name
Test status
Simulation time 340872602 ps
CPU time 1.68 seconds
Started May 16 01:51:32 PM PDT 24
Finished May 16 01:51:36 PM PDT 24
Peak memory 198544 kb
Host smart-e7d06437-a5c2-4f60-9f67-f1dcf5e897b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237463433 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.2237463433
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.582763256
Short name T92
Test name
Test status
Simulation time 4227011597 ps
CPU time 7.06 seconds
Started May 16 01:51:30 PM PDT 24
Finished May 16 01:51:39 PM PDT 24
Peak memory 197588 kb
Host smart-145db65c-07d1-48fb-a027-f5a6f65dd947
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582763256 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl
_intg_err.582763256
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.382378362
Short name T403
Test name
Test status
Simulation time 419126005 ps
CPU time 0.95 seconds
Started May 16 01:51:33 PM PDT 24
Finished May 16 01:51:36 PM PDT 24
Peak memory 196056 kb
Host smart-5f7a7e48-117a-47a6-9c0d-17c09a3983c4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382378362 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.382378362
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.4207429006
Short name T379
Test name
Test status
Simulation time 547887894 ps
CPU time 0.85 seconds
Started May 16 01:51:30 PM PDT 24
Finished May 16 01:51:33 PM PDT 24
Peak memory 184012 kb
Host smart-18591b6a-0107-4758-b05f-f49d306b9246
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207429006 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.4207429006
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.4103802296
Short name T279
Test name
Test status
Simulation time 318977190 ps
CPU time 1.03 seconds
Started May 16 01:51:33 PM PDT 24
Finished May 16 01:51:37 PM PDT 24
Peak memory 183668 kb
Host smart-cbc6423f-2aec-4f68-a290-f719af6a6d9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103802296 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.4103802296
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.2240730822
Short name T70
Test name
Test status
Simulation time 1773057274 ps
CPU time 1.4 seconds
Started May 16 01:51:29 PM PDT 24
Finished May 16 01:51:32 PM PDT 24
Peak memory 193456 kb
Host smart-8e734987-fe50-4dfd-9f2f-07b792e1aea1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240730822 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao
n_timer_same_csr_outstanding.2240730822
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.186920182
Short name T295
Test name
Test status
Simulation time 798284485 ps
CPU time 2.37 seconds
Started May 16 01:51:29 PM PDT 24
Finished May 16 01:51:33 PM PDT 24
Peak memory 198636 kb
Host smart-30675eb0-9bdf-467a-966a-b019c42e6d12
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186920182 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.186920182
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.869921005
Short name T354
Test name
Test status
Simulation time 3985154543 ps
CPU time 4.11 seconds
Started May 16 01:51:31 PM PDT 24
Finished May 16 01:51:38 PM PDT 24
Peak memory 197640 kb
Host smart-c4682c7b-d5ed-4319-af00-b5a88efb8a4b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869921005 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl
_intg_err.869921005
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.3795274811
Short name T58
Test name
Test status
Simulation time 542394339 ps
CPU time 0.97 seconds
Started May 16 01:50:25 PM PDT 24
Finished May 16 01:50:28 PM PDT 24
Peak memory 194280 kb
Host smart-a66d4572-3f83-47ca-93ec-3e6cd7411586
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795274811 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_a
liasing.3795274811
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.819739003
Short name T388
Test name
Test status
Simulation time 7120633086 ps
CPU time 9.97 seconds
Started May 16 01:50:21 PM PDT 24
Finished May 16 01:50:35 PM PDT 24
Peak memory 194312 kb
Host smart-4fbc2174-7724-4129-8af3-2d32f60a8088
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819739003 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_bi
t_bash.819739003
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.1326307156
Short name T293
Test name
Test status
Simulation time 733060404 ps
CPU time 1.21 seconds
Started May 16 01:50:21 PM PDT 24
Finished May 16 01:50:25 PM PDT 24
Peak memory 183824 kb
Host smart-00e4ccee-b055-4745-8708-490af50ab6cf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326307156 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_h
w_reset.1326307156
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.1793364390
Short name T315
Test name
Test status
Simulation time 464150756 ps
CPU time 1.39 seconds
Started May 16 01:50:33 PM PDT 24
Finished May 16 01:50:36 PM PDT 24
Peak memory 196392 kb
Host smart-9c18ef71-c490-4f3c-9db2-7819a0ccc8c3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793364390 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.1793364390
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.2811880955
Short name T373
Test name
Test status
Simulation time 393441927 ps
CPU time 0.72 seconds
Started May 16 01:50:21 PM PDT 24
Finished May 16 01:50:25 PM PDT 24
Peak memory 183760 kb
Host smart-13ec8f45-cf2e-40ff-a897-d67a1dc32991
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811880955 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.2811880955
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.3920869572
Short name T285
Test name
Test status
Simulation time 419436545 ps
CPU time 0.67 seconds
Started May 16 01:50:19 PM PDT 24
Finished May 16 01:50:20 PM PDT 24
Peak memory 183600 kb
Host smart-345eb0e1-8fe6-4bd5-b36e-9b32539e97bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920869572 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.3920869572
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.317343271
Short name T322
Test name
Test status
Simulation time 477095574 ps
CPU time 0.76 seconds
Started May 16 01:50:19 PM PDT 24
Finished May 16 01:50:22 PM PDT 24
Peak memory 183596 kb
Host smart-9e45a724-9e8b-4dbf-aaed-e5c1ff4c2476
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317343271 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_ti
mer_mem_partial_access.317343271
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.1193148075
Short name T390
Test name
Test status
Simulation time 272043306 ps
CPU time 0.77 seconds
Started May 16 01:50:22 PM PDT 24
Finished May 16 01:50:26 PM PDT 24
Peak memory 183700 kb
Host smart-6d32d073-1680-4929-9ea2-b661c496aa48
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193148075 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_w
alk.1193148075
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.2390643828
Short name T404
Test name
Test status
Simulation time 1514011515 ps
CPU time 0.95 seconds
Started May 16 01:50:35 PM PDT 24
Finished May 16 01:50:38 PM PDT 24
Peak memory 183860 kb
Host smart-9bf54ae2-76b0-4adc-a287-809c6478b24a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390643828 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon
_timer_same_csr_outstanding.2390643828
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.2359307161
Short name T359
Test name
Test status
Simulation time 810347257 ps
CPU time 1.82 seconds
Started May 16 01:50:19 PM PDT 24
Finished May 16 01:50:24 PM PDT 24
Peak memory 198600 kb
Host smart-23b76b90-9605-4840-aab5-1668786439bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359307161 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.2359307161
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.2237432474
Short name T387
Test name
Test status
Simulation time 8435682377 ps
CPU time 13.92 seconds
Started May 16 01:50:24 PM PDT 24
Finished May 16 01:50:40 PM PDT 24
Peak memory 197980 kb
Host smart-d1366bab-e7fa-4178-b524-3125cbe29e19
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237432474 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl
_intg_err.2237432474
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.3109237136
Short name T299
Test name
Test status
Simulation time 457061726 ps
CPU time 1.2 seconds
Started May 16 01:51:31 PM PDT 24
Finished May 16 01:51:34 PM PDT 24
Peak memory 183692 kb
Host smart-6f155bca-e0e7-460b-aa22-e437f506988d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109237136 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.3109237136
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.2568729634
Short name T300
Test name
Test status
Simulation time 422323204 ps
CPU time 0.59 seconds
Started May 16 01:51:31 PM PDT 24
Finished May 16 01:51:35 PM PDT 24
Peak memory 183688 kb
Host smart-77d31b9d-3b47-41ab-998b-06227c2ae07a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568729634 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.2568729634
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.1471321393
Short name T286
Test name
Test status
Simulation time 299314930 ps
CPU time 0.65 seconds
Started May 16 01:51:32 PM PDT 24
Finished May 16 01:51:36 PM PDT 24
Peak memory 183704 kb
Host smart-21a69309-df2b-46dc-83bb-9f87abb312d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471321393 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.1471321393
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.1744248289
Short name T278
Test name
Test status
Simulation time 417648674 ps
CPU time 1.15 seconds
Started May 16 01:51:31 PM PDT 24
Finished May 16 01:51:35 PM PDT 24
Peak memory 183684 kb
Host smart-12d66e32-a07b-41d1-ab8f-cd0d818a73fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744248289 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.1744248289
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.3299950926
Short name T382
Test name
Test status
Simulation time 504993232 ps
CPU time 0.89 seconds
Started May 16 01:51:29 PM PDT 24
Finished May 16 01:51:32 PM PDT 24
Peak memory 183688 kb
Host smart-f7662a99-5922-40b4-bcf3-56bdcbcad81a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299950926 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.3299950926
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.630550728
Short name T335
Test name
Test status
Simulation time 402195567 ps
CPU time 1.12 seconds
Started May 16 01:51:29 PM PDT 24
Finished May 16 01:51:31 PM PDT 24
Peak memory 183660 kb
Host smart-3c4917d7-49f7-4448-afde-822cf021b2f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630550728 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.630550728
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.2503135988
Short name T346
Test name
Test status
Simulation time 463658954 ps
CPU time 1.07 seconds
Started May 16 01:51:29 PM PDT 24
Finished May 16 01:51:32 PM PDT 24
Peak memory 183680 kb
Host smart-5fcaf9f2-3819-4e64-8796-a30469c5bf6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503135988 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.2503135988
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.1298640135
Short name T287
Test name
Test status
Simulation time 325661523 ps
CPU time 0.66 seconds
Started May 16 01:51:38 PM PDT 24
Finished May 16 01:51:40 PM PDT 24
Peak memory 183668 kb
Host smart-c0df4c82-b09d-41a4-8b98-0e9c2d1b965d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298640135 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.1298640135
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.2736920347
Short name T329
Test name
Test status
Simulation time 450515958 ps
CPU time 0.88 seconds
Started May 16 01:51:38 PM PDT 24
Finished May 16 01:51:40 PM PDT 24
Peak memory 183668 kb
Host smart-540ae9ff-586e-411c-9ecd-74f2b2ccd30c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736920347 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.2736920347
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.2648701524
Short name T307
Test name
Test status
Simulation time 482044076 ps
CPU time 0.93 seconds
Started May 16 01:51:32 PM PDT 24
Finished May 16 01:51:36 PM PDT 24
Peak memory 183644 kb
Host smart-214784b8-cd31-4fec-9ea5-33c398122ec7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648701524 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.2648701524
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.2299116005
Short name T349
Test name
Test status
Simulation time 605211321 ps
CPU time 1.08 seconds
Started May 16 01:50:33 PM PDT 24
Finished May 16 01:50:35 PM PDT 24
Peak memory 183776 kb
Host smart-7ee3e5b1-ee3a-487d-a200-68e6f28cbb0d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299116005 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_a
liasing.2299116005
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.3564103824
Short name T56
Test name
Test status
Simulation time 11181701413 ps
CPU time 17.4 seconds
Started May 16 01:50:33 PM PDT 24
Finished May 16 01:50:52 PM PDT 24
Peak memory 192264 kb
Host smart-92936bb8-5402-4306-a7c9-c5b0e42df5f8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564103824 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_b
it_bash.3564103824
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.1974190204
Short name T68
Test name
Test status
Simulation time 999185684 ps
CPU time 1.02 seconds
Started May 16 01:50:34 PM PDT 24
Finished May 16 01:50:37 PM PDT 24
Peak memory 183760 kb
Host smart-220f8cc0-6524-4753-8fc0-fda27451066c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974190204 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_h
w_reset.1974190204
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.943056618
Short name T348
Test name
Test status
Simulation time 507463720 ps
CPU time 0.82 seconds
Started May 16 01:50:35 PM PDT 24
Finished May 16 01:50:38 PM PDT 24
Peak memory 195628 kb
Host smart-1cd5e03d-4f00-47dc-a06f-83f9ce17719b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943056618 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.943056618
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.532364675
Short name T64
Test name
Test status
Simulation time 517946168 ps
CPU time 0.97 seconds
Started May 16 01:50:33 PM PDT 24
Finished May 16 01:50:35 PM PDT 24
Peak memory 183944 kb
Host smart-0eebd564-d37d-40e1-b1d7-15febb804575
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532364675 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.532364675
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.3733484257
Short name T326
Test name
Test status
Simulation time 528964543 ps
CPU time 0.71 seconds
Started May 16 01:50:33 PM PDT 24
Finished May 16 01:50:36 PM PDT 24
Peak memory 183708 kb
Host smart-b47f3f0c-757d-4d07-883a-14edbe1d92e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733484257 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.3733484257
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.2559134360
Short name T365
Test name
Test status
Simulation time 316924955 ps
CPU time 0.59 seconds
Started May 16 01:50:41 PM PDT 24
Finished May 16 01:50:42 PM PDT 24
Peak memory 183604 kb
Host smart-2ad9ebd9-05f3-4d6f-9c4b-0977017e7058
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559134360 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_t
imer_mem_partial_access.2559134360
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.3300455487
Short name T331
Test name
Test status
Simulation time 353788803 ps
CPU time 0.65 seconds
Started May 16 01:50:32 PM PDT 24
Finished May 16 01:50:34 PM PDT 24
Peak memory 183676 kb
Host smart-0e5cdf8f-5e16-43f1-90e5-f4da46291ebf
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300455487 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_w
alk.3300455487
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.2491776598
Short name T368
Test name
Test status
Simulation time 1337126325 ps
CPU time 3.73 seconds
Started May 16 01:50:39 PM PDT 24
Finished May 16 01:50:44 PM PDT 24
Peak memory 193432 kb
Host smart-32d37700-719c-4ca6-850e-457c8a474e18
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491776598 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon
_timer_same_csr_outstanding.2491776598
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.1031500859
Short name T308
Test name
Test status
Simulation time 835929135 ps
CPU time 1.8 seconds
Started May 16 01:50:34 PM PDT 24
Finished May 16 01:50:37 PM PDT 24
Peak memory 198588 kb
Host smart-838894c8-856d-426d-82a4-b3155ef52162
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031500859 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.1031500859
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.3052551426
Short name T37
Test name
Test status
Simulation time 4200681934 ps
CPU time 6.34 seconds
Started May 16 01:50:33 PM PDT 24
Finished May 16 01:50:41 PM PDT 24
Peak memory 197460 kb
Host smart-5c6a7739-7085-4733-9390-17ef7d415f92
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052551426 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl
_intg_err.3052551426
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.841430491
Short name T302
Test name
Test status
Simulation time 480835444 ps
CPU time 1.34 seconds
Started May 16 01:51:30 PM PDT 24
Finished May 16 01:51:34 PM PDT 24
Peak memory 183672 kb
Host smart-32667d15-46a7-4e55-a2d4-cdd66330a223
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841430491 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.841430491
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.1336358170
Short name T358
Test name
Test status
Simulation time 404401026 ps
CPU time 0.83 seconds
Started May 16 01:51:31 PM PDT 24
Finished May 16 01:51:34 PM PDT 24
Peak memory 183684 kb
Host smart-f4d979d2-e12b-480b-b095-5a09953fad78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336358170 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.1336358170
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.3181442110
Short name T380
Test name
Test status
Simulation time 495264500 ps
CPU time 0.9 seconds
Started May 16 01:51:38 PM PDT 24
Finished May 16 01:51:40 PM PDT 24
Peak memory 183668 kb
Host smart-3436502c-c4c2-454e-88dc-728c1a19df75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181442110 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.3181442110
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.2563116131
Short name T276
Test name
Test status
Simulation time 517197295 ps
CPU time 1.36 seconds
Started May 16 01:51:30 PM PDT 24
Finished May 16 01:51:34 PM PDT 24
Peak memory 183684 kb
Host smart-88e9a30c-8f13-4c60-b8fa-75405ef38067
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563116131 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.2563116131
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.432186116
Short name T317
Test name
Test status
Simulation time 518270750 ps
CPU time 0.64 seconds
Started May 16 01:51:32 PM PDT 24
Finished May 16 01:51:35 PM PDT 24
Peak memory 183644 kb
Host smart-9dc3854a-da83-42aa-874f-9c2c6078fe66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432186116 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.432186116
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.1600116407
Short name T397
Test name
Test status
Simulation time 490382160 ps
CPU time 1.32 seconds
Started May 16 01:51:32 PM PDT 24
Finished May 16 01:51:36 PM PDT 24
Peak memory 183704 kb
Host smart-16e4c036-02ba-4b3c-b2e1-b09fc5e1936d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600116407 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.1600116407
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.2839349325
Short name T347
Test name
Test status
Simulation time 288775863 ps
CPU time 0.95 seconds
Started May 16 01:51:31 PM PDT 24
Finished May 16 01:51:34 PM PDT 24
Peak memory 183672 kb
Host smart-7a14fe54-7c8b-45fd-a01b-3da4fc124c1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839349325 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.2839349325
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.853847834
Short name T298
Test name
Test status
Simulation time 470300614 ps
CPU time 0.71 seconds
Started May 16 01:51:32 PM PDT 24
Finished May 16 01:51:35 PM PDT 24
Peak memory 183704 kb
Host smart-eb61aaeb-7beb-4721-95f5-2f96c171d76c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853847834 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.853847834
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.1764964713
Short name T296
Test name
Test status
Simulation time 535137775 ps
CPU time 0.63 seconds
Started May 16 01:51:30 PM PDT 24
Finished May 16 01:51:34 PM PDT 24
Peak memory 183680 kb
Host smart-95f01fb0-7171-460e-84ca-16269bc3c8e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764964713 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.1764964713
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.808048591
Short name T340
Test name
Test status
Simulation time 340854823 ps
CPU time 0.98 seconds
Started May 16 01:51:31 PM PDT 24
Finished May 16 01:51:35 PM PDT 24
Peak memory 183684 kb
Host smart-f86b8d42-edfa-4f76-bfe2-49c4e5a7f30b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808048591 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.808048591
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.856445422
Short name T57
Test name
Test status
Simulation time 513449019 ps
CPU time 1.57 seconds
Started May 16 01:50:33 PM PDT 24
Finished May 16 01:50:36 PM PDT 24
Peak memory 193292 kb
Host smart-2b1ec04e-26f2-4a91-887d-9e9f8c1bdf1c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856445422 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_al
iasing.856445422
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.2678322071
Short name T288
Test name
Test status
Simulation time 13936096831 ps
CPU time 27.38 seconds
Started May 16 01:50:35 PM PDT 24
Finished May 16 01:51:04 PM PDT 24
Peak memory 194708 kb
Host smart-ba08b0bd-6ced-481b-bed5-9f63e939e0e1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678322071 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_b
it_bash.2678322071
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.930685532
Short name T66
Test name
Test status
Simulation time 1017493489 ps
CPU time 2.26 seconds
Started May 16 01:50:32 PM PDT 24
Finished May 16 01:50:36 PM PDT 24
Peak memory 183816 kb
Host smart-13875a89-3cc7-4e6f-8aa3-c326b849cc1d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930685532 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_hw
_reset.930685532
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.3118025831
Short name T399
Test name
Test status
Simulation time 713794964 ps
CPU time 0.95 seconds
Started May 16 01:50:35 PM PDT 24
Finished May 16 01:50:38 PM PDT 24
Peak memory 197500 kb
Host smart-1fbe7002-b249-42e6-9a47-d534a55c8994
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118025831 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.3118025831
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.4202284731
Short name T63
Test name
Test status
Simulation time 352775871 ps
CPU time 0.85 seconds
Started May 16 01:50:36 PM PDT 24
Finished May 16 01:50:38 PM PDT 24
Peak memory 183776 kb
Host smart-a52f1128-e9e5-4076-9f9b-63120aa86c33
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202284731 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.4202284731
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.91877941
Short name T413
Test name
Test status
Simulation time 291130057 ps
CPU time 0.77 seconds
Started May 16 01:50:40 PM PDT 24
Finished May 16 01:50:41 PM PDT 24
Peak memory 183664 kb
Host smart-4b55306a-d358-4c14-b6bc-ea51cfcd3121
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91877941 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.91877941
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.1500173577
Short name T294
Test name
Test status
Simulation time 419336766 ps
CPU time 1 seconds
Started May 16 01:50:34 PM PDT 24
Finished May 16 01:50:36 PM PDT 24
Peak memory 183576 kb
Host smart-f4ceadda-f292-4612-92ad-4ec75c46ecab
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500173577 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_t
imer_mem_partial_access.1500173577
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.1456749530
Short name T283
Test name
Test status
Simulation time 407083806 ps
CPU time 1.13 seconds
Started May 16 01:50:33 PM PDT 24
Finished May 16 01:50:36 PM PDT 24
Peak memory 183660 kb
Host smart-c4acc75c-264c-4bcb-847b-c6a3904eecc4
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456749530 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_w
alk.1456749530
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.3527559224
Short name T364
Test name
Test status
Simulation time 2228484227 ps
CPU time 2.13 seconds
Started May 16 01:50:35 PM PDT 24
Finished May 16 01:50:39 PM PDT 24
Peak memory 194404 kb
Host smart-0f7c949d-f828-4f26-991c-00ff57bb7ec4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527559224 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon
_timer_same_csr_outstanding.3527559224
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.892330693
Short name T374
Test name
Test status
Simulation time 493869533 ps
CPU time 2.66 seconds
Started May 16 01:50:36 PM PDT 24
Finished May 16 01:50:40 PM PDT 24
Peak memory 198616 kb
Host smart-ff944f31-7a9b-4ee3-a3ec-17df36e7686b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892330693 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.892330693
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.48821638
Short name T353
Test name
Test status
Simulation time 266562638 ps
CPU time 0.89 seconds
Started May 16 01:51:30 PM PDT 24
Finished May 16 01:51:34 PM PDT 24
Peak memory 183688 kb
Host smart-3d7ff31e-6fee-41d3-bc6f-5e37c9a2745f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48821638 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.48821638
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.486685001
Short name T343
Test name
Test status
Simulation time 287981435 ps
CPU time 0.88 seconds
Started May 16 01:51:31 PM PDT 24
Finished May 16 01:51:34 PM PDT 24
Peak memory 183688 kb
Host smart-be79d8e4-449f-419f-95d8-127648e44b38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486685001 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.486685001
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.2084699621
Short name T396
Test name
Test status
Simulation time 455092514 ps
CPU time 0.68 seconds
Started May 16 01:51:40 PM PDT 24
Finished May 16 01:51:43 PM PDT 24
Peak memory 183720 kb
Host smart-86dbf7e1-ce34-46fa-890f-d3cdacc3f1cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084699621 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.2084699621
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.1039901063
Short name T370
Test name
Test status
Simulation time 493825326 ps
CPU time 0.69 seconds
Started May 16 01:51:39 PM PDT 24
Finished May 16 01:51:41 PM PDT 24
Peak memory 183676 kb
Host smart-5362312b-7e1e-45c2-951e-9bb5ff415e4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039901063 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.1039901063
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.1412214368
Short name T391
Test name
Test status
Simulation time 384510236 ps
CPU time 0.67 seconds
Started May 16 01:51:39 PM PDT 24
Finished May 16 01:51:42 PM PDT 24
Peak memory 183696 kb
Host smart-85af61cb-e1eb-431c-a4ca-198171ba0db7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412214368 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.1412214368
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.4022557957
Short name T385
Test name
Test status
Simulation time 348189407 ps
CPU time 0.65 seconds
Started May 16 01:51:40 PM PDT 24
Finished May 16 01:51:43 PM PDT 24
Peak memory 183724 kb
Host smart-1aa6378d-1d80-43d0-acec-7eb5bffa6c44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022557957 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.4022557957
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.3710382543
Short name T292
Test name
Test status
Simulation time 308830228 ps
CPU time 0.73 seconds
Started May 16 01:51:39 PM PDT 24
Finished May 16 01:51:42 PM PDT 24
Peak memory 183672 kb
Host smart-bd29c36b-e958-43cd-9f4b-06aebf90e3d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710382543 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.3710382543
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.1156101940
Short name T318
Test name
Test status
Simulation time 475710086 ps
CPU time 0.7 seconds
Started May 16 01:51:39 PM PDT 24
Finished May 16 01:51:42 PM PDT 24
Peak memory 183680 kb
Host smart-933d48c4-b6f5-4324-9fbf-81f6663aeb36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156101940 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.1156101940
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.3631087619
Short name T313
Test name
Test status
Simulation time 475246136 ps
CPU time 0.87 seconds
Started May 16 01:51:40 PM PDT 24
Finished May 16 01:51:42 PM PDT 24
Peak memory 183688 kb
Host smart-bf06bd22-a99e-4750-b083-1b0dadc38e4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631087619 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.3631087619
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.3084950039
Short name T378
Test name
Test status
Simulation time 408998043 ps
CPU time 0.85 seconds
Started May 16 01:51:39 PM PDT 24
Finished May 16 01:51:42 PM PDT 24
Peak memory 183668 kb
Host smart-f2c90656-4c4f-4390-a747-acd488b7185a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084950039 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.3084950039
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.2688893119
Short name T334
Test name
Test status
Simulation time 379026953 ps
CPU time 0.93 seconds
Started May 16 01:50:50 PM PDT 24
Finished May 16 01:50:52 PM PDT 24
Peak memory 195808 kb
Host smart-02548bc9-580f-4f37-8fe2-d146bf66568d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688893119 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.2688893119
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.2949641706
Short name T402
Test name
Test status
Simulation time 399383105 ps
CPU time 0.67 seconds
Started May 16 01:50:44 PM PDT 24
Finished May 16 01:50:46 PM PDT 24
Peak memory 192040 kb
Host smart-0b18d98f-8143-45e3-9601-e2c3062fb740
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949641706 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.2949641706
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.1869471132
Short name T337
Test name
Test status
Simulation time 326686482 ps
CPU time 1.01 seconds
Started May 16 01:50:44 PM PDT 24
Finished May 16 01:50:46 PM PDT 24
Peak memory 183688 kb
Host smart-4f4d0b30-4e55-40aa-ab20-ecb3a53f2f93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869471132 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.1869471132
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.3382120699
Short name T71
Test name
Test status
Simulation time 2607459504 ps
CPU time 2.32 seconds
Started May 16 01:50:45 PM PDT 24
Finished May 16 01:50:49 PM PDT 24
Peak memory 183952 kb
Host smart-84f84e28-9f11-4353-845d-798a844eb809
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382120699 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon
_timer_same_csr_outstanding.3382120699
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.3513773857
Short name T405
Test name
Test status
Simulation time 343288277 ps
CPU time 1.72 seconds
Started May 16 01:50:34 PM PDT 24
Finished May 16 01:50:37 PM PDT 24
Peak memory 198524 kb
Host smart-443f6f35-606d-4225-a19b-d22de5ca777d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513773857 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.3513773857
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.1613692830
Short name T95
Test name
Test status
Simulation time 8503401008 ps
CPU time 12.81 seconds
Started May 16 01:50:35 PM PDT 24
Finished May 16 01:50:50 PM PDT 24
Peak memory 198056 kb
Host smart-b4e5429f-d700-430e-b9b1-cea19738a45f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613692830 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl
_intg_err.1613692830
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.4211348072
Short name T409
Test name
Test status
Simulation time 505776116 ps
CPU time 0.69 seconds
Started May 16 01:50:43 PM PDT 24
Finished May 16 01:50:45 PM PDT 24
Peak memory 195716 kb
Host smart-e0b77ec6-1474-4247-ae18-65b1e7d33806
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211348072 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.4211348072
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.3168862540
Short name T345
Test name
Test status
Simulation time 373204596 ps
CPU time 1.1 seconds
Started May 16 01:50:47 PM PDT 24
Finished May 16 01:50:48 PM PDT 24
Peak memory 183644 kb
Host smart-b1d3351a-8f10-40d6-9348-a2aaee132778
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168862540 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.3168862540
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.2173107017
Short name T73
Test name
Test status
Simulation time 1568623248 ps
CPU time 2.66 seconds
Started May 16 01:50:44 PM PDT 24
Finished May 16 01:50:49 PM PDT 24
Peak memory 193320 kb
Host smart-29713cea-9373-4c4e-88ce-89e38ab045dc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173107017 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon
_timer_same_csr_outstanding.2173107017
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.3600279412
Short name T325
Test name
Test status
Simulation time 385970011 ps
CPU time 2.22 seconds
Started May 16 01:50:43 PM PDT 24
Finished May 16 01:50:47 PM PDT 24
Peak memory 198628 kb
Host smart-ecd064e0-b0ce-4652-b9a3-10eb63469cff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600279412 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.3600279412
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.1507329130
Short name T93
Test name
Test status
Simulation time 8817812600 ps
CPU time 12.22 seconds
Started May 16 01:50:45 PM PDT 24
Finished May 16 01:50:58 PM PDT 24
Peak memory 197880 kb
Host smart-fe54df8f-47a7-4199-b185-9501d43f4929
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507329130 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl
_intg_err.1507329130
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.3057115460
Short name T341
Test name
Test status
Simulation time 406796334 ps
CPU time 0.76 seconds
Started May 16 01:50:44 PM PDT 24
Finished May 16 01:50:46 PM PDT 24
Peak memory 195220 kb
Host smart-230e198c-8be7-4fd4-b90b-c58d18a95246
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057115460 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.3057115460
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.2719984752
Short name T355
Test name
Test status
Simulation time 334613134 ps
CPU time 0.74 seconds
Started May 16 01:50:43 PM PDT 24
Finished May 16 01:50:44 PM PDT 24
Peak memory 183772 kb
Host smart-93b6adc9-ec77-4439-bbca-7aa6365439c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719984752 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.2719984752
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.3150516194
Short name T314
Test name
Test status
Simulation time 500740051 ps
CPU time 0.72 seconds
Started May 16 01:50:43 PM PDT 24
Finished May 16 01:50:44 PM PDT 24
Peak memory 183684 kb
Host smart-6aa52c1f-3d51-48c4-b9a4-1862265e04b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150516194 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.3150516194
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.1981006331
Short name T33
Test name
Test status
Simulation time 2757774416 ps
CPU time 2.88 seconds
Started May 16 01:50:45 PM PDT 24
Finished May 16 01:50:50 PM PDT 24
Peak memory 194512 kb
Host smart-88da02db-6d0b-4ccf-9330-5cf1bfaf4873
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981006331 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon
_timer_same_csr_outstanding.1981006331
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.3688171888
Short name T407
Test name
Test status
Simulation time 424805986 ps
CPU time 1.72 seconds
Started May 16 01:50:44 PM PDT 24
Finished May 16 01:50:47 PM PDT 24
Peak memory 198628 kb
Host smart-24f0a6a0-2b63-4474-8336-e7e8f642d786
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688171888 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.3688171888
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.807438579
Short name T97
Test name
Test status
Simulation time 8223583191 ps
CPU time 4.58 seconds
Started May 16 01:50:44 PM PDT 24
Finished May 16 01:50:50 PM PDT 24
Peak memory 198052 kb
Host smart-cd66ec61-ab55-4cbf-afcc-70ef0c2cf9c4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807438579 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_
intg_err.807438579
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.1566860679
Short name T398
Test name
Test status
Simulation time 815699813 ps
CPU time 0.83 seconds
Started May 16 01:51:04 PM PDT 24
Finished May 16 01:51:07 PM PDT 24
Peak memory 197044 kb
Host smart-1dcfbf3e-cf0a-41d1-8c1a-b3c79b37f580
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566860679 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.1566860679
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.2576531640
Short name T381
Test name
Test status
Simulation time 372643098 ps
CPU time 0.74 seconds
Started May 16 01:50:54 PM PDT 24
Finished May 16 01:50:55 PM PDT 24
Peak memory 183756 kb
Host smart-b508fe3d-c5cb-46dc-bc7a-1af325b86b6c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576531640 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.2576531640
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.2676684829
Short name T408
Test name
Test status
Simulation time 481803117 ps
CPU time 0.73 seconds
Started May 16 01:50:55 PM PDT 24
Finished May 16 01:50:56 PM PDT 24
Peak memory 183684 kb
Host smart-d826f78f-e694-453a-8aa7-fd7c83ce10f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676684829 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.2676684829
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.4218962273
Short name T327
Test name
Test status
Simulation time 1275369335 ps
CPU time 0.98 seconds
Started May 16 01:50:53 PM PDT 24
Finished May 16 01:50:54 PM PDT 24
Peak memory 193316 kb
Host smart-9221f103-e53b-4c05-8e27-8697eab6fd8b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218962273 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon
_timer_same_csr_outstanding.4218962273
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.3267721869
Short name T376
Test name
Test status
Simulation time 553318441 ps
CPU time 1.92 seconds
Started May 16 01:50:43 PM PDT 24
Finished May 16 01:50:46 PM PDT 24
Peak memory 198536 kb
Host smart-7424a258-bba5-41dd-81df-7b2d557769ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267721869 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.3267721869
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.2292517992
Short name T350
Test name
Test status
Simulation time 511332436 ps
CPU time 1.36 seconds
Started May 16 01:51:04 PM PDT 24
Finished May 16 01:51:08 PM PDT 24
Peak memory 196068 kb
Host smart-cde51f59-d24d-4a90-bf3a-694b87e4adf2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292517992 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.2292517992
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.2870047384
Short name T305
Test name
Test status
Simulation time 369717000 ps
CPU time 1.09 seconds
Started May 16 01:51:03 PM PDT 24
Finished May 16 01:51:05 PM PDT 24
Peak memory 183752 kb
Host smart-69f06505-d75d-4a2f-8652-f457c8b2b4fd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870047384 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.2870047384
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.2650106095
Short name T274
Test name
Test status
Simulation time 348081956 ps
CPU time 0.65 seconds
Started May 16 01:51:05 PM PDT 24
Finished May 16 01:51:08 PM PDT 24
Peak memory 183604 kb
Host smart-3353ba4a-a35f-405a-9ad1-c4041d26436e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650106095 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.2650106095
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.677702006
Short name T328
Test name
Test status
Simulation time 1581897024 ps
CPU time 1.47 seconds
Started May 16 01:51:05 PM PDT 24
Finished May 16 01:51:09 PM PDT 24
Peak memory 183820 kb
Host smart-16216ff1-5c40-4e45-bc31-3049f07ada5b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677702006 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_
timer_same_csr_outstanding.677702006
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.336378428
Short name T406
Test name
Test status
Simulation time 634940186 ps
CPU time 1.17 seconds
Started May 16 01:51:04 PM PDT 24
Finished May 16 01:51:07 PM PDT 24
Peak memory 198360 kb
Host smart-80f52f8e-9132-46c1-a148-451f1da3352d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336378428 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.336378428
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.3560786232
Short name T98
Test name
Test status
Simulation time 4533737610 ps
CPU time 2.22 seconds
Started May 16 01:51:05 PM PDT 24
Finished May 16 01:51:10 PM PDT 24
Peak memory 197772 kb
Host smart-ce477613-976b-4f8d-a7bd-02c822088838
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560786232 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl
_intg_err.3560786232
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_jump.2709207954
Short name T191
Test name
Test status
Simulation time 542939050 ps
CPU time 1.36 seconds
Started May 16 02:55:29 PM PDT 24
Finished May 16 02:55:36 PM PDT 24
Peak memory 183508 kb
Host smart-114b8bff-0ee4-44fc-ae6a-546b897a2e83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709207954 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.2709207954
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.3059346768
Short name T232
Test name
Test status
Simulation time 10619688367 ps
CPU time 1.45 seconds
Started May 16 02:55:28 PM PDT 24
Finished May 16 02:55:36 PM PDT 24
Peak memory 183604 kb
Host smart-87c38001-9482-4827-9c7f-4eca1fd1efce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059346768 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.3059346768
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.3144894409
Short name T190
Test name
Test status
Simulation time 461906290 ps
CPU time 0.96 seconds
Started May 16 02:55:26 PM PDT 24
Finished May 16 02:55:33 PM PDT 24
Peak memory 183548 kb
Host smart-227b4ffa-e663-4299-9aac-a60211c3c0f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144894409 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.3144894409
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.3408825935
Short name T135
Test name
Test status
Simulation time 152405620500 ps
CPU time 235.77 seconds
Started May 16 02:55:30 PM PDT 24
Finished May 16 02:59:32 PM PDT 24
Peak memory 194196 kb
Host smart-02a83486-d47c-4cc6-854f-5b70bd7218d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408825935 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_a
ll.3408825935
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_jump.3961064695
Short name T154
Test name
Test status
Simulation time 544443172 ps
CPU time 1.42 seconds
Started May 16 02:55:30 PM PDT 24
Finished May 16 02:55:38 PM PDT 24
Peak memory 183516 kb
Host smart-684684c6-24d4-4ce5-b4dd-47a5065d7355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961064695 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.3961064695
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.2372467061
Short name T233
Test name
Test status
Simulation time 10043010863 ps
CPU time 3.6 seconds
Started May 16 02:55:28 PM PDT 24
Finished May 16 02:55:38 PM PDT 24
Peak memory 183600 kb
Host smart-d1b1973d-11b8-47e2-af00-ebf013508ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372467061 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.2372467061
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.2377055358
Short name T16
Test name
Test status
Simulation time 7679529965 ps
CPU time 11.96 seconds
Started May 16 02:55:28 PM PDT 24
Finished May 16 02:55:47 PM PDT 24
Peak memory 215292 kb
Host smart-8c05c0db-0603-4740-a9cc-45df60966fe2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377055358 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.2377055358
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.1019710199
Short name T124
Test name
Test status
Simulation time 509643580 ps
CPU time 0.92 seconds
Started May 16 02:55:28 PM PDT 24
Finished May 16 02:55:36 PM PDT 24
Peak memory 183548 kb
Host smart-8678f2a0-97d8-4d4f-ba0e-c332eefa8f6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019710199 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.1019710199
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.2942052463
Short name T163
Test name
Test status
Simulation time 79311789730 ps
CPU time 123.64 seconds
Started May 16 02:55:28 PM PDT 24
Finished May 16 02:57:38 PM PDT 24
Peak memory 191772 kb
Host smart-dd53ac15-8c9b-440f-a2ce-2e1661f731b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942052463 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_a
ll.2942052463
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/10.aon_timer_jump.3150675673
Short name T107
Test name
Test status
Simulation time 499352978 ps
CPU time 1.34 seconds
Started May 16 02:55:39 PM PDT 24
Finished May 16 02:55:43 PM PDT 24
Peak memory 183180 kb
Host smart-8166ac6f-c07f-4f34-821f-a0cdea6d6f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150675673 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.3150675673
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.3487375112
Short name T110
Test name
Test status
Simulation time 11554410418 ps
CPU time 18.88 seconds
Started May 16 02:55:36 PM PDT 24
Finished May 16 02:55:59 PM PDT 24
Peak memory 183540 kb
Host smart-e13f0328-590b-470c-90cc-e8091785a97d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487375112 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.3487375112
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.1855415339
Short name T150
Test name
Test status
Simulation time 520692446 ps
CPU time 0.77 seconds
Started May 16 02:55:45 PM PDT 24
Finished May 16 02:55:47 PM PDT 24
Peak memory 183024 kb
Host smart-6e344e79-9470-422f-b593-5f59254dcd09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855415339 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.1855415339
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.3339468775
Short name T187
Test name
Test status
Simulation time 127382958032 ps
CPU time 36.54 seconds
Started May 16 02:55:38 PM PDT 24
Finished May 16 02:56:17 PM PDT 24
Peak memory 193556 kb
Host smart-83e04e56-aa60-4f05-bc72-603ef7f94162
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339468775 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_
all.3339468775
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_jump.1267542128
Short name T244
Test name
Test status
Simulation time 422017615 ps
CPU time 0.73 seconds
Started May 16 02:55:45 PM PDT 24
Finished May 16 02:55:47 PM PDT 24
Peak memory 182888 kb
Host smart-4eafb5d7-96ca-4b24-ba33-c7c71560a029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267542128 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.1267542128
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.3476725800
Short name T164
Test name
Test status
Simulation time 10145699497 ps
CPU time 9 seconds
Started May 16 02:55:36 PM PDT 24
Finished May 16 02:55:49 PM PDT 24
Peak memory 183612 kb
Host smart-670b8e4e-6355-4d72-a7b1-e38575fd2ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476725800 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.3476725800
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.1107432074
Short name T228
Test name
Test status
Simulation time 486647723 ps
CPU time 1.22 seconds
Started May 16 02:55:46 PM PDT 24
Finished May 16 02:55:49 PM PDT 24
Peak memory 183544 kb
Host smart-2748bbc9-c605-413b-b13b-fdc499aefd5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107432074 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.1107432074
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.3052906907
Short name T85
Test name
Test status
Simulation time 91845253252 ps
CPU time 164.04 seconds
Started May 16 02:55:49 PM PDT 24
Finished May 16 02:58:36 PM PDT 24
Peak memory 198468 kb
Host smart-92cfd47c-6dab-4081-ba97-db34422cda9e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052906907 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand_reset.3052906907
Directory /workspace/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.aon_timer_jump.3591522048
Short name T241
Test name
Test status
Simulation time 579221130 ps
CPU time 0.81 seconds
Started May 16 02:55:48 PM PDT 24
Finished May 16 02:55:52 PM PDT 24
Peak memory 183516 kb
Host smart-9d6b0032-ca0e-4c6d-93ab-d96b364e82b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591522048 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.3591522048
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.2182935861
Short name T36
Test name
Test status
Simulation time 36101288257 ps
CPU time 61.8 seconds
Started May 16 02:55:48 PM PDT 24
Finished May 16 02:56:53 PM PDT 24
Peak memory 191728 kb
Host smart-55fbd6ef-a251-45da-a1cc-e3a4dbb9a2be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182935861 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.2182935861
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.1137959046
Short name T234
Test name
Test status
Simulation time 468972749 ps
CPU time 1.27 seconds
Started May 16 02:55:48 PM PDT 24
Finished May 16 02:55:52 PM PDT 24
Peak memory 183504 kb
Host smart-22fa28f3-b8d6-4b82-b5d5-7685822e7738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137959046 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.1137959046
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.1258300063
Short name T29
Test name
Test status
Simulation time 388965796214 ps
CPU time 128.12 seconds
Started May 16 02:55:49 PM PDT 24
Finished May 16 02:58:00 PM PDT 24
Peak memory 193916 kb
Host smart-419597be-154e-4e60-8c2b-b6702807b2ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258300063 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_
all.1258300063
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.3485015569
Short name T151
Test name
Test status
Simulation time 71581299927 ps
CPU time 168.52 seconds
Started May 16 02:55:46 PM PDT 24
Finished May 16 02:58:37 PM PDT 24
Peak memory 198372 kb
Host smart-ce937420-0f5a-4566-ab27-6e7fec62f99f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485015569 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.3485015569
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_jump.1374412030
Short name T128
Test name
Test status
Simulation time 449625784 ps
CPU time 0.87 seconds
Started May 16 02:55:48 PM PDT 24
Finished May 16 02:55:52 PM PDT 24
Peak memory 183508 kb
Host smart-32a8aa2f-f455-4bde-b69f-ac751cf4410c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374412030 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.1374412030
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.908075716
Short name T203
Test name
Test status
Simulation time 15984305479 ps
CPU time 7.79 seconds
Started May 16 02:55:49 PM PDT 24
Finished May 16 02:55:59 PM PDT 24
Peak memory 183604 kb
Host smart-587bc3fd-c044-49dc-bf3d-8b76afd1b668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908075716 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.908075716
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.1608957466
Short name T247
Test name
Test status
Simulation time 590990898 ps
CPU time 0.74 seconds
Started May 16 02:55:52 PM PDT 24
Finished May 16 02:55:55 PM PDT 24
Peak memory 183544 kb
Host smart-c52e9c83-0f2f-465b-b5d4-e2d0a07e7c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608957466 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.1608957466
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.4208921322
Short name T195
Test name
Test status
Simulation time 35501840239 ps
CPU time 12.77 seconds
Started May 16 02:55:48 PM PDT 24
Finished May 16 02:56:04 PM PDT 24
Peak memory 195524 kb
Host smart-97b91901-8185-41ae-b625-3fb81c01846c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208921322 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_
all.4208921322
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_jump.1571952002
Short name T25
Test name
Test status
Simulation time 452216380 ps
CPU time 0.71 seconds
Started May 16 02:55:50 PM PDT 24
Finished May 16 02:55:53 PM PDT 24
Peak memory 183548 kb
Host smart-035b0ee5-9229-42cc-91bd-0634b99cab70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571952002 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.1571952002
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.106666251
Short name T257
Test name
Test status
Simulation time 13717443957 ps
CPU time 5.61 seconds
Started May 16 02:55:47 PM PDT 24
Finished May 16 02:55:55 PM PDT 24
Peak memory 183584 kb
Host smart-8678feaa-b1f3-42ab-8492-99b0e4fdb0dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106666251 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.106666251
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.2187828387
Short name T165
Test name
Test status
Simulation time 375462985 ps
CPU time 1.05 seconds
Started May 16 02:55:48 PM PDT 24
Finished May 16 02:55:52 PM PDT 24
Peak memory 183508 kb
Host smart-0e99add1-e420-433b-a9cf-f024ce558a1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187828387 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.2187828387
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.2078979104
Short name T212
Test name
Test status
Simulation time 165313589966 ps
CPU time 70.64 seconds
Started May 16 02:55:49 PM PDT 24
Finished May 16 02:57:03 PM PDT 24
Peak memory 198496 kb
Host smart-6e7b1def-a0d2-40a8-abff-1c2f5676dd7b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078979104 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.2078979104
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.aon_timer_jump.3110456239
Short name T129
Test name
Test status
Simulation time 494638007 ps
CPU time 0.94 seconds
Started May 16 02:55:48 PM PDT 24
Finished May 16 02:55:52 PM PDT 24
Peak memory 183576 kb
Host smart-2be4f308-2619-41f5-a23f-5a87de7a5d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110456239 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.3110456239
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.4031042114
Short name T156
Test name
Test status
Simulation time 35920319611 ps
CPU time 50.3 seconds
Started May 16 02:55:48 PM PDT 24
Finished May 16 02:56:41 PM PDT 24
Peak memory 183576 kb
Host smart-6626ce6f-b432-4bfe-bc19-f90a6bb47d26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031042114 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.4031042114
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.1739654480
Short name T231
Test name
Test status
Simulation time 430109155 ps
CPU time 1.12 seconds
Started May 16 02:55:49 PM PDT 24
Finished May 16 02:55:53 PM PDT 24
Peak memory 183380 kb
Host smart-a26c306f-1456-4398-8bfb-8375523bdef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739654480 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.1739654480
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.2432438967
Short name T114
Test name
Test status
Simulation time 237016667291 ps
CPU time 171.6 seconds
Started May 16 02:55:58 PM PDT 24
Finished May 16 02:58:51 PM PDT 24
Peak memory 195044 kb
Host smart-95623b6a-360b-44e3-b87e-8dd0ad423aa9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432438967 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_
all.2432438967
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_jump.3136148908
Short name T199
Test name
Test status
Simulation time 590047659 ps
CPU time 0.85 seconds
Started May 16 02:56:03 PM PDT 24
Finished May 16 02:56:05 PM PDT 24
Peak memory 183532 kb
Host smart-caad975f-08ca-440e-9f15-01d2acfdaa17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136148908 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.3136148908
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.2865493305
Short name T229
Test name
Test status
Simulation time 45407059822 ps
CPU time 30.88 seconds
Started May 16 02:56:01 PM PDT 24
Finished May 16 02:56:34 PM PDT 24
Peak memory 183552 kb
Host smart-3d2502c8-fdc5-4ee1-abbc-72bd756c543f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865493305 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.2865493305
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.2217852777
Short name T24
Test name
Test status
Simulation time 375105600 ps
CPU time 0.69 seconds
Started May 16 02:55:59 PM PDT 24
Finished May 16 02:56:01 PM PDT 24
Peak memory 183388 kb
Host smart-1f91277e-2333-4318-a317-e73d7e8244e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217852777 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.2217852777
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.2437102705
Short name T224
Test name
Test status
Simulation time 176673833384 ps
CPU time 153.9 seconds
Started May 16 02:56:00 PM PDT 24
Finished May 16 02:58:37 PM PDT 24
Peak memory 183504 kb
Host smart-6a7bc686-9c41-4c0c-85fb-7bba3d13d881
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437102705 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_
all.2437102705
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.2196926231
Short name T40
Test name
Test status
Simulation time 32320581844 ps
CPU time 65.94 seconds
Started May 16 02:56:00 PM PDT 24
Finished May 16 02:57:09 PM PDT 24
Peak memory 198480 kb
Host smart-e26ce4be-6e2e-4502-a5b5-ce485826bd7c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196926231 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.2196926231
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.aon_timer_jump.3104321248
Short name T230
Test name
Test status
Simulation time 461126017 ps
CPU time 1.38 seconds
Started May 16 02:56:00 PM PDT 24
Finished May 16 02:56:04 PM PDT 24
Peak memory 183480 kb
Host smart-c92061d8-a447-454c-ad67-16627025d78e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104321248 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.3104321248
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.1758116723
Short name T144
Test name
Test status
Simulation time 37155890766 ps
CPU time 30.34 seconds
Started May 16 02:56:00 PM PDT 24
Finished May 16 02:56:33 PM PDT 24
Peak memory 183572 kb
Host smart-3a5a03eb-5a5a-408a-aff1-483d99cb2bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758116723 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.1758116723
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.206291469
Short name T100
Test name
Test status
Simulation time 655799539 ps
CPU time 0.65 seconds
Started May 16 02:56:00 PM PDT 24
Finished May 16 02:56:04 PM PDT 24
Peak memory 183488 kb
Host smart-dd7a032d-f338-4784-b1dc-7e1a4d8b45c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206291469 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.206291469
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.115941917
Short name T264
Test name
Test status
Simulation time 51665210917 ps
CPU time 20.75 seconds
Started May 16 02:56:02 PM PDT 24
Finished May 16 02:56:25 PM PDT 24
Peak memory 193876 kb
Host smart-5295882e-b962-46f3-abda-e989e9709168
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115941917 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_a
ll.115941917
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_jump.1719867380
Short name T178
Test name
Test status
Simulation time 556424461 ps
CPU time 1.01 seconds
Started May 16 02:56:04 PM PDT 24
Finished May 16 02:56:06 PM PDT 24
Peak memory 183484 kb
Host smart-58aef138-a5d4-4055-abf2-375b27f59bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719867380 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.1719867380
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.3276332009
Short name T160
Test name
Test status
Simulation time 50540401677 ps
CPU time 80.02 seconds
Started May 16 02:56:00 PM PDT 24
Finished May 16 02:57:22 PM PDT 24
Peak memory 191748 kb
Host smart-514739e6-4156-4dfc-b9ed-ec0193ea25bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276332009 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.3276332009
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.2232411293
Short name T271
Test name
Test status
Simulation time 414367492 ps
CPU time 1.14 seconds
Started May 16 02:56:00 PM PDT 24
Finished May 16 02:56:03 PM PDT 24
Peak memory 183528 kb
Host smart-5984e752-142b-4108-a158-8028009fb0c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232411293 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.2232411293
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.355021808
Short name T242
Test name
Test status
Simulation time 208305673432 ps
CPU time 85.32 seconds
Started May 16 02:56:00 PM PDT 24
Finished May 16 02:57:28 PM PDT 24
Peak memory 191736 kb
Host smart-a7a6e307-89c8-4c67-8bcd-903457485b57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355021808 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_a
ll.355021808
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.3736065151
Short name T221
Test name
Test status
Simulation time 142880720756 ps
CPU time 211.91 seconds
Started May 16 02:56:00 PM PDT 24
Finished May 16 02:59:35 PM PDT 24
Peak memory 198444 kb
Host smart-e7462e6a-e93e-4f8c-8d75-226265f48c78
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736065151 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.3736065151
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.aon_timer_jump.4043719263
Short name T266
Test name
Test status
Simulation time 493467638 ps
CPU time 0.99 seconds
Started May 16 02:56:00 PM PDT 24
Finished May 16 02:56:03 PM PDT 24
Peak memory 183480 kb
Host smart-4a94d242-8b80-432a-a138-797a822083f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043719263 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.4043719263
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.3653680216
Short name T119
Test name
Test status
Simulation time 11751607134 ps
CPU time 4.62 seconds
Started May 16 02:56:00 PM PDT 24
Finished May 16 02:56:07 PM PDT 24
Peak memory 183612 kb
Host smart-ddfe4406-3424-4b0f-a991-e46e6d076ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653680216 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.3653680216
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.4008136324
Short name T181
Test name
Test status
Simulation time 414024386 ps
CPU time 0.86 seconds
Started May 16 02:56:02 PM PDT 24
Finished May 16 02:56:05 PM PDT 24
Peak memory 183532 kb
Host smart-23361295-5f56-4fe3-813c-c089209fe769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008136324 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.4008136324
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.20401957
Short name T171
Test name
Test status
Simulation time 227921382281 ps
CPU time 166.74 seconds
Started May 16 02:55:59 PM PDT 24
Finished May 16 02:58:47 PM PDT 24
Peak memory 192900 kb
Host smart-38c4e8f8-b92e-48d0-9406-a3dbc5aa9a3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20401957 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_al
l.20401957
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_jump.425502377
Short name T183
Test name
Test status
Simulation time 390154130 ps
CPU time 0.91 seconds
Started May 16 02:55:29 PM PDT 24
Finished May 16 02:55:37 PM PDT 24
Peak memory 183516 kb
Host smart-c919e68e-f994-44c9-8c10-8f66fefd1205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425502377 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.425502377
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.1451133790
Short name T273
Test name
Test status
Simulation time 37653915957 ps
CPU time 57.7 seconds
Started May 16 02:55:27 PM PDT 24
Finished May 16 02:56:31 PM PDT 24
Peak memory 183588 kb
Host smart-c6524029-2719-4b7a-aa1f-6ec8bb655cca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451133790 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.1451133790
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.3009475556
Short name T13
Test name
Test status
Simulation time 4831389519 ps
CPU time 8.42 seconds
Started May 16 02:55:28 PM PDT 24
Finished May 16 02:55:43 PM PDT 24
Peak memory 215184 kb
Host smart-181bfdd6-bf71-489d-bef5-f2a9b652e859
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009475556 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.3009475556
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.16406407
Short name T3
Test name
Test status
Simulation time 505300700 ps
CPU time 0.68 seconds
Started May 16 02:55:31 PM PDT 24
Finished May 16 02:55:38 PM PDT 24
Peak memory 183456 kb
Host smart-e2e97b1f-a870-4f9a-9086-bd7e6be4caef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16406407 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.16406407
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.3635337456
Short name T254
Test name
Test status
Simulation time 297664172811 ps
CPU time 473.68 seconds
Started May 16 02:55:30 PM PDT 24
Finished May 16 03:03:30 PM PDT 24
Peak memory 183624 kb
Host smart-c00b28ee-4c98-42ef-b644-fb640d9c78fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635337456 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_a
ll.3635337456
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.1312145178
Short name T84
Test name
Test status
Simulation time 11275859746 ps
CPU time 79.53 seconds
Started May 16 02:55:32 PM PDT 24
Finished May 16 02:56:57 PM PDT 24
Peak memory 198484 kb
Host smart-3b3488e3-8252-4e34-88da-c04b2a2f33f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312145178 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.1312145178
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.aon_timer_jump.1698956163
Short name T101
Test name
Test status
Simulation time 477225062 ps
CPU time 0.72 seconds
Started May 16 02:56:00 PM PDT 24
Finished May 16 02:56:03 PM PDT 24
Peak memory 183520 kb
Host smart-6d383fe9-e949-4d86-b98d-d2d8fcd44197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698956163 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.1698956163
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.434237335
Short name T2
Test name
Test status
Simulation time 10548859395 ps
CPU time 4.3 seconds
Started May 16 02:56:00 PM PDT 24
Finished May 16 02:56:06 PM PDT 24
Peak memory 183560 kb
Host smart-5ee9781b-c55d-4e45-a96a-21dddda10014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434237335 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.434237335
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.4218525710
Short name T268
Test name
Test status
Simulation time 519098262 ps
CPU time 0.72 seconds
Started May 16 02:56:00 PM PDT 24
Finished May 16 02:56:02 PM PDT 24
Peak memory 183556 kb
Host smart-096620b0-275d-4325-93c3-2770325a9609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218525710 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.4218525710
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.3102246130
Short name T88
Test name
Test status
Simulation time 380865418952 ps
CPU time 271.68 seconds
Started May 16 02:55:58 PM PDT 24
Finished May 16 03:00:31 PM PDT 24
Peak memory 195156 kb
Host smart-cf631a61-8b3e-4b9d-b9f6-0d1bbb4e0e77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102246130 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_
all.3102246130
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.3565443889
Short name T80
Test name
Test status
Simulation time 361674150877 ps
CPU time 828.84 seconds
Started May 16 02:56:03 PM PDT 24
Finished May 16 03:09:53 PM PDT 24
Peak memory 201504 kb
Host smart-cdc79129-636a-458d-a896-c66f81d79a4d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565443889 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.3565443889
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_jump.3411798602
Short name T148
Test name
Test status
Simulation time 475707056 ps
CPU time 1.22 seconds
Started May 16 02:56:00 PM PDT 24
Finished May 16 02:56:03 PM PDT 24
Peak memory 183508 kb
Host smart-205ac336-c3eb-47e8-a649-e27b90195c74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411798602 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.3411798602
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.290052624
Short name T26
Test name
Test status
Simulation time 16517953464 ps
CPU time 2.78 seconds
Started May 16 02:55:59 PM PDT 24
Finished May 16 02:56:03 PM PDT 24
Peak memory 191800 kb
Host smart-897402c9-dd13-4106-bd40-6f6f6fe7d23d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290052624 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.290052624
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.4034010528
Short name T219
Test name
Test status
Simulation time 402091245 ps
CPU time 0.64 seconds
Started May 16 02:55:57 PM PDT 24
Finished May 16 02:55:59 PM PDT 24
Peak memory 183464 kb
Host smart-f744a25b-05e1-4a87-b6ef-826fa1d46a1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034010528 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.4034010528
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.2420364210
Short name T116
Test name
Test status
Simulation time 191515110573 ps
CPU time 68.66 seconds
Started May 16 02:56:09 PM PDT 24
Finished May 16 02:57:21 PM PDT 24
Peak memory 195408 kb
Host smart-41b21561-a99e-475b-b60c-2b8b95b4b405
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420364210 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_
all.2420364210
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.4077033461
Short name T7
Test name
Test status
Simulation time 164538209073 ps
CPU time 1226.45 seconds
Started May 16 02:56:02 PM PDT 24
Finished May 16 03:16:31 PM PDT 24
Peak memory 206252 kb
Host smart-0739745d-3323-4bcc-b696-ae8a69e4110f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077033461 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.4077033461
Directory /workspace/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.aon_timer_jump.1029826547
Short name T176
Test name
Test status
Simulation time 505843038 ps
CPU time 0.76 seconds
Started May 16 02:56:08 PM PDT 24
Finished May 16 02:56:10 PM PDT 24
Peak memory 183496 kb
Host smart-14d7e704-cf7c-49b6-9295-fbe911752475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029826547 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.1029826547
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.2293319863
Short name T118
Test name
Test status
Simulation time 5733303138 ps
CPU time 8.33 seconds
Started May 16 02:56:09 PM PDT 24
Finished May 16 02:56:20 PM PDT 24
Peak memory 183588 kb
Host smart-e41a1cd3-bd59-4f31-9e30-0eeec02986ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293319863 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.2293319863
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.3117642436
Short name T46
Test name
Test status
Simulation time 333763992 ps
CPU time 1.07 seconds
Started May 16 02:56:09 PM PDT 24
Finished May 16 02:56:13 PM PDT 24
Peak memory 183388 kb
Host smart-764d495e-63e6-4b77-858c-bbf4b30eaaaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117642436 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.3117642436
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.3508649881
Short name T10
Test name
Test status
Simulation time 52170701519 ps
CPU time 82.58 seconds
Started May 16 02:56:08 PM PDT 24
Finished May 16 02:57:33 PM PDT 24
Peak memory 183624 kb
Host smart-f9eaef49-f999-48a5-b2be-a8e03e2bf921
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508649881 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_
all.3508649881
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.1473170933
Short name T77
Test name
Test status
Simulation time 30421558862 ps
CPU time 313.54 seconds
Started May 16 02:56:09 PM PDT 24
Finished May 16 03:01:26 PM PDT 24
Peak memory 198456 kb
Host smart-a8391711-40f7-4e46-883b-99adfe2b1a78
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473170933 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.1473170933
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.aon_timer_jump.336663418
Short name T120
Test name
Test status
Simulation time 484715964 ps
CPU time 0.74 seconds
Started May 16 02:56:09 PM PDT 24
Finished May 16 02:56:12 PM PDT 24
Peak memory 183536 kb
Host smart-a7da9320-4501-46d4-928b-05e19481d8f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336663418 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.336663418
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.2522191398
Short name T131
Test name
Test status
Simulation time 1139730042 ps
CPU time 0.93 seconds
Started May 16 02:56:11 PM PDT 24
Finished May 16 02:56:14 PM PDT 24
Peak memory 183480 kb
Host smart-babe2d44-a5c7-496e-9865-37a225037bb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522191398 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.2522191398
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.4020882032
Short name T52
Test name
Test status
Simulation time 517516820 ps
CPU time 0.63 seconds
Started May 16 02:56:08 PM PDT 24
Finished May 16 02:56:11 PM PDT 24
Peak memory 183472 kb
Host smart-bacaa14c-669c-4aa5-8e31-0a49c530579e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020882032 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.4020882032
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.1454139885
Short name T86
Test name
Test status
Simulation time 34693068764 ps
CPU time 263.81 seconds
Started May 16 02:56:08 PM PDT 24
Finished May 16 03:00:33 PM PDT 24
Peak memory 198484 kb
Host smart-6d5ccfa0-813f-41e9-a84e-a603cd03ca73
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454139885 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.1454139885
Directory /workspace/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.aon_timer_jump.719335765
Short name T251
Test name
Test status
Simulation time 432984321 ps
CPU time 1.12 seconds
Started May 16 02:56:11 PM PDT 24
Finished May 16 02:56:14 PM PDT 24
Peak memory 183476 kb
Host smart-c0c422cc-be37-406a-aba5-a63fdb9f8d3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719335765 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.719335765
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.159610981
Short name T108
Test name
Test status
Simulation time 4736192044 ps
CPU time 3.86 seconds
Started May 16 02:56:09 PM PDT 24
Finished May 16 02:56:15 PM PDT 24
Peak memory 183520 kb
Host smart-d7b93a14-1371-499f-8ab2-eef7e713b89b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159610981 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.159610981
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.78215755
Short name T253
Test name
Test status
Simulation time 378776423 ps
CPU time 1.16 seconds
Started May 16 02:56:08 PM PDT 24
Finished May 16 02:56:12 PM PDT 24
Peak memory 183500 kb
Host smart-4788ce1c-4b79-490f-820a-c64fd779b4a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78215755 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.78215755
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.2219138850
Short name T146
Test name
Test status
Simulation time 161141595865 ps
CPU time 217.6 seconds
Started May 16 02:56:12 PM PDT 24
Finished May 16 02:59:51 PM PDT 24
Peak memory 193216 kb
Host smart-1d3f6b22-504b-4f88-b177-fb8cfce327e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219138850 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_
all.2219138850
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/25.aon_timer_jump.1608733795
Short name T208
Test name
Test status
Simulation time 620646999 ps
CPU time 0.88 seconds
Started May 16 02:56:09 PM PDT 24
Finished May 16 02:56:13 PM PDT 24
Peak memory 183492 kb
Host smart-dfde5311-22c7-4623-b994-ebd654e59169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608733795 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.1608733795
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.2414814032
Short name T113
Test name
Test status
Simulation time 5344669692 ps
CPU time 1.21 seconds
Started May 16 02:56:07 PM PDT 24
Finished May 16 02:56:09 PM PDT 24
Peak memory 183596 kb
Host smart-51fc31df-a6e2-4bc2-a3b1-6f6330698c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414814032 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.2414814032
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.2994440559
Short name T174
Test name
Test status
Simulation time 453532879 ps
CPU time 1.27 seconds
Started May 16 02:56:09 PM PDT 24
Finished May 16 02:56:13 PM PDT 24
Peak memory 183488 kb
Host smart-0d9a65a4-6e13-43db-b8ca-2178c36b45de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994440559 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.2994440559
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.1667817609
Short name T186
Test name
Test status
Simulation time 84080610248 ps
CPU time 36.61 seconds
Started May 16 02:56:08 PM PDT 24
Finished May 16 02:56:47 PM PDT 24
Peak memory 183592 kb
Host smart-5a03e5d9-feab-4edd-b098-10ea9b611ca5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667817609 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_
all.1667817609
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.3844218623
Short name T198
Test name
Test status
Simulation time 88448154794 ps
CPU time 125.88 seconds
Started May 16 02:56:12 PM PDT 24
Finished May 16 02:58:19 PM PDT 24
Peak memory 198408 kb
Host smart-6ddee64d-2aa3-4ea1-8141-f9b8eb321010
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844218623 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.3844218623
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.aon_timer_jump.3020594980
Short name T127
Test name
Test status
Simulation time 483302716 ps
CPU time 1.35 seconds
Started May 16 02:56:09 PM PDT 24
Finished May 16 02:56:13 PM PDT 24
Peak memory 183508 kb
Host smart-d4482475-8041-468a-9d63-0baeffb0542b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020594980 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.3020594980
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.2898401566
Short name T168
Test name
Test status
Simulation time 45353877504 ps
CPU time 66.29 seconds
Started May 16 02:56:08 PM PDT 24
Finished May 16 02:57:16 PM PDT 24
Peak memory 191800 kb
Host smart-f15634c9-e656-45af-adf3-bd98c285ee1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898401566 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.2898401566
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.345560480
Short name T213
Test name
Test status
Simulation time 489324208 ps
CPU time 0.89 seconds
Started May 16 02:56:10 PM PDT 24
Finished May 16 02:56:14 PM PDT 24
Peak memory 183480 kb
Host smart-c1224471-51bf-40f5-a093-1a0e4588e58f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345560480 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.345560480
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.157807206
Short name T125
Test name
Test status
Simulation time 22920387026 ps
CPU time 9.7 seconds
Started May 16 02:56:11 PM PDT 24
Finished May 16 02:56:23 PM PDT 24
Peak memory 194520 kb
Host smart-7d0d2bfe-9ec7-42dd-88d2-490b9f800b0f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157807206 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_a
ll.157807206
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/27.aon_timer_jump.961232686
Short name T112
Test name
Test status
Simulation time 441305658 ps
CPU time 1.31 seconds
Started May 16 02:56:10 PM PDT 24
Finished May 16 02:56:14 PM PDT 24
Peak memory 183476 kb
Host smart-85d14660-714f-431f-8010-5b19536cc626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961232686 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.961232686
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.1173448891
Short name T249
Test name
Test status
Simulation time 37020475040 ps
CPU time 61.99 seconds
Started May 16 02:56:08 PM PDT 24
Finished May 16 02:57:11 PM PDT 24
Peak memory 183548 kb
Host smart-586626e9-7d49-426f-bc83-26fe26d3b88d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173448891 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.1173448891
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.620377907
Short name T179
Test name
Test status
Simulation time 431356028 ps
CPU time 0.95 seconds
Started May 16 02:56:11 PM PDT 24
Finished May 16 02:56:14 PM PDT 24
Peak memory 183552 kb
Host smart-6f28de62-1eb1-4456-8cd8-c5842a32c46d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620377907 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.620377907
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.3156635860
Short name T197
Test name
Test status
Simulation time 20686598155 ps
CPU time 32.37 seconds
Started May 16 02:56:09 PM PDT 24
Finished May 16 02:56:44 PM PDT 24
Peak memory 195152 kb
Host smart-ea0acb13-8a85-4112-b623-9034ea3c1320
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156635860 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_
all.3156635860
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.2880875223
Short name T54
Test name
Test status
Simulation time 271554160625 ps
CPU time 443.5 seconds
Started May 16 02:56:08 PM PDT 24
Finished May 16 03:03:33 PM PDT 24
Peak memory 198508 kb
Host smart-d70dbb8f-6df5-42b8-a40d-64b089399d72
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880875223 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.2880875223
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_jump.4008154361
Short name T267
Test name
Test status
Simulation time 505897559 ps
CPU time 1.39 seconds
Started May 16 02:56:08 PM PDT 24
Finished May 16 02:56:12 PM PDT 24
Peak memory 183480 kb
Host smart-922fcd94-228d-4cc3-9e2b-ab962b67dcc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008154361 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.4008154361
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.1733973679
Short name T152
Test name
Test status
Simulation time 3034693570 ps
CPU time 1.54 seconds
Started May 16 02:56:10 PM PDT 24
Finished May 16 02:56:14 PM PDT 24
Peak memory 183568 kb
Host smart-20ad484a-041b-4471-bfd2-e694f0277002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733973679 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.1733973679
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.4079036694
Short name T48
Test name
Test status
Simulation time 425590088 ps
CPU time 0.7 seconds
Started May 16 02:56:10 PM PDT 24
Finished May 16 02:56:13 PM PDT 24
Peak memory 183512 kb
Host smart-2e71fa99-b8ab-4259-a1b5-98ed7985ef9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079036694 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.4079036694
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.1333489624
Short name T89
Test name
Test status
Simulation time 69430990631 ps
CPU time 774.12 seconds
Started May 16 02:56:08 PM PDT 24
Finished May 16 03:09:05 PM PDT 24
Peak memory 200904 kb
Host smart-fcdd8bac-68f0-4066-988c-790b4ba9f4d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333489624 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.1333489624
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.aon_timer_jump.3127965512
Short name T147
Test name
Test status
Simulation time 357288558 ps
CPU time 1.09 seconds
Started May 16 02:56:25 PM PDT 24
Finished May 16 02:56:29 PM PDT 24
Peak memory 183492 kb
Host smart-14fd2a3b-8be9-48c7-9752-94cc18477a64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127965512 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.3127965512
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.2799425376
Short name T50
Test name
Test status
Simulation time 40258580318 ps
CPU time 16.05 seconds
Started May 16 02:56:19 PM PDT 24
Finished May 16 02:56:37 PM PDT 24
Peak memory 183576 kb
Host smart-eadfce8d-6ee1-46a9-8f54-bf99784e7010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799425376 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.2799425376
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.3830481453
Short name T141
Test name
Test status
Simulation time 391000408 ps
CPU time 0.71 seconds
Started May 16 02:56:18 PM PDT 24
Finished May 16 02:56:20 PM PDT 24
Peak memory 183508 kb
Host smart-8a3187a4-4f13-44a7-b0c0-32d19ff339ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830481453 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.3830481453
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.916779629
Short name T210
Test name
Test status
Simulation time 63177775446 ps
CPU time 96.95 seconds
Started May 16 02:56:19 PM PDT 24
Finished May 16 02:57:58 PM PDT 24
Peak memory 194104 kb
Host smart-c532ad8e-1b4b-43d5-bffe-15572c3db43a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916779629 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_a
ll.916779629
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_jump.1267901987
Short name T143
Test name
Test status
Simulation time 568649895 ps
CPU time 0.94 seconds
Started May 16 02:55:31 PM PDT 24
Finished May 16 02:55:38 PM PDT 24
Peak memory 183556 kb
Host smart-d227f5d3-42dc-4256-be4e-193360a13f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267901987 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.1267901987
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.2712065538
Short name T239
Test name
Test status
Simulation time 38327156518 ps
CPU time 5.92 seconds
Started May 16 02:55:30 PM PDT 24
Finished May 16 02:55:42 PM PDT 24
Peak memory 183584 kb
Host smart-b4468409-69f6-4d59-aa92-bec3d495ee62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712065538 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.2712065538
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.4068083098
Short name T14
Test name
Test status
Simulation time 8425930530 ps
CPU time 7.34 seconds
Started May 16 02:55:28 PM PDT 24
Finished May 16 02:55:42 PM PDT 24
Peak memory 215196 kb
Host smart-9e272092-f90f-48d8-90cd-a5bed56c9bf5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068083098 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.4068083098
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.1629974313
Short name T166
Test name
Test status
Simulation time 610108014 ps
CPU time 0.78 seconds
Started May 16 02:55:29 PM PDT 24
Finished May 16 02:55:36 PM PDT 24
Peak memory 183468 kb
Host smart-371838ac-1380-4341-8fa0-e0951b33f5fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629974313 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.1629974313
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.535092793
Short name T87
Test name
Test status
Simulation time 587951390939 ps
CPU time 402.69 seconds
Started May 16 02:55:27 PM PDT 24
Finished May 16 03:02:16 PM PDT 24
Peak memory 198408 kb
Host smart-457e5d36-8c1c-48e0-84b0-062a32510a70
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535092793 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.535092793
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_jump.411560121
Short name T161
Test name
Test status
Simulation time 347394892 ps
CPU time 1.08 seconds
Started May 16 02:56:21 PM PDT 24
Finished May 16 02:56:25 PM PDT 24
Peak memory 183456 kb
Host smart-fe4a6226-2441-405b-b68e-bbf26b7a05d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411560121 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.411560121
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.1350594183
Short name T8
Test name
Test status
Simulation time 50690373393 ps
CPU time 78.72 seconds
Started May 16 02:56:24 PM PDT 24
Finished May 16 02:57:46 PM PDT 24
Peak memory 183560 kb
Host smart-59ee3958-d9c5-4c84-8cae-2ee7a3133b67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350594183 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.1350594183
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.1023138967
Short name T211
Test name
Test status
Simulation time 480068876 ps
CPU time 0.71 seconds
Started May 16 02:56:21 PM PDT 24
Finished May 16 02:56:25 PM PDT 24
Peak memory 183504 kb
Host smart-8ac1c0db-0c45-4060-b1f0-35406c64e41a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023138967 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.1023138967
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.2729052640
Short name T123
Test name
Test status
Simulation time 227718709554 ps
CPU time 331.45 seconds
Started May 16 02:56:20 PM PDT 24
Finished May 16 03:01:55 PM PDT 24
Peak memory 183564 kb
Host smart-647b428a-02b9-424e-8157-eef1a3f61ca5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729052640 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_
all.2729052640
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.2162174099
Short name T79
Test name
Test status
Simulation time 50595898511 ps
CPU time 281.15 seconds
Started May 16 02:56:23 PM PDT 24
Finished May 16 03:01:08 PM PDT 24
Peak memory 198464 kb
Host smart-b66cf02b-548b-4b88-bdba-0c75285acf76
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162174099 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.2162174099
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.aon_timer_jump.2409192957
Short name T30
Test name
Test status
Simulation time 563636061 ps
CPU time 0.74 seconds
Started May 16 02:56:21 PM PDT 24
Finished May 16 02:56:25 PM PDT 24
Peak memory 183496 kb
Host smart-b6273a21-6986-4661-8c2a-4ae9b42040b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409192957 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.2409192957
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.1133672501
Short name T194
Test name
Test status
Simulation time 56200174320 ps
CPU time 83.64 seconds
Started May 16 02:56:18 PM PDT 24
Finished May 16 02:57:44 PM PDT 24
Peak memory 191796 kb
Host smart-db0dc422-2118-4c26-9737-2b469cdfc427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133672501 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.1133672501
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.2307397129
Short name T162
Test name
Test status
Simulation time 561355833 ps
CPU time 0.79 seconds
Started May 16 02:56:19 PM PDT 24
Finished May 16 02:56:22 PM PDT 24
Peak memory 183508 kb
Host smart-97bd4fe6-30df-4b31-8790-1f8ea024ebf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307397129 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.2307397129
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.3697820263
Short name T215
Test name
Test status
Simulation time 84265475688 ps
CPU time 95.78 seconds
Started May 16 02:56:19 PM PDT 24
Finished May 16 02:57:58 PM PDT 24
Peak memory 193772 kb
Host smart-66f43e6e-c6b5-4e09-8d37-0c7c4e39592d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697820263 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_
all.3697820263
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.198309083
Short name T38
Test name
Test status
Simulation time 79541125684 ps
CPU time 437.28 seconds
Started May 16 02:56:19 PM PDT 24
Finished May 16 03:03:38 PM PDT 24
Peak memory 198420 kb
Host smart-c7e78429-a4bd-4afc-b923-1943e3cca834
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198309083 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.198309083
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.aon_timer_jump.30015788
Short name T106
Test name
Test status
Simulation time 365289442 ps
CPU time 0.72 seconds
Started May 16 02:56:21 PM PDT 24
Finished May 16 02:56:24 PM PDT 24
Peak memory 183496 kb
Host smart-c3646738-21a7-4523-b733-e8a18f173b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30015788 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.30015788
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.3447591055
Short name T207
Test name
Test status
Simulation time 9080668225 ps
CPU time 6.96 seconds
Started May 16 02:56:22 PM PDT 24
Finished May 16 02:56:33 PM PDT 24
Peak memory 191812 kb
Host smart-8f4305e3-fd42-4481-85c0-92f6b40a2b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447591055 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.3447591055
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.65365155
Short name T237
Test name
Test status
Simulation time 394980100 ps
CPU time 0.66 seconds
Started May 16 02:56:18 PM PDT 24
Finished May 16 02:56:20 PM PDT 24
Peak memory 183484 kb
Host smart-b8590376-56fa-4a37-b3d2-ad3311d47bd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65365155 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.65365155
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.772935077
Short name T111
Test name
Test status
Simulation time 85954181522 ps
CPU time 144.88 seconds
Started May 16 02:56:19 PM PDT 24
Finished May 16 02:58:47 PM PDT 24
Peak memory 195484 kb
Host smart-b06f7dfd-bbd2-4187-82a6-3f6c41c9d18e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772935077 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_a
ll.772935077
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.311484147
Short name T43
Test name
Test status
Simulation time 1400947155478 ps
CPU time 686.57 seconds
Started May 16 02:56:21 PM PDT 24
Finished May 16 03:07:51 PM PDT 24
Peak memory 200156 kb
Host smart-ee827ada-e2e5-493e-9fb2-1d508d3cfce0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311484147 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_reset.311484147
Directory /workspace/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.aon_timer_jump.3358324031
Short name T137
Test name
Test status
Simulation time 413455150 ps
CPU time 0.7 seconds
Started May 16 02:56:18 PM PDT 24
Finished May 16 02:56:22 PM PDT 24
Peak memory 183548 kb
Host smart-9c943ee1-7867-4f9c-b707-4adb094cb460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358324031 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.3358324031
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.2397669583
Short name T216
Test name
Test status
Simulation time 5305546167 ps
CPU time 9.42 seconds
Started May 16 02:56:20 PM PDT 24
Finished May 16 02:56:32 PM PDT 24
Peak memory 183560 kb
Host smart-ef5d6b30-5eb5-47f2-91fa-62bd140043b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397669583 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.2397669583
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.2500945525
Short name T258
Test name
Test status
Simulation time 546559226 ps
CPU time 0.94 seconds
Started May 16 02:56:19 PM PDT 24
Finished May 16 02:56:23 PM PDT 24
Peak memory 183536 kb
Host smart-af55db52-dcd4-41ce-b463-38e42765c10c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500945525 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.2500945525
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_jump.1496242258
Short name T173
Test name
Test status
Simulation time 539372049 ps
CPU time 1.26 seconds
Started May 16 02:56:19 PM PDT 24
Finished May 16 02:56:23 PM PDT 24
Peak memory 183468 kb
Host smart-bd883ebd-7c4c-487f-8eee-238ba2534470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496242258 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.1496242258
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.3275621018
Short name T158
Test name
Test status
Simulation time 26547049006 ps
CPU time 44.87 seconds
Started May 16 02:56:17 PM PDT 24
Finished May 16 02:57:04 PM PDT 24
Peak memory 191772 kb
Host smart-db917123-d7f2-4d00-abfb-f105b6743a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275621018 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.3275621018
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.1860995485
Short name T103
Test name
Test status
Simulation time 466143718 ps
CPU time 0.85 seconds
Started May 16 02:56:17 PM PDT 24
Finished May 16 02:56:20 PM PDT 24
Peak memory 183536 kb
Host smart-cce2b2fc-85e9-4f46-9a13-07c15322f5c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860995485 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.1860995485
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.1436391047
Short name T145
Test name
Test status
Simulation time 309405945645 ps
CPU time 106.57 seconds
Started May 16 02:56:18 PM PDT 24
Finished May 16 02:58:07 PM PDT 24
Peak memory 183652 kb
Host smart-b8b3b39b-2cc8-4e03-bf58-3bdf08cdea69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436391047 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_
all.1436391047
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/35.aon_timer_jump.830929648
Short name T132
Test name
Test status
Simulation time 554557179 ps
CPU time 0.93 seconds
Started May 16 02:56:19 PM PDT 24
Finished May 16 02:56:22 PM PDT 24
Peak memory 183448 kb
Host smart-5f8f7a71-2db0-43b9-a0be-a580ade475b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830929648 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.830929648
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.1774330305
Short name T256
Test name
Test status
Simulation time 27652875579 ps
CPU time 3.4 seconds
Started May 16 02:56:19 PM PDT 24
Finished May 16 02:56:25 PM PDT 24
Peak memory 183576 kb
Host smart-f5b5babf-59c0-4a92-bf25-fe29f86e5166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774330305 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.1774330305
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.1853455809
Short name T206
Test name
Test status
Simulation time 575765416 ps
CPU time 1.03 seconds
Started May 16 02:56:19 PM PDT 24
Finished May 16 02:56:23 PM PDT 24
Peak memory 183500 kb
Host smart-29afa454-7627-49da-b369-b009e97532a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853455809 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.1853455809
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.780686634
Short name T189
Test name
Test status
Simulation time 13740061994 ps
CPU time 136.82 seconds
Started May 16 02:56:16 PM PDT 24
Finished May 16 02:58:35 PM PDT 24
Peak memory 198460 kb
Host smart-d1f67188-baa9-4653-bb87-3102d80b6745
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780686634 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.780686634
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.aon_timer_jump.1099774911
Short name T269
Test name
Test status
Simulation time 528462185 ps
CPU time 1.35 seconds
Started May 16 02:56:22 PM PDT 24
Finished May 16 02:56:26 PM PDT 24
Peak memory 183544 kb
Host smart-d46bd1d7-4697-4b5f-96ad-389b0693ce30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099774911 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.1099774911
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.2266959951
Short name T105
Test name
Test status
Simulation time 17312117031 ps
CPU time 27.68 seconds
Started May 16 02:56:24 PM PDT 24
Finished May 16 02:56:54 PM PDT 24
Peak memory 183556 kb
Host smart-cb847f64-3953-4510-b43d-1d0b46cd9212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266959951 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.2266959951
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.4121645013
Short name T223
Test name
Test status
Simulation time 386443951 ps
CPU time 0.78 seconds
Started May 16 02:56:20 PM PDT 24
Finished May 16 02:56:24 PM PDT 24
Peak memory 183496 kb
Host smart-bb5fc638-fa41-45f1-a796-be3b331f0131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121645013 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.4121645013
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.3032047735
Short name T53
Test name
Test status
Simulation time 37318102089 ps
CPU time 372.05 seconds
Started May 16 02:56:22 PM PDT 24
Finished May 16 03:02:37 PM PDT 24
Peak memory 198492 kb
Host smart-60e90696-e8d4-47b4-9709-f46b6dbfe4ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032047735 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.3032047735
Directory /workspace/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.aon_timer_jump.3656920181
Short name T218
Test name
Test status
Simulation time 602104675 ps
CPU time 0.73 seconds
Started May 16 02:56:28 PM PDT 24
Finished May 16 02:56:32 PM PDT 24
Peak memory 183512 kb
Host smart-24bd041a-f00d-410c-8cf4-cb486f2f1a1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656920181 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.3656920181
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.3845772077
Short name T153
Test name
Test status
Simulation time 18048607744 ps
CPU time 7.89 seconds
Started May 16 02:56:28 PM PDT 24
Finished May 16 02:56:38 PM PDT 24
Peak memory 183596 kb
Host smart-738a17f6-798a-44d7-b613-919184fd7e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845772077 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.3845772077
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.1699384054
Short name T261
Test name
Test status
Simulation time 380657387 ps
CPU time 0.84 seconds
Started May 16 02:56:31 PM PDT 24
Finished May 16 02:56:34 PM PDT 24
Peak memory 183504 kb
Host smart-d3a9ca9d-10a9-4bd0-9989-c1c6eac0d2fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699384054 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.1699384054
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.1840858081
Short name T9
Test name
Test status
Simulation time 275454912976 ps
CPU time 48.9 seconds
Started May 16 02:56:33 PM PDT 24
Finished May 16 02:57:25 PM PDT 24
Peak memory 183608 kb
Host smart-c58f35af-d2af-4790-b020-d6a708c9d251
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840858081 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_
all.1840858081
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.3912766584
Short name T76
Test name
Test status
Simulation time 28858871175 ps
CPU time 263.75 seconds
Started May 16 02:56:26 PM PDT 24
Finished May 16 03:00:52 PM PDT 24
Peak memory 198468 kb
Host smart-5781c3d7-7b72-49fe-b956-528993169022
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912766584 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.3912766584
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.aon_timer_jump.616502951
Short name T130
Test name
Test status
Simulation time 485440191 ps
CPU time 0.72 seconds
Started May 16 02:56:32 PM PDT 24
Finished May 16 02:56:35 PM PDT 24
Peak memory 183536 kb
Host smart-5d829d12-6acc-423f-83b0-284a0f849f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616502951 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.616502951
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.3080529108
Short name T263
Test name
Test status
Simulation time 14660488553 ps
CPU time 24.24 seconds
Started May 16 02:56:31 PM PDT 24
Finished May 16 02:56:58 PM PDT 24
Peak memory 191764 kb
Host smart-d62c4f48-e88a-416d-9f6c-71f082c9243e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080529108 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.3080529108
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.1044834914
Short name T175
Test name
Test status
Simulation time 477838209 ps
CPU time 0.71 seconds
Started May 16 02:56:25 PM PDT 24
Finished May 16 02:56:28 PM PDT 24
Peak memory 183512 kb
Host smart-a0ef958c-180d-4d7f-bc14-d981f08d9c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044834914 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.1044834914
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.363408410
Short name T5
Test name
Test status
Simulation time 96452178085 ps
CPU time 34.01 seconds
Started May 16 02:56:33 PM PDT 24
Finished May 16 02:57:09 PM PDT 24
Peak memory 183612 kb
Host smart-1db705f9-5c4d-48a3-87d6-1b0d765ad1fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363408410 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_a
ll.363408410
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.3921823923
Short name T248
Test name
Test status
Simulation time 268805030755 ps
CPU time 494.25 seconds
Started May 16 02:56:34 PM PDT 24
Finished May 16 03:04:50 PM PDT 24
Peak memory 198440 kb
Host smart-652365b9-6b39-44ae-9c3c-cbaa0bfd7a8c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921823923 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand_reset.3921823923
Directory /workspace/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.aon_timer_jump.99847271
Short name T170
Test name
Test status
Simulation time 402814819 ps
CPU time 1.2 seconds
Started May 16 02:56:27 PM PDT 24
Finished May 16 02:56:31 PM PDT 24
Peak memory 183504 kb
Host smart-d57642b3-a597-4be1-9226-30fdeb0a48ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99847271 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.99847271
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.3754930580
Short name T259
Test name
Test status
Simulation time 13971575082 ps
CPU time 5.39 seconds
Started May 16 02:56:33 PM PDT 24
Finished May 16 02:56:41 PM PDT 24
Peak memory 183600 kb
Host smart-691ad151-3e09-4fe0-820d-8beb9a367f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754930580 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.3754930580
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.2444252001
Short name T136
Test name
Test status
Simulation time 414337602 ps
CPU time 1.19 seconds
Started May 16 02:56:26 PM PDT 24
Finished May 16 02:56:30 PM PDT 24
Peak memory 183504 kb
Host smart-51ac5b3d-ac18-4fc7-b653-94525212ce88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444252001 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.2444252001
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.1278312699
Short name T121
Test name
Test status
Simulation time 246382650041 ps
CPU time 359.02 seconds
Started May 16 02:56:26 PM PDT 24
Finished May 16 03:02:28 PM PDT 24
Peak memory 193280 kb
Host smart-eaf1964e-2461-4982-bdd2-225711239837
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278312699 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_
all.1278312699
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.1733597700
Short name T42
Test name
Test status
Simulation time 135298257139 ps
CPU time 266.92 seconds
Started May 16 02:56:33 PM PDT 24
Finished May 16 03:01:02 PM PDT 24
Peak memory 198480 kb
Host smart-6140b3c0-8a3f-42c6-9cce-7f4e33253058
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733597700 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.1733597700
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_jump.599459282
Short name T243
Test name
Test status
Simulation time 525905490 ps
CPU time 1.29 seconds
Started May 16 02:55:33 PM PDT 24
Finished May 16 02:55:39 PM PDT 24
Peak memory 183548 kb
Host smart-12151efe-04e4-4244-8801-664aadf89b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599459282 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.599459282
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.807627235
Short name T47
Test name
Test status
Simulation time 19602012874 ps
CPU time 7.67 seconds
Started May 16 02:55:29 PM PDT 24
Finished May 16 02:55:43 PM PDT 24
Peak memory 183620 kb
Host smart-574f35b7-ea35-4964-87c5-3d9a4d18f6ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807627235 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.807627235
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.428527558
Short name T17
Test name
Test status
Simulation time 3880782755 ps
CPU time 2.34 seconds
Started May 16 02:55:30 PM PDT 24
Finished May 16 02:55:39 PM PDT 24
Peak memory 215536 kb
Host smart-a4eae1c3-0abe-4297-a9a5-4f79ab4141bd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428527558 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.428527558
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.1923730220
Short name T18
Test name
Test status
Simulation time 408992928 ps
CPU time 0.75 seconds
Started May 16 02:55:28 PM PDT 24
Finished May 16 02:55:35 PM PDT 24
Peak memory 183512 kb
Host smart-da27b6a1-c26a-431a-9a4a-1788e29cacd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923730220 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.1923730220
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.2373339363
Short name T44
Test name
Test status
Simulation time 143913413977 ps
CPU time 143.83 seconds
Started May 16 02:55:29 PM PDT 24
Finished May 16 02:57:59 PM PDT 24
Peak memory 198456 kb
Host smart-a4ad5cd5-0af5-4e00-bf36-602334f75b08
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373339363 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.2373339363
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.aon_timer_jump.3247748744
Short name T45
Test name
Test status
Simulation time 528907751 ps
CPU time 0.6 seconds
Started May 16 02:56:35 PM PDT 24
Finished May 16 02:56:38 PM PDT 24
Peak memory 183556 kb
Host smart-03d0c55c-d1db-4a13-b326-5f0daa720128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247748744 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.3247748744
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.751462735
Short name T20
Test name
Test status
Simulation time 29097492747 ps
CPU time 24.57 seconds
Started May 16 02:56:27 PM PDT 24
Finished May 16 02:56:54 PM PDT 24
Peak memory 183584 kb
Host smart-406f6066-9850-431a-a71a-ccc454822891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751462735 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.751462735
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.103647734
Short name T240
Test name
Test status
Simulation time 412173794 ps
CPU time 0.67 seconds
Started May 16 02:56:30 PM PDT 24
Finished May 16 02:56:33 PM PDT 24
Peak memory 183504 kb
Host smart-96ce6a9a-5a2c-46dc-b9de-6b7ba43164dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103647734 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.103647734
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.1197725509
Short name T252
Test name
Test status
Simulation time 5032421505 ps
CPU time 9.22 seconds
Started May 16 02:56:36 PM PDT 24
Finished May 16 02:56:48 PM PDT 24
Peak memory 183532 kb
Host smart-05afe488-fae6-4b74-8a9f-0210deaf82c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197725509 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_
all.1197725509
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.1743409333
Short name T19
Test name
Test status
Simulation time 188665279667 ps
CPU time 349.66 seconds
Started May 16 02:56:35 PM PDT 24
Finished May 16 03:02:27 PM PDT 24
Peak memory 198516 kb
Host smart-e19dd586-a4c1-4ee6-81fe-9d6c2773b727
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743409333 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.1743409333
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.aon_timer_jump.2298814434
Short name T201
Test name
Test status
Simulation time 447859817 ps
CPU time 0.76 seconds
Started May 16 02:56:35 PM PDT 24
Finished May 16 02:56:38 PM PDT 24
Peak memory 183484 kb
Host smart-19a24353-f386-4eb6-b662-1a9e1dd9ead8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298814434 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.2298814434
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.275065342
Short name T75
Test name
Test status
Simulation time 43346950983 ps
CPU time 36.67 seconds
Started May 16 02:56:37 PM PDT 24
Finished May 16 02:57:16 PM PDT 24
Peak memory 183492 kb
Host smart-53240f48-96e7-4aa1-8dce-7db653303857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275065342 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.275065342
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.535124976
Short name T157
Test name
Test status
Simulation time 429522552 ps
CPU time 0.86 seconds
Started May 16 02:56:36 PM PDT 24
Finished May 16 02:56:40 PM PDT 24
Peak memory 183520 kb
Host smart-159be3ef-7395-47b2-963a-649e7f6eb832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535124976 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.535124976
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.202501074
Short name T90
Test name
Test status
Simulation time 172300776351 ps
CPU time 50.34 seconds
Started May 16 02:56:35 PM PDT 24
Finished May 16 02:57:28 PM PDT 24
Peak memory 194124 kb
Host smart-841bced9-4a33-4388-bb51-b9318d07541b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202501074 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_a
ll.202501074
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.4058441681
Short name T83
Test name
Test status
Simulation time 319284471485 ps
CPU time 339.96 seconds
Started May 16 02:56:36 PM PDT 24
Finished May 16 03:02:19 PM PDT 24
Peak memory 198492 kb
Host smart-fb462901-3990-4469-9c51-3b785f852a0d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058441681 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.4058441681
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.aon_timer_jump.4205816830
Short name T270
Test name
Test status
Simulation time 444365570 ps
CPU time 0.76 seconds
Started May 16 02:56:36 PM PDT 24
Finished May 16 02:56:39 PM PDT 24
Peak memory 183508 kb
Host smart-96e50553-942d-46df-8b0a-9834921ae2a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205816830 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.4205816830
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.3709776325
Short name T217
Test name
Test status
Simulation time 13411815018 ps
CPU time 18.09 seconds
Started May 16 02:56:38 PM PDT 24
Finished May 16 02:56:58 PM PDT 24
Peak memory 183516 kb
Host smart-a826b86c-1b37-4627-95b4-26d83d909dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709776325 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.3709776325
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.2894474464
Short name T246
Test name
Test status
Simulation time 457504453 ps
CPU time 0.65 seconds
Started May 16 02:56:35 PM PDT 24
Finished May 16 02:56:37 PM PDT 24
Peak memory 183388 kb
Host smart-6fe49a9a-6bf0-4d55-b38f-a3b3df631a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894474464 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.2894474464
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.4272154876
Short name T134
Test name
Test status
Simulation time 204284145613 ps
CPU time 82.26 seconds
Started May 16 02:56:35 PM PDT 24
Finished May 16 02:57:59 PM PDT 24
Peak memory 183620 kb
Host smart-43446947-9834-4c73-928d-d8b90b4762f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272154876 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_
all.4272154876
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.1309753242
Short name T12
Test name
Test status
Simulation time 15174885847 ps
CPU time 145.82 seconds
Started May 16 02:56:37 PM PDT 24
Finished May 16 02:59:05 PM PDT 24
Peak memory 198484 kb
Host smart-5dee4595-6c3e-4aa2-84dc-71e2b08887a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309753242 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.1309753242
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.aon_timer_jump.2304631740
Short name T126
Test name
Test status
Simulation time 353106298 ps
CPU time 1.05 seconds
Started May 16 02:56:37 PM PDT 24
Finished May 16 02:56:40 PM PDT 24
Peak memory 183564 kb
Host smart-d4140573-62f8-499e-891d-1dbb422c0945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304631740 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.2304631740
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.3702647110
Short name T188
Test name
Test status
Simulation time 4716029747 ps
CPU time 4.38 seconds
Started May 16 02:56:39 PM PDT 24
Finished May 16 02:56:45 PM PDT 24
Peak memory 183512 kb
Host smart-476c0154-9536-47db-a8b7-742572ea7ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702647110 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.3702647110
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.75341160
Short name T49
Test name
Test status
Simulation time 674236860 ps
CPU time 0.59 seconds
Started May 16 02:56:36 PM PDT 24
Finished May 16 02:56:39 PM PDT 24
Peak memory 183544 kb
Host smart-f03e9021-a67b-4ac1-b0f7-d568ccbb1c12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75341160 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.75341160
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.1094142028
Short name T142
Test name
Test status
Simulation time 256373117451 ps
CPU time 246.98 seconds
Started May 16 02:56:37 PM PDT 24
Finished May 16 03:00:46 PM PDT 24
Peak memory 183624 kb
Host smart-629d66bc-df59-4df1-a31b-78fbb8276170
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094142028 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_
all.1094142028
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.160484961
Short name T238
Test name
Test status
Simulation time 29517554529 ps
CPU time 240.33 seconds
Started May 16 02:56:36 PM PDT 24
Finished May 16 03:00:38 PM PDT 24
Peak memory 198412 kb
Host smart-f67c34e3-be2d-4194-90f3-3cf86411c3e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160484961 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.160484961
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.aon_timer_jump.3146989282
Short name T225
Test name
Test status
Simulation time 640531736 ps
CPU time 0.78 seconds
Started May 16 02:56:45 PM PDT 24
Finished May 16 02:56:49 PM PDT 24
Peak memory 183496 kb
Host smart-380a7c5d-bd38-4138-a227-622c7259b693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146989282 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.3146989282
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.1605302281
Short name T236
Test name
Test status
Simulation time 3601577165 ps
CPU time 1.91 seconds
Started May 16 02:56:47 PM PDT 24
Finished May 16 02:56:53 PM PDT 24
Peak memory 183576 kb
Host smart-7be9d197-a5e2-4109-b1bb-a07e88f74792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605302281 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.1605302281
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.629702793
Short name T204
Test name
Test status
Simulation time 498258258 ps
CPU time 0.7 seconds
Started May 16 02:56:38 PM PDT 24
Finished May 16 02:56:40 PM PDT 24
Peak memory 183452 kb
Host smart-e7e9d775-d171-4862-856b-ca3ba12462f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629702793 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.629702793
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.3533342491
Short name T149
Test name
Test status
Simulation time 193349806652 ps
CPU time 148 seconds
Started May 16 02:56:48 PM PDT 24
Finished May 16 02:59:20 PM PDT 24
Peak memory 183620 kb
Host smart-35c5ad71-27fb-447c-b305-8add278bebba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533342491 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_
all.3533342491
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.62218981
Short name T245
Test name
Test status
Simulation time 31427943427 ps
CPU time 275.12 seconds
Started May 16 02:56:46 PM PDT 24
Finished May 16 03:01:25 PM PDT 24
Peak memory 198504 kb
Host smart-3b6b40ad-dbb1-472d-88b3-296999141479
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62218981 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.62218981
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.aon_timer_jump.642468368
Short name T155
Test name
Test status
Simulation time 415086047 ps
CPU time 1.2 seconds
Started May 16 02:56:45 PM PDT 24
Finished May 16 02:56:50 PM PDT 24
Peak memory 183532 kb
Host smart-461082f5-2613-4885-a17c-ebeae0a90384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642468368 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.642468368
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.2556408073
Short name T1
Test name
Test status
Simulation time 17652739656 ps
CPU time 27.62 seconds
Started May 16 02:56:44 PM PDT 24
Finished May 16 02:57:14 PM PDT 24
Peak memory 183612 kb
Host smart-89a5fc2a-e2f0-4fff-b74e-8975fb1f3e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556408073 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.2556408073
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.3401524491
Short name T193
Test name
Test status
Simulation time 489989027 ps
CPU time 1.28 seconds
Started May 16 02:56:48 PM PDT 24
Finished May 16 02:56:53 PM PDT 24
Peak memory 183472 kb
Host smart-220b7301-4fc7-4410-bbaa-44c19e95155c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401524491 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.3401524491
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.3068582833
Short name T192
Test name
Test status
Simulation time 66473436973 ps
CPU time 47.54 seconds
Started May 16 02:56:46 PM PDT 24
Finished May 16 02:57:37 PM PDT 24
Peak memory 183744 kb
Host smart-94459d11-b66b-46ff-a758-0d992d4bd89e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068582833 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_
all.3068582833
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.4215853176
Short name T82
Test name
Test status
Simulation time 84731623610 ps
CPU time 343.68 seconds
Started May 16 02:56:47 PM PDT 24
Finished May 16 03:02:35 PM PDT 24
Peak memory 198484 kb
Host smart-21d79b79-d3a5-4251-afc5-2b03dc785507
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215853176 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.4215853176
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.aon_timer_jump.3265776749
Short name T255
Test name
Test status
Simulation time 436189456 ps
CPU time 0.9 seconds
Started May 16 02:56:48 PM PDT 24
Finished May 16 02:56:53 PM PDT 24
Peak memory 183548 kb
Host smart-ef319e4d-f1de-4d8a-8f5e-08d7c068d78c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265776749 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.3265776749
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.3292802495
Short name T260
Test name
Test status
Simulation time 37922894979 ps
CPU time 13.66 seconds
Started May 16 02:56:46 PM PDT 24
Finished May 16 02:57:04 PM PDT 24
Peak memory 183576 kb
Host smart-a8d7254d-4b0f-4a8d-b65f-f5295aaacc4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292802495 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.3292802495
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.2497516660
Short name T139
Test name
Test status
Simulation time 434955467 ps
CPU time 0.67 seconds
Started May 16 02:56:47 PM PDT 24
Finished May 16 02:56:52 PM PDT 24
Peak memory 183492 kb
Host smart-160dc44c-d3c7-4691-83ba-7ecdaa798e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497516660 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.2497516660
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.411562242
Short name T185
Test name
Test status
Simulation time 11834003154 ps
CPU time 9.98 seconds
Started May 16 02:56:48 PM PDT 24
Finished May 16 02:57:02 PM PDT 24
Peak memory 183572 kb
Host smart-8a162a17-7d64-48f2-8279-323a67d7022f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411562242 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_a
ll.411562242
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.305446832
Short name T182
Test name
Test status
Simulation time 504693315625 ps
CPU time 235.56 seconds
Started May 16 02:56:48 PM PDT 24
Finished May 16 03:00:47 PM PDT 24
Peak memory 198484 kb
Host smart-aa0831ed-c45f-454b-847e-1e1b8ba30125
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305446832 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.305446832
Directory /workspace/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.aon_timer_jump.4293020694
Short name T22
Test name
Test status
Simulation time 498462913 ps
CPU time 1.39 seconds
Started May 16 02:56:46 PM PDT 24
Finished May 16 02:56:52 PM PDT 24
Peak memory 183532 kb
Host smart-7918c1f4-1ead-490d-b319-0d327892c09c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293020694 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.4293020694
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.3620445643
Short name T226
Test name
Test status
Simulation time 49902561287 ps
CPU time 37.11 seconds
Started May 16 02:56:46 PM PDT 24
Finished May 16 02:57:26 PM PDT 24
Peak memory 191776 kb
Host smart-93052d70-0dee-41d7-b6e8-147fff921ddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620445643 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.3620445643
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.1913041968
Short name T177
Test name
Test status
Simulation time 551048183 ps
CPU time 0.74 seconds
Started May 16 02:56:48 PM PDT 24
Finished May 16 02:56:52 PM PDT 24
Peak memory 183484 kb
Host smart-31f7227d-a82f-4ddc-a7c6-fc0bd7b6c7b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913041968 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.1913041968
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.2861295684
Short name T202
Test name
Test status
Simulation time 78474276330 ps
CPU time 120.54 seconds
Started May 16 02:56:46 PM PDT 24
Finished May 16 02:58:50 PM PDT 24
Peak memory 195652 kb
Host smart-6bfa05a1-fcdb-4e79-b50a-717b4e7bda74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861295684 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_
all.2861295684
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.3852208083
Short name T227
Test name
Test status
Simulation time 311216305176 ps
CPU time 551.7 seconds
Started May 16 02:56:49 PM PDT 24
Finished May 16 03:06:05 PM PDT 24
Peak memory 199216 kb
Host smart-31601f44-851d-4698-aea6-f471d09ced24
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852208083 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.3852208083
Directory /workspace/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_jump.3597728499
Short name T140
Test name
Test status
Simulation time 508407792 ps
CPU time 0.63 seconds
Started May 16 02:56:57 PM PDT 24
Finished May 16 02:57:03 PM PDT 24
Peak memory 183508 kb
Host smart-eb10b89f-1ead-44f6-b4d4-35417473369e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597728499 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.3597728499
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.4094384340
Short name T21
Test name
Test status
Simulation time 16348037557 ps
CPU time 27.39 seconds
Started May 16 02:56:56 PM PDT 24
Finished May 16 02:57:28 PM PDT 24
Peak memory 191764 kb
Host smart-e76cb0cd-9987-43a2-b686-79c30ab0a137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094384340 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.4094384340
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.1209546884
Short name T27
Test name
Test status
Simulation time 395959853 ps
CPU time 0.66 seconds
Started May 16 02:56:55 PM PDT 24
Finished May 16 02:57:00 PM PDT 24
Peak memory 183496 kb
Host smart-9fa17049-83aa-464d-b508-03114d56a9c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209546884 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.1209546884
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.2741348280
Short name T133
Test name
Test status
Simulation time 209536952326 ps
CPU time 145.01 seconds
Started May 16 02:56:58 PM PDT 24
Finished May 16 02:59:28 PM PDT 24
Peak memory 193752 kb
Host smart-7e6a49d1-d48f-4b04-8f19-f966a669f085
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741348280 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_
all.2741348280
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_jump.2346005455
Short name T104
Test name
Test status
Simulation time 554810086 ps
CPU time 1.54 seconds
Started May 16 02:56:56 PM PDT 24
Finished May 16 02:57:02 PM PDT 24
Peak memory 183476 kb
Host smart-ae2e2bb6-5a60-4bcf-959e-cba91225388f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346005455 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.2346005455
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.2117784760
Short name T184
Test name
Test status
Simulation time 12281030038 ps
CPU time 9.61 seconds
Started May 16 02:56:57 PM PDT 24
Finished May 16 02:57:11 PM PDT 24
Peak memory 191760 kb
Host smart-b14ca729-15a5-43c8-b1b8-680558c15e26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117784760 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.2117784760
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.3763577019
Short name T23
Test name
Test status
Simulation time 511341581 ps
CPU time 0.74 seconds
Started May 16 02:57:00 PM PDT 24
Finished May 16 02:57:06 PM PDT 24
Peak memory 183500 kb
Host smart-de9fa314-f177-4a31-84d3-4f6be9109b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763577019 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.3763577019
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.2235982863
Short name T115
Test name
Test status
Simulation time 130602326538 ps
CPU time 233.91 seconds
Started May 16 02:56:56 PM PDT 24
Finished May 16 03:00:54 PM PDT 24
Peak memory 192964 kb
Host smart-d7e9a808-3c33-4424-8c6a-5431b1538006
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235982863 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_
all.2235982863
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.1437968558
Short name T81
Test name
Test status
Simulation time 159508932988 ps
CPU time 491.5 seconds
Started May 16 02:56:55 PM PDT 24
Finished May 16 03:05:11 PM PDT 24
Peak memory 198476 kb
Host smart-a96a3359-663c-4944-8529-ea23cc5a9e26
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437968558 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.1437968558
Directory /workspace/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.aon_timer_jump.341239967
Short name T102
Test name
Test status
Simulation time 498609105 ps
CPU time 1.23 seconds
Started May 16 02:55:35 PM PDT 24
Finished May 16 02:55:40 PM PDT 24
Peak memory 183524 kb
Host smart-8745c87b-4aa3-47fb-b79c-861d4f1c315c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341239967 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.341239967
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.135806115
Short name T172
Test name
Test status
Simulation time 16978820790 ps
CPU time 24.36 seconds
Started May 16 02:55:29 PM PDT 24
Finished May 16 02:56:00 PM PDT 24
Peak memory 183636 kb
Host smart-158e3c65-b090-4c9d-9a16-442516c29392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135806115 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.135806115
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.2630242091
Short name T51
Test name
Test status
Simulation time 544488149 ps
CPU time 1.39 seconds
Started May 16 02:55:30 PM PDT 24
Finished May 16 02:55:38 PM PDT 24
Peak memory 183504 kb
Host smart-11de06e4-5456-4ea5-95eb-4bd1ba07d73f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630242091 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.2630242091
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.992897066
Short name T28
Test name
Test status
Simulation time 192856762907 ps
CPU time 83.3 seconds
Started May 16 02:55:30 PM PDT 24
Finished May 16 02:56:59 PM PDT 24
Peak memory 195060 kb
Host smart-0f83157e-ba27-456d-8034-a034f27302b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992897066 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_al
l.992897066
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.3547932549
Short name T200
Test name
Test status
Simulation time 419169068456 ps
CPU time 527.6 seconds
Started May 16 02:55:31 PM PDT 24
Finished May 16 03:04:25 PM PDT 24
Peak memory 198640 kb
Host smart-433a3d08-8ca0-423d-8c2f-31f945f519c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547932549 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.3547932549
Directory /workspace/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.aon_timer_jump.458725553
Short name T205
Test name
Test status
Simulation time 417975353 ps
CPU time 0.71 seconds
Started May 16 02:55:31 PM PDT 24
Finished May 16 02:55:38 PM PDT 24
Peak memory 183464 kb
Host smart-090bdd9d-69cf-4cca-92ab-45b3a26d51ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458725553 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.458725553
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.1969092574
Short name T117
Test name
Test status
Simulation time 28297903984 ps
CPU time 20.45 seconds
Started May 16 02:55:28 PM PDT 24
Finished May 16 02:55:55 PM PDT 24
Peak memory 183596 kb
Host smart-8f55b632-9ea8-464c-94ce-228555cb2e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969092574 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.1969092574
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.51369217
Short name T122
Test name
Test status
Simulation time 502134525 ps
CPU time 1.2 seconds
Started May 16 02:55:30 PM PDT 24
Finished May 16 02:55:38 PM PDT 24
Peak memory 183504 kb
Host smart-24a68e67-15e2-4ec7-9078-b3214cb4cd42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51369217 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.51369217
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.3332157396
Short name T272
Test name
Test status
Simulation time 106497613443 ps
CPU time 42.67 seconds
Started May 16 02:55:32 PM PDT 24
Finished May 16 02:56:20 PM PDT 24
Peak memory 194064 kb
Host smart-31732de9-0829-46a3-bae3-a03a15227219
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332157396 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_a
ll.3332157396
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.1048159654
Short name T250
Test name
Test status
Simulation time 251157252737 ps
CPU time 536.46 seconds
Started May 16 02:55:29 PM PDT 24
Finished May 16 03:04:33 PM PDT 24
Peak memory 199144 kb
Host smart-cb90b65f-e0de-4fc4-a60a-0258ac007e47
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048159654 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.1048159654
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.aon_timer_jump.2925953396
Short name T109
Test name
Test status
Simulation time 374830491 ps
CPU time 0.82 seconds
Started May 16 02:55:30 PM PDT 24
Finished May 16 02:55:37 PM PDT 24
Peak memory 183532 kb
Host smart-7a9827e9-930b-4b43-b24a-935bb93f6edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925953396 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.2925953396
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.3435530396
Short name T180
Test name
Test status
Simulation time 37377461787 ps
CPU time 62.42 seconds
Started May 16 02:55:35 PM PDT 24
Finished May 16 02:56:41 PM PDT 24
Peak memory 183576 kb
Host smart-58777484-2ee5-4f93-9735-6eee0569ba6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435530396 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.3435530396
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.752730645
Short name T265
Test name
Test status
Simulation time 586611740 ps
CPU time 0.74 seconds
Started May 16 02:55:28 PM PDT 24
Finished May 16 02:55:36 PM PDT 24
Peak memory 183572 kb
Host smart-6f181115-e4d5-4f08-851c-f7badeefe46e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752730645 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.752730645
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.3984202514
Short name T220
Test name
Test status
Simulation time 120267780019 ps
CPU time 169.24 seconds
Started May 16 02:55:47 PM PDT 24
Finished May 16 02:58:39 PM PDT 24
Peak memory 183604 kb
Host smart-9747feed-b8f1-4b2a-a19f-df3d0ceb6440
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984202514 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_a
ll.3984202514
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.2554220706
Short name T214
Test name
Test status
Simulation time 43384350190 ps
CPU time 453.16 seconds
Started May 16 02:55:30 PM PDT 24
Finished May 16 03:03:10 PM PDT 24
Peak memory 198464 kb
Host smart-d2b45545-8c55-4098-8c9b-44b8eb7bd813
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554220706 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.2554220706
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.aon_timer_jump.4188174388
Short name T159
Test name
Test status
Simulation time 555527543 ps
CPU time 1 seconds
Started May 16 02:55:40 PM PDT 24
Finished May 16 02:55:42 PM PDT 24
Peak memory 183188 kb
Host smart-8892b0c5-2106-4573-98d8-2f7c41e535bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188174388 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.4188174388
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.886446327
Short name T138
Test name
Test status
Simulation time 2912063485 ps
CPU time 1.01 seconds
Started May 16 02:55:43 PM PDT 24
Finished May 16 02:55:46 PM PDT 24
Peak memory 183576 kb
Host smart-dc6bf3f8-fd2f-4e05-a956-a8c2ca028c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886446327 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.886446327
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.3274938348
Short name T196
Test name
Test status
Simulation time 552924005 ps
CPU time 1.28 seconds
Started May 16 02:55:38 PM PDT 24
Finished May 16 02:55:42 PM PDT 24
Peak memory 183508 kb
Host smart-da090468-e7cb-4e41-b5dd-006b3bdd9c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274938348 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.3274938348
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.1091612695
Short name T222
Test name
Test status
Simulation time 193766821934 ps
CPU time 223.23 seconds
Started May 16 02:55:37 PM PDT 24
Finished May 16 02:59:23 PM PDT 24
Peak memory 195428 kb
Host smart-8dc6051d-5e82-4c81-b0a7-5d7e02d40150
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091612695 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_a
ll.1091612695
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_jump.682012385
Short name T169
Test name
Test status
Simulation time 537855123 ps
CPU time 0.7 seconds
Started May 16 02:55:47 PM PDT 24
Finished May 16 02:55:50 PM PDT 24
Peak memory 183540 kb
Host smart-055c742a-31f1-41b4-a62b-d47df41e2ccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682012385 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.682012385
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.226438814
Short name T209
Test name
Test status
Simulation time 7554635372 ps
CPU time 10.22 seconds
Started May 16 02:55:45 PM PDT 24
Finished May 16 02:55:57 PM PDT 24
Peak memory 183608 kb
Host smart-e5b75d2d-55e0-4f21-9e71-afb4c7a76a64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226438814 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.226438814
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.2783538136
Short name T235
Test name
Test status
Simulation time 529659343 ps
CPU time 1.36 seconds
Started May 16 02:55:46 PM PDT 24
Finished May 16 02:55:49 PM PDT 24
Peak memory 183532 kb
Host smart-84a33777-719c-4932-b2e8-b0faa17f5648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783538136 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.2783538136
Directory /workspace/9.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.753357026
Short name T167
Test name
Test status
Simulation time 8171730709 ps
CPU time 5.55 seconds
Started May 16 02:55:49 PM PDT 24
Finished May 16 02:55:58 PM PDT 24
Peak memory 183604 kb
Host smart-19f843ff-c0d6-4aac-a6b9-5455343febe7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753357026 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_al
l.753357026
Directory /workspace/9.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.353931700
Short name T262
Test name
Test status
Simulation time 629560984374 ps
CPU time 386.37 seconds
Started May 16 02:55:48 PM PDT 24
Finished May 16 03:02:17 PM PDT 24
Peak memory 198468 kb
Host smart-dd794965-dc19-4fe5-9c4b-f38dd80bd588
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353931700 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.353931700
Directory /workspace/9.aon_timer_stress_all_with_rand_reset/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%