Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
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Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
24.86 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv


Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 173 130 43 24.86


Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
bark_thold_cp 34 32 2 5.88 100 1 1 0
bite_thold_cp 34 32 2 5.88 100 1 1 0
pause_in_sleep_cp 2 1 1 50.00 100 1 1 2
prescale_cp 34 1 33 97.06 100 1 1 0
wdog_regwen_cp 2 0 2 100.00 100 1 1 2
wkup_cause_cp 1 0 1 100.00 100 1 1 0
wkup_thold_cp 66 64 2 3.03 100 1 1 0


Summary for Variable bark_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 32 2 5.88


User Defined Bins for bark_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
bark_max 0 1 1
bark[1] 0 1 1
bark[2] 0 1 1
bark[3] 0 1 1
bark[4] 0 1 1
bark[5] 0 1 1
bark[6] 0 1 1
bark[7] 0 1 1
bark[8] 0 1 1
bark[9] 0 1 1
bark[10] 0 1 1
bark[11] 0 1 1
bark[12] 0 1 1
bark[13] 0 1 1
bark[14] 0 1 1
bark[15] 0 1 1
bark[16] 0 1 1
bark[17] 0 1 1
bark[18] 0 1 1
bark[19] 0 1 1
bark[20] 0 1 1
bark[21] 0 1 1
bark[22] 0 1 1
bark[23] 0 1 1
bark[24] 0 1 1
bark[25] 0 1 1
bark[26] 0 1 1
bark[27] 0 1 1
bark[28] 0 1 1
bark[29] 0 1 1
bark[30] 0 1 1
bark[31] 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
bark[0] 46307 1 T1 11 T2 11 T3 627
bark_0 4471 1 T1 7 T2 7 T3 33


Summary for Variable bite_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 32 2 5.88


User Defined Bins for bite_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
bite_max 0 1 1
bite[1] 0 1 1
bite[2] 0 1 1
bite[3] 0 1 1
bite[4] 0 1 1
bite[5] 0 1 1
bite[6] 0 1 1
bite[7] 0 1 1
bite[8] 0 1 1
bite[9] 0 1 1
bite[10] 0 1 1
bite[11] 0 1 1
bite[12] 0 1 1
bite[13] 0 1 1
bite[14] 0 1 1
bite[15] 0 1 1
bite[16] 0 1 1
bite[17] 0 1 1
bite[18] 0 1 1
bite[19] 0 1 1
bite[20] 0 1 1
bite[21] 0 1 1
bite[22] 0 1 1
bite[23] 0 1 1
bite[24] 0 1 1
bite[25] 0 1 1
bite[26] 0 1 1
bite[27] 0 1 1
bite[28] 0 1 1
bite[29] 0 1 1
bite[30] 0 1 1
bite[31] 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
bite[0] 45857 1 T1 10 T2 10 T3 623
bite_0 4921 1 T1 8 T2 8 T3 37


Summary for Variable pause_in_sleep_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for pause_in_sleep_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 50778 1 T1 18 T2 18 T3 660


Summary for Variable prescale_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for prescale_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
prescale_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
prescale[0] 882 1 T3 2 T12 72 T34 40
prescale[1] 1005 1 T12 2 T34 69 T41 19
prescale[2] 908 1 T3 63 T39 19 T98 211
prescale[3] 773 1 T35 23 T115 24 T116 30
prescale[4] 576 1 T3 69 T16 50 T39 19
prescale[5] 1094 1 T3 73 T117 9 T41 19
prescale[6] 781 1 T34 76 T16 37 T40 115
prescale[7] 866 1 T30 192 T34 108 T98 44
prescale[8] 1243 1 T9 24 T30 61 T34 19
prescale[9] 959 1 T11 2 T39 249 T115 19
prescale[10] 535 1 T8 9 T12 20 T39 19
prescale[11] 977 1 T3 100 T5 18 T11 21
prescale[12] 643 1 T7 9 T11 55 T12 2
prescale[13] 647 1 T41 48 T42 18 T43 72
prescale[14] 464 1 T12 2 T39 14 T35 19
prescale[15] 1353 1 T39 29 T41 241 T118 88
prescale[16] 1041 1 T12 37 T34 90 T40 76
prescale[17] 843 1 T12 2 T44 9 T30 2
prescale[18] 537 1 T9 23 T11 64 T34 20
prescale[19] 445 1 T9 24 T113 9 T115 19
prescale[20] 702 1 T39 19 T118 23 T23 60
prescale[21] 459 1 T9 19 T11 19 T34 2
prescale[22] 829 1 T12 2 T41 99 T119 40
prescale[23] 611 1 T3 87 T12 2 T39 19
prescale[24] 876 1 T40 46 T35 23 T120 9
prescale[25] 591 1 T11 2 T39 19 T121 28
prescale[26] 980 1 T9 9 T34 19 T39 121
prescale[27] 825 1 T5 19 T34 2 T39 19
prescale[28] 871 1 T5 41 T34 86 T122 9
prescale[29] 670 1 T46 9 T40 2 T123 49
prescale[30] 958 1 T3 179 T5 49 T11 137
prescale[31] 1142 1 T16 44 T42 19 T24 9
prescale_0 24692 1 T1 18 T2 18 T3 87


Summary for Variable wdog_regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for wdog_regwen_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 37973 1 T1 9 T2 18 T3 583
auto[1] 12805 1 T1 9 T3 77 T5 18


Summary for Variable wkup_cause_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for wkup_cause_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
wkup_cause_cleared 50778 1 T1 18 T2 18 T3 660


Summary for Variable wkup_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 66 64 2 3.03


User Defined Bins for wkup_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
wkup_max 0 1 1
wkup[1] 0 1 1
wkup[2] 0 1 1
wkup[3] 0 1 1
wkup[4] 0 1 1
wkup[5] 0 1 1
wkup[6] 0 1 1
wkup[7] 0 1 1
wkup[8] 0 1 1
wkup[9] 0 1 1
wkup[10] 0 1 1
wkup[11] 0 1 1
wkup[12] 0 1 1
wkup[13] 0 1 1
wkup[14] 0 1 1
wkup[15] 0 1 1
wkup[16] 0 1 1
wkup[17] 0 1 1
wkup[18] 0 1 1
wkup[19] 0 1 1
wkup[20] 0 1 1
wkup[21] 0 1 1
wkup[22] 0 1 1
wkup[23] 0 1 1
wkup[24] 0 1 1
wkup[25] 0 1 1
wkup[26] 0 1 1
wkup[27] 0 1 1
wkup[28] 0 1 1
wkup[29] 0 1 1
wkup[30] 0 1 1
wkup[31] 0 1 1
wkup[32] 0 1 1
wkup[33] 0 1 1
wkup[34] 0 1 1
wkup[35] 0 1 1
wkup[36] 0 1 1
wkup[37] 0 1 1
wkup[38] 0 1 1
wkup[39] 0 1 1
wkup[40] 0 1 1
wkup[41] 0 1 1
wkup[42] 0 1 1
wkup[43] 0 1 1
wkup[44] 0 1 1
wkup[45] 0 1 1
wkup[46] 0 1 1
wkup[47] 0 1 1
wkup[48] 0 1 1
wkup[49] 0 1 1
wkup[50] 0 1 1
wkup[51] 0 1 1
wkup[52] 0 1 1
wkup[53] 0 1 1
wkup[54] 0 1 1
wkup[55] 0 1 1
wkup[56] 0 1 1
wkup[57] 0 1 1
wkup[58] 0 1 1
wkup[59] 0 1 1
wkup[60] 0 1 1
wkup[61] 0 1 1
wkup[62] 0 1 1
wkup[63] 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
wkup[0] 47242 1 T1 13 T2 13 T3 635
wkup_0 3536 1 T1 5 T2 5 T3 25

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