Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
92.98 99.25 93.67 100.00 98.40 99.51 67.06


Total test records in report: 418
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html
T37 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.1172989998 May 19 12:39:10 PM PDT 24 May 19 12:39:17 PM PDT 24 8591454388 ps
T130 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.1886023865 May 19 12:38:55 PM PDT 24 May 19 12:38:58 PM PDT 24 353171704 ps
T132 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.2113893089 May 19 12:38:25 PM PDT 24 May 19 12:38:36 PM PDT 24 7494036370 ps
T285 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.1500899432 May 19 12:38:57 PM PDT 24 May 19 12:38:59 PM PDT 24 533393804 ps
T286 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.2100040269 May 19 12:38:45 PM PDT 24 May 19 12:38:50 PM PDT 24 7094782755 ps
T287 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.1065533767 May 19 12:38:54 PM PDT 24 May 19 12:38:56 PM PDT 24 505295153 ps
T131 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.2495947758 May 19 12:38:40 PM PDT 24 May 19 12:38:42 PM PDT 24 344886309 ps
T288 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.2746328554 May 19 12:38:47 PM PDT 24 May 19 12:38:50 PM PDT 24 399932300 ps
T289 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.2717134735 May 19 12:39:23 PM PDT 24 May 19 12:39:26 PM PDT 24 565747389 ps
T63 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.1846910627 May 19 12:38:18 PM PDT 24 May 19 12:38:19 PM PDT 24 520623703 ps
T290 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.1204617953 May 19 12:38:54 PM PDT 24 May 19 12:38:57 PM PDT 24 451017222 ps
T291 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.714461120 May 19 12:38:22 PM PDT 24 May 19 12:38:28 PM PDT 24 474972100 ps
T88 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.1263240934 May 19 12:39:04 PM PDT 24 May 19 12:39:09 PM PDT 24 1588572680 ps
T292 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.3478303668 May 19 12:38:19 PM PDT 24 May 19 12:38:21 PM PDT 24 378600099 ps
T293 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.3812981994 May 19 12:38:55 PM PDT 24 May 19 12:38:57 PM PDT 24 457867045 ps
T89 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.2861506763 May 19 12:38:24 PM PDT 24 May 19 12:38:26 PM PDT 24 948893590 ps
T294 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.3605478733 May 19 12:39:05 PM PDT 24 May 19 12:39:08 PM PDT 24 407467126 ps
T295 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.1487503588 May 19 12:39:12 PM PDT 24 May 19 12:39:13 PM PDT 24 722481631 ps
T296 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.1952522974 May 19 12:38:52 PM PDT 24 May 19 12:38:55 PM PDT 24 403772833 ps
T90 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.2946672478 May 19 12:38:52 PM PDT 24 May 19 12:38:56 PM PDT 24 1770783738 ps
T38 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.2219780090 May 19 12:39:06 PM PDT 24 May 19 12:39:12 PM PDT 24 4660786105 ps
T297 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.1807920874 May 19 12:39:01 PM PDT 24 May 19 12:39:04 PM PDT 24 468957292 ps
T298 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.3876200903 May 19 12:39:05 PM PDT 24 May 19 12:39:07 PM PDT 24 346532293 ps
T299 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.3771033618 May 19 12:38:55 PM PDT 24 May 19 12:38:58 PM PDT 24 472496009 ps
T300 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.458608656 May 19 12:38:57 PM PDT 24 May 19 12:39:00 PM PDT 24 412749519 ps
T301 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.899211743 May 19 12:39:30 PM PDT 24 May 19 12:39:31 PM PDT 24 407210743 ps
T302 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.1922816824 May 19 12:38:50 PM PDT 24 May 19 12:38:53 PM PDT 24 558228898 ps
T303 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.629929739 May 19 12:38:45 PM PDT 24 May 19 12:38:47 PM PDT 24 361146878 ps
T304 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.3951675565 May 19 12:39:04 PM PDT 24 May 19 12:39:06 PM PDT 24 308877675 ps
T305 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.14810270 May 19 12:38:55 PM PDT 24 May 19 12:38:58 PM PDT 24 615800302 ps
T306 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.3402639852 May 19 12:38:24 PM PDT 24 May 19 12:38:26 PM PDT 24 321174137 ps
T307 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.4131037372 May 19 12:39:01 PM PDT 24 May 19 12:39:05 PM PDT 24 615369022 ps
T126 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.809885170 May 19 12:39:01 PM PDT 24 May 19 12:39:17 PM PDT 24 8717440335 ps
T91 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.2785021741 May 19 12:39:01 PM PDT 24 May 19 12:39:08 PM PDT 24 2185266581 ps
T308 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.2939916914 May 19 12:38:59 PM PDT 24 May 19 12:39:02 PM PDT 24 383893255 ps
T309 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.3563363792 May 19 12:38:59 PM PDT 24 May 19 12:39:01 PM PDT 24 266729897 ps
T310 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.892179543 May 19 12:39:06 PM PDT 24 May 19 12:39:08 PM PDT 24 421722427 ps
T127 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.1997168248 May 19 12:38:55 PM PDT 24 May 19 12:39:04 PM PDT 24 4506148546 ps
T311 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.1795741655 May 19 12:39:02 PM PDT 24 May 19 12:39:05 PM PDT 24 319777151 ps
T312 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.3071972798 May 19 12:39:07 PM PDT 24 May 19 12:39:09 PM PDT 24 398919413 ps
T313 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.732098183 May 19 12:38:49 PM PDT 24 May 19 12:38:51 PM PDT 24 733368823 ps
T314 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.1444920016 May 19 12:39:25 PM PDT 24 May 19 12:39:26 PM PDT 24 455891685 ps
T315 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.3393476927 May 19 12:39:10 PM PDT 24 May 19 12:39:11 PM PDT 24 300107720 ps
T316 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.397425466 May 19 12:39:01 PM PDT 24 May 19 12:39:03 PM PDT 24 473553757 ps
T317 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.1113032585 May 19 12:38:50 PM PDT 24 May 19 12:38:51 PM PDT 24 311235662 ps
T318 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.1845276261 May 19 12:39:08 PM PDT 24 May 19 12:39:10 PM PDT 24 517378205 ps
T92 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.514488415 May 19 12:38:57 PM PDT 24 May 19 12:38:59 PM PDT 24 2090111865 ps
T64 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.4103142681 May 19 12:39:00 PM PDT 24 May 19 12:39:03 PM PDT 24 544211649 ps
T319 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.971944004 May 19 12:38:17 PM PDT 24 May 19 12:38:19 PM PDT 24 890408020 ps
T320 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.1070692552 May 19 12:39:08 PM PDT 24 May 19 12:39:10 PM PDT 24 300357409 ps
T93 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.1970385220 May 19 12:38:52 PM PDT 24 May 19 12:38:54 PM PDT 24 396872822 ps
T94 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.2642952386 May 19 12:38:54 PM PDT 24 May 19 12:38:59 PM PDT 24 2957569570 ps
T321 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.1512240742 May 19 12:38:21 PM PDT 24 May 19 12:38:23 PM PDT 24 321984831 ps
T65 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.2781669086 May 19 12:38:36 PM PDT 24 May 19 12:38:38 PM PDT 24 1094218933 ps
T322 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.57750073 May 19 12:39:23 PM PDT 24 May 19 12:39:25 PM PDT 24 396113765 ps
T323 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.3705020551 May 19 12:38:46 PM PDT 24 May 19 12:38:48 PM PDT 24 442912085 ps
T324 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.3550403089 May 19 12:39:08 PM PDT 24 May 19 12:39:10 PM PDT 24 480406786 ps
T325 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.1803291863 May 19 12:39:11 PM PDT 24 May 19 12:39:13 PM PDT 24 478833571 ps
T326 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.774039255 May 19 12:39:03 PM PDT 24 May 19 12:39:05 PM PDT 24 448064372 ps
T66 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.1766570500 May 19 12:38:26 PM PDT 24 May 19 12:38:28 PM PDT 24 401429562 ps
T327 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.2226466574 May 19 12:38:45 PM PDT 24 May 19 12:38:50 PM PDT 24 2500917316 ps
T328 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.3583992373 May 19 12:39:06 PM PDT 24 May 19 12:39:13 PM PDT 24 7809257676 ps
T329 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.2170127165 May 19 12:38:58 PM PDT 24 May 19 12:39:00 PM PDT 24 489699307 ps
T330 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.628747071 May 19 12:38:54 PM PDT 24 May 19 12:39:03 PM PDT 24 4233335027 ps
T331 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.879257095 May 19 12:38:55 PM PDT 24 May 19 12:38:57 PM PDT 24 353971839 ps
T67 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.402228622 May 19 12:39:05 PM PDT 24 May 19 12:39:07 PM PDT 24 450176982 ps
T332 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.410062061 May 19 12:38:40 PM PDT 24 May 19 12:38:43 PM PDT 24 357333627 ps
T333 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.2826161965 May 19 12:38:51 PM PDT 24 May 19 12:38:53 PM PDT 24 577012015 ps
T334 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.165920088 May 19 12:39:02 PM PDT 24 May 19 12:39:05 PM PDT 24 478272220 ps
T128 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.2161723213 May 19 12:39:01 PM PDT 24 May 19 12:39:11 PM PDT 24 7835850220 ps
T335 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.2099566414 May 19 12:38:50 PM PDT 24 May 19 12:38:52 PM PDT 24 572550966 ps
T124 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.2069191783 May 19 12:38:51 PM PDT 24 May 19 12:38:57 PM PDT 24 4683311342 ps
T336 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.4260790256 May 19 12:39:07 PM PDT 24 May 19 12:39:14 PM PDT 24 466930283 ps
T337 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.4247124624 May 19 12:38:52 PM PDT 24 May 19 12:38:54 PM PDT 24 514650902 ps
T68 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.95712109 May 19 12:38:52 PM PDT 24 May 19 12:38:54 PM PDT 24 469673758 ps
T129 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.1248939000 May 19 12:38:28 PM PDT 24 May 19 12:38:42 PM PDT 24 8566263502 ps
T338 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.3476949788 May 19 12:38:44 PM PDT 24 May 19 12:38:48 PM PDT 24 496871063 ps
T339 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.3068355283 May 19 12:39:07 PM PDT 24 May 19 12:39:09 PM PDT 24 499731089 ps
T340 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.1383760897 May 19 12:38:48 PM PDT 24 May 19 12:38:50 PM PDT 24 330780000 ps
T341 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.1385243028 May 19 12:38:55 PM PDT 24 May 19 12:38:57 PM PDT 24 442004701 ps
T342 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.584285333 May 19 12:38:45 PM PDT 24 May 19 12:38:47 PM PDT 24 2399008310 ps
T343 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.593587639 May 19 12:38:53 PM PDT 24 May 19 12:39:08 PM PDT 24 8233870650 ps
T344 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.2863571517 May 19 12:38:55 PM PDT 24 May 19 12:38:57 PM PDT 24 534115579 ps
T345 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.2594440365 May 19 12:39:00 PM PDT 24 May 19 12:39:05 PM PDT 24 4370921692 ps
T346 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.3555318067 May 19 12:39:03 PM PDT 24 May 19 12:39:05 PM PDT 24 323326898 ps
T347 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.1169543692 May 19 12:38:58 PM PDT 24 May 19 12:39:00 PM PDT 24 442580159 ps
T69 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.2409587611 May 19 12:38:35 PM PDT 24 May 19 12:38:37 PM PDT 24 1074470517 ps
T71 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.54819677 May 19 12:39:07 PM PDT 24 May 19 12:39:09 PM PDT 24 547353074 ps
T348 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.3292976606 May 19 12:38:53 PM PDT 24 May 19 12:38:56 PM PDT 24 354252451 ps
T349 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.138502225 May 19 12:38:55 PM PDT 24 May 19 12:38:58 PM PDT 24 388161899 ps
T350 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.346006875 May 19 12:39:03 PM PDT 24 May 19 12:39:05 PM PDT 24 1326946288 ps
T351 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.234086680 May 19 12:38:57 PM PDT 24 May 19 12:39:00 PM PDT 24 481933970 ps
T352 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.3711815409 May 19 12:38:49 PM PDT 24 May 19 12:38:52 PM PDT 24 436158540 ps
T125 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.490953468 May 19 12:38:56 PM PDT 24 May 19 12:39:00 PM PDT 24 4574301435 ps
T72 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.3817325580 May 19 12:39:15 PM PDT 24 May 19 12:39:17 PM PDT 24 488745956 ps
T353 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.1786246902 May 19 12:39:04 PM PDT 24 May 19 12:39:07 PM PDT 24 409215845 ps
T354 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.1805466443 May 19 12:38:25 PM PDT 24 May 19 12:38:26 PM PDT 24 375913951 ps
T355 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.2587001173 May 19 12:39:02 PM PDT 24 May 19 12:39:05 PM PDT 24 585878855 ps
T356 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.4276611135 May 19 12:39:00 PM PDT 24 May 19 12:39:03 PM PDT 24 380934716 ps
T73 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.3452369924 May 19 12:38:20 PM PDT 24 May 19 12:38:21 PM PDT 24 683362231 ps
T357 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.3751658492 May 19 12:38:45 PM PDT 24 May 19 12:38:48 PM PDT 24 693340230 ps
T358 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.3483690502 May 19 12:39:05 PM PDT 24 May 19 12:39:07 PM PDT 24 554910248 ps
T359 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.2072493372 May 19 12:38:38 PM PDT 24 May 19 12:38:40 PM PDT 24 432818535 ps
T360 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.2387887085 May 19 12:39:01 PM PDT 24 May 19 12:39:06 PM PDT 24 2336581583 ps
T361 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.2810931819 May 19 12:38:47 PM PDT 24 May 19 12:39:01 PM PDT 24 8056274141 ps
T362 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.3351744892 May 19 12:38:44 PM PDT 24 May 19 12:38:46 PM PDT 24 338256129 ps
T363 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.2040353266 May 19 12:38:52 PM PDT 24 May 19 12:38:54 PM PDT 24 348655810 ps
T87 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.1790729020 May 19 12:39:01 PM PDT 24 May 19 12:39:08 PM PDT 24 339029761 ps
T364 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.2205606120 May 19 12:38:57 PM PDT 24 May 19 12:39:05 PM PDT 24 2052230190 ps
T365 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.1131864806 May 19 12:38:35 PM PDT 24 May 19 12:38:36 PM PDT 24 435420966 ps
T366 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.4137456405 May 19 12:39:03 PM PDT 24 May 19 12:39:07 PM PDT 24 448402748 ps
T367 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.2699476274 May 19 12:39:06 PM PDT 24 May 19 12:39:09 PM PDT 24 338534910 ps
T368 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.3638516131 May 19 12:38:54 PM PDT 24 May 19 12:38:58 PM PDT 24 529632458 ps
T369 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.4016123221 May 19 12:38:56 PM PDT 24 May 19 12:38:58 PM PDT 24 608072120 ps
T370 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.2903907371 May 19 12:38:57 PM PDT 24 May 19 12:39:00 PM PDT 24 391067168 ps
T371 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.2658617389 May 19 12:38:32 PM PDT 24 May 19 12:38:34 PM PDT 24 756225895 ps
T372 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.2585631308 May 19 12:38:49 PM PDT 24 May 19 12:38:52 PM PDT 24 418359632 ps
T373 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.1310773995 May 19 12:39:01 PM PDT 24 May 19 12:39:04 PM PDT 24 627705029 ps
T70 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.1332045080 May 19 12:38:24 PM PDT 24 May 19 12:38:30 PM PDT 24 356808781 ps
T374 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.577714996 May 19 12:39:16 PM PDT 24 May 19 12:39:17 PM PDT 24 381631945 ps
T375 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.2076553857 May 19 12:38:48 PM PDT 24 May 19 12:38:51 PM PDT 24 1278799064 ps
T376 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.741520891 May 19 12:38:28 PM PDT 24 May 19 12:38:31 PM PDT 24 552260150 ps
T377 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.2971845233 May 19 12:39:02 PM PDT 24 May 19 12:39:05 PM PDT 24 341450375 ps
T378 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.3259540059 May 19 12:39:07 PM PDT 24 May 19 12:39:10 PM PDT 24 1429016712 ps
T74 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.4256386379 May 19 12:38:46 PM PDT 24 May 19 12:38:48 PM PDT 24 672473819 ps
T75 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.21036649 May 19 12:38:52 PM PDT 24 May 19 12:39:10 PM PDT 24 12333596343 ps
T379 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.927396893 May 19 12:39:01 PM PDT 24 May 19 12:39:04 PM PDT 24 457016156 ps
T380 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.78191453 May 19 12:38:54 PM PDT 24 May 19 12:39:02 PM PDT 24 4232692935 ps
T381 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.3735160793 May 19 12:38:50 PM PDT 24 May 19 12:38:52 PM PDT 24 293181554 ps
T382 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.3438444833 May 19 12:38:57 PM PDT 24 May 19 12:38:59 PM PDT 24 458752289 ps
T383 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.1313372595 May 19 12:39:10 PM PDT 24 May 19 12:39:12 PM PDT 24 459207920 ps
T384 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.3258607894 May 19 12:39:23 PM PDT 24 May 19 12:39:25 PM PDT 24 652700076 ps
T385 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.164816534 May 19 12:39:01 PM PDT 24 May 19 12:39:04 PM PDT 24 390511458 ps
T386 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.2659628877 May 19 12:39:00 PM PDT 24 May 19 12:39:03 PM PDT 24 503992580 ps
T387 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.1237989733 May 19 12:38:23 PM PDT 24 May 19 12:38:25 PM PDT 24 282888419 ps
T388 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.2873117957 May 19 12:38:48 PM PDT 24 May 19 12:38:51 PM PDT 24 439314116 ps
T389 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.3926698070 May 19 12:39:02 PM PDT 24 May 19 12:39:11 PM PDT 24 4381429043 ps
T390 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.2089931035 May 19 12:38:52 PM PDT 24 May 19 12:38:54 PM PDT 24 378061821 ps
T391 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.4139500320 May 19 12:39:03 PM PDT 24 May 19 12:39:07 PM PDT 24 433620797 ps
T392 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.390631330 May 19 12:39:00 PM PDT 24 May 19 12:39:03 PM PDT 24 401191892 ps
T393 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.274900628 May 19 12:39:06 PM PDT 24 May 19 12:39:08 PM PDT 24 304123915 ps
T394 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.2204664317 May 19 12:38:33 PM PDT 24 May 19 12:38:34 PM PDT 24 565371153 ps
T395 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.2731345158 May 19 12:38:52 PM PDT 24 May 19 12:38:58 PM PDT 24 8624143944 ps
T396 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.1056027019 May 19 12:38:46 PM PDT 24 May 19 12:38:49 PM PDT 24 561902650 ps
T397 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.2203383744 May 19 12:38:50 PM PDT 24 May 19 12:38:53 PM PDT 24 2204555045 ps
T398 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.2032561875 May 19 12:39:05 PM PDT 24 May 19 12:39:07 PM PDT 24 500833457 ps
T399 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.1625902591 May 19 12:38:19 PM PDT 24 May 19 12:38:20 PM PDT 24 511536066 ps
T400 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.1064522630 May 19 12:39:08 PM PDT 24 May 19 12:39:10 PM PDT 24 377798546 ps
T76 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.426471704 May 19 12:38:44 PM PDT 24 May 19 12:38:46 PM PDT 24 465335700 ps
T401 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.3041944490 May 19 12:38:54 PM PDT 24 May 19 12:38:55 PM PDT 24 377316197 ps
T402 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.2778282591 May 19 12:39:08 PM PDT 24 May 19 12:39:10 PM PDT 24 342378713 ps
T403 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.1349101803 May 19 12:38:58 PM PDT 24 May 19 12:39:03 PM PDT 24 1122198963 ps
T404 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.1261319779 May 19 12:38:48 PM PDT 24 May 19 12:38:50 PM PDT 24 441024103 ps
T405 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.3695417732 May 19 12:38:58 PM PDT 24 May 19 12:39:03 PM PDT 24 1306940549 ps
T406 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.3203514467 May 19 12:38:56 PM PDT 24 May 19 12:39:02 PM PDT 24 8913218919 ps
T407 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.3294916490 May 19 12:39:19 PM PDT 24 May 19 12:39:20 PM PDT 24 292527902 ps
T408 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.2570455026 May 19 12:38:26 PM PDT 24 May 19 12:38:28 PM PDT 24 1305008044 ps
T409 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.2241792983 May 19 12:38:58 PM PDT 24 May 19 12:39:00 PM PDT 24 2265391570 ps
T410 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.2106032314 May 19 12:38:20 PM PDT 24 May 19 12:38:22 PM PDT 24 4565795140 ps
T411 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.610781465 May 19 12:38:21 PM PDT 24 May 19 12:38:24 PM PDT 24 477337123 ps
T412 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.786986729 May 19 12:38:26 PM PDT 24 May 19 12:38:28 PM PDT 24 366016584 ps
T413 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.2892691529 May 19 12:39:12 PM PDT 24 May 19 12:39:14 PM PDT 24 525088107 ps
T414 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.2566361042 May 19 12:38:56 PM PDT 24 May 19 12:39:01 PM PDT 24 1172920430 ps
T415 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.1067419631 May 19 12:38:25 PM PDT 24 May 19 12:38:34 PM PDT 24 7032329635 ps
T416 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.367500445 May 19 12:38:46 PM PDT 24 May 19 12:38:48 PM PDT 24 474175317 ps
T417 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.3823885609 May 19 12:38:54 PM PDT 24 May 19 12:38:57 PM PDT 24 1055898953 ps
T418 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.3668293563 May 19 12:38:23 PM PDT 24 May 19 12:38:28 PM PDT 24 4334027274 ps
T77 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.1563923683 May 19 12:38:59 PM PDT 24 May 19 12:39:01 PM PDT 24 355128431 ps

Test location /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.152221611
Short name T3
Test name
Test status
Simulation time 143353294558 ps
CPU time 189.07 seconds
Started May 19 01:28:56 PM PDT 24
Finished May 19 01:32:11 PM PDT 24
Peak memory 198500 kb
Host smart-bed137d7-b8a5-4646-ab1c-82b11714d0f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152221611 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand_reset.152221611
Directory /workspace/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.2400764722
Short name T16
Test name
Test status
Simulation time 19149916633 ps
CPU time 3.72 seconds
Started May 19 01:29:14 PM PDT 24
Finished May 19 01:29:19 PM PDT 24
Peak memory 183572 kb
Host smart-498c73f6-7006-4ee8-81a6-e8839ab0aebe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400764722 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_
all.2400764722
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.1886785608
Short name T31
Test name
Test status
Simulation time 8812181959 ps
CPU time 13.53 seconds
Started May 19 12:38:24 PM PDT 24
Finished May 19 12:38:38 PM PDT 24
Peak memory 197792 kb
Host smart-fe96cd68-9601-4fcf-ae5d-9e8906f3cf27
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886785608 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl
_intg_err.1886785608
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.1942181617
Short name T39
Test name
Test status
Simulation time 56538742405 ps
CPU time 107.59 seconds
Started May 19 01:28:59 PM PDT 24
Finished May 19 01:30:54 PM PDT 24
Peak memory 198472 kb
Host smart-d5a1cd43-7342-46bb-a88e-6d6e63d168fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942181617 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.1942181617
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.3022660177
Short name T9
Test name
Test status
Simulation time 168078940144 ps
CPU time 72.76 seconds
Started May 19 01:29:00 PM PDT 24
Finished May 19 01:30:19 PM PDT 24
Peak memory 183564 kb
Host smart-7af662cd-2153-4d88-b268-63a100b617a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022660177 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_
all.3022660177
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.1668360222
Short name T41
Test name
Test status
Simulation time 129589566141 ps
CPU time 729.36 seconds
Started May 19 01:28:49 PM PDT 24
Finished May 19 01:41:03 PM PDT 24
Peak memory 201844 kb
Host smart-35ee78dc-2495-4831-b7b6-94c16ae28f2b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668360222 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.1668360222
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.1846910627
Short name T63
Test name
Test status
Simulation time 520623703 ps
CPU time 0.75 seconds
Started May 19 12:38:18 PM PDT 24
Finished May 19 12:38:19 PM PDT 24
Peak memory 193028 kb
Host smart-9772955f-2084-4f7d-a76b-f8dca56815e8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846910627 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.1846910627
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.159222569
Short name T15
Test name
Test status
Simulation time 4290743964 ps
CPU time 4.45 seconds
Started May 19 01:28:45 PM PDT 24
Finished May 19 01:28:52 PM PDT 24
Peak memory 214732 kb
Host smart-da075fa4-7d08-413b-805a-d32b99ca3246
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159222569 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.159222569
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.2459227647
Short name T60
Test name
Test status
Simulation time 506208318388 ps
CPU time 725.29 seconds
Started May 19 01:28:55 PM PDT 24
Finished May 19 01:41:06 PM PDT 24
Peak memory 201592 kb
Host smart-a8069e66-1765-4ff9-8e78-b22dc28112d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459227647 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.2459227647
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.212200921
Short name T171
Test name
Test status
Simulation time 580586682741 ps
CPU time 650.93 seconds
Started May 19 01:28:42 PM PDT 24
Finished May 19 01:39:35 PM PDT 24
Peak memory 200544 kb
Host smart-52153ba1-c36f-40e7-9cff-e8d08fd441b9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212200921 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.212200921
Directory /workspace/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.aon_timer_jump.3782268421
Short name T21
Test name
Test status
Simulation time 453184092 ps
CPU time 1.33 seconds
Started May 19 01:28:55 PM PDT 24
Finished May 19 01:29:02 PM PDT 24
Peak memory 183456 kb
Host smart-45e4fe77-54b3-40fa-a754-3a757f5f113c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782268421 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.3782268421
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.3668293563
Short name T418
Test name
Test status
Simulation time 4334027274 ps
CPU time 4.14 seconds
Started May 19 12:38:23 PM PDT 24
Finished May 19 12:38:28 PM PDT 24
Peak memory 197416 kb
Host smart-fd44aa6f-410e-4566-8998-cd904ab46e66
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668293563 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl
_intg_err.3668293563
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.3452369924
Short name T73
Test name
Test status
Simulation time 683362231 ps
CPU time 0.91 seconds
Started May 19 12:38:20 PM PDT 24
Finished May 19 12:38:21 PM PDT 24
Peak memory 194156 kb
Host smart-b36cceeb-089c-4886-977b-324036033f7c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452369924 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_a
liasing.3452369924
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.2409587611
Short name T69
Test name
Test status
Simulation time 1074470517 ps
CPU time 1.56 seconds
Started May 19 12:38:35 PM PDT 24
Finished May 19 12:38:37 PM PDT 24
Peak memory 192068 kb
Host smart-73a417b1-f308-4c8d-8f68-b7688fccf43a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409587611 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_b
it_bash.2409587611
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.971944004
Short name T319
Test name
Test status
Simulation time 890408020 ps
CPU time 0.82 seconds
Started May 19 12:38:17 PM PDT 24
Finished May 19 12:38:19 PM PDT 24
Peak memory 183648 kb
Host smart-f279735b-ff99-431d-9be1-d5df1fcf351c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971944004 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_hw
_reset.971944004
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.2863571517
Short name T344
Test name
Test status
Simulation time 534115579 ps
CPU time 1.1 seconds
Started May 19 12:38:55 PM PDT 24
Finished May 19 12:38:57 PM PDT 24
Peak memory 195900 kb
Host smart-6c16ccab-c565-4a44-8944-51108e96a085
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863571517 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.2863571517
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.714461120
Short name T291
Test name
Test status
Simulation time 474972100 ps
CPU time 0.86 seconds
Started May 19 12:38:22 PM PDT 24
Finished May 19 12:38:28 PM PDT 24
Peak memory 183432 kb
Host smart-a17b3bdf-101f-4ef5-9ab2-f6068b551491
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714461120 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.714461120
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.1625902591
Short name T399
Test name
Test status
Simulation time 511536066 ps
CPU time 0.69 seconds
Started May 19 12:38:19 PM PDT 24
Finished May 19 12:38:20 PM PDT 24
Peak memory 183480 kb
Host smart-3bd3185a-faf7-4ad4-af9b-d0d0b3a402f2
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625902591 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_t
imer_mem_partial_access.1625902591
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.1131864806
Short name T365
Test name
Test status
Simulation time 435420966 ps
CPU time 0.78 seconds
Started May 19 12:38:35 PM PDT 24
Finished May 19 12:38:36 PM PDT 24
Peak memory 183588 kb
Host smart-c707a58b-ae6a-4da1-a32c-acc0dfdcbaab
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131864806 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_w
alk.1131864806
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.3344798351
Short name T33
Test name
Test status
Simulation time 2415632850 ps
CPU time 2.24 seconds
Started May 19 12:38:46 PM PDT 24
Finished May 19 12:38:49 PM PDT 24
Peak memory 183688 kb
Host smart-fa1499ce-f6c0-461f-a9a8-13e3595ac03c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344798351 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon
_timer_same_csr_outstanding.3344798351
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.3478303668
Short name T292
Test name
Test status
Simulation time 378600099 ps
CPU time 1.77 seconds
Started May 19 12:38:19 PM PDT 24
Finished May 19 12:38:21 PM PDT 24
Peak memory 198340 kb
Host smart-a0823f3b-818f-499f-93d1-bbb9401fce94
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478303668 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.3478303668
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.2106032314
Short name T410
Test name
Test status
Simulation time 4565795140 ps
CPU time 1.31 seconds
Started May 19 12:38:20 PM PDT 24
Finished May 19 12:38:22 PM PDT 24
Peak memory 196496 kb
Host smart-856d48fb-16bf-4c62-b54d-31274342b90e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106032314 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl
_intg_err.2106032314
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.426471704
Short name T76
Test name
Test status
Simulation time 465335700 ps
CPU time 0.79 seconds
Started May 19 12:38:44 PM PDT 24
Finished May 19 12:38:46 PM PDT 24
Peak memory 192940 kb
Host smart-675cc985-d3a9-4009-9e97-23de9dbf5b65
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426471704 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_al
iasing.426471704
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.1067419631
Short name T415
Test name
Test status
Simulation time 7032329635 ps
CPU time 8.18 seconds
Started May 19 12:38:25 PM PDT 24
Finished May 19 12:38:34 PM PDT 24
Peak memory 195452 kb
Host smart-c15103a3-6d9d-4011-96d6-48129a4f64d3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067419631 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_b
it_bash.1067419631
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.2076553857
Short name T375
Test name
Test status
Simulation time 1278799064 ps
CPU time 1.62 seconds
Started May 19 12:38:48 PM PDT 24
Finished May 19 12:38:51 PM PDT 24
Peak memory 183528 kb
Host smart-319ae48b-d3ef-4f20-a9b6-d9cfa63e675d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076553857 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_h
w_reset.2076553857
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.786986729
Short name T412
Test name
Test status
Simulation time 366016584 ps
CPU time 0.79 seconds
Started May 19 12:38:26 PM PDT 24
Finished May 19 12:38:28 PM PDT 24
Peak memory 195264 kb
Host smart-ce850df5-8d1e-4cee-bb8d-2e1e527097ba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786986729 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.786986729
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.95712109
Short name T68
Test name
Test status
Simulation time 469673758 ps
CPU time 0.7 seconds
Started May 19 12:38:52 PM PDT 24
Finished May 19 12:38:54 PM PDT 24
Peak memory 192960 kb
Host smart-f1b4aee1-35b8-4816-a82a-59b6defd96d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95712109 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.95712109
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.879257095
Short name T331
Test name
Test status
Simulation time 353971839 ps
CPU time 0.65 seconds
Started May 19 12:38:55 PM PDT 24
Finished May 19 12:38:57 PM PDT 24
Peak memory 183492 kb
Host smart-2bec2120-2b1b-48f8-942b-97f1f36f5508
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879257095 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.879257095
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.2585631308
Short name T372
Test name
Test status
Simulation time 418359632 ps
CPU time 1.19 seconds
Started May 19 12:38:49 PM PDT 24
Finished May 19 12:38:52 PM PDT 24
Peak memory 183396 kb
Host smart-b0809880-6143-4d0e-b897-71637068afdf
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585631308 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_t
imer_mem_partial_access.2585631308
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.2072493372
Short name T359
Test name
Test status
Simulation time 432818535 ps
CPU time 1.24 seconds
Started May 19 12:38:38 PM PDT 24
Finished May 19 12:38:40 PM PDT 24
Peak memory 183904 kb
Host smart-45a5e50b-a89d-4276-9385-58b84fb3c57d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072493372 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_w
alk.2072493372
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.584285333
Short name T342
Test name
Test status
Simulation time 2399008310 ps
CPU time 1.51 seconds
Started May 19 12:38:45 PM PDT 24
Finished May 19 12:38:47 PM PDT 24
Peak memory 183788 kb
Host smart-ba1a483c-2032-43a8-99dc-d8df5a213dbf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584285333 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_
timer_same_csr_outstanding.584285333
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.3638516131
Short name T368
Test name
Test status
Simulation time 529632458 ps
CPU time 2.7 seconds
Started May 19 12:38:54 PM PDT 24
Finished May 19 12:38:58 PM PDT 24
Peak memory 198424 kb
Host smart-1e39f562-7726-4daf-ba17-8cd4e5157504
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638516131 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.3638516131
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.2826161965
Short name T333
Test name
Test status
Simulation time 577012015 ps
CPU time 0.87 seconds
Started May 19 12:38:51 PM PDT 24
Finished May 19 12:38:53 PM PDT 24
Peak memory 195948 kb
Host smart-2f208b1e-99cc-443a-a53b-2c8b1445ae25
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826161965 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.2826161965
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.1970385220
Short name T93
Test name
Test status
Simulation time 396872822 ps
CPU time 0.77 seconds
Started May 19 12:38:52 PM PDT 24
Finished May 19 12:38:54 PM PDT 24
Peak memory 183560 kb
Host smart-f7342df7-d8e5-405e-9ab7-a4eb6da9b4c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970385220 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.1970385220
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.2040353266
Short name T363
Test name
Test status
Simulation time 348655810 ps
CPU time 0.76 seconds
Started May 19 12:38:52 PM PDT 24
Finished May 19 12:38:54 PM PDT 24
Peak memory 183492 kb
Host smart-390e19bc-5ab7-453b-9635-a795f57757ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040353266 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.2040353266
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.2241792983
Short name T409
Test name
Test status
Simulation time 2265391570 ps
CPU time 1.26 seconds
Started May 19 12:38:58 PM PDT 24
Finished May 19 12:39:00 PM PDT 24
Peak memory 194216 kb
Host smart-657f0a72-9e7c-46d7-ab3d-114e989480af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241792983 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.ao
n_timer_same_csr_outstanding.2241792983
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.14810270
Short name T305
Test name
Test status
Simulation time 615800302 ps
CPU time 1.55 seconds
Started May 19 12:38:55 PM PDT 24
Finished May 19 12:38:58 PM PDT 24
Peak memory 198412 kb
Host smart-0fe17691-b179-46dc-bdad-c8924a045f31
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14810270 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.14810270
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.2219780090
Short name T38
Test name
Test status
Simulation time 4660786105 ps
CPU time 4.36 seconds
Started May 19 12:39:06 PM PDT 24
Finished May 19 12:39:12 PM PDT 24
Peak memory 197600 kb
Host smart-5c338d14-0692-44d8-9a97-58fa0428eb60
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219780090 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_t
l_intg_err.2219780090
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.2587001173
Short name T355
Test name
Test status
Simulation time 585878855 ps
CPU time 0.82 seconds
Started May 19 12:39:02 PM PDT 24
Finished May 19 12:39:05 PM PDT 24
Peak memory 194864 kb
Host smart-10952831-bab6-4881-95aa-a18364c938b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587001173 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.2587001173
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.1790729020
Short name T87
Test name
Test status
Simulation time 339029761 ps
CPU time 1.06 seconds
Started May 19 12:39:01 PM PDT 24
Finished May 19 12:39:08 PM PDT 24
Peak memory 192940 kb
Host smart-5610cadd-78a7-4393-8c48-a67bad007d71
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790729020 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.1790729020
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.3041944490
Short name T401
Test name
Test status
Simulation time 377316197 ps
CPU time 0.77 seconds
Started May 19 12:38:54 PM PDT 24
Finished May 19 12:38:55 PM PDT 24
Peak memory 183548 kb
Host smart-f3408b2a-d157-4a29-948d-91bd502865f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041944490 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.3041944490
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.2226466574
Short name T327
Test name
Test status
Simulation time 2500917316 ps
CPU time 3.88 seconds
Started May 19 12:38:45 PM PDT 24
Finished May 19 12:38:50 PM PDT 24
Peak memory 194424 kb
Host smart-d88ec7e0-e4cb-4c35-9c7e-3176bf669244
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226466574 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.ao
n_timer_same_csr_outstanding.2226466574
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.4137456405
Short name T366
Test name
Test status
Simulation time 448402748 ps
CPU time 2.05 seconds
Started May 19 12:39:03 PM PDT 24
Finished May 19 12:39:07 PM PDT 24
Peak memory 198356 kb
Host smart-7eff3e27-5450-4408-91dc-e8fce005ef7d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137456405 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.4137456405
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.809885170
Short name T126
Test name
Test status
Simulation time 8717440335 ps
CPU time 14.29 seconds
Started May 19 12:39:01 PM PDT 24
Finished May 19 12:39:17 PM PDT 24
Peak memory 198292 kb
Host smart-389d5e05-faa8-4948-866d-5047c73d7649
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809885170 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl
_intg_err.809885170
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.2971845233
Short name T377
Test name
Test status
Simulation time 341450375 ps
CPU time 0.87 seconds
Started May 19 12:39:02 PM PDT 24
Finished May 19 12:39:05 PM PDT 24
Peak memory 195448 kb
Host smart-2d770a13-38ce-4f1d-be19-99f7a18d148f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971845233 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.2971845233
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.367500445
Short name T416
Test name
Test status
Simulation time 474175317 ps
CPU time 0.74 seconds
Started May 19 12:38:46 PM PDT 24
Finished May 19 12:38:48 PM PDT 24
Peak memory 183540 kb
Host smart-0558b49e-9266-47fc-b650-ed65626c0370
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367500445 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.367500445
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.1113032585
Short name T317
Test name
Test status
Simulation time 311235662 ps
CPU time 0.65 seconds
Started May 19 12:38:50 PM PDT 24
Finished May 19 12:38:51 PM PDT 24
Peak memory 183524 kb
Host smart-36293bb2-63db-4ab9-892b-8ab9737f6d5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113032585 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.1113032585
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.514488415
Short name T92
Test name
Test status
Simulation time 2090111865 ps
CPU time 1.33 seconds
Started May 19 12:38:57 PM PDT 24
Finished May 19 12:38:59 PM PDT 24
Peak memory 193092 kb
Host smart-acc0be6b-eae3-4e45-becc-589a169780db
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514488415 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon
_timer_same_csr_outstanding.514488415
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.2717134735
Short name T289
Test name
Test status
Simulation time 565747389 ps
CPU time 2.35 seconds
Started May 19 12:39:23 PM PDT 24
Finished May 19 12:39:26 PM PDT 24
Peak memory 198384 kb
Host smart-59537c5a-4c05-4f5c-8710-997afaa24f01
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717134735 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.2717134735
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.1172989998
Short name T37
Test name
Test status
Simulation time 8591454388 ps
CPU time 5.56 seconds
Started May 19 12:39:10 PM PDT 24
Finished May 19 12:39:17 PM PDT 24
Peak memory 197948 kb
Host smart-7ce0ceff-ddc0-4b18-bed4-27e696808c5a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172989998 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_t
l_intg_err.1172989998
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.2873117957
Short name T388
Test name
Test status
Simulation time 439314116 ps
CPU time 0.94 seconds
Started May 19 12:38:48 PM PDT 24
Finished May 19 12:38:51 PM PDT 24
Peak memory 195296 kb
Host smart-59879118-2246-443f-bd34-b6ec67b0f268
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873117957 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.2873117957
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.1169543692
Short name T347
Test name
Test status
Simulation time 442580159 ps
CPU time 0.77 seconds
Started May 19 12:38:58 PM PDT 24
Finished May 19 12:39:00 PM PDT 24
Peak memory 183652 kb
Host smart-5d375562-07b2-42c9-8ed6-dba1dc3aafba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169543692 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.1169543692
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.3951675565
Short name T304
Test name
Test status
Simulation time 308877675 ps
CPU time 0.65 seconds
Started May 19 12:39:04 PM PDT 24
Finished May 19 12:39:06 PM PDT 24
Peak memory 183524 kb
Host smart-69c056f4-571f-4987-a330-22221a6a5e0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951675565 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.3951675565
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.346006875
Short name T350
Test name
Test status
Simulation time 1326946288 ps
CPU time 0.76 seconds
Started May 19 12:39:03 PM PDT 24
Finished May 19 12:39:05 PM PDT 24
Peak memory 193192 kb
Host smart-cc2d3928-1036-47ac-8278-c8cd4ad6ae2b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346006875 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon
_timer_same_csr_outstanding.346006875
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.443845612
Short name T284
Test name
Test status
Simulation time 575850426 ps
CPU time 2.4 seconds
Started May 19 12:38:49 PM PDT 24
Finished May 19 12:38:53 PM PDT 24
Peak memory 198452 kb
Host smart-043332cb-566e-4438-a80b-9f71129b155b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443845612 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.443845612
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.3203514467
Short name T406
Test name
Test status
Simulation time 8913218919 ps
CPU time 4.68 seconds
Started May 19 12:38:56 PM PDT 24
Finished May 19 12:39:02 PM PDT 24
Peak memory 197816 kb
Host smart-2cfa25f3-f688-4115-803b-07f278738eed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203514467 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_t
l_intg_err.3203514467
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.3292976606
Short name T348
Test name
Test status
Simulation time 354252451 ps
CPU time 1.09 seconds
Started May 19 12:38:53 PM PDT 24
Finished May 19 12:38:56 PM PDT 24
Peak memory 195468 kb
Host smart-070d3430-bcdd-4d9b-85c7-33d328ea239e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292976606 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.3292976606
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.54819677
Short name T71
Test name
Test status
Simulation time 547353074 ps
CPU time 0.84 seconds
Started May 19 12:39:07 PM PDT 24
Finished May 19 12:39:09 PM PDT 24
Peak memory 192948 kb
Host smart-2748e673-62bb-4617-807d-eec13daf3265
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54819677 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.54819677
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.3550403089
Short name T324
Test name
Test status
Simulation time 480406786 ps
CPU time 0.89 seconds
Started May 19 12:39:08 PM PDT 24
Finished May 19 12:39:10 PM PDT 24
Peak memory 183520 kb
Host smart-6ce17a70-9778-4af9-8e13-9d0c69071c7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550403089 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.3550403089
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.3259540059
Short name T378
Test name
Test status
Simulation time 1429016712 ps
CPU time 1.4 seconds
Started May 19 12:39:07 PM PDT 24
Finished May 19 12:39:10 PM PDT 24
Peak memory 193124 kb
Host smart-f418cf27-b751-41f2-923d-e9a4aa315294
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259540059 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao
n_timer_same_csr_outstanding.3259540059
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.874116849
Short name T282
Test name
Test status
Simulation time 483765013 ps
CPU time 1.9 seconds
Started May 19 12:38:58 PM PDT 24
Finished May 19 12:39:06 PM PDT 24
Peak memory 198452 kb
Host smart-c02713b7-5385-4199-85be-dda936045260
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874116849 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.874116849
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.2069191783
Short name T124
Test name
Test status
Simulation time 4683311342 ps
CPU time 4.41 seconds
Started May 19 12:38:51 PM PDT 24
Finished May 19 12:38:57 PM PDT 24
Peak memory 197312 kb
Host smart-1fbf67de-9319-444c-bb54-38708008a245
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069191783 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_t
l_intg_err.2069191783
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.3605478733
Short name T294
Test name
Test status
Simulation time 407467126 ps
CPU time 1.23 seconds
Started May 19 12:39:05 PM PDT 24
Finished May 19 12:39:08 PM PDT 24
Peak memory 195368 kb
Host smart-92377c6f-8e17-4680-83e3-e45c84e9dc5a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605478733 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.3605478733
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.4103142681
Short name T64
Test name
Test status
Simulation time 544211649 ps
CPU time 1.37 seconds
Started May 19 12:39:00 PM PDT 24
Finished May 19 12:39:03 PM PDT 24
Peak memory 192908 kb
Host smart-4ba57add-37d6-4f3b-b51f-35ac571662d7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103142681 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.4103142681
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.397425466
Short name T316
Test name
Test status
Simulation time 473553757 ps
CPU time 1.19 seconds
Started May 19 12:39:01 PM PDT 24
Finished May 19 12:39:03 PM PDT 24
Peak memory 183540 kb
Host smart-b84c4b21-6cde-46f9-8e3e-82a2f3a26ab6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397425466 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.397425466
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.2205606120
Short name T364
Test name
Test status
Simulation time 2052230190 ps
CPU time 1.07 seconds
Started May 19 12:38:57 PM PDT 24
Finished May 19 12:39:05 PM PDT 24
Peak memory 194180 kb
Host smart-1486a8d7-f544-4240-bad4-a4d8658e6201
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205606120 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.ao
n_timer_same_csr_outstanding.2205606120
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.4131037372
Short name T307
Test name
Test status
Simulation time 615369022 ps
CPU time 2.41 seconds
Started May 19 12:39:01 PM PDT 24
Finished May 19 12:39:05 PM PDT 24
Peak memory 198420 kb
Host smart-690a3cec-ad8b-4a42-a051-447426af09ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131037372 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.4131037372
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.2731345158
Short name T395
Test name
Test status
Simulation time 8624143944 ps
CPU time 4.35 seconds
Started May 19 12:38:52 PM PDT 24
Finished May 19 12:38:58 PM PDT 24
Peak memory 197892 kb
Host smart-5d18548f-36e1-4aa8-a32c-7ab34c5eca4b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731345158 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_t
l_intg_err.2731345158
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.1487503588
Short name T295
Test name
Test status
Simulation time 722481631 ps
CPU time 0.7 seconds
Started May 19 12:39:12 PM PDT 24
Finished May 19 12:39:13 PM PDT 24
Peak memory 195388 kb
Host smart-8a1d85e8-e0e6-4d82-9e13-2995dcd38145
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487503588 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.1487503588
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.2659628877
Short name T386
Test name
Test status
Simulation time 503992580 ps
CPU time 0.76 seconds
Started May 19 12:39:00 PM PDT 24
Finished May 19 12:39:03 PM PDT 24
Peak memory 192840 kb
Host smart-c7995b25-c440-428c-923b-b741a9ed25b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659628877 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.2659628877
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.1952522974
Short name T296
Test name
Test status
Simulation time 403772833 ps
CPU time 1.04 seconds
Started May 19 12:38:52 PM PDT 24
Finished May 19 12:38:55 PM PDT 24
Peak memory 183512 kb
Host smart-6b6388cc-4764-405b-9497-9f1eb3fd6579
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952522974 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.1952522974
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.2785021741
Short name T91
Test name
Test status
Simulation time 2185266581 ps
CPU time 3.9 seconds
Started May 19 12:39:01 PM PDT 24
Finished May 19 12:39:08 PM PDT 24
Peak memory 194288 kb
Host smart-f088413c-485a-49c9-882c-1d58ff15d80c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785021741 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.ao
n_timer_same_csr_outstanding.2785021741
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.4059553937
Short name T110
Test name
Test status
Simulation time 497267211 ps
CPU time 1.78 seconds
Started May 19 12:39:04 PM PDT 24
Finished May 19 12:39:08 PM PDT 24
Peak memory 198448 kb
Host smart-ecb7f072-28cc-4a91-bbc7-58188a64436f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059553937 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.4059553937
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.3583992373
Short name T328
Test name
Test status
Simulation time 7809257676 ps
CPU time 6.13 seconds
Started May 19 12:39:06 PM PDT 24
Finished May 19 12:39:13 PM PDT 24
Peak memory 197884 kb
Host smart-dfb0bd9e-203f-4e6a-a902-d30ad1be2666
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583992373 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_t
l_intg_err.3583992373
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.165920088
Short name T334
Test name
Test status
Simulation time 478272220 ps
CPU time 0.87 seconds
Started May 19 12:39:02 PM PDT 24
Finished May 19 12:39:05 PM PDT 24
Peak memory 196176 kb
Host smart-d4e386a4-0b18-418c-8e20-3929c3e7ddae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165920088 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.165920088
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.3817325580
Short name T72
Test name
Test status
Simulation time 488745956 ps
CPU time 0.92 seconds
Started May 19 12:39:15 PM PDT 24
Finished May 19 12:39:17 PM PDT 24
Peak memory 192892 kb
Host smart-60ebe13a-f13d-4bfc-b503-3a720e41660a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817325580 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.3817325580
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.57750073
Short name T322
Test name
Test status
Simulation time 396113765 ps
CPU time 0.68 seconds
Started May 19 12:39:23 PM PDT 24
Finished May 19 12:39:25 PM PDT 24
Peak memory 183456 kb
Host smart-9a1b30e3-7a0f-4191-819f-138f86d38d18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57750073 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.57750073
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.1263240934
Short name T88
Test name
Test status
Simulation time 1588572680 ps
CPU time 3.74 seconds
Started May 19 12:39:04 PM PDT 24
Finished May 19 12:39:09 PM PDT 24
Peak memory 193380 kb
Host smart-ecefc06e-1e14-49ee-ad1f-d962d3c28a3e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263240934 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.ao
n_timer_same_csr_outstanding.1263240934
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.4139500320
Short name T391
Test name
Test status
Simulation time 433620797 ps
CPU time 2.77 seconds
Started May 19 12:39:03 PM PDT 24
Finished May 19 12:39:07 PM PDT 24
Peak memory 198492 kb
Host smart-c2d51e3f-eb87-4c11-89a9-ef8c1385ec9d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139500320 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.4139500320
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.628747071
Short name T330
Test name
Test status
Simulation time 4233335027 ps
CPU time 7.3 seconds
Started May 19 12:38:54 PM PDT 24
Finished May 19 12:39:03 PM PDT 24
Peak memory 197444 kb
Host smart-1fb84fe8-6fdc-4610-9fb1-f9d0a1bfbd60
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628747071 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl
_intg_err.628747071
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.4016123221
Short name T369
Test name
Test status
Simulation time 608072120 ps
CPU time 1.15 seconds
Started May 19 12:38:56 PM PDT 24
Finished May 19 12:38:58 PM PDT 24
Peak memory 196348 kb
Host smart-e823ec00-b7d3-4487-979c-3841ea477c5c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016123221 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.4016123221
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.1886023865
Short name T130
Test name
Test status
Simulation time 353171704 ps
CPU time 1.08 seconds
Started May 19 12:38:55 PM PDT 24
Finished May 19 12:38:58 PM PDT 24
Peak memory 183668 kb
Host smart-946cf2ce-8dff-43fb-8fd2-33c63422d8f0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886023865 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.1886023865
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.3711815409
Short name T352
Test name
Test status
Simulation time 436158540 ps
CPU time 1.15 seconds
Started May 19 12:38:49 PM PDT 24
Finished May 19 12:38:52 PM PDT 24
Peak memory 183432 kb
Host smart-51570d50-70e4-4892-96e9-7cc8cf0420c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711815409 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.3711815409
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.1841452062
Short name T32
Test name
Test status
Simulation time 2545924737 ps
CPU time 2.39 seconds
Started May 19 12:38:49 PM PDT 24
Finished May 19 12:38:53 PM PDT 24
Peak memory 183760 kb
Host smart-0a750c0f-b146-4e25-b381-c9c8ed62a124
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841452062 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.ao
n_timer_same_csr_outstanding.1841452062
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.3483690502
Short name T358
Test name
Test status
Simulation time 554910248 ps
CPU time 1.39 seconds
Started May 19 12:39:05 PM PDT 24
Finished May 19 12:39:07 PM PDT 24
Peak memory 198392 kb
Host smart-1f6e35af-a2b6-4177-90ab-d5deecd7ec67
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483690502 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.3483690502
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.3926698070
Short name T389
Test name
Test status
Simulation time 4381429043 ps
CPU time 6.29 seconds
Started May 19 12:39:02 PM PDT 24
Finished May 19 12:39:11 PM PDT 24
Peak memory 196288 kb
Host smart-d7061975-6813-4868-8e2a-64cb50aeec6d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926698070 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_t
l_intg_err.3926698070
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.3438444833
Short name T382
Test name
Test status
Simulation time 458752289 ps
CPU time 1.13 seconds
Started May 19 12:38:57 PM PDT 24
Finished May 19 12:38:59 PM PDT 24
Peak memory 198104 kb
Host smart-cd516250-a5b8-4924-936a-d0bd7ad8c6e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438444833 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.3438444833
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.402228622
Short name T67
Test name
Test status
Simulation time 450176982 ps
CPU time 1.02 seconds
Started May 19 12:39:05 PM PDT 24
Finished May 19 12:39:07 PM PDT 24
Peak memory 192916 kb
Host smart-a0cfc5bb-86d4-444c-85c1-bd9e14e52601
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402228622 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.402228622
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.1383760897
Short name T340
Test name
Test status
Simulation time 330780000 ps
CPU time 0.65 seconds
Started May 19 12:38:48 PM PDT 24
Finished May 19 12:38:50 PM PDT 24
Peak memory 183564 kb
Host smart-56bbd834-799c-4e0d-8f94-cc36a391ac81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383760897 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.1383760897
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.3695417732
Short name T405
Test name
Test status
Simulation time 1306940549 ps
CPU time 3.45 seconds
Started May 19 12:38:58 PM PDT 24
Finished May 19 12:39:03 PM PDT 24
Peak memory 193552 kb
Host smart-ce94ed12-303f-4174-b8ee-1721c5b879a3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695417732 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao
n_timer_same_csr_outstanding.3695417732
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.4276611135
Short name T356
Test name
Test status
Simulation time 380934716 ps
CPU time 2.27 seconds
Started May 19 12:39:00 PM PDT 24
Finished May 19 12:39:03 PM PDT 24
Peak memory 198452 kb
Host smart-e297af2f-aa04-4fcc-981a-639e9ebf6e64
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276611135 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.4276611135
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.2594440365
Short name T345
Test name
Test status
Simulation time 4370921692 ps
CPU time 2.79 seconds
Started May 19 12:39:00 PM PDT 24
Finished May 19 12:39:05 PM PDT 24
Peak memory 196072 kb
Host smart-8a6d578f-f4e3-44bc-a14c-245e597a3308
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594440365 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_t
l_intg_err.2594440365
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.732098183
Short name T313
Test name
Test status
Simulation time 733368823 ps
CPU time 1.32 seconds
Started May 19 12:38:49 PM PDT 24
Finished May 19 12:38:51 PM PDT 24
Peak memory 183688 kb
Host smart-0e9b61a3-62c2-4519-9ad9-f38d28190bb0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732098183 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_al
iasing.732098183
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.2113893089
Short name T132
Test name
Test status
Simulation time 7494036370 ps
CPU time 9.52 seconds
Started May 19 12:38:25 PM PDT 24
Finished May 19 12:38:36 PM PDT 24
Peak memory 192080 kb
Host smart-1f021f42-8610-49ad-a270-5e6d6ad98c69
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113893089 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_b
it_bash.2113893089
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.2781669086
Short name T65
Test name
Test status
Simulation time 1094218933 ps
CPU time 1.53 seconds
Started May 19 12:38:36 PM PDT 24
Finished May 19 12:38:38 PM PDT 24
Peak memory 183568 kb
Host smart-64d1e2c4-ed6e-4c41-97ff-8b985b0344c8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781669086 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_h
w_reset.2781669086
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.1056027019
Short name T396
Test name
Test status
Simulation time 561902650 ps
CPU time 1.44 seconds
Started May 19 12:38:46 PM PDT 24
Finished May 19 12:38:49 PM PDT 24
Peak memory 195076 kb
Host smart-d80ca3f8-4c67-4c60-bf76-05359ba110c1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056027019 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.1056027019
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.1332045080
Short name T70
Test name
Test status
Simulation time 356808781 ps
CPU time 0.84 seconds
Started May 19 12:38:24 PM PDT 24
Finished May 19 12:38:30 PM PDT 24
Peak memory 192772 kb
Host smart-3459dec1-d9ac-48ad-8b94-1ac87dbab084
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332045080 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.1332045080
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.1512240742
Short name T321
Test name
Test status
Simulation time 321984831 ps
CPU time 0.94 seconds
Started May 19 12:38:21 PM PDT 24
Finished May 19 12:38:23 PM PDT 24
Peak memory 183528 kb
Host smart-c2385959-504b-4c67-a242-3a29f9daf404
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512240742 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.1512240742
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.3812981994
Short name T293
Test name
Test status
Simulation time 457867045 ps
CPU time 0.57 seconds
Started May 19 12:38:55 PM PDT 24
Finished May 19 12:38:57 PM PDT 24
Peak memory 183500 kb
Host smart-019294ba-3cb5-4a14-b73d-c249abce6098
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812981994 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_t
imer_mem_partial_access.3812981994
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.1500899432
Short name T285
Test name
Test status
Simulation time 533393804 ps
CPU time 0.65 seconds
Started May 19 12:38:57 PM PDT 24
Finished May 19 12:38:59 PM PDT 24
Peak memory 183492 kb
Host smart-c6004059-120a-4e72-96d3-38ac7f77e080
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500899432 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_w
alk.1500899432
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.2861506763
Short name T89
Test name
Test status
Simulation time 948893590 ps
CPU time 1.21 seconds
Started May 19 12:38:24 PM PDT 24
Finished May 19 12:38:26 PM PDT 24
Peak memory 183660 kb
Host smart-ac2d967a-2e67-4fe8-8398-e6c52cf29711
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861506763 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon
_timer_same_csr_outstanding.2861506763
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.610781465
Short name T411
Test name
Test status
Simulation time 477337123 ps
CPU time 2.24 seconds
Started May 19 12:38:21 PM PDT 24
Finished May 19 12:38:24 PM PDT 24
Peak memory 198436 kb
Host smart-518140e4-4ee6-447a-9194-ea2095172769
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610781465 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.610781465
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.3555318067
Short name T346
Test name
Test status
Simulation time 323326898 ps
CPU time 0.7 seconds
Started May 19 12:39:03 PM PDT 24
Finished May 19 12:39:05 PM PDT 24
Peak memory 183560 kb
Host smart-3337ca7c-a932-4dc3-a8e1-1735253df663
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555318067 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.3555318067
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.2778282591
Short name T402
Test name
Test status
Simulation time 342378713 ps
CPU time 1.1 seconds
Started May 19 12:39:08 PM PDT 24
Finished May 19 12:39:10 PM PDT 24
Peak memory 183492 kb
Host smart-e1c06852-356d-44f8-9c09-da516c5ea639
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778282591 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.2778282591
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.274900628
Short name T393
Test name
Test status
Simulation time 304123915 ps
CPU time 0.77 seconds
Started May 19 12:39:06 PM PDT 24
Finished May 19 12:39:08 PM PDT 24
Peak memory 183468 kb
Host smart-213e97e6-233a-4c68-8dad-87beb73365a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274900628 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.274900628
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.2903907371
Short name T370
Test name
Test status
Simulation time 391067168 ps
CPU time 1.26 seconds
Started May 19 12:38:57 PM PDT 24
Finished May 19 12:39:00 PM PDT 24
Peak memory 183508 kb
Host smart-b64106e3-fe63-4531-8ce0-498121fc5118
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903907371 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.2903907371
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.3071972798
Short name T312
Test name
Test status
Simulation time 398919413 ps
CPU time 0.66 seconds
Started May 19 12:39:07 PM PDT 24
Finished May 19 12:39:09 PM PDT 24
Peak memory 183896 kb
Host smart-713720fd-f862-4ca3-acfd-1d526b84e3bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071972798 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.3071972798
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.2170127165
Short name T329
Test name
Test status
Simulation time 489699307 ps
CPU time 1.3 seconds
Started May 19 12:38:58 PM PDT 24
Finished May 19 12:39:00 PM PDT 24
Peak memory 183536 kb
Host smart-0d5b7219-bb81-42ec-a1c3-da15bbf9b2f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170127165 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.2170127165
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.3258607894
Short name T384
Test name
Test status
Simulation time 652700076 ps
CPU time 0.56 seconds
Started May 19 12:39:23 PM PDT 24
Finished May 19 12:39:25 PM PDT 24
Peak memory 183524 kb
Host smart-70763d19-71d4-46aa-976e-08b6b338d594
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258607894 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.3258607894
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.1795741655
Short name T311
Test name
Test status
Simulation time 319777151 ps
CPU time 0.79 seconds
Started May 19 12:39:02 PM PDT 24
Finished May 19 12:39:05 PM PDT 24
Peak memory 183472 kb
Host smart-65e736a2-cee3-44c5-868c-01a5e1d78ee0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795741655 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.1795741655
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.774039255
Short name T326
Test name
Test status
Simulation time 448064372 ps
CPU time 0.88 seconds
Started May 19 12:39:03 PM PDT 24
Finished May 19 12:39:05 PM PDT 24
Peak memory 183560 kb
Host smart-51e8cbce-bb34-4805-bb00-29e24b8fd97b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774039255 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.774039255
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.3294916490
Short name T407
Test name
Test status
Simulation time 292527902 ps
CPU time 0.94 seconds
Started May 19 12:39:19 PM PDT 24
Finished May 19 12:39:20 PM PDT 24
Peak memory 183524 kb
Host smart-4d99340b-7195-4815-ba4b-26bb7be00acc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294916490 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.3294916490
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.4256386379
Short name T74
Test name
Test status
Simulation time 672473819 ps
CPU time 0.85 seconds
Started May 19 12:38:46 PM PDT 24
Finished May 19 12:38:48 PM PDT 24
Peak memory 191788 kb
Host smart-0d79aefc-a54c-4a3a-9c76-f497f03fad05
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256386379 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_a
liasing.4256386379
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.21036649
Short name T75
Test name
Test status
Simulation time 12333596343 ps
CPU time 17.15 seconds
Started May 19 12:38:52 PM PDT 24
Finished May 19 12:39:10 PM PDT 24
Peak memory 194200 kb
Host smart-b9587873-a6c8-4454-8580-c35f801f9fab
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21036649 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_bit
_bash.21036649
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.2566361042
Short name T414
Test name
Test status
Simulation time 1172920430 ps
CPU time 2.4 seconds
Started May 19 12:38:56 PM PDT 24
Finished May 19 12:39:01 PM PDT 24
Peak memory 183664 kb
Host smart-57b40256-a4e1-4a8d-960e-8cd2447e8ab0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566361042 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_h
w_reset.2566361042
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.2204664317
Short name T394
Test name
Test status
Simulation time 565371153 ps
CPU time 0.95 seconds
Started May 19 12:38:33 PM PDT 24
Finished May 19 12:38:34 PM PDT 24
Peak memory 195736 kb
Host smart-800d6959-6815-400c-92a3-3c157069a94c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204664317 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.2204664317
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.3735160793
Short name T381
Test name
Test status
Simulation time 293181554 ps
CPU time 0.78 seconds
Started May 19 12:38:50 PM PDT 24
Finished May 19 12:38:52 PM PDT 24
Peak memory 183520 kb
Host smart-f50029b8-e8fa-48d8-b9f7-7c22570857d5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735160793 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.3735160793
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.1237989733
Short name T387
Test name
Test status
Simulation time 282888419 ps
CPU time 0.89 seconds
Started May 19 12:38:23 PM PDT 24
Finished May 19 12:38:25 PM PDT 24
Peak memory 183560 kb
Host smart-64be3aa0-cdfb-48eb-9a58-bfb55d73b069
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237989733 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.1237989733
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.629929739
Short name T303
Test name
Test status
Simulation time 361146878 ps
CPU time 0.77 seconds
Started May 19 12:38:45 PM PDT 24
Finished May 19 12:38:47 PM PDT 24
Peak memory 183380 kb
Host smart-205c5b00-c487-4829-90ef-0c4d1aef9759
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629929739 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_ti
mer_mem_partial_access.629929739
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.1805466443
Short name T354
Test name
Test status
Simulation time 375913951 ps
CPU time 0.7 seconds
Started May 19 12:38:25 PM PDT 24
Finished May 19 12:38:26 PM PDT 24
Peak memory 183448 kb
Host smart-d0eafe4e-d307-4556-882e-6ad2de1bd21b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805466443 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_w
alk.1805466443
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.2946672478
Short name T90
Test name
Test status
Simulation time 1770783738 ps
CPU time 3.26 seconds
Started May 19 12:38:52 PM PDT 24
Finished May 19 12:38:56 PM PDT 24
Peak memory 193224 kb
Host smart-334afbd3-d5e4-4308-8145-61cf22a1909e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946672478 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon
_timer_same_csr_outstanding.2946672478
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.3402639852
Short name T306
Test name
Test status
Simulation time 321174137 ps
CPU time 1.87 seconds
Started May 19 12:38:24 PM PDT 24
Finished May 19 12:38:26 PM PDT 24
Peak memory 198416 kb
Host smart-6be50cea-3d18-408e-b195-475d7401cdd6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402639852 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.3402639852
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.78191453
Short name T380
Test name
Test status
Simulation time 4232692935 ps
CPU time 7.48 seconds
Started May 19 12:38:54 PM PDT 24
Finished May 19 12:39:02 PM PDT 24
Peak memory 197572 kb
Host smart-e11ce2ac-8799-418b-a334-b04873f5da98
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78191453 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_i
ntg_err.78191453
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.899211743
Short name T301
Test name
Test status
Simulation time 407210743 ps
CPU time 0.67 seconds
Started May 19 12:39:30 PM PDT 24
Finished May 19 12:39:31 PM PDT 24
Peak memory 183932 kb
Host smart-3d1e1600-a5b8-4c91-b51a-e8e31fd84418
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899211743 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.899211743
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.2032561875
Short name T398
Test name
Test status
Simulation time 500833457 ps
CPU time 0.56 seconds
Started May 19 12:39:05 PM PDT 24
Finished May 19 12:39:07 PM PDT 24
Peak memory 183508 kb
Host smart-8e08833f-20b8-4208-96e4-f4d710318372
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032561875 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.2032561875
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.1310773995
Short name T373
Test name
Test status
Simulation time 627705029 ps
CPU time 0.58 seconds
Started May 19 12:39:01 PM PDT 24
Finished May 19 12:39:04 PM PDT 24
Peak memory 183464 kb
Host smart-f337a45f-7ae6-4c65-8d95-09c5daaba461
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310773995 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.1310773995
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.138502225
Short name T349
Test name
Test status
Simulation time 388161899 ps
CPU time 1.09 seconds
Started May 19 12:38:55 PM PDT 24
Finished May 19 12:38:58 PM PDT 24
Peak memory 183596 kb
Host smart-594bf334-8d76-41e5-b1be-cca9406a0c23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138502225 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.138502225
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.1313372595
Short name T383
Test name
Test status
Simulation time 459207920 ps
CPU time 1.11 seconds
Started May 19 12:39:10 PM PDT 24
Finished May 19 12:39:12 PM PDT 24
Peak memory 183520 kb
Host smart-dd261a0f-2149-4eba-ae4c-f1c6fd5637a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313372595 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.1313372595
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.458608656
Short name T300
Test name
Test status
Simulation time 412749519 ps
CPU time 0.83 seconds
Started May 19 12:38:57 PM PDT 24
Finished May 19 12:39:00 PM PDT 24
Peak memory 183472 kb
Host smart-72c59796-f91e-419e-be59-298e5def4e64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458608656 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.458608656
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.1070692552
Short name T320
Test name
Test status
Simulation time 300357409 ps
CPU time 0.9 seconds
Started May 19 12:39:08 PM PDT 24
Finished May 19 12:39:10 PM PDT 24
Peak memory 183492 kb
Host smart-20c766fc-4806-4645-99d4-a490adfec10c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070692552 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.1070692552
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.1786246902
Short name T353
Test name
Test status
Simulation time 409215845 ps
CPU time 1.14 seconds
Started May 19 12:39:04 PM PDT 24
Finished May 19 12:39:07 PM PDT 24
Peak memory 183484 kb
Host smart-6f54ea14-7fa8-45e8-a775-d23f11123a02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786246902 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.1786246902
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.1065533767
Short name T287
Test name
Test status
Simulation time 505295153 ps
CPU time 1.23 seconds
Started May 19 12:38:54 PM PDT 24
Finished May 19 12:38:56 PM PDT 24
Peak memory 183516 kb
Host smart-64c1d161-6c69-422c-9aeb-7d8b4f1efae9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065533767 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.1065533767
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.164816534
Short name T385
Test name
Test status
Simulation time 390511458 ps
CPU time 0.69 seconds
Started May 19 12:39:01 PM PDT 24
Finished May 19 12:39:04 PM PDT 24
Peak memory 183484 kb
Host smart-b692af9a-31de-478e-9cba-450fd5e3c561
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164816534 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.164816534
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.3751658492
Short name T357
Test name
Test status
Simulation time 693340230 ps
CPU time 1.83 seconds
Started May 19 12:38:45 PM PDT 24
Finished May 19 12:38:48 PM PDT 24
Peak memory 193812 kb
Host smart-f96854a0-3abf-47d3-ae4d-ed356997c32b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751658492 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_a
liasing.3751658492
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.2100040269
Short name T286
Test name
Test status
Simulation time 7094782755 ps
CPU time 3.76 seconds
Started May 19 12:38:45 PM PDT 24
Finished May 19 12:38:50 PM PDT 24
Peak memory 192084 kb
Host smart-1974573d-2461-4f50-93fe-388f14ec6688
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100040269 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_b
it_bash.2100040269
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.2658617389
Short name T371
Test name
Test status
Simulation time 756225895 ps
CPU time 1.68 seconds
Started May 19 12:38:32 PM PDT 24
Finished May 19 12:38:34 PM PDT 24
Peak memory 183540 kb
Host smart-453bdbaa-d49a-4f0a-a86f-6ff47d1c5256
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658617389 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_h
w_reset.2658617389
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.1385243028
Short name T341
Test name
Test status
Simulation time 442004701 ps
CPU time 1.35 seconds
Started May 19 12:38:55 PM PDT 24
Finished May 19 12:38:57 PM PDT 24
Peak memory 196752 kb
Host smart-b843d432-dbd3-4937-9b94-b96f522fa8c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385243028 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.1385243028
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.1766570500
Short name T66
Test name
Test status
Simulation time 401429562 ps
CPU time 0.85 seconds
Started May 19 12:38:26 PM PDT 24
Finished May 19 12:38:28 PM PDT 24
Peak memory 183924 kb
Host smart-f814ae6a-0cf6-4d64-8ca1-1080159e968a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766570500 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.1766570500
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.1261319779
Short name T404
Test name
Test status
Simulation time 441024103 ps
CPU time 0.91 seconds
Started May 19 12:38:48 PM PDT 24
Finished May 19 12:38:50 PM PDT 24
Peak memory 183492 kb
Host smart-5722f0d8-8af2-4d90-b854-0959ea25f4e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261319779 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.1261319779
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.3628366711
Short name T283
Test name
Test status
Simulation time 277257873 ps
CPU time 0.61 seconds
Started May 19 12:38:40 PM PDT 24
Finished May 19 12:38:41 PM PDT 24
Peak memory 183424 kb
Host smart-83c518a6-14c7-4770-ae93-d5a13d73d554
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628366711 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_t
imer_mem_partial_access.3628366711
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.3351744892
Short name T362
Test name
Test status
Simulation time 338256129 ps
CPU time 0.64 seconds
Started May 19 12:38:44 PM PDT 24
Finished May 19 12:38:46 PM PDT 24
Peak memory 183468 kb
Host smart-6b72cd09-06de-4aae-a113-4a9c34a3145b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351744892 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_w
alk.3351744892
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.3823885609
Short name T417
Test name
Test status
Simulation time 1055898953 ps
CPU time 2.11 seconds
Started May 19 12:38:54 PM PDT 24
Finished May 19 12:38:57 PM PDT 24
Peak memory 193140 kb
Host smart-ae1e31b2-de04-4f07-b587-2ed51cd43f89
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823885609 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon
_timer_same_csr_outstanding.3823885609
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.410062061
Short name T332
Test name
Test status
Simulation time 357333627 ps
CPU time 1.8 seconds
Started May 19 12:38:40 PM PDT 24
Finished May 19 12:38:43 PM PDT 24
Peak memory 198360 kb
Host smart-e18e343c-15c0-4226-a076-a8c1534a78f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410062061 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.410062061
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.593587639
Short name T343
Test name
Test status
Simulation time 8233870650 ps
CPU time 13.93 seconds
Started May 19 12:38:53 PM PDT 24
Finished May 19 12:39:08 PM PDT 24
Peak memory 197880 kb
Host smart-a59643d5-2cfb-4e2a-8776-d5f7cff6d4d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593587639 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_
intg_err.593587639
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.892179543
Short name T310
Test name
Test status
Simulation time 421722427 ps
CPU time 1.06 seconds
Started May 19 12:39:06 PM PDT 24
Finished May 19 12:39:08 PM PDT 24
Peak memory 183508 kb
Host smart-36bdf48d-d1a2-4439-bd79-3401edcd30d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892179543 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.892179543
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.1444920016
Short name T314
Test name
Test status
Simulation time 455891685 ps
CPU time 0.9 seconds
Started May 19 12:39:25 PM PDT 24
Finished May 19 12:39:26 PM PDT 24
Peak memory 183476 kb
Host smart-eea35a63-7782-42f8-bf6a-1be6cc08dd3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444920016 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.1444920016
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.1807920874
Short name T297
Test name
Test status
Simulation time 468957292 ps
CPU time 1.07 seconds
Started May 19 12:39:01 PM PDT 24
Finished May 19 12:39:04 PM PDT 24
Peak memory 183572 kb
Host smart-98a91fb2-c403-414e-b266-37b5adc28bdf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807920874 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.1807920874
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.2699476274
Short name T367
Test name
Test status
Simulation time 338534910 ps
CPU time 0.9 seconds
Started May 19 12:39:06 PM PDT 24
Finished May 19 12:39:09 PM PDT 24
Peak memory 183508 kb
Host smart-3b56b0d4-7d48-4917-aae4-0c5da8751e28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699476274 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.2699476274
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.3393476927
Short name T315
Test name
Test status
Simulation time 300107720 ps
CPU time 0.62 seconds
Started May 19 12:39:10 PM PDT 24
Finished May 19 12:39:11 PM PDT 24
Peak memory 183448 kb
Host smart-d4a1b0b1-7396-4357-b966-6e270fa1c5d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393476927 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.3393476927
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.3068355283
Short name T339
Test name
Test status
Simulation time 499731089 ps
CPU time 0.58 seconds
Started May 19 12:39:07 PM PDT 24
Finished May 19 12:39:09 PM PDT 24
Peak memory 183472 kb
Host smart-345a4799-0df1-46aa-a14b-029ba9dfa304
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068355283 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.3068355283
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.1803291863
Short name T325
Test name
Test status
Simulation time 478833571 ps
CPU time 0.7 seconds
Started May 19 12:39:11 PM PDT 24
Finished May 19 12:39:13 PM PDT 24
Peak memory 183520 kb
Host smart-1cdecbd4-4bbd-496f-8dfb-8ba9c591c0a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803291863 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.1803291863
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.3771033618
Short name T299
Test name
Test status
Simulation time 472496009 ps
CPU time 0.87 seconds
Started May 19 12:38:55 PM PDT 24
Finished May 19 12:38:58 PM PDT 24
Peak memory 183596 kb
Host smart-d3b1acd1-33bf-453d-815b-38e8ddc60185
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771033618 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.3771033618
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.577714996
Short name T374
Test name
Test status
Simulation time 381631945 ps
CPU time 0.67 seconds
Started May 19 12:39:16 PM PDT 24
Finished May 19 12:39:17 PM PDT 24
Peak memory 183932 kb
Host smart-dead10a7-974f-4186-80e8-e6ed9bd49b79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577714996 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.577714996
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.1845276261
Short name T318
Test name
Test status
Simulation time 517378205 ps
CPU time 0.61 seconds
Started May 19 12:39:08 PM PDT 24
Finished May 19 12:39:10 PM PDT 24
Peak memory 183416 kb
Host smart-7d7b7df9-0aac-4a05-ac76-5aa8c8042de5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845276261 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.1845276261
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.4260790256
Short name T336
Test name
Test status
Simulation time 466930283 ps
CPU time 1.13 seconds
Started May 19 12:39:07 PM PDT 24
Finished May 19 12:39:14 PM PDT 24
Peak memory 194768 kb
Host smart-2b8bdec5-4e6c-45e1-8000-cc2134596e8b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260790256 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.4260790256
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.2495947758
Short name T131
Test name
Test status
Simulation time 344886309 ps
CPU time 0.82 seconds
Started May 19 12:38:40 PM PDT 24
Finished May 19 12:38:42 PM PDT 24
Peak memory 192936 kb
Host smart-944000fb-c3ce-4bdf-8a6e-dbaaac333fe1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495947758 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.2495947758
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.2089931035
Short name T390
Test name
Test status
Simulation time 378061821 ps
CPU time 0.83 seconds
Started May 19 12:38:52 PM PDT 24
Finished May 19 12:38:54 PM PDT 24
Peak memory 183492 kb
Host smart-7edae9e9-1703-4937-8e9a-1d14f677d254
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089931035 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.2089931035
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.2570455026
Short name T408
Test name
Test status
Simulation time 1305008044 ps
CPU time 1.07 seconds
Started May 19 12:38:26 PM PDT 24
Finished May 19 12:38:28 PM PDT 24
Peak memory 193256 kb
Host smart-f9fe7476-43db-4992-8152-0370de8e25a6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570455026 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon
_timer_same_csr_outstanding.2570455026
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.741520891
Short name T376
Test name
Test status
Simulation time 552260150 ps
CPU time 2.48 seconds
Started May 19 12:38:28 PM PDT 24
Finished May 19 12:38:31 PM PDT 24
Peak memory 198364 kb
Host smart-4ced56c1-fe5b-4a09-a17c-e3b42b3fb63c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741520891 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.741520891
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.490953468
Short name T125
Test name
Test status
Simulation time 4574301435 ps
CPU time 2.35 seconds
Started May 19 12:38:56 PM PDT 24
Finished May 19 12:39:00 PM PDT 24
Peak memory 196360 kb
Host smart-03fd19e6-2fff-4e92-adb8-3e954a402fb7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490953468 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_
intg_err.490953468
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.1922816824
Short name T302
Test name
Test status
Simulation time 558228898 ps
CPU time 1.5 seconds
Started May 19 12:38:50 PM PDT 24
Finished May 19 12:38:53 PM PDT 24
Peak memory 195444 kb
Host smart-a8c58d10-c241-4487-8bcd-061a9ea30895
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922816824 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.1922816824
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.390631330
Short name T392
Test name
Test status
Simulation time 401191892 ps
CPU time 1.1 seconds
Started May 19 12:39:00 PM PDT 24
Finished May 19 12:39:03 PM PDT 24
Peak memory 183608 kb
Host smart-e89bf192-2c81-4d05-89dd-9bd1b7583af4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390631330 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.390631330
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.3705020551
Short name T323
Test name
Test status
Simulation time 442912085 ps
CPU time 0.81 seconds
Started May 19 12:38:46 PM PDT 24
Finished May 19 12:38:48 PM PDT 24
Peak memory 183480 kb
Host smart-ba5e616b-d7a9-49f8-bb99-23a400e8a09f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705020551 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.3705020551
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.2203383744
Short name T397
Test name
Test status
Simulation time 2204555045 ps
CPU time 1.82 seconds
Started May 19 12:38:50 PM PDT 24
Finished May 19 12:38:53 PM PDT 24
Peak memory 195080 kb
Host smart-6883a4ce-013e-4bb1-bfab-2ea5f2278d4c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203383744 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon
_timer_same_csr_outstanding.2203383744
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.3476949788
Short name T338
Test name
Test status
Simulation time 496871063 ps
CPU time 2.37 seconds
Started May 19 12:38:44 PM PDT 24
Finished May 19 12:38:48 PM PDT 24
Peak memory 198360 kb
Host smart-1bcd88a6-32f0-4154-9658-921118d30926
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476949788 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.3476949788
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.1248939000
Short name T129
Test name
Test status
Simulation time 8566263502 ps
CPU time 13.74 seconds
Started May 19 12:38:28 PM PDT 24
Finished May 19 12:38:42 PM PDT 24
Peak memory 197668 kb
Host smart-8497ea03-7baa-45ad-a2e8-9ced1f5aa0f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248939000 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl
_intg_err.1248939000
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.927396893
Short name T379
Test name
Test status
Simulation time 457016156 ps
CPU time 1.02 seconds
Started May 19 12:39:01 PM PDT 24
Finished May 19 12:39:04 PM PDT 24
Peak memory 195700 kb
Host smart-5b95a476-412e-49db-810f-961320f0e0ae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927396893 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.927396893
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.1563923683
Short name T77
Test name
Test status
Simulation time 355128431 ps
CPU time 0.67 seconds
Started May 19 12:38:59 PM PDT 24
Finished May 19 12:39:01 PM PDT 24
Peak memory 192968 kb
Host smart-c92a06e4-1c18-4156-bc37-8e2d9a0257b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563923683 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.1563923683
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.1064522630
Short name T400
Test name
Test status
Simulation time 377798546 ps
CPU time 0.85 seconds
Started May 19 12:39:08 PM PDT 24
Finished May 19 12:39:10 PM PDT 24
Peak memory 183596 kb
Host smart-ea1c37e9-a7e4-474b-bb37-2559dfcb38e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064522630 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.1064522630
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.2642952386
Short name T94
Test name
Test status
Simulation time 2957569570 ps
CPU time 3.7 seconds
Started May 19 12:38:54 PM PDT 24
Finished May 19 12:38:59 PM PDT 24
Peak memory 194468 kb
Host smart-055cbf43-bde8-482d-8f62-e9910c23c16f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642952386 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon
_timer_same_csr_outstanding.2642952386
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.2746328554
Short name T288
Test name
Test status
Simulation time 399932300 ps
CPU time 1.72 seconds
Started May 19 12:38:47 PM PDT 24
Finished May 19 12:38:50 PM PDT 24
Peak memory 198488 kb
Host smart-a3ab4530-88f4-45bd-bda0-6825ef875fe6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746328554 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.2746328554
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.2810931819
Short name T361
Test name
Test status
Simulation time 8056274141 ps
CPU time 12.64 seconds
Started May 19 12:38:47 PM PDT 24
Finished May 19 12:39:01 PM PDT 24
Peak memory 197972 kb
Host smart-920beba9-177c-4162-b01e-7609a686f8c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810931819 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl
_intg_err.2810931819
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.234086680
Short name T351
Test name
Test status
Simulation time 481933970 ps
CPU time 1.33 seconds
Started May 19 12:38:57 PM PDT 24
Finished May 19 12:39:00 PM PDT 24
Peak memory 196064 kb
Host smart-4c6ed88d-0644-4759-8ffe-2aa3af782289
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234086680 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.234086680
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.4247124624
Short name T337
Test name
Test status
Simulation time 514650902 ps
CPU time 0.95 seconds
Started May 19 12:38:52 PM PDT 24
Finished May 19 12:38:54 PM PDT 24
Peak memory 183504 kb
Host smart-593e7e6b-1dc1-4ea9-b8b8-8102a1821d98
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247124624 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.4247124624
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.3876200903
Short name T298
Test name
Test status
Simulation time 346532293 ps
CPU time 0.81 seconds
Started May 19 12:39:05 PM PDT 24
Finished May 19 12:39:07 PM PDT 24
Peak memory 183544 kb
Host smart-4bc73cda-4498-4af6-8d78-c5fe1043d874
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876200903 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.3876200903
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.2387887085
Short name T360
Test name
Test status
Simulation time 2336581583 ps
CPU time 3.02 seconds
Started May 19 12:39:01 PM PDT 24
Finished May 19 12:39:06 PM PDT 24
Peak memory 183728 kb
Host smart-a7f88710-4ed8-4f99-b533-5bd1f9fc2bd6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387887085 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon
_timer_same_csr_outstanding.2387887085
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.2939916914
Short name T308
Test name
Test status
Simulation time 383893255 ps
CPU time 2.61 seconds
Started May 19 12:38:59 PM PDT 24
Finished May 19 12:39:02 PM PDT 24
Peak memory 198356 kb
Host smart-2d0cebe6-53d3-48be-bc65-65b7e6f1f574
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939916914 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.2939916914
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.1997168248
Short name T127
Test name
Test status
Simulation time 4506148546 ps
CPU time 7.55 seconds
Started May 19 12:38:55 PM PDT 24
Finished May 19 12:39:04 PM PDT 24
Peak memory 197292 kb
Host smart-e37554bf-7e78-4eaa-82aa-8b1dd8fe4825
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997168248 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl
_intg_err.1997168248
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.1204617953
Short name T290
Test name
Test status
Simulation time 451017222 ps
CPU time 0.95 seconds
Started May 19 12:38:54 PM PDT 24
Finished May 19 12:38:57 PM PDT 24
Peak memory 195952 kb
Host smart-c206e9be-0e82-4973-883b-476f041ccbe8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204617953 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.1204617953
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.2892691529
Short name T413
Test name
Test status
Simulation time 525088107 ps
CPU time 1.39 seconds
Started May 19 12:39:12 PM PDT 24
Finished May 19 12:39:14 PM PDT 24
Peak memory 183596 kb
Host smart-070f9087-c8f3-49ff-a1a8-d4241a02ae83
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892691529 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.2892691529
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.3563363792
Short name T309
Test name
Test status
Simulation time 266729897 ps
CPU time 0.91 seconds
Started May 19 12:38:59 PM PDT 24
Finished May 19 12:39:01 PM PDT 24
Peak memory 183492 kb
Host smart-03a5a004-bf0d-439c-a5cf-a0b304f67ea1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563363792 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.3563363792
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.1349101803
Short name T403
Test name
Test status
Simulation time 1122198963 ps
CPU time 4.23 seconds
Started May 19 12:38:58 PM PDT 24
Finished May 19 12:39:03 PM PDT 24
Peak memory 193080 kb
Host smart-98d18576-9adb-446c-8d88-f52b857de12c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349101803 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon
_timer_same_csr_outstanding.1349101803
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.2099566414
Short name T335
Test name
Test status
Simulation time 572550966 ps
CPU time 1.39 seconds
Started May 19 12:38:50 PM PDT 24
Finished May 19 12:38:52 PM PDT 24
Peak memory 198356 kb
Host smart-088c9abc-44bf-47e3-8a6f-6f943e109bcd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099566414 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.2099566414
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.2161723213
Short name T128
Test name
Test status
Simulation time 7835850220 ps
CPU time 7.06 seconds
Started May 19 12:39:01 PM PDT 24
Finished May 19 12:39:11 PM PDT 24
Peak memory 197872 kb
Host smart-04140d54-e91b-4380-8016-190ff3796ee0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161723213 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl
_intg_err.2161723213
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_jump.3606234783
Short name T207
Test name
Test status
Simulation time 602155503 ps
CPU time 0.84 seconds
Started May 19 01:28:42 PM PDT 24
Finished May 19 01:28:46 PM PDT 24
Peak memory 183812 kb
Host smart-36fc8f96-485d-44e5-ac36-43f709a8ea07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606234783 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.3606234783
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.3521982920
Short name T229
Test name
Test status
Simulation time 25307103841 ps
CPU time 11.28 seconds
Started May 19 01:28:45 PM PDT 24
Finished May 19 01:29:00 PM PDT 24
Peak memory 183528 kb
Host smart-b5dc377d-c268-473f-9704-9587b440a7d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521982920 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.3521982920
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.4227593843
Short name T96
Test name
Test status
Simulation time 394937067 ps
CPU time 0.82 seconds
Started May 19 01:28:45 PM PDT 24
Finished May 19 01:28:49 PM PDT 24
Peak memory 183424 kb
Host smart-90af170d-3cdd-4a33-ab3b-3a3e87c3141a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227593843 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.4227593843
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.2924028726
Short name T153
Test name
Test status
Simulation time 100957595171 ps
CPU time 83.64 seconds
Started May 19 01:28:45 PM PDT 24
Finished May 19 01:30:12 PM PDT 24
Peak memory 183500 kb
Host smart-bb571447-2fc4-480f-bfc4-90157f09f2d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924028726 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_a
ll.2924028726
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_jump.2895090535
Short name T272
Test name
Test status
Simulation time 610595871 ps
CPU time 1.15 seconds
Started May 19 01:28:43 PM PDT 24
Finished May 19 01:28:47 PM PDT 24
Peak memory 183432 kb
Host smart-0b5fceee-9d51-45ac-bbeb-86a837f73028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895090535 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.2895090535
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.4213029509
Short name T26
Test name
Test status
Simulation time 22024485559 ps
CPU time 8.31 seconds
Started May 19 01:28:44 PM PDT 24
Finished May 19 01:28:56 PM PDT 24
Peak memory 183556 kb
Host smart-076d117b-3d4a-453c-a8c5-1f6f14094d43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213029509 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.4213029509
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.2123806035
Short name T18
Test name
Test status
Simulation time 8144157315 ps
CPU time 3.83 seconds
Started May 19 01:28:42 PM PDT 24
Finished May 19 01:28:48 PM PDT 24
Peak memory 215480 kb
Host smart-88396554-1bc1-41f0-8004-aa69a24f51a3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123806035 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.2123806035
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.2000568143
Short name T97
Test name
Test status
Simulation time 336170103 ps
CPU time 1.13 seconds
Started May 19 01:28:41 PM PDT 24
Finished May 19 01:28:44 PM PDT 24
Peak memory 183500 kb
Host smart-baa0922d-680b-457f-9bd9-7b8ce40bdc2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000568143 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.2000568143
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.54690141
Short name T260
Test name
Test status
Simulation time 406435184022 ps
CPU time 558.96 seconds
Started May 19 01:28:46 PM PDT 24
Finished May 19 01:38:09 PM PDT 24
Peak memory 193964 kb
Host smart-ea386ed9-4eff-46d7-80c1-a04bda0f9063
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54690141 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all
.54690141
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.255257600
Short name T106
Test name
Test status
Simulation time 360637975367 ps
CPU time 724.61 seconds
Started May 19 01:28:43 PM PDT 24
Finished May 19 01:40:52 PM PDT 24
Peak memory 200804 kb
Host smart-cb36a7af-ba4a-4099-be6b-70e3b768cc6d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255257600 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.255257600
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.aon_timer_jump.3867428353
Short name T206
Test name
Test status
Simulation time 379134212 ps
CPU time 0.7 seconds
Started May 19 01:28:49 PM PDT 24
Finished May 19 01:28:55 PM PDT 24
Peak memory 183484 kb
Host smart-acd43d66-57bb-4244-a416-389d5bde8ed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867428353 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.3867428353
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.3493216834
Short name T151
Test name
Test status
Simulation time 11105257722 ps
CPU time 18.71 seconds
Started May 19 01:28:49 PM PDT 24
Finished May 19 01:29:13 PM PDT 24
Peak memory 191688 kb
Host smart-5d293a41-89ea-41ef-99c8-3a6a95b81cf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493216834 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.3493216834
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.1654914004
Short name T143
Test name
Test status
Simulation time 564627447 ps
CPU time 1.35 seconds
Started May 19 01:28:53 PM PDT 24
Finished May 19 01:29:00 PM PDT 24
Peak memory 183424 kb
Host smart-54d1b480-4b90-4b60-bb27-b1663cc88678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654914004 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.1654914004
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_jump.422515698
Short name T200
Test name
Test status
Simulation time 566005412 ps
CPU time 0.83 seconds
Started May 19 01:28:48 PM PDT 24
Finished May 19 01:28:53 PM PDT 24
Peak memory 183776 kb
Host smart-b998955c-a3bd-4f7f-9083-60cad37859dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422515698 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.422515698
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.2515071590
Short name T226
Test name
Test status
Simulation time 10630422448 ps
CPU time 9.58 seconds
Started May 19 01:28:47 PM PDT 24
Finished May 19 01:29:01 PM PDT 24
Peak memory 183524 kb
Host smart-e8410749-d87f-46af-879c-b8578a3d6617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515071590 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.2515071590
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.2856158525
Short name T170
Test name
Test status
Simulation time 548824270 ps
CPU time 0.82 seconds
Started May 19 01:28:49 PM PDT 24
Finished May 19 01:28:54 PM PDT 24
Peak memory 183484 kb
Host smart-07f63987-b7aa-4dd6-a5c6-987e83edde84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856158525 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.2856158525
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.3715518780
Short name T116
Test name
Test status
Simulation time 10289995779 ps
CPU time 6.3 seconds
Started May 19 01:28:49 PM PDT 24
Finished May 19 01:29:00 PM PDT 24
Peak memory 193008 kb
Host smart-ddd831f7-6f96-44b2-af2f-9ecdd5f13a57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715518780 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_
all.3715518780
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.3559172657
Short name T100
Test name
Test status
Simulation time 85989676398 ps
CPU time 630.98 seconds
Started May 19 01:28:56 PM PDT 24
Finished May 19 01:39:34 PM PDT 24
Peak memory 198392 kb
Host smart-1747772a-2fd0-4cdf-8380-0ee9680a0fb8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559172657 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand_reset.3559172657
Directory /workspace/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.aon_timer_jump.3829096407
Short name T6
Test name
Test status
Simulation time 524112341 ps
CPU time 0.79 seconds
Started May 19 01:28:56 PM PDT 24
Finished May 19 01:29:03 PM PDT 24
Peak memory 183460 kb
Host smart-1e0f5722-4b9d-4832-8ca3-6a3d03be48d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829096407 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.3829096407
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.2749649746
Short name T162
Test name
Test status
Simulation time 17905446767 ps
CPU time 25.13 seconds
Started May 19 01:28:53 PM PDT 24
Finished May 19 01:29:24 PM PDT 24
Peak memory 183484 kb
Host smart-757cddf2-5816-45dc-88a0-d22ecb463c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749649746 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.2749649746
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.1979574675
Short name T269
Test name
Test status
Simulation time 449660626 ps
CPU time 1.29 seconds
Started May 19 01:28:46 PM PDT 24
Finished May 19 01:28:52 PM PDT 24
Peak memory 183472 kb
Host smart-2921e961-fbe0-4e60-a5e8-b43c7106b18e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979574675 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.1979574675
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.3539752367
Short name T188
Test name
Test status
Simulation time 141017007825 ps
CPU time 150.8 seconds
Started May 19 01:28:50 PM PDT 24
Finished May 19 01:31:26 PM PDT 24
Peak memory 193300 kb
Host smart-28740262-8743-4a17-967d-f1c3046dad07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539752367 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_
all.3539752367
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/13.aon_timer_jump.662957416
Short name T222
Test name
Test status
Simulation time 560745953 ps
CPU time 0.75 seconds
Started May 19 01:28:56 PM PDT 24
Finished May 19 01:29:03 PM PDT 24
Peak memory 183428 kb
Host smart-6aaf3db9-edae-4ff3-b7a7-d66ec6d12629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662957416 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.662957416
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.2327196729
Short name T85
Test name
Test status
Simulation time 22958522694 ps
CPU time 31.75 seconds
Started May 19 01:28:44 PM PDT 24
Finished May 19 01:29:20 PM PDT 24
Peak memory 183544 kb
Host smart-2255f756-4d39-458a-9f6a-b3aa0d0df254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327196729 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.2327196729
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.1032162977
Short name T209
Test name
Test status
Simulation time 343501367 ps
CPU time 1.06 seconds
Started May 19 01:28:45 PM PDT 24
Finished May 19 01:28:50 PM PDT 24
Peak memory 183484 kb
Host smart-3c6f50cd-2e79-4076-a080-0bf93611e55b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032162977 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.1032162977
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.1143383480
Short name T149
Test name
Test status
Simulation time 154289937261 ps
CPU time 256.09 seconds
Started May 19 01:28:55 PM PDT 24
Finished May 19 01:33:17 PM PDT 24
Peak memory 194068 kb
Host smart-0cc7e31c-6c51-4205-8c21-476071df30dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143383480 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_
all.1143383480
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.3124053738
Short name T43
Test name
Test status
Simulation time 182390837397 ps
CPU time 392.6 seconds
Started May 19 01:28:56 PM PDT 24
Finished May 19 01:35:35 PM PDT 24
Peak memory 198392 kb
Host smart-5aeeaff8-8220-4c4d-a357-3a2368dc7454
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124053738 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.3124053738
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.1889585516
Short name T259
Test name
Test status
Simulation time 26852954386 ps
CPU time 48.35 seconds
Started May 19 01:28:52 PM PDT 24
Finished May 19 01:29:46 PM PDT 24
Peak memory 191684 kb
Host smart-44402158-3a95-4f53-9f4c-afcf1c288a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889585516 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.1889585516
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.121459667
Short name T2
Test name
Test status
Simulation time 356071620 ps
CPU time 0.66 seconds
Started May 19 01:28:49 PM PDT 24
Finished May 19 01:28:55 PM PDT 24
Peak memory 183428 kb
Host smart-3882af28-d49a-4497-8e54-500b57c868d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121459667 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.121459667
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.794901303
Short name T118
Test name
Test status
Simulation time 371746438802 ps
CPU time 150.92 seconds
Started May 19 01:28:53 PM PDT 24
Finished May 19 01:31:29 PM PDT 24
Peak memory 193480 kb
Host smart-d92d94ee-29c0-4608-944f-1c03e1769b18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794901303 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_a
ll.794901303
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.3144699090
Short name T203
Test name
Test status
Simulation time 117424556349 ps
CPU time 122.42 seconds
Started May 19 01:28:55 PM PDT 24
Finished May 19 01:31:04 PM PDT 24
Peak memory 198460 kb
Host smart-42e5e989-cf87-4e03-994f-69dc5f081192
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144699090 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.3144699090
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.aon_timer_jump.3544261535
Short name T134
Test name
Test status
Simulation time 447053359 ps
CPU time 1.28 seconds
Started May 19 01:28:54 PM PDT 24
Finished May 19 01:29:01 PM PDT 24
Peak memory 183464 kb
Host smart-a1beff89-d400-407d-a16a-91e760511698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544261535 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.3544261535
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.1574871335
Short name T193
Test name
Test status
Simulation time 32541903364 ps
CPU time 54.67 seconds
Started May 19 01:28:53 PM PDT 24
Finished May 19 01:29:53 PM PDT 24
Peak memory 183556 kb
Host smart-daba46c8-4e94-456f-b3b6-1929ee90a33b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574871335 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.1574871335
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.1405795999
Short name T138
Test name
Test status
Simulation time 506574796 ps
CPU time 1.35 seconds
Started May 19 01:28:55 PM PDT 24
Finished May 19 01:29:03 PM PDT 24
Peak memory 183456 kb
Host smart-a7d03bc8-67a2-4623-9e8f-444f47db9049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405795999 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.1405795999
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.3066459603
Short name T55
Test name
Test status
Simulation time 74215649592 ps
CPU time 115.62 seconds
Started May 19 01:28:52 PM PDT 24
Finished May 19 01:30:52 PM PDT 24
Peak memory 194664 kb
Host smart-7146899b-7251-4dc4-affb-643993bc0b4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066459603 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_
all.3066459603
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.2398612244
Short name T109
Test name
Test status
Simulation time 147022784131 ps
CPU time 136.21 seconds
Started May 19 01:28:50 PM PDT 24
Finished May 19 01:31:12 PM PDT 24
Peak memory 198368 kb
Host smart-c81f0060-d1a3-4d1f-8b9e-745a239ecd4f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398612244 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.2398612244
Directory /workspace/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.aon_timer_jump.3949122254
Short name T176
Test name
Test status
Simulation time 553383269 ps
CPU time 1.28 seconds
Started May 19 01:28:56 PM PDT 24
Finished May 19 01:29:03 PM PDT 24
Peak memory 183448 kb
Host smart-9441633c-f0ae-443e-b48a-065717e1061a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949122254 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.3949122254
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.1119038635
Short name T238
Test name
Test status
Simulation time 11048897817 ps
CPU time 17.56 seconds
Started May 19 01:28:56 PM PDT 24
Finished May 19 01:29:21 PM PDT 24
Peak memory 192020 kb
Host smart-b4d15758-ef8f-44b7-9718-6e0a6edd5bdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119038635 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.1119038635
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.3114898005
Short name T180
Test name
Test status
Simulation time 553786150 ps
CPU time 0.65 seconds
Started May 19 01:28:58 PM PDT 24
Finished May 19 01:29:05 PM PDT 24
Peak memory 183492 kb
Host smart-9ecd5c2c-6b7a-48da-aa95-c2c90db99343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114898005 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.3114898005
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.3960472485
Short name T84
Test name
Test status
Simulation time 314549191957 ps
CPU time 228.36 seconds
Started May 19 01:28:51 PM PDT 24
Finished May 19 01:32:44 PM PDT 24
Peak memory 195184 kb
Host smart-7359d023-ff87-4f90-abe7-df6c1c37d7b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960472485 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_
all.3960472485
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/17.aon_timer_jump.3595763246
Short name T276
Test name
Test status
Simulation time 491070373 ps
CPU time 1.3 seconds
Started May 19 01:28:55 PM PDT 24
Finished May 19 01:29:02 PM PDT 24
Peak memory 183432 kb
Host smart-9825597e-fc32-42d2-a340-8be904d6fc47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595763246 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.3595763246
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.2326532833
Short name T195
Test name
Test status
Simulation time 47856064678 ps
CPU time 19.47 seconds
Started May 19 01:28:51 PM PDT 24
Finished May 19 01:29:15 PM PDT 24
Peak memory 183548 kb
Host smart-e8aec65b-10de-41cc-b67a-e3c423160228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326532833 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.2326532833
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.2878430557
Short name T232
Test name
Test status
Simulation time 580933070 ps
CPU time 0.62 seconds
Started May 19 01:28:57 PM PDT 24
Finished May 19 01:29:04 PM PDT 24
Peak memory 183496 kb
Host smart-75fadbac-15f3-4185-b909-1f373f8bde08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878430557 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.2878430557
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.3956907158
Short name T208
Test name
Test status
Simulation time 81895894828 ps
CPU time 70.58 seconds
Started May 19 01:28:54 PM PDT 24
Finished May 19 01:30:10 PM PDT 24
Peak memory 195148 kb
Host smart-fc8ce664-4d30-4edf-a003-e33db46399cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956907158 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_
all.3956907158
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.962401434
Short name T40
Test name
Test status
Simulation time 100236743011 ps
CPU time 192.3 seconds
Started May 19 01:28:55 PM PDT 24
Finished May 19 01:32:13 PM PDT 24
Peak memory 198480 kb
Host smart-8ae7b676-12ef-438e-b346-20612ca3ad2b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962401434 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.962401434
Directory /workspace/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.aon_timer_jump.3756150432
Short name T136
Test name
Test status
Simulation time 533172102 ps
CPU time 1.44 seconds
Started May 19 01:28:52 PM PDT 24
Finished May 19 01:28:59 PM PDT 24
Peak memory 183448 kb
Host smart-4a3cf1b2-c4e0-45fc-8be3-19958d264b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756150432 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.3756150432
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.211063135
Short name T78
Test name
Test status
Simulation time 39178178674 ps
CPU time 14.73 seconds
Started May 19 01:28:55 PM PDT 24
Finished May 19 01:29:16 PM PDT 24
Peak memory 183580 kb
Host smart-60669b61-7b95-4a9e-bb1b-7489f07534b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211063135 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.211063135
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.1518402641
Short name T163
Test name
Test status
Simulation time 363857845 ps
CPU time 1.11 seconds
Started May 19 01:28:53 PM PDT 24
Finished May 19 01:29:00 PM PDT 24
Peak memory 183504 kb
Host smart-a6c0c5dd-1985-4b06-a7ee-7aafd45850cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518402641 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.1518402641
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.352131321
Short name T56
Test name
Test status
Simulation time 43674659976 ps
CPU time 71.46 seconds
Started May 19 01:28:52 PM PDT 24
Finished May 19 01:30:08 PM PDT 24
Peak memory 195552 kb
Host smart-60c28f2a-452a-4d25-a5cb-8d95a5d76b35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352131321 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_a
ll.352131321
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.2457127580
Short name T201
Test name
Test status
Simulation time 95241778413 ps
CPU time 353.74 seconds
Started May 19 01:28:56 PM PDT 24
Finished May 19 01:34:56 PM PDT 24
Peak memory 198428 kb
Host smart-05e40661-bb3c-4ac6-b2a2-fef74f0b61c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457127580 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.2457127580
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.aon_timer_jump.1432113710
Short name T49
Test name
Test status
Simulation time 337221513 ps
CPU time 1.06 seconds
Started May 19 01:28:53 PM PDT 24
Finished May 19 01:28:59 PM PDT 24
Peak memory 183464 kb
Host smart-1ebeef59-d3cf-4cf5-bb13-fd1ec865fe7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432113710 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.1432113710
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.4235776517
Short name T113
Test name
Test status
Simulation time 38416582143 ps
CPU time 10.23 seconds
Started May 19 01:28:58 PM PDT 24
Finished May 19 01:29:15 PM PDT 24
Peak memory 183556 kb
Host smart-f03dd9f4-e8bf-46dc-94bd-0cf76b3b0dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235776517 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.4235776517
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.2992573270
Short name T261
Test name
Test status
Simulation time 516207663 ps
CPU time 0.65 seconds
Started May 19 01:28:52 PM PDT 24
Finished May 19 01:28:58 PM PDT 24
Peak memory 183508 kb
Host smart-511551b0-e01f-469b-93be-f2b0ec487f7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992573270 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.2992573270
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.1217237242
Short name T165
Test name
Test status
Simulation time 197637347518 ps
CPU time 172.76 seconds
Started May 19 01:28:59 PM PDT 24
Finished May 19 01:31:59 PM PDT 24
Peak memory 193836 kb
Host smart-d36985f3-7482-426f-8ca6-b4ab2d41a7cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217237242 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_
all.1217237242
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_jump.3539864654
Short name T48
Test name
Test status
Simulation time 584444821 ps
CPU time 1.5 seconds
Started May 19 01:28:43 PM PDT 24
Finished May 19 01:28:47 PM PDT 24
Peak memory 183504 kb
Host smart-01c29878-3953-43b8-903e-311b636b59d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539864654 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.3539864654
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.2520805822
Short name T44
Test name
Test status
Simulation time 23144480890 ps
CPU time 40.77 seconds
Started May 19 01:28:39 PM PDT 24
Finished May 19 01:29:22 PM PDT 24
Peak memory 183568 kb
Host smart-d8202752-3abd-4dc3-a6db-7ac52a8cc3aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520805822 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.2520805822
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.3299030678
Short name T14
Test name
Test status
Simulation time 4011156454 ps
CPU time 1.92 seconds
Started May 19 01:28:46 PM PDT 24
Finished May 19 01:28:52 PM PDT 24
Peak memory 214768 kb
Host smart-d1c3c81e-694d-4a3d-9f77-9d01547eb609
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299030678 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.3299030678
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.893722571
Short name T161
Test name
Test status
Simulation time 575708980 ps
CPU time 1.31 seconds
Started May 19 01:28:44 PM PDT 24
Finished May 19 01:28:49 PM PDT 24
Peak memory 183496 kb
Host smart-4252a8d4-8596-4747-acf2-e8405a2bd4b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893722571 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.893722571
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.1009313269
Short name T218
Test name
Test status
Simulation time 72139512231 ps
CPU time 16.95 seconds
Started May 19 01:28:46 PM PDT 24
Finished May 19 01:29:08 PM PDT 24
Peak memory 183472 kb
Host smart-3cb13109-74be-405c-aea5-0c7c26565af8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009313269 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_a
ll.1009313269
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.755999701
Short name T233
Test name
Test status
Simulation time 53440318596 ps
CPU time 219.26 seconds
Started May 19 01:28:50 PM PDT 24
Finished May 19 01:32:34 PM PDT 24
Peak memory 198440 kb
Host smart-74164ee9-a5d1-49e5-a0a1-6a1a104fbecf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755999701 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.755999701
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.aon_timer_jump.1197648989
Short name T237
Test name
Test status
Simulation time 481335792 ps
CPU time 0.77 seconds
Started May 19 01:28:52 PM PDT 24
Finished May 19 01:28:58 PM PDT 24
Peak memory 183496 kb
Host smart-14d3f84b-c7a4-4897-b3f6-381cde91e4d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197648989 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.1197648989
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.172547212
Short name T247
Test name
Test status
Simulation time 12629749455 ps
CPU time 20.18 seconds
Started May 19 01:28:53 PM PDT 24
Finished May 19 01:29:19 PM PDT 24
Peak memory 191716 kb
Host smart-90046610-8164-4113-8ef5-23917c1abd3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172547212 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.172547212
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.1782986473
Short name T230
Test name
Test status
Simulation time 382922259 ps
CPU time 0.81 seconds
Started May 19 01:28:51 PM PDT 24
Finished May 19 01:28:56 PM PDT 24
Peak memory 183476 kb
Host smart-8b78273e-2a47-4ac1-b979-f57c5588515b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782986473 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.1782986473
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.1882926087
Short name T280
Test name
Test status
Simulation time 87170061520 ps
CPU time 58.39 seconds
Started May 19 01:29:15 PM PDT 24
Finished May 19 01:30:15 PM PDT 24
Peak memory 183540 kb
Host smart-5bcc9c87-39be-4b4a-8edd-e2af6143650f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882926087 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_
all.1882926087
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.741666938
Short name T182
Test name
Test status
Simulation time 85396573938 ps
CPU time 682.46 seconds
Started May 19 01:28:56 PM PDT 24
Finished May 19 01:40:25 PM PDT 24
Peak memory 200156 kb
Host smart-f396895a-5016-4437-b0e2-75c31ba7ac09
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741666938 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.741666938
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_jump.1697825284
Short name T47
Test name
Test status
Simulation time 625591007 ps
CPU time 1.01 seconds
Started May 19 01:28:55 PM PDT 24
Finished May 19 01:29:02 PM PDT 24
Peak memory 183484 kb
Host smart-bab3f444-e303-4363-83c5-7638fded19e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697825284 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.1697825284
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.1621043543
Short name T189
Test name
Test status
Simulation time 20201439686 ps
CPU time 2.91 seconds
Started May 19 01:28:53 PM PDT 24
Finished May 19 01:29:02 PM PDT 24
Peak memory 191744 kb
Host smart-694b2b88-a4eb-49fb-857b-fe7f08770fe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621043543 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.1621043543
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.2811003271
Short name T241
Test name
Test status
Simulation time 480501501 ps
CPU time 1.27 seconds
Started May 19 01:28:56 PM PDT 24
Finished May 19 01:29:04 PM PDT 24
Peak memory 183460 kb
Host smart-5fedd2c8-05bd-4ede-ae95-e3205efd6bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811003271 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.2811003271
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.1019447826
Short name T273
Test name
Test status
Simulation time 47484391418 ps
CPU time 73.85 seconds
Started May 19 01:28:56 PM PDT 24
Finished May 19 01:30:17 PM PDT 24
Peak memory 183484 kb
Host smart-6d1417d8-0c42-4878-8f74-edf049a7ac68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019447826 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_
all.1019447826
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.513066410
Short name T231
Test name
Test status
Simulation time 833736932560 ps
CPU time 935.53 seconds
Started May 19 01:28:51 PM PDT 24
Finished May 19 01:44:32 PM PDT 24
Peak memory 203552 kb
Host smart-f39005c9-73c9-4832-b80d-8d72e52acc74
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513066410 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.513066410
Directory /workspace/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.aon_timer_jump.1549977044
Short name T95
Test name
Test status
Simulation time 490731601 ps
CPU time 0.94 seconds
Started May 19 01:28:55 PM PDT 24
Finished May 19 01:29:02 PM PDT 24
Peak memory 183488 kb
Host smart-7a080968-e9a0-405d-9b92-be39c9c7a352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549977044 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.1549977044
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.305249594
Short name T219
Test name
Test status
Simulation time 22347249595 ps
CPU time 33.74 seconds
Started May 19 01:28:53 PM PDT 24
Finished May 19 01:29:33 PM PDT 24
Peak memory 183588 kb
Host smart-a62dde12-6f41-4a80-8bb6-020ccbb181f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305249594 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.305249594
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.1308358206
Short name T270
Test name
Test status
Simulation time 352820759 ps
CPU time 1.13 seconds
Started May 19 01:28:50 PM PDT 24
Finished May 19 01:28:56 PM PDT 24
Peak memory 183460 kb
Host smart-34d8e846-d051-440c-ba6d-5f32149f0181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308358206 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.1308358206
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.2911614276
Short name T80
Test name
Test status
Simulation time 59485347235 ps
CPU time 22.67 seconds
Started May 19 01:28:55 PM PDT 24
Finished May 19 01:29:24 PM PDT 24
Peak memory 183532 kb
Host smart-c0039ebd-9c8c-4c45-a07b-939dfda96bc1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911614276 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_
all.2911614276
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.1154805042
Short name T179
Test name
Test status
Simulation time 28845623464 ps
CPU time 125.91 seconds
Started May 19 01:28:52 PM PDT 24
Finished May 19 01:31:03 PM PDT 24
Peak memory 198456 kb
Host smart-e6a2a2a4-d0cd-405e-9229-6a4fbebfd423
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154805042 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.1154805042
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.aon_timer_jump.1955771450
Short name T53
Test name
Test status
Simulation time 470160595 ps
CPU time 0.64 seconds
Started May 19 01:28:57 PM PDT 24
Finished May 19 01:29:04 PM PDT 24
Peak memory 183776 kb
Host smart-c7cf230c-e372-403c-8c17-5ffd44fab68f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955771450 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.1955771450
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.2679302958
Short name T79
Test name
Test status
Simulation time 45228356709 ps
CPU time 20.73 seconds
Started May 19 01:28:54 PM PDT 24
Finished May 19 01:29:21 PM PDT 24
Peak memory 183532 kb
Host smart-048a0bf8-14be-48d1-9857-bfdc41cf9ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679302958 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.2679302958
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.2842561351
Short name T159
Test name
Test status
Simulation time 425632249 ps
CPU time 0.7 seconds
Started May 19 01:28:56 PM PDT 24
Finished May 19 01:29:04 PM PDT 24
Peak memory 183776 kb
Host smart-dd8f347b-eea0-4b1d-870b-839a367015d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842561351 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.2842561351
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.75861768
Short name T144
Test name
Test status
Simulation time 128724281986 ps
CPU time 55.8 seconds
Started May 19 01:28:54 PM PDT 24
Finished May 19 01:29:55 PM PDT 24
Peak memory 183572 kb
Host smart-4cb4fe2e-4769-4953-b977-41d0f24fe893
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75861768 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_al
l.75861768
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.1436084616
Short name T105
Test name
Test status
Simulation time 92546107913 ps
CPU time 333.51 seconds
Started May 19 01:28:55 PM PDT 24
Finished May 19 01:34:35 PM PDT 24
Peak memory 198460 kb
Host smart-ce18ce04-2eca-4374-b391-15082909812b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436084616 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.1436084616
Directory /workspace/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.aon_timer_jump.1050321654
Short name T217
Test name
Test status
Simulation time 467221942 ps
CPU time 0.71 seconds
Started May 19 01:28:54 PM PDT 24
Finished May 19 01:29:01 PM PDT 24
Peak memory 183456 kb
Host smart-1937a397-13f2-4b92-8638-b1cae3807b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050321654 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.1050321654
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.2293446513
Short name T242
Test name
Test status
Simulation time 12759421458 ps
CPU time 16.29 seconds
Started May 19 01:28:51 PM PDT 24
Finished May 19 01:29:12 PM PDT 24
Peak memory 191620 kb
Host smart-f4502600-ae99-4870-ace5-952719dc5fd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293446513 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.2293446513
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.3370072793
Short name T187
Test name
Test status
Simulation time 480226110 ps
CPU time 0.79 seconds
Started May 19 01:28:55 PM PDT 24
Finished May 19 01:29:02 PM PDT 24
Peak memory 183476 kb
Host smart-1a635c69-2d6d-4ee4-b26f-5db9c51c54de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370072793 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.3370072793
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.3278270625
Short name T228
Test name
Test status
Simulation time 232445664427 ps
CPU time 343.73 seconds
Started May 19 01:28:59 PM PDT 24
Finished May 19 01:34:50 PM PDT 24
Peak memory 195220 kb
Host smart-8ddde047-fa71-480f-b08d-12f760422ce3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278270625 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_
all.3278270625
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/25.aon_timer_jump.3960208704
Short name T152
Test name
Test status
Simulation time 453474658 ps
CPU time 0.71 seconds
Started May 19 01:28:59 PM PDT 24
Finished May 19 01:29:07 PM PDT 24
Peak memory 183484 kb
Host smart-6c2e4c33-5f4c-442e-a974-3b04fc6c1a56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960208704 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.3960208704
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.3937763656
Short name T245
Test name
Test status
Simulation time 39250653988 ps
CPU time 67.7 seconds
Started May 19 01:28:59 PM PDT 24
Finished May 19 01:30:14 PM PDT 24
Peak memory 183552 kb
Host smart-ab0e7da9-57d4-4f79-a5e0-9ffb52861c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937763656 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.3937763656
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.1699430381
Short name T257
Test name
Test status
Simulation time 464197450 ps
CPU time 0.62 seconds
Started May 19 01:28:54 PM PDT 24
Finished May 19 01:29:01 PM PDT 24
Peak memory 183484 kb
Host smart-f41ea1cf-6f63-4f0d-bb69-3bfdbfac9190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699430381 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.1699430381
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.813628129
Short name T25
Test name
Test status
Simulation time 137187218539 ps
CPU time 152.76 seconds
Started May 19 01:28:55 PM PDT 24
Finished May 19 01:31:34 PM PDT 24
Peak memory 191752 kb
Host smart-51950e1a-3727-44e3-bd77-ce6c3215297b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813628129 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_a
ll.813628129
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.21532853
Short name T108
Test name
Test status
Simulation time 91638912525 ps
CPU time 346.57 seconds
Started May 19 01:28:53 PM PDT 24
Finished May 19 01:34:45 PM PDT 24
Peak memory 198364 kb
Host smart-6a11eecf-e16c-45a9-89fb-21c5feae87ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21532853 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.21532853
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.aon_timer_jump.1534683219
Short name T216
Test name
Test status
Simulation time 466524282 ps
CPU time 0.77 seconds
Started May 19 01:28:55 PM PDT 24
Finished May 19 01:29:02 PM PDT 24
Peak memory 183496 kb
Host smart-8de83b87-66a3-4655-bc52-156e96a29770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534683219 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.1534683219
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.4105570387
Short name T22
Test name
Test status
Simulation time 9997656901 ps
CPU time 15.81 seconds
Started May 19 01:28:59 PM PDT 24
Finished May 19 01:29:21 PM PDT 24
Peak memory 191760 kb
Host smart-104e8544-c7c2-462e-a413-20e5e16a4d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105570387 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.4105570387
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.2357998481
Short name T251
Test name
Test status
Simulation time 544569210 ps
CPU time 0.94 seconds
Started May 19 01:28:57 PM PDT 24
Finished May 19 01:29:04 PM PDT 24
Peak memory 183492 kb
Host smart-69861900-6855-4127-8256-be6880b12b13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357998481 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.2357998481
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.1095416389
Short name T271
Test name
Test status
Simulation time 197171431064 ps
CPU time 23.41 seconds
Started May 19 01:28:57 PM PDT 24
Finished May 19 01:29:27 PM PDT 24
Peak memory 194088 kb
Host smart-d89d5e69-a70e-4f57-9e10-69a0cae0ac1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095416389 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_
all.1095416389
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.1788857733
Short name T11
Test name
Test status
Simulation time 210372553646 ps
CPU time 449.9 seconds
Started May 19 01:28:59 PM PDT 24
Finished May 19 01:36:35 PM PDT 24
Peak memory 198688 kb
Host smart-5df55660-a270-4969-8045-61c6719cf57d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788857733 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.1788857733
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_jump.395184929
Short name T248
Test name
Test status
Simulation time 514577043 ps
CPU time 1.35 seconds
Started May 19 01:28:59 PM PDT 24
Finished May 19 01:29:06 PM PDT 24
Peak memory 183496 kb
Host smart-414d71fc-3bbb-4834-af5c-0757b8886bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395184929 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.395184929
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.537353980
Short name T120
Test name
Test status
Simulation time 47775648724 ps
CPU time 80.85 seconds
Started May 19 01:28:55 PM PDT 24
Finished May 19 01:30:22 PM PDT 24
Peak memory 191732 kb
Host smart-013b462a-7c4d-4de1-8c1b-da8545a3ae2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537353980 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.537353980
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.1826635778
Short name T196
Test name
Test status
Simulation time 586200725 ps
CPU time 0.63 seconds
Started May 19 01:28:58 PM PDT 24
Finished May 19 01:29:05 PM PDT 24
Peak memory 183488 kb
Host smart-45f500ea-59bc-47fd-b574-150cd8419eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826635778 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.1826635778
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.2498639150
Short name T81
Test name
Test status
Simulation time 29294392382 ps
CPU time 244.4 seconds
Started May 19 01:28:59 PM PDT 24
Finished May 19 01:33:10 PM PDT 24
Peak memory 198476 kb
Host smart-15f6171a-6f70-4139-b13e-65d018625124
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498639150 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.2498639150
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_jump.1894071641
Short name T202
Test name
Test status
Simulation time 419916875 ps
CPU time 1.25 seconds
Started May 19 01:28:58 PM PDT 24
Finished May 19 01:29:05 PM PDT 24
Peak memory 183424 kb
Host smart-865f506f-c7bf-44d2-bae3-b6a615801170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894071641 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.1894071641
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.525279678
Short name T46
Test name
Test status
Simulation time 37689333532 ps
CPU time 60.03 seconds
Started May 19 01:28:58 PM PDT 24
Finished May 19 01:30:04 PM PDT 24
Peak memory 183564 kb
Host smart-20232438-0082-47b3-863a-52f18681f217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525279678 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.525279678
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.3840898733
Short name T4
Test name
Test status
Simulation time 519439277 ps
CPU time 0.79 seconds
Started May 19 01:28:58 PM PDT 24
Finished May 19 01:29:05 PM PDT 24
Peak memory 183808 kb
Host smart-f29e0afe-e55e-4e0d-a1eb-5a2994d4ec47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840898733 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.3840898733
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.1808114279
Short name T145
Test name
Test status
Simulation time 50679404922 ps
CPU time 20.03 seconds
Started May 19 01:29:00 PM PDT 24
Finished May 19 01:29:26 PM PDT 24
Peak memory 195348 kb
Host smart-2bce41af-db24-421f-b405-ab0cd672e0fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808114279 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_
all.1808114279
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.1780272796
Short name T51
Test name
Test status
Simulation time 73115773163 ps
CPU time 601.6 seconds
Started May 19 01:29:01 PM PDT 24
Finished May 19 01:39:09 PM PDT 24
Peak memory 198488 kb
Host smart-330fa6fe-980f-4dd3-99c9-ce92f4faba5a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780272796 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.1780272796
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.aon_timer_jump.1782218815
Short name T215
Test name
Test status
Simulation time 463230504 ps
CPU time 0.78 seconds
Started May 19 01:28:58 PM PDT 24
Finished May 19 01:29:05 PM PDT 24
Peak memory 183484 kb
Host smart-0eeb0bb8-2609-480c-9827-4ade35210c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782218815 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.1782218815
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.69939836
Short name T239
Test name
Test status
Simulation time 24247515129 ps
CPU time 2.99 seconds
Started May 19 01:28:57 PM PDT 24
Finished May 19 01:29:06 PM PDT 24
Peak memory 183540 kb
Host smart-c28a6c72-7af1-45b3-aa89-bbaa2ab32d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69939836 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.69939836
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.4123617853
Short name T139
Test name
Test status
Simulation time 566792097 ps
CPU time 1.33 seconds
Started May 19 01:28:56 PM PDT 24
Finished May 19 01:29:04 PM PDT 24
Peak memory 183468 kb
Host smart-e7101726-8b83-4668-9d86-d184c5fc5247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123617853 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.4123617853
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.1224143036
Short name T178
Test name
Test status
Simulation time 37523478217 ps
CPU time 13.13 seconds
Started May 19 01:28:58 PM PDT 24
Finished May 19 01:29:17 PM PDT 24
Peak memory 193968 kb
Host smart-3a0ddb04-0a8b-4039-ae56-648f0487b2fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224143036 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_
all.1224143036
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.519415648
Short name T104
Test name
Test status
Simulation time 25717849742 ps
CPU time 185.82 seconds
Started May 19 01:28:56 PM PDT 24
Finished May 19 01:32:08 PM PDT 24
Peak memory 198484 kb
Host smart-401af166-cae5-454a-83f5-73a5cb35b293
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519415648 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.519415648
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.aon_timer_jump.1798264188
Short name T267
Test name
Test status
Simulation time 515502146 ps
CPU time 1.42 seconds
Started May 19 01:28:46 PM PDT 24
Finished May 19 01:28:51 PM PDT 24
Peak memory 183488 kb
Host smart-f52967ed-1205-4929-bd67-6bd01856976d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798264188 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.1798264188
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.1982392254
Short name T20
Test name
Test status
Simulation time 21174644046 ps
CPU time 25.78 seconds
Started May 19 01:28:50 PM PDT 24
Finished May 19 01:29:21 PM PDT 24
Peak memory 183552 kb
Host smart-309df9c2-85c1-41b4-a437-9293e23ae46e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982392254 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.1982392254
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.3190140686
Short name T17
Test name
Test status
Simulation time 8064963279 ps
CPU time 7.39 seconds
Started May 19 01:28:47 PM PDT 24
Finished May 19 01:28:58 PM PDT 24
Peak memory 215740 kb
Host smart-374e8558-20a0-49f1-8aac-3af7fa56f8ad
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190140686 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.3190140686
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.671012643
Short name T137
Test name
Test status
Simulation time 501924558 ps
CPU time 1.45 seconds
Started May 19 01:28:48 PM PDT 24
Finished May 19 01:28:53 PM PDT 24
Peak memory 183432 kb
Host smart-4c84ad2e-7ec3-4060-bb44-032866d7b7a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671012643 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.671012643
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_jump.3288323651
Short name T221
Test name
Test status
Simulation time 457127833 ps
CPU time 0.61 seconds
Started May 19 01:28:56 PM PDT 24
Finished May 19 01:29:03 PM PDT 24
Peak memory 183752 kb
Host smart-e704f49a-b2f5-47a5-bb2e-82e8b5f00bce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288323651 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.3288323651
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.1823632809
Short name T166
Test name
Test status
Simulation time 13881531143 ps
CPU time 11.98 seconds
Started May 19 01:28:58 PM PDT 24
Finished May 19 01:29:17 PM PDT 24
Peak memory 183868 kb
Host smart-a46d0bbe-a159-44b9-9633-3765d1c450d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823632809 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.1823632809
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.1142223344
Short name T112
Test name
Test status
Simulation time 471012412 ps
CPU time 0.76 seconds
Started May 19 01:28:59 PM PDT 24
Finished May 19 01:29:07 PM PDT 24
Peak memory 183460 kb
Host smart-afc6a2a2-a124-4a5a-8602-0fe3af495454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142223344 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.1142223344
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.4172572838
Short name T243
Test name
Test status
Simulation time 87622429628 ps
CPU time 29.99 seconds
Started May 19 01:28:58 PM PDT 24
Finished May 19 01:29:35 PM PDT 24
Peak memory 195112 kb
Host smart-141fa924-ea39-4d9e-bac2-15f95432c6ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172572838 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_
all.4172572838
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_jump.1517937089
Short name T211
Test name
Test status
Simulation time 423033155 ps
CPU time 0.71 seconds
Started May 19 01:28:59 PM PDT 24
Finished May 19 01:29:06 PM PDT 24
Peak memory 183496 kb
Host smart-dbbab09e-06eb-4032-afa9-43116285a4bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517937089 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.1517937089
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.1234399228
Short name T122
Test name
Test status
Simulation time 36619297090 ps
CPU time 7.25 seconds
Started May 19 01:28:58 PM PDT 24
Finished May 19 01:29:12 PM PDT 24
Peak memory 183560 kb
Host smart-23cb2ccc-679f-4d22-a3e1-595bcbf54311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234399228 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.1234399228
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.1291003789
Short name T140
Test name
Test status
Simulation time 446250443 ps
CPU time 0.99 seconds
Started May 19 01:28:59 PM PDT 24
Finished May 19 01:29:06 PM PDT 24
Peak memory 183496 kb
Host smart-0be7be82-4edc-481a-af93-ed1a03d9a2d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291003789 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.1291003789
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.524858895
Short name T281
Test name
Test status
Simulation time 266542673347 ps
CPU time 332.73 seconds
Started May 19 01:28:59 PM PDT 24
Finished May 19 01:34:38 PM PDT 24
Peak memory 191764 kb
Host smart-89a60270-2aba-40a7-a672-bc55af582fb1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524858895 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_a
ll.524858895
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/32.aon_timer_jump.370993099
Short name T274
Test name
Test status
Simulation time 409349835 ps
CPU time 0.84 seconds
Started May 19 01:29:01 PM PDT 24
Finished May 19 01:29:07 PM PDT 24
Peak memory 183464 kb
Host smart-a5cfa714-7a30-4770-a789-fa1d09370b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370993099 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.370993099
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.2300375024
Short name T240
Test name
Test status
Simulation time 18352371380 ps
CPU time 7.94 seconds
Started May 19 01:29:04 PM PDT 24
Finished May 19 01:29:16 PM PDT 24
Peak memory 183496 kb
Host smart-7c945cc8-a937-463d-bf9e-4e9addd77418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300375024 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.2300375024
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.4268254407
Short name T236
Test name
Test status
Simulation time 377132761 ps
CPU time 1.23 seconds
Started May 19 01:28:58 PM PDT 24
Finished May 19 01:29:06 PM PDT 24
Peak memory 183492 kb
Host smart-2963bce5-c501-4bc5-a4a5-187c36b28f80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268254407 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.4268254407
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.2204596196
Short name T5
Test name
Test status
Simulation time 480220746277 ps
CPU time 101.17 seconds
Started May 19 01:29:05 PM PDT 24
Finished May 19 01:30:50 PM PDT 24
Peak memory 183536 kb
Host smart-66f5e626-2d95-4fa9-90f2-59dc00426867
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204596196 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_
all.2204596196
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.1642990832
Short name T263
Test name
Test status
Simulation time 41851827065 ps
CPU time 440.73 seconds
Started May 19 01:29:03 PM PDT 24
Finished May 19 01:36:29 PM PDT 24
Peak memory 198424 kb
Host smart-2ae9c521-1e95-4047-8598-a52b2a578542
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642990832 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_reset.1642990832
Directory /workspace/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.aon_timer_jump.2326805308
Short name T160
Test name
Test status
Simulation time 353913117 ps
CPU time 0.88 seconds
Started May 19 01:29:05 PM PDT 24
Finished May 19 01:29:09 PM PDT 24
Peak memory 183484 kb
Host smart-79a6f0d3-9577-4315-8a69-05af5011cadb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326805308 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.2326805308
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.8680678
Short name T190
Test name
Test status
Simulation time 11931283228 ps
CPU time 20.73 seconds
Started May 19 01:29:05 PM PDT 24
Finished May 19 01:29:29 PM PDT 24
Peak memory 183504 kb
Host smart-4d6e2639-6b2a-4ed4-b174-f282c819411a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8680678 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.8680678
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.46482167
Short name T52
Test name
Test status
Simulation time 450431097 ps
CPU time 0.68 seconds
Started May 19 01:29:02 PM PDT 24
Finished May 19 01:29:08 PM PDT 24
Peak memory 183500 kb
Host smart-d37b1288-8bb4-4128-9f54-d84298314c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46482167 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.46482167
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.1690621576
Short name T155
Test name
Test status
Simulation time 80331862670 ps
CPU time 57.28 seconds
Started May 19 01:29:05 PM PDT 24
Finished May 19 01:30:05 PM PDT 24
Peak memory 183516 kb
Host smart-7a6a2d02-4955-4897-9f4a-6788491f2c01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690621576 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_
all.1690621576
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.1185434139
Short name T83
Test name
Test status
Simulation time 362303079398 ps
CPU time 287.73 seconds
Started May 19 01:29:01 PM PDT 24
Finished May 19 01:33:54 PM PDT 24
Peak memory 206660 kb
Host smart-d2d6a00b-3374-4292-96b3-d5e948ca2bd3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185434139 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.1185434139
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.aon_timer_jump.1923631853
Short name T135
Test name
Test status
Simulation time 370432273 ps
CPU time 1.17 seconds
Started May 19 01:29:04 PM PDT 24
Finished May 19 01:29:09 PM PDT 24
Peak memory 183432 kb
Host smart-0d6eafb2-4f60-4e06-a1b2-eccb3c6bc088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923631853 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.1923631853
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.4112361162
Short name T250
Test name
Test status
Simulation time 10229197641 ps
CPU time 13.47 seconds
Started May 19 01:29:04 PM PDT 24
Finished May 19 01:29:21 PM PDT 24
Peak memory 183500 kb
Host smart-94c2982b-594f-4b6a-9ea8-a349b6262544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112361162 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.4112361162
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.3366727117
Short name T169
Test name
Test status
Simulation time 540560568 ps
CPU time 1.37 seconds
Started May 19 01:29:02 PM PDT 24
Finished May 19 01:29:08 PM PDT 24
Peak memory 183464 kb
Host smart-a511e522-d852-4d28-8dae-7d5d0de3bcde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366727117 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.3366727117
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.1309026243
Short name T121
Test name
Test status
Simulation time 261297952827 ps
CPU time 213.95 seconds
Started May 19 01:29:03 PM PDT 24
Finished May 19 01:32:41 PM PDT 24
Peak memory 183784 kb
Host smart-cf0c3b99-517b-4d72-a6ab-134a0af821bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309026243 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_
all.1309026243
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.2117309330
Short name T62
Test name
Test status
Simulation time 20368339693 ps
CPU time 215.96 seconds
Started May 19 01:29:02 PM PDT 24
Finished May 19 01:32:43 PM PDT 24
Peak memory 198448 kb
Host smart-7e2c423c-8ad1-4ebf-968c-1da5df43b69c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117309330 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.2117309330
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.aon_timer_jump.4162427883
Short name T45
Test name
Test status
Simulation time 460327937 ps
CPU time 0.92 seconds
Started May 19 01:29:03 PM PDT 24
Finished May 19 01:29:09 PM PDT 24
Peak memory 183396 kb
Host smart-aa875538-6f72-41ec-a011-75037a7b9229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162427883 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.4162427883
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.1162606112
Short name T177
Test name
Test status
Simulation time 46034642933 ps
CPU time 10.48 seconds
Started May 19 01:28:59 PM PDT 24
Finished May 19 01:29:16 PM PDT 24
Peak memory 191764 kb
Host smart-1183b29c-dd6d-4b19-b13b-fdbb6a03eafb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162606112 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.1162606112
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.740394376
Short name T255
Test name
Test status
Simulation time 643548099 ps
CPU time 0.63 seconds
Started May 19 01:29:05 PM PDT 24
Finished May 19 01:29:09 PM PDT 24
Peak memory 183444 kb
Host smart-bf055ba3-ef3e-4f7d-8e88-0ad5bdd73eaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740394376 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.740394376
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.98466573
Short name T148
Test name
Test status
Simulation time 184959862388 ps
CPU time 304.89 seconds
Started May 19 01:29:03 PM PDT 24
Finished May 19 01:34:12 PM PDT 24
Peak memory 195680 kb
Host smart-d58064c9-f0ea-4755-b8f2-d1720efbfe45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98466573 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_al
l.98466573
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.1175637760
Short name T42
Test name
Test status
Simulation time 33318850055 ps
CPU time 164.9 seconds
Started May 19 01:29:05 PM PDT 24
Finished May 19 01:31:54 PM PDT 24
Peak memory 198468 kb
Host smart-51e1fe44-0c1e-48b2-afda-3e988de770c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175637760 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.1175637760
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.aon_timer_jump.219672735
Short name T244
Test name
Test status
Simulation time 510684818 ps
CPU time 1.35 seconds
Started May 19 01:29:02 PM PDT 24
Finished May 19 01:29:08 PM PDT 24
Peak memory 183480 kb
Host smart-e6d77652-7699-469f-8aec-b07444b48176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219672735 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.219672735
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.1786798115
Short name T227
Test name
Test status
Simulation time 35102426116 ps
CPU time 49.16 seconds
Started May 19 01:29:02 PM PDT 24
Finished May 19 01:29:56 PM PDT 24
Peak memory 183552 kb
Host smart-7c36df19-0606-4946-9a89-601bc17b4cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786798115 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.1786798115
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.1539635770
Short name T167
Test name
Test status
Simulation time 573123333 ps
CPU time 0.96 seconds
Started May 19 01:29:01 PM PDT 24
Finished May 19 01:29:08 PM PDT 24
Peak memory 183448 kb
Host smart-0cdc6ddb-a16c-4867-8271-fa661b28d784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539635770 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.1539635770
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.3755253615
Short name T256
Test name
Test status
Simulation time 96764194353 ps
CPU time 154.64 seconds
Started May 19 01:29:01 PM PDT 24
Finished May 19 01:31:41 PM PDT 24
Peak memory 183724 kb
Host smart-4be24a29-eb02-4b24-9272-f0860bad8bac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755253615 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_
all.3755253615
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.1279961246
Short name T61
Test name
Test status
Simulation time 156038911979 ps
CPU time 256.21 seconds
Started May 19 01:29:01 PM PDT 24
Finished May 19 01:33:23 PM PDT 24
Peak memory 198584 kb
Host smart-4d32162c-ceae-4417-b936-d4dc18cb510e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279961246 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.1279961246
Directory /workspace/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.aon_timer_jump.3464290160
Short name T258
Test name
Test status
Simulation time 419489591 ps
CPU time 1.18 seconds
Started May 19 01:29:06 PM PDT 24
Finished May 19 01:29:10 PM PDT 24
Peak memory 183452 kb
Host smart-0fedcba7-6337-4078-8b3a-d461d44d11df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464290160 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.3464290160
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.2208659846
Short name T164
Test name
Test status
Simulation time 29190535799 ps
CPU time 11.23 seconds
Started May 19 01:29:01 PM PDT 24
Finished May 19 01:29:18 PM PDT 24
Peak memory 183564 kb
Host smart-bb1f5d42-1823-49ea-bc2d-d88f1ea01acc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208659846 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.2208659846
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.2463360378
Short name T268
Test name
Test status
Simulation time 581611894 ps
CPU time 1.31 seconds
Started May 19 01:29:02 PM PDT 24
Finished May 19 01:29:09 PM PDT 24
Peak memory 183492 kb
Host smart-dc36fa1a-4f6b-4aef-ba8e-7023c6906f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463360378 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.2463360378
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.759949932
Short name T99
Test name
Test status
Simulation time 50192819086 ps
CPU time 232.45 seconds
Started May 19 01:29:03 PM PDT 24
Finished May 19 01:33:00 PM PDT 24
Peak memory 198460 kb
Host smart-94579e05-2f0a-4a37-b8cc-b5c8689391c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759949932 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.759949932
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.aon_timer_jump.1796689327
Short name T29
Test name
Test status
Simulation time 492155054 ps
CPU time 0.76 seconds
Started May 19 01:29:08 PM PDT 24
Finished May 19 01:29:11 PM PDT 24
Peak memory 183388 kb
Host smart-ea2ddc97-d96e-4e7c-8b54-8d155ac66060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796689327 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.1796689327
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.536973161
Short name T205
Test name
Test status
Simulation time 59435744645 ps
CPU time 15.04 seconds
Started May 19 01:29:08 PM PDT 24
Finished May 19 01:29:25 PM PDT 24
Peak memory 183140 kb
Host smart-4266c377-a9e5-4580-90c4-d7c50c5bac33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536973161 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.536973161
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.2138405537
Short name T86
Test name
Test status
Simulation time 505155618 ps
CPU time 1.26 seconds
Started May 19 01:29:08 PM PDT 24
Finished May 19 01:29:11 PM PDT 24
Peak memory 183480 kb
Host smart-29738490-e55c-40d3-bb7e-a43385ce4141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138405537 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.2138405537
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.2678482884
Short name T252
Test name
Test status
Simulation time 626780757456 ps
CPU time 208.79 seconds
Started May 19 01:29:09 PM PDT 24
Finished May 19 01:32:39 PM PDT 24
Peak memory 195188 kb
Host smart-f9ffc2ea-189d-44c2-aa11-f82845df936c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678482884 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_
all.2678482884
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.712462172
Short name T214
Test name
Test status
Simulation time 76376340158 ps
CPU time 855.42 seconds
Started May 19 01:29:08 PM PDT 24
Finished May 19 01:43:25 PM PDT 24
Peak memory 202648 kb
Host smart-ee998fa3-a77b-4995-b343-5eebfbe44c85
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712462172 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand_reset.712462172
Directory /workspace/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.aon_timer_jump.383741085
Short name T220
Test name
Test status
Simulation time 369761061 ps
CPU time 0.83 seconds
Started May 19 01:29:06 PM PDT 24
Finished May 19 01:29:10 PM PDT 24
Peak memory 183372 kb
Host smart-a105f370-43ac-4500-97e3-00059d95c05f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383741085 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.383741085
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.1292989584
Short name T8
Test name
Test status
Simulation time 14372051087 ps
CPU time 3.81 seconds
Started May 19 01:29:07 PM PDT 24
Finished May 19 01:29:13 PM PDT 24
Peak memory 183572 kb
Host smart-9f4be273-f055-4e55-af76-d942196189de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292989584 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.1292989584
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.1713969174
Short name T197
Test name
Test status
Simulation time 544202350 ps
CPU time 1.44 seconds
Started May 19 01:29:07 PM PDT 24
Finished May 19 01:29:11 PM PDT 24
Peak memory 183492 kb
Host smart-80175d59-0d8f-44b8-9279-045aa61edd22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713969174 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.1713969174
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.3655163897
Short name T35
Test name
Test status
Simulation time 53269847655 ps
CPU time 85.98 seconds
Started May 19 01:29:08 PM PDT 24
Finished May 19 01:30:36 PM PDT 24
Peak memory 183192 kb
Host smart-655a2867-1b62-4eb9-b501-cd4c703bd5ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655163897 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_
all.3655163897
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.96524780
Short name T12
Test name
Test status
Simulation time 110187513000 ps
CPU time 252.02 seconds
Started May 19 01:29:08 PM PDT 24
Finished May 19 01:33:22 PM PDT 24
Peak memory 198316 kb
Host smart-6ffd5987-c3bc-4d1f-9bf4-15c8488fab60
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96524780 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.96524780
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_jump.1265271431
Short name T114
Test name
Test status
Simulation time 507957553 ps
CPU time 0.97 seconds
Started May 19 01:28:46 PM PDT 24
Finished May 19 01:28:50 PM PDT 24
Peak memory 183496 kb
Host smart-6bd49786-2e63-4525-9758-a83ac1a6115c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265271431 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.1265271431
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.1021971535
Short name T54
Test name
Test status
Simulation time 33609877913 ps
CPU time 14.79 seconds
Started May 19 01:28:44 PM PDT 24
Finished May 19 01:29:03 PM PDT 24
Peak memory 183440 kb
Host smart-d26b8553-45ac-42f7-96ae-0d41634c6508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021971535 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.1021971535
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.3067840825
Short name T13
Test name
Test status
Simulation time 4056595330 ps
CPU time 2.15 seconds
Started May 19 01:28:46 PM PDT 24
Finished May 19 01:28:53 PM PDT 24
Peak memory 214812 kb
Host smart-c3def6d2-fc60-462b-8052-8f5ce1b488b5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067840825 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.3067840825
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.2334336114
Short name T1
Test name
Test status
Simulation time 391550746 ps
CPU time 0.66 seconds
Started May 19 01:28:46 PM PDT 24
Finished May 19 01:28:50 PM PDT 24
Peak memory 183460 kb
Host smart-25cb9a85-2722-44fb-aa16-2cd75b4ce7ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334336114 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.2334336114
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.3202320075
Short name T142
Test name
Test status
Simulation time 68026938427 ps
CPU time 53.67 seconds
Started May 19 01:28:46 PM PDT 24
Finished May 19 01:29:44 PM PDT 24
Peak memory 183500 kb
Host smart-1b377339-2ddf-4e6c-8878-43a6d085b99e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202320075 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_a
ll.3202320075
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.3934556068
Short name T156
Test name
Test status
Simulation time 139467995163 ps
CPU time 250.58 seconds
Started May 19 01:28:49 PM PDT 24
Finished May 19 01:33:04 PM PDT 24
Peak memory 206668 kb
Host smart-b9e3fd47-5a31-4265-90b1-d83c9892b780
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934556068 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.3934556068
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.aon_timer_jump.8308738
Short name T199
Test name
Test status
Simulation time 391081859 ps
CPU time 0.76 seconds
Started May 19 01:29:07 PM PDT 24
Finished May 19 01:29:10 PM PDT 24
Peak memory 183460 kb
Host smart-41b508e1-a6cf-4fa4-89ce-3ef59ef9db13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8308738 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.8308738
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.2437101755
Short name T183
Test name
Test status
Simulation time 1521489376 ps
CPU time 2.77 seconds
Started May 19 01:29:08 PM PDT 24
Finished May 19 01:29:13 PM PDT 24
Peak memory 183464 kb
Host smart-21ee31a6-f333-4af5-a142-ac34c68574c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437101755 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.2437101755
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.1337464630
Short name T10
Test name
Test status
Simulation time 445939085 ps
CPU time 0.91 seconds
Started May 19 01:29:08 PM PDT 24
Finished May 19 01:29:11 PM PDT 24
Peak memory 183496 kb
Host smart-d8369974-b45c-4555-afd5-74dc8f8ee9c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337464630 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.1337464630
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.62490427
Short name T278
Test name
Test status
Simulation time 140319871832 ps
CPU time 62.7 seconds
Started May 19 01:29:08 PM PDT 24
Finished May 19 01:30:13 PM PDT 24
Peak memory 194816 kb
Host smart-42cca63a-740c-4de4-b051-ed27595b7c42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62490427 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_al
l.62490427
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_jump.1183949162
Short name T234
Test name
Test status
Simulation time 474756405 ps
CPU time 0.76 seconds
Started May 19 01:29:09 PM PDT 24
Finished May 19 01:29:11 PM PDT 24
Peak memory 183804 kb
Host smart-8ac5614f-e0fa-4d1d-bfde-3a1bb4176d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183949162 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.1183949162
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.221221664
Short name T27
Test name
Test status
Simulation time 44271669914 ps
CPU time 5.79 seconds
Started May 19 01:29:08 PM PDT 24
Finished May 19 01:29:16 PM PDT 24
Peak memory 191740 kb
Host smart-016a5b90-7921-42ca-9d14-34b41472f189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221221664 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.221221664
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.4249694771
Short name T185
Test name
Test status
Simulation time 471734495 ps
CPU time 0.57 seconds
Started May 19 01:29:06 PM PDT 24
Finished May 19 01:29:09 PM PDT 24
Peak memory 183492 kb
Host smart-96f756e9-2bdc-4965-b52c-4a4b3ad2e334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249694771 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.4249694771
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.206394686
Short name T277
Test name
Test status
Simulation time 142560739296 ps
CPU time 230.23 seconds
Started May 19 01:29:12 PM PDT 24
Finished May 19 01:33:04 PM PDT 24
Peak memory 183552 kb
Host smart-cc93813e-9a62-4e18-b41f-f5720dd73d71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206394686 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_a
ll.206394686
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.1897005567
Short name T103
Test name
Test status
Simulation time 26017041557 ps
CPU time 119.13 seconds
Started May 19 01:29:12 PM PDT 24
Finished May 19 01:31:12 PM PDT 24
Peak memory 198512 kb
Host smart-f1e73b5d-546e-4ab1-a20a-d2c4d6f3a8bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897005567 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.1897005567
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.aon_timer_jump.110430065
Short name T265
Test name
Test status
Simulation time 469346250 ps
CPU time 0.91 seconds
Started May 19 01:29:14 PM PDT 24
Finished May 19 01:29:16 PM PDT 24
Peak memory 183452 kb
Host smart-1f82c248-8772-4c75-ba13-89835e97c0ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110430065 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.110430065
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.727910171
Short name T7
Test name
Test status
Simulation time 24249521866 ps
CPU time 8.23 seconds
Started May 19 01:29:15 PM PDT 24
Finished May 19 01:29:24 PM PDT 24
Peak memory 183504 kb
Host smart-393a9ce2-c638-43f9-af6e-c5b953c360d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727910171 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.727910171
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.257610402
Short name T246
Test name
Test status
Simulation time 371476220 ps
CPU time 1.16 seconds
Started May 19 01:29:24 PM PDT 24
Finished May 19 01:29:27 PM PDT 24
Peak memory 183356 kb
Host smart-fa2b7484-daec-4a0f-bf2a-d224f9c130d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257610402 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.257610402
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.965937851
Short name T279
Test name
Test status
Simulation time 392744467031 ps
CPU time 347.44 seconds
Started May 19 01:29:11 PM PDT 24
Finished May 19 01:34:59 PM PDT 24
Peak memory 195832 kb
Host smart-e6289c89-7d4f-4a78-89e9-52105c73a9f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965937851 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_a
ll.965937851
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.3184676917
Short name T98
Test name
Test status
Simulation time 81038534049 ps
CPU time 172.81 seconds
Started May 19 01:29:12 PM PDT 24
Finished May 19 01:32:07 PM PDT 24
Peak memory 198468 kb
Host smart-f3a88ed5-f8d6-41a2-a944-c233633950aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184676917 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.3184676917
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.aon_timer_jump.51415514
Short name T147
Test name
Test status
Simulation time 471165664 ps
CPU time 0.92 seconds
Started May 19 01:29:24 PM PDT 24
Finished May 19 01:29:27 PM PDT 24
Peak memory 183356 kb
Host smart-ea191523-7ccb-4619-8963-5f40072e8388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51415514 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.51415514
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.3964224605
Short name T224
Test name
Test status
Simulation time 37248030291 ps
CPU time 9.69 seconds
Started May 19 01:29:24 PM PDT 24
Finished May 19 01:29:36 PM PDT 24
Peak memory 183404 kb
Host smart-dae30364-4cda-4029-9b37-4a26442e7225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964224605 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.3964224605
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.3243956028
Short name T19
Test name
Test status
Simulation time 428279118 ps
CPU time 0.7 seconds
Started May 19 01:29:15 PM PDT 24
Finished May 19 01:29:17 PM PDT 24
Peak memory 183476 kb
Host smart-b1b384d7-ce44-49f4-896e-9e610cc48e66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243956028 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.3243956028
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_jump.3589731928
Short name T191
Test name
Test status
Simulation time 590391620 ps
CPU time 1.49 seconds
Started May 19 01:29:24 PM PDT 24
Finished May 19 01:29:28 PM PDT 24
Peak memory 183352 kb
Host smart-e11d250c-b1d2-495a-b139-0323fec755f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589731928 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.3589731928
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.3602559599
Short name T186
Test name
Test status
Simulation time 5036929192 ps
CPU time 4.76 seconds
Started May 19 01:29:16 PM PDT 24
Finished May 19 01:29:22 PM PDT 24
Peak memory 183564 kb
Host smart-7b56f8f9-c1ea-4ef7-bae4-4ad41f7ba3a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602559599 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.3602559599
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.3662232449
Short name T212
Test name
Test status
Simulation time 627409887 ps
CPU time 0.59 seconds
Started May 19 01:29:12 PM PDT 24
Finished May 19 01:29:14 PM PDT 24
Peak memory 183504 kb
Host smart-b12a03d3-01b2-466d-b04e-08f9caf87e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662232449 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.3662232449
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.1819007842
Short name T57
Test name
Test status
Simulation time 249521076808 ps
CPU time 328.42 seconds
Started May 19 01:29:12 PM PDT 24
Finished May 19 01:34:42 PM PDT 24
Peak memory 194220 kb
Host smart-453e2cff-ce2c-49a1-866d-1aca8272c801
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819007842 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_
all.1819007842
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.2635539239
Short name T34
Test name
Test status
Simulation time 107286663843 ps
CPU time 609.71 seconds
Started May 19 01:29:12 PM PDT 24
Finished May 19 01:39:23 PM PDT 24
Peak memory 199024 kb
Host smart-f55332f5-c835-4688-a209-6038a23feb1e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635539239 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.2635539239
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.aon_timer_jump.4110136551
Short name T181
Test name
Test status
Simulation time 566451208 ps
CPU time 1.05 seconds
Started May 19 01:29:12 PM PDT 24
Finished May 19 01:29:14 PM PDT 24
Peak memory 183352 kb
Host smart-1478436c-0131-4e17-8541-6be90301494c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110136551 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.4110136551
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.3867451375
Short name T194
Test name
Test status
Simulation time 53569406222 ps
CPU time 77.59 seconds
Started May 19 01:29:16 PM PDT 24
Finished May 19 01:30:36 PM PDT 24
Peak memory 191732 kb
Host smart-d6bec78e-f0f2-4ec1-84e8-d215036c70cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867451375 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.3867451375
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.2297402760
Short name T154
Test name
Test status
Simulation time 425620512 ps
CPU time 0.65 seconds
Started May 19 01:29:12 PM PDT 24
Finished May 19 01:29:15 PM PDT 24
Peak memory 183464 kb
Host smart-f3fed5aa-9302-4c2a-9f5c-75c4e7128ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297402760 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.2297402760
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.3967087725
Short name T210
Test name
Test status
Simulation time 282773433063 ps
CPU time 116.96 seconds
Started May 19 01:29:14 PM PDT 24
Finished May 19 01:31:12 PM PDT 24
Peak memory 195056 kb
Host smart-9d578c43-3839-44c1-bd25-db72aefb3694
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967087725 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_
all.3967087725
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.3380509454
Short name T157
Test name
Test status
Simulation time 60018135826 ps
CPU time 244.89 seconds
Started May 19 01:29:14 PM PDT 24
Finished May 19 01:33:20 PM PDT 24
Peak memory 198468 kb
Host smart-ecd45d67-900b-49f4-9b32-2713ad708f58
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380509454 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.3380509454
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.aon_timer_jump.2738022134
Short name T204
Test name
Test status
Simulation time 418039373 ps
CPU time 1.08 seconds
Started May 19 01:29:12 PM PDT 24
Finished May 19 01:29:14 PM PDT 24
Peak memory 183500 kb
Host smart-f30da7f8-6e4c-4e71-858c-305b707cb967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738022134 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.2738022134
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.3411429526
Short name T253
Test name
Test status
Simulation time 704517026 ps
CPU time 1.13 seconds
Started May 19 01:29:24 PM PDT 24
Finished May 19 01:29:27 PM PDT 24
Peak memory 183356 kb
Host smart-d635d4a8-e302-4851-ad92-630051829e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411429526 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.3411429526
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.1278510991
Short name T28
Test name
Test status
Simulation time 503043616 ps
CPU time 0.96 seconds
Started May 19 01:29:24 PM PDT 24
Finished May 19 01:29:27 PM PDT 24
Peak memory 183352 kb
Host smart-fa9effad-2775-445a-bafe-532cd16b512d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278510991 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.1278510991
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.2929463346
Short name T102
Test name
Test status
Simulation time 29121947090 ps
CPU time 220.67 seconds
Started May 19 01:29:15 PM PDT 24
Finished May 19 01:32:56 PM PDT 24
Peak memory 198436 kb
Host smart-4c4b49d5-48dd-4749-a233-a3ebd7282a71
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929463346 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.2929463346
Directory /workspace/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.aon_timer_jump.1739659578
Short name T141
Test name
Test status
Simulation time 463300309 ps
CPU time 0.84 seconds
Started May 19 01:29:24 PM PDT 24
Finished May 19 01:29:27 PM PDT 24
Peak memory 183352 kb
Host smart-70f07d1d-f8e8-4334-9423-c685acd7b2af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739659578 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.1739659578
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.690218825
Short name T24
Test name
Test status
Simulation time 40664011093 ps
CPU time 15.77 seconds
Started May 19 01:29:12 PM PDT 24
Finished May 19 01:29:29 PM PDT 24
Peak memory 183592 kb
Host smart-1704d46a-afa5-4100-abcf-b5d1a89893c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690218825 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.690218825
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.402947091
Short name T146
Test name
Test status
Simulation time 405565840 ps
CPU time 1.17 seconds
Started May 19 01:29:16 PM PDT 24
Finished May 19 01:29:19 PM PDT 24
Peak memory 183500 kb
Host smart-b3ae718d-0163-4a32-93d2-070dbb590e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402947091 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.402947091
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.2405864808
Short name T174
Test name
Test status
Simulation time 85294949491 ps
CPU time 67.19 seconds
Started May 19 01:29:15 PM PDT 24
Finished May 19 01:30:24 PM PDT 24
Peak memory 193988 kb
Host smart-7567541b-d661-4b29-8d6b-6c97ac44dbfb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405864808 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_
all.2405864808
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.1185876822
Short name T101
Test name
Test status
Simulation time 75341209769 ps
CPU time 814.09 seconds
Started May 19 01:29:14 PM PDT 24
Finished May 19 01:42:49 PM PDT 24
Peak memory 201260 kb
Host smart-1b3cfd50-d272-4503-a1e6-caa7bfe71e61
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185876822 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.1185876822
Directory /workspace/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_jump.2854525938
Short name T111
Test name
Test status
Simulation time 552976447 ps
CPU time 0.75 seconds
Started May 19 01:29:12 PM PDT 24
Finished May 19 01:29:14 PM PDT 24
Peak memory 183452 kb
Host smart-720d9590-ef4a-402f-944e-634fb5337fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854525938 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.2854525938
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.2916319645
Short name T59
Test name
Test status
Simulation time 9535121017 ps
CPU time 15.43 seconds
Started May 19 01:29:12 PM PDT 24
Finished May 19 01:29:29 PM PDT 24
Peak memory 183536 kb
Host smart-0304d561-edc7-4ebd-b04d-be74585e3d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916319645 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.2916319645
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.1004522085
Short name T158
Test name
Test status
Simulation time 390518512 ps
CPU time 1.11 seconds
Started May 19 01:29:24 PM PDT 24
Finished May 19 01:29:27 PM PDT 24
Peak memory 183360 kb
Host smart-52d8b896-8728-458b-8abe-ec361d894647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004522085 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.1004522085
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.451723450
Short name T119
Test name
Test status
Simulation time 228545902379 ps
CPU time 87.29 seconds
Started May 19 01:29:13 PM PDT 24
Finished May 19 01:30:42 PM PDT 24
Peak memory 194100 kb
Host smart-9adc8f82-d2f1-4e24-9034-040429767fa4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451723450 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_a
ll.451723450
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_jump.187923626
Short name T175
Test name
Test status
Simulation time 514509360 ps
CPU time 0.73 seconds
Started May 19 01:29:20 PM PDT 24
Finished May 19 01:29:23 PM PDT 24
Peak memory 183436 kb
Host smart-80a3c389-bb4f-41b2-b628-2ef54e60d80d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187923626 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.187923626
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.3821347963
Short name T198
Test name
Test status
Simulation time 41242427706 ps
CPU time 62.84 seconds
Started May 19 01:29:16 PM PDT 24
Finished May 19 01:30:21 PM PDT 24
Peak memory 183812 kb
Host smart-6c3d2bbd-0c43-4f96-9691-551028e80b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821347963 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.3821347963
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.2766387309
Short name T275
Test name
Test status
Simulation time 533429055 ps
CPU time 1.36 seconds
Started May 19 01:29:20 PM PDT 24
Finished May 19 01:29:23 PM PDT 24
Peak memory 183460 kb
Host smart-56605164-449e-4c71-8b58-09ece8bf67f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766387309 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.2766387309
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.4143561193
Short name T23
Test name
Test status
Simulation time 85652790107 ps
CPU time 29.62 seconds
Started May 19 01:29:18 PM PDT 24
Finished May 19 01:29:49 PM PDT 24
Peak memory 194872 kb
Host smart-f33c03fe-8a1f-4115-945a-bf0bf230dbfd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143561193 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_
all.4143561193
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.561980138
Short name T30
Test name
Test status
Simulation time 10173563685 ps
CPU time 101.88 seconds
Started May 19 01:29:16 PM PDT 24
Finished May 19 01:31:00 PM PDT 24
Peak memory 198448 kb
Host smart-5e59b56c-6993-4737-94a7-ddaf5acbf39b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561980138 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.561980138
Directory /workspace/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.aon_timer_jump.2757480559
Short name T225
Test name
Test status
Simulation time 558939125 ps
CPU time 1.45 seconds
Started May 19 01:28:49 PM PDT 24
Finished May 19 01:28:55 PM PDT 24
Peak memory 183504 kb
Host smart-0ae56360-ec89-42ff-9c8d-c27880070343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757480559 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.2757480559
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.805621076
Short name T50
Test name
Test status
Simulation time 30001669037 ps
CPU time 23.02 seconds
Started May 19 01:28:49 PM PDT 24
Finished May 19 01:29:16 PM PDT 24
Peak memory 191720 kb
Host smart-89e58d92-ca82-45a9-9dd1-95f20f181c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805621076 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.805621076
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.1203405144
Short name T36
Test name
Test status
Simulation time 429882026 ps
CPU time 0.88 seconds
Started May 19 01:28:46 PM PDT 24
Finished May 19 01:28:51 PM PDT 24
Peak memory 183504 kb
Host smart-266356b0-f4e1-4db3-8085-0a909fbfa1e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203405144 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.1203405144
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.1018943727
Short name T150
Test name
Test status
Simulation time 110201926768 ps
CPU time 42.17 seconds
Started May 19 01:28:47 PM PDT 24
Finished May 19 01:29:33 PM PDT 24
Peak memory 183536 kb
Host smart-5f40943e-6070-4c0b-ac8e-411a94d7d658
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018943727 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_a
ll.1018943727
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_jump.3193424571
Short name T184
Test name
Test status
Simulation time 515454958 ps
CPU time 1.01 seconds
Started May 19 01:28:51 PM PDT 24
Finished May 19 01:28:57 PM PDT 24
Peak memory 183496 kb
Host smart-9309d4ef-cd26-42c0-b1a8-b8982d1c74c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193424571 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.3193424571
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.2463555322
Short name T172
Test name
Test status
Simulation time 47608036323 ps
CPU time 15.86 seconds
Started May 19 01:28:51 PM PDT 24
Finished May 19 01:29:11 PM PDT 24
Peak memory 183556 kb
Host smart-fd34b452-bc05-445c-be2e-6deddff44307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463555322 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.2463555322
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.2440631674
Short name T235
Test name
Test status
Simulation time 438344323 ps
CPU time 1.17 seconds
Started May 19 01:28:47 PM PDT 24
Finished May 19 01:28:52 PM PDT 24
Peak memory 183476 kb
Host smart-1c770bed-1d2f-48f4-91cf-7cfe58dbedd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440631674 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.2440631674
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.4071487604
Short name T266
Test name
Test status
Simulation time 102339165019 ps
CPU time 154.1 seconds
Started May 19 01:28:50 PM PDT 24
Finished May 19 01:31:29 PM PDT 24
Peak memory 193904 kb
Host smart-68f587cd-0792-4238-a50a-557f839da919
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071487604 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_a
ll.4071487604
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.589653652
Short name T58
Test name
Test status
Simulation time 50619803331 ps
CPU time 262.25 seconds
Started May 19 01:28:46 PM PDT 24
Finished May 19 01:33:12 PM PDT 24
Peak memory 198420 kb
Host smart-e123f877-2d73-4f79-8811-267401717b04
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589653652 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.589653652
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.aon_timer_jump.4240561772
Short name T168
Test name
Test status
Simulation time 593730891 ps
CPU time 1.52 seconds
Started May 19 01:28:49 PM PDT 24
Finished May 19 01:28:55 PM PDT 24
Peak memory 183432 kb
Host smart-f1d3922b-f783-4b38-b45c-966dfea39a77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240561772 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.4240561772
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.1910856515
Short name T117
Test name
Test status
Simulation time 11245602344 ps
CPU time 8.77 seconds
Started May 19 01:28:52 PM PDT 24
Finished May 19 01:29:06 PM PDT 24
Peak memory 183552 kb
Host smart-58fcc822-6599-456d-85e6-ff08fb61ee58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910856515 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.1910856515
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.1287879594
Short name T249
Test name
Test status
Simulation time 483778814 ps
CPU time 0.9 seconds
Started May 19 01:28:51 PM PDT 24
Finished May 19 01:28:56 PM PDT 24
Peak memory 183480 kb
Host smart-3377eb63-22ba-4fb3-aa43-20bf42b64657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287879594 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.1287879594
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.1646589118
Short name T173
Test name
Test status
Simulation time 71835342727 ps
CPU time 17.12 seconds
Started May 19 01:28:49 PM PDT 24
Finished May 19 01:29:11 PM PDT 24
Peak memory 194636 kb
Host smart-9e4c90f0-13a9-4d3d-b703-d52677cede3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646589118 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_a
ll.1646589118
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.436125812
Short name T262
Test name
Test status
Simulation time 58791629385 ps
CPU time 471.86 seconds
Started May 19 01:28:49 PM PDT 24
Finished May 19 01:36:46 PM PDT 24
Peak memory 198444 kb
Host smart-35baaa73-3c03-4fbb-8340-9eebfad5f0bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436125812 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.436125812
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.aon_timer_jump.3251580436
Short name T82
Test name
Test status
Simulation time 471932041 ps
CPU time 0.68 seconds
Started May 19 01:28:53 PM PDT 24
Finished May 19 01:29:00 PM PDT 24
Peak memory 183460 kb
Host smart-4f697519-86aa-4e4b-b3a9-6012f54ba91c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251580436 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.3251580436
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.117770163
Short name T264
Test name
Test status
Simulation time 23586989290 ps
CPU time 10.53 seconds
Started May 19 01:28:49 PM PDT 24
Finished May 19 01:29:04 PM PDT 24
Peak memory 191692 kb
Host smart-c79277ad-9e10-4774-8128-a17362410864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117770163 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.117770163
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.516912305
Short name T213
Test name
Test status
Simulation time 554368818 ps
CPU time 1.27 seconds
Started May 19 01:28:55 PM PDT 24
Finished May 19 01:29:03 PM PDT 24
Peak memory 183448 kb
Host smart-0125f0f5-625f-4790-8688-d3f2e234ed98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516912305 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.516912305
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.2484392584
Short name T115
Test name
Test status
Simulation time 115491200998 ps
CPU time 192.4 seconds
Started May 19 01:28:53 PM PDT 24
Finished May 19 01:32:11 PM PDT 24
Peak memory 183492 kb
Host smart-8bf7c6cd-94ed-4d94-ab48-1590aae4e638
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484392584 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_a
ll.2484392584
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.2780742294
Short name T223
Test name
Test status
Simulation time 71264449483 ps
CPU time 576.74 seconds
Started May 19 01:28:51 PM PDT 24
Finished May 19 01:38:32 PM PDT 24
Peak memory 198516 kb
Host smart-38428f82-7ac3-46b9-8ef1-8009b24415b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780742294 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.2780742294
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.aon_timer_jump.776041254
Short name T133
Test name
Test status
Simulation time 377605887 ps
CPU time 0.67 seconds
Started May 19 01:28:49 PM PDT 24
Finished May 19 01:28:54 PM PDT 24
Peak memory 183504 kb
Host smart-905aee58-6163-4345-aa37-9b51b6ef0b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776041254 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.776041254
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.1269933783
Short name T192
Test name
Test status
Simulation time 18706999366 ps
CPU time 28.33 seconds
Started May 19 01:28:49 PM PDT 24
Finished May 19 01:29:22 PM PDT 24
Peak memory 183256 kb
Host smart-c9075053-0e04-4ca0-b5ea-9b70b72b45ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269933783 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.1269933783
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.3456346977
Short name T254
Test name
Test status
Simulation time 482551004 ps
CPU time 0.66 seconds
Started May 19 01:28:52 PM PDT 24
Finished May 19 01:28:58 PM PDT 24
Peak memory 183420 kb
Host smart-9cf7a882-318d-493b-b96a-a149cfff6524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456346977 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.3456346977
Directory /workspace/9.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.2636145268
Short name T123
Test name
Test status
Simulation time 95409192893 ps
CPU time 145.44 seconds
Started May 19 01:28:56 PM PDT 24
Finished May 19 01:31:28 PM PDT 24
Peak memory 193640 kb
Host smart-813b49ce-54df-4e91-88dd-cc1eeb4f57a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636145268 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_a
ll.2636145268
Directory /workspace/9.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.1023267766
Short name T107
Test name
Test status
Simulation time 127123163120 ps
CPU time 252.46 seconds
Started May 19 01:28:55 PM PDT 24
Finished May 19 01:33:14 PM PDT 24
Peak memory 198464 kb
Host smart-3da40898-f9a8-43a0-a8f6-7a30438f92f5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023267766 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.1023267766
Directory /workspace/9.aon_timer_stress_all_with_rand_reset/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%